LH79525N0Q100A1,557_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF52235

Rev. 10, 3/2011

MCF52235

LQFP-80

LQFP-112

14mm x 14mm

20mm_x_20mm

MCF52235 ColdFire

Microcontroller Data Sheet

MAPBGA-121

12mm_x_12mm

Supports MCF52230, MCF52231,

MCF52232, MCF52233, MCF52234,

MCF52235, and MCF52236

®

The MCF52235 is a member of the ColdFire family of

• Two 16-bit periodic interrupt timers (PITs)

• Real-time clock (RTC) module

• Programmable software watchdog timer

• Two interrupt controllers providing every peripheral with a

unique selectable-priority interrupt vector plus seven

external interrupts with fixed levels/priorities

• Clock module with support for crystal or external oscillator

and integrated phase-locked loop (PLL)

reduced instruction set computing (RISC) microcontrollers.

This document provides an overview of the MCF52235

microcontroller family, focusing on its highly integrated and

diverse feature set.

This 32-bit device is based on the Version 2 ColdFire core

operating at a frequency up to 60 MHz, offering high

performance and low power consumption. On-chip memories

connected tightly to the processor core include up to 256

Kbytes of Flash and 32 Kbytes of static random access

memory (SRAM). On-chip modules include:

• V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60

MHz executing out of on-chip Flash memory using

enhanced multiply accumulate (EMAC) and hardware

divider

• Test access/debug port (JTAG, BDM)

• Enhanced Multiply Accumulate Unit (EMAC) and

hardware divide module

• Cryptographic Acceleration Unit (CAU) coprocessor

• Fast Ethernet Controller (FEC)

• On-chip Ethernet Transceiver (EPHY)

• FlexCAN controller area network (CAN) module

• Three universal asynchronous/synchronous

receiver/transmitters (UARTs)

• Inter-integrated circuit (I²C™) bus controller

• Queued serial peripheral interface (QSPI) module

• Eight-channel 10- or 12-bit fast analog-to-digital converter

(ADC)

• Four channel direct memory access (DMA) controller

• Four 32-bit input capture/output compare timers with

DMA support (DTIM)

• Four-channel general-purpose timer (GPT) capable of

input capture/output compare, pulse width modulation

(PWM) and pulse accumulation

• Eight/Four-channel 8/16-bit pulse width modulation timers

(two adjacent 8-bit PWMs can be concatenated to form a

single 16-bit timer)

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

Table of Contents

1

MCF52235 Family Configurations . . . . . . . . . . . . . . . . . . . . . .3

Figure 14.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 15.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . 45

Figure 16.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . 45

Figure 17.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18.Real-Time Trace AC Timing. . . . . . . . . . . . . . . . . . . . 46

Figure 19.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 46

1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .22

1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .23

1.8 Fast Ethernet Controller EPHY Signals . . . . . . . . . . . .23

1.9 I²C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.10 UART Module Signals. . . . . . . . . . . . . . . . . . . . . . . . . .24

1.11 DMA Timer Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .25

1.14 Pulse Width Modulator Signals. . . . . . . . . . . . . . . . . . .25

1.15 Debug Support Signals. . . . . . . . . . . . . . . . . . . . . . . . .25

1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .27

1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .27

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

2.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .32

2.4 Phase Lock Loop Electrical Specifications . . . . . . . . . .33

2.5 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .35

2.6 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

2.7 I²C Input/Output Timing Specifications. . . . . . . . . . . . .36

2.8 EPHY Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

2.9 Analog-to-Digital Converter (ADC) Parameters . . . . . .40

2.10 DMA Timers Timing Specifications. . . . . . . . . . . . . . . .42

2.11 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .42

2.12 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .43

2.13 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . .44

2.14 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .46

Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .47

3.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .47

3.2 112-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .48

3.3 121 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . .51

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

List of Tables

Table 1. MCF52235 Family Configurations . . . . . . . . . . . . . . . . . 3

Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 13

Table 3. Pin Functions by Primary and Alternate Purpose . . . . 17

Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Mode Selection Signals. . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Queued Serial Peripheral Interface (QSPI) Signals. . . 23

Table 9. Fast Ethernet Controller (FEC) Signals . . . . . . . . . . . . 23

Table 10.I²C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15.PWM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 27

Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19.Absolute Maximum Ratings, . . . . . . . . . . . . . . . . . . . 29

Table 20.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21.ESD Protection Characteristics . . . . . . . . . . . . . . . . . . 31

Table 22.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32

Table 23.Active Current Consumption Specifications. . . . . . . . . 33

Table 24.Current Consumption Specifications in

2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 33

Table 26.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 27.Reset and Configuration Override Timing . . . . . . . . . . 35

Table 28.I²C Input Timing Specifications between

3

4

I2C_SCL and I2C_SDA . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 29. I²C Output Timing Specifications between

List of Figures

I2C_SCL and I2C_SDA . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 1.MCF52235 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2.80-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . . 14

Figure 3.112-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . 15

Figure 4.121 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . 16

Figure 5.Suggested Connection Scheme for Power and Ground 28

Figure 6.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7.RSTI and Configuration Override Timing . . . . . . . . . . 36

Figure 8.I²C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 37

Figure 9.EPHY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 10.10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . 39

Figure 11.10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . 39

Figure 12.Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . 42

Figure 13.QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 30.EPHY Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 38

Table 31.10BASE-T SQE (Heartbeat) Timing Parameters . . . . 38

Table 32.10BASE-T Jab and Unjab Timing Parameters . . . . . . 39

Table 33.10BASE-T Transceiver Characteristics . . . . . . . . . . . . 40

Table 34.100BASE-TX Transceiver Characteristics . . . . . . . . . . 40

Table 35.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 36.Timer Module AC Timing Specifications . . . . . . . . . . . 42

Table 37.EzPort Electrical Specifications. . . . . . . . . . . . . . . . . . 42

Table 38.QSPI Modules AC Timing Specifications. . . . . . . . . . . 43

Table 39.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 44

Table 40.Debug AC Timing Specification. . . . . . . . . . . . . . . . . . 46

Table 41.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

2

Freescale Semiconductor

MCF52235 Family Configurations

1 MCF52235 Family Configurations

Table 1. MCF52235 Family Configurations

Module

52230

52231

52232

52233

52234

52235

52236

Version 2 ColdFire Core with EMAC

(Enhanced Multiply-Accumulate Unit)



System Clock (MHz)

60

56

60

56

50

46

60

56

60

56

60

56

50

46

Performance (Dhrystone 2.1 MIPS)

Flash / Static RAM (SRAM)

128/32

Kbytes

128/32

Kbytes

128/32

Kbytes

256/32

Kbytes

256/32

Kbytes

256/32

Kbytes

256/32

Kbytes

Interrupt Controllers (INTC0/INTC1)

Fast Analog-to-Digital Converter (ADC)



Random Number Generator and Crypto

Acceleration Unit (CAU)

—

FlexCAN 2.0B Module

—



—



—

Fast Ethernet Controller (FEC) with on-chip

interface (EPHY)



Four-channel Direct-Memory Access (DMA)

Software Watchdog Timer (WDT)

Programmable Interrupt Timer

Four-Channel General Purpose Timer

32-bit DMA Timers



2



4



3



2



4



3



2



4



3



2



4



3



2



4



3



2



4



3



2



4



3



QSPI

UART(s)

I²C

Eight/Four-channel 8/16-bit PWM Timer

General Purpose I/O Module (GPIO)

Chip Configuration and Reset Controller

Module

Background Debug Mode (BDM)

JTAG - IEEE 1149.1 Test Access Port¹

Package



80 LQFP 80 LQFP 80 LQFP 80 LQFP 112 LQFP 112 LQFP 80 LQFP

112 LQFP 112 LQFP 112 LQFP 121 121

MAPBGA MAPBGA

1

The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug interface is bonded on the

80-pin package.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

3

MCF52235 Family Configurations

1.1

Block Diagram

The MCF52235 (or its variants) comes in 80- and 112-pin low-profile quad flat pack packages (LQFP) and a 121 MAPBGA,

and operates in single-chip mode only. Figure 1 shows a top-level block diagram of the MCF52235.

EzPD

EzPQ

EzPCK

EzPCS

EPHY_TX

EPHY_RX

EzPort

Arbiter

GPTn

QSPI_DIN,

QSPI_DOUT

Interrupt

Controller 1

Interrupt

Controller 2

EPHY

QSPI_CLK,

QSPI_CSn

SDA

Fast

SCL

Ethernet

Controller

(FEC)

UTXDn

URXDn

URTSn

UCTSn

DTINn/DTOUTn

CANRX

CANTX

PWMn

UART

0

UART

1

UART

2

I²C

QSPI

RTC

4 CH DMA

DTIM

0

DTIM

1

DTIM

2

DTIM

3

To/From PADI

MUX

JTAG_EN

V2 ColdFire CPU

CAU

IFP OEP

EMAC

PMM

CIM

JTAG

TAP

32 Kbytes

SRAM

256 Kbytes

Flash

(32K16)4

RSTIN

PORTS

(GPIO)

AN[7:0]

ADC

RSTOUT

(4K16)4

V_RHV_RL

PLL

CLKGEN

Edge

Port 1

PWM

PIT1

FlexCAN

Edge

Port 2

EXTAL XTAL CLKOUT

GPT

PIT0

RNGA

To/From Interrupt Controller

Figure 1. MCF52235 Block Diagram

1.2

Features

This document contains information on a new product under development. Freescale reserves the right to change or discontinue

this product without notice. Specifications and information herein are subject to change without notice.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

4

Freescale Semiconductor

MCF52235 Family Configurations

1.2.1 Feature Overview

The MCF52235 family includes the following features:

•

Version 2 ColdFire variable-length RISC processor core

— Static operation

— 32-bit address and data paths on-chip

— Up to 60 MHz processor core frequency

— Sixteen general-purpose, 32-bit data and address registers

— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions

for improved bit processing (ISA_A+)

— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support 16  16  32 or 32  32  32

operations

— Cryptography Acceleration Unit (CAU)

–

Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions

FIPS-140 compliant random number generator

— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms

— Illegal instruction decode that allows for 68K emulation support

System debug support

•

— Real time trace for determining dynamic execution path

— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)

— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into

a 1- or 2-level trigger

•

On-chip memories

— Up to 32 Kbytes of dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power

supply support

— Up to 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses

Power management

— Fully static operation with processor sleep and whole chip stop modes

— Rapid response to interrupts from the low-power sleep mode (wake-up feature)

— Clock enable/disable for each peripheral when not used

Fast Ethernet Controller (FEC)

•

— 10/100 BaseT/TX capability, half duplex or full duplex

— On-chip transmit and receive FIFOs

— Built-in dedicated DMA controller

— Memory-based flexible descriptor rings

On-chip Ethernet Transceiver (EPHY)

— Digital adaptive equalization

— Supports auto-negotiation

— Baseline wander correction

— Full-/Half-duplex support in all modes

— Loopback modes

— Supports MDIO preamble suppression

— Jumbo packet

•

FlexCAN 2.0B module

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

5

MCF52235 Family Configurations

— Based on and includes all existing features of the Freescale TouCAN module

— Full implementation of the CAN protocol specification version 2.0B

–

Standard Data and Remote Frames (up to 109 bits long)

Extended Data and Remote Frames (up to 127 bits long)

0–8 bytes data length

Programmable bit rate up to 1 Mbit/sec

— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as

Rx or Tx, all supporting standard and extended messages

— Unused Message Buffer space can be used as general purpose RAM space

— Listen only mode capability

— Content-related addressing

— No read/write semaphores required

— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15

— Programmable transmit-first scheme: lowest ID or lowest buffer number

— Time stamp based on 16-bit free-running timer

— Global network time, synchronized by a specific message

— Maskable interrupts

•

Three universal asynchronous/synchronous receiver transmitters (UARTs)

— 16-bit divider for clock generation

— Interrupt control logic with maskable interrupts

— DMA support

— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity

— Up to 2 stop bits in 1/16 increments

— Error-detection capabilities

— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs

— Transmit and receive FIFO buffers

•

I²C module

— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

— Fully compatible with industry-standard I²C bus

— Master and slave modes support multiple masters

— Automatic interrupt generation with programmable level

Queued serial peripheral interface (QSPI)

— Full-duplex, three-wire synchronous transfers

— Up to four chip selects available

— Master mode operation only

— Programmable bit rates up to half the CPU clock frequency

— Up to 16 pre-programmed transfers

•

Fast analog-to-digital converter (ADC)

— Eight analog input channels

— 12-bit resolution

— Minimum 1.125 s conversion time

— Simultaneous sampling of two channels for motor control applications

— Single-scan or continuous operation

— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit

— Unused analog channels can be used as digital I/O

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

6

Freescale Semiconductor

MCF52235 Family Configurations

•

Four 32-bit DMA timers

— 17-ns resolution at 60 MHz

— Programmable sources for clock input, including an external clock option

— Programmable prescaler

— Input capture capability with programmable trigger edge on input pin

— Output compare with programmable mode for the output pin

— Free run and restart modes

— Maskable interrupts on input capture or output compare

— DMA trigger capability on input capture or output compare

Four-channel general purpose timers

•

— 16-bit architecture

— Programmable prescaler

— Output pulse widths variable from microseconds to seconds

— Single 16-bit input pulse accumulator

— Toggle-on-overflow feature for pulse-width modulator (PWM) generation

— One dual-mode pulse accumulation channel

Pulse-width modulation timer

— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution

— Programmable period and duty cycle

— Programmable enable/disable for each channel

— Software selectable polarity for each channel

— Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached

(PWM counter reaches zero) or when the channel is disabled.

— Programmable center or left aligned outputs on individual channels

— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies

— Emergency shutdown

•

Real-Time Clock (RTC)

— Maintains system time-of-day clock

— Provides stopwatch and alarm interrupt functions

•

Two periodic interrupt timers (PITs)

— 16-bit counter

— Selectable as free running or count down

Software watchdog timer

— 32-bit counter

— Low power mode support

Clock Generation Features

— Crystal input

— On-chip PLL

— Provides clock for integrated EPHY

Dual Interrupt Controllers (INTC0/INTC1)

— Support for multiple interrupt sources organized as follows:

•

–

Fully-programmable interrupt sources for each peripheral

7 fixed-level interrupt sources

Seven external interrupt signals

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

7

MCF52235 Family Configurations

— Unique vector number for each interrupt source

— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

— Support for hardware and software interrupt acknowledge (IACK) cycles

— Combinatorial path to provide wake-up from low power modes

DMA controller

•

— Four fully programmable channels

— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4 x 32-bit)

burst transfers

— Source/destination address pointers that can increment or remain constant

— 24-bit byte transfer counter per channel

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle steal support

— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)

Reset

•

— Separate reset in and reset out signals

— Seven sources of reset:

–

Power-on reset (POR)

External

Software

Watchdog

Loss of clock

Loss of lock

Low-voltage detection (LVD)

— Status flag indication of source of last reset

Chip integration module (CIM)

•

— System configuration during reset

— Selects one of three clock modes

— Configures output pad drive strength

— Unique part identification number and part revision number

General purpose I/O interface

— Up to 56 bits of general purpose I/O

— Bit manipulation supported via set/clear functions

— Programmable drive strengths

— Unused peripheral pins may be used as extra GPIO

JTAG support for system level board testing

•

1.2.2

V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage

instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is

a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).

The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage

(AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack

pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235 core includes the enhanced

multiply-accumulate (EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

8

Freescale Semiconductor

MCF52235 Family Configurations

pipeline, optimized for 1616 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and

32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types.

The EMAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware

cost.

1.2.3

Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and

emulator development tools. Through a standard debug interface, access debug information and real-time tracing capability is

provided on 112-and 121-lead packages. This allows the processor and system to be debugged at full speed without the need

for costly in-circuit emulators.

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,

a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the

dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint

registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or

dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.

The MCF52235 implements revision B+ of the ColdFire Debug Architecture.

The MCF52235’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be

serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging.

To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.

These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining

processor activity at the CPU’s clock rate. The MCF52235 includes a new debug signal, ALLPST. This signal is the logical

AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] =

1111).

The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product features the dedicated

debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.2.4

JTAG

The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action

Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and

three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register

links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device

system logic.

The MCF52235 implementation can do the following:

•

Perform boundary-scan operations to test circuit board electrical continuity

Sample MCF52235 system pins during operation and transparently shift out the result in the boundary scan register

Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan register to a single bit

Disable the output drive to pins during circuit-board testing

Drive output pins to stable levels

1.2.5

On-Chip Memories

1.2.5.1

SRAM

The dual-ported SRAM module provides a general-purpose 16- or 32-Kbyte memory block that the ColdFire core can access

in a single cycle. The location of the memory block can be set to any 16- or 32-Kbyte boundary within the 4-Gbyte address

space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

9

MCF52235 Family Configurations

module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or

memory-referencing commands from the debug module.

The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing

applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to

maximize system performance.

1.2.5.2

Flash

The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local

bus. The CFM is constructed with four banks of 32 K16-bit flash arrays to generate 256 Kbytes of 32-bit flash memory. These

arrays serve as electrically erasable and programmable, non-volatile program and data memory. The flash memory is ideal for

program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high

voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller which supports

interleaved accesses from the 2-cycle flash arrays. A backdoor mapping of the flash memory is used for all program, erase, and

verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort,

which is a serial flash programming interface that allows the flash to be read, erased and programmed by an external controller

in a format compatible with most SPI bus flash memory chips. This allows easy device programming via Automated Test

Equipment or bulk programming tools.

1.2.6

Cryptography Acceleration Unit

The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor

tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of

software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms.

Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules

supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.

1.2.7

Power Management

The MCF52235 incorporates several low-power modes of operation which are entered under program control and exited by

several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset

as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or

interrupt condition if it falls below the LVD trip point.

1.2.8

FlexCAN

The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN

protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh

EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers.

1.2.9

UARTs

The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus

clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital

I/O functions.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

10

Freescale Semiconductor

MCF52235 Family Configurations

1.2.10 I²C Bus

The I²C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the

interconnection between devices. This bus is suitable for applications requiring occasional communications over a short

distance between many devices on a circuit board.

1.2.11 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability.

It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.

1.2.12 Fast ADC

The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding

separate 10- or 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform a programmed

scan sequence repeatedly until manually stopped.

The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight

channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a

scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This

configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low

threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.

1.2.13 DMA Timers (DTIM0–DTIM3)

There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the each device.

Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured

to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected,

it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual

timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode.

Timer events may optionally cause interrupt requests or DMA transfers.

1.2.14 General Purpose Timer (GPT)

The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter driven by a 7-stage

programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, one of

the channels, channel 3, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.

The input capture and output compare functions allow simultaneous input waveform measurements and output waveform

generation. The input capture function can capture the time of a selected transition edge. The output compare function can

generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a

gated time accumulator.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

11

MCF52235 Family Configurations

1.2.15 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal

processor intervention. Each timer can count down from the value written in its PIT modulus register or can be a free-running

down-counter.

1.2.16 Pulse Width Modulation (PWM) Timers

The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a

dedicated counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates

from 0 to 100%. The PWM outputs have programmable polarity and can be programmed as left-aligned outputs or

center-aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0])

can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or

0/4 8-/16-bit channels.

1.2.17 Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running

down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.

1.2.18 Phase Locked Loop (PLL)

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced

frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL,

crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are

powered by the normal supply pins, VDD and VSS.

1.2.19 Interrupt Controller (INTC0/INTC1)

There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven levels with up to nine

interrupt sources per level. Each interrupt source has a unique interrupt vector, and provide each peripheral with all necessary

interrupts. Each internal interrupt has a programmable level [1-7] and priority within the level. The seven external interrupts

have fixed levels/priorities.

1.2.20 DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor

intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered

by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.

1.2.21 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what

caused the last reset. There are seven sources of reset:

•

External reset input

Power-on reset (POR)

Watchdog timer

Phase locked-loop (PLL) loss of lock

PLL loss of clock

Software

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

12

Freescale Semiconductor

MCF52235 Family Configurations

•

Low-voltage detector (LVD)

Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags

indicating the last source of reset and a control bit for software assertion of the RSTO pin.

1.2.22 GPIO

Nearly all pins on the MCF52235 have general purpose I/O capability in addition to their primary functions and are grouped

into 8-bit ports. Some ports do not utilize all 8 bits. Each port has registers that configure, monitor, and control the port pins.

1.2.23 Part Numbers and Packaging

Table 2. Orderable Part Number Summary

Freescale Part

Number

Speed Flash/SRAM

Temp range

Description

Package

(MHz)

(Kbytes)

(C)

MCF52230CAF60

MCF52230CAL60

MCF52231CAF60

MCF52231CAL60

MCF52232CAF50

MCF52232AF50

MCF52230 Microcontroller

60

50

60

50

128 / 32

256 / 32

80 LQFP

112 LQFP

80 LQFP

112 LQFP

80 LQFP

112 LQFP

-40 to +85

0 to +70

MCF52231 Microcontroller, FlexCAN

MCF52232 Microcontroller

MCF52233CAF60

MCF52233CAL60

MCF52233CAL60A

MCF52233CVM60

MCF52234CAL60

MCF52234CVM60

MCF52233 Microcontroller

-40 to +85

MCF52233 Microcontroller

121 MAPBGA -40 to +85

112 LQFP -40 to +85

121 MAPBGA -40 to +85

MCF52234 Microcontroller, FlexCAN

MCF52235CAL60 MCF52235 Microcontroller, FlexCAN, CAU, RNGA

MCF52235CAL60A MCF52235 Microcontroller, FlexCAN, CAU, RNGA

MCF52235CVM60 MCF52235 Microcontroller, FlexCAN, CAU, RNGA

112 LQFP

-40 to +85

121 MAPBGA -40 to +85

MCF52236CAF50

MCF52236AF50

MCF52236AF50A

MCF52236 Microcontroller

80 LQFP

-40 to +85

0 to +70

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

13

MCF52235 Family Configurations

1.2.24 Package Pinouts

Figure 2 shows the pinout configuration for the 80-pin LQFP.

TCLK/PSTCLK

TMS/BKPT

RCON/EZPCS

TDI/DSI

TDO/DSO

TRST/DSCLK

ALLPST

DTIN0/DTOUT0

DTIN1/DTOUT1

VDDX1

ACTLED

LNKLED

VDDR

SPDLED

1

2

3

4

5

6

7

8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

PHY_VSSRX

PHY_VDDRX

PHY_RXN

PHY_RXP

PHY_VSSTX

PHY_TXN

PHY_TXP

PHY_VDDTX

PHY_VDDA

PHY_VSSA

PHY_RBIAS

VDD2

9

10

11

12

13

14

15

16

17

18

19

20

80-pin

LQFP

VSSX1

JTAG_EN

DTIN2/DTOUT2

DTIN3/DTOUT3

URTS1

UCTS1

URTS0

UCTS0

SYNCB

VSS2

DUPLED

COLLED

IRQ11

SYNCA

Figure 2. 80-pin LQFP Pin Assignments

Figure 3 shows the pinout configuration for the 112-pin LQFP.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

14

Freescale Semiconductor

MCF52235 Family Configurations

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

1

2

3

4

5

6

7

8

ACTLED

LNKLED

VDDR

SPDLED

PST3

PST2

PST1

TCLK/PSTCLK

TMS/BKPT

RCON/EZPCS

TDI/DSI

TDO/DSO

TRST/DSCLK

ALLPST

DTIN0/DTOUT0

DTIN1/DTOUT1

IRQ8

PST0

9

PHY_VSSRX

PHY_VDDRX

PHY_RXN

PHY_RXP

PHY_VSSTX

PHY_TXN

PHY_TXP

PHY_VDDTX

PHY_VDDA

PHY_VSSA

PHY_RBIAS

VDD2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

IRQ9

DDATA3

DDATA2

VDDX1

VSSX1

DDATA1

DDATA0

JTAG_EN

IRQ6

112-pin LQFP

IRQ5

VSS2

UTXD2

URXD2

UCTS2

DTIN2/DTOUT2

DTIN3/DTOUT3

URTS1

UCTS1

URTS0

UCTS0

SYNCB

URTS2

DUPLED

COLLED

IRQ11

SYNCA

Figure 3. 112-pin LQFP Pin Assignments

Figure 4 shows the pinout configuration for the 121 MAPBGA.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

15

MCF52235 Family Configurations

1.3

Reset Signals

Table 4 describes signals that are used to either reset the chip or as a reset indication.

Table 4. Reset Signals

Signal Name

Abbreviation

Function

I/O

Reset In

RSTI

Primary reset input to the device. Asserting RSTI immediately resets

the CPU and peripherals.

I

Reset Out

RSTO

Driven low for 512 CPU clocks after the reset source has deasserted.

O

1.4

PLL and Clock Signals

Table 5 describes signals that are used to support the on-chip clock generation circuitry.

Table 5. PLL and Clock Signals

Signal Name

Abbreviation

Function

I/O

External Clock In

Crystal

EXTAL

XTAL

Crystal oscillator or external clock input.

Crystal oscillator output.

I

O

Clock Out

CLKOUT

This output signal reflects the internal system clock.

1.5

Mode Selection

Table 6 describes signals used in mode selection, Table 6 describes particular clocking modes.

Table 6. Mode Selection Signals

Signal Name

Abbreviation

Function

I/O

Reset Configuration

RCON

The Serial Flash Programming mode is entered by asserting the

RCON pin (with the TEST pin negated) as the chip comes out of

reset. During this mode, the EzPort has access to the Flash memory

which can be programmed from an external device.

—

Test

TEST

Reserved for factory testing only and in normal modes of operation

should be connected to VSS to prevent unintentional activation of

test functions.

I

1.6

External Interrupt Signals

Table 7 describes the external interrupt signals.

Table 7. External Interrupt Signals

Signal Name

Abbreviation

Function

I/O

External Interrupts

IRQ[15:1] External interrupt sources.

I

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

22

Freescale Semiconductor

MCF52235 Family Configurations

1.7

Queued Serial Peripheral Interface (QSPI)

Table 8 describes QSPI signals.

Table 8. Queued Serial Peripheral Interface (QSPI) Signals

Signal Name

Abbreviation

Function

I/O

QSPI Synchronous

Serial Output

QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be

driven on the rising or falling edge of QSPI_CLK.

O

QSPI Synchronous

Serial Data Input

QSPI_DIN Provides the serial data to the QSPI and can be programmed to be

sampled on the rising or falling edge of QSPI_CLK.

I

QSPI Serial Clock

QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of

QSPI_CLK are programmable.

O

SynchronousPeripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active

Chip Selects high or low.

1.8

Fast Ethernet Controller EPHY Signals

Table 9 describes the Fast Ethernet Controller (FEC) signals.

Table 9. Fast Ethernet Controller (FEC) Signals

Signal Name

Abbreviation

Function

I/O

Twisted Pair Input +

RXP

Differential Ethernet twisted-pair input pin. This pin is high-impedance

out of reset.

I

Twisted Pair Input -

Twisted Pair Output +

Twisted Pair Output -

Bias Control Resistor

RXN

TXN

Differential Ethernet twisted-pair input pin. This pin is high-impedance

out of reset.

I

Differential Ethernet twisted-pair output pin. This pin is

high-impedance out of reset.

O

I

TXP

Differential Ethernet twisted-pair output pin. This pin is

high-impedance out of reset.

RBIAS

Connect a 12.4 k(1.0%) external resistor, RBIAS, between the

PHY_RBIAS pin and analog ground.

Place this resistor as near to the chip pin as possible. Stray

capacitance must be kept to less than 10 pF

(>50 pF causes instability). No high-speed signals can be permitted in

the region of RBIAS.

Activity LED

Link LED

ACT_LED

Indicates when the EPHY is transmitting or receiving

O

LINK_LED Indicates when the EPHY has a valid link

SPD_LED Indicates the speed of the EPHY connection

Speed LED

Duplex LED

Collision LED

Transmit LED

Receive LED

DUPLED

COLLED

TXLED

Indicates the duplex (full or half) of the EPHY connection

Indicates if the EPHY detects a collision

Indicates if the EPHY is transmitting

RXLED

Indicates if the EPHY is receiving

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

23

MCF52235 Family Configurations

2

1.9

I C I/O Signals

2

Table 10 describes the I C serial interface module signals.

2

Table 10. I C I/O Signals

Signal Name

Abbreviation

Function

I/O

Serial Clock

SCL

Open-drain clock signal for the for the I²C interface. Either it is driven

by the I²C module when the bus is in master mode or it becomes the

clock input when the I²C is in slave mode.

I/O

Serial Data

SDA

Open-drain signal that serves as the data input/output for the I²C

interface.

I/O

1.10 UART Module Signals

Table 11 describes the UART module signals.

Table 11. UART Module Signals

Function

Signal Name

Abbreviation

I/O

Transmit Serial Data

Output

UTXDn

Transmitter serial data outputs for the UART modules. The output is

held high (mark condition) when the transmitter is disabled, idle, or in

the local loopback mode. Data is shifted out, LSB first, on this pin at

the falling edge of the serial clock source.

O

Receive Serial Data

Input

URXDn

Receiver serial data inputs for the UART modules. Data is received on

this pin LSB first. When the UART clock is stopped for power-down

mode, any transition on this pin restarts it.

I

Clear-to-Send

UCTSn

URTSn

Indicate to the UART modules that they can begin data transmission.

I

Request-to-Send

Automatic request-to-send outputs from the UART modules. This

signal can also be configured to be asserted and negated as a

function of the RxFIFO level.

O

1.11 DMA Timer Signals

Table 12 describes the signals of the four DMA timer modules.

Table 12. DMA Timer Signals

Signal Name

Abbreviation

Function

I/O

DMA Timer Input

DTINn

Event input to the DMA timer modules.

I

DMA Timer Output

DTOUTn

Programmable output from the DMA timer modules.

O

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

24

Freescale Semiconductor

MCF52235 Family Configurations

1.12 ADC Signals

Table 13 describes the signals of the Analog-to-Digital Converter.

Table 13. ADC Signals

Function

Signal Name

Abbreviation

I/O

Analog Inputs

AN[7:0]

V_RH

Inputs to the A-to-D converter.

I

Analog Reference

Reference voltage high and low inputs.

V_RL

Analog Supply

V_DDA

V_SSA

Isolate the ADC circuitry from power supply noise

—

1.13 General Purpose Timer Signals

Table 14 describes the General Purpose Timer Signals.

Table 14. GPT Signals

Function

Inputs to or outputs from the general purppose timer module

Signal Name

Abbreviation

I/O

General Purpose Timer

Input/Output

GPT[3:0]

I/O

1.14 Pulse Width Modulator Signals

Table 15 describes the PWM signals.

Table 15. PWM Signals

Function

PWM[7:0] Pulse width modulated output for PWM channels

Signal Name

Abbreviation

I/O

PWM Output Channels

O

1.15 Debug Support Signals

These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM logic.

Table 16. Debug Support Signals

Signal Name

Abbreviation

Function

I/O

JTAG Enable

Test Reset

JTAG_EN

TRST

Select between debug module and JTAG signals at reset

I

This active-low signal is used to initialize the JTAG logic

asynchronously.

Test Clock

TCLK

TMS

Used to synchronize the JTAG logic.

I

Test Mode Select

Used to sequence the JTAG state machine. TMS is sampled on the

rising edge of TCLK.

Test Data Input

TDI

Serial input for test instructions and data. TDI is sampled on the rising

edge of TCLK.

I

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

25

MCF52235 Family Configurations

Table 16. Debug Support Signals (continued)

Function

Signal Name

Abbreviation

TDO

I/O

Test Data Output

Serial output for test instructions and data. TDO is tri-stateable and is

actively driven in the shift-IR and shift-DR controller states. TDO

changes on the falling edge of TCLK.

O

Development Serial

Clock

DSCLK

BKPT

Development Serial Clock. Internally synchronized input. (The logic

level on DSCLK is validated if it has the same value on two

consecutive rising bus clock edges.) Clocks the serial communication

port to the debug module during packet transfers. Maximum frequency

is PSTCLK/5. At the synchronized rising edge of DSCLK, the data

input on DSI is sampled and DSO changes state.

I

Breakpoint

Breakpoint. Input used to request a manual breakpoint. Assertion of

BKPT puts the processor into a halted state after the current

instruction completes. Halt status is reflected on processor status

signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling

normal BKPT functionality), asserting BKPT generates a debug

interrupt exception in the processor.

Development Serial

Input

DSI

Development Serial Input. Internally synchronized input that provides

data input for the serial communication port to the debug module after

the DSCLK has been seen as high (logic 1).

I

Development Serial

Output

DSO

Development Serial Output. Provides serial output communication for

debug module responses. DSO is registered internally. The output is

delayed from the validation of DSCLK high.

O

Debug Data

DDATA[3:0] Display captured processor data and breakpoint status. The CLKOUT

signal can be used by the development system to know when to

sample DDATA[3:0].

Processor Status Clock

PSTCLK

Processor Status Clock. Delayed version of the processor clock. Its

rising edge appears in the center of valid PST and DDATA output.

PSTCLK indicates when the development system should sample PST

and DDATA values.

If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, PST,

and DDATA outputs from toggling without disabling triggers.

Non-quiescent operation can be re-enabled by clearing CSR[PCD],

although the external development systems must resynchronize with

the PST and DDATA outputs.

PSTCLK starts clocking only when the first non-zero PST value (0xC,

0xD, or 0xF) occurs during system reset exception processing.

Processor Status

Outputs

PST[3:0]

ALLPST

Indicate core status. Debug mode timing is synchronous with the

processor clock; status is unrelated to the current bus transfer. The

CLKOUT signal can be used by the development system to know

when to sample PST[3:0].

O

All Processor Status

Outputs

Logical AND of PST[3:0]

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

26

Freescale Semiconductor

MCF52235 Family Configurations

1.16 EzPort Signal Descriptions

Table 17 contains a list of EzPort external signals

Table 17. EzPort Signal Descriptions

Abbreviation Function

EZPCK Shift clock for EzPort transfers

Signal Name

I/O

EzPort Clock

I

EzPort Chip Select

EZPCS

EZPD

EZPQ

Chip select for signalling the start and end

of serial transfers

I

EzPort Serial Data In

EzPort Serial Data Out

EZPD is sampled on the rising edge of

EZPCK

I

EZPQ transitions on the falling edge of

EZPCK

O

1.17 Power and Ground Pins

The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided for adequate current

capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.

Table 18. Power and Ground Pins

Signal Name

Abbreviation

Function

I/O

PLL Analog Supply

VDDPLL,

VSSPLL

Dedicated power supply signals to isolate the sensitive PLL analog

circuitry from the normal levels of noise present on the digital power

supply.

I

Positive Supply

Ground

VDD

VSS

These pins supply positive power to the core logic.

This pin is the negative supply (ground) to the chip.

I

—

Some of the V and V pins on the device are only to be used for noise bypass. Figure 5 shows a typical connection diagram.

DD

SS

Pay particular attention to those pins which show only capacitor connections. Do not connect power supply voltage directly to

these pins.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

27

Electrical Characteristics

33

35

69

70

71

72

58

11

10

31

30

45

44

74

73

V_DDPLL

0.22µF

0.1µF

1000pF

V

_SSPLL

V_DDA

V_RH

10µF

10V

Tantalum

0.1µF

10µH

*

V_RL

V_SSA

V_DDR

V_SSX1

V_DDX1

V_DDX2

V_SSX2

V_DD2

V_SS2

V_DD1

V_SS1

0.1µF

3.3V

MCF52235

0.1µF

Pin numbering is shown

for the 80-pin LQFP

0.22µF

0.22µF 0.22µF 0.22µF

12.4K

1%

*

optional

Figure 5. Suggested Connection Scheme for Power and Ground

2

Electrical Characteristics

This section contains electrical specification tables and reference timing diagrams for the MCF52235, including detailed

information on power considerations, DC/AC electrical characteristics, and AC timing specifications.

NOTE

The parameters specified in this appendix supersede any values found in the module

specifications.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

28

Freescale Semiconductor

Electrical Characteristics

2.1

Maximum Ratings

1, 2

Table 19. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply voltage

V_DD

V_DDPLL

V_IN

–0.3 to +4.0

–0.3 to + 4.0

0 to 3.3

V

Clock synthesizer supply voltage

Digital input voltage ³

EXTAL pin voltage

V

V_EXTAL

V_XTAL

I_DD

V

XTAL pin voltage

0 to 3.3

V

Instantaneous maximum current

25

mA

Single pin limit (applies to all pins) ^{4, 5}

Operating temperature range (packaged)

T_A

(T_L- T_H)

–40 to 85

C

Storage temperature range

T_stg

–65 to 150

1

2

Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum

Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress

beyond those listed may affect device reliability or cause permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or electrical

fields; however, it is advised that normal precautions be taken to avoid application of any voltages

higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is

enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V_SSor V_DD).

Input must be current limited to the I_DDvalue specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then

use the larger of the two values.

3

4

5

All functional non-supply pins are internally clamped to V_SSand V_DD

The power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_in> V_DD) is greater than I_DD

.

,

the injection current may flow out of V_DDand could result in external power supply going out of

regulation. Ensure external V_DDload shunts current greater than maximum injection current. This is

the greatest risk when the MCU is not consuming power (ex; no clock). The power supply must

maintain regulation within operating V_DDrange during instantaneous and operating maximum

current conditions.

Table 20 lists thermal resistance values.

NOTE

The use of this device in one- or two-layer board designs is not recommended due to the

limited thermal conductance provided by those boards.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

29

Electrical Characteristics

Table 20. Thermal Characteristics

Symbol

Characteristic

Junction to ambient, natural convection

Package¹

Value

Unit

_JA

80-pin LQFP, four-layer board

112-pin LQFP, four-layer board

121 MAPBGA, four-layer board

80-pin LQFP, one-layer board¹

121 MAPBGA, one-layer board¹

112-pin LQFP, one-layer board¹

80-pin LQFP, four-layer board

112-pin LQFP, four-layer board

121 MAPBGA, four-layer board

80-pin LQFP, one-layer board¹

112-pin LQFP, one-layer board¹

121 MAPBGA, one-layer board¹

80-pin LQFP

36.0^2,3

35.0

32

C/W

49.0¹

56¹

44.0¹

30.0

29.0

28

Junction to ambient (@200 ft/min)

_JMA

C/W

39.0¹

35.0¹

46¹

Junction to board

_JB

_JC

_jt

T_j

22.0⁴

23.0

18

C/W

^oC

112-pin LQFP

121 MAPBGA, four-layer board

80-pin LQFP

Junction to case

6.0⁵

112-pin LQFP

6.0

121 MAPBGA

10

Junction to top of package, natural convection

Maximum operating junction temperature

80-pin LQFP

2.0⁶

130

112-pin LQFP

121 MAPBGA

All

1

The use of this device in one- or two-layer board designs is not recommended due to the limited thermal conductance

provided by those boards.

2



_JMAand _jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of _JMAand power dissipation specifications in the system design to prevent device junction

temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures

can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature

specification can be verified by physical measurement in the customer’s system using the _jtparameter, the device power

dissipation, and the method described in EIA/JESD Standard 51-2.

3

4

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

5

6

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

in conformance with Psi-JT.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

30

Freescale Semiconductor

Electrical Characteristics

The average chip-junction temperature (T ) in C can be obtained from

J

T_J= T_A+ P_D _JMA



Eqn. 1

where

•

T = ambient temperature, C

A



= package thermal resistance, junction-to-ambient, C/W

JMA

P = P

+ P

I/O

D

INT

P

= chip internal power, I  V , watts

DD DD

= power dissipation on input and output pins — user determined

INT

I/O

For most applications, PI/O < P

and can be ignored. An approximate relationship between P and T (if P is neglected) is:

INT

D

J

I/O

P_D= K  T_J+ 273C

Eqn. 2

Eqn. 3

Solving equations 1 and 2 for K gives:

2

K = P_D T_A+ 273C + _JMA P_D

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)

D

for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively

A

D

J

for any value of T .

A

2.2

ESD Protection

1

Table 21. ESD Protection Characteristics

Characteristic

Symbol

Value

Units

ESD target for Human Body Model

HBM

1500 (ADC and EPHY pins)

2000 (All other pins)

V

ESD target for Charged Device Model

HBM circuit description

CDM

R_series

C

250

1500

100

V

ohms

pF

Number of pulses per pin (HBM)

positive pulses

negative pulses

—

1

Number of pulses per pin (CDM)

positive pulses

negative pulses

—

3

Interval of pulses (HBM)

—

1.0

0.2

sec

Interval of pulses (CDM)

1

A device is defined as a failure if the device no longer meets the device specification requirements after

exposure to ESD pulses. Complete DC parametric and functional testing is performed per applicable device

specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

31

Electrical Characteristics

2.3

DC Electrical Specifications

1

Table 22. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Supply voltage

V_DD

V_IH

3.0

0.7 V_DD

V_SS– 0.3

0.06 V_DD

2.15

3.6

4.0

V

Input high voltage

Input low voltage

V_IL

0.35 x V_DD

—

V

Input hysteresis

V_HYS

V_LVD

V_LVDHYS

I_in

mV

V

Low-voltage detect trip voltage (V_DDfalling)

Low-voltage detect hysteresis (V_DDrising)

Input leakage current

2.3

60

120

mV

A

–1.0

1.0

V_in= V_DDor V_SS, input-only pins

High impedance (off-state) leakage current

I_OZ

V_OH

V_OL

–1.0

V_DD- 0.5

__

1.0

__

A

V

V_in= V_DDor V_SS, all input/output and output pins

Output high voltage (all input/output and all output pins)

I_OH= –2.0 mA

Output low voltage (all input/output and all output pins)

I_OL= 2.0 mA

0.5

V

Weak internal pull-up device current, tested at V_ILmax.²

Input capacitance ³

I_APU

C_in

–10

–130

A

pF

All input-only pins

All input/output (three-state) pins

—

7

Load capacitance⁴

Low drive strength

High drive strength

pF

C_L

I_IC

25

50

3, 5, 6, 7

DC injection current

mA

V_NEGCLAMP=V_SS– 0.3 V, V_POSCLAMP= V_DD+ 0.3

Single pin limit

Total MCU limit, Includes sum of all stressed pins

–1.0

–10

1.0

10

1

Refer to Table 25 for additional PLL specifications.

Refer to Table 3 for pins with internal pull-up devices.

2

3

4

This parameter is characterized before qualification rather than 100% tested.

pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces

require transmission line analysis to determine proper drive strength and termination.

5

6

All functional non-supply pins are internally clamped to V_SSand their respective V_DD

.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.

7

The power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum

current conditions. If positive injection current (V_in> V_DD) is greater than I_DD, the injection current may flow out of V_DD

and could result in external power supply going out of regulation. Ensure that the external V_DDload shunts current

greater than maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are:

if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, the system

clock is not present during the power-up sequence until the PLL has attained lock.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

32

Freescale Semiconductor

Electrical Characteristics

Table 23. Active Current Consumption Specifications

Typical

Running from Running from Running from Running from

Characteristic

Symbol

Peak

Unit

SRAM,

Flash,

Flash, EPHY Flash, EPHY

EPHY Off

10BaseT

100BaseT

Active current, core and I/O I_DDR+I_DDX

PLL @25 MHz

PLL @60 MHz

+I_DDA

75

130

82

138

150

220

260

310

290

340

mA

Analog supply current

Normal operation

Low-power STOP

I_DDA

20

15

20

15

20

15

20

15

30

50

mA

A

1

Table 24. Current Consumption Specifications in Low-Power Modes

PLL @25 MHz PLL @60 MHz PLL @60 MHz

Mode²

Unit

(typical)³

(peak)⁴

STOP mode 3 (STPMD[1:0]=11)

0.2

7

1.0

—

mA

STOP mode 2 (STPMD[1:0]=10)

STOP mode 1 (STPMD[1:0]=01)

10

16

25

12

27

45

STOP mode 0 (STPMD[1:0]=00)

WAIT

DOZE

RUN

1

All values are measured with a 3.30 V power supply.

Refer to the “Power Management” chapter in the MCF52235 ColdFire^®Integrated

Microcontroller Reference Manual for more information on low-power modes.

2

3

4

These values were obtained with CLKOUT and all peripheral clocks except for the CFM clock

disabled prior to entering low-power mode. The tests were performed at room temperature. All

code was executed from flash memory; running code from SRAM further reduces power

consumption.

These values were obtained with CLKOUT and all peripheral clocks enabled. All code was

executed from flash memory.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

33

Electrical Characteristics

2.4

Phase Lock Loop Electrical Specifications

Table 25. Oscillator and PLL Electrical Specifications

(V_DDand V_DDPLL= 2.7 to 3.6 V, V_SS= V_SSPLL= 0 V)

Characteristic

Symbol

Min

Max

Unit

Clock Source Frequency Range of EXTAL Frequency Range

MHz

• Crystal

f_crystal

f_ext

0.5

0

25.0

60.0

• External¹

PLL reference frequency range

f_{ref_pll}

2

10.0

MHz

System frequency ²

External clock mode

On-Chip PLL Frequency

f_sys

MHz

0

60

f

_ref/ 32

Loss of reference frequency ^{3, 5}

Self clocked mode frequency ^{4, 5}

Crystal start-up time ^{5, 6}

f_LOR

f_SCM

t_cst

100

1

1000

5

kHz

MHz

ms

—

10

EXTAL input high voltage

Crystal reference

V_IHEXT

V

V_DD- 1.0

2.0

V_DD

3.0⁷

External reference

EXTAL input low voltage

Crystal reference

V_ILEXT

V

V_SS

1.0

0.8

External reference

XTAL output high voltage

I_OH= 1.0 mA

V_OL

V

V_DD–1.0

—

XTAL output low voltage

I_OL= 1.0 mA

—

0.5

—

XTAL load capacitance⁸

PLL lock time^5,9

pF

t_lpll

500

s

Power-up to lock time ^{5, 7,9}

With crystal reference

t_lplk

—

10.5

500

ms

s

Without crystal reference

Duty cycle of reference ⁵

Frequency un-LOCK range

Frequency LOCK range

t_dc

40

60

1.5

% f_sys

f_UL

–1.5

–0.75

fLCK

C_jitter

0.75

CLKOUT period Jitter ^{5, 6, 8, 10,11}, measured at f_SYSMax

Peak-to-peak jitter (clock edge to clock edge)

Long term jitter (averaged over 2 ms interval)

—

10

0.01

% f_sys

1

In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.

All internal registers retain data at 0 Hz.

Loss of reference frequency is the reference frequency detected internally that transitions the PLL into self-clocked mode.

2

3

4

Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f_LORwith

default MFD/RFD settings.

5

6

This parameter is characterized before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

34

Freescale Semiconductor

Electrical Characteristics

7

8

9

This value has been updated

Load capacitance determined from crystal manufacturer specifications and include circuit board parasitics.

Assuming a reference is available at power up, lock time is measured from the time V_DDand V_DDPLLare valid to RSTO

negating. If the crystal oscillator is the reference for the PLL, the crystal start up time must be added to the PLL lock time to

determine the total start-up time.

¹⁰Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_sys

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via V_DDPLLand V_SSPLLand variation in crystal oscillator frequency increase the C_jitterpercentage

for a given interval

¹¹Based on slow system clock of 40 MHz measured at f_sysmax.

2.5

General Purpose I/O Timing

GPIO can be configured for certain pins of the QSPI, timers, UARTs, FEC, and interrupts. When in GPIO mode, the timing

specification for these pins is given in Table 26 and Figure 6.

The GPIO timing is met under the following load test conditions:

•

50 pF / 50  for high drive

25 pF / 25  for low drive

Table 26. GPIO Timing

Num

Characteristic

Symbol

Min

Max

Unit

G1

G2

G3

G4

CLKOUT high to GPIO output valid

CLKOUT high to GPIO output invalid

GPIO input valid to CLKOUT high

CLKOUT high to GPIO input invalid

t_CHPOV

t_CHPOI

t_PVCH

t_CHPI

—

1.5

9

10

—

ns

1.5

CLKOUT

G2

G1

GPIO Outputs

G3

G4

GPIO Inputs

Figure 6. GPIO Timing

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

35

Electrical Characteristics

2.6

Reset Timing

Table 27. Reset and Configuration Override Timing

(V_DD= 2.7 to 3.6 V, V_SS= 0 V, T_A= T_Lto T_H)¹

Num

Characteristic

Symbol

Min

Max

Unit

R1 RSTI input valid to CLKOUT high

R2 CLKOUT high to RSTI input invalid

R3 RSTI input valid time ²

t_RVCH

t_CHRI

9

1.5

5

—

10

ns

t_RIVT

t_CYC

ns

R4 CLKOUT high to RSTO valid

t_CHROV

—

1

2

All AC timing is shown with respect to 50% V_DDlevels unless otherwise noted.

During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the

system. Therefore, RSTI must be held a minimum of 100ns.

CLKOUT

1R1

R2

R3

RSTI

R4

RSTO

Figure 7. RSTI and Configuration Override Timing

2

2.7

I C Input/Output Timing Specifications

2

Table 28 lists specifications for the I C input timing parameters shown in Figure 8.

2

Table 28. I C Input Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1

I2

I3

I4

I5

I6

I7

I8

I9

2  t_CYC

8  t_CYC

—

1

ns

ms

ns

ms

ns

Clock low period

SCL/SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

0

—

1

SCL/SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

4  t_CYC

0

—

Data setup time

Start condition setup time (for repeated start condition only)

Stop condition setup time

2  t_CYC

2

Table 29 lists specifications for the I C output timing parameters shown in Figure 8.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

36

Freescale Semiconductor

Electrical Characteristics

Table 29. I C Output Timing Specifications between I2C_SCL and I2C_SDA

2

Num

Characteristic

Start condition hold time

Min

Max

Units

I1 ¹

I2 ¹

I3 ²

6  t_CYC

10  t_CYC

—

ns

µs

Clock low period

I2C_SCL/I2C_SDA rise time

(V_IL= 0.5 V to V_IH= 2.4 V)

I4 ¹

I5 ³

Data hold time

7  t_CYC

—

3

ns

I2C_SCL/I2C_SDA fall time

(V_IH= 2.4 V to V_IL= 0.5 V)

—

I6 ¹

I7 ¹

I8 ¹

Clock high time

Data setup time

10  t_CYC

2  t_CYC

20 x t_CYC

—

ns

Start condition setup time (for repeated start

condition only)

I9 ¹

Stop condition setup time

10 x t_CYC

—

ns

1

Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the

maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 29. The I²C

interface is designed to scale the actual data transition time to move it to the middle of the SCL low

period. The actual position is affected by the prescale and division values programmed into the IFDR;

however, the numbers given in Table 29 are minimum values.

2

3

Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive

low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up

resistor values.

Specified at a nominal 50-pF load.

Figure 8 shows timing for the values in Table 28 and Table 29.

I2

I6

I5

SCL

SDA

I3

I1

I4

I8

I9

I7

2

Figure 8. I C Input/Output Timings

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

37

Electrical Characteristics

2.8

EPHY Parameters

2.8.1

EPHY Timing

Table 30 and Figure 9 show the relevant EPHY timing parameters.

Table 30. EPHY Timing Parameters

Num

Characteristic

EPHY startup time

Symbol

Value

Unit

E1

t_Start-Up

360

s

EPHYEN

MDIO

E1

Figure 9. EPHY Timing

2.8.2

10BASE-T SQE (Heartbeat) Timing

Table 31 and Figure 10 show the relevant 10BASE-T SQE (heartbeat) timing parameters.

Table 31. 10BASE-T SQE (Heartbeat) Timing Parameters

Characteristic

Symbol

Min

Typ¹

Max

Units

COL (SQE) delay after TXEN off

COL (SQE) pulse duration

t1

t2

—

1.0

—

s

1

Typical values are at 25C.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

38

Freescale Semiconductor

Electrical Characteristics

TXC

TXEN

t1

t2

COL

Figure 10. 10BASE-T SQE (Heartbeat) Timing

2.8.3

10BASE-T Jab and Unjab Timing

Table 32 and Figure 11 show the relevant 10BASE-T jab and unjab timing parameters.

Table 32. 10BASE-T Jab and Unjab Timing Parameters

Parameter

Maximum transmit time

Unjab time

Symbol

Min

Typ¹

Max

Units

t1

t2

—

98

—

ms

525

1

Typical values are at 25C.

TXEN

t1

TXD

COL

t2

Figure 11. 10BASE-T Jab and Unjab Timing

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

39

Electrical Characteristics

2.8.4

Transceiver Characteristics

Table 33. 10BASE-T Transceiver Characteristics

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Peak differential output voltage

V_OP

2.2

2.5

2.8

V

With specified transformer and line

replaced by 100 ( 1%) load

Transmit timing jitter

—

0

2

11

ns

Using line model specified in the

IEEE 802.3

Receive dc input impedance

Z_in

—

10

—

k

0.0 < V_in< 3.3 V

Receive differential squelch level

V_squelch

300

400

585

mV

3.3 MHz sine wave input

Table 34. 100BASE-TX Transceiver Characteristics

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Transmit Peak Differential Output

Voltage

V_OP

0.95

1.00

1.05

V

With specified transformer and line

replaced by 100 ( 1%) load

Transmit Signal Amplitude

Symmetry

V_sym

t_rf

98

3

100

4

102

5

%

With specified transformer and line

replaced by 100  ( 1%) load

Transmit Rise/Fall Time

ns

With specified transformer and line

replaced by 100  ( 1%) load

Transmit Rise/Fall Time Symmetry

Transmit Overshoot/UnderShoot

Transmit Jitter

t_rfs

V_osh

—

–0.5

—

0

+0.5

5

ns

%

ns

V

See IEEE 802.3 for details

2.5

.6

1.4

—

Receive Common Mode Voltage

Receiver Maximum Input Voltage

V_cm

V_max

—

1.6

—

V_DDRX= 2.5 V

4.7

V

V_DDRX= 2.5 V. Internal circuits

protected by divider in shutdown

2.9

Analog-to-Digital Converter (ADC) Parameters

Table 35 lists specifications for the analog-to-digital converter.

1

Table 35. ADC Parameters

Name

Characteristic

Low reference voltage

Min

Typical

Max

Unit

V_REFL

V_REFH

V_DDA

V_ADIN

RES

INL

V_SS

—

V_REFH

V_DDA

3.6

V

High reference voltage

V_REFL

3.0

—

Analog supply voltage

3.3

V

Input voltages

V_REFL

12

—

V_REFH

12

V

Resolution

bits

LSB³

LSB

Integral non-linearity (full input signal range)²

Integral non-linearity (10% to 90% input signal range)⁴

Differential non-linearity

Monotonicity

—

2.5

3

INL

—

2.5

3

DNL

—

–1 < DNL < 1

<1

Guaranteed

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

40

Freescale Semiconductor

Electrical Characteristics

1

Table 35. ADC Parameters (continued)

Name

Characteristic

Min

Typical

Max

Unit

f_ADIC

R_AD

ADC internal clock

Conversion range

ADC power-up time⁵

Recovery from auto standby

Conversion time

0.1

V_REFL

—

5.0

V_REFH

13

1

MHz

—

V

t_ADPU

t_REC

t_ADC

t_ADS

C_ADI

X_IN

6

t_AICcycles⁶

—

0

t_AICcycles

—

6

—

t_AICcycles

Sample time

—

1

—

t_AICcycles

pF

Input capacitance

—

See Figure 12

—

Input impedance

—

See Figure 12

—

W

I_ADI

Input injection current⁷, per pin

V_REFHcurrent

—

0

3

mA

mV

—

I_VREFH

—

V_OFFSETOffset voltage internal reference

E_GAINGain error (transfer path)

V_OFFSETOffset voltage external reference

—

11

1

15

1.01

—

.99

—

3

mV

dB

SNR

THD

Signal-to-noise ratio

—

62 to 66

–75

75

—

Total harmonic distortion

Spurious free dynamic range

Signal-to-noise plus distortion

Effective number OF bits

—

dB

SFDR

SINAD

ENOB

—

dB

—

65

—

dB

9.1

10.6

—

Bits

1

2

3

4

5

6

7

All measurements were made at V_DD= 3.3V, V_REFH= 3.3V, and V_REFL= ground

INL measured from V_IN= V_REFLto V_IN= V_REFH

LSB = Least Significant Bit

INL measured from V_IN= 0.1V_REFHto V_IN= 0.9V_REFH

Includes power-up of ADC and V_REF

ADC clock cycles

The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the

ADC

2.9.1

Equivalent Circuit for ADC Inputs

Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3

is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (V_REFH-V_REFL)/2,

while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via

S3, with the result that a single-ended analog input is switched to a differential voltage centered about (V_REFH-V_REFL)/2. The

switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional

capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides

isolation during the charge-sharing phase. One aspect of this circuit is that there is an ongoing input current, which is a function

of the analog input voltage, V_REF, and the ADC clock frequency.

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

41

Electrical Characteristics

125W ESD Resistor

8pF noise damping capacitor

4

3

Analog Input

S1

C1

S/H

S3

C2

S2

(V_REFH- V_REFL)  2

2

1

C1 = C2 = 1pF

1

Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF

2

3

4

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF

Equivalent resistance for the channel select mux; 100 ohms

Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input

and is only connected to it at sampling time; 1.4pF

1

5

-----------------------------------------------------------------------------------------

Equivalent input impedance, when the input is selected =

ADC CLOCK RATE  1.4  10^–12

Figure 12. Equivalent Circuit for A/D Loading

2.10 DMA Timers Timing Specifications

Table 36 lists timer module AC timings.

Table 36. Timer Module AC Timing Specifications

Name

Characteristic¹

Min

Max

Unit

T1

T2

DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time

DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width

3  t_CYC

1  t_CYC

—

ns

1

All timing references to CLKOUT are given to its rising edge.

2.11 EzPort Electrical Specifications

Table 37. EzPort Electrical Specifications

Name

Characteristic

Min

Max

_sys/ 2

Unit

EP1

EP1a

EP2

EP3

EP4

EP5

EP6

EPCK frequency of operation (all commands except READ)

EPCK frequency of operation (READ command)

EPCS_b negation to next EPCS_b assertion

EPCS_B input valid to EPCK high (setup)

EPCK high to EPCS_B input invalid (hold)

EPD input valid to EPCK high (setup)

—

f

MHz

ns

—

f_sys/ 8

—

2 × T_cyc

5

2

5

—

ns

—

ns

—

ns

EPCK high to EPD input invalid (hold)

—

ns

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

42

Freescale Semiconductor

Electrical Characteristics

Table 37. EzPort Electrical Specifications (continued)

Name

Characteristic

Min

Max

Unit

EP7

EP8

EP9

EPCK low to EPQ output valid (out setup)

EPCK low to EPQ output invalid (out hold)

EPCS_B negation to EPQ tri-state

—

0

12

—

12

ns

—

2.12 QSPI Electrical Specifications

Table 38 lists QSPI timings.

Table 38. QSPI Modules AC Timing Specifications

Characteristic

Name

Min

Max

Unit

QS1

QS2

QS3

QS4

QS5

QSPI_CS[3:0] to QSPI_CLK

1

—

2

510

10

—

t_CYC

ns

QSPI_CLK high to QSPI_DOUT valid

QSPI_CLK high to QSPI_DOUT invalid (output hold)

QSPI_DIN to QSPI_CLK (input setup)

QSPI_DIN to QSPI_CLK (input hold)

ns

9

—

ns

9

—

ns

The values in Table 38 correspond to Figure 13.

QS1

QSPI_CS[3:0]

QSPI_CLK

QS2

QSPI_DOUT

QSPI_DIN

QS3

QS4

QS5

Figure 13. QSPI Timing

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

43

Electrical Characteristics

2.13 JTAG and Boundary Scan Timing

Table 39. JTAG and Boundary Scan Timing

Num

Characteristics¹

TCLK frequency of operation

Symbol

Min

Max

Unit

J1

J2

f_JCYC

t_JCYC

DC

1/4

—

3

f_sys/2

ns

TCLK cycle period

4  t_CYC

J3

TCLK clock pulse width

t_JCW

26

0

J4

TCLK rise and fall times

t_JCRF

J5

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

t_BSDST

t_BSDHT

t_BSDV

4

—

33

—

26

8

J6

26

0

J7

J8

t_BSDZ

0

J9

t_TAPBST

t_TAPBHT

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

4

J10

J11

J12

J13

J14

10

0

TCLK low to TDO high Z

0

TRST assert time

100

10

—

TRST setup time (negation) to TCLK high

1

JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.

J2

J3

V_IH

TCLK

V_IL

(input)

J4

Figure 14. Test Clock Input Timing

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

44

Freescale Semiconductor

Electrical Characteristics

TCLK

V_IL

V_IH

J5

Input Data Valid

J6

Data Inputs

J7

J8

Data Outputs

Output Data Valid

Data Outputs

J7

Output Data Valid

Figure 15. Boundary Scan (JTAG) Timing

TCLK

V_IL

V_IH

J9

J10

TDI

TMS

Input Data Valid

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 16. Test Access Port Timing

TCLK

TRST

14

13

Figure 17. TRST Timing

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

45

Electrical Characteristics

2.14 Debug AC Timing Specifications

Table 40 lists specifications for the debug AC timing parameters shown in Figure 19.

Table 40. Debug AC Timing Specification

60 MHz

Num

Characteristic

Units

Min

Max

D1

D2

PST, DDATA to CLKOUT setup

4

—

ns

CLKOUT to PST, DDATA hold

DSI-to-DSCLK setup

1.5

D3

1  t_CYC

4  t_CYC

5  t_CYC

4

—

D4 ¹

DSCLK-to-DSO hold

—

D5

DSCLK cycle time

—

D6

BKPT input data setup time to CLKOUT Rise

BKPT input data hold time to CLKOUT Rise

CLKOUT high to BKPT high Z

—

D7

1.5

—

D8

0.0

10.0

1

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to

the rising edge of CLKOUT.

Figure 18 shows real-time trace timing for the values in Table 40.

CLKOUT

D1

D2

PST[3:0]

DDATA[3:0]

Figure 18. Real-Time Trace AC Timing

Figure 19 shows BDM serial port AC timing for the values in Table 40.

CLKOUT

DSCLK

DSI

D5

D3

Current

Past

DSO

Current

Figure 19. BDM Serial Port AC Timing

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

46

Freescale Semiconductor

Mechanical Outline Drawings

3

Mechanical Outline Drawings

This section describes the physical properties of the MCF52235 and its derivatives.

3.1

80-pin LQFP Package

–X–

X= L, M, N

4X

4X 20 TIPS

0.20 (0.008)

H

L–M

N

T

L–M

N

P

80

61

C

L

1

60

AB

G

–M–

B1

VIEW Y

B

V

PLATING

F

–L–

3X VIEW Y

BASE

METAL

J

V1

41

20

D

U

21

40

–N–

M

S

0.13 (0.005)

T

L–M

N

A1

S1

SECTION AB–AB

ROTATED 90 CLOCKWISE

A

S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –L–, –M– AND –N– TO BE DETERMINED

AT DATUM PLANE –H–.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –T–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –H–.

C

8X

2

0.10 (0.004)

T

–H–

–T–

SEATING

PLANE

VIEW AA

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460

(0.018). MINIMUM SPACE BETWEEN

PROTRUSION AND ADJACENT LEAD OR

PROTRUSION 0.07 (0.003).

(W)

C2

S

0.05 (0.002)

MILLIMETERS

MIN MAX

14.00 BSC

7.00 BSC

14.00 BSC

7.00 BSC

INCHES

MIN MAX

0.551 BSC

0.276 BSC

0.551 BSC

0.276 BSC

1

DIM

A

A1

B

B1

C

C1

C2

D

E

F

G

J

K

P

R1

S

S1

U

0.25 (0.010)

2X R R1

GAGE

PLANE

–––

0.04

1.30

0.22

0.40

0.17

1.60

–––

0.002

0.051

0.009

0.016

0.007

0.063

0.24

1.50

0.38

0.75

0.33

0.009

0.059

0.015

0.030

0.013

(K)

C1

E

(Z)

0.65 BSC

0.026 BSC

VIEW AA

0.09

0.27

0.004

0.011

0.50 REF

0.325 BSC

0.020 REF

0.013 REF

0.004 0.008

0.630 BSC

0.315 BSC

0.10

0.20

16.00 BSC

8.00 BSC

0.09

0.16

0.004

0.006

V

16.00 BSC

0.630 BSC

0.315 BSC

0.008 REF

0.039 REF

V1

W

Z

8.00 BSC

0.20 REF

1.00 REF

0

01

02

0

9

10

–––

14

0

9

10

–––

14

CASE 917A–02

ISSUE C

DATE 09/21/95

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

47

Mechanical Outline Drawings

3.2 112-pin LQFP Package

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

48

Freescale Semiconductor

Mechanical Outline Drawings

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

49

Mechanical Outline Drawings

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

50

Freescale Semiconductor

Mechanical Outline Drawings

3.3 121 MAPBGA Package

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

51

Mechanical Outline Drawings

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

52

Freescale Semiconductor

Revision History

4 Revision History

Table 41. Revision History

Revision

Description

2 (Jul 2006)

• Updated available packages.

• Inserted mechanical drawings.

• Corrected signal pinouts and table.

3 (Feb 2007)

• Changed signal names TIN to DTIN and TOUT to DTOUT to match the MCF52235 ColdFire^®Integrated

Microcontroller Reference Manual.

• Added overbars to extend over entire UCTSn and URTSn signal name.

• Added revision history.

• Formatting, layout, spelling, and grammar corrections.

• Updated block diagram and feature information to match Revision 3 of the MCF52235 ColdFire^®

Integrated Microcontroller Reference Manual.

• Deleted the “PSTCLK cycle time” row from the “Debug AC Timing Specifications” table.

• Added “EPHY Timing” section.

• Deleted the “RAM standby supply voltage” entry from Table 19.

• Changed the minimum value for SNR, THD, SFDR, and SINAD in the “ADC parameters” table (was

TBD, is “—”).

• In the “Pin Functions by Primary and Alternate Purpose” table, changed the pin number for IRQ11 on

the 80 LQFP package (was “—”, is 41).

• Updated the “Thermal characteristics” table to include proper thermal resistance values.

• Added two tables, “Active Current Consumption Specifications” and “Current Consumption

Specifications in Low-Power Modes”, containing the latest current consumption information.

• Changed the value of T_jin the “Thermal Characteristics” table (was 105 C, is 130 C for all packages).

• Added the following note to and above the “Thermal Characteristics” table: “The use of this device in

one- or two-layer board designs is not recommended due to the limited thermal conductance provided

by those boards.”

• Added the value for _jtfor the 121MAPBGA package (2.0 C/W).

4 (May 2007)

5 (Sep 2007)

• Formatting, layout, spelling, and grammar corrections.

• Added load test condition information to the “General Purpose I/O Timing” section.

• Added specifications for V_LVDand V_LVDHYSto the “DC electrical specifications” table.

• Formatting, layout, spelling, and grammar corrections.

• Added information about the MCF52232 and MCF52236 devices.

• Revised the part number table to include full Freescale orderable part numbers.

• Synchronized the “Pin Functions by Primary and Alternate Purpose” table in the device reference

manual and data sheet.

• Added specifications for V_REFL, V_REFH, and V_DDAto the “ADC Parameters” table.

• Added several EPHY specifications.

6 (Oct 2007)

7 (Aug 2008)

• Formatting, layout, spelling, and grammar corrections.

• Changed the data sheet classification (was “Product Preview”, is “Advance Information”).

• Added the “EzPort Electrical Specifications” section.

• Updated the “ESD Protection” section.

• Changed document type from Advance Information to Technical Data.

• Added supported device list in subtitle.

• Removed preliminary text from electrical specifications section as device is fully characterized.

• Corrected I_VREFH, VREFH current unit from “m” to “mA” in ADC specification table.

• Changed V_OFFSETfrom TBD to — in ADC specification table.

8 (Jun 2009)

• Updated Orderable Part Number Summary table to include MCF52233CAL60A, MCF52235CAL60A,

and MCF52236AF50A parts

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

Freescale Semiconductor

53

Revision History

Revision

Table 41. Revision History (continued)

Description

8 Sep 2009

8 April 2010

22 Mar 2011

• Updated Table 25 — PLL Electrical Specifications.

• Updated Table 37— EzPort Electrical Specifications

• Updated Table Oscillator and PLL Electrical Specification. In EXTAL input high voltage updated VDD to

3.0

23-Mar-2011

• Changed EXTAL input high voltage (External reference) Maximum to "3.0V" (Instead of "VDD"). Also,

add a note this value has been updated.

• Updated clock generation feature

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10

54

Freescale Semiconductor

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale Semiconductor data sheets and/or specifications can and do vary

in different applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

Semiconductor was negligent regarding the design or manufacture of the part.

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality

and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free

counterparts. For further information, see http://www.freescale.com or contact your

Freescale sales representative.

Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor China Ltd.

Exchange Building 23F

No. 118 Jianguo Road

Chaoyang District

For information on Freescale’s Environmental Products program, go to

http://www.freescale.com/epp.

Beijing 100022

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners.

China

+86 10 5879 8000

support.asia@freescale.com

Freescale Semiconductor Literature Distribution Center

1-800-441-2447 or +1-303-675-2140

Fax: +1-303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Document Number: MCF52235

Rev. 10

3/2011


型号：	LH79525N0Q100A1,557
厂家：	NXP
描述：	RISC Microcontroller, 32-Bit, FLASH, CMOS, PQFP176 时钟微控制器外围集成电路
文件：	总55页 (文件大小：1133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LH79525N0Q100A1,557 [NXP]

相关型号：

LH79531

LH79532/Y

LH79533

LH7A400

LH7A400

LH7A400N0B000

LH7A400N0B000B3A

LH7A400N0B000B5

LH7A400N0C000

LH7A400N0E000

LH7A400N0E000B3A

LH7A400N0E000B5