LPC1102UK_技术文档

LPC1102

32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB

SRAM

Rev. 3 — 18 April 2011

Product data sheet

1. General description

The LPC1102 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit

microcontroller applications, offering performance, low power, simple instruction set and

memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC1102 operates at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC1102 includes 32 kB of flash memory, 8 kB of data

memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general

purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.

2. Features and benefits

System:

ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Serial Wire Debug.

System tick timer.

Memory:

32 kB on-chip flash programming memory.

8 kB SRAM.

In-Application Programming (IAP) and In-System Programming (ISP) support via

on-chip bootloader software.

Digital peripherals:

11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.

GPIO pins can be used as edge and level sensitive interrupt sources.

Four general purpose counter/timers with a total of one capture input and nine

match outputs.

Programmable WatchDog Timer (WDT).

Analog peripherals:

10-bit ADC with input multiplexing among five pins.

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

One SPI controller with SSP features and with FIFO and multi-protocol capabilities

(see Section 7.16).

Clock generation:

12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from an external clock or the internal RC

oscillator.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep and Deep-sleep modes.

Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for any given application through one simple function

call.

Two reduced power modes: Sleep and Deep-sleep modes.

Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

six of the functional pins.

Power-On Reset (POR).

Brownout detect with four separate thresholds for interrupt and forced reset.

Unique device serial number for identification.

Single 3.3 V power supply (1.8 V to 3.6 V).

Available as WLCSP16 package.

3. Applications

Mobile devices

8-/16-bit applications

Portable devices

Consumer peripherals

Lighting

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

wafer level chip-size package; 16 bumps; 2.17 × 2.32 × 0.6 mm

Version

LPC1102UK

WLCSP16

-

4.1 Ordering options

Table 2.

Ordering options

Type number

Flash

Total

SRAM

UART

RS-485

SPI

ADC

channels

Package

WLCSP16

LPC1102UK

32 kB

8 kB

1

5

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

2 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

5. Block diagram

XTALIN

RESET

SWD

LPC1102

IRC

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

TEST/DEBUG

INTERFACE

POR

FUNCTIONS

ARM

CORTEX-M0

clocks and

controls

FLASH

32 kB

SRAM

8 kB

ROM

system bus

slave

HIGH-SPEED

GPIO

GPIO port

PIO0/1

AHB-LITE BUS

slave

AHB TO APB

BRIDGE

RXD

TXD

UART

AD[4:0]

10-bit ADC

SCK, MISO,

MOSI

SPI

CT32B0_MAT[3,1,0]

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

WDT

CT32B1_MAT[2:0]

CT32B1_CAP0

IOCONFIG

CT16B0_MAT[2:0]

SYSTEM CONTROL

PMU

002aaf524

Fig 1. LPC1102 block diagram

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

3 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

6. Pinning information

6.1 Pinning

LPC1102UK

D

C

B

A

ball A1

index area

1

2

3

4

002aaf525

Fig 2. Pin configuration WLCSP16 package

6.2 Pin description

Table 3.

Symbol

LPC1102 pin description table

Start Type Reset Description

logic

input

state^[1]

RESET/PIO0_0

C1^[2]

yes

I

I; PU

RESET — External reset input with 20 ns glitch filter. A LOW

-going pulse as short as 50 ns on this pin resets the device,

causing I/O ports and peripherals to take on their default states,

and processor execution to begin at address 0.

I/O

O

-

PIO0_0 — General purpose digital input/output pin.

PIO0_8 — General purpose digital input/output pin.

MISO0 — Master In Slave Out for SPI.

PIO0_8/MISO/

CT16B0_MAT0

A2^[3]

A3^[3]

A4^[3]

yes

I; PU

-

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9 — General purpose digital input/output pin.

MOSI0 — Master Out Slave In for SPI.

PIO0_9/MOSI/

CT16B0_MAT1

I/O

O

I; PU

-

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWCLK — Serial wire clock.

SWCLK/

I

I; PU

PIO0_10/

SCK/CT16B0_MAT2

I/O

O

-

PIO0_10 — General purpose digital input/output pin.

SCK — Serial clock for SPI.

-

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R — Reserved.

R/PIO0_11/

B4^[4]

yes

-

I; PU

AD0/CT32B0_MAT3

I/O

I

-

PIO0_11 — General purpose digital input/output pin.

AD0 — A/D converter, input 0.

I

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

4 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

LPC1102 pin description table …continued

Start Type Reset Description

logic

input

state^[1]

R/PIO1_0/

AD1/CT32B1_CAP0

B3^[4]

yes

no

-

I; PU

R — Reserved.

I/O

I

-

PIO1_0 — General purpose digital input/output pin.

AD1 — A/D converter, input 1.

-

I

-

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R — Reserved.

R/PIO1_1/

AD2/CT32B1_MAT0

C4^[4]

-

I; PU

I/O

I

-

PIO1_1 — General purpose digital input/output pin.

AD2 — A/D converter, input 2.

-

O

-

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R — Reserved.

R/PIO1_2/

AD3/CT32B1_MAT1

C3^[4]

I; PU

I/O

I

-

PIO1_2 — General purpose digital input/output pin.

AD3 — A/D converter, input 3.

-

O

I/O

I

-

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO — Serial wire debug input/output.

PIO1_3 — General purpose digital input/output pin.

AD4 — A/D converter, input 4.

SWDIO/PIO1_3/AD4/ D4^[4]

CT32B1_MAT2

I; PU

-

O

I/O

I

-

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_6 — General purpose digital input/output pin.

RXD — Receiver input for UART.

PIO1_6/RXD/

CT32B0_MAT0

C2^[3]

D1^[3]

no

I; PU

-

O

I/O

O

I

-

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7 — General purpose digital input/output pin.

TXD — Transmitter output for UART.

PIO1_7/TXD/

CT32B0_MAT1

I; PU

-

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

V_DD

D2; A1

B2^[5]

-

3.3 V supply voltage to the internal regulator, the external rail,

and the ADC. Also used as the ADC reference voltage.

XTALIN

V_SS

I

-

External clock input and input to internal clock generator circuits.

Input voltage must not exceed 1.8 V.

D3; B1

Ground.

[1] Pin state at reset for default function: I = Input; PU = internal pull-up enabled.

[2] 5 V tolerant pad. See Figure 21 for the reset pad configuration.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 20).

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 20).

[5] When the external clock is not used, connect XTALIN as follows: XTALIN can be left floating or can be grounded (grounding is preferred

to reduce susceptibility to noise).

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

5 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The LPC1102 contains 32 kB of on-chip flash memory.

Remark: The LPC1102 supports In-Application Programming (IAP) and In-System

Programming (ISP). For ISP, since there is no dedicated ISP entry pin, user code is

required to invoke ISP functionality. Unprogrammed parts will automatically boot into ISP

mode.

7.3 On-chip SRAM

The LPC1102 contains 8 kB on-chip static RAM memory.

7.4 Memory map

The LPC1102 incorporates several distinct memory regions, shown in the following

figures. Figure 3 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kB of space. This allows

simplifying the address decoding for each peripheral.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

6 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

AHB peripherals

0x5020 0000

LPC1102

4 GB

0xFFFF FFFF

reserved

private peripheral bus

reserved

0xE010 0000

0xE000 0000

127 - 16 reserved

0x5004 0000

reserved

15-12

11-8

7-4

0x5003 0000

0x5002 0000

0x5020 0000

0x5000 0000

reserved

AHB peripherals

reserved

GPIO PIO1

GPIO PIO0

0x5001 0000

0x5000 0000

3-0

APB peripherals

0x4008 0000

31 - 23 reserved

reserved

0x4005 C000

0x4005 8000

0x4008 0000

0x4000 0000

22

APB peripherals

reserved

1 GB

21 - 19 reserved

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

system control

IOCONFIG

18

17

SPI

16

15

flash controller

0x4003 C000

0x4003 8000

0x2000 0000

0.5 GB

14

PMU

reserved

13 - 10 reserved

0x1FFF 4000

0x1FFF 0000

0x4002 8000

0x4002 4000

0x4002 0000

16 kB boot ROM

reserved

9

8

7

6

5

4

3

2

ADC

0x4001 C000

0x4001 8000

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x1000 2000

0x1000 0000

8 kB SRAM

reserved

WDT

1

0

0x4000 4000

0x4000 0000

reserved

0x0000 00C0

0x0000 8000

0x0000 0000

active interrupt vectors

0x0000 0000

32 kB on-chip flash

0 GB

002aaf526

Fig 3. LPC1102 memory map

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

• In the LPC1102, the NVIC supports 19 vectored interrupts including up to 6 inputs to

the start logic from individual GPIO pins.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

7 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

• Four programmable interrupt priority levels, with hardware priority level masking.

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 11 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

The LPC1102 uses accelerated GPIO functions:

• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of 11 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to inputs with pull-ups enabled after reset.

• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin.

7.8 UART

The LPC1102 contains one UART.

Support for RS-485/9-bit mode allows both software address detection and automatic

address detection using 9-bit mode.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

8 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

• Maximum UART data bit rate of 3.125 Mbit/s.

• 16 Byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• FIFO control mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

7.9 SPI serial I/O controller

The LPC1102 contains one SPI controller and fully supports SSP features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SPI supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

Remark: Care must be taken when using the SPI because the SPI clock SCK and the

serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the

SPI is enabled, the serial wire debugger is no longer available.

7.9.1 Features

• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.10 10-bit ADC

The LPC1102 contains one ADC. It is a single 10-bit successive approximation ADC with

five channels.

7.10.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 5 pins.

• Power-down mode.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

9 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

• Measurement range 0 V to V_DD

.

• 10-bit conversion time ≥ 2.44 μs.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

7.11 General purpose external event counter/timers

The LPC1102 includes two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.11.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel that can take a snapshot of the timer value when an input signal

transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.12 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.13 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time

period.

7.13.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

10 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK)× 256 × 4) to (T_cy(WDCLK)× 2²⁴× 4) in

multiples of T_cy(WDCLK)× 4.

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of Watchdog operation under different power reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components and wiring for

increased reliability.

7.14 Clocking and power control

7.14.1 Crystal oscillators

The LPC1102 includes two independent oscillators. These are the Internal RC oscillator

(IRC) and the Watchdog oscillator. Each oscillator can be used for more than one purpose

as required in a particular application.

Following reset, the LPC1102 will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

See Figure 4 for an overview of the LPC1102 clock generation.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

11 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

AHB clock 0

(system)

system clock

SYSTEM CLOCK

DIVIDER

18

AHB clocks 1 to 18

(memories

and peripherals)

AHBCLKCTRL[1:18]

(AHB clock enable)

SPI0 PERIPHERAL

CLOCK DIVIDER

SPI0

IRC oscillator

main clock

UART PERIPHERAL

CLOCK DIVIDER

UART

watchdog oscillator

MAINCLKSEL

(main clock select)

IRC oscillator

WDT CLOCK

DIVIDER

WDT

IRC oscillator

external clock

watchdog oscillator

SYSTEM PLL

WDTUEN

(WDT clock update enable)

SYSPLLCLKSEL

(system PLL clock select)

002aaf527

Fig 4. LPC1102 clock generation block diagram

7.14.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC1102 uses the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.14.1.2 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU or the

watchdog timer. The watchdog oscillator nominal frequency is programmable between 7.8

kHz and 1.7 MHz. The frequency spread over processing and temperature is ±40 %.

7.14.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The PLL

output frequency must be lower than 100 MHz. The output divider may be set to divide by

2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

12 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100 μs.

7.14.3 Wake-up process

The LPC1102 begins operation at power-up by using the 12 MHz IRC oscillator as the

clock source. This allows chip operation to resume quickly. If an external clock or the PLL

is needed by the application, software will need to enable these features and wait for them

to stabilize before they are used as a clock source.

7.14.4 Power control

The LPC1102 supports a variety of power control features. There are two special modes

of processor power reduction: Sleep mode and Deep-sleep mode. The CPU clock rate

may also be controlled as needed by changing clock sources, reconfiguring PLL values,

and/or altering the CPU clock divider value. This allows a trade-off of power versus

processing speed based on application requirements. In addition, a register is provided for

shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides even

better power control.

7.14.4.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through a simple call to the power profiles. The power configuration routine configures the

LPC1102 for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profiles includes a routine to select the optimal PLL settings for a

given system clock and PLL input clock.

7.14.4.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.14.4.3 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut

down except for the watchdog oscillator and the BOD circuit, which can be configured to

remain running in Deep-sleep mode to allow a reset initiated by a timer or BOD event.

Deep-sleep mode allows for additional power savings.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

13 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Six of the GPIO pins (see Table 3) serve as external wake-up pins to a dedicated start

logic to wake up the chip from Deep-sleep mode.

The clock source should be switched to IRC before entering Deep-sleep mode unless the

watchdog oscillator remains running in Deep-sleep mode. The IRC can be switched on

and off glitch-free and provides a clean clock signal after start-up.

7.15 System control

7.15.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.15.2 Reset

Reset has four sources on the LPC1102: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. In addition, there is an ARM

software reset. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by

any source, once the operating voltage attains a usable level, starts the IRC and initializes

the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.15.3 Brownout detection

The LPC1102 includes four levels for monitoring the voltage on the V_DDpin. If this voltage

falls below one of the four selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

7.15.4 Code security (Code Read Protection - CRP)

This feature of the LPC1102 allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) can be

restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0). This mode is useful when CRP is required and flash field

updates are needed but all sectors can not be erased.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

14 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update.

3. Running an application with level CRP3 selected fully disables any access to the chip

via the SWD pins.

Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all

three CRP levels, the user’s application code must provide a flash update mechanism

which reinvokes ISP by defining a user-selected PIO pin for ISP entry.

CAUTION

If Code Read Protection of any level (CRP1, CRP2 or CRP3) is selected, no future factory

testing can be performed on the device.

7.15.5 APB interface

The APB peripherals are located on one APB bus.

7.15.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.15.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.15.1).

7.16 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

Remark: Care must be taken when using the SPI because the SPI clock SCK and the

serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the

SPI is enabled, the serial wire debugger is no longer available.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

15 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD

Parameter

Conditions

Min

1.8

Max

3.6

Unit

V

supply voltage (core and external rail)

input voltage

[2]

V_I

5 V tolerant I/O

pins; only valid

when the V_DD

supply voltage is

present

−0.5

+5.5

V

[3]

I_DD

supply current

per supply pin

per ground pin

-

100

mA

I_SS

ground current

I/O latch-up current

I_latch

−(0.5V_DD) < V_I<

(1.5V_DD);

T_j< 125 °C

[4]

T_stg

storage temperature

−65

+150

150

1.5

°C

W

T_j(max)

P_tot(pack)

maximum junction temperature

total power dissipation (per package)

-

based on package

heat transfer, not

device power

consumption

[5]

V_ESD

electrostatic discharge voltage

human body

−6500

+6500

V

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

16 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

9. Static characteristics

Table 5.

Static characteristics

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

V_DD

Parameter

Conditions

Min

Typ^[1]

Max

Unit

supply voltage (core

and external rail)

1.8

3.3

3.6

V

I_DD

supply current

Active mode; code

while(1){}

executed from flash

system clock = 12 MHz

[2][3][4]

[5][6]

-

2

7

1

-

mA

V

_DD= 3.3 V

system clock = 50 MHz

_DD= 3.3 V

[2][3][5]

[6][7]

V

[2][3][4]

[5][6]

Sleep mode;

system clock = 12 MHz

V_DD= 3.3 V

[2][3][8]

Deep-sleep mode;

V_DD= 3.3 V

-

2

-

μA

Standard port pins, RESET

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up

resistor disabled

-

0.5

10

nA

I_IH

HIGH-level input

current

V_I= V_DD; on-chip

pull-down resistor

disabled

I_OZ

OFF-state output

current

V_O= 0 V; V_O= V_DD

on-chip pull-up/down

resistors disabled

;

-

0.5

-

10

nA

V

[9][10]

V_I

input voltage

pin configured to provide

a digital function

0

5.0

V_O

output voltage

output active

0

-

V_DD

-

V

V_IH

HIGH-level input

voltage

0.7V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

V_OH

-

0.4

-

HIGH-level output

voltage

2.0 V ≤ V_DD≤ 3.6 V;

I_OH= −4 mA

V_DD− 0.4

1.8 V ≤ V_DD< 2.0 V;

I_OH= −3 mA

V_DD− 0.4

-

V

V_OL

LOW-level output

voltage

2.0 V ≤ V_DD≤ 3.6 V;

-

0.4

-

V

I

_OL= 4 mA

1.8 V ≤ V_DD< 2.0 V;

I_OL= 3 mA

-

V

I_OH

HIGH-level output

current

V_OH= V_DD− 0.4 V;

2.0 V ≤ V_DD≤ 3.6 V

1.8 V ≤ V_DD< 2.0 V

−4

mA

−3

-

mA

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

17 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 5.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_OL

LOW-level output

current

V_OL= 0.4 V

4

-

mA

2.0 V ≤ V_DD≤ 3.6 V

1.8 V ≤ V_DD< 2.0 V

3

-

mA

[11]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

−45

LOW-level short-circuit V_OL= V_DD

output current

-

50

mA

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

V_I= 0 V;

10

50

150

μA

−15

−50

−85

2.0 V ≤ V_DD≤ 3.6 V

1.8 V ≤ V_DD< 2.0 V

−10

−50

−85

μA

V_DD< V_I< 5 V

0

External clock input

V_i(xtal)crystal input voltage

−0.5

1.8

1.95

V

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] T_amb= 25 °C.

[3] I_DDmeasurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; external clock disabled; system PLL disabled.

[5] BOD disabled.

[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration

block. Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[7] IRC disabled; system oscillator enabled; system PLL enabled.

[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[9] Including voltage on outputs in 3-state mode.

[10] V_DDsupply voltage must be present.

[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

18 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 6.

ADC static characteristics

T_amb= −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, V_DD= 2.5 V to 3.6 V.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DD

1

Unit

V

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

C_ia

pF

[1][2]

[3]

E_D

± 1

LSB

%

E_L(adj)

E_O

± 1.5

± 3.5

0.6

[4]

[5]

E_G

gain error

[6]

E_T

absolute error

± 4

LSB

kΩ

R_vsi

voltage source interface

resistance

40

[7][8]

R_i

input resistance

-

2.5

MΩ

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 5.

[3] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 5.

[4] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 5.

[5] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 5.

[6] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 5.

[7] T_amb= 25 °C; maximum sampling frequency f_s= 4.5 MHz and analog input capacitance C_ia= 1 pF.

[8] Input resistance R_idepends on the sampling frequency f_s: R_i= 1 / (f_s× C_ia).

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

19 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

offset

error

gain

error

E

G

O

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

offset error

E

O

V

− V

DD SS

1024

1 LSB =

002aaf426

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 5. ADC characteristics

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

20 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

9.1 BOD static characteristics

Table 7.

BOD static characteristics^[1]

T_amb= 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 0

assertion

-

1.65

1.80

-

V

de-assertion

interrupt level 1

assertion

-

2.22

2.35

-

V

de-assertion

interrupt level 2

assertion

-

2.52

2.66

-

V

de-assertion

interrupt level 3

assertion

-

2.80

2.90

-

V

de-assertion

reset level 0

assertion

-

1.46

1.63

-

V

de-assertion

reset level 1

assertion

-

2.06

2.15

-

V

de-assertion

reset level 2

assertion

-

2.35

2.43

-

V

de-assertion

reset level 3

assertion

-

2.63

2.71

-

V

de-assertion

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC1102

user manual.

9.2 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the

following conditions (see LPC1102 user manual):

• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

• Configure GPIO pins as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

21 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

002aaf980

10

I

DD

(mA)

8

6

4

2

0

(2)

48 MHz

(2)

36 MHz

(2)

24 MHz

(1)

12 MHz

1.8

2.4

3.0

3.6

V

DD

(V)

Conditions: T_amb= 25 °C; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

(1) System PLL disabled; IRC enabled.

(2) System PLL enabled; IRC disabled.

Fig 6. Active mode: Typical supply current I_DDversus supply voltage V_DDfor different

system clock frequencies

002aaf981

10

I

DD

(mA)

8

6

4

2

0

(2)

48 MHz

36 MHz

(2)

(1)

24 MHz

12 MHz

−40

−15

10

35

60

85

temperature (°C)

Conditions: V_DD= 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

(1) System PLL disabled; IRC enabled.

(2) System PLL enabled; IRC disabled.

Fig 7. Active mode: Typical supply current I_DDversus temperature for different system

clock frequencies

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

22 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

002aaf982

6

4

2

0

I

DD

(mA)

(2)

48 MHz

(2)

36 MHz

(2)

24 MHz

(1)

12 MHz

−40

−15

10

35

60

85

temperature (°C)

Conditions: V_DD= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

(1) System PLL disabled; IRC enabled.

(2) System PLL enabled; IRC disabled.

Fig 8. Sleep mode: Typical supply current I_DDversus temperature for different system

clock frequencies

002aaf977

5.5

I

DD

(μA)

4.5

3.5

2.5

1.5

V

DD

= 3.3 V, 3.6 V

1.8 V

−40

−15

10

35

60

85

temperature (°C)

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 9. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

23 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

9.3 Electrical pin characteristics

002aae991

15

I

OL

T = 85 °C

25 °C

−40 °C

(mA)

10

5

0

0.2

0.4

0.6

V

OL

(V)

Conditions: V_DD= 3.3 V; standard port pins.

Fig 10. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

002aae992

3.6

V

OH

(V)

T = 85 °C

25 °C

−40 °C

3.2

2.8

2.4

2

0

8

16

24

I

(mA)

OH

Conditions: V_DD= 3.3 V; standard port pins.

Fig 11. Typical HIGH-level output voltage V_OHversus HIGH-level output source current

I_OH

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

24 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

002aae988

10

I

pu

(μA)

−10

−30

−50

−70

T = 85 °C

25 °C

−40 °C

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 3.3 V; standard port pins.

Fig 12. Typical pull-up current I_puversus input voltage V_I

002aae989

80

T = 85 °C

I

pd

25 °C

(μA)

−40 °C

60

40

20

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 3.3 V; standard port pins.

Fig 13. Typical pull-down current I_pdversus input voltage V_I

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

25 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

10. Dynamic characteristics

10.1 Power-up ramp conditions

Table 8.

Power-up characteristics

T_amb= −40 °C to +85 °C.

Symbol Parameter

Conditions

Min

0

Typ

Max

500

-

Unit

ms

μs

[1]

t_r

rise time

at t = t₁: 0 < V_I≤ 400 mV

-

[1][2]

t_wait

V_I

wait time

12

0

input voltage

at t = t₁on pin V_DD

400

mV

[1] See Figure 14.

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

t

r

V

DD

400 mV

0

t

wait

t = t

1

002aag001

Condition: 0 < V_I≤ 400 mV at start of power-up (t = t₁)

Fig 14. Power-up ramp

10.2 Flash memory

Table 9.

Flash characteristics

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

N_endu

t_ret

Parameter

endurance

Conditions

Min

10000

10

Typ

Max

Unit

[1]

100000

-

cycles

years

ms

retention time

powered

-

unpowered

20

-

t_er

erase time

sector or multiple

consecutive

sectors

95

100

105

[2]

t_prog

programming

time

0.95

1

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

26 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

10.3 External clock

Table 10. Dynamic characteristic: external clock

T_amb= −40 °C to +85 °C; V_DDover specified ranges.^[1]

Symbol

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk)× 0.4

-

ns

T_cy(clk)× 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 15. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

27 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

10.4 Internal oscillators

Table 11. Dynamic characteristic: internal oscillators

T_amb= −40 °C to +85 °C; 2.7 V ≤ V_DD≤ 3.6 V.^[1]

Symbol Parameter

Conditions

Min

Typ^[2]

Max

Unit

f_osc(RC)internal RC oscillator frequency -

11.88

12

12.12

MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

002aaf403

12.15

f

(MHz)

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

12.05

2.4 V

2.0 V

11.95

11.85

−40

−15

10

35

60

85

temperature (°C)

Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for

2.7 V ≤ V_DD≤ 3.6 V and T_amb= −40 °C to +85 °C. Variations between parts may cause the IRC to

fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.

Fig 16. Internal RC oscillator frequency versus temperature

Table 12. Dynamic characteristics: Watchdog oscillator

Symbol Parameter

Conditions

Min Typ^[1]

Max Unit

[2][3]

f_osc(int)internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1

-

7.8

-

kHz

frequency

in the WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register

-

1700

-

kHz

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (T_amb= −40 °C to +85 °C) is ±40 %.

[3] See the LPC1102 user manual.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

28 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

10.5 I/O pins

Table 13. Dynamic characteristic: I/O pins^[1]

T_amb= −40 °C to +85 °C; 3.0 V ≤ V_DD≤ 3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_r

rise time

3.0

-

5.0

ns

configured as

output

t_f

fall time

2.5

-

5.0

ns

configured as

output

[1] Applies to standard port pins and RESET pin.

10.6 SPI interfaces

Table 14. Dynamic characteristics of SPI pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SPI master (in SPI mode)

[1]

[2]

T_cy(clk)

clock cycle time

data set-up time

when only receiving

when only transmitting

in SPI mode

40

-

ns

27.8

15

t_DS

2.4 V ≤ V_DD≤ 3.6 V

2.0 V ≤ V_DD< 2.4 V

1.8 V ≤ V_DD< 2.0 V

in SPI mode

[2]

20

24

0

ns

-

t_DH

data hold time

-

t_v(Q)

t_h(Q)

data output valid time in SPI mode

data output hold time in SPI mode

-

10

-

0

SPI slave (in SPI mode)

T_cy(PCLK)PCLK cycle time

20

0

-

ns

[3][4]

t_DS

data set-up time

data hold time

in SPI mode

t_DH

3 × T_cy(PCLK)+ 4

t_v(Q)

t_h(Q)

data output valid time in SPI mode

data output hold time in SPI mode

-

3 × T_cy(PCLK)+ 11

2 × T_cy(PCLK)+ 5

[1] T_cy(clk)= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f_main. The clock cycle time derived from the SPI bit rate T_cy(clk)is a function of the

main clock frequency f_main, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2]

[3] T_cy(clk)= 12 × T_cy(PCLK)

[4] T_amb= 25 °C; for normal voltage supply range: V_DD= 3.3 V.

T_amb= −40 °C to 85 °C.

.

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

29 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

T

t

clk(L)

cy(clk)

clk(H)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

h(Q)

v(Q)

DATA VALID

CPHA = 1

t

DH

DS

DATA VALID

MISO

t

h(Q)

v(Q)

DATA VALID

t

MOSI

MISO

t

CPHA = 0

DS

DH

DATA VALID

002aae829

Fig 17. SPI master timing in SPI mode

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

30 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

T

t

clk(L)

cy(clk)

clk(H)

SCK (CPOL = 0)

SCK (CPOL = 1)

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

v(Q)

CPHA = 1

DATA VALID

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

CPHA = 0

v(Q)

DATA VALID

002aae830

Fig 18. SPI slave timing in SPI mode

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

31 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

11. Application information

11.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 6:

• The ADC input trace must be short and as close as possible to the LPC1102 chip.

• The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lines.

• Because the ADC and the digital core share the same power supply, the power supply

line must be adequately filtered.

• To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave

mode, a minimum of 200 mV (RMS) is needed.

LPC1xxx

XTALIN

C

i

C

g

100 pF

002aae788

Fig 19. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(Figure 19), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

11.3 Standard I/O pad configuration

Figure 20 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Analog input

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

32 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

V

DD

ESD

output enable

pin configured

as digital output

driver

output

ESD

V

DD

V

SS

weak

pull-up

pull-up enable

weak

pull-down

repeater mode

enable

pin configured

as digital input

pull-down enable

data input

select analog input

pin configured

as analog input

analog input

002aaf304

Fig 20. Standard I/O pad configuration

11.4 Reset pad configuration

V

DD

V

DD

V

DD

R

pu

ESD

20 ns RC

GLITCH FILTER

reset

ESD

V

SS

002aaf274

Fig 21. Reset pad configuration

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

33 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

12. Package outline

WLCSP16: wafer level chip-size package; 16 bumps; body 2.17 x 2.32 x 0.6 mm

LPC1102UK

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

1/2 e

b

C

∅ v

∅ w

C

A

B

e

y

D

e

C

B

A

1/2 e

e

2

ball A1

index area

1

2

3

4

X

0

1

2 mm

scale

Dimensions

Unit

A

1

A

2

b

D

E

e

1

e

2

v

w

y

max 0.65 0.27 0.38 0.35 2.21 2.36

mm nom 0.60 0.24 0.36 0.32 2.17 2.32 0.5 1.5 1.5 0.15 0.05 0.05

min 0.55 0.21 0.34 0.29 2.13 2.28

lpc1102uk_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

- - -

JEITA

- - -

10-10-15

10-10-18

LPC1102UK

Fig 22. Package outline LPC1102UK (WLCSP16)

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

34 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

13. Abbreviations

Table 15. Abbreviations

Acronym

ADC

AHB

APB

BOD

GPIO

PLL

Description

Analog-to-Digital Converter

Advanced High-performance Bus

Advanced Peripheral Bus

BrownOut Detection

General Purpose Input/Output

Phase-Locked Loop

RC

Resistor-Capacitor

SPI

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

SSI

SSP

UART

Universal Asynchronous Receiver/Transmitter

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

35 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

14. Revision history

Table 16. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC1102 v.3

20110418

Product data sheet

-

LPC1102 v.2

Modifications:

• Changed data sheet status to Product.

• Power consumption data added (see Figure 6 to Figure 9).

• Section 10.1 “Power-up ramp conditions” added.

• RESET pad description updated (5 V tolerant) in Table 3.

• IRC frequency data added (see Figure 16 “Internal RC oscillator frequency versus

temperature”.

• Clock output removed from feature list.

LPC1102 v.2

Modifications:

LPC1102 v.1

20101126

Preliminary data sheet -

LPC1102 v.1

-

• Changed data sheet status to Preliminary.

20101116

Objective data sheet

-

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

36 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

37 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC1102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 April 2011

38 of 39

LPC1102

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

17. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.15.5

7.15.6

7.15.7

7.16

APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 15

AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

External interrupt inputs. . . . . . . . . . . . . . . . . 15

Emulation and debugging . . . . . . . . . . . . . . . 15

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

4

4.1

5

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 16

9

Static characteristics . . . . . . . . . . . . . . . . . . . 17

BOD static characteristics . . . . . . . . . . . . . . . 21

Power consumption . . . . . . . . . . . . . . . . . . . 21

Electrical pin characteristics. . . . . . . . . . . . . . 24

9.1

9.2

9.3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

10

Dynamic characteristics. . . . . . . . . . . . . . . . . 26

Power-up ramp conditions . . . . . . . . . . . . . . . 26

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 26

External clock. . . . . . . . . . . . . . . . . . . . . . . . . 27

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 28

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 29

7

7.1

7.2

7.3

7.4

7.5

7.5.1

7.5.2

7.6

7.7

7.7.1

7.8

7.8.1

7.9

7.9.1

7.10

7.10.1

7.11

Functional description . . . . . . . . . . . . . . . . . . . 6

ARM Cortex-M0 processor. . . . . . . . . . . . . . . . 6

On-chip flash program memory . . . . . . . . . . . . 6

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 6

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Nested Vectored Interrupt Controller (NVIC) . . 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . 8

IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . . 8

Fast general purpose parallel I/O . . . . . . . . . . . 8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SPI serial I/O controller. . . . . . . . . . . . . . . . . . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

General purpose external event

10.1

10.2

10.3

10.4

10.5

10.6

11

Application information . . . . . . . . . . . . . . . . . 32

ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 32

XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Standard I/O pad configuration . . . . . . . . . . . 32

Reset pad configuration. . . . . . . . . . . . . . . . . 33

11.1

11.2

11.3

11.4

12

13

14

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision history . . . . . . . . . . . . . . . . . . . . . . . 36

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 37

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38

15.1

15.2

15.3

15.4

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

System tick timer . . . . . . . . . . . . . . . . . . . . . . 10

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clocking and power control . . . . . . . . . . . . . . 11

Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 11

7.11.1

7.12

7.13

7.13.1

7.14

7.14.1

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 38

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.14.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 12

7.14.1.2 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 12

7.14.2

7.14.3

7.14.4

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 13

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.14.4.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 13

7.14.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.14.4.3 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 13

7.15

System control . . . . . . . . . . . . . . . . . . . . . . . . 14

Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Brownout detection. . . . . . . . . . . . . . . . . . . . . 14

Code security (Code Read Protection - CRP) 14

7.15.1

7.15.2

7.15.3

7.15.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 April 2011

Document identifier: LPC1102


型号：	LPC1102UK
厂家：	NXP
描述：	32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM 32位ARM Cortex -M0微控制器; 32 KB的闪存和8 KB的SRAM 闪存微控制器静态存储器
文件：	总39页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC1102UK [NXP]

相关型号：

LPC1102_11

LPC1102_1106

LPC1104

LPC110CTP

LPC1110

LPC1110FD20

LPC1110FD20,529

LPC1111

LPC1111FDH20/002

LPC1111FHN33/101

LPC1111FHN33/101,5

LPC1111FHN33/102