LPC1114LVFHN24/103 [NXP]
32-bit ARM Cortex-M0 MCU; up to 32 kB flash, 8 kB SRAM; 8-bit ADC;
| 型号： | LPC1114LVFHN24/103 |
| 厂家： | 
NXP |
| 描述： | 32-bit ARM Cortex-M0 MCU; up to 32 kB flash, 8 kB SRAM; 8-bit ADC 静态存储器 |
| 文件： | 总53页 (文件大小：1354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPC111xLV/LPC11xxLVUK
32-bit ARM Cortex-M0 MCU; up to 32 kB flash, 8 kB SRAM;
8-bit ADC
Rev. 2 — 10 October 2012
Product data sheet
1. General description
The LPC111xLV/LPC11xxLVUK is an ARM Cortex-M0-based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC111xLV/LPC11xxLVUK operate at CPU frequencies of up to 50 MHz.
The peripherals of the LPC111xLV/LPC11xxLVUK include up to 32 kB of flash memory, up
to 8 kB of SRAM data memory, a Fast-mode Plus I2C-bus interface, one SSP/SPI
interface, one UART, four general-purpose counter/timers, an 8-bit ADC, and up to 27
general-purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug.
System tick timer.
Memory:
Up to 32 kB on-chip flash programming memory with a 256 byte page erase
function.
Up to 8 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Digital peripherals:
Up to 27 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors and a configurable open-drain mode.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current output driver on one pin.
High-current sink drivers on two I2C-bus pins in Fast-mode Plus.
Four general-purpose counter/timers with up to 7 capture inputs and 13 match
outputs.
Programmable windowed WDT.
Analog peripherals:
8-bit ADC with input multiplexing among up to 8 pins.
Serial interfaces:
LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
UART with fractional baud rate generation and internal FIFO.
One SPI controller with SSP features and with FIFO and multi-protocol capabilities.
I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
12 MHz internal RC oscillator trimmed to 2.5 % accuracy for Tamb = -20 °C to
+85 °C and to 5 % accuracy for Tamb = -40 °C to -20 °C. The IRC can optionally be
used as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, and the Watchdog clock.
Power control:
Two reduced power modes: Sleep and Deep-sleep mode.
Ultra-low power consumption in Deep-sleep mode ( 1.6 A).
5 s wake-up time from Deep-sleep mode.
Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
13 of the functional pins.
Power-On Reset (POR).
Brown-Out Detection (BOD) causing a forced reset.
Unique device serial number for identification.
Single power supply (1.65 V to 1.95 V)
Available as WLCSP25, HVQFN24, and HVQFN33 package. Other package options
are available for high-volume customers.
3. Applications
Mobile phones
Tablets/Ultra books
Active cables
Mobile accessories
Cameras
Portable medical electronics
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC1101LVUK
WLCSP25
WLCSP25
HVQFN24
wafer level chip-size package; 25 bumps; 2.17 2.32 0.56 mm
wafer level chip-size package; 25 bumps; 2.17 2.32 0.56 mm
-
LPC1102LVUK
-
LPC1112LVFHN24/003
plastic thermal enhanced very thin quad flat package; no leads; 24
terminals; body 4 x 4 x 0.85 mm
SOT616-3
LPC1114LVFHN24/103
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads; 24
terminals; body 4 x 4 x 0.85 mm
SOT616-3
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
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LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 1.
Ordering information …continued
Type number
Package
Name
Description
Version
LPC1114LVFHN24/303
LPC1112LVFHI33/103
LPC1114LVFHI33/303
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads; 24
terminals; body 4 x 4 x 0.85 mm
SOT616-3
HVQFN33
HVQFN33
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5 5 0.85 mm
n/a
plastic thermal enhanced very thin quad flat package; no leads; 33
n/a
terminals; body 5 5 0.85 mm
4.1 Ordering options
Table 2.
Ordering options
Type number
Flash Total
SPI/ I2C UART ADC
GPI Package
in kB SRAM in SSP
kB
O
pins
LPC1101LVUK
LPC1102LVUK
32
32
2
8
2
4
8
4
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6-channel
6-channel
6-channel
6-channel
6-channel
8-channel
8-channel
21
21
20
20
20
27
27
WLCSP25
WLCSP25
HVQFN24
HVQFN24
HVQFN24
HVQFN33
HVQFN33
LPC1112LVFHN24/003 16
LPC1114LVFHN24/103 32
LPC1114LVFHN24/303 32
LPC1112LVFHI33/103 16
LPC1114LVFHI33/303 32
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
3 of 53
LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
XTALIN
XTALOUT
RESET
SWD
LPC110xLVUK
LPC111xLV
IRC
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
CLKOUT
TEST/DEBUG
INTERFACE
POR
FUNCTIONS
ARM
CORTEX-M0
clocks and
controls
FLASH
16/32 kB
SRAM
2/4/8 kB
ROM
system bus
slave
slave
slave
slave
HIGH-SPEED
GPIO
AHB-LITE BUS
GPIO ports
slave
AHB TO APB
BRIDGE
RXD
TXD
(2)
UART
AD[7:0]
10-bit/8-bit ADC
SPI0
(3)
(3)
DSR , RTS,
(3)
CTS , DTR
SCK0, SSEL0
MISO0, MOSI0
CT32B0_MAT[3:0]
CT32B0_CAP0
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
(1)
CT32B1_CAP[1:0]
SCL
SDA
2
I C-BUS
CT16B0_MAT[2:0]
(1)
CT16B0_CAP[1:0]
(1)
CT16B1_MAT[1:0]
WWDT
IOCON
(1)
CT16B1_CAP[1:0]
SYSTEM CONTROL
002aag851
(1) CT16B1_MAT1, CT32B1_CAP1, CT1B0_CAP1, CT16B1_CAP1 available on HVQFN33 only. CT16B1_MAT0 available on
HVQFN33 and WLCSP25 packages only.
(2) 6 channels on WLCSP25 and HVQFN24 packages. 8 channels on HVQFN33 packages.
(3) DSR on WLCSP25 package only. DTR on HVQFN33 package only. CTS on HVQFN24 and HVQFN33 packages only.
Fig 1. LPC111xLV/LPC11xxLVUK block diagram
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
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LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
ball A1
index area
LPC1101/02LVUK
1
2
3
4
5
A
B
C
D
E
002aag852
Transparent top view
Fig 2. Pin configuration WLCSP25 package
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
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LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
terminal 1
index area
1
2
3
4
5
6
18
17
16
15
14
13
PIO1_7/TXD/CT32B0_MAT1
RESET/PIO0_0
R/PIO1_2/AD3/CT32B1_MAT1
R/PIO1_1/AD2/CT32B1_MAT0
R/PIO1_0/AD1/CT32B1_CAP0
R/PIO0_11/AD0/CT32B0_MAT3
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_1/CLKOUT/CT32B0_MAT2
XTALIN
XTALOUT
PIO1_8/CT16B1_CAP0
002aag849
Transparent top view
For parts LPC1112LVFHN24/003, LPC1114LVFHN24/103, LPC1114LVFHN24/303.
Fig 3. Pin configuration HVQFN24 package
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
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LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
terminal 1
index area
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIO2_0/DTR
R/PIO1_2/AD3/CT32B1_MAT1
R/PIO1_1/AD2/CT32B1_MAT0
R/PIO1_0/AD1/CT32B1_CAP0
R/PIO0_11/AD0/CT32B0_MAT3
PIO1_10/AD6/CT16B1_MAT1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_8/MISO0/CT16B0_MAT0
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2
XTALIN
XTALOUT
V
DD(IO)
33 V
PIO1_8/CT16B1_CAP0
SS
PIO0_2/SSEL0/CT16B0_CAP0
002aag850
Transparent top view
For parts LPC1112LVFHI33/103 and LPC1114LVFHI33/303.
Fig 4. Pin configuration HVQFN33 package
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
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LPC111xLV/LPC11xxLVUK
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32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3.
Symbol
LPC110xLVUK/LPC111xLV pin description table
Start Type Reset Description
logic
input
state
[1]
[2]
RESET/PIO0_0
D1
2
2
yes
I
I; PU RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets
the device, causing I/O ports and peripherals to take on
their default states, and processor execution to begin at
address 0.
I/O
I/O
-
PIO0_0 — General purpose digital input/output pin with
10 ns glitch filter.
[3]
[3]
PIO0_1/CLKOUT/
CT32B0_MAT2
C3
B2
3
7
3
8
yes
yes
I; PU PIO0_1 — General purpose digital input/output pin. A
LOW level on this pin during reset starts the ISP
command handler.
O
-
-
CLKOUT — Clockout pin.
O
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0
I/O
I/O
I
I; PU PIO0_2 — General purpose digital input/output pin.
-
-
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
[3]
[4]
PIO0_3
-
-
9
yes
yes
I/O
I/O
I;PU PIO0_3 — General purpose digital input/output pin.
PIO0_4/SCL
A2
8
10
I; IA
PIO0_4 — General purpose digital input/output pin
(open-drain).
I/O
-
SCL — I2C-bus, open-drain clock input/output.
High-current sink only if I2C Fast-mode Plus is selected
in the I/O configuration register.
[4]
PIO0_5/SDA
A3
9
11
yes
I/O
I/O
I; IA
-
PIO0_5 — General purpose digital input/output pin
(open-drain).
SDA — I2C-bus, open-drain data input/output.
High-current sink only if I2C Fast-mode Plus is selected
in the I/O configuration register.
[3]
[3]
PIO0_6/SCK0
PIO0_7/CTS
A4
-
10 15
11 16
yes
yes
I/O
I/O
I/O
I; PU PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
-
I; PU PIO0_7 — General purpose digital input/output pin
(high-current output driver).
I
-
CTS — Clear To Send input for UART.
[3]
[3]
PIO0_8/MISO0/
CT16B0_MAT0
A5
B5
12 17
13 18
yes
yes
I/O
I/O
O
I; PU PIO0_8 — General purpose digital input/output pin.
-
-
MISO0 — Master In Slave Out for SPI0.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1
I/O
I/O
O
I; PU PIO0_9 — General purpose digital input/output pin.
-
-
MOSI0 — Master Out Slave In for SPI0.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
8 of 53
LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
LPC110xLVUK/LPC111xLV pin description table
Start Type Reset Description
logic
input
state
[1]
[3]
[5]
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
B4
C5
14 19
yes
yes
I
I; PU SWCLK — Serial wire clock.
I/O
I/O
O
I
-
-
-
PIO0_10 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
15 21
I; PU R — Reserved. Configure for an alternate function in
AD0/CT32B0_MAT3
the IOCON block.
I/O
-
-
-
PIO0_11 — General purpose digital input/output pin.
AD0 — A/D converter, input 0.
I
O
I
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
[5]
[5]
[5]
R/PIO1_0/
AD1/CT32B1_CAP0
C4
D5
D4
16 22
17 23
18 24
yes
no
I; PU R — Reserved. Configure for an alternate function in
the IOCON block.
I/O
-
-
-
PIO1_0 — General purpose digital input/output pin.
AD1 — A/D converter, input 1.
I
I
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0
O
I; PU R — Reserved. Configure for an alternate function in
the IOCON block.
I/O
-
-
-
PIO1_1 — General purpose digital input/output pin.
AD2 — A/D converter, input 2.
I
O
I
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
no
I; PU R — Reserved. Configure for an alternate function in
AD3/CT32B1_MAT1
the IOCON block.
I/O
I
-
-
-
PIO1_2 — General purpose digital input/output pin.
AD3 — A/D converter, input 3.
O
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
[5]
[5]
SWDIO/PIO1_3/
AD4/CT32B1_MAT2
E5
D3
19 25
no
no
I/O
I/O
I
I; PU SWDIO — Serial wire debug input/output.
-
-
-
PIO1_3 — General purpose digital input/output pin.
AD4 — A/D converter, input 4.
O
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
20 26
I/O
I; PU PIO1_4 — General purpose digital input/output pin with
CT32B1_MAT3
10 ns glitch filter.
I
-
-
AD5 — A/D converter, input 5.
O
I/O
O
I
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
[3]
[3]
PIO1_5/RTS/
CT32B0_CAP0
E2
D2
23 30
24 31
no
no
I; PU PIO1_5 — General purpose digital input/output pin.
-
-
RTS — Request To Send output for UART.
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0
I/O
I
I; PU PIO1_6 — General purpose digital input/output pin.
-
-
RXD — Receiver input for UART.
O
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
9 of 53
LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
LPC110xLVUK/LPC111xLV pin description table
Start Type Reset Description
logic
input
state
[1]
[3]
PIO1_7/TXD/
CT32B0_MAT1
E1
1
32
no
I/O
O
O
I/O
I
I; PU PIO1_7 — General purpose digital input/output pin.
-
-
TXD — Transmitter output for UART.
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
[3]
[3]
[5]
PIO1_8/
CT16B1_CAP0
B1
B3
-
6
-
7
no
no
no
I; PU PIO1_8 — General purpose digital input/output pin.
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
I; PU PIO1_9 — General purpose digital input/output pin.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I;PU PIO1_10 — General purpose digital input/output pin.
-
PIO1_9/
CT16B1_MAT0
12
20
I/O
O
I/O
I
-
PIO1_10/AD6/
CT16B1_MAT1
-
-
-
AD6 — A/D converter, input 6.
O
I/O
I
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
[5]
PIO1_11/AD7/
CT32B0_MAT3
-
-
27
no
I;PU PIO1_11 — General purpose digital input/output pin.
-
-
AD7 — A/D converter, input 7.
O
I/O
O
I/O
I
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
[3]
[3]
[3]
PIO2_0/DTR
PIO2_1/DSR
-
-
-
-
1
no
no
no
I;PU PIO2_0 — General purpose digital input/output pin.
DTR — Data Terminal Ready output for UART.
I; PU PIO2_1 — General purpose digital input/output pin.
DSR — Data Set Ready input for UART.
I;PU PIO3_4 — General purpose digital input/output pin.
-
A1
-
-
-
PIO3_4/
CT16B0_CAP1/RXD
13
I/O
I
-
-
CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.
RXD — Receiver input for UART.
I
[3]
PIO3_5/
CT16B1_CAP1/TXD
-
-
14
no
I/O
I
I;PU PIO3_5 — General purpose digital input/output pin.
-
-
-
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
TXD — Transmitter output for UART.
O
-
VDD
E3
C1
22 29;
-
-
1.8 V supply voltage to the core, the external rail, and
the ADC. Also used as the ADC reference voltage.
6;
28
[6]
[6]
XTALIN
4
5
4
I
-
Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed 1.8 V.
XTALOUT
VSS
C2
E4
5
-
-
O
-
-
-
Output from the oscillator amplifier.
Ground.
21 33
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level 0; IA = inactive,
no pull-up/down enabled.
[2] See Figure 28 for the reset pad configuration.
[3] Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 27).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.
[5] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When
configured as an ADC input, digital section of the pad is disabled (see Figure 27).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
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LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7. Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.2 On-chip flash program memory
The LPC111xLV/LPC11xxLVUK contains up to 32 kB of on-chip flash memory.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages of 256 byte each can be erased using the IAP erase page command.
7.3 On-chip SRAM
The LPC111xLV/LPC11xxLVUK contains up to 8 kB on-chip static RAM memory.
7.4 Memory map
The LPC111xLV/LPC11xxLVUK incorporates several distinct memory regions, shown in
the following figures. Figure 5 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128
peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
LPC111XLV_LPC11XXLVUK
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
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LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LPC110xLVUK
LPC111xLV
AHB peripherals
0x5020 0000
4 GB
0xFFFF FFFF
reserved
0xE010 0000
0xE000 0000
127-16 reserved
private peripheral bus
0x5004 0000
0x5003 0000
0x5002 0000
GPIO PIO3
GPIO PIO2
GPIO PIO1
GPIO PIO0
15-12
11-8
7-4
reserved
0x5020 0000
0x5000 0000
AHB peripherals
0x5001 0000
0x5000 0000
3-0
reserved
APB peripherals
0x4008 0000
31-23 reserved
reserved
0x4005 C000
0x4005 8000
0x4008 0000
0x4000 0000
22
APB peripherals
reserved
1 GB
21-19 reserved
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
system control
IOCON
18
17
0x2000 0000
0.5 GB
SPI0
16
15
flash controller
0x4003 C000
0x4003 8000
reserved
14
reserved
0x1FFF 4000
0x1FFF 0000
16 kB boot ROM
reserved
13-10 reserved
0x4002 8000
0x4002 4000
0x4002 0000
reserved
reserved
9
8
7
6
5
4
3
2
0x1000 2000
0x1000 1000
8 kB SRAM
LPC1114LV/303, LPC1102LVUK
ADC
0x4001 C000
0x4001 8000
32-bit counter/timer 1
4 kB SRAM
LPC1114LV/103, LPC1112LV/103
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
UART
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x1000 0800
0x1000 0000
0x0000 8000
2 kB SRAM
LPC1101LVUK, LPC1112LV/003
reserved
WDT
1
0
0x4000 4000
0x4000 0000
32 kB on-chip flash
LPC1101LVUK, LPC1102LVUK
LPC1114LV
2
I C-bus
0x0000 4000
0x0000 0000
0x0000 00C0
16 kB on-chip flash
LPC1112LV
active interrupt vectors
0x0000 0000
0 GB
002aag853
Fig 5. LPC111xLV/LPC11xxLVUK memory map
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
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• In the LPC111xLV/LPC11xxLVUK, the NVIC supports 32 vectored interrupts including
up to 13 inputs to the start logic from individual GPIO pins.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 18 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
7.6 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.7 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC111xLV/LPC11xxLVUK use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of up to 18 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.7.1 Features
• Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
• Direction control of individual bits.
• All I/O default to inputs with pull-ups enabled after reset with the exception of the
I2C-bus pins PIO0_4 and PIO0_5.
• Pull-up/pull-down resistor configuration can be programmed through the IOCON block
for each GPIO pin (except for pins PIO0_4 and PIO0_5).
• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 1.8 V (VDD = 1.8 V) if their
pull-up resistor is enabled in the IOCON block (single power supply).
• Programmable open-drain mode.
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7.8 UART
32-bit ARM Cortex-M0 microcontroller
The LPC111xLV/LPC11xxLVUK contains one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.8.1 Features
• Maximum UART data bit rate of 3.125 MBit/s.
• 16 Byte Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• FIFO control mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
7.9 SPI serial I/O controller
The LPC111xLV/LPC11xxLVUK contains one SPI controller.
The SPI controller is capable of operation on an SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SPI supports
full-duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.9.1 Features
• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.10 I2C-bus serial I/O controller
The LPC111xLV/LPC11xxLVUK contains one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
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capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.10.1 Features
• The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The
I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.11 ADC
The LPC111xLV/LPC11xxLVUK contains one ADC. It is a single 8-bit successive
approximation ADC with up to eight channels.
Remark: ADC specifications are valid for Tamb = -40 °C to +85 °C on HVQFN33 and
WLCSP25 packages. ADC specifications are valid for Tamb = -10 °C to 85 °C on the
HVQFN24 package.
7.11.1 Features
• 8-bit successive approximation ADC.
• Input multiplexing among 6 pins (WLCSP25 and HVQFN24 packages).
• Input multiplexing among 8 pins (HVQFN33 packages).
• Power-down mode.
• Measurement range 0 V to VDD
.
• 8-bit sampling rate of up to 10 kSamples/s.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
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7.12 General purpose external event counter/timers
The LPC111xLV/LPC11xxLVUK includes two 32-bit counter/timers and two 16-bit
counter/timers. The counter/timer is designed to count cycles of the system derived clock.
It can optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. Each counter/timer also includes one capture input to trap
the timer value when an input signal transitions, optionally generating an interrupt.
7.12.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
7.13 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.14 Windowed WatchDog Timer
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.14.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
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• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). This gives a wide range of potential timing choices of
watchdog operation under different power conditions.
7.15 Clocking and power control
7.15.1 Crystal oscillators
The LPC111xLV/LPC11xxLVUK include three independent oscillators. These are the
system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each
oscillator can be used for more than one purpose as required in a particular application.
Following reset, the LPC111xLV/LPC11xxLVUK will operate from the Internal RC oscillator
until switched by software. This allows systems to operate without any external crystal and
the bootloader code to operate at a known frequency.
See Figure 6 for an overview of the LPC111xLV/LPC11xxLVUK clock generation.
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AHB clock 0
(system)
system clock
SYSTEM CLOCK
DIVIDER
18
AHB clocks 1 to 18
(memories
and peripherals)
SYSAHBCLKCTRL[1:18]
(AHB clock enable)
SPI0 PERIPHERAL
SPI0
CLOCK DIVIDER
IRC oscillator
main clock
UART PERIPHERAL
UART
CLOCK DIVIDER
watchdog oscillator
MAINCLKSEL
(main clock select)
IRC oscillator
SYSTEM PLL
system oscillator
IRC oscillator
WWDT CLOCK
WDT
DIVIDER
SYSPLLCLKSEL
(system PLL clock select)
watchdog oscillator
WDTUEN
(WDT clock update enable)
IRC oscillator
system oscillator
watchdog oscillator
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
CLKOUTUEN
(CLKOUT update enable)
002aag859
Fig 6. LPC111xLV/LPC11xxLVUK clock generation block diagram
7.15.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 2.5 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC111xLV/LPC11xxLVUK use the IRC as the clock
source. Software may later switch to one of the other available clock sources.
7.15.1.2 System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
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7.15.1.3 Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and
temperature is 40 %.
7.15.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The PLL
output frequency must be lower than 100 MHz. The output divider may be set to divide by
2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 s.
7.15.3 Clock output
The LPC111xLV/LPC11xxLVUK features a clock output function that routes the IRC
oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.15.4 Wake-up process
The LPC111xLV/LPC11xxLVUK begin operation at power-up by using the 12 MHz IRC
oscillator as the clock source. This allows chip operation to resume quickly. If the system
oscillator or the PLL is needed by the application, software will need to enable these
features and wait for them to stabilize before they are used as a clock source.
7.15.5 Power control
The LPC111xLV/LPC11xxLVUK support a variety of power control features. There are two
special modes of processor power reduction: Sleep mode, and Deep-sleep mode. The
CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a
trade-off of power versus processing speed based on application requirements. In
addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine-tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
7.15.5.1 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
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7.15.5.2 Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the IRC, the BOD, and the
watchdog timer/watchdog oscillator running for self-timed wake-up. Deep-sleep mode
allows for additional power savings.
Up to 13 pins can serve as external wake-up pins to the start logic to wake up the chip
from Deep-sleep mode.
Unless the watchdog oscillator or the IRC are selected to run in Deep-sleep mode, the
clock source should be switched to IRC before entering Deep-sleep mode, because the
IRC can be switched on and off glitch-free.
7.16 System control
7.16.1 Start logic
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin
shown in Table 3 as input to the start logic is connected to an individual interrupt in the
NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when
the chip is in Active mode. In addition, an input signal on the start logic pins can wake up
the chip from Deep-sleep mode when all clocks are shut down.
The start logic must be configured in the system configuration block and in the NVIC
before being used.
7.16.2 Reset
Reset has four sources on the LPC111xLV/LPC11xxLVUK: the RESET pin, the Watchdog
reset, the BrownOut Detection (BOD) circuit, and Power-On Reset (POR). The RESET
pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating
voltage attains a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.16.3 BrownOut Detection (BOD)
The LPC111xLV/LPC11xxLVUK includes a BOD circuit which monitors the voltage level
on the VDD pin. If this voltage falls below a fixed level (see Table 8), the BOD asserts a
chip reset.
7.16.4 Code security (Code Read Protection - CRP)
This feature of the LPC111xLV/LPC11xxLVUK allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the Serial Wire
Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed,
CRP is invoked by programming a specific pattern into a dedicated flash location. IAP
commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC111xLV user manual.
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There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled (NO_ISP mode). For details see the LPC111xLV user manual.
7.16.5 APB interface
The APB peripherals are located on one APB bus.
7.16.6 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
7.16.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see Section 7.16.1).
7.17 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
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8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter
Conditions
Min
1.65
0.5
Max
1.95
+3.0
Unit
V
VDD
VI
supply voltage (core and external rail)
[2]
input voltage
only valid when the VDD supply
voltage is present
V
1.65 V VDD < 1.8 V
VDD 1.8 V
0.5
+5.0
100
100
100
V
IDD
supply current
per supply pin
-
-
-
mA
mA
mA
ISS
ground current
I/O latch-up current
per ground pin
Ilatch
(0.5VDD) < VI < (1.5VDD);
Tj < 125 C
[3]
[4]
Tstg
storage temperature
non-operating
65
+150
150
1.5
C
C
W
Tj(max)
maximum junction temperature
-
-
Ptot(pack) total power dissipation (per package)
based on package heat transfer, not
device power consumption
VESD electrostatic discharge voltage
human body model; all pins
6500
+6500
V
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Refer to the JEDEC spec (J-STD-033B.1) for further details.
[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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9. Static characteristics
9.1 Static characteristics
Table 5.
Static characteristics (single power supply
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VDD
supply voltage (core
and external rail)
1.65
1.8
1.95
V
Power consumption
IDD
supply current
Active mode; code
while(1){}
executed from flash
system clock = 12 MHz
[2][3][4]
[5]
-
-
-
2
-
-
-
mA
mA
mA
VDD = 1.8 V
[2][3]
[5][6]
system clock = 50 MHz
VDD = 1.8 V
8
[2][3][4]
[5]
Sleep mode;
0.8
system clock = 12 MHz
VDD = 1.8 V
[2][3][7]
Deep-sleep mode;
VDD = 1.8 V
-
1.6
-
A
Standard port pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
0.5
0.5
10
10
nA
nA
IIH
HIGH-level input
current
VI = VDD; on-chip
pull-down resistor
disabled
IOZ
OFF-state output
current
VO = 0 V; VO = VDD
on-chip pull-up/down
resistors disabled
;
-
0.5
10
nA
[8][9]
VI
input voltage
pin configured to provide
a digital function;
V
DD = 1.8 V
0
-
-
-
3.0
VDD
-
V
V
V
VO
output voltage
output active
0
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
V
V
Vhys
VOH
-
0.4
-
-
-
HIGH-level output
voltage
1.65 V VDD 1.95 V;
IOH = 3 mA
VDD 0.4
VOL
IOH
LOW-level output
voltage
1.65 V VDD 1.95 V;
IOL = 3 mA
-
-
-
0.4
-
V
HIGH-level output
current
VOH = VDD 0.4 V;
1.65 V VDD 1.95 V
VOL = 0.4 V
3
mA
IOL
LOW-level output
current
3
-
-
mA
1.65 V VDD 1.95 V
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Table 5.
Static characteristics (single power supply …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
[10]
[10]
IOHS
HIGH-level short-circuit VOH = 0 V
output current
-
-
45
mA
IOLS
Ipd
LOW-level short-circuit VOL = VDD
output current
-
-
50
mA
A
A
pull-down current
VI = 1.8 V
10
3
29
13
90
(VDD = 1.8 V)
Ipu
pull-up current
VI = 0 V;
85
1.65 V VDD 1.95 V
VDD < VI < 3.0 V
0
0
0
A
High-drive output pin (PIO0_7)
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
0.5
0.5
10
10
nA
nA
IIH
HIGH-level input
current
VI = VDD; on-chip
pull-down resistor
disabled
IOZ
OFF-state output
current
VO = 0 V; VO = VDD
on-chip pull-up/down
resistors disabled
;
-
0.5
10
nA
[8][9]
VI
input voltage
pin configured to provide
a digital function;
VDD = 1.8 V
output active
0
-
-
-
3.0
VDD
-
V
V
V
VO
output voltage
0
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
V
V
Vhys
VOH
-
0.4
-
-
-
HIGH-level output
voltage
1.65 V VDD 1.95 V;
IOH = 10 mA
VDD 0.4
VOL
IOH
LOW-level output
voltage
1.65 V VDD 1.95 V;
IOL = 3 mA
-
-
-
0.4
-
V
HIGH-level output
current
VOH = VDD 0.4 V;
1.65 V VDD 1.95 V
VOL = 0.4 V
10
mA
IOL
LOW-level output
current
3
-
-
-
-
mA
mA
1.65 V VDD 1.95 V
[10]
IOLS
LOW-level short-circuit VOL = VDD
output current
50
Ipd
Ipu
pull-down current
pull-up current
VI = 1.8 V
10
29
90
A
A
VI = 0 V;
3
13
85
1.65 V VDD 1.95 V
VDD < VI < 3.0 V
0
0
0
A
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Table 5.
Static characteristics (single power supply …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
I2C-bus pins (PIO0_4 and PIO0_5)
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
Vhys
IOL
-
0.05VDD
-
-
-
V
LOW-level output
current
VOL = 0.4 V; I2C-bus pins
configured as standard
mode pins
2.5
mA
1.65 V VDD 1.95 V
IOL
LOW-level output
current
VOL = 0.4 V; I2C-bus pins
configured as Fast-mode
Plus pins
15
-
-
mA
1.65 V VDD 1.95 V;
[11]
ILI
input leakage current
VI = VDD
-
2
4
A
Oscillator pins
Vi(xtal)
crystal input voltage
crystal output voltage
0.5
0.5
1.8
1.8
1.95
1.95
V
V
Vo(xtal)
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Tamb = 25 C.
[3]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. BOD disabled
for all measurements.
[4] IRC enabled; system oscillator disabled; system PLL disabled.
[5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0 disabled in system configuration block.
[6] IRC disabled; system oscillator enabled; system PLL enabled.
[7] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.
[8] Including voltage on outputs in 3-state mode.
[9]
[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[11] To VSS
VDD supply voltage must be present.
.
9.1.1 Analog characteristics
Remark: ADC specifications are valid for Tamb = -40 °C to +85 °C on HVQFN33 and
WLCSP25 packages. ADC specifications are valid for Tamb = -10 °C to +85 °C on the
HVQFN24 package.
Table 6.
8-bit ADC static characteristics
Tamb = 40 C to +85 C for HVQFN33 and WLCSP25 packages. Tamb = 10 C to +85 C for the
HVQFN24 package. VDD = 1.8 V 5 %; 8-bit resolution.
Symbol
VIA
Parameter
Min
Typ
Max
VDD
1
Unit
V
analog input voltage
analog input capacitance
differential non-linearity
integral non-linearity
offset error
0
-
-
-
-
-
-
Cia
pF
[1][2]
[3]
DNL
INL
-
1
LSB
LSB
LSB
-
1.5
1
[4]
EO
-
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Table 6.
8-bit ADC static characteristics …continued
Tamb = 40 C to +85 C for HVQFN33 and WLCSP25 packages. Tamb = 10 C to +85 C for the
HVQFN24 package. VDD = 1.8 V 5 %; 8-bit resolution.
Symbol
EG
Parameter
Min
Typ
Max
2
110
10
Unit
[5]
gain error
-
-
-
-
-
-
-
-
LSB
fclk(ADC)
fs
ADC clock frequency
sampling rate
kHz
kSamples/s
k
Rvsi
voltage source interface
resistance
40
[6][7]
Ri
input resistance
-
-
2.5
M
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
See Figure 7.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 7.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 7.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer
curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 7.
[6]
Tamb = 25 C; maximum sampling frequency fs = 10 kSamples/s and analog input capacitance Cia = 1 pF.
[7] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs Cia).
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offset
error
O
gain
error
E
E
G
255
254
253
252
251
250
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
250
251
252
253
254
255
256
1
2
3
4
5
6
7
V
IA
(LSB
)
ideal
offset error
E
O
V - V
DD SS
256
1 LSB =
002aag903
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 7. ADC characteristics
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9.2 Electrical pin characteristics
002aah391
2
1.8
1.6
1.4
1.2
V
OH
(V)
-40 °C
+ 25 °C
+ 85 °C
0
4
8
12
16
20
I
(mA)
OH
Conditions: high-drive pin PIO0_7; VDD = 1.8 V.
Fig 8. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH
.
002aah392
30
OL
-40 °C
+ 25 °C
+ 85 °C
I
(mA)
24
18
12
6
0
0
0.1
0.2
0.3
0.4
0.5
0.6
V
(V)
OL
Conditions: I2C-bus pins PIO0_4 and PIO0_5; VDD = 1.8 V; configured for Fast mode plus in the
IOCON PIO0_4 and PIO0_5 registers.
Fig 9. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
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32-bit ARM Cortex-M0 microcontroller
002aah387
2
1.8
1.6
1.4
1.2
V
OH
(V)
-40 °C
+ 25 °C
+ 85 °C
0
1
2
3
4
5
6
I
(mA)
OH
Conditions: standard port pins; VDD = 1.8 V.
Fig 10. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
002aah388
8
I
OL
(mA)
-40 °C
+25 °C
+ 85 °C
6
4
2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
V
(V)
OL
Conditions: standard port pins; VDD = 1.8 V.
Fig 11. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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002aah394
10
5
I
pu
(μA)
+85 °C
+25 °C
-40 °C
0
-5
-10
-15
-20
0
0.6
1.2
1.8
2.4
3
3.6
V (V)
I
Conditions: standard port pins; VDD = 1.8 V.
Fig 12. Typical pull-up current Ipu versus input voltage VI
002aah393
40
I
pd
(μA)
32
24
16
8
-40 °C
+25 °C
+85 °C
0
0
0.6
1.2
1.8
2.4
3
3.6
V (V)
I
Conditions: standard port pins; VDD = 1.8 V.
Fig 13. Typical pull-down current Ipd versus input voltage VI
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9.3 Power consumption
002aah297
1
I
DD
(mA)
6 MHz
0.8
0.6
0.4
0.2
0
4 MHz
2 MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
V
(V)
DD
Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; System oscillator, system PLL, IRC, BOD
disabled; system clock provided by external clock.
Fig 14. Active mode (2 MHz to 6 MHz): Typical supply current IDD versus supply voltage
VDD for different clock frequencies
002aah296
1
I
DD
(mA)
6 MHz
4 MHz
2 MHz
0.8
0.6
0.4
0.2
0
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD = 1.8 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; System oscillator, system PLL, IRC, BOD
disabled; system clock provided by external clock.
Fig 15. Active mode (2 MHz to 6 MHz): Typical supply current IDD versus temperature for
different clock frequencies
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002aah299
8
6
4
2
0
I
DD
(mA)
(2)
48 MHz
(2)
36 MHz
(2)
24 MHz
(1)
12 MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
V
(V)
DD
Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 16. Active mode: Typical supply current IDD versus supply voltage for different
system clock frequencies
002aah298
8
I
DD
(mA)
(2)
(2)
48 MHz
36 MHz
6
4
2
0
(2)
(1)
24 MHz
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD = 1.8 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 17. Active mode: Typical supply current IDD versus temperature for different system
clock frequencies
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002aag770
0.6
6 MHz
I
DD
(mA)
4 MHz
2 MHz
0.5
0.4
0.3
1.65
1.75
1.85
1.95
V
(V)
DD
Conditions: Tamb = 25 C; Sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; System oscillator and system PLL disabled; IRC disabled; system clock
provided by external clock.
Fig 18. Sleep mode (2 MHz to 6 MHz): Typical supply current IDD versus supply voltage
VDD for different clock frequencies
002aag769
3
(2)
48 MHz
I
DD
(mA)
(2)
(2)
36 MHz
24 MHz
2
1
0
(1)
12 MHz
1.65
1.75
1.85
1.95
V
(V)
DD
Conditions: Tamb = 25 C; Sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 19. Sleep mode (12 MHz to 48 MHz): Typical supply current IDD versus supply voltage
VDD for different clock frequencies
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32-bit ARM Cortex-M0 microcontroller
002aah295
3
I
DD
(mA)
(2)
48 MHz
2.5
(2)
36 MHz
2
(2)
24 MHz
1.5
1
(1)
12 MHz
0.5
0
-40
-15
10
35
60
85
temperature (°C)
Conditions: Tamb = 25 C; VDD = 1.8 V; Sleep mode entered from flash; all peripherals disabled in
the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled;
internal pull-up resistors disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 20. Sleep mode (12 MHz to 48 MHz): Typical supply current IDD versus temperature for
different clock frequencies
002aah294
15
I
DD
(μA)
12
9
6
1.95 V
1.8 V
1.65 V
3
0
-40
-15
10
35
60
85
temperature (°C)
Conditions: all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 21. Deep-sleep mode: Typical supply current IDD versus temperature
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9.4 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
Table 7.
Power consumption for individual analog and digital blocks
Peripheral
Typical supply current in
mA
Notes
n/a
12 MHz 48 MHz
IRC
0.26
-
-
-
-
-
-
System oscillator running; PLL off; independent
of main clock frequency.
System oscillator 0.18
at 12 MHz
IRC running; PLL off; independent of main clock
frequency.
Watchdog
oscillator at
500 kHz/2
0.004
System oscillator running; PLL off; independent
of main clock frequency.
Main PLL
ADC
-
-
-
0.061
0.08
0.18
-
0.29
0.45
CLKOUT
Main clock divided by 4 in the CLKOUTDIV
register.
CT16B0
CT16B1
CT32B0
CT32B1
GPIO
-
-
-
-
-
0.02
0.02
0.02
0.02
0.23
0.06
0.06
0.07
0.06
0.88
GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
IOCON
I2C
-
-
-
-
-
-
0.03
0.04
0.04
0.12
0.22
0.02
0.10
0.13
0.15
0.45
0.82
0.06
ROM
SPI0
UART
WWDT
Main clock selected as clock source for the
WWDT.
9.5 BOD static characteristics
Table 8.
BOD static characteristics
Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage reset level 0
assertion
-
-
1.46
1.63
-
-
V
V
de-assertion
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10. Dynamic characteristics
10.1 Flash memory
Table 9.
Flash characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Nendu
tret
Parameter
endurance
Conditions
Min
10000
10
Typ
Max
Unit
[1]
100000
-
cycles
years
years
ms
retention time
powered
-
-
unpowered
20
-
-
ter
erase time
sector or multiple
consecutive
sectors
95
100
105
[2]
tprog
programming
time
0.95
1
1.05
ms
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
10.2 External clock
Table 10. Dynamic characteristic: external clock
Tamb = 40 C to +85 C; VDD over specified ranges.[1]
Symbol
fosc
Parameter
Conditions
Min
Typ[2]
Max
Unit
MHz
ns
oscillator frequency
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
1
-
-
-
-
-
-
25
Tcy(clk)
tCHCX
tCLCX
tCLCH
tCHCL
40
1000
Tcy(clk) 0.4
-
ns
Tcy(clk) 0.4
-
ns
-
-
5
5
ns
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 22. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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10.3 Internal oscillators
Table 11. Dynamic characteristic: internal oscillators
VDD 1.65V to 1.95 V.
Symbol Parameter
Conditions
Min
Typ[2] Max
Unit
fosc(RC)
internal RC oscillator -20 C Tamb +85 C 12 - 2.5 % 12
12 + 2.5 % MHz
frequency
-40 C Tamb < -20 C 12 - 5 % 12
12 + 5 %
MHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
002aah435
12.6
f
(MHz)
VDD = 1.95 V
12.3
VDD = 1.8 V
VDD = 1.65 V
12
11.7
11.4
-40
-15
10
35
60
85
temperature (°C)
Fig 23. Typical internal RC oscillator frequency for different supply voltages VDD
Table 12. Dynamic characteristics: Watchdog oscillator
Symbol Parameter
Conditions
Min Typ[1]
Max Unit
[2][3]
[2][3]
fosc(int) internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1
-
9.4
-
kHz
frequency
in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
-
2300
-
kHz
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3] See the LPC111xLV user manual.
10.4 I2C-bus
Table 13. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
0
Max
100
400
1
Unit
kHz
kHz
MHz
fSCL
SCL clock
frequency
Standard-mode
Fast-mode
0
Fast-mode Plus
0
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Table 13. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
[4][5][6][7]
tf
fall time
of both SDA and
SCL signals
-
300
ns
Standard-mode
Fast-mode
20 + 0.1 Cb 300
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
Fast-mode Plus
Standard-mode
Fast-mode
-
120
tLOW
LOW period of
the SCL clock
4.7
1.3
0.5
4.0
0.6
0.26
0
-
-
-
-
-
-
-
-
-
-
-
-
Fast-mode Plus
Standard-mode
Fast-mode
tHIGH
HIGH period of
the SCL clock
Fast-mode Plus
Standard-mode
Fast-mode
[3][4][8]
[9][10]
tHD;DAT
data hold time
0
Fast-mode Plus
Standard-mode
Fast-mode
0
tSU;DAT
data set-up
time
250
100
50
Fast-mode Plus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement
t
SU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must
meet this set-up time.
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t
t
SU;DAT
f
70 %
30 %
70 %
30 %
SDA
SCL
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
LOW
1 / f
S
SCL
002aaf425
Fig 24. I2C-bus pins clock timing
10.5 SPI interface
Table 14. Dynamic characteristics of SPI pins in SPI mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI master (in SPI mode)
[1]
[1]
[2]
Tcy(clk)
clock cycle time
data set-up time
data hold time
full-duplex mode
when only transmitting
in SPI mode
50
40
24
-
-
-
-
-
-
ns
ns
ns
tDS
1.8 V VDD < 1.95 V
in SPI mode
[2]
[2]
[2]
tDH
0
-
-
-
-
-
ns
ns
ns
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
10
-
0
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = 40 C to 85 C.
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T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
CPHA = 1
t
t
DH
DS
DATA VALID
DATA VALID
MISO
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
t
MOSI
MISO
t
CPHA = 0
DS
DH
DATA VALID
DATA VALID
002aae829
Fig 25. SPI master timing in SPI mode
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T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
t
t
h(Q)
v(Q)
CPHA = 1
DATA VALID
DATA VALID
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
DATA VALID
t
t
h(Q)
CPHA = 0
v(Q)
DATA VALID
002aae830
Fig 26. SPI slave timing in SPI mode
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11. Application information
11.1 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6:
• The ADC input trace must be short and as close as possible to the
LPC111xLV/LPC11xxLVUK chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
11.2 Standard I/O pad configuration
Figure 27 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver with configurable open-drain output
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Analog input
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V
DD
V
DD
open-drain enable
output enable
data output
strong
pull-up
ESD
pin configured
as digital output
driver
PIN
strong
pull-down
ESD
V
SS
V
DD
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pin configured
as digital input
pull-down enable
data input
10 ns RC
GLITCH FILTER
select data
inverter
select glitch
filter
select analog input
pin configured
as analog input
analog input
002aaf695
Fig 27. Standard I/O pad configuration
11.3 Reset pad configuration
V
DD
V
DD
V
DD
R
pu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
V
SS
002aaf274
Fig 28. Reset pad configuration
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12. Package outline
WLCSP25: wafer level chip-size package; 25 bumps; 2.17 x 2.32 x 0.56 mm
WLCSP25217X232
D
B
A
E
ball A1
index area
A
2
A
A
1
detail X
e
C
1
Ø v
Ø w
C A
C
B
e
y
b
E
D
C
B
A
e
e
2
ball A1
1
2
3
4
5
e
index area
X
0
2 mm
scale
v
Dimensions (mm are the original dimensions)
Unit
A
A
1
A
b
D
E
e
1
e
2
w
y
2
max 0.615 0.23 0.385 0.29 2.21 2.36
mm nom 0.560 0.20 0.360 0.26 2.17 2.32 0.4 1.6 1.6 0.15 0.05 0.05
0.505 0.17 0.335 0.23 2.13 2.28
min
wlcsp25_217x232_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
11-05-04
12-02-13
WLCSP25217X232
Fig 29. Package outline (WLCSP25)
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32-bit ARM Cortex-M0 microcontroller
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
SOT616-3
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
e
1
C
1/2 e
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12
w
L
13
6
e
e
E
h
2
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
mm
A
b
c
E
e
e
e
y
D
D
E
L
v
w
y
1
1
h
1
2
h
0.05 0.30
0.00 0.18
4.1
3.9
2.75
2.45
4.1
3.9
2.75
2.45
0.5
0.3
0.05
0.1
1
0.2
0.5
2.5
2.5
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-11-19
05-03-10
SOT616-3
- - -
MO-220
- - -
Fig 30. Package outline (HVQFN24)
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NXP Semiconductors
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HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D
B
A
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
v
w
C A
C
B
C
1
e
1/2 e
b
9
16
L
17
8
e
e
E
h
2
1/2 e
24
1
terminal 1
index area
32
25
X
D
h
0
2.5
scale
5 mm
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
(1)
Unit
A
A
1
b
c
D
D
E
E
e
e
e
L
v
w
y
y
1
h
h
1
2
max
0.05 0.30
5.1 3.75 5.1 3.75
0.5
mm nom 0.85
min
0.2
0.5 3.5 3.5
0.1 0.05 0.05 0.1
0.00 0.18
4.9 3.45 4.9 3.45
0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
hvqfn33f_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
11-10-11
11-10-17
MO-220
Fig 31. Package outline (HVQFN33)
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13. Soldering
Footprint information for reflow soldering of HVQFN24 package
SOT616-3
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
SPy
nSPx
Hy Gy
SLy By
Ay
nSPy
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx nSPy
2
2
Dimensions in mm
Ax
P
Ay
Bx
By
C
D
SLx
SLy
SPx tot
1.500
SPy tot
1.500
SPx
SPy
Gx
Gy
Hx
Hy
0.500 5.000 5.000 3.200 3.200 0.900 0.240 2.500 2.500
0.550 0.550 4.300 4.300 5.250 5.250
07-05-07
Issue date
sot616-3_fr
09-06-15
Fig 32. Reflow soldering for the HVQFN24 package
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Footprint information for reflow soldering of HVQFN33 package
Hx
Gx
see detail X
P
nSPx
Ay
By
SLy
Hy Gy
nSPy
C
D
SLx
Bx
Ax
0.60
0.30
solder land
solder paste
occupied area
detail X
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
Gx
Gy
5.25
Hx
Hy
SLx
SLy
nSPx nSPy
0.5
5.95
5.95
4.25
4.25
0.85
0.27
5.25
6.2
6.2
3.75
3.75
3
3
11-11-15
11-11-20
Issue date
002aag766
Fig 33. Reflow soldering for the HVQFN33 (5x5) package
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14. Abbreviations
Table 15. Abbreviations
Acronym
ADC
Description
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
AMBA
APB
BOD
Brown-Out Detect
GPIO
JEDEC
NVM
PLL
General-Purpose Input/Output
Joint Electron Devices Engineering Council
Non-Volatile Memory
Phase-Locked Loop
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
Transistor-Transistor Logic
TTL
USART
Universal Synchronous Asynchronous Receiver/Transmitter
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15. Revision history
Table 16. Revision history
Document ID
Release
date
Data sheet status Change notice Supersedes
LPC111XLV_LPC11XXLVUK v.2 20121010
Modifications:
Product data sheet
-
LPC111XLV_LPC11XXLVUK v.1
• Functions CT16B0_CAP1/RXD added to pin PIO3_4.
• Functions CT16B1_CAP1/TXD added to pin PIO3_5.
• Function CT32B1_CAP1 added to pin PIO1_11.
• Capture/clear functionality added to counter/timers. See Section 7.12.
• Figure 21 “Deep-sleep mode: Typical supply current IDD versus temperature”
updated.
• Electrical pin characteristics data combined in Section 9.2 for dual and single power
supplies.
• SSP timing characteristics in slave mode removed for single power supply parts in
Table 14.
• Table 11 “Dynamic characteristic: internal oscillators” and Figure 23 updated.
• Figure 33 corrected.
• Removed dual-power supply option. All parts use a single 1.8 V +/- 10 % power
supply.
• Removed 10-bit ADC. Only the 8-bit ADC is available.
• Temperature range for ADC characteristics on the HVQFN24 package restricted to
Tamb = -10 °C to +85 °C.
• BOD interrupt level 0 removed in Table 8.
• IRC accuracy updated to 2.5 % accuracy for Tamb = -20 °C to +85 °C and to 5 %
accuracy for Tamb = -40 °C to -20 °C.
• Data sheet status changed to Product data sheet.
LPC111XLV_LPC11XXLVUK v.1 20120621
Objective data
sheet
-
-
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16. Legal information
17. Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
17.1 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
LPC111XLV_LPC11XXLVUK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
51 of 53
LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
17.3 Trademarks
non-automotive qualified products in automotive equipment or applications.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC111XLV_LPC11XXLVUK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
52 of 53
LPC111xLV/LPC11xxLVUK
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
19. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.16.2
7.16.3
7.16.4
7.16.5
7.16.6
7.16.7
7.17
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
BrownOut Detection (BOD) . . . . . . . . . . . . . . 20
Code security (Code Read Protection - CRP) 20
APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 21
AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
External interrupt inputs. . . . . . . . . . . . . . . . . 21
Emulation and debugging . . . . . . . . . . . . . . . 21
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Static characteristics . . . . . . . . . . . . . . . . . . . 23
Static characteristics . . . . . . . . . . . . . . . . . . . 23
Analog characteristics . . . . . . . . . . . . . . . . . . 25
Electrical pin characteristics. . . . . . . . . . . . . . 28
Power consumption . . . . . . . . . . . . . . . . . . . . 31
Peripheral power consumption . . . . . . . . . . . 35
BOD static characteristics . . . . . . . . . . . . . . . 35
9.1
9.1.1
9.2
9.3
9.4
9.5
7
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.6
7.7
7.7.1
7.8
7.8.1
7.9
7.9.1
7.10
7.10.1
7.11
7.11.1
7.12
Functional description . . . . . . . . . . . . . . . . . . 11
ARM Cortex-M0 processor. . . . . . . . . . . . . . . 11
On-chip flash program memory . . . . . . . . . . . 11
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Nested Vectored Interrupt Controller (NVIC) . 12
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 13
Fast general purpose parallel I/O . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2C-bus serial I/O controller . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General purpose external event
10
Dynamic characteristics. . . . . . . . . . . . . . . . . 36
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 36
External clock. . . . . . . . . . . . . . . . . . . . . . . . . 36
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 37
I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.1
10.2
10.3
10.4
10.5
11
Application information . . . . . . . . . . . . . . . . . 42
ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 42
Standard I/O pad configuration . . . . . . . . . . . 42
Reset pad configuration. . . . . . . . . . . . . . . . . 43
11.1
11.2
11.3
12
13
14
15
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 44
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision history . . . . . . . . . . . . . . . . . . . . . . . 50
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 16
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System tick timer . . . . . . . . . . . . . . . . . . . . . . 16
Windowed WatchDog Timer . . . . . . . . . . . . . 16
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clocking and power control . . . . . . . . . . . . . . 17
Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 17
16
17
17.1
17.2
17.3
Legal information . . . . . . . . . . . . . . . . . . . . . . 51
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.12.1
7.13
7.14
7.14.1
7.15
7.15.1
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 52
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 18
7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 18
7.15.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 19
7.15.2
7.15.3
7.15.4
7.15.5
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 19
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.15.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.15.5.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 20
7.16
7.16.1
System control . . . . . . . . . . . . . . . . . . . . . . . . 20
Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 October 2012
Document identifier: LPC111XLV_LPC11XXLVUK
相关型号：
LPC1114LVFHN24/303
LPC1114LVFHN24 - 32-bit ARM Cortex-M0 MCU; 32 kB flash, 4/8 kB SRAM; ADC QFN 24-Pin
NXP
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