LPC1224FBD48/121,1_技术文档

LPC122x

32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and

8 kB SRAM

Rev. 2 — 26 August 2011

Product data sheet

1. General description

The LPC122x extend NXP's 32-bit ARM microcontroller continuum and target a wide

range of industrial applications in the areas of factory and home automation. Benefitting

from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher

code density compared to common 8/16-bit microcontroller performing typical tasks. The

LPC122x also feature an optimized ROM-based divide library for Cortex-M0, which offers

several times the arithmetic performance of software-based libraries, as well as highly

deterministic cycle time combined with reduced flash code size. The ARM Cortex-M0

efficiency also helps the LPC122x achieve lower average power for similar applications.

The LPC122x operate at CPU frequencies of up to 45 MHz.They offer a wide range of

flash memory options, from 32 kB to 128 kB. The small 512-byte page erase of the flash

memory brings multiple design benefits, such as finer EEPROM emulation, boot-load

support from any serial interface and ease of in-field programming with reduced on-chip

RAM buffer requirements.

The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with

output feedback loop, two UARTs, one SSP/SPI interface, one I²C-bus interface with

Fast-mode Plus features, a Windowed Watchdog Timer, a DMA controller, a CRC engine,

four general purpose timers, a 32-bit RTC, a 1 % internal oscillator for baud rate

generation, and up to 55 General Purpose I/O (GPIO) pins.

2. Features and benefits

 Processor core

 ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state

from flash) or 30 MHz (zero wait states from flash). The LPC122x have a high

score of over 45 in CoreMark CPU performance benchmark testing, equivalent to

1.51/MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Serial Wire Debug (SWD).

 System tick timer.

 Memory

 Up to 8 kB SRAM.

 Up to 128 kB on-chip flash programming memory.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 Includes ROM-based 32-bit integer division routines.

 Clock generation unit

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy that can optionally be

used as a system clock.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

 Clock output function with divider that can reflect the system oscillator clock, IRC

clock, main clock, and Watchdog clock.

 Real-Time Clock (RTC).

 Digital peripherals

 Micro DMA controller with 21 channels.

 CRC engine.

 Two UARTs with fractional baud rate generation and internal FIFO. One UART with

RS-485 and modem support and one standard UART with IrDA.

 SSP/SPI controller with FIFO and multi-protocol capabilities.

 I²C-bus interface supporting full I²C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode. I²C-bus

pins have programmable glitch filter.

 Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor,

open-drain mode, programmable digital input glitch filter, and programmable input

inverter.

 Programmable output drive on all GPIO pins. Four pins support high-current output

drivers.

 All GPIO pins can be used as edge and level sensitive interrupt sources.

 Four general purpose counter/timers with four capture inputs and four match

outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers).

 Windowed WatchDog Timer (WWDT); IEC-60335 Class B certified.

 Analog peripherals

 One 8-channel, 10-bit ADC.

 Two highly flexible analog comparators. Comparator outputs can be programmed

to trigger a timer match signal or can be used to emulate 555 timer behavior.

 Power

 Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

 Processor wake-up from Deep-sleep mode via start logic using 12 port pins.

 Processor wake-up from Deep-power down and Deep-sleep modes via the RTC.

 Brownout detect with three separate thresholds each for interrupt and forced reset.

 Power-On Reset (POR).

 Integrated PMU (Power Management Unit).

 Unique device serial number for identification.

 3.3 V power supply.

 Available as 64-pin and 48-pin LQFP package.

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

2 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

3. Applications

 eMetering

 Lighting

 Industrial networking

 Alarm systems

 White goods

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC1227FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1226FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1225FBD64/321 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1225FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1224FBD64/121 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1224FBD64/101 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1227FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1226FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1225FBD48/321 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1225FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1224FBD48/121 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1224FBD48/101 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

3 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

4.1 Ordering options

Table 2.

Ordering options for LPC122x

Type number

Flash Total UART

SRAM

I²C/

FM+

SSP/ ADC

GPIO Package

SPI

channels

LPC1227

LPC1227FBD64/301 128 kB 8 kB

LPC1227FBD48/301 128 kB 8 kB

LPC1226

2

1

8

55

39

LQFP64

LQFP48

LPC1226FBD64/301 96 kB 8 kB

LPC1226FBD48/301 96 kB 8 kB

LPC1225

2

1

8

55

39

LQFP64

LQFP48

LPC1225FBD64/321 80 kB 8 kB

LPC1225FBD64/301 64 kB 8 kB

LPC1225FBD48/321 80 kB 8 kB

LPC1225FBD48/301 64 kB 8 kB

LPC1224

2

1

8

55

39

LQFP64

LQFP48

LPC1224FBD64/121 48 kB 4 kB

LPC1224FBD64/101 32 kB 4 kB

LPC1224FBD48/121 48 kB 4 kB

LPC1224FBD48/101 32 kB 4 kB

2

1

8

55

39

LQFP64

LQFP48

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

4 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

5. Block diagram

XTALIN

XTALOUT

RESET

SWD

LPC122x

IRC, OSCILLATORS

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

CLKOUT

BOD

POR

TEST/DEBUG

INTERFACE

FUNCTIONS

clocks and controls

ARM

CORTEX-M0

32/48/64/80/

MICRO DMA

4/8 kB

SRAM

96/128 kB

FLASH

ROM

CONTROLLER

system

bus

master

slave

AHB-LITE BUS

slave

HIGH-SPEED

GPIO

CRC

ENGINE

GPIO ports

AHB-APB

BRIDGE

SCK

SSEL

MISO

MOSI

SSP/SPI

UART0 RS-485

UART1

10-bit ADC

AD[7:0]

ACMP0_I[3:0]

ACMP1_I[3:0]

ACMP0_O

ACMP1_O

VREF_CMP

RXD0

TXD0

COMPARATOR0/1

DTR0, DSR0, CTS0,

DCD0, RI0, RTS0

RXD1

TXD1

WINDOWED WDT

IOCONFIG

SCL

SDA

2

I C

RTCXOUT

RTCXIN

RTC

32 kHz OSCILLATOR

SYSTEM CONTROL

4 × MAT

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

4 × CAP

4 × MAT

4 × CAP

2 × MAT

MICRO DMA REGISTERS

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

2 × CAP

2 × MAT

2 × CAP

Grey-shaded blocks represent peripherals

with connection to the micro DMA controller

002aaf269

Fig 1. LPC122x block diagram

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

5 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

6. Pinning information

6.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

XTALIN

XTALOUT

R/PIO1_0

R/PIO0_31

R/PIO0_30

PIO0_18

3

VREF_CMP

PIO0_19

4

5

PIO0_20

PIO0_17

6

PIO0_21

PIO0_16

7

PIO0_22

PIO0_15

8

PIO0_23

PIO0_14

LPC122x

9

PIO0_24

RESET/PIO0_13

(1)

10

11

12

13

14

15

16

SWDIO/PIO0_25

SWCLK/PIO0_26

PIO0_12

PIO0_11

PIO0_10

PIO2_7

PIO2_6

PIO2_5

PIO2_4

(1)

PIO0_27

PIO2_12

PIO2_13

PIO2_14

PIO2_15

002aaf554

(1) High-current output driver.

Remark: For a full listing of all functions for each pin see Table 3.

Fig 2. Pin configuration LQFP64 package

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

6 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

1

2

36

35

34

33

32

31

30

29

28

27

26

25

XTALIN

R/PIO1_0

R/PIO0_31

R/PIO0_30

PIO0_18

XTALOUT

VREF_CMP

PIO0_19

3

4

5

PIO0_20

PIO0_17

6

PIO0_21

PIO0_16

LPC122x

7

PIO0_22

PIO0_15

8

PIO0_23

PIO0_14

9

PIO0_24

RESET/PIO0_13

(1)

10

11

12

SWDIO/PIO0_25

SWCLK/PIO0_26

PIO0_12

PIO0_11

PIO0_10

(1)

PIO0_27

002aaf724

(1) High-current output driver.

Remark: For a full listing of all functions for each pin see Table 3.

Fig 3. Pin configuration LQFP48 package

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

7 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

All pins except the supply pins can have more than one function as shown in Table 3. The

pin function is selected through the pin’s IOCON register in the IOCONFIG block. The

multiplexed functions (see Table 4) include the counter/timer inputs and outputs, the

UART receive, transmit, and control functions, and the serial wire debug functions.

For each pin, the default function is listed first together with the pin’s reset state.

Table 3.

Symbol

LPC122x pin description

Start Type Reset Description

logic

input

state

[1]

PIO0_0 to PIO0_31

PIO0_0/RTS0

I/O

Port 0 — Port 0 is a 32-bit I/O port with individual direction and

function controls for each bit. The operation of port 0 pins

depends on the function selected through the IOCONFIG

register block.

[2]

[3]

15 19

16 20

yes

I/O

O

I/O

I

I; PU PIO0_0 — General purpose digital input/output pin.

RTS0 — Request To Send output for UART0.

I; PU PIO0_1 — General purpose digital input/output pin.

-

[2]

[3]

PIO0_1/RXD0/

CT32B0_CAP0/

CT32B0_MAT0

-

RXD0 — Receiver input for UART0.

I

CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0.

CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 0.

O

I/O

O

I

[2]

[3]

PIO0_2/TXD0/

CT32B0_CAP1/

CT32B0_MAT1

17 21

18 22

19 23

yes

I; PU PIO0_2 — General purpose digital input/output pin.

-

TXD0 — Transmitter output for UART0.

CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0.

CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 0.

O

I/O

O

I

[2]

[3]

PIO0_3/DTR0/

CT32B0_CAP2/

CT32B0_MAT2

I; PU PIO0_3 — General purpose digital input/output pin.

-

DTR0 — Data Terminal Ready output for UART0.

CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0.

CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0.

O

I/O

I

[2]

[3]

PIO0_4/DSR0/

CT32B0_CAP3/

CT32B0_MAT3

I; PU PIO0_4 — General purpose digital input/output pin.

-

DSR0 — Data Set Ready input for UART0.

I

CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0.

CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0.

O

I/O

I

[2]

[3]

PIO0_5/DCD0

20 24

21 25

yes

I; PU PIO0_5 — General purpose digital input/output pin.

DCD0 — Data Carrier Detect input for UART0.

I; PU PIO0_6 — General purpose digital input/output pin.

-

[2]

[3]

PIO0_6/RI0/

CT32B1_CAP0/

CT32B1_MAT0

I/O

I

-

RI0 — Ring Indicator input for UART0.

I

CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.

CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.

O

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

8 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

LPC122x pin description …continued

Start Type Reset Description

logic

input

state

[1]

[2]

[3]

PIO0_7/CTS0/

CT32B1_CAP1/

CT32B1_MAT1

22 26

23 27

24 28

yes

I/O

I

I; PU PIO0_7 — General purpose digital input/output pin.

-

CTS0 — Clear To Send input for UART0.

I

CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.

CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.

O

I/O

I

[2]

[3]

PIO0_8/RXD1/

CT32B1_CAP2/

CT32B1_MAT2

I; PU PIO0_8 — General purpose digital input/output pin.

-

RXD1 — Receiver input for UART1.

I

CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.

CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.

O

I/O

O

I

[2]

[3]

PIO0_9/TXD1/

CT32B1_CAP3/

CT32B1_MAT3

I; PU PIO0_9 — General purpose digital input/output pin.

-

TXD1 — Transmitter output for UART1.

-

CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1.

CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.

PIO0_10 — General purpose digital input/output pin.

SCL — I²C-bus clock input/output.

O

I/O

I

-

[4]

PIO0_10/SCL

25 37

26 38

yes

I; IA

-

PIO0_11/SDA/

CT16B0_CAP0/

CT16B0_MAT0

I; IA

PIO0_11 — General purpose digital input/output pin.

SDA — I²C-bus data input/output.

-

CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.

CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.

O

I/O

[9]

PIO0_12/CLKOUT/

CT16B0_CAP1/

CT16B0_MAT1

27 39

no

I; PU PIO0_12 — General purpose digital input/output pin. A LOW

level on this pin during reset starts the ISP command handler.

High-current output driver.

O

I

-

CLKOUT — Clock out pin.

CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.

CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.

O

I

[5]

[3]

RESET/PIO0_13

PIO0_14/SCK

28 40

I; PU RESET — External reset input: A LOW on this pin resets the

device, causing I/O ports and peripherals to take on their

default states, and processor execution to begin at address 0.

I/O

I

-

PIO0_13 — General purpose digital input/output pin.

I; PU PIO0_14 — General purpose digital input/output pin.

SCK — Serial clock for SSP/SPI.

I; PU PIO0_15 — General purpose digital input/output pin.

[2]

[3]

29 41

30 42

no

-

[2]

[3]

PIO0_15/SSEL/

CT16B1_CAP0/

CT16B1_MAT0

-

SSEL — Slave select for SSP/SPI.

CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.

CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.

O

[2]

[3]

PIO0_16/MISO/

CT16B1_CAP1/

CT16B1_MAT1

31 43

no

I/O

I

I; PU PIO0_16 — General purpose digital input/output pin.

-

MISO — Master In Slave Out for SSP/SPI.

CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.

CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.

O

LPC122X

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Product data sheet

Rev. 2 — 26 August 2011

9 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

LPC122x pin description …continued

Start Type Reset Description

logic

input

state

[1]

[2]

[3]

PIO0_17/MOSI

32 44

33 45

no

I/O

I

I; PU PIO0_17 — General purpose digital input/output pin.

MOSI — Master Out Slave In for SSP/SPI.

I; PU PIO0_18 — General purpose digital input/output pin.

-

[2]

[3]

PIO0_18/SWCLK/

CT32B0_CAP0/

CT32B0_MAT0

-

SWCLK — Serial wire clock, alternate location.

I

CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0.

CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 0.

O

I/O

I

[6]

[7]

PIO0_19/ACMP0_I0/

CT32B0_CAP1/

CT32B0_MAT1

4

5

6

4

5

6

no

I; PU PIO0_19 — General purpose digital input/output pin.

-

ACMP0_I0 — Input 0 for comparator 0.

I

CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0.

CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 0

O

I/O

I

[6]

[7]

PIO0_20/ACMP0_I1/

CT32B0_CAP2/

CT32B0_MAT2

I; PU PIO0_20 — General purpose digital input/output pin.

-

ACMP0_I1 — Input 1 for comparator 0.

I

CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0.

CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0.

O

I/O

I

[6]

[7]

PIO0_21/ACMP0_I2/

CT32B0_CAP3/

CT32B0_MAT3

I; PU PIO0_21 — General purpose digital input/output pin.

-

ACMP0_I2 — Input 2 for comparator 0.

I

CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0.

CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0.

O

I/O

I

[6]

[7]

PIO0_22/ACMP0_I3

7

8

7

8

no

I; PU PIO0_22 — General purpose digital input/output pin.

ACMP0_I3 — Input 3 for comparator 0.

I; PU PIO0_23 — General purpose digital input/output pin.

-

[6]

[7]

PIO0_23/

ACMP1_I0/

CT32B1_CAP0/

CT32B1_MAT0

I/O

I

-

ACMP1_I0 — Input 0 for comparator 1.

I

CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.

CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.

O

I/O

I

[6]

[7]

PIO0_24/ACMP1_I1/

CT32B1_CAP1/

CT32B1_MAT1

9

no

I; PU PIO0_24 — General purpose digital input/output pin.

-

ACMP1_I1 — Input 1 for comparator 1.

I

CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.

CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.

O

I/O

I

[6]

[7]

SWDIO/ACMP1_I2/

CT32B1_CAP2/

CT32B1_MAT2/

PIO0_25

10 10

I; PU SWDIO — Serial wire debug input/output, default location.

-

ACMP1_I2 — Input 2 for comparator 1.

I

CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.

CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.

PIO0_25 — General purpose digital input/output pin.

O

I/O

I

[6]

[7]

SWCLK/ACMP1_I3/

CT32B1_CAP3/

CT32B1_MAT3/

PIO0_26

11 11

no

I; PU SWCLK — Serial wire clock, default location.

I

-

ACMP1_I3 — Input 3 for comparator 1.

I

CT32B1_CAP3 — Capture input, channel 3 or 32-bit timer 1.

CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.

PIO0_26 — General purpose digital input/output pin.

O

I/O

LPC122X

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 26 August 2011

10 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

LPC122x pin description …continued

Start Type Reset Description

logic

input

state

[1]

[9]

PIO0_27/ACMP0_O

12 12

13 17

no

I/O

I; PU PIO0_27 — General purpose digital input/output pin

(high-current output driver).

O

-

ACMP0_O — Output for comparator 0.

PIO0_28/ACMP1_O/

CT16B0_CAP0/

CT16B0_MAT0

I/O

I; PU PIO0_28 — General purpose digital input/output pin

(high-current output driver).

O

I

-

ACMP1_O — Output for comparator 1.

CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.

CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.

O

I/O

[9]

PIO0_29/ROSC/

CT16B0_CAP1/

CT16B0_MAT1

14 18

no

I; PU PIO0_29 — General purpose digital input/output pin

(high-current output driver).

I/O

-

ROSC — Relaxation oscillator for 555 timer applications.

CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.

CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.

I

O

I

[6]

[3]

R/PIO0_30/AD0

R/PIO0_31/AD1

34 46

35 47

no

I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O

-

PIO0_30 — General purpose digital input/output pin.

AD0 — A/D converter, input 0.

I

[6]

[3]

I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O

I

-

PIO0_31 — General purpose digital input/output pin.

AD1 — A/D converter, input 1.

PIO1_0 to PIO1_6

R/PIO1_0/AD2

I/O

Port 1 — Port 1 is a 32-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins

depends on the function selected through the IOCONFIG

register block. Pins PIO1_7 through PIO1_31 are not available.

[6]

[3]

36 48

37 49

38 50

no

O

I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O

-

PIO1_0 — General purpose digital input/output pin.

AD2 — A/D converter, input 2.

I

[6]

[3]

R/PIO1_1/AD3

I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.Do not pull this pin LOW at reset.

I/O

-

PIO1_1 — General purpose digital input/output pin.

AD3 — A/D converter, input 3.

I

[6]

[3]

PIO1_2/SWDIO/AD4

no

I/O

I; PU PIO1_2 — General purpose digital input/output pin.

I/O

-

SWDIO — Serial wire debug input/output, alternate location.

AD4 — A/D converter, input 4.

I

[8]

[3]

PIO1_3/AD5/WAKEUP 39 51

I/O

I; PU PIO1_3 — General purpose digital input/output pin.

I

-

AD5 — A/D converter, input 5.

I

WAKEUP — Deep power-down mode wake-up pin.

[6]

[3]

PIO1_4/AD6

40 52

I/O

I

I; PU PIO1_4 — General purpose digital input/output pin.

AD6 — A/D converter, input 6.

-

LPC122X

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Product data sheet

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11 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

LPC122x pin description …continued

Start Type Reset Description

logic

input

state

[1]

[6]

[3]

PIO1_5/AD7/

CT16B1_CAP0/

CT16B1_MAT0

41 53

42 54

no

I/O

I

I; PU PIO1_5 — General purpose digital input/output pin.

-

AD7 — A/D converter, input 7.

I

CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.

CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.

O

I/O

I

[2]

[3]

PIO1_6/

CT16B1_CAP1/

CT16B1_MAT1

I; PU PIO1_6 — General purpose digital input/output pin.

-

CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.

CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.

O

I/O

PIO2_0 to PIO2_15

Port 2 — Port 2 is a 32-bit I/O port with individual direction and

function controls for each bit. The operation of port 2 pins

depends on the function selected through the IOCONFIG

register block. Pins PIO2_16 through PIO2_31 are not

available.

[2]

[3]

PIO2_0/

-

29

30

31

32

33

34

no

I/O

I

I; PU PIO2_0 — General purpose digital input/output pin.

CT16B0_CAP0/

CT16B0_MAT0/

RTS0

-

CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.

CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.

RTS0 — Request To Send output for UART0.

O

I/O

I

[2]

[3]

PIO2_1/

CT16B0_CAP1/

CT16B0_MAT1/RXD0

I; PU PIO2_1 — General purpose digital input/output pin.

-

CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.

CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.

RXD0 — Receiver input for UART0.

O

I

[2]

[3]

PIO2_2/

CT16B1_CAP0/

CT16B1_MAT0/TXD0

I/O

I

I; PU PIO2_2 — General purpose digital input/output pin.

-

CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.

CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.

TXD0 — Transmitter output for UART0.

O

I/O

I

[2]

[3]

PIO2_3/

CT16B1_CAP1/

CT16B1_MAT1/DTR0

I; PU PIO2_3 — General purpose digital input/output pin.

-

CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.

CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.

DTR0 — Data Terminal Ready output for UART0.

O

I/O

I

[2]

[3]

PIO2_4/

CT32B0_CAP0/

CT32B0_MAT0/CTS0

I; PU PIO2_4 — General purpose digital input/output pin.

-

CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0.

CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 0.

CTS0 — Clear To Send input for UART0.

O

I

[2]

[3]

PIO2_5/

CT32B0_CAP1/

CT32B0_MAT1/RI0

I/O

I

I; PU PIO2_5 — General purpose digital input/output pin.

-

CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0.

CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 0.

RI0 — Ring Indicator input for UART0.

O

I

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Product data sheet

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LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

LPC122x pin description …continued

Start Type Reset Description

logic

input

state

[1]

[2]

[3]

PIO2_6/

CT32B0_CAP2/

CT32B0_MAT2/DCD0

-

35

36

no

I/O

I

I; PU PIO2_6 — General purpose digital input/output pin.

-

CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0.

CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0.

DCD0 — Data Carrier Detect input for UART0.

O

I

[2]

[3]

PIO2_7/

CT32B0_CAP3/

CT32B0_MAT3/DSR0

I/O

I

I; PU PIO2_7 — General purpose digital input/output pin.

-

CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0.

CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0.

DSR0 — Data Set Ready input for UART0.

O

I

[2]

[3]

PIO2_8/

CT32B1_CAP0/

CT32B1_MAT0

-

59

60

61

no

I/O

I

I; PU PIO2_8 — General purpose digital input/output pin.

-

CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.

CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.

O

I/O

I

[2]

[3]

PIO2_9/

CT32B1_CAP1/

CT32B1_MAT1

I; PU PIO2_9 — General purpose digital input/output pin.

-

CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.

CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.

O

I/O

I

[2]

[3]

PIO2_10/

CT32B1_CAP2/

CT32B1_MAT2/TXD1

I; PU PIO2_10 — General purpose digital input/output pin.

-

CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.

CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.

TXD1 — Transmitter output for UART1.

O

I/O

I

[2]

[3]

PIO2_11/

CT32B1_CAP3/

CT32B1_MAT3/RXD1

-

62

no

I; PU PIO2_11 — General purpose digital input/output pin.

-

CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1.

CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.

RXD1 — Receiver input for UART1.

O

I

[2]

[3]

PIO2_12/RXD1

PIO2_13/TXD1

-

13

14

no

I/O

I

I; PU PIO2_12 — General purpose digital input/output pin.

RXD1 — Receiver input for UART1.

I; PU PIO2_13 — General purpose digital input/output pin.

TXD1 — Transmitter output for UART1.

-

[2]

[3]

I/O

O

I/O

-

[2]

[3]

PIO2_14

PIO2_15

-

15

16

no

I; PU PIO2_14 — General purpose digital input/output pin.

[2]

[3]

I/O

I; PU PIO2_15 — General purpose digital input/output pin.

[10]

RTCXIN

RTCXOUT

XTALIN

46 58

45 57

-

I

-

Input to the 32 kHz oscillator circuit.

O

I

Output from the 32 kHz oscillator amplifier.

1

Input to the system oscillator circuit and internal clock

generator circuits.

XTALOUT

2

3

2

3

-

O

I

-

Output from the system oscillator amplifier.

Reference voltage for comparator.

VREF_CMP

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Product data sheet

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LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

LPC122x pin description …continued

Start Type Reset Description

logic

input

state

[1]

V_DD(IO)

47 63

44 56

-

I

-

Input/output supply voltage.

V_DD(3V3)

3.3 V supply voltage to the internal regulator and the ADC. Also

used as the ADC reference voltage.

V_SSIO

V_SS

48 64

43 55

-

I

-

Ground.

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.

[2] 3.3 V tolerant, digital I/O pin; default: pull-up enabled, no hysteresis.

[3] If set to output, this normal-drive pin is in low mode by default.

[4] I²C-bus pins; 5 V tolerant; open-drain; default: no pull-up/pull-down; no hysteresis.

[5] 3.3 V tolerant, digital I/O pin with RESET function; default: pull-up enabled, no hysteresis. An external pull-up resistor is required on this

pin for the Deep power-down mode.

[6] 3.3 V tolerant, digital I/O pin with analog function; default: pull-up enabled, no hysteresis.

[7] If set to output, this normal-drive pin is in high mode by default.

[8] 3.3 V tolerant, digital I/O pin with analog function and WAKEUP function; default: pull-up enabled, no hysteresis.

[9] 3.3 V tolerant, high-drive digital I/O pin; default: pull-up enabled, no hysteresis.

[10] If the RTC is not used, RTCXIN and RTCXOUT can be left floating.

To enable a peripheral function, find the corresponding port pin, or select a port pin if the

function is multiplexed, and program the port pin’s IOCONFIG register to enable that

function. The primary SWD functions and RESET are the default functions on their pins

after reset.

Table 4.

Pin multiplexing

Peripheral

Function

ROSC

Type

Available on ports:

Analog comparators

I/O

PIO0_29

PIO0_19

PIO0_20

PIO0_21

PIO0_22

PIO0_27

PIO0_23

PIO0_24

PIO0_25

PIO0_26

PIO0_28

-

ACMP0_I0

ACMP0_I1

ACMP0_I2

ACMP0_I3

ACMP0_O

ACMP1_I0

ACMP1_I1

ACMP1_I2

ACMP1_I3

ACMP1_O

I

O

I

O

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LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 4.

Pin multiplexing

Function

Peripheral

Type

Available on ports:

ADC

AD0

I

PIO0_30

PIO0_31

PIO1_0

PIO1_1

PIO1_2

PIO1_3

PIO1_4

PIO1_5

PIO0_11

PIO0_12

PIO0_11

PIO0_12

PIO0_15

PIO0_16

PIO0_15

PIO0_16

PIO0_1

PIO0_2

PIO0_3

PIO0_4

PIO0_1

PIO0_2

PIO0_3

PIO0_4

PIO0_6

PIO0_7

PIO0_8

PIO0_9

PIO0_6

PIO0_7

PIO0_8

PIO0_9

PIO0_1

PIO0_2

PIO0_7

PIO0_5

PIO0_4

PIO0_3

PIO0_6

PIO0_0

-

AD1

I

-

AD2

I

-

AD3

I

-

AD4

I

-

AD5

I

-

AD6

I

-

AD7

I

-

CT16B0

CT16B1

CT32B0

CT16B0_CAP0

CT16B0_CAP1

CT16B0_MAT0

CT16B0_MAT1

CT16B1_CAP0

CT16B1_CAP1

CT16B1_MAT0

CT16B1_MAT1

CT32B0_CAP0

CT32B0_CAP1

CT32B0_CAP2

CT32B0_CAP3

CT32B0_MAT0

CT32B0_MAT1

CT32B0_MAT2

CT32B0_MAT3

CT32B1_CAP0

CT32B1_CAP1

CT32B1_CAP2

CT32B1_CAP3

CT32B1_MAT0

CT32B1_MAT1

CT32B1_MAT2

CT32B1_MAT3

RXD0

I

PIO0_28

PIO0_29

PIO0_28

PIO0_29

PIO1_5

PIO1_6

PIO1_5

PIO1_6

PIO0_18

PIO0_19

PIO0_20

PIO0_21

PIO0_18

PIO0_19

PIO0_20

PIO0_21

PIO0_23

PIO0_24

PIO0_25

PIO0_26

PIO0_23

PIO0_24

PIO0_25

PIO0_26

PIO2_1

PIO2_2

PIO2_4

PIO2_6

PIO2_7

PIO2_3

PIO2_5

PIO2_0

PIO2_1

PIO2_0

PIO2_1

PIO2_2

PIO2_3

PIO2_2

PIO2_3

PIO2_4

PIO2_5

PIO2_6

PIO2_7

PIO2_4

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

PIO2_10

PIO2_11

PIO2_8

PIO2_9

PIO2_10

PIO2_11

-

I

O

I

O

I

O

I

CT32B1

I

O

I

UART0

TXD0

O

I

-

CTS0

-

DCD0

I

-

DSR0

I

-

DTR0

O

I

-

RI0

-

RTS0

O

-

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LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 4.

Pin multiplexing

Function

Peripheral

Type

I

Available on ports:

UART1

RXD1

TXD1

PIO0_8

PIO2_11

PIO2_12

O

PIO0_9

PIO2_10

PIO2_13

SSP/SPI

SCK

I/O

I

PIO0_14

PIO0_16

PIO0_17

PIO0_15

PIO0_10

PIO0_11

PIO0_18

PIO0_25

PIO0_13

PIO0_12

-

MISO

-

MOSI

-

SSEL

-

I2C

SCL

-

SDA

-

SWD

SWCLK^[1]

SWDIO^[1]

RESET

CLKOUT

PIO0_26

I/O

I

PIO1_2

Reset

-

Clockout pin

O

[1] After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25.

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.1.1 System tick timer

The ARM Cortex-M0 includes a System Tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.2 On-chip flash program memory

The LPC122x contain up to 128 kB of on-chip flash memory.

7.3 On-chip SRAM

The LPC122x contain a total of up to 8 kB on-chip static RAM memory.

7.4 Memory map

The LPC122x incorporates several distinct memory regions, shown in the following

figures. Figure 4 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

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LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

AHB peripherals

0x5008 0000

CRC

7

LPC122x

0x5007 0000

4 GB

0xFFFF FFFF

3 - 6 reserved

reserved

private peripheral bus

reserved

0x5003 0000

0x5002 0000

0xE010 0000

0xE000 0000

GPIO PIO2

GPIO PIO1

GPIO PIO0

2

1

0

0x5001 0000

0x5000 0000

0x5008 0000

0x5000 0000

AHB peripherals

reserved

APB peripherals

0x4008 0000

22 - 31 reserved

0x4005 8000

0x4005 4000

0x4008 0000

0x4000 0000

comparator 0/1

RTC

21

20

19

18

APB peripherals

reserved

1 GB

0x4005 0000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

micro DMA registers

system control

0x1FFF 2000

0x1FFF 0000

0x1FFE 2000

0x1FFE 0000

0x1FFC 4000

IOCONFIG

SSP

17

16

15

14

8 kB boot ROM

reserved

0x4003 C000

0x4003 8000

PMU

8 kB custom ROM

reserved

9 - 13 reserved

16 kB NXP library ROM

0x1FFC 0000

0x4002 4000

0x4002 0000

reserved

ADC

8

7

6

5

4

3

2

0x1000 2000

0x1000 1000

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART1

0x4001 C000

0x4001 8000

8 kB SRAM (LPC1225/6/7)

4 kB SRAM (LPC1224)

0x1000 0000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

reserved

0x0002 0000

0x0001 8000

0x0001 4000

0x0001 0000

128 kB on-chip flash (LPC1227/301)

96 kB on-chip flash (LPC1226/301)

80 kB on-chip flash (LPC1225/321)

64 kB on-chip flash (LPC1225/301)

48 kB on-chip flash (LPC1224/121)

32 kB on-chip flash (LPC1224/101)

UART0

WDT

1

0

0x4000 4000

0x4000 0000

2

I C-bus

0x0000 C000

0x0000 8000

0x0000 00C0

active interrupt vectors

0x0000 0000

002aaf270

0x0000 0000

0 GB

Fig 4. LPC122x memory map

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

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LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

• In the LPC122x, the NVIC supports 32 vectored interrupts. In addition, up to 12 of the

individual GPIO inputs are NVIC-vector capable.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation.

• Non-maskable Interrupt (NMI) can be programmed to use any of the peripheral

interrupts. The NMI is not available on an external pin.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 55 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, a rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.6.1 Features

• Programmable pull-up resistor.

• Programmable digital glitch filter.

• Programmable input inverter.

• Programmable drive current.

• Programmable open-drain mode.

7.7 Micro DMA controller

The micro DMA controller enables memory-to-memory, memory-to-peripheral, and

peripheral-to-memory data transfers. The supported peripherals are: UART0 (transmit

and receive), UART1 (transmit and receive), SSP/SPI (transmit and receive), ADC, RTC,

32-bit counter/timer 0 (match output channels 0 and 1), 32-bit counter/timer 1 (match

output channels 0 and 1), 16-bit counter/timer 0 (match output channel 0), 16-bit

counter/timer 1 (match output channel 0), comparator 0, comparator 1, GPIO0 to GPIO2.

7.7.1 Features

• Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit

data bus.

• 21 DMA channels.

• Handshake signals and priority level programmable for each channel.

• Each priority level arbitrates using a fixed priority that is determined by the DMA

channel number.

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Product data sheet

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LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

• Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory

transfers.

• Supports multiple DMA cycle types and multiple DMA transfer widths.

• Performs all DMA transfers using the single AHB-Lite burst type.

7.8 CRC engine

The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings

supports several CRC standards commonly used. To save system power and bus

bandwidth, the CRC engine supports DMA transfers.

7.8.1 Features

• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

– CRC-CCITT: x¹⁶+ x¹²+ x⁵+ 1

– CRC-16: x¹⁶+ x¹⁵+ x²+ 1

– CRC-32: x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵+ x⁴+ x²+ x + 1

• Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

• Programmable seed number setting.

• Supports CPU programmed I/O or DMA back-to-back transfer.

• Accept any size of data width per write: 8, 16 or 32-bit.

– 8-bit write: 1-cycle operation

– 16-bit write: 2-cycle operation (8-bit  2-cycle)

– 32-bit write: 4-cycle operation (8-bit  4-cycle)

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

7.9.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

7.10 UARTs

The LPC122x contains two UARTs. UART0 supports full modem control and RS-485/9-bit

mode and allows both software address detection and automatic hardware address

detection using 9-bit mode.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

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7.10.1 Features

• 16-byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto-baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Support for RS-485/9-bit mode (UART0).

• Support for modem control (UART0).

7.11 SSP/SPI serial I/O controller

The LPC122x contain one SSP/SPI controller. The SSP/SPI controller is capable of

operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data flowing from the master to the slave and from the slave to the master. In

practice, often only one of these data flows carries meaningful data.

7.11.1 Features

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.12 I²C-bus serial I/O controller

The LPC122x contain one I²C-bus controller.

The I²C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.12.1 Features

• The I²C-interface is a standard I²C-compliant bus interface with open-drain pins and

supports I²C Fast-mode Plus with bit rates of up to 1 Mbit/s.

• Programmable digital glitch filter providing a 60 ns to 1 s input filter.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

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• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

• The I²C-bus controller supports multiple address recognition and a bus monitor mode.

7.13 10-bit ADC

The LPC122x contains one ADC. It is a single 10-bit successive approximation ADC with

eight channels.

7.13.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 V to V_DD(3V3)

• 10-bit conversion time of 257 kHz.

.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or counter/timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

7.14 Comparator block

The comparator block consists of two analog comparators.

7.14.1 Features

• Up to six selectable external sources per comparator; fully configurable on either

positive or negative comparator input channels.

• BOD 0.9 V internal reference voltage selectable on both comparators; configurable on

either positive or negative comparator input channels.

• 32-stage voltage ladder internal reference voltage selectable on both comparators;

configurable on either positive or negative comparator input channels.

• Voltage ladder source voltage is selectable from an external pin or an internal 3.3 V

voltage rail if external power source is not available.

• Voltage ladder can be separately powered down for applications only requiring the

comparator function.

• Relaxation oscillator circuitry output for a feedback 555-style timer application.

• Common interrupt connected to NVIC.

• Comparator outputs selectable as synchronous or asynchronous.

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• Comparator outputs connect to two timers, allowing for the recording of comparison

event time stamps.

7.15 General purpose external event counter/timers

The LPC122x includes two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes up to four capture inputs to trap the

timer value when an input signal transitions, optionally generating an interrupt.

7.15.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• Up to four capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Supports timed DMA requests.

7.16 Windowed WatchDog timer (WWDT)

The purpose of the watchdog is to reset the microcontroller within a windowed amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.16.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Safe operation: can be locked by software to be always on.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

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• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2²⁴ 4) in

multiples of T_cy(WDCLK) 4.

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC) or the Watchdog oscillator. This gives a wide range of potential timing choices of

Watchdog operation under different power reduction conditions. It also provides the

ability to run the WDT from an entirely internal source that is not dependent on an

external crystal and its associated components and wiring for increased reliability.

7.17 Real-time clock (RTC)

The RTC provides a basic alarm function or can be used as a long time base counter. The

RTC generates an interrupt after counting for a programmed number of cycles of the RTC

clock input.

7.17.1 Features

• Uses dedicated 32 kHz ultra low-power oscillator.

• Selectable clock inputs: RTC oscillator (1 Hz, delayed 1 Hz, or 1 kHz clock) or main

clock with programmable clock divider.

• 32-bit counter.

• Programmable 32-bit match/compare register.

• Software maskable interrupt when counter and compare registers are identical.

• Generates wake-up from Deep-sleep and Deep power-down modes.

7.18 Clocking and power control

7.18.1 Crystal oscillators

The LPC122x include four independent oscillators. These are the system oscillator, the

Internal RC oscillator (IRC), the RTC 32 kHz oscillator (for the RTC only), and the

Watchdog oscillator. Except for the RTC oscillator, each oscillator can be used for more

than one purpose as required in a particular application.

Following reset, the LPC122x will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

See Figure 5 for an overview of the LPC122x clock generation.

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AHB clock 0

(system)

main clock

system clock

CLOCK

DIVIDER

AHB clocks

1 to 31

31

(memories

and peripherals)

SYSAHBCLKCTRL[1:31]

(AHB clock enable)

3

7

CLOCK

DIVIDER

peripheral clocks

(SSP, UART0, UART1)

CLOCK

DIVIDER

peripheral clocks

(IOCONFIG glitch filter)

CLOCK

DIVIDER

IRC oscillator

RTC oscillator 1 Hz clock

RTC oscillator 1 Hz delayed clock

RTC oscillator 1 kHz clock

RTC

watchdog oscillator

MAINCLKSEL

RTCOSCCTRL

(main clock select)

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

CLOCK

DIVIDER

SYSTEM PLL

CLKOUT pin

system oscillator

SYSPLLCLKSEL

CLKOUTUEN

(CLKOUT clock update enable)

IRC oscillator

WWDT

watchdog oscillator

WDCLKSEL

(WWDT clock select)

002aaf271

Fig 5. LPC122x clocking generation block diagram

7.18.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC122x use the IRC as the clock source. Software

may later switch to one of the other available clock sources.

7.18.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

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The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this

document.

7.18.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and

temperature is 40 %.

7.18.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output

frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100 s.

7.18.3 Clock output

The LPC122x features a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.

7.18.4 Wake-up process

The LPC122x begin operation at power-up and when awakened from Deep power-down

mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation

to resume quickly. If the main oscillator or the PLL is needed by the application, software

will need to enable these features and wait for them to stabilize before they are used as a

clock source.

7.18.5 Power control

The LPC122x support a variety of power control features. There are three special modes

of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down

mode. The CPU clock rate may also be controlled as needed by changing clock sources,

reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a

trade-off of power versus processing speed based on application requirements. In

addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any peripherals that are not required for the application. Selected peripherals have

their own clock divider which provides even better power control.

7.18.5.1 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

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In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.18.5.2 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows

for additional power savings.

The GPIO pins PIO0_0 to PIO0_11 (up to 12 pins total) and the RTC match interrupt can

serve as a wake-up input to the start logic to wake up the chip from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.18.5.3 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

Real Time Clock, the four general-purpose registers, and the WAKEUP pin. The LPC122x

can wake up from Deep power-down mode via the WAKEUP pin or the RTC match

interrupt.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

7.19 System control

7.19.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.19.2 Reset

Reset has four sources on the LPC122x: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

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An external pull-up resistor is required on the RESET pin if Deep power-down mode is

used.

7.19.3 Brownout detection

The LPC122x includes four levels for monitoring the voltage on the V_DD(3V3)pin. If this

voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to

the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading

a dedicated status register. An additional threshold level can be selected to cause a

forced reset of the chip.

7.19.4 Code security (Code Read Protection - CRP)

This feature of the LPC122x allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the SWD and ISP can be restricted. When

needed, CRP is invoked by programming a specific pattern into a dedicated flash location.

IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disables access to chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_12

pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

In addition to the three CRP levels, sampling of pin PIO0_12 for valid user code can be

disabled.

7.19.5 APB interface

The APB peripherals are located on one APB bus.

7.19.6 AHB-Lite

The AHB-Lite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.19.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.

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7.20 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug is supported.

7.21 Integer division routines

The LPC122x contain performance-optimized integer division routines with support for up

to 32-bit width in the numerator and denominator. Routines for signed and unsigned

division and division with remainder are available. The integer division routines are

ROM-based to reduce code-size.

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8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD(3V3)

V_DD(IO)

V_I

Parameter

Conditions

Min

3.0

0.5

0

Max

3.6

Unit

V

supply voltage (3.3 V)

input/output supply voltage

input voltage

3.6

V

[2]

on all digital pins

+3.6

5.5

V

on pins PIO0_10

and PIO0_11

(I²C-bus pins)

V

[3]

I_DD

supply current

per supply pin

per ground pin

-

100

mA

I_SS

ground current

I/O latch-up current

I_latch

(0.5V_DD) < V_I<

(1.5V_DD);

T_j< 125 C

[4]

[5]

T_stg

storage temperature

65

+150

1.5

C

P_tot(pack)

total power dissipation (per package)

based on package

heat transfer, not

device power

-

W

consumption

V_ESD

electrostatic discharge voltage

human body

8000

+8000

V

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

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9. Thermal characteristics

9.1 Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T_j= T_amb+ P_D R_{thj – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 6.

Thermal characteristics

V_DD= 3.0 V to 3.6 V; T_amb= 40 C to +85 C unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_th(j-a)

thermal resistance from

junction to ambient

JEDEC test board; no

air flow

-

LQFP64 package

LQFP48 package

JEDEC test board

LQFP64 package

LQFP48 package

61

86

-

C/W

R_th(j-c)

thermal resistance from

junction to case

-

19

36

-

C/W

C

-

T_j(max)

maximum junction

temperature

150

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10. Static characteristics

Table 7.

Static characteristics

T_amb= 40 C to +85 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_DD(IO)

input/output supply

voltage

on pin V_DD(IO)

3.0

3.3

3.6

V

V_DD(3V3)

I_DD

supply voltage (3.3 V)

supply current

3.0

3.3

3.6

V

Active mode;

V_DD(3V3)= 3.3 V;

T_amb= 25 C; code

while(1){}

executed from flash

all peripherals disabled:

CCLK = 12 MHz

-

4.6

9

-

mA

CCLK = 24 MHz

CCLK = 33 MHz

12.2

all peripherals enabled:

CCLK = 12 MHz

-

6.6

-

mA

CCLK = 24 MHz

10.9

14.1

CCLK = 33 MHz

Sleep mode;

V_DD(3V3)= 3.3 V;

T_amb= 25 C;

all peripherals disabled

CCLK = 12 MHz

CCLK = 24 MHz

CCLK = 33 MHz

-

1.8

3.3

4.4

30

-

mA

A

Deep-sleep mode;

V_DD(3V3)= 3.3 V;

T_amb= 25 C

Deep power-down mode;

-

720

-

nA

V

_DD(3V3)= 3.3 V;

T_amb= 25 C

Normal-drive output pins (Standard port pins, RESET)

I_IL

LOW-level input

current

V_I= 0 V;

-

100

nA

V

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD(IO)

;

-

100

OFF-state output

current

V_O= 0 V; V_O= V_DD(IO)

;

-

100

[2][3][4]

input voltage

pin configured to provide a

digital function

0

V_DD(IO)

V_O

output voltage

output active

0

-

V_DD(IO)

-

V

V_IH

HIGH-level input

voltage

0.7V_DD(IO)

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Table 7.

Static characteristics …continued

T_amb= 40 C to +85 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_IL

LOW-level input

voltage

-

0.3V_DD(I

V

O)

V_hys

V_OH

hysteresis voltage

-

0.4

-

V

HIGH-level output

voltage

low mode; I_OH= 2 mA

high mode; I_OH= 4 mA

V_DD(IO)

0.4



-

V_DD(IO)

0.4

-

V

V_OL

LOW-level output

voltage

low mode; I_OL= 2 mA

high mode; I_OL= 4 mA

-

0.4

-

I_OH

HIGH-level output

current

low mode; V_OH= V_DD(IO)

0.4 V



2

4

-

mA

high mode; V_OH= V_DD(IO)

0.4 V



-

I_OL

LOW-level output

current

low mode; V_OL= 0.4 V

high mode; V_OL= 0.4 V

V_OH= 0 V

2

4

-

mA

-

[5]

I_OHS

HIGH-level

short-circuit output

current

45

I_OLS

LOW-level

V_OL= V_DDA

-

50

mA

short-circuit output

current

I_pu

pull-up current

V_I= 0 V

50

80

100

A

High-drive output pins (PIO0_27, PIO0_28, PIO0_29, PIO0_12)

I_IL

LOW-level input

current

V_I= 0 V;

-

100

nA

V

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD(IO)

;

-

100

OFF-state output

current

V_O= 0 V; V_O= V_DD(IO)

;

-

100

[2][3]

[4]

input voltage

pin configured to provide a

digital function

0

V_DD(IO)

V_O

output voltage

output active

0

-

V_DD(IO)

-

V

V_IH

HIGH-level input

voltage

0.7V_DD(IO)

-

V_IL

LOW-level input

voltage

-

0.3V_DD(IO)

-

V_hys

V_OH

hysteresis voltage

-

V

HIGH-level output

voltage

low mode; I_OH= 20 mA

high mode; I_OH= 28 mA

V_DD(IO)

0.7



V_DD(IO)

0.7

-

V

V_OL

LOW-level output

voltage

low mode; I_OL= 12 mA

high mode; I_OL= 18 mA

-

0.4

V

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Table 7.

Static characteristics …continued

T_amb= 40 C to +85 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_OH

HIGH-level output

current

low mode; V_OH= V_DD(IO)

0.7



20

-

mA

high mode; V_OH= V_DD(IO)

0.7



28

12

-

mA

I_OL

LOW-level output

current

V_OL= 0.4 V

low mode

high mode

18

-

mA

[5]

I_OLS

LOW-level

V_OL= V_DD

short-circuit output

current

I_pu

pull-up current

V_I= 0 V

50

80

100

A

I²C-bus pins (PIO0_10 and PIO0_11)

V_IH

HIGH-level input

voltage

0.7V_DD(IO)

-

V

V_IL

LOW-level input

voltage

0.3V_DD(I

O)

V_hys

V_OL

hysteresis voltage

-

0.05V_DD(IO)

-

V

LOW-level output

voltage

I_OLS= 20 mA

0.4

[6]

I_LI

C_i

input leakage current V_I= V_DD(IO)

V_I= 5 V

-

2

4

A

pF

10

-

22

8

capacitance for each

I/O pin

on pins PIO0_10 and

PIO0_11

Oscillator pins

V_i(xtal)

crystal input voltage

crystal output voltage

see Section 12.1

0

1.8

1.95

V

V_o(xtal)

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] Including voltage on outputs in 3-state mode.

[3] V_DD(3V3)and V_DD(IO)supply voltages must be present.

[4] 3-state outputs go into 3-state mode when V_DD(IO)is grounded.

[5] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[6] To V_SS

.

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10.1 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Measured on a typical sample at T_amb= 25 C and

V

_DD(3V3)= 3.3 V.

Table 8.

Peripheral power consumption

Typical current consumption I_DDin mA

Peripheral

Frequency

24 MHz

12 MHz

independent

system

IRC + PLL

system

IRC

oscillator + PLL

oscillator

IRC

0.29

1.87

-

PLL (PLL output

frequency = 24 MHz)

WDosc (WDosc output 0.25

frequency = 500 kHz)

-

BOD

0.06

-

Analog comparator 0/1

-

0.05

1.86

0.04

0.09

0.08

0.34

0.36

0.09

0.10

0.30

0.52

0.18

0.06

0.05

1.85

0.04

0.09

0.08

0.34

0.37

0.09

0.10

0.29

0.51

0.18

0.06

0.03

1.61

0.02

0.04

0.17

0.18

0.05

0.15

0.26

0.09

0.03

0.02

1.61

0.02

0.04

0.17

0.18

0.05

0.15

0.26

0.09

0.03

ADC

CRC engine

16-bit timer 0 (CT16B0)

16-bit timer 1 (CT16B1)

32-bit timer 0 (CT32B0)

32-bit timer 1 (CT32B1)

GPIO0

GPIO1

GPIO2

I2C

IOCON

RTC

SSP

UART0

UART1

DMA

WWDT

10.2 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the

following conditions (see LPC122x user manual):

• Active mode: all GPIO pins set to input with external pull-up resistors.

• Sleep and Deep-sleep modes: all GPIO pins set to output driving LOW.

• Deep power-down mode: all GPIO pins set to input with external pull-up resistors.

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002aag186

16

I

DD

(mA)

(2)

33 MHz

24 MHz

12

8

4

0

(1)

12 MHz

(3)

4 MHz

1 MHz

3

3.2

3.4

3.6

V

(V)

DD(3V3)

Conditions: T_amb= 25 C; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled; IRC and system PLL disabled.

Fig 6. Active mode: Typical supply current I_DDversus supply voltage V_DD(3V3)for

different system clock frequencies (all peripherals disabled)

002aag023

16

I

DD

(mA)

(2)

33 MHz

24 MHz

12

8

4

0

(1)

12 MHz

(3)

4 MHz

1 MHz

(3)

-40

-15

10

35

60

85

temperature (°C)

Conditions: V_DD(3V3)= 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled; IRC and system PLL disabled.

Fig 7. Active mode: Typical supply current I_DDversus temperature for different system

clock frequencies (peripherals disabled)

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002aag187

16

(2)

33 MHz

24 MHz

I

DD

(mA)

12

8

4

0

(1)

12 MHz

(3)

4 MHz

1 MHz

3

3.2

3.4

3.6

V

(V)

DD(3V3)

Conditions: T_amb= 25 C; active mode entered executing code while(1){} from flash; all

peripherals enabled in the SYSAHBCLKCTRL register.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled with external clock input; IRC and system PLL disabled.

Fig 8. Active mode: Typical supply current I_DDversus supply voltage V_DD(3V3)for

different system clock frequencies (all peripherals enabled)

002aag024

16

(2)

33 MHz

I

DD

(mA)

(2)

24 MHz

12

8

4

0

(1)

12 MHz

(3)

4 MHz

1 MHz

(3)

-40

-15

10

35

60

85

temperature (°C)

Conditions: V_DD(3V3)= 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals enabled in the SYSAHBCLKCTRL register.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled with external clock input; IRC and system PLL disabled.

Fig 9. Active mode: Typical supply current I_DDversus temperature for different system

clock frequencies (peripherals enabled)

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002aag188

5

4

3

2

1

0

(2)

33 MHz

24 MHz

I

DD

(mA)

(1)

12 MHz

(3)

4 MHz

1 MHz

3.0

3.2

3.4

3.6

V

(V)

DD(3V3)

Conditions: V_DD(3V3)= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled with external clock input; IRC and system PLL disabled.

Fig 10. Sleep mode: Typical supply current I_DDversus supply voltage V_DD(3V3)for

different system clock frequencies

002aag190

50

I

DD

(μA)

V

= 3.6 V

3.3 V

DD(3V3)

40

3.0 V

30

20

10

-40

-15

10

35

60

85

temperature (°C)

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

Fig 11. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD(3V3)

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002aag189

1.0

I

DD

(μA)

0.9

0.8

0.7

0.6

V

= 3.6 V

3.3 V

3.0 V

DD(3V3)

-40

-15

10

35

60

85

temperature (°C)

Fig 12. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD(3V3)

10.3 Electrical pin characteristics

002aag175

3.6

V

OH

(V)

3.2

low mode

-40 °C

+25 °C

+70 °C

+85 °C

low mode

-40 °C

+25 °C

+70 °C

+85 °C

2.8

2.4

2

0

16

32

48

I

(mA)

OH

Conditions: V_DD(IO)= 3.3 V

Fig 13. High-drive pins: Typical HIGH-level output voltage V_OHversus HIGH-level output

current I_OH

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002aag310

1.2

high mode

-40 °C

+25 °C

+70 °C

+85 °C

V

OL

low mode

-40 °C

+25 °C

+70 °C

+85 °C

(V)

0.8

0.4

0

16

32

48

I

(mA)

OL

Conditions: V_DD(IO)= 3.3 V

Fig 14. High-drive pins: Typical LOW-level output voltage V_OLversus LOW-level output

current I_OL

002aag180

0.8

V

OL

(V)

-40 °C

+25 °C

+70 °C

+85 °C

0.6

0.4

0.2

0

12

24

36

48

I

(mA)

OL

Conditions: V_DD(IO)= 3.3 V.

Fig 15. I²C-bus pins (high current sink): Typical LOW-level output voltage V_OLversus

LOW-level output current I_OL

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002aag181

1.2

high mode

-

40 °C

V

OL

+25 °C

+70 °C

+85 °C

(V)

low mode

-

40 °C

0.8

+25 °C

+70 °C

+85 °C

0.4

0

4

8

12

16

I

(mA)

OL

Conditions: V_DD(IO)= 3.3 V.

Fig 16. Normal-drive pins: Typical LOW-level output voltage V_OLversus LOW-level output

current I_OL

002aag182

3.4

high mode

-40 °C

+25 °C

+70 °C

+85 °C

V

OH

(V)

3.0

low mode

-40 °C

+25 °C

+70 °C

+85 °C

2.6

2.2

1.8

0

4

8

12

16

I

(mA)

OH

Conditions: V_DD(IO)= 3.3 V.

Fig 17. Normal-drive pins: Typical HIGH-level output voltage V_OHversus HIGH-level

output source current I_OH

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002aag185

0

I

pu

(mA)

-20

-40

+85 °C

+70 °C

+25 °C

-40 °C

-60

-80

-100

0

1

2

3

V (mA)

I

Conditions: V_DD(IO)= 3.3 V.

Fig 18. Typical pull-up current I_puversus input voltage V_I

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10.4 ADC characteristics

Table 9.

ADC static characteristics

T_amb= 40 C to +85 C unless otherwise specified; ADC frequency 9 MHz, V_DD(3V3)= 3.0 V to

3.6 V.

Symbol

V_IA

Parameter

Conditions

Min

Typ^[1]Max

Unit

V

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

V_DD(3V3)

C_ia

1

pF

[2][3][4]

[2][5]

[2][6]

[2][7]

[2][8]

E_D

 1

 2.5

 1

 3

257

3.9

LSB

kHz

M

E_L(adj)

E_O

E_G

gain error

E_T

absolute error

f_c(ADC)

R_i

ADC conversion frequency

input resistance

[9][10]

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] Conditions: V_SS= 0 V, V_DD(3V3)= 3.3 V.

[3] The ADC is monotonic, there are no missing codes.

[4] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width.

See Figure 19.

[5] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 19.

[6] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 19.

[7] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer

curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 19.

[8] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer

curve of the non-calibrated ADC and the ideal transfer curve. See Figure 19.

[9]

T_amb= 25 C; maximum sampling frequency f_s= 257 kHz and analog input capacitance C_ia= 1 pF.

[10] Input resistance R_idepends on the sampling frequency fs: R_i= 1 / (f_s C_ia).

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offset

error

gain

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

offset error

E

O

V

− V

SS

DD(3V3)

1 LSB =

1024

002aae787

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 19. ADC characteristics

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10.5 BOD static characteristics

Table 10. BOD static characteristics^[1]

T_amb= 25 C.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 1

assertion

-

2.25

2.39

-

V

de-assertion

interrupt level 2

assertion

-

2.54

2.67

-

V

de-assertion

interrupt level 3

assertion

-

2.83

2.93

-

V

de-assertion

reset level 1

assertion

-

2.04

2.18

-

V

de-assertion

reset level 2

assertion

-

2.34

2.47

-

V

de-assertion

reset level 3

assertion

-

2.62

2.76

-

V

de-assertion

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC122x

user manual.

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11. Dynamic characteristics

11.1 Power-up ramp conditions

Table 11. Power-up characteristics

_amb= 40 C to +85 C.

T

Symbol Parameter

Conditions

Min

0

Typ

Max

500

-

Unit

ms

s

[1]

t_r

rise time

at t = t₁: 0 < V_I 400 mV

-

[1][2]

t_wait

V_I

wait time

12

0

input voltage

at t = t₁on pin V_DD

400

mV

[1] See Figure 20.

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

t

r

V

DD

400 mV

0

t

wait

t = t

1

002aag001

Condition: 0 < V_I 400 mV at start of power-up (t = t₁)

Fig 20. Power-up ramp

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11.2 Flash memory

Table 12. Dynamic characteristic: flash memory

T_amb= 40 C to +85 C; V_DD(3V3)over specified ranges.

Symbol

Parameter

Conditions

Min

Max

20

Unit

ms

[1]

t_er

erase time

for one page (512 byte)

for one sector (4 kB)

-

162

20

ms

for all sectors; mass

erase

-

ms

[1]

t_prog

programming

time

one word (4 bytes)

-

49

s

four sequential words

194

765

128 bytes (one row of 32

words)

[2]

N_endu

t_ret

endurance

20000

10

-

cycles

years

retention time

[1] Erase and programming times are valid over the lifetime of the device (minimum 20000 cycles).

[2] Number of program/erase cycles.

11.3 External clock

Table 13. Dynamic characteristic: external clock

T_amb= 40 C to +85 C; V_DD(3V3)over specified ranges.^[1]

Symbol

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk) 0.4

-

ns

T_cy(clk) 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 21. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

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11.4 Internal oscillators

Table 14. Dynamic characteristic: internal oscillators

T_amb= 40 C to +85 C; V_DD(3V3)over specified ranges.^[1]

Symbol Parameter

f_osc(RC)internal RC oscillator frequency

Conditions

Min

Typ^[2]Max

12 12.12

Unit

-

11.88

MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

002aag020

12.15

12 MHz + 1%

f

osc(RC)

(MHz)

VDD = 3.6 V

3.3 V

3.0 V

12.05

11.95

11.85

12 MHz − 1%

−40

−15

10

35

60

85

temperature (°C)

Fig 22. Internal RC oscillator frequency versus temperature

Table 15. Dynamic characteristics: Watchdog oscillator

Symbol Parameter

Conditions

Min Typ^[1]

Max Unit

[2][3]

f_osc(int)internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1

-

7.8

-

kHz

frequency

in the WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register

-

1700

-

kHz

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +85 C) is 40 %.

[3] See the LPC122x user manual.

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11.5 I²C-bus

Table 16. Dynamic characteristic: I²C-bus pins

T_amb= 40 C to +85 C.^[1]

Symbol

Parameter

Conditions

Min

Max

100

400

1

Unit

kHz

MHz

ns

f_SCL

SCL clock frequency

Standard-mode

Fast-mode

0

-

Fast-mode Plus

[3][4][5][6]

t_f

fall time

of both SDA and

SCL signals

300

Standard-mode

Fast-mode

20 + 0.1  C_b

300

ns

s

ns

Fast-mode Plus

Standard-mode

Fast-mode

-

120

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

data hold time

4.7

1.3

0.5

4.0

0.6

0.26

0

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

Fast-mode Plus

Standard-mode

Fast-mode

[2][3][7]

[8][9]

t_HD;DAT

0

Fast-mode Plus

Standard-mode

Fast-mode

0

t_SU;DAT

data set-up time

250

100

50

Fast-mode Plus

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[4] C_b= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[5] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[7] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t_VD;DATor

t

_VD;ACKby a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[9] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement t_SU;DAT= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

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t

SU;DAT

f

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 23. I²C-bus pins clock timing

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12. Application information

12.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave

mode, a minimum of 200 mV(RMS) is needed.

LPC1xxx

XTALIN

C

i

C

g

100 pF

002aae788

Fig 24. Slave mode operation of the on-chip oscillator

12.2 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1,C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_x1and C_x2should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

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12.3 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967-2 standard using the

TEM-cell method are shown for the LPC1227FBD64/301 in Table 17.

Table 17. ElectroMagnetic Compatibility (EMC) for part LPC1227FBD64/301 (TEM-cell

method)

V_DD= 3.3 V; T_amb= 25 C.

Parameter Frequency band

System clock =

12 MHz

Unit

24 MHz

33 MHz

Input clock: IRC (12 MHz)

maximum

peak level

150 kHz - 30 MHz

4.2

3.8

6.4

dBV

30 MHz - 150 MHz

7.3

16.4

M

5.4

20.1

L

9

dBV

-

150 MHz - 1 GHz

-

23.4

L

IEC level^[1]

Input clock: crystal oscillator (12 MHz)

maximum

peak level

150 kHz - 30 MHz

4.8

4

6.6

dBV

30 MHz - 150 MHz

6.9

16.3

M

5.6

20.3

L

10

22.3

L

dBV

-

150 MHz - 1 GHz

-

IEC level^[1]

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

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13. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 25. Package outline SOT314-2 (LQFP64)

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LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 26. Package outline SOT313-2 (LQFP48)

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14. Soldering

Footprint information for reflow soldering of LQFP48 package

SOT313-2

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650

sot313-2_fr

Fig 27. Reflow soldering of the LQFP48 package

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Footprint information for reflow soldering of LQFP64 package

SOT314-2

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 13.300 13.300 10.300 10.300 1.500 0.280 0.400 10.500 10.500 13.550 13.550

sot314-2_fr

Fig 28. Reflow soldering of the LQFP64 package

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15. Abbreviations

Table 18. Abbreviations

Acronym

ADC

AHB

APB

Description

Analog-to-Digital-Converter

Advanced High-performance Bus

Advanced Peripheral Bus

BrownOut Detection

BOD

CCITT

CRC

DMA

FIFO

GPIO

I/O

Comité Consultatif International Téléphonique et Télégraphique

Cyclic Redundancy Check

Direct Memory Access

First-In-First-Out

General Purpose Input/Output

Input/Output

IrDA

Infrared Data Association

IRC

Internal Resistor-Capacitor

Joint Electron Devices Engineering Council

Phase-Locked Loop

JEDEC

PLL

SPI

Serial Peripheral Interface

SSI

Serial Synchronous Interface

Synchronous Serial Port

SSP

UART

Universal Asynchronous Receiver/Transmitter

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16. Revision history

Table 19. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

LPC122X v.2

20110826

Product data sheet

-

LPC122X v.1.2

Modifications:

• Power consumption data updated in Table 7.

• Power consumption graphs added in Section 10.2.

• Electrical pin characteristics updated for all pins in Table 7 and Section 10.3.

• Parameter R_iadded to Table 9.

• EMC data added (Section 12.3).

• Parameter V_Iupdated for I²C-bus pins in Table 5.

• Section 11.1 “Power-up ramp conditions” added.

• Data sheet status updated to Product Data Sheet.

• SSP dynamic characteristics removed.

LPC122X v.1.2

Modifications:

20110329

Objective data sheet

-

LPC122X v.1.1

• Figure 2 “Pin configuration LQFP64 package”: Pin RTCXIN changed to 58 and pin

RTCXOUT changed to 57.

• Table 3 “LPC122x pin description”: In column Pin LQFP64, pin RTCXIN changed to 58

and pin RTCXOUT changed to 57.

LPC122X v.1.1

Modifications:

20110221

Objective data sheet

-

LPC122X v.1

• Section 1 “General description”: Updated text.

• Section 2 “Features and benefits”: Updated text.

LPC122X v.1

20110214

Objective data sheet

-

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

17.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

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Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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19. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.18.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 25

7.18.2

7.18.3

7.18.4

7.18.5

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 25

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 25

Power control. . . . . . . . . . . . . . . . . . . . . . . . . 25

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

4

4.1

5

7.18.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.18.5.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 26

7.18.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 26

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.19

System control . . . . . . . . . . . . . . . . . . . . . . . . 26

Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Brownout detection . . . . . . . . . . . . . . . . . . . . 27

Code security (Code Read Protection - CRP) 27

APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 27

AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

External interrupt inputs. . . . . . . . . . . . . . . . . 27

Emulation and debugging . . . . . . . . . . . . . . . 28

Integer division routines. . . . . . . . . . . . . . . . . 28

7.19.1

7.19.2

7.19.3

7.19.4

7.19.5

7.19.6

7.19.7

7.20

7

7.1

7.1.1

7.2

7.3

Functional description . . . . . . . . . . . . . . . . . . 16

ARM Cortex-M0 processor . . . . . . . . . . . . . . . 16

System tick timer . . . . . . . . . . . . . . . . . . . . . . 16

On-chip flash program memory . . . . . . . . . . . 16

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Nested Vectored Interrupt Controller (NVIC) . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18

IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Micro DMA controller . . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Fast general purpose parallel I/O . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SSP/SPI serial I/O controller . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I²C-bus serial I/O controller . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Comparator block . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

General purpose external event

7.4

7.5

7.21

7.5.1

7.5.2

7.6

7.6.1

7.7

7.7.1

7.8

7.8.1

7.9

7.9.1

7.10

7.10.1

7.11

7.11.1

7.12

7.12.1

7.13

7.13.1

7.14

7.14.1

7.15

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

Thermal characteristics . . . . . . . . . . . . . . . . . 30

9

9.1

10

Static characteristics . . . . . . . . . . . . . . . . . . . 31

Peripheral power consumption . . . . . . . . . . . 34

Power consumption . . . . . . . . . . . . . . . . . . . 34

Electrical pin characteristics. . . . . . . . . . . . . . 38

ADC characteristics . . . . . . . . . . . . . . . . . . . . 42

BOD static characteristics . . . . . . . . . . . . . . . 44

10.1

10.2

10.3

10.4

10.5

11

Dynamic characteristics. . . . . . . . . . . . . . . . . 45

Power-up ramp conditions . . . . . . . . . . . . . . . 45

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 45

External clock. . . . . . . . . . . . . . . . . . . . . . . . . 46

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47

I²C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11.1

11.2

11.3

11.4

11.5

12

12.1

12.2

Application information . . . . . . . . . . . . . . . . . 50

XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

XTAL Printed Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

ElectroMagnetic Compatibility (EMC) . . . . . . 51

12.3

13

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Windowed WatchDog timer (WWDT) . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Real-time clock (RTC) . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clocking and power control . . . . . . . . . . . . . . 23

Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 23

7.15.1

7.16

7.16.1

7.17

7.17.1

7.18

7.18.1

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 52

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 56

Revision history . . . . . . . . . . . . . . . . . . . . . . . 57

14

15

16

17

Legal information . . . . . . . . . . . . . . . . . . . . . . 58

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 58

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 58

17.1

17.2

17.3

7.18.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24

7.18.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 24

continued >>

LPC122X

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 26 August 2011

60 of 61

LPC122x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

17.4

18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Contact information. . . . . . . . . . . . . . . . . . . . . 59

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 August 2011

Document identifier: LPC122X


型号：	LPC1224FBD48/121,1
厂家：	NXP
描述：	LPC1224FBD48 - 32kB flash, 4kB SRAM, LQFP48 package QFP 48-Pin 时钟 PC 微控制器静态存储器外围集成电路
文件：	总61页 (文件大小：381K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC1224FBD48/121,1 [NXP]

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