LPC1756FBD80_技术文档

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB

SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

Rev. 04 — 26 January 2010

Product data sheet

1. General description

The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The

LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU

incorporates a 3-stage pipeline and uses a Harvard architecture with separate local

instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3

CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash

memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,

8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,

SPI interface, 2 I²C-bus interfaces, 2-input plus 2-output I²S-bus interface, 6 channel

12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general

purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)

with separate battery supply, and up to 52 general purpose I/O pins.

2. Features

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

(LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit

(MPU) supporting eight regions is included.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator

enables high-speed 120 MHz operation with zero wait states.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

On-chip SRAM includes:

Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance

CPU access.

Two/one 16 kB SRAM blocks with separate access paths for higher throughput.

These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA

memory, as well as for general purpose CPU instruction and data storage.

Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I²S-bus, UART, the Analog-to-Digital and

Digital-to-Analog converter peripherals, timer match signals, and for

memory-to-memory transfers.

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC

(LPC1758 only), and the USB interface. This interconnect provides communication

with no arbitration delays.

Split APB bus allows high throughput with few stalls between the CPU and DMA.

Serial interfaces:

On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA

controller.

USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and

on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB

device controller only.

Four UARTs with fractional baud rate generation, internal FIFO, and DMA support.

One UART has modem control I/O and RS-485/EIA-485 support, and one UART

has IrDA support.

CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.

SPI controller with synchronous, serial, full duplex communication and

programmable data length.

Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces

can be used with the GPDMA controller.

Two I²C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with

multiple address recognition and monitor mode.

On the LPC1759/58/56 only, I²S (Inter-IC Sound) interface for digital audio input or

output, with fractional rate control. The I²S-bus interface can be used with the

GPDMA. The I²S-bus interface supports 3-wire and 4-wire data transmit and

receive as well as master clock input/output.

Other peripherals:

52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All

GPIOs support a new, configurable open-drain operating mode. The GPIO block is

accessed through the AHB multilayer bus for fast access and located in memory

such that it supports Cortex-M3 bit banding and use by the General Purpose DMA

Controller.

12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins,

conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can

be used with the GPDMA controller.

On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with

dedicated conversion timer and DMA support.

Four general purpose timers/counters, with a total of three capture inputs and ten

compare outputs. Each timer block has an external count input. Specific timer

events can be selected to generate DMA requests.

One motor control PWM with support for three-phase motor control.

Quadrature encoder interface that can monitor one external quadrature encoder.

One standard PWM/timer block with external count input.

Real-Time Clock (RTC) with a separate power domain and dedicated RTC

oscillator. The RTC block includes 20 bytes of battery-powered backup registers.

Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

ARM Cortex-M3 system tick timer, including an external clock input option.

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

2 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Repetitive Interrupt Timer (RIT) provides programmable and repeating timed

interrupts.

Each peripheral has its own clock divider for further power savings.

Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire

Debug and Serial Wire Trace Port options.

Emulation trace module enables non-intrusive, high-speed real-time tracing of

instruction execution.

Integrated PMU (Power Management Unit) automatically adjusts internal regulators to

minimize power consumption during Sleep, Deep sleep, Power-down, and Deep

power-down modes.

Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.

Single 3.3 V power supply (2.4 V to 3.6 V).

One external interrupt input configurable as edge/level sensitive. All pins on Port 0 and

Port 2 can be used as edge sensitive interrupt sources.

Non-maskable Interrupt (NMI) input.

The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from

any priority interrupt that can occur while the clocks are stopped in Deep sleep,

Power-down, and Deep power-down modes.

Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt (LPC1758 only), CAN bus activity, Port 0/2 pin interrupt, and NMI).

Brownout detect with separate threshold for interrupt and forced reset.

Power-On Reset (POR).

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a

system clock.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,

or the RTC oscillator.

USB PLL for added flexibility.

Code Read Protection (CRP) with different security levels.

Unique device serial number for identification purposes.

Available as 80-pin LQFP package (12 mm × 12 mm × 1.4 mm).

3. Applications

eMetering

Lighting

Industrial networking

Alarm systems

White goods

Motor control

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

3 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC1759FBD80

LPC1758FBD80

LPC1756FBD80

LPC1754FBD80

LPC1752FBD80

LPC1751FBD80

LQFP80

plastic low-profile quad package; 80 leads; body 12 × 12 × 1.4 mm

SOT315-1

4.1 Ordering options

Table 2.

Ordering options

Type number

Flash SRAM in kB

Ethernet USB

CAN I²S-bus DAC Maximum

CPU

operating

frequency

CPU AHB

AHB

Total

SRAM0 SRAM1

LPC1759FBD80 512 kB 32

LPC1758FBD80 512 kB 32

LPC1756FBD80 256 kB 16

LPC1754FBD80 128 kB 16

LPC1752FBD80 64 kB 16

16

-

16

-

64

32

16

8

no

yes

no

Device/Host/OTG 2

yes

no

yes 120 MHz

yes 100 MHz

Device/Host/OTG 2

Device/Host/OTG 1

-

Device only

1

no

100 MHz

LPC1751FBD80 32 kB

8

-

no

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

4 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

5. Block diagram

XTAL1

debug

port

JTAG

interface

RMII pins

USB pins

USB PHY

XTAL2

RESET

LPC1759/58/56/54/52/51

TEST/DEBUG

INTERFACE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

USB HOST/

DEVICE/OTG

CONTROLLER

ETHERNET

ARM

CORTEX-M3

DMA

CONTROLLER

FUNCTIONS

(2)

WITH DMA

(4)

WITH DMA

clocks and

controls

I-code

bus

D-code

bus

system

bus

master

slave

ROM

slave

MULTILAYER AHB MATRIX

SRAM

64/32/

16/8 kB

slave

FLASH

ACCELERATOR

slave

AHB TO

APB

BRIDGE 1

P0, P1,

P2, P4

HIGH-SPEED

GPIO

AHB TO

APB

BRIDGE 0

FLASH

512/256/128/64/32 kB

APB slave group 0

SSP1

APB slave group 1

SSP0

SCK0

SCK1

SSEL0

MISO0

MOSI0

SSEL1

MISO1

MOSI1

RXD2/3

TXD2/3

RXD0/TXD0

8 × UART1

UART2/3

UART0/1

1 × I2SRX

3 × I2STX

TX_MCLK

RX_MCLK

RD1/2

TD1/2

(1)

CAN1/CAN2

(1)

I2S

SCL1

SDA1

I2C1

SPI0

SCL2

SDA2

I2C2

SCK/SSEL

MOSI/MISO

2 × MAT0/1

RI TIMER

TIMER2/3

TIMER 0/1

WDT

1 × CAP0,

2 × CAP1

4 × MAT2

2 × MAT3

PWM1[6:1]

PCAP1[1:0]

EXTERNAL INTERRUPTS

SYSTEM CONTROL

EINT0

PWM1

12-bit ADC

AD0[7:2]

MCOA[2:0]

MCOB[2:0]

MCI[2:0]

PIN CONNECT

MOTOR CONTROL PWM

P0, P2

GPIO INTERRUPT CONTROL

32 kHz

(3)

DAC

AOUT

RTCX1

RTCX2

PHA, PHB

INDEX

RTC

OSCILLATOR

QUADRATURE ENCODER

(1)

VBAT

LPC1759/58/56 only

LPC1758 only

LPC1759/58/56/54 only

LPC1752/51 USB device only

BACKUP REGISTERS

RTC POWER DOMAIN

(2)

(3)

(4)

002aae153

Grey-shaded blocks represent peripherals with connection to the GPDMA.

Fig 1. Block diagram

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

5 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

6. Pinning information

6.1 Pinning

1

60

20

41

002aae158

Fig 2. Pin configuration LQFP80 package

6.2 Pin description

Table 3.

Pin description

Symbol

Type

Description

P0[0] to P0[31]

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The

operation of Port 0 pins depends upon the pin function selected via the pin

connect block. Some port pins are not available on the LQFP80 package.

P0[0]/RD1/TXD3/

SDA1

37^[1]

I/O

I

P0[0] — General purpose digital input/output pin.

RD1 — CAN1 receiver input.

O

TXD3 — Transmitter output for UART3.

I/O

O

SDA1 — I²C1 data input/output (this is not an I²C-bus compliant open-drain pin).

P0[1] — General purpose digital input/output pin.

TD1 — CAN1 transmitter output.

P0[1]/TD1/RXD3/

SCL1

38^[1]

I

RXD3 — Receiver input for UART3.

I/O

O

SCL1 — I²C1 clock input/output (this is not an I²C-bus compliant open-drain pin).

P0[2] — General purpose digital input/output pin.

TXD0 — Transmitter output for UART0.

P0[2]/TXD0/AD0[7] 79^[2]

P0[3]/RXD0/AD0[6] 80^[2]

I

AD0[7] — A/D converter 0, input 7.

I/O

I

P0[3] — General purpose digital input/output pin.

RXD0 — Receiver input for UART0.

I

AD0[6] — A/D converter 0, input 6.

P0[6]/

I2SRX_SDA/

SSEL1/MAT2[0]

64^[1]

I/O

P0[6] — General purpose digital input/output pin.

I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I²S-bus specification.

(LPC1759/58/56 only).

I/O

O

SSEL1 — Slave Select for SSP1.

MAT2[0] — Match output for Timer 2, channel 0.

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

6 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

P0[7]/I2STX_CLK/ 63^[1]

SCK1/MAT2[1]

Pin description …continued

Type

I/O

Description

P0[7] — General purpose digital input/output pin.

I/O

I2STX_CLK — Transmit Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I²S-bus specification.

(LPC1759/58/56 only).

I/O

O

SCK1 — Serial Clock for SSP1.

MAT2[1] — Match output for Timer 2, channel 1.

P0[8] — General purpose digital input/output pin.

P0[8]/I2STX_WS/

MISO1/MAT2[2]

62^[1]

I/O

I2STX_WS — Transmit Word Select. It is driven by the master and received by the

slave. Corresponds to the signal WS in the I²S-bus specification. (LPC1759/58/56

only).

I/O

O

MISO1 — Master In Slave Out for SSP1.

MAT2[2] — Match output for Timer 2, channel 2.

P0[9] — General purpose digital input/output pin.

P0[9]/I2STX_SDA/ 61^[1]

MOSI1/MAT2[3]

I/O

I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I²S-bus specification.

(LPC1759/58/56 only).

I/O

O

MOSI1 — Master Out Slave In for SSP1.

MAT2[3] — Match output for Timer 2, channel 3.

P0[10] — General purpose digital input/output pin.

TXD2 — Transmitter output for UART2.

P0[10]/TXD2/

SDA2/MAT3[0]

39^[1]

40^[1]

47^[1]

48^[1]

46^[1]

45^[1]

I/O

O

I/O

O

SDA2 — I²C2 data input/output (this is not an open-drain pin).

MAT3[0] — Match output for Timer 3, channel 0.

P0[11] — General purpose digital input/output pin.

RXD2 — Receiver input for UART2.

P0[11]/RXD2/

SCL2/MAT3[1]

I/O

I

I/O

O

SCL2 — I²C2 clock input/output (this is not an open-drain pin).

MAT3[1] — Match output for Timer 3, channel 1.

P0[15] — General purpose digital input/output pin.

TXD1 — Transmitter output for UART1.

P0[15]/TXD1/

SCK0/SCK

I/O

O

I/O

I

SCK0 — Serial clock for SSP0.

SCK — Serial clock for SPI.

P0[16]/RXD1/

SSEL0/SSEL

P0[16] — General purpose digital input/output pin.

RXD1 — Receiver input for UART1.

I/O

I

SSEL0 — Slave Select for SSP0.

SSEL — Slave Select for SPI.

P0[17]/CTS1/

MISO0/MISO

P0[17] — General purpose digital input/output pin.

CTS1 — Clear to Send input for UART1.

MISO0 — Master In Slave Out for SSP0.

MISO — Master In Slave Out for SPI.

I/O

I

P0[18]/DCD1/

MOSI0/MOSI

P0[18] — General purpose digital input/output pin.

DCD1 — Data Carrier Detect input for UART1.

MOSI0 — Master Out Slave In for SSP0.

MOSI — Master Out Slave In for SPI.

I/O

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

7 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Symbol

44^[1]

Type

I/O

O

Description

P0[22]/RTS1/TD1

P0[22] — General purpose digital input/output pin.

RTS1 — Request to Send output for UART1. Can also be configured to be an

RS-485/EIA-485 output enable signal.

O

TD1 — CAN1 transmitter output.

P0[25]/AD0[2]/

I2SRX _SDA/

TXD3

7^[2]

I/O

I

P0[25] — General purpose digital input/output pin.

AD0[2] — A/D converter 0, input 2.

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I²S-bus specification.

(LPC1759/58/56 only).

O

TXD3 — Transmitter output for UART3.

P0[26] — General purpose digital input/output pin.

AD0[3] — A/D converter 0, input 3.

P0[26]/AD0[3]/

AOUT/RXD3

6^[3]

I/O

I

O

AOUT — DAC output. (LPC1759/58/56/54 only).

RXD3 — Receiver input for UART3.

I

P0[29]/USB_D+

P0[30]/USB_D−

P1[0] to P1[31]

22^[4]

23^[4]

I/O

P0[29] — General purpose digital input/output pin.

USB_D+ — USB bidirectional D+ line.

P0[30] — General purpose digital input/output pin.

USB_D− — USB bidirectional D− line.

Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 1 pins depends upon the pin function selected via the pin connect

block. Some port pins are not available on the LQFP80 package.

P1[0]/

ENET_TXD0

76^[1]

75^[1]

74^[1]

73^[1]

72^[1]

71^[1]

70^[1]

69^[1]

25^[1]

I/O

O

P1[0] — General purpose digital input/output pin.

ENET_TXD0 — Ethernet transmit data 0. (LPC1758 only).

P1[1] — General purpose digital input/output pin.

ENET_TXD1 — Ethernet transmit data 1. (LPC1758 only).

P1[4] — General purpose digital input/output pin.

ENET_TX_EN — Ethernet transmit data enable. (LPC1758 only).

P1[8] — General purpose digital input/output pin.

ENET_CRS — Ethernet carrier sense. (LPC1758 only).

P1[9] — General purpose digital input/output pin.

ENET_RXD0 — Ethernet receive data. (LPC1758 only).

P1[10] — General purpose digital input/output pin.

ENET_RXD1 — Ethernet receive data. (LPC1758 only).

P1[14] — General purpose digital input/output pin.

ENET_RX_ER — Ethernet receive error. (LPC1758 only).

P1[15] — General purpose digital input/output pin.

ENET_REF_CLK — Ethernet reference clock. (LPC1758 only).

P1[18] — General purpose digital input/output pin.

P1[1]/

ENET_TXD1

I/O

O

P1[4]/

ENET_TX_EN

I/O

O

P1[8]/

ENET_CRS

I/O

I

P1[9]/

ENET_RXD0

I/O

I

P1[10]/

ENET_RXD1

I/O

I

P1[14]/

ENET_RX_ER

I/O

I

P1[15]/

ENET_REF_CLK

I/O

I

P1[18]/

I/O

O

USB_UP_LED/

PWM1[1]/

CAP1[0]

USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is

configured (non-control endpoints enabled). It is HIGH when the device is not

configured or during global suspend.

O

I

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

CAP1[0] — Capture input for Timer 1, channel 0.

LPC1759_58_56_54_52_51_4

Product data sheet

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8 of 64

LPC1759/58/56/54/52/51

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

26^[1]

Type

I/O

O

Description

P1[19]/MCOA0/

USB_PPWR

CAP1[1]

P1[19] — General purpose digital input/output pin.

MCOA0 — Motor control PWM channel 0, output A.

USB_PPWR — Port Power enable signal for USB port. (LPC1759/58/56/54 only).

CAP1[1] — Capture input for Timer 1, channel 1.

O

I

P1[20]/MCI0/

PWM1[2]/SCK0

27^[1]

28^[1]

29^[1]

30^[1]

I/O

I

P1[20] — General purpose digital input/output pin.

MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface

PHA input.

O

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

SCK0 — Serial clock for SSP0.

I/O

O

P1[22]/MCOB0/

USB_PWRD/

MAT1[0]

P1[22] — General purpose digital input/output pin.

MCOB0 — Motor control PWM channel 0, output B.

I

USB_PWRD — Power Status for USB port (host power switch).

(LPC1759/58/56/54 only).

O

I/O

I

MAT1[0] — Match output for Timer 1, channel 0.

P1[23] — General purpose digital input/output pin.

P1[23]/MCI1/

PWM1[4]/MISO0

MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface

PHB input.

O

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

MISO0 — Master In Slave Out for SSP0.

I/O

I

P1[24]/MCI2/

PWM1[5]/MOSI0

P1[24] — General purpose digital input/output pin.

MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface

INDEX input.

O

I/O

O

I/O

O

I

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

MOSI0 — Master Out Slave in for SSP0.

P1[25]/MCOA1/

MAT1[1]

31^[1]

32^[1]

P1[25] — General purpose digital input/output pin.

MCOA1 — Motor control PWM channel 1, output A.

MAT1[1] — Match output for Timer 1, channel 1.

P1[26] — General purpose digital input/output pin.

MCOB1 — Motor control PWM channel 1, output B.

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

CAP0[0] — Capture input for Timer 0, channel 0.

P1[28] — General purpose digital input/output pin.

MCOA2 — Motor control PWM channel 2, output A.

PCAP1[0] — Capture input for PWM1, channel 0.

MAT0[0] — Match output for Timer 0, channel 0.

P1[29] — General purpose digital input/output pin.

MCOB2 — Motor control PWM channel 2, output B.

PCAP1[1] — Capture input for PWM1, channel 1.

MAT0[1] — Match output for Timer 0, channel 1.

P1[26]/MCOB1/

PWM1[6]/CAP0[0]

P1[28]/MCOA2/

PCAP1[0]/

MAT0[0]

35^[1]

I/O

O

I

O

I/O

O

I

P1[29]/MCOB2/

PCAP1[1]/

MAT0[1]

36^[1]

O

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

9 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

18^[2]

Type

I/O

I

Description

P1[30]/V_BUS

AD0[4]

/

P1[30] — General purpose digital input/output pin.

V_BUS— Monitors the presence of USB bus power.

Note: This signal must be HIGH for USB reset to occur.

AD0[4] — A/D converter 0, input 4.

I

P1[31]/SCK1/

AD0[5]

17^[2]

I/O

I

P1[31] — General purpose digital input/output pin.

SCK1 — Serial Clock for SSP1.

AD0[5] — A/D converter 0, input 5.

P2[0] to P2[31]

I/O

Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 2 pins depends upon the pin function selected via the pin connect

block. Some port pins are not available on the LQFP80 package.

P2[0]/PWM1[1]/

TXD1

60^[1]

59^[1]

58^[1]

I/O

O

I/O

O

I

P2[0] — General purpose digital input/output pin.

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

TXD1 — Transmitter output for UART1.

P2[1]/PWM1[2]/

RXD1

P2[1] — General purpose digital input/output pin.

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

RXD1 — Receiver input for UART1.

P2[2]/PWM1[3]/

CTS1/

TRACEDATA[3]

I/O

O

I

P2[2] — General purpose digital input/output pin.

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

CTS1 — Clear to Send input for UART1.

O

I/O

O

I

TRACEDATA[3] — Trace data, bit 3.

P2[3]/PWM1[4]/

DCD1/

TRACEDATA[2]

55^[1]

54^[1]

53^[1]

P2[3] — General purpose digital input/output pin.

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

DCD1 — Data Carrier Detect input for UART1.

TRACEDATA[2] — Trace data, bit 2.

O

I/O

O

I

P2[4]/PWM1[5]/

DSR1/

TRACEDATA[1]

P2[4] — General purpose digital input/output pin.

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

DSR1 — Data Set Ready input for UART1.

O

I/O

O

TRACEDATA[1] — Trace data, bit 1.

P2[5]/PWM1[6]/

DTR1/

TRACEDATA[0]

P2[5] — General purpose digital input/output pin.

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an

RS-485/EIA-485 output enable signal.

O

I/O

I

TRACEDATA[0] — Trace data, bit 0.

P2[6]/PCAP1[0]/

RI1/TRACECLK

52^[1]

P2[6] — General purpose digital input/output pin.

PCAP1[0] — Capture input for PWM1, channel 0.

RI1 — Ring Indicator input for UART1.

I

O

I/O

I

TRACECLK — Trace Clock.

P2[7]/RD2/

RTS1

51^[1]

P2[7] — General purpose digital input/output pin.

RD2 — CAN2 receiver input. (LPC1759/58/56 only).

O

RTS1 — Request to Send output for UART1. Can also be configured to be an

RS-485/EIA-485 output enable signal.

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Table 3.

Symbol

Pin description …continued

50^[1]

Type

I/O

O

Description

P2[8]/TD2/

TXD2

P2[8] — General purpose digital input/output pin.

TD2 — CAN2 transmitter output. (LPC1759/58/56 only).

TXD2 — Transmitter output for UART2.

O

P2[9]/

USB_CONNECT/

RXD2

49^[1]

I/O

O

P2[9] — General purpose digital input/output pin.

USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under

software control. Used with the SoftConnect USB feature.

I

RXD2 — Receiver input for UART2.

P2[10]/EINT0/NMI 41^[5]

I/O

P2[10] — General purpose digital input/output pin.

Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take

over control of the part after a reset.

I

EINT0 — External interrupt 0 input.

NMI — Non-maskable interrupt input.

I

P4[0] to P4[31]

I/O

Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 4 pins depends upon the pin function selected via the pin connect

block. Some port pins are not available on the LQFP80 package.

P4[28]/RX_MCLK/ 65^[1]

MAT2[0]/TXD3

I/O

I

P4[28] — General purpose digital input/output pin.

RX_MCLK — I²S receive master clock. (LPC1759/58/56 only).

MAT2[0] — Match output for Timer 2, channel 0.

TXD3 — Transmitter output for UART3.

O

I/O

I

P4[29]/TX_MCLK/ 68^[1]

MAT2[1]/RXD3

P4[29] — General purpose digital input/output pin.

TX_MCLK — I²S transmit master clock. (LPC1759/58/56 only).

MAT2[1] — Match output for Timer 2, channel 1.

RXD3 — Receiver input for UART3.

O

I

TDO/SWO

1^[1]

O

I

TDO — Test Data out for JTAG interface.

SWO — Serial wire trace output.

TDI

2^[1]

3^[1]

TDI — Test Data in for JTAG interface.

TMS/SWDIO

I

TMS — Test Mode Select for JTAG interface.

SWDIO — Serial wire debug data input/output.

TRST — Test Reset for JTAG interface.

I/O

I

TRST

4^[1]

5^[1]

TCK/SWDCLK

I

TCK — Test Clock for JTAG interface.

I

SWDCLK — Serial wire clock.

RSTOUT

RESET

11

O

RSTOUT — This is a 3.3 V pin. LOW on this pin indicates

LPC1759/58/56/54/52/51 being in Reset state.

14^[6]

I

External reset input: A LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

RTCX1

RTCX2

V_SS

19^[7][8]

20^[7][8]

13^[7]

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator amplifier.

O

I

Input to the RTC oscillator circuit.

15^[7]

O

I

Output from the RTC oscillator circuit.

ground: 0 V reference.

24, 33,

43, 57,

66, 78

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Table 3.

Symbol

V_SSA

Pin description …continued

Type

Description

analog ground: 0 V reference. This should nominally be the same voltage as V_SS,

9

I

but should be isolated to minimize noise and error.

V_DD(3V3)

V_DD(REG)(3V3)

V_DDA

21, 42,

56, 77

I

3.3 V supply voltage: This is the power supply voltage for the I/O ports.

34, 67

3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip

voltage regulator only.

8

analog 3.3 V pad supply voltage: This should be nominally the same voltage as

V_DD(3V3)but should be isolated to minimize noise and error. This voltage is used to

power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are

not used.

VREFP

10

I

ADC positive reference voltage: This should be nominally the same voltage as

V_DDAbut should be isolated to minimize noise and error. Level on this pin is used

as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and

DAC are not used.

VREFN

VBAT

12

16

I

ADC negative reference voltage: This should be nominally the same voltage as

V_SSbut should be isolated to minimize noise and error. Level on this pin is used as

a reference for ADC and DAC.

RTC pin power supply: 3.3 V on this pin supplies the power to the RTC

peripheral.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,

digital section of the pad is disabled and the pin is not 5 V tolerant.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[5] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[6] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[7] Pad provides special analog functionality.

[8] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

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7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the

system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus

dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of

two core buses allows for simultaneous operations if concurrent operations target different

devices.

The LPC1759/58/56/54/52/51 use a multi-layer AHB matrix to connect the ARM

Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slaves ports of the matrix to be

accessed simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptable/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller,

and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual that can be found on official ARM website.

7.3 On-chip flash program memory

The LPC1759/58/56/54/52/51 contain up to 512 kB of on-chip flash memory. A new

two-port flash accelerator maximizes performance for use with the two fast AHB-Lite

buses.

7.4 On-chip SRAM

The LPC1759/58/56/54/52/51 contain a total of up to 64 kB on-chip static RAM memory.

This includes the main 32/16/8 kB SRAM, accessible by the CPU and DMA controller on a

higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a

separate slave port on the AHB multilayer matrix.

This architecture allows CPU and DMA accesses to be spread over three separate RAMs

that can be accessed simultaneously.

7.5 Memory Protection Unit (MPU)

The LPC1759/58/56/54/52/51 have a Memory Protection Unit (MPU) which can be used

to improve the reliability of an embedded system by protecting critical data within the user

application.

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The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to 8 regions each of which can be

divided into 8 subregions. Accesses to memory locations that are not defined in the MPU

regions, or not permitted by the region setting, will cause the Memory Management Fault

exception to take place.

7.6 Memory map

The LPC1759/58/56/54/52/51 incorporate several distinct memory regions, shown in the

following figures. Figure 3 shows the overall map of the entire address space from the

user program viewpoint following reset. The interrupt vector area supports address

remapping.

The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.

The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

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7.7 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.7.1 Features

• Controls system exceptions and peripheral interrupts

• In the LPC1759/58/56/54/52/51, the NVIC supports 33 vectored interrupts

• 32 programmable interrupt priority levels, with hardware priority level masking

• Relocatable vector table

• Non-Maskable Interrupt (NMI)

• Software interrupt generation

7.7.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any pin on Port 0 and Port 2 (total of 30 pins) regardless of the selected function, can be

programmed to generate an interrupt on a rising edge, a falling edge, or both.

7.8 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or

no resistor enabled.

7.9 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected

LPC1759/58/56/54/52/51 peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. The source and

destination areas can each be either a memory region or a peripheral, and can be

accessed through the AHB master. The GPDMA controller allows data transfers between

the USB and Ethernet (LPC1758 only) controllers and the various on-chip SRAM areas.

The supported APB peripherals are SSP0/1, all UARTs, the I²S-bus interface, the ADC,

and the DAC. Two match signals for each timer can be used to trigger DMA transfers.

Remark: Note that the DAC is not available on the LPC1752/51, and the I²S-bus interface

is not available on the LPC1754/52/51.

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7.9.1 Features

• Eight DMA channels. Each channel can support an unidirectional transfer.

• 16 DMA request lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers are supported.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

• One AHB bus master for transferring data. The interface transfers data when a DMA

request goes active.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

• Internal four-word FIFO per channel.

• Supports 8, 16, and 32-bit wide transactions.

• Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.10 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

LPC1759/58/56/54/52/51 use accelerated GPIO functions:

• GPIO registers are accessed through the AHB multilayer bus so that the fastest

possible I/O timing can be achieved.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

• Support for Cortex-M3 bit banding.

• Support for use with the GPDMA controller.

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Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can

be programmed to generate an interrupt on a rising edge, a falling edge, or both. The

edge detection is asynchronous, so it may operate when clocks are not present such as

during Power-down mode. Each enabled interrupt can be used to wake up the chip from

Power-down mode.

7.10.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Pull-up/pull-down resistor configuration and open-drain configuration can be

programmed through the pin connect block for each GPIO pin.

7.11 Ethernet (LPC1758 only)

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, flow control, control frames, hardware acceleration for transmit retry, receive

packet filtering and wake-up on LAN activity. Automatic frame transmission and reception

with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus

through the AHB-multilayer matrix to access the various on-chip SRAM blocks for

Ethernet data, control, and status information.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII

(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial

bus.

The Ethernet block supports bus clock rates of up to 100 MHz.

7.11.1 Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.

– Flexible transmit and receive frame options.

– Virtual Local Area Network (VLAN) frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

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– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Cyclic

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

• Physical interface:

– Attachment of external PHY chip through standard RMII interface.

– PHY register access is available via the MIIM interface.

7.12 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

The LPC1759/58/56/54 USB interface includes a device, Host, and OTG controller with

on-chip PHY for device and Host functions. The OTG switching protocol is supported

through the use of an external controller. Details on typical USB interfacing solutions can

be found in Section 14.1. The LPC1752/51 include a USB device controller only.

7.12.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory, and a

DMA controller. The serial interface engine decodes the USB data stream and writes data

to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled. When

enabled, the DMA controller transfers data between the endpoint buffer and the on-chip

SRAM.

7.12.1.1 Features

• Fully compliant with USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

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• While USB is in the Suspend mode, the LPC1759/58/56/54/52/51 can enter one of the

reduced power modes and wake up on USB activity.

• Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.

• Allows dynamic switching between CPU-controlled slave and DMA modes.

• Double buffer implementation for Bulk and Isochronous endpoints.

7.12.2 USB host controller (LPC1759/58/56/54 only).

The host controller enables full- and low-speed data exchange with USB devices attached

to the bus. It consists of a register interface, a serial interface engine, and a DMA

controller. The register interface complies with the Open Host Controller Interface (OHCI)

specification.

7.12.2.1 Features

• OHCI compliant.

• One downstream port.

• Supports port power switching.

7.12.3 USB OTG controller (LPC1759/58/56/54 only).

USB OTG is a supplement to the USB 2.0 specification that augments the capability of

existing mobile devices and USB peripherals by adding host functionality for connection to

USB peripherals.

The OTG Controller integrates the host controller, device controller, and a master-only

I²C-bus interface to implement OTG dual-role device functionality. The dedicated I²C-bus

interface controls an external OTG transceiver.

7.12.3.1 Features

• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

1.0a.

• Hardware support for Host Negotiation Protocol (HNP).

• Includes a programmable timer required for HNP and Session Request Protocol

(SRP).

• Supports any OTG transceiver compliant with the OTG Transceiver Specification

(CEA-2011), Rev. 1.0.

7.13 CAN controller and acceptance filters

The Controller Area Network (CAN) is a serial communications protocol which efficiently

supports distributed real-time control with a very high level of security. Its domain of

application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a gateway, switch, or router among a number of CAN buses in

industrial or automotive applications.

Remark: LPC1754/52/51 have only one CAN bus.

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7.13.1 Features

• One or two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit)

receive identifiers for all CAN buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identifiers.

• FullCAN messages can generate interrupts.

7.14 12-bit ADC

The LPC1759/58/56/54/52/51 contain one ADC. It is a single 12-bit successive

approximation ADC with six channels and DMA support.

7.14.1 Features

• 12-bit successive approximation ADC.

• Input multiplexing among 6 pins.

• Power-down mode.

• Measurement range VREFN to VREFP.

• 12-bit conversion rate: 200 kHz.

• Individual channels can be selected for conversion.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or Timer Match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

• DMA support.

7.15 10-bit DAC (LPC1759/58/56/54 only)

The DAC allows to generate a variable analog output. The maximum output value of the

DAC is VREFP.

7.15.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

• Dedicated conversion timer

• DMA support

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7.16 UARTs

32-bit ARM Cortex-M3 microcontroller

The LPC1759/58/56/54/52/51 each contain four UARTs. In addition to standard transmit

and receive data lines, UART1 also provides a full modem control handshake interface

and support for RS-485/9-bit mode allowing both software address detection and

automatic address detection using 9-bit mode.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.16.1 Features

• Maximum UART data bit rate of 6.25 MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

• Support for RS-485/9-bit/EIA-485 mode (UART1).

• UART3 includes an IrDA mode to support infrared communication.

• All UARTs have DMA support.

7.17 SPI serial I/O controller

The LPC1759/58/56/54/52/51 contain one SPI controller. SPI is a full duplex serial

interface designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the

slave, and the slave always sends 8 bits to 16 bits of data to the master.

7.17.1 Features

• Maximum SPI data bit rate of 12.5 Mbit/s

• Compliant with SPI specification

• Synchronous, serial, full duplex communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

7.18 SSP serial I/O controller

The LPC1759/58/56/54/52/51 contain two SSP controllers. The SSP controller is capable

of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters

and slaves on the bus. Only a single master and a single slave can communicate on the

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bus during a given data transfer. The SSP supports full duplex transfers, with frames of

4 bits to 16 bits of data flowing from the master to the slave and from the slave to the

master. In practice, often only one of these data flows carries meaningful data.

7.18.1 Features

• Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.19 I²C-bus serial I/O controllers

The LPC1759/58/56/54/52/51 each contain two I²C-bus controllers.

The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.19.1 Features

• I²C1 and I²C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I²C-bus).

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

• Both I²C-bus controllers support multiple address recognition and a bus monitor

mode.

7.20 I²S-bus serial I/O controllers (LPC1759/58/56 only)

The I²S-bus provides a standard communication interface for digital audio applications.

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The I²S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I²S connection has one master, which is always the

master, and one slave. The I²S-bus interface provides a separate transmit and receive

channel, each of which can operate as either a master or a slave.

7.20.1 Features

• The interface has separate input/output channels each of which can operate in master

or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,

96) kHz.

• Support for an audio master clock.

• Configurable word select period in master mode (separately for I²S input and output).

• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

to the GPDMA block.

• Controls include reset, stop and mute options separately for I²S input and I²S output.

7.21 General purpose 32-bit timers/external event counters

The LPC1759/58/56/54/52/51 include four 32-bit timer/counters. The timer/counter is

designed to count cycles of the system derived clock or an externally-supplied clock. It

can optionally generate interrupts, generate timed DMA requests, or perform other actions

at specified timer values, based on four match registers. Each timer/counter also includes

two capture inputs to trap the timer value when an input signal transitions, optionally

generating an interrupt.

7.21.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

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• Up to two match registers can be used to generate timed DMA requests.

7.22 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC1759/58/56/54/52/51. The Timer is

designed to count cycles of the system derived clock and optionally switch pins, generate

interrupts or perform other actions when specified timer values occur, based on seven

match registers. The PWM function is in addition to these features, and is based on match

register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the PWMMR0 match register controls the PWM cycle rate. The other match

registers control the two PWM edge positions. Additional double edge controlled PWM

outputs require only two match registers each, since the repetition rate is the same for all

PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

7.22.1 Features

• LPC1759/58/56/54/52/51 has one PWM block with Counter or Timer operation (may

use the peripheral clock or one of the capture inputs as the clock source).

• Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the

output is a constant low. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

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• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler

if the PWM mode is not enabled.

7.23 Motor control PWM

The motor control PWM is a specialized PWM supporting 3-phase motors and other

combinations. Feedback inputs are provided to automatically sense rotor position and use

that information to ramp speed up or down. At the same time, the motor control PWM is

highly configurable for other generalized timing, counting, capture, and compare

applications.

7.24 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two signals, the user can track the position, direction of rotation, and

velocity. In addition, a third channel, or index signal, can be used to reset the position

counter. The quadrature encoder interface decodes the digital pulses from a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In

addition, the QEI can capture the velocity of the encoder wheel.

7.24.1 Features

• Tracks encoder position.

• Increments/decrements depending on direction.

• Programmable for 2× or 4× position counting.

• Velocity capture using built-in timer.

• Velocity compare function with “less than” interrupt.

• Uses 32-bit registers for position and velocity.

• Three position compare registers with interrupts.

• Index counter for revolution counting.

• Index compare register with interrupts.

• Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

• Digital filter with programmable delays for encoder input signals.

• Can accept decoded signal inputs (clk and direction).

• Connected to APB.

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7.25 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 32-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.25.1 Features

• 32-bit counter running from PCLK. Counter can be free-running or be reset by a

generated interrupt.

• 32-bit compare value.

• 32-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

7.26 ARM Cortex-M3 system tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval. In the LPC1759/58/56/54/52/51, this

timer can be clocked from the internal AHB clock or from a device pin.

7.27 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.27.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK)× 256 × 4) to (T_cy(WDCLK)× 2³²× 4) in

multiples of T_cy(WDCLK)× 4.

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC)

oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of

potential timing choices of Watchdog operation under different power reduction

conditions. It also provides the ability to run the WDT from an entirely internal source

that is not dependent on an external crystal and its associated components and wiring

for increased reliability.

• Includes lock/safe feature.

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7.28 RTC and backup registers

The RTC is a set of counters for measuring time when system power is on, and optionally

when it is off. The RTC on the LPC1759/58/56/54/52/51 is designed to have extremely low

power consumption, i.e. less than 1 μA. The RTC will typically run from the main chip

power supply, conserving battery power while the rest of the device is powered up. When

operating from a battery, the RTC will continue working down to 2.1 V. Battery power can

be provided from a standard 3 V Lithium button cell.

An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion

of the RTC, moving most of the power consumption out of the time counting function.

The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way

that will provide less than 1 second per day error when operated at a constant voltage and

temperature.

The RTC contains a small set of backup registers (20 bytes) for holding data while the

main part of the LPC1759/58/56/54/52/51 is powered off.

The RTC includes an alarm function that can wake up the LPC1759/58/56/54/52/51 from

all reduced power modes with a time resolution of 1 s.

7.28.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

• Periodic interrupts can be generated from increments of any field of the time registers.

• Backup registers (20 bytes) powered by VBAT.

• RTC power supply is isolated from the rest of the chip.

7.29 Clocking and power control

7.29.1 Crystal oscillators

The LPC1759/58/56/54/52/51 include three independent oscillators. These are the main

oscillator, the IRC oscillator, and the RTC oscillator. Each oscillator can be used for more

than one purpose as required in a particular application. Any of the three clock sources

can be chosen by software to drive the main PLL and ultimately the CPU.

Following reset, the LPC1759/58/56/54/52/51 will operate from the Internal RC oscillator

until switched by software. This allows systems to operate without any external crystal and

the bootloader code to operate at a known frequency.

See Figure 4 for an overview of the LPC1759/58/56/54/52/51 clock generation.

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LPC17xx

usbclk

(48 MHz)

USB PLL

USB

CLOCK

DIVIDER

MAIN

OSCILLATOR

USB BLOCK

MAIN PLL

pllclk

USB clock config

(USBCLKCFG)

USB PLL enable

cclk

CPU

CLOCK

DIVIDER

system

clock

select

ARM

CORTEX-M3

main PLL enable

ETHERNET

BLOCK

(CLKSRCSEL)

CPU clock config

(CCLKCFG)

INTERNAL

RC

OSCILLATOR

DMA

GPIO

NVIC

WATCHDOG

TIMER

CCLK/8

CCLK/6

CCLK/4

CCLK/2

CCLK

32 kHz

PERIPHERAL

CLOCK

GENERATOR

pclk

WDT

APB peripherals

RTC

rtclk = 1Hz

OSCILLATOR

REAL-TIME

CLOCK

002aad947

Fig 4. LPC1759/58/56/54/52/51 clocking generation block diagram

7.29.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC1759/58/56/54/52/51 use the IRC as the clock

source. Software may later switch to one of the other available clock sources.

7.29.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using the

PLL. The main oscillator also provides the clock source for the dedicated USB PLL.

The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the main

PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock

frequency is referred to as CCLK elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The

clock frequency for each peripheral can be selected individually and is referred to as

PCLK. Refer to Section 7.29.2 for additional information.

7.29.1.3 RTC oscillator

The RTC oscillator can be used as the clock source for the RTC block, the main PLL,

and/or the CPU.

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7.29.2 Main PLL (PLL0)

The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input

frequency is multiplied up to a high frequency, then divided down to provide the actual

clock used by the CPU and/or the USB block.

The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a

value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range

of output frequencies from the same input frequency.

Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the

range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to

550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a

phase-frequency detector to compare the divided CCO output to the multiplier input. The

error value is used to adjust the CCO frequency.

The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down

mode. PLL0 is enabled by software only. The program must configure and activate the

PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source.

7.29.3 USB PLL (PLL1)

The LPC1759/58/56/54/52/51 contain a second, dedicated USB PLL1 to provide clocking

for the USB interface.

The PLL1 receives its clock input from the main oscillator only and provides a fixed

48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the

PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main

PLL0.

The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The

input frequency is multiplied up the range of 48 MHz for the USB clock using a Current

Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle.

7.29.4 Wake-up timer

The LPC1759/58/56/54/52/51 begin operation at power-up and when awakened from

Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip

operation to resume quickly. If the main oscillator or the PLL is needed by the application,

software will need to enable these features and wait for them to stabilize before they are

used as a clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the wake-up Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some event caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufficient amplitude to drive the clock logic. The amount of time depends on many factors,

including the rate of V_DD(3V3)ramp (in the case of power on), the type of crystal and its

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electrical characteristics (if a quartz crystal is used), as well as any other external circuitry

(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.29.5 Power control

The LPC1759/58/56/54/52/51 support a variety of power control features. There are four

special modes of processor power reduction: Sleep mode, Deep-sleep mode,

Power-down mode, and Deep power-down mode. The CPU clock rate may also be

controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering

the CPU clock divider value. This allows a trade-off of power versus processing speed

based on application requirements. In addition, Peripheral Power Control allows shutting

down the clocks to individual on-chip peripherals, allowing fine tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Each of the peripherals has its own clock divider which provides even

better power control.

Integrated PMU (Power Management Unit) automatically adjust internal regulators to

minimize power consumption during Sleep, Deep sleep, Power-down, and Deep

power-down modes.

The LPC1759/58/56/54/52/51 also implement a separate power domain to allow turning

off power to the bulk of the device while maintaining operation of the RTC and a small set

of registers for storing data during any of the power-down modes.

7.29.5.1 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.29.5.2 Deep-sleep mode

In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.

The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later.

The RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The CCLK and

USB clock dividers automatically get reset to zero.

The Deep-sleep mode can be terminated and normal operation resumed by either a

Reset or certain specific interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power

consumption to a very low value. Power to the flash memory is left on in Deep-sleep

mode, allowing a very quick wake-up.

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On wake-up from Deep-sleep mode, the code execution and peripherals activities will

resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the

main external oscillator was used, the code execution will resume when 4096 cycles

expire. PLL and clock dividers need to be reconfigured accordingly.

7.29.5.3 Power-down mode

Power-down mode does everything that Deep-sleep mode does, but also turns off the

power to the IRC oscillator and the flash memory. This saves more power but requires

waiting for resumption of flash operation before execution of code or data access in the

flash memory can be accomplished.

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60 μs to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. In the meantime, the

flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 μs flash start-up

time. When it times out, access to the flash will be allowed. Users need to reconfigure the

PLL and clock dividers accordingly.

7.29.5.4 Deep power-down mode

The Deep power-down mode can only be entered from the RTC block. In Deep

power-down mode, power is shut off to the entire chip with the exception of the RTC

module and the RESET pin.

The LPC1759/58/56/54/52/51 can wake up from Deep power-down mode via the RESET

pin or an alarm match event of the RTC.

7.29.5.5 Wakeup interrupt controller

The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any

enabled priority interrupt that can occur while the clocks are stopped in Deep sleep,

Power-down, and Deep power-down modes.

The Wakeup Interrupt Controller (WIC) works in connection with the Nested Vectored

Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep

power-down mode, the NVIC sends a mask of the current interrupt situation to the

WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority

to be serviced immediately. With this information, the WIC simply notices when one of the

interrupts has occurred and then it wakes up the CPU.

The Wakeup Interrupt Controller (WIC) eliminates the need to periodically wake up the

CPU and poll the interrupts resulting in additional power savings.

7.29.6 Peripheral power control

A power control for peripherals feature allows individual peripherals to be turned off if they

are not needed in the application, resulting in additional power savings.

7.29.7 Power domains

The LPC1759/58/56/54/52/51 provide two independent power domains that allow the bulk

of the device to have power removed while maintaining operation of the RTC and the

backup Registers.

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On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3.3 V (V_DD(3V3)) pins, while

the V_DD(REG)(3V3)pin powers the on-chip voltage regulator which in turn provides power to

the CPU and most of the peripherals.

Depending on the LPC1759/58/56/54/52/51 application, a design can use two power

options to manage power consumption.

The first option assumes that power consumption is not a concern and the design ties the

V

_DD(3V3)and V_DD(REG)(3V3)pins together. This approach requires only one 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (V_DD(3V3)) and

a dedicated 3.3 V supply for the CPU (V_DD(REG)(3V3)). Having the on-chip voltage regulator

powered independently from the I/O pad ring enables shutting down of the I/O pad power

supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of

power to operate, which can be supplied by an external battery. The device core power

(V_DD(REG)(3V3)) is used to operate the RTC whenever V_DD(REG)(3V3)is present. Therefore,

there is no power drain from the RTC battery when V_DD(REG)(3V3)is available.

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32-bit ARM Cortex-M3 microcontroller

LPC17xx

V

to I/O pads

DD(3V3)

to core

V

SS

3.3 V REGULATOR

to memories,

peripherals,

oscillators,

PLLs

V

DD(REG)(3V3)

MAIN POWER DOMAIN

ULTRA-LOW

POWER

REGULATOR

POWER

SELECTOR

VBAT

BACKUP REGISTERS

REAL-TIME CLOCK

RTCX1

RTCX2

32 kHz

OSCILLATOR

RTC POWER DOMAIN

DAC

ADC

V

DDA

VREFP

VREFN

V

SSA

ADC POWER DOMAIN

002aad978

Fig 5. Power distribution

7.30 System control

7.30.1 Reset

Reset has four sources on the LPC1759/58/56/54/52/51: the RESET pin, the Watchdog

reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET

pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the

operating voltage attains a usable level, starts the Wake-up timer (see description in

Section 7.29.4), causing reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a fixed number of clocks have passed, and the flash controller

has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

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32-bit ARM Cortex-M3 microcontroller

7.30.2 Brownout detection

The LPC1759/58/56/54/52/51 include 2-stage monitoring of the voltage on the

_DD(REG)(3V3)pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to

V

the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt

Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor

the signal by reading a dedicated status register.

The second stage of low-voltage detection asserts reset to inactivate the

LPC1759/58/56/54/52/51 when the voltage on the V_DD(REG)(3V3)pins falls below 2.65 V.

This reset prevents alteration of the flash as operation of the various elements of the chip

would otherwise become unreliable due to low voltage. The BOD circuit maintains this

reset down below 1 V, at which point the power-on reset circuitry maintains the overall

reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

7.30.3 Code security (Code Read Protection - CRP)¹

This feature of the LPC1759/58/56/54/52/51 allows user to enable different levels of

security in the system so that access to the on-chip flash and use of the JTAG and ISP

can be restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

7.30.4 APB interface

The APB peripherals are split into two separate APB buses in order to distribute the bus

bandwidth and thereby reducing stalls caused by contention between the CPU and the

GPDMA controller.

1. LPC1751FBD80 with device ID 25001110 does not support CRP feature. LPC1751FBD80 with device ID 25001118 does support

CRP. See errata note in ES_LPC1751.

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7.30.5 AHB multilayer matrix

The LPC1759/58/56/54/52/51 use an AHB multilayer matrix. This matrix connects the

instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash

memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access

all of these memories. The peripheral DMA controllers, Ethernet (LPC1758 only) and

USB, can access all SRAM blocks. Additionally, the matrix connects the CPU system bus

and all of the DMA controllers to the various peripheral functions.

7.30.6 External interrupt inputs

The LPC1759/58/56/54/52/51 include up to 30 edge sensitive interrupt inputs combined

with one level sensitive external interrupt input as selectable pin function. The external

interrupt input can optionally be used to wake up the processor from Power-down mode.

7.30.7 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

Register contained in the NVIC.

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 128 word (512 byte) boundary because the

NVIC on the LPC1759/58/56/54/52/51 is configured for 128 total interrupts.

7.31 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

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8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

Parameter

Conditions

Min

Max

Unit

V_DD(3V3)

supply voltage (3.3 V)

core and external

rail

2.4

3.6

V

V_DD(REG)(3V3)regulator supply voltage (3.3 V)

2.4

3.6

V

V_DDA

analog 3.3 V pad supply voltage

input voltage on pin VBAT

input voltage on pin VREFP

analog input voltage

−0.5

+4.6

+5.1

V_i(VBAT)

V_i(VREFP)

V_IA

for the RTC

on ADC related

pins

[2]

V_I

input voltage

5 V tolerant I/O

pins; only valid

when the V_DD(3V3)

supply voltage is

present

−0.5

+5.5

V

[2][3]

other I/O pins

−0.5

V_DD(3V3)

0.5

+

V

[4]

I_DD

supply current

per supply pin

per ground pin

-

100

mA

I_SS

ground current

I/O latch-up current

I_latch

−(0.5V_DD(3V3)) < V_I

< (1.5V_DD(3V3));

T_j< 125 °C

[5]

[6]

T_stg

storage temperature

−65

+150

1.5

°C

P_tot(pack)

total power dissipation (per package)

based on package

heat transfer, not

device power

-

W

consumption

V_ESD

electrostatic discharge voltage

human body

−4000

+4000

V

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] Dependent on package type.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

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9. Thermal characteristics

9.1 Thermal characteristics

The average chip junction temperature, T_J(°C), can be calculated using the following

equation:

T_J= T_amb+ (P_D× R_{th(j – a)}

)

(1)

• T_amb= ambient temperature (°C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (°C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 5.

Thermal characteristics

V_DD= 2.4 V to 3.6 V; T_amb= −40 °C to +85 °C unless otherwise specified;

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_j(max)

maximum junction

temperature

-

125

°C

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10. Static characteristics

Table 6.

Static characteristics

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Supply pins

V_DD(3V3)

supply voltage (3.3 V)

core and external rail

2.4

3.3

3.6

V

V_DD(REG)(3V3)

regulator supply voltage

(3.3 V)

V_DDA

analog 3.3 V pad supply

voltage

2.7

2.1

2.7

3.3

3.6

V

[2]

V_i(VBAT)

input voltage on pin

VBAT

3.6

V_i(VREFP)

I_DD(REG)(3V3)

input voltage on pin

VREFP

V_DDA

regulator supply current active mode; code

(3.3 V)

while(1){}

executed from flash; all

peripherals disabled;

PCLK = ^CCLK

⁄

8

[3]

CCLK = 12 MHz; PLL

disabled

-

7

-

mA

CCLK = 100 MHz; PLL

enabled

42

67

[3][4]

CCLK = 120 MHz; PLL

enabled

[3][5]

[3][6]

[3]

Sleep mode

-

2

-

mA

μA

nA

Deep sleep mode

Power-down mode

240

31

Deep power-down mode;

RTC not running

517

I_BAT

battery supply current

Deep power-down mode;

RTC running

[7]

[8]

V_DD(REG)(3V3)present

-

134

-

nA

V_DD(REG)(3V3)not

present

634

40

10

38

24

-

nA

[9]

I_DD(IO)

I_DD(ADC)

I_I(ADC)

I/O supply current

ADC supply current

ADC input current

Deep sleep mode

Power-down mode

Deep power-down mode

Deep sleep mode

Power-down mode

Deep power-down mode

on pin VREFP

-

[9]

[10]

[11]

Deep sleep mode

Power-down mode

-

100

-

nA

Deep power-down

mode

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Table 6.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Standard port pins, RESET

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up

resistor disabled

-

3

μA

I_IH

HIGH-level input

current

V_I= V_DD(3V3); on-chip

pull-down resistor

disabled

I_OZ

OFF-state output

current

V_O= 0 V; V_O= V_DD(3V3)

on-chip pull-up/down

resistors disabled

;

-

3

μA

[12][13]

[14]

V_I

input voltage

pin configured to provide

a digital function

0

5.0

V

V_O

output voltage

output active

0

-

V_DD(3V3)

-

V

V_IH

HIGH-level input

voltage

2.0

V_IL

LOW-level input voltage

hysteresis voltage

-

0.8

V

V_hys

V_OH

0.4

-

[15]

[16]

HIGH-level output

voltage

I_OH= −4 mA

V_DD(3V3)

0.4

−

V_OL

I_OH

LOW-level output

voltage

I_OL= 4 mA

-

0.4

-

V

HIGH-level output

current

V_OH= V_DD(3V3)− 0.4 V

V_OL= 0.4 V

−4

4

-

mA

I_OL

LOW-level output

current

-

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

−45

50

LOW-level short-circuit V_OL= V_DD(3V3)

output current

-

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

−15

0

50

−50

0

150

−85

0

μA

V_I= 0 V

V_DD(3V3)< V_I< 5 V

Oscillator pins

V_i(XTAL1)

input voltage on pin

XTAL1

−0.5

1.8

1.95

V

V_o(XTAL2)

V_i(RTCX1)

V_o(RTCX2)

output voltage on pin

XTAL2

input voltage on pin

RTCX1

output voltage on pin

RTCX2

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Table 6.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

USB pins

I_OZ

Parameter

Conditions

Min

Typ^[1]

Max

Unit

OFF-state output

current

0 V < V_I< 3.3 V

-

±10

μA

V_BUS

V_DI

bus supply voltage

-

5.25

-

V

differential input

|(D+) − (D−)|

0.2

sensitivity voltage

V_CM

differential common

mode voltage range

includes V_DIrange

0.8

-

2.5

2.0

V

V_th(rs)se

single-ended receiver

switching threshold

voltage

V_OL

LOW-level output

voltage for

low-/full-speed

R_Lof 1.5 kΩ to 3.6 V

R_Lof 15 kΩ to GND

-

0.18

3.5

V

V_OH

HIGH-level output

voltage (driven) for

low-/full-speed

2.8

C_trans

Z_DRV

transceiver capacitance pin to GND

-

20

pF

[17]

driver output

with 33 Ω series resistor;

steady state drive

36

44.1

Ω

impedance for driver

which is not high-speed

capable

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] The RTC typically fails when V_i(VBAT)drops below 1.6 V.

[3] V_DD(REG)(3V3)= 3.3 V; T_amb= 25 °C for all power consumption measurements.

[4] LPC1759 only.

[5] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = ^CCLK⁄₈.

[6] BOD disabled.

[7] On pin VBAT. I_DD(REG)(3V3)= 520 nA. V_DD(REG)(3V3)= 3.3 V; V_BAT= 3.3 V. T_amb= 25 °C.

[8] On pin VBAT. V_BAT= 3.3 V. T_amb= 25 °C.

[9] All internal pull-ups disabled. All pins configured as output and driven LOW. V_DD(3V3)= 3.3 V; T_amb= 25 °C.

[10] V_DDA= 3.3 V; T_amb= 25 °C.

[11] V_i(VREFP)= 3.3 V; T_amb= 25 °C.

[12] Including voltage on outputs in 3-state mode.

[13] V_DD(3V3)supply voltages must be present.

[14] 3-state outputs go into 3-state mode in Deep power-down mode.

[15] Accounts for 100 mV voltage drop in all supply lines.

[16] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[17] Includes external resistors of 33 Ω ± 1 % on D+ and D−.

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10.1 Electrical pin characteristics

002aaf112

3.6

V

OH

(V)

T = 85 °C

25 °C

−40 °C

3.2

2.8

2.4

2.0

0

8

16

24

I

(mA)

OH

Conditions: V_DD(REG)(3V3)= V_DD(3V3)= 3.3 V; standard port pins.

Fig 6. Typical HIGH-level output voltage V_OHversus HIGH-level output source current

I_OH

002aaf111

15

I

OL

T = 85 °C

25 °C

−40 °C

(mA)

10

5

0

0.2

0.4

0.6

V

OL

(V)

Conditions: V_DD(REG)(3V3)= V_DD(3V3)= 3.3 V; standard port pins.

Fig 7. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

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002aaf108

10

I

pu

(μA)

−10

−30

−50

−70

T = 85 °C

25 °C

−40 °C

0

1

2

3

4

5

V (V)

I

Conditions: V_DD(REG)(3V3)= V_DD(3V3)= 3.3 V; standard port pins.

Fig 8. Typical pull-up current I_puversus input voltage V_I

002aaf109

90

I

pd

(μA)

70

T = 85 °C

25 °C

−40 °C

50

30

10

−10

0

1

2

3

4

5

V (V)

I

Conditions: V_DD(REG)(3V3)= V_DD(3V3)= 3.3 V; standard port pins.

Fig 9. Typical pull-down current I_pdversus input voltage V_I

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11. Dynamic characteristics

11.1 Flash memory

Table 7.

Flash characteristics

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

N_endu

t_ret

Parameter

endurance

Conditions

Min

10000

10

Typ

Max

Unit

[1]

-

cycles

years

retention time

powered

unpowered

20

[1] Number of program/erase cycles.

11.2 External clock

Table 8.

Dynamic characteristic: external clock

T_amb= −40 °C to +85 °C; V_DD(3V3)over specified ranges.^[1]

Symbol

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk)× 0.4

-

ns

T_cy(clk)× 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 10. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

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11.3 Internal oscillators

Table 9.

Dynamic characteristic: internal oscillators

T_amb= −40 °C to +85 °C; 2.7 V ≤ V_DD(3V3)≤ 3.6 V.^[1]

Symbol

f_osc(RC)

f_i(RTC)

Parameter

Conditions

Min

3.96

-

Typ^[2]

4.00

Max

4.04

-

Unit

MHz

kHz

internal RC oscillator frequency

RTC input frequency

-

32.768

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

002aaf107

4.036

f

osc(RC)

(MHz)

4.032

4.028

4.024

4.020

4.016

VDD(3V) = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

−40

−15

10

35

60

85

temperature (°C)

Conditions: Frequency values are typical values. 4 MHz ± 1 % accuracy is guaranteed for

2.7 V ≤ V_DD(3V3)≤ 3.6 V and T_amb= −40 °C to +85 °C. Variations between parts may cause the IRC

to fall outside the 4 MHz ± 1 % accuracy specification for voltage below 2.7 V.

Fig 11. Internal RC oscillator frequency versus temperature

11.4 I/O pins

Table 10. Dynamic characteristic: I/O pins^[1]

T_amb= −40 °C to +85 °C; V_DD(3V3)over specified ranges.

Symbol

Parameter

rise time

fall time

Conditions

Min

3.0

2.5

Typ

Max

5.0

Unit

ns

t_r

t_f

pin configured as output

-

5.0

ns

[1] Applies to standard port pins and RESET pin.

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11.5 I²C-bus interface

Table 11. Dynamic characteristic: I²C-bus pins (Fast-mode Plus)

T_amb= −40 °C to +85 °C; V_DD(3V3)over specified ranges.^[1][2][3]

Symbol

f_SCL

Parameter

Conditions

Min

Typ

Max

1

Unit

MHz

ns

SCL clock frequency

fall time

-

t_f

-

45

-

t_SU;DAT

data set-up time

-

50

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] CCLK = PCLK = 20 MHz; I²C-bus interface configured in master mode.

[3] Bus capacitance C_bin pF (50 pF), external pull-up resistance = 218 Ω.

SDA

SCL

t

f

P

S

t

SU;DAT

002aae860

Fig 12. I²C-bus pins clock timing

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11.6 I²S-bus interface (LPC1759/58/56 only)

Table 12. Dynamic characteristics: I²S-bus interface pins

T_amb= −40 °C to +85 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

common to input and output

[1]

t_r

rise time

-

35

-

ns

-

t_f

fall time

-

t_WH

pulse width HIGH

on pins I2STX_CLK and

I2SRX_CLK

0.495 × T_cy(clk)

[1]

t_WL

pulse width LOW

on pins I2STX_CLK and

I2SRX_CLK

-

0.505 × T_cy(clk)ns

output

[1]

t_v(Q)

data output valid time

on pin I2STX_SDA;

on pin I2STX_WS

-

30

ns

input

t_su(D)

t_h(D)

[1]

data input set-up time

data input hold time

on pin I2SRX_SDA

3.5

4.0

-

ns

[1] CCLK = 20 MHz; peripheral clock to the I²S-bus interface PCLK = ^CCLK⁄₄; T_cy(clk)= 1600 ns, corresponds to the SCK signal in the I²S-bus

specification.

T

t

r

cy(clk)

f

I2STX_CLK

I2STX_SDA

t

WL

WH

t

v(Q)

I2STX_WS

002aad992

t

v(Q)

Fig 13. I²S-bus timing (output)

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32-bit ARM Cortex-M3 microcontroller

T

t

r

cy(clk)

f

I2SRX_CLK

t

WL

WH

I2SRX_SDA

I2SRX_WS

t

h(D)

su(D)

002aae159

t

su(D)

Fig 14. I²S-bus timing (input)

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11.7 SSP interface

Table 13. Dynamic characteristic: SSP interface

T_amb= 25 °C; V_DD(3V3)over specified ranges.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

t_{su(SPI_MISO)}

SPI_MISO set-up time

measured in SPI Master mode;

see Figure 15

30

-

ns

[1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz.

shifting edges

SCK

sampling edges

MOSI

MISO

t

su(SPI_MISO)

002aad326

Fig 15. SSP MISO line set-up time in SPI Master mode

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11.8 USB interface

Table 14. Dynamic characteristics: USB pins (full-speed)

C_L= 50 pF; R_pu= 1.5 kΩ on D+ to V_DD(3V3), unless otherwise specified.

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

t_r/ t_f

Min

8.5

7.7

-

Typ

Max

13.8

13.7

109

Unit

ns

t_r

-

t_f

ns

t_FRFM

differential rise and fall time

matching

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

1.3

160

−2

-

2.0

175

+5

V

t_FEOPT

t_FDEOP

see Figure 16

ns

source jitter for differential transition see Figure 16

to SE0 transition

t_JR1

receiver jitter to next transition

−18.5

−9

-

+18.5

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

+9

-

[1]

t_EOPR1

must reject as

EOP; see

Figure 16

40

t_EOPR2

EOP width at receiver

must accept as

EOP; see

82

-

ns

Figure 16

[1] Characterized but not implemented as production test. Guaranteed by design.

T

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × T

+ t

FDEOP

PERIOD

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 16. Differential data-to-EOP transition skew and EOP width

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11.9 SPI

32-bit ARM Cortex-M3 microcontroller

Table 15. Dynamic characteristics of SPI pins

T_amb= −40 °C to +85 °C.

Symbol

T_cy(PCLK)

T_SPICYC

t_SPICLKH

t_SPICLKL

SPI master

t_SPIDSU

t_SPIDH

Parameter

Min

Typ Max

Unit

ns

PCLK cycle time

SPI cycle time

10

-

[1]

79.6

ns

SPICLK HIGH time

SPICLK LOW time

0.485 × T_SPICYC

ns

0.515 × T_SPICYCns

[2]

SPI data set-up time

0

-

ns

SPI data hold time

2 × T_cy(PCLK)− 5

2 × T_cy(PCLK)+ 30

2 × T_cy(PCLK)+ 5

t_SPIQV

SPI data output valid time

SPI output data hold time

t_SPIOH

SPI slave

t_SPIDSU

t_SPIDH

[2]

SPI data set-up time

0

-

ns

SPI data hold time

2 × T_cy(PCLK)+ 5

2 × T_cy(PCLK)+ 35

2 × T_cy(PCLK)+ 15

t_SPIQV

SPI data output valid time

SPI output data hold time

t_SPIOH

[1] T_SPICYC= (T_cy(PCLK)× n) ± 0.5 %, n is the SPI clock divider value (n ≥ 8); PCLK is derived from the

processor clock CCLK.

[2] Timing parameters are measured with respect to the 50 % edge of the clock PCLK and the 10 % (90 %)

edge of the data signal (MOSI or MISO).

T

t

SPICLKH

t

SPICYC

SPICLKL

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

SPIOH

SPIQV

DATA VALID

t

SPIDH

SPIDSU

MISO

DATA VALID

002aad986

Fig 17. SPI master timing (CPHA = 1)

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T

t

SPICLKH

t

SPICYC

SPICLKL

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

SPIOH

SPIQV

DATA VALID

t

SPIDH

SPIDSU

DATA VALID

MISO

002aad987

Fig 18. SPI master timing (CPHA = 0)

T

t

SPICLKH

t

SPICYC

SPICLKL

SCK (CPOL = 0)

SCK (CPOL = 1)

t

SPIDH

SPIDSU

MOSI

MISO

DATA VALID

t

SPIOH

SPIQV

DATA VALID

002aad988

Fig 19. SPI slave timing (CPHA = 1)

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T

t

SPICLKH

t

SPICYC

SPICLKL

SCK (CPOL = 0)

SCK (CPOL = 1)

t

SPIDH

SPIDSU

MOSI

MISO

DATA VALID

t

SPIOH

SPIQV

DATA VALID

002aad989

Fig 20. SPI slave timing (CPHA = 0)

12. ADC electrical characteristics

Table 16. ADC characteristics

V_DDA= 2.7 V to 3.6 V; T_amb= −40 °C to +85 °C unless otherwise specified; ADC frequency 13 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

15

Unit

V

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

C_ia

-

pF

[1][2][3]

[1][4]

[1][5]

[1][6]

[1][7]

[8]

E_D

-

±1

LSB

%

E_L(adj)

E_O

-

±3

±2

-

E_G

gain error

0.5

4

E_T

absolute error

-

LSB

kΩ

R_vsi

voltage source interface

resistance

-

7.5

f_clk(ADC)

f_c(ADC)

ADC clock frequency

-

13

MHz

kHz

ADC conversion frequency

200

[1] Conditions: V_SSA= 0 V, V_DDA= 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 21.

[4] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 21.

[5] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 21.

[6] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 21.

[7] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 21.

[8] See Figure 22.

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32-bit ARM Cortex-M3 microcontroller

offset

error

gain

error

E

O

G

4095

4094

4093

4092

4091

4090

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

offset error

E

O

VREFP − VREFN

1 LSB =

4096

002aad948

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 21. 12-bit ADC characteristics

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32-bit ARM Cortex-M3 microcontroller

LPC17xx

R

i2

2 kΩ - 5.2 kΩ

i1

100 Ω - 600 Ω

2.2 pF

ADC

COMPARATOR

BLOCK

AD0[n]

750 fF

65 fF

C

ia

R

vsi

V

SS

V

EXT

002aaf197

The values of resistor components R_i1and R_i2vary with temperature and input voltage and are

process-dependent.

Fig 22. ADC interface to pins AD0[n]

13. DAC electrical characteristics (LPC1759/58/56/54 only)

Table 17. DAC electrical characteristics

V_DDA= 2.7 V to 3.6 V; T_amb= −40 °C to +85 °C unless otherwise specified

Symbol

E_D

Parameter

Conditions

Min

Typ

±1

Max

Unit

LSB

%

differential linearity error

integral non-linearity

offset error

-

E_L(adj)

E_O

-

±1.5

0.6

200

-

E_G

gain error

-

%

C_L

load capacitance

load resistance

-

pF

R_L

1

kΩ

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14. Application information

14.1 Suggested USB interface solutions

V

DD(3V3)

USB_UP_LED

USB_CONNECT

LPC17xx

SoftConnect switch

R1

1.5 kΩ

V

BUS

R

= 33 Ω

S

USB-B

connector

USB_D+

S

USB_D−

V

SS

002aad939

Fig 23. LPC1759/58/56/54/52/51 USB interface on a self-powered device

V

DD(3V3)

R2

LPC17xx

R1

1.5 kΩ

USB_UP_LED

V

BUS

USB-B

connector

R

= 33 Ω

S

USB_D+

S

USB_D−

V

SS

002aad940

Fig 24. LPC1759/58/56/54/52/51 USB interface on a bus-powered device

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32-bit ARM Cortex-M3 microcontroller

V

DD

V

RSTOUT

RESET_N

ADR/PSW

OE_N/INT_N

SPEED

BUS

ID

33 Ω

DP

V

DD

Mini-AB

33 Ω

connector

DM

ISP1302

SUSPEND

LPC1759/58/

56/54

V

SS

SCL

SDA

SCL1/2

SDA1/2

INT_N

EINT0

USB_D+

USB_D−

USB_UP_LED

002aae155

V

DD

Fig 25. LPC1759/58/56/54 USB OTG port configuration

V

DD

USB_UP_LED

V

SS

33 Ω

D+

USB_D+

USB_D−

D−

USB-A

connector

LPC1759/58/

56/54

15 kΩ

V

DD

V

BUS

USB_PWRD

USB_PPWR

FLAGA

OUTA

ENA

IN

5 V

LM3526-L

002aae156

Fig 26. LPC1759/58/56/54 USB host port configuration

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32-bit ARM Cortex-M3 microcontroller

V

DD

USB_UP_LED

V

DD

USB_CONNECT

LPC17xx

V

SS

33 Ω

USB_D+

D+

USB-B

connector

D−

USB_D−

V

BUS

V

BUS

002aad943

Fig 27. LPC1759/58/56/54/52/51 USB device port configuration

14.2 XTAL1 input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/ (C_i+ C_g). In

slave mode, a minimum of 200 mV (RMS) is needed. For more details see the LPC17xx

User manual.

LPC1xxx

XTAL1

C

i

C

g

100 pF

002aae835

Fig 28. Slave mode operation of the on-chip oscillator

14.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1, C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_x1and C_x2should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

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32-bit ARM Cortex-M3 microcontroller

15. Package outline

LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm

SOT315-1

y

X

A

60

41

Z

61

40

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

L

pin 1 index

80

21

detail X

1

20

Z

D

v

M

A

e

w M

b

p

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

p

v

w

y

Z

θ

1

2

3

p

E

D

E

max.

7^o

0^o

0.16 1.5

0.04 1.3

0.27 0.18 12.1 12.1

0.13 0.12 11.9 11.9

14.15 14.15

13.85 13.85

0.75

0.30

1.45 1.45

1.05 1.05

mm

1.6

0.25

0.5

1

0.2 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT315-1

136E15

MS-026

Fig 29. Package outline (LQFP80)

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16. Abbreviations

Table 18. Abbreviations

Description

Acronym

ADC

AHB

AMBA

APB

BOD

CAN

DAC

DCC

DMA

DSP

EOP

ETM

GPIO

IRC

Analog-to-Digital Converter

Advanced High-performance Bus

Advanced Microcontroller Bus Architecture

Advanced Peripheral Bus

BrownOut Detection

Controller Area Network

Digital-to-Analog Converter

Debug Communication Channel

Direct Memory Access

Digital Signal Processing

End Of Packet

Embedded Trace Macrocell

General Purpose Input/Output

Internal RC

IrDA

JTAG

MAC

MIIM

OTG

PHY

PLL

Infrared Data Association

Joint Test Action Group

Media Access Control

Media Independent Interface Management

On-The-Go

Physical Layer

Phase-Locked Loop

PWM

RMII

SE0

Pulse Width Modulator

Reduced Media Independent Interface

Single Ended Zero

SPI

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus

SSI

SSP

TTL

UART

USB

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17. Revision history

Table 19. Revision history

Document ID

Release date

Data sheet status

Product data sheet

Change Supersedes

notice

LPC1759_58_56_54_52_51_4

Modifications:

20100126

-

LPC1758_56_54_52_51_3

• Added parameters t_rand t_f(Section 11.4).

• ADC static characteristics: Parameter R_vsiand Figure 22 added.

• Table note 14 in Table 6 updated.

• In Table 6 move parameter V_hysvalue from typical to minimum.

• Added part LPC1759.

• Added SRAM sizes for CPU SRAM, AHB SRAM0, and AHB SRAM1 in Table 2.

• Added table note for XTAL1 and XTAL2 pins in Table 3.

• Changed minimum value of parameters V_i(XTAL1), V_i(XTAL2), V_i(RTCX1), and

V_i(RTCX2)to −0.5 V.

LPC1758_56_54_52_51_3

Modifications:

20091119

Product data sheet

-

LPC1758_56_54_52_51_2

• Added Electrical pin characteristics (Section 10.1).

• Changed data sheet status to Product.

• Maximum data bit rate for SPI, SSP, UART added.

• RTC back-up RAM size updated (20 bytes).

• WDT clock source added: RTC oscillator.

• ADC conversion rate changed to 200 kHz.

• Removed symbols from timing diagram (Figure 12).

• Updated motor control PWM pin names in Table 3 “Pin description” and Figure 1

“Block diagram”.

• ENET_MDC and ENET_MDIO functions removed from pin P2[8] and P2[9]

(Table 3).

• V_DDAand VREFP pin descriptions updated (Table 3).

• CLKOUT function removed (Table 3).

• V_esdchanged to ± 4000 V (Table 4).

• Power consumption data added to Table 6.

• Flash characteristics table updated (Table 7).

• I²S-bus timing characteristics added (Table 12).

• SPI timing characteristics added (Table 15).

• ADC absolute error E_Tadded (Table 16).

• DAC electrical characteristics updated (Table 17).

• XTAL1 circuit and PCB layout recommendations added (see Section 14.2 and

Section 14.3).

• Updated parameters E_Dand E_L(adj)in Table 16 “ADC characteristics”.

LPC1758_56_54_52_51_2

Modifications:

20090211

Objective data sheet

-

LPC1758_56_54_52_51_1

• Updated Flash characteristics.

• Updated Figure 3 “LPC1758/56/54/52/51 memory map”.

• Updated descriptive title.

LPC1758_56_54_52_51_1

20090115

Objective data sheet

-

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18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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20. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.18.1

7.19

7.19.1

7.20

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I²C-bus serial I/O controllers . . . . . . . . . . . . . 23

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I²S-bus serial I/O controllers

(LPC1759/58/56 only) . . . . . . . . . . . . . . . . . . 23

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

General purpose 32-bit timers/external

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

4

4.1

5

7.20.1

7.21

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

event counters . . . . . . . . . . . . . . . . . . . . . . . . 24

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Pulse width modulator . . . . . . . . . . . . . . . . . . 25

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Motor control PWM . . . . . . . . . . . . . . . . . . . . 26

Quadrature Encoder Interface

(QEI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 27

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ARM Cortex-M3 system tick timer . . . . . . . . . 27

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 27

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

RTC and backup registers . . . . . . . . . . . . . . . 28

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Clocking and power control . . . . . . . . . . . . . . 28

Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 28

7.21.1

7.22

7.22.1

7.23

7

Functional description . . . . . . . . . . . . . . . . . . 13

Architectural overview . . . . . . . . . . . . . . . . . . 13

ARM Cortex-M3 processor . . . . . . . . . . . . . . . 13

On-chip flash program memory . . . . . . . . . . . 13

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Protection Unit (MPU). . . . . . . . . . . . 13

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Nested Vectored Interrupt Controller

(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 16

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 16

General purpose DMA controller . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Fast general purpose parallel I/O . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ethernet (LPC1758 only) . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 19

USB device controller. . . . . . . . . . . . . . . . . . . 19

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.24

7.24.1

7.25

7.25.1

7.26

7.27

7.27.1

7.28

7.28.1

7.29

7.29.1

7.7.1

7.7.2

7.8

7.9

7.9.1

7.10

7.10.1

7.11

7.11.1

7.12

7.12.1

7.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 29

7.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 29

7.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 29

7.29.2

7.29.3

7.29.4

7.29.5

Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 30

USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 30

Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 30

Power control. . . . . . . . . . . . . . . . . . . . . . . . . 31

7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.12.2

7.29.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.29.5.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 31

7.29.5.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 32

7.29.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 32

7.29.5.5 Wakeup interrupt controller . . . . . . . . . . . . . . 32

USB host controller

(LPC1759/58/56/54 only).. . . . . . . . . . . . . . . . 20

7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.12.3

USB OTG controller

(LPC1759/58/56/54 only).. . . . . . . . . . . . . . . . 20

7.29.6

7.29.7

7.30

7.30.1

7.30.2

7.30.3

Peripheral power control . . . . . . . . . . . . . . . . 32

Power domains . . . . . . . . . . . . . . . . . . . . . . . 32

System control . . . . . . . . . . . . . . . . . . . . . . . . 34

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Brownout detection . . . . . . . . . . . . . . . . . . . . 35

Code security

(Code Read Protection - CRP) . . . . . . . . . . . 35

APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 35

AHB multilayer matrix . . . . . . . . . . . . . . . . . . 36

External interrupt inputs. . . . . . . . . . . . . . . . . 36

Memory mapping control . . . . . . . . . . . . . . . . 36

Emulation and debugging . . . . . . . . . . . . . . . 36

7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.13

7.13.1

7.14

7.14.1

7.15

7.15.1

7.16

7.16.1

7.17

7.17.1

7.18

CAN controller and acceptance filters . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10-bit DAC (LPC1759/58/56/54 only). . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SSP serial I/O controller . . . . . . . . . . . . . . . . . 22

7.30.4

7.30.5

7.30.6

7.30.7

7.31

continued >>

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

63 of 64

LPC1759/58/56/54/52/51

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 37

9

Thermal characteristics . . . . . . . . . . . . . . . . . 38

Thermal characteristics. . . . . . . . . . . . . . . . . . 38

Static characteristics. . . . . . . . . . . . . . . . . . . . 39

Electrical pin characteristics . . . . . . . . . . . . . . 42

9.1

10

10.1

11

Dynamic characteristics . . . . . . . . . . . . . . . . . 44

Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 44

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 44

Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 45

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 46

I²S-bus interface (LPC1759/58/56 only). . . . . 47

SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 49

USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 50

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

12

13

ADC electrical characteristics . . . . . . . . . . . . 53

DAC electrical characteristics

(LPC1759/58/56/54 only) . . . . . . . . . . . . . . . . . 55

14

Application information. . . . . . . . . . . . . . . . . . 56

Suggested USB interface solutions . . . . . . . . 56

XTAL1 input . . . . . . . . . . . . . . . . . . . . . . . . . . 58

XTAL and RTCX Printed Circuit Board

14.1

14.2

14.3

(PCB) layout guidelines . . . . . . . . . . . . . . . . . 58

15

16

17

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 59

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 60

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 61

18

Legal information. . . . . . . . . . . . . . . . . . . . . . . 62

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 62

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.1

18.2

18.3

18.4

19

20

Contact information. . . . . . . . . . . . . . . . . . . . . 62

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 January 2010

Document identifier: LPC1759_58_56_54_52_51_4


型号：	LPC1756FBD80
厂家：	NXP
描述：	32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN 32位ARM Cortex-M3的MCU ;高达512 KB的闪存和64 KB的SRAM，带有以太网， USB 2.0主机/设备/ OTG ， CAN 闪存微控制器和处理器外围集成电路静态存储器以太网时钟
文件：	总64页 (文件大小：746K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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