LPC1850FET256_技术文档

LPC1850/30/20/10

32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet,

two High-speed USB, LCD, and external memory controller

Rev. 1 — 3 January 2011

Objective data sheet

1. General description

The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded

applications. The ARM Cortex-M3 is a next generation core that offers system

enhancements such as low power consumption, enhanced debug features, and a high

level of support block integration.

The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash

Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB

controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog

peripherals.

2. Features and benefits

Processor core

ARM Cortex-M3 processor, running at frequencies of up to 150 MHz.

ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

Non-maskable Interrupt (NMI) input.

JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.

ETM and ETB support.

System tick timer.

On-chip memory

136 kB SRAM for code and data use.

Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be

powered down individually.

32 kB ROM containing boot code and on-chip software drivers.

32-bit One-Time Programmable (OTP) memory for general-purpose customer use.

Clock generation unit

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

12 MHz internal RC oscillator trimmed to 1 % accuracy.

Ultra-low power RTC crystal oscillator.

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Two PLLs allow CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. Second PLL can be used for USB.

Clock output.

Serial interfaces:

Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per

second total.

10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load.

One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip PHY.

One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY.

Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support synchronous mode and a smart

card interface conforming to ISO7816 specification.

One C_CAN 2.0B controller with one channel.

Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I²C-bus specification. Supports data rates of up to

1 Mbit/s.

One standard I²C-bus interface with monitor mode and standard I/O pins.

One I²S interface with DMA support and with one input and one output.

Digital peripherals:

External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,

and SDRAM devices.

LCD controller with DMA support and a programmable display resolution of up to

1024H × 768V. Supports monochrome and color STN panels and TFT color panels;

supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.

SD/MMC card interface.

Eight-channel General-Purpose DMA (GPDMA) controller can access all memories

on the AHB and all DMA-capable AHB slaves.

Up to 80 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors and open-drain modes.

GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

State Configurable Timer (SCT) subsystem on AHB.

Four general-purpose timer/counters with capture and match capabilities.

One motor control PWM for three-phase motor control.

One Quadrature Encoder Interface (QEI).

Repetitive Interrupt timer (RI timer).

Windowed watchdog timer.

Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes

of battery powered backup registers.

Alarm timer; can be battery powered.

Analog peripherals:

One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

2 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.

Security:

AES decryption engine programmable through an on-chip API.

Two 128-bit secure OTP memories for AES key storage and customer use.

Unique ID for each device.

Power:

Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for

the core supply and the RTC power domain.

RTC power domain can be powered separately by a 3 V battery supply.

Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

Overdrive mode to increase CPU and bus clock frequency.

Processor wake-up from Sleep mode via wake-up interrupts from various

peripherals.

Wake-up from Deep-sleep, Power-down, and Deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the RTC

power domain.

Brownout detect with four separate thresholds for interrupt and forced reset.

Power-On Reset (POR).

Available as 208-pin and 144-pin LQFP packages and as 100-pin, 180-pin, and

256-pin LBGA packages.

3. Applications

Industrial

RFID readers

e-Metering

Consumer

White goods

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC1850FET256

LPC1850

LBGA256

LQFP208

BGA180

LBGA256

LQFP208

BGA180

LQFP144

BGA100

LQFP144

BGA100

plastic low profile ball grid array package; 256 balls; body 17 × 17 × 1 mm sot740-2

<tbd>

LPC1850

LPC1830FET256

LPC1830

plastic low profile ball grid array package; 256 balls; body 17 × 17 × 1 mm sot740-2

<tbd>

LPC1830

LPC1820

LPC1820FET100

LPC1810

LPC1810FET100

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

3 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

4.1 Ordering options

Table 2.

Ordering options

Type number

SRAM

LCD

Ethernet

USB0 (Host,

USB1 (Host,

Package

Device, OTG) Device)

LPC1850

LPC1830

LPC1820

LPC1810

200 kB

168 kB

136 kB

yes

no

yes

no

yes

no

yes

no

LBGA256

LQFP208

BGA180

LBGA256

BGA180

LQFP208

BGA100

LQFP144

BGA100

LQFP144

no

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

4 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

5. Block diagram

SWD/TRACE PORT/JTAG

LPC1850/30/20/10

HIGH-SPEED PHY

TEST/DEBUG

INTERFACE

HIGH-

(1)

ETHERNET

10/100

SPEED

(1)

USB1

GPDMA

(1)

USB0

(1)

MAC

LCD

SD/

MMC

HOST/

DEVICE

ARM

CORTEX-M3

HOST/

DEVICE/

OTG

(1)

IEEE 1588

masters

slaves

AHB MULTILAYER MATRIX

SPIFI

slaves

BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

EMC

32 kB ROM

2

MOTOR

CONTROL

PWM

RI TIMER

USART2

USART3

TIMER2

TIMER3

SSP1

I C1

CGU

CCU1

CCU2

RGU

WWDT

ALARM TIMER

64/96 kB LOCAL SRAM

40 kB LOCAL SRAM

USART0

10-bit DAC

C_CAN

BACKUP REGISTERS

2

16/32 kB AHB SRAM

16 kB +

I C0

POWER MODE CONTROL

UART1

SSP0

2

I S0

10-bit ADC0

10-bit ADC1

CONFIGURATION

REGISTERS

(1)

16 kB AHB SRAM

TIMER0

EVENT ROUTER

OTP MEMORY

AES

HS GPIO

SCT

TIMER1

SCU

QEI

RTC

RTC OSC

12 MHz IRC

RTC POWER DOMAIN

= connected to GPDMA

002aaf218

(1) Not available on all parts (see Table 2).

Fig 1. LPC1850/30/20/10 block diagram

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

5 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

6. Pinning information

6.1 Pinning

LPC1850/30FET256

ball A1

index area

2

4

6

8

10 12 14 16

9 11 13 15

1

3

5

7

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

002aaf230

Transparent top view

Fig 2. Pin configuration LBGA256 package

6.2 Pin description

On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA

to PF, with up to 20 pins used per port. Each digital pin may support up to four different

digital functions, including General Purpose I/O (GPIO), selectable through the SYSCON

registers. Note that the pin name is not indicative of the GPIO port assigned to it.

Analog functions and power pins are pinned out separately and do not share pins with

digital functions.

Table 3.

Symbol

Pin description

Reset Type Description

state

[1]

Multiplexed digital pins

P0_0^[2]

L3

I; PU

I/O

I

GPIO0[0] — General purpose digital input/output pin.

SSP1_MISO — Master In Slave Out for SSP1.

ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

n.c.

-

P0_1^[2]

M2

I/O

I

GPIO0[1] — General purpose digital input/output pin.

SSP1_MOSI — Master Out Slave in for SSP1.

ENET_COL — Ethernet Collision detect (MII interface).

n.c.

-

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

6 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P1_0^[2]

P1_1^[2]

P2

R2

I; PU

I/O

I

GPIO0[4] — General purpose digital input/output pin.

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

EXTBUS_A5 — External memory address line 5.

n.c.

I/O

-

I/O

O

GPIO0[8] — General purpose digital input/output pin.

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O

EXTBUS_A6 — External memory address line 6. Boot control pin 0 (see

Table 5).

-

n.c.

P1_2^[2]

R3

I; PU

I/O

O

GPIO0[9] — General purpose digital input/output pin.

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

I/O

EXTBUS_A7 — External memory address line 7. Boot control pin 1 (see

Table 5).

-

n.c.

P1_3^[2]

P1_4^[2]

P1_5^[2]

P1_6^[2]

P1_7^[2]

P1_8^[2]

P5

T3

R5

T4

T5

R7

I; PU

I/O

O

-

GPIO0[10] — General purpose digital input/output pin.

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

n.c.

O

I/O

O

-

EXTBUS_OE — LOW active Output Enable signal.

GPIO0[11] — General purpose digital input/output pin.

CTOUT_9 — SCT output 9. Match output 1 of timer 2.

n.c.

O

I/O

O

-

EXTBUS_BLS0 — LOW active Byte Lane select signal 0.

GPIO1[8] — General purpose digital input/output pin.

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

n.c.

O

I/O

I

EXTBUS_CS0 — LOW active Chip Select 0 signal.

GPIO1[9] — General purpose digital input/output pin.

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

n.c.

-

O

I/O

I

EXTBUS_WE — LOW active Write Enable signal.

GPIO1[0] — General purpose digital input/output pin.

U1_DSR — Data Set Ready input for UART1.

CTOUT_13 — SCT output 13. Match output 1 of timer 3.

EXTBUS_D0 — External memory data line 0.

GPIO1[1] — General purpose digital input/output pin.

U1_DTR — Data Terminal Ready output for UART1.

CTOUT_12 — SCT output 12. Match output 0 of timer 3.

EXTBUS_D1 — External memory data line 1.

O

I/O

O

I/O

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

7 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P1_9^[2]

T7

R8

T9

R9

I; PU

I/O

O

I/O

I

GPIO1[2] — General purpose digital input/output pin.

U1_RTS — Request to Send output for UART1.

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

EXTBUS_D2 — External memory data line 2.

GPIO1[3] — General purpose digital input/output pin.

U1_RI — Ring Indicator input for UART1.

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

EXTBUS_D3 — External memory data line 3.

GPIO1[4] — General purpose digital input/output pin.

U1_CTS — Clear to Send input for UART1.

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

EXTBUS_D4 — External memory data line 4.

GPIO1[5] — General purpose digital input/output pin.

U1_DCD — Data Carrier Detect input for UART1.

n.c.

P1_10^[2]

P1_11^[2]

P1_12^[2]

P1_13^[2]

P1_14^[2]

P1_15^[2]

P1_16^[2]

O

I/O

I

O

I/O

I

-

I/O

O

-

EXTBUS_D5 — External memory data line 5.

GPIO1[6] — General purpose digital input/output pin.

U1_TXD — Transmitter output for UART1.

n.c.

R10 I; PU

R11 I; PU

T12 I; PU

I/O

I

EXTBUS_D6 — External memory data line 6.

GPIO1[7] — General purpose digital input/output pin.

U1_RXD — Receiver input for UART1.

n.c.

-

I/O

O

-

EXTBUS_D7 — External memory data line 7.

GPIO0[2] — General purpose digital input/output pin.

U2_TXD — Transmitter output for UART2.

n.c.

I

ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

GPIO0[3] — General purpose digital input/output pin.

U2_RXD — Receiver input for UART2.

n.c.

M7

M8

I; PU

I/O

I

-

I

ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII interface) or

Ethernet Carrier Sense/Data Valid (RMII interface).

P1_17^[2]

I/O

-

GPIO0[12] — General purpose digital input/output pin.

U2_UCLK — Serial clock input/output for UART2 in synchronous mode.

n.c.

I/O

ENET_MDIO — Ethernet MIIM data input and output.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

8 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P1_18^[2]

P1_19^[2]

N12 I; PU

I/O

-

GPIO0[13] — General purpose digital input/output pin.

U2_DIR — RS-485/EIA-485 output enable/direction control for UART2.

n.c.

O

I

ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

M11 <tbd>

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII

interface) or Ethernet Reference Clock (RMII interface).

I/O

-

SSP1_SCK — Serial clock for SSP1.

n.c.

-

n.c.

P1_20^[2]

M10 I; PU

T16 <tbd>

I/O

-

GPIO0[15] — General purpose digital input/output pin.

SSP1_SSEL — Slave Select for SSP1.

n.c.

O

-

ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

n.c.

P2_0^[2]

O

I/O

O

U0_TXD — Transmitter output for USART0.

EXTBUS_A13 — External memory address line 13.

USB0_PWR_EN — VBUS drive signal (towards external charge pump or

power management unit); indicates that Vbus must be driven (active high).

P2_1^[2]

N15 <tbd>

-

n.c.

I

U0_RXD — Receiver input for USART0.

EXTBUS_A12 — External memory address line 12.

I/O

O

USB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external circuitry

required to detect over-current condition).

P2_2^[2]

P2_3^[2]

M15 <tbd>

J12 <tbd>

-

n.c.

I/O

O

U0_UCLK — Serial clock input/output for USART0 in synchronous mode.

EXTBUS_A11 — External memory address line 11.

USB0_IND1 — USB0 port indicator LED control output 1.

n.c.

-

I/O

I2C1_SDA — I²C1 data input/output (this pin does not use a specialized I²C

pad).

O

I

U3_TXD — Transmitter output for USART3.

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2.

P2_4^[2]

K11 <tbd>

-

n.c.

I/O

I2C1_SCL — I²C1 clock input/output (this pin does not use a specialized I²C

pad).

I

U3_RXD — Receiver input for USART3.

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

9 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P2_5^[3]

K14 <tbd>

-

I

n.c.

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

USB1_VBUS — Monitors the presence of USB1 bus power.

Note: This signal must be HIGH for USB reset to occur.

ADCTRIG1 — ADC trigger input 1.

I

P2_6^[2]

P2_7^[2]

K16 <tbd>

H14 I; PU

-

n.c.

I/O

O

U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.

EXTBUS_A10 — External memory address line 10.

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

GPIO0[7] — General purpose digital input/output pin. This pin is sampled at

RESET for ISP entry.

O

CTOUT_1 — SCT output 1. Match output 1 of timer 0.

U3_UCLK — Serial clock input/output for USART3 in synchronous mode.

EXTBUS_A9 — External memory address line 9.

n.c.

I/O

-

P2_8^[2]

J16 <tbd>

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.

I/O

EXTBUS_A8 — External memory address line 8. Boot control pin 2 (see

Table 5).

P2_9^[2]

H16 I; PU

G16 I; PU

F16 I; PU

E15 I; PU

C16 I; PU

I/O

O

GPIO1[10] — General purpose digital input/output pin.

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

U3_BAUD3 — <tbd>for USART3.

I/O

O

EXTBUS_A0 — External memory address line 0.

GPIO0[14] — General purpose digital input/output pin.

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

U2_TXD — Transmitter output for USART2.

EXTBUS_A1 — External memory address line 1.

GPIO1[11] — General purpose digital input/output pin.

CTOUT_5 — SCT output 5. Match output 1 of timer 1.

U2_RXD — Receiver input for USART2.

P2_10^[2]

P2_11^[2]

P2_12^[2]

P2_13^[2]

O

I/O

O

I

I/O

O

EXTBUS_A2 — External memory address line 2.

GPIO1[12] — General purpose digital input/output pin.

CTOUT_4 — SCT output 4. Match output 0 of timer 1.

n.c.

-

I/O

I

EXTBUS_A3 — External memory address line 3.

GPIO1[13] — General purpose digital input/output pin.

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

n.c.

-

I/O

EXTBUS_A4 — External memory address line 4.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

10 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P3_0^[2]

P3_1^[2]

P3_2^[2]

F13 <tbd> I/O

I2S_RX_SCK — Receive Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I²S-bus specification.

O

I2S_RX_MCLK — I2S receive master clock.

I2S_TX_SCK — I²S transmit clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S-bus specification.

I/O

O

I2S_TX_MCLK — I2S transmit master clock.

G11 <tbd> I/O

I2S_TX_WS — Transmit Word Select. It is driven by the master and received

by the slave. Corresponds to the signal WS in the I²S-bus specification.

I/O

I2S_RX_WS — Receive Word Select. It is driven by the master and received

by the slave. Corresponds to the signal WS in the I²S-bus specification.

I

O

CAN1_RD — CAN1 receiver input.

USB1_IND1 — USB1 port indicator LED control output 1.

I2S_TX_SDA — I²S transmit data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S-bus specification.

F11 <tbd> I/O

I/O

I2S_RX_SDA — I²S Receive data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S-bus specification.

O

CAN1_TD — CAN1 transmitter output.

USB1_IND0 — USB1 port indicator LED control output 0.

P3_3^[2]

P3_4^[2]

P3_5^[2]

P3_6^[2]

P3_7^[2]

B14 <tbd>

A15 I; PU

C12 I; PU

B13 I; PU

C11 <tbd>

-

n.c.

-

n.c.

I/O

O

I/O

-

SSP0_SCK — Serial clock for SSP0.

SPIFI_SCK — Serial clock for SPIFI.

GPIO1[14] — General purpose digital input/output pin.

n.c.

-

n.c.

I/O

-

SPIFI_SIO3 — I/O lane 3 for SPIFI.

GPIO1[15] — General purpose digital input/output pin.

n.c.

-

n.c.

I/O

-

SPIFI_SIO2 — I/O lane 2 for SPIFI.

GPIO0[6] — General purpose digital input/output pin.

n.c.

I/O

-

SSP0_SSEL — Slave Select for SSP0.

SPIFI_MISO — Input I1 in SPIFI quad mode; SPIFI output IO1.

n.c.

-

n.c.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

11 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P3_8^[2]

P4_0^[2]

P4_1^[2]

P4_2^[2]

P4_3^[2]

P4_4^[2]

P4_5^[2]

P4_6^[2]

P4_7^[2]

C10 <tbd>

-

n.c.

-

I/O

O

I

SSP0_MOSI — Master Out Slave in for SSP0.

SPIFI_CS — SPIFI serial flash chip select.

GPIO2[0] — General purpose digital input/output pin.

MCOA0 — Motor control PWM channel 0, output A.

NMI — External interrupt input to NMI.

n.c.

D5

A1

D3

C2

B1

D2

C1

H4

I; PU

<tbd>

-

I/O

O

-

GPIO2[1] — General purpose digital input/output pin.

CTOUT_1 — SCT output 1. Match output 1 of timer 0.

LCDVD0 — LCD data.

n.c.

I/O

O

-

GPIO2[2] — General purpose digital input/output pin.

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

LCDVD3 — LCD data.

n.c.

I/O

O

-

GPIO2[3] — General purpose digital input/output pin.

CTOUT_3 — SCT output 0. Match output 3 of timer 0.

LCDVD2 — LCD data.

n.c.

I/O

O

-

GPIO2[4] — General purpose digital input/output pin.

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

LCDVD1 — LCD data.

n.c.

I/O

O

-

GPIO2[5] — General purpose digital input/output pin.

CTOUT_5 — SCT output 5. Match output 1 of timer 1.

LCDFP — Frame pulse (STN). Vertical synchronization pulse (TFT).

n.c.

I/O

O

-

GPIO2[6] — General purpose digital input/output pin.

CTOUT_4 — SCT output 4. Match output 0 of timer 1.

LCDENAB/LCDM — STN AC bias drive or TFT data enable input.

n.c.

O

I

LCDDCLK — LCD panel clock.

GP_CLKIN — General purpose clock input to the CGU.

n.c.

-

n.c.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

12 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P4_8^[2]

P4_9^[2]

P4_10^[2]

P5_0^[2]

P5_1^[2]

P5_2^[2]

P5_3^[2]

P5_4^[2]

P5_5^[2]

E2

L2

<tbd>

I; PU

-

n.c.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

LCDVD9 — LCD data.

O

-

n.c.

-

n.c.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

LCDVD11 — LCD data.

O

-

n.c.

M3

N3

P3

R4

T8

P9

-

n.c.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

LCDVD10 — LCD data.

O

-

n.c.

I/O

O

I/O

-

GPIO2[9] — General purpose digital input/output pin.

MCOB2 — Motor control PWM channel 2, output B.

EXTBUS_D12 — External memory data line 12.

n.c.

I/O

I

GPIO2[10] — General purpose digital input/output pin.

MCI2 — Motor control PWM channel 2, input.

EXTBUS_D13 — External memory data line 13.

n.c.

I/O

-

I/O

I

GPIO2[11] — General purpose digital input/output pin.

MCI1 — Motor control PWM channel 1, input.

EXTBUS_D14 — External memory data line 14.

n.c.

I/O

-

I/O

I

GPIO2[12] — General purpose digital input/output pin.

MCI0 — Motor control PWM channel 0, input.

EXTBUS_D15 — External memory data line 15.

n.c.

I/O

-

I/O

O

I/O

-

GPIO2[13] — General purpose digital input/output pin.

MCOB0 — Motor control PWM channel 0, output B.

EXTBUS_D8 — External memory data line 8.

n.c.

P10 I; PU

I/O

O

I/O

-

GPIO2[14] — General purpose digital input/output pin.

MCOA1 — Motor control PWM channel 1, output A.

EXTBUS_D9 — External memory data line 9.

n.c.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

13 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P5_6^[2]

P5_7^[2]

P6_0

T13 I; PU

I/O

O

GPIO2[15] — General purpose digital input/output pin.

MCOB1 — Motor control PWM channel 1, output B.

I/O

-

EXTBUS_D10 — External memory data line 10.

n.c.

R12 I; PU

I/O

O

GPIO2[7] — General purpose digital input/output pin.

MCOA2 — Motor control PWM channel 2, output A.

EXTBUS_D11 — External memory data line 11.

n.c.

I/O

-

M12 <tbd> I/O

I2S_RX_SCK — Receive Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I²S-bus specification.

O

-

I2S_RX_MCLK — I2S receive master clock.

n.c.

-

n.c.

P6_1^[2]

P6_2^[2]

P6_3^[2]

R15 I; PU

L13 I; PU

P15 I; PU

I/O

O

GPIO3[0] — General purpose digital input/output pin.

EXTBUS_DYCS1 — SDRAM chip select 1.

U0_UCLK — Serial clock input/output for USART0 in synchronous mode.

I/O

I2S_RX_WS — Receive Word Select. It is driven by the master and received

by the slave. Corresponds to the signal WS in the I²S-bus specification.

I/O

O

GPIO3[1] — General purpose digital input/output pin.

EXTBUS_CKEOUT1 — SDRAM clock enable 1.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.

I2S_RX_SDA — I²S Receive data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S-bus specification.

I/O

O

GPIO3[2] — General purpose digital input/output pin.

USB0_PWR_EN — VBUS drive signal (towards external charge pump or

power management unit); indicates that Vbus must be driven (active high).

-

n.c.

O

I/O

I

EXTBUS_CS1 — LOW active Chip Select 1 signal.

GPIO3[3] — General purpose digital input/output pin.

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

U0_TXD — Transmitter output for USART0.

EXTBUS_CAS — LOW active SDRAM Column Address Strobe.

GPIO3[4] — General purpose digital input/output pin.

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

U0_RXD — Receiver input for USART0.

P6_4^[2]

P6_5^[2]

R16 I; PU

P16 I; PU

O

I/O

O

I

O

EXTBUS_RAS — LOW active SDRAM Row Address Strobe.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

14 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P6_6^[2]

L14 I; PU

I/O

O

-

GPIO0[5] — General purpose digital input/output pin.

EXTBUS_BLS1 — LOW active Byte Lane select signal 1.

n.c.

O

USB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external circuitry

required to detect over-current condition).

P6_7^[2]

P6_8^[2]

P6_9^[2]

P6_10^[2]

P6_11^[2]

P6_12^[2]

P7_0^[2]

P7_1^[2]

J13 <tbd>

H13 <tbd>

J15 I; PU

H15 I; PU

H12 I; PU

G15 I; PU

B16 I; PU

C14 I; PU

-

n.c.

I/O

-

EXTBUS_A15 — External memory address line 15.

n.c.

O

-

USB0_IND1 — USB0 port indicator LED control output 1.

n.c.

I/O

-

EXTBUS_A14 — External memory address line 14.

n.c.

O

I/O

-

USB0_IND0 — USB0 port indicator LED control output 0.

GPIO3[5] — General purpose digital input/output pin.

n.c.

-

n.c.

O

I/O

O

-

EXTBUS_DYCS0 — SDRAM chip select 0.

GPIO3[6] — General purpose digital input/output pin.

MCABORT — Motor control PWM, LOW-active fast abort.

n.c.

O

I/O

-

EXTBUS_DQMOUT1 — Data mask 1 used with SDRAM and static devices.

GPIO3[7] — General purpose digital input/output pin.

n.c.

-

n.c.

O

I/O

O

-

EXTBUS_CKEOUT0 — SDRAM clock enable 0.

GPIO2[8] — General purpose digital input/output pin.

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

n.c.

O

I/O

O

-

EXTBUS_DQMOUT0 — Data mask 0 used with SDRAM and static devices.

GPIO3[8] — General purpose digital input/output pin.

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

n.c.

O

I/O

O

I/O

LCDLE — Line end signal.

GPIO3[9] — General purpose digital input/output pin.

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

I2S_TX_WS — Transmit Word Select. It is driven by the master and received

by the slave. Corresponds to the signal WS in the I²S-bus specification.

O

LCDVD19 — LCD data.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

15 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P7_2^[2]

A16 I; PU

I/O

I

GPIO3[10] — General purpose digital input/output pin.

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

I/O

I2S_TX_SDA — I²S transmit data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S-bus specification.

O

I/O

I

LCDVD18 — LCD data.

P7_3^[2]

P7_4^[2]

P7_5^[2]

P7_6^[2]

C13 I; PU

GPIO3[11] — General purpose digital input/output pin.

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

n.c.

-

O

I/O

O

-

LCDVD17 — LCD data.

C8

A7

C7

I; PU

GPIO3[12] — General purpose digital input/output pin.

CTOUT_13 — SCT output 13. Match output 1 of timer 3.

n.c.

O

I/O

O

-

LCDVD16 — LCD data.

GPIO3[13] — General purpose digital input/output pin.

CTOUT_12 — SCT output 12. Match output 0 of timer 3.

n.c.

O

I/O

O

-

LCDVD8 — LCD data.

GPIO3[14] — General purpose digital input/output pin.

CTOUT_11 — SCT output 1. Match output 3 of timer 2.

n.c.

O

LCDLP — Line synchronization pulse (STN). Horizontal synchronization

pulse (TFT).

P7_7^[2]

P8_0^[2]

B6

E5

I; PU

I/O

O

GPIO3[15] — General purpose digital input/output pin.

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

n.c.

-

O

LCDPWR — LCD panel power enable.

GPIO4[0] — General purpose digital input/output pin.

I/O

O

USB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external circuitry

required to detect over-current condition).

-

n.c.

I

MCI2 — Motor control PWM channel 2, input.

GPIO4[1] — General purpose digital input/output pin.

USB0_IND1 — USB0 port indicator LED control output 1.

n.c.

P8_1^[2]

P8_2^[2]

H5

K4

I; PU

I/O

O

-

I

MCI1 — Motor control PWM channel 1, input.

GPIO4[2] — General purpose digital input/output pin.

USB0_IND0 — USB0 port indicator LED control output 0.

n.c.

I/O

O

-

I

MCI0 — Motor control PWM channel 0, input.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

16 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P8_3^[2]

P8_4^[2]

P8_5^[2]

P8_6^[2]

J3

J2

J1

K3

I; PU

I/O

-

GPIO4[3] — General purpose digital input/output pin.

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

n.c.

O

LCDVD12 — LCD data.

I/O

-

GPIO4[4] — General purpose digital input/output pin.

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

n.c.

O

LCDVD7 — LCD data.

I/O

-

GPIO4[5] — General purpose digital input/output pin.

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

n.c.

O

LCDVD6 — LCD data.

I/O

I

GPIO4[6] — General purpose digital input/output pin.

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the

PHY.

-

n.c.

O

I/O

O

LCDVD5 — LCD data.

P8_7^[2]

K1

L1

I; PU

GPIO4[7] — General purpose digital input/output pin.

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt

transfers to the PHY.

-

n.c.

O

-

LCDVD4 — LCD data.

P8_8^[2]

<tbd>

n.c.

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the

PHY.

-

n.c.

-

n.c.

P9_0^[2]

P9_1^[2]

P9_2^[2]

T1

N6

N8

I; PU

I/O

O

-

GPIO4[12] — General purpose digital input/output pin.

MCABORT — Motor control PWM, LOW-active fast abort.

n.c.

-

n.c.

I/O

O

-

GPIO4[13] — General purpose digital input/output pin.

MCOA2 — Motor control PWM channel 2, output A.

n.c.

-

n.c.

I/O

O

-

GPIO4[14] — General purpose digital input/output pin.

MCOB2 — Motor control PWM channel 2, output B.

n.c.

-

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

17 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

P9_3^[2]

P9_4^[2]

P9_5^[2]

P9_6^[2]

M6

I; PU

I/O

O

-

GPIO4[15] — General purpose digital input/output pin.

MCOA0 — Motor control PWM channel 0, output A.

USB1_IND1 — USB1 Port indicator LED control output 1.

n.c.

N10 <tbd>

-

n.c.

O

-

MCOB0 — Motor control PWM channel 0, output B.

USB1_IND0 — USB1 Port indicator LED control output 0.

n.c.

M9

<tbd>

-

n.c.

O

-

MCOA1 — Motor control PWM channel 1, output A.

USB1_VBUS_EN — USB1 VBUS power enable.

n.c.

L11 I; PU

I/O

O

GPIO4[11] — General purpose digital input/output pin.

MCOB1 — Motor control PWM channel 1, output B.

USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current

condition; this signal monitors over-current on the USB1 bus (external

circuitry required to detect over-current condition).

-

n.c.

PA_0^[2]

PA_1^[2]

PA_2^[2]

PA_3^[2]

PA_4^[2]

L12 <tbd>

J14 I; PU

K15 I; PU

H11 I; PU

G13 <tbd>

-

n.c.

O

SPIFI_SCK — Serial clock for SPIFI.

-

n.c.

-

n.c.

I/O

GPIO4[8] — General purpose digital input/output pin.

I

QEI_IDX — Quadrature Encoder Interface INDEX input.

-

n.c.

-

n.c.

I/O

GPIO4[9] — General purpose digital input/output pin.

I

QEI_PHB — Quadrature Encoder Interface PHB input.

-

n.c.

-

n.c.

I/O

I

GPIO4[10] — General purpose digital input/output pin.

QEI_PHA — Quadrature Encoder Interface PHA input.

-

n.c.

I/O

-

SPIFI_SIO3 — I/O lane 3 for SPIFI.

n.c.

O

-

CTOUT_9 — SCT output 9. Match output 1 of timer 2.

n.c.

I/O

EXTBUS_A23 — External memory address line 23.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

18 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PB_0^[2]

PB_1^[2]

B15 <tbd>

A14 <tbd>

-

n.c.

O

-

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

LCDVD23 — LCD data.

n.c.

-

I

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line

direction.

O

-

LCDVD22 — LCD data.

n.c.

PB_2^[2]

PB_3^[2]

PB_4^[2]

PB_5^[2]

PB_6^[2]

PC_0^[2]

B12 <tbd>

A13 <tbd>

B11 <tbd>

A12 <tbd>

-

n.c.

I/O

O

-

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

LCDVD21 — LCD data.

n.c.

-

n.c.

I/O

O

-

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

LCDVD20 — LCD data.

n.c.

-

n.c.

I/O

O

-

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

LCDVD15 — LCD data.

n.c.

-

n.c.

I/O

O

-

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

LCDVD14 — LCD data.

n.c.

A6

D4

<tbd>

-

n.c.

I/O

O

-

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

LCDVD13 — LCD data.

n.c.

<tbd> I/O

ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock (MII

interface) or Ethernet Reference Clock (RMII interface).

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the

PHY.

-

n.c.

I/O

SDIO_CLK — SD/MMC card clock.

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

SDIO_VOLT0 — SD/MMC bus voltage select output 0.

U1_RI — Ring Indicator input for UART 1.

ENET_MDC — Ethernet MIIM clock.

PC_1^[2]

E4

<tbd> I/O

O

I

O

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

19 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PC_2^[2]

PC_3^[2]

F6

F5

<tbd> I/O

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

SDIO_RST — SD/MMC reset signal for MMC4.4 card.

O

I

U1_CTS — Clear to Send input for UART 1.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

SDIO_VOLT1 — SD/MMC bus voltage select output 1.

<tbd> I/O

O

U1_RTS — Request to Send output for UART 1. Can also be configured to be

an RS-485/EIA-485 output enable signal for UART 1.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

SDIO_D0 — SD/MMC data bus line 0.

PC_4^[2]

PC_5^[2]

PC_6^[2]

PC_7^[2]

PC_8^[2]

PC_9^[2]

F4

G4

H6

G5

N4

K2

<tbd> I/O

I/O

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

SPIFI_CS — SPIFI serial flash chip select.

ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface).

SDIO_D1 — SD/MMC data bus line 1.

I/O

O

<tbd> I/O

I/O

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

SPIFI_MISO — Input I1 in SPIFI quad mode; SPIFI output IO1.

ENET_TX_ER — Ethernet Transmit Error (MII interface).

SDIO_D2 — SD/MMC data bus line 2.

I/O

O

<tbd> I/O

I/O

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

n.c.

-

I

ENET_RXD2 — Ethernet receive data 2 (RMII/MII interface).

SDIO_D3 — SD/MMC data bus line 3.

<tbd> I/O

I/O

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

n.c.

-

I

ENET_RXD3 — Ethernet receive data 3 (RMII/MII interface).

SDIO_CD — SD/MMC card detect input.

<tbd>

I

I/O

I

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

SPIFI_SIO2 — I/O lane 2 for SPIFI.

ENET_RX_DV — Ethernet Receive Data Valid (MII interface).

SDIO_POW — <tbd>.

O

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the

PHY.

-

I

n.c.

ENET_RX_ER — Ethernet receive error (RMII/MII interface).

SDIO_CMD — SD/MMC command signal.

PC_10^[2]

M5

<tbd> I/O

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt

transfers to the PHY.

I

U1_DSR — Data Set Ready input for UART 1.

-

n.c.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

20 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PC_11^[2]

L5

L6

<tbd> I/O

I

SDIO_D4 — SD/MMC data bus line 4.

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line

direction.

I

U1_DCD — Data Carrier Detect input for UART 1.

-

n.c.

PC_12^[2]

<tbd> I/O

SDIO_D5 — SD/MMC data bus line 5.

-

n.c.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also be configured

to be an RS-485/EIA-485 output enable signal for UART 1.

-

n.c.

PC_13^[2]

PC_14^[2]

PD_0^[2]

PD_1^[2]

PD_2^[2]

PD_3^[2]

PD_4^[2]

M1

N1

N2

P1

R1

P4

T2

<tbd> I/O

SDIO_D6 — SD/MMC data bus line 6.

-

n.c.

O

U1_TXD — Transmitter output for UART 1.

-

n.c.

<tbd> I/O

SDIO_D7 — SD/MMC data bus line 7.

-

I

n.c.

U1_RXD — Receiver input for UART 1.

-

n.c.

<tbd>

-

n.c.

O

-

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

EXTBUS_DQMOUT2 — Data mask 2 used with SDRAM and static devices.

n.c.

-

n.c.

-

n.c.

O

-

EXTBUS_CKEOUT2 — SDRAM clock enable 2.

n.c.

-

n.c.

O

I/O

-

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

EXTBUS_D16 — External memory data line 16.

n.c.

-

n.c.

O

I/O

-

CTOUT_6 — SCT output 7. Match output 2 of timer 1.

EXTBUS_D17 — External memory data line 17.

n.c.

-

n.c.

O

I/O

-

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

EXTBUS_D18 — External memory data line 18.

n.c.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

21 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PD_5^[2]

PD_6^[2]

PD_7^[2]

PD_8^[2]

PD_9^[2]

PD_10^[2]

PD_11^[2]

PD_12^[2]

PD_13^[2]

P6

R6

T6

P8

<tbd>

-

n.c.

O

I/O

-

CTOUT_9 — SCT output 9. Match output 1 of timer 2.

EXTBUS_D19 — External memory data line 19.

n.c.

-

n.c.

O

I/O

-

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

EXTBUS_D20 — External memory data line 20.

n.c.

-

n.c.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

I/O

-

EXTBUS_D21 — External memory data line 21.

n.c.

-

n.c.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

I/O

-

EXTBUS_D22 — External memory data line 22.

n.c.

T11 <tbd>

P11 <tbd>

-

n.c.

O

I/O

-

CTOUT_13 — SCT output 13. Match output 1 of timer 3.

EXTBUS_D23 — External memory data line 23.

n.c.

-

n.c.

I

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2.

O

-

EXTBUS_BLS3 — LOW active Byte Lane select signal 3.

n.c.

N9

<tbd>

-

n.c.

-

n.c.

O

-

EXTBUS_CS3 — LOW active Chip Select 3 signal.

n.c.

N11 <tbd>

T14 <tbd>

-

n.c.

-

n.c.

O

-

EXTBUS_CS2 — LOW active Chip Select 2 signal.

n.c.

-

n.c.

I

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

EXTBUS_BLS2 — LOW active Byte Lane select signal 2.

n.c.

O

-

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

22 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PD_14^[2]

PD_15^[2]

PD_16^[2]

PE_0^[2]

PE_1^[2]

PE_2^[2]

PE_3^[2]

PE_4^[2]

PE_5^[2]

R13 <tbd>

T15 <tbd>

R14 <tbd>

P14 <tbd>

N14 <tbd>

M14 <tbd>

K12 <tbd>

K13 <tbd>

N16 <tbd>

-

n.c.

-

O

EXTBUS_DYCS2 — SDRAM chip select 2.

-

n.c.

-

n.c.

-

n.c.

I/O

EXTBUS_A17 — External memory address line 17.

-

n.c.

-

n.c.

-

n.c.

I/O

EXTBUS_A16 — External memory address line 16.

-

n.c.

-

n.c.

-

n.c.

-

n.c.

I/O

EXTBUS_A18 — External memory address line 18.

-

n.c.

-

n.c.

-

n.c.

I/O

I

EXTBUS_A19 — External memory address line 19.

ADCTRIG0 — ADC trigger input 0.

CAN1_RD — CAN1 receiver input.

SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.

EXTBUS_A20 — External memory address line 20.

n.c.

I

I/O

-

O

I

CAN1_TD — CAN1 transmitter output.

ADCTRIG1 — ADC trigger input 1.

EXTBUS_A21 — External memory address line 21.

n.c.

I/O

-

I

NMI — External interrupt input to NMI.

n.c.

-

I/O

-

EXTBUS_A22 — External memory address line 22.

n.c.

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

U1_RTS — Request to Send output for UART 1. Can also be configured to be

an RS-485/EIA-485 output enable signal for UART 1.

I/O

EXTBUS_D24 — External memory data line 24.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

23 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PE_6^[2]

PE_7^[2]

PE_8^[2]

PE_9^[2]

PE_10^[2]

M16 <tbd>

F15 <tbd>

F14 <tbd>

E16 <tbd>

E14 <tbd>

-

n.c.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

U1_RI — Ring Indicator input for UART 1.

EXTBUS_D25 — External memory data line 25.

n.c.

I

I/O

-

O

CTOUT_5 — SCT output 5. Match output 1 of timer 1.

U1_CTS — Clear to Send input for UART1.

EXTBUS_D26 — External memory data line 26.

n.c.

I

I/O

-

O

CTOUT_4 — SCT output 4. Match output 0 of timer 0.

U1_DSR — Data Set Ready input for UART 1.

EXTBUS_D27 — External memory data line 27.

n.c.

I

I/O

-

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

U1_DCD — Data Carrier Detect input for UART 1.

EXTBUS_D28 — External memory data line 28.

n.c.

I

I/O

-

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also be configured

to be an RS-485/EIA-485 output enable signal for UART 1.

I/O

-

EXTBUS_D29 — External memory data line 29.

n.c.

PE_11^[2]

PE_12^[2]

PE_13^[2]

D16 <tbd>

D15 <tbd>

G14 <tbd>

O

I/O

-

CTOUT_12 — SCT output 12. Match output 0 of timer 3.

U1_TXD — Transmitter output for UART 1.

EXTBUS_D30 — External memory data line 30.

n.c.

O

I

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

U1_RXD — Receiver input for UART 1.

EXTBUS_D31 — External memory data line 31.

n.c.

I/O

-

O

I/O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

I2C1_SDA — I²C1 data input/output (this pin does not use a specialized I²C

pad).

O

-

EXTBUS_DQMOUT3 — Data mask 3 used with SDRAM and static devices.

PE_14^[2]

C15 <tbd>

n.c.

-

n.c.

-

n.c.

O

EXTBUS_DYCS3 — SDRAM chip select 3.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

24 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PE_15^[2]

E13 <tbd>

-

n.c.

O

I/O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

I2C1_SCL — I²C1 clock input/output (this pin does not use a specialized I²C

pad).

O

EXTBUS_CKEOUT3 — SDRAM clock enable 3.

PF_0^[2]

PF_1^[2]

PF_2^[2]

PF_3^[2]

PF_4^[2]

PF_5^[2]

PF_6^[2]

PF_7^[2]

D12 <tbd> I/O

SSP0_SCK — Serial clock for SSP0.

-

n.c.

E11 <tbd>

D11 <tbd>

E10 <tbd>

-

n.c.

-

n.c.

I/O

SSP0_SSEL — Slave Select for SSP0.

-

n.c.

-

n.c.

O

U3_TXD — Transmitter output for USART3.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

n.c.

-

n.c.

I

U3_RXD — Receiver input for USART3.

SSP0_MOSI — Master Out Slave in for SSP0.

n.c.

I/O

-

D10 <tbd> I/O

SSP1_SCK — Serial clock for SSP1.

GP_CLKIN — General purpose clock input to the CGU.

TRACECLK — Trace clock.

I

O

-

n.c.

E9

E7

B7

<tbd>

-

n.c.

I/O

O

U3_UCLK — Serial clock input/output for USART3 in synchronous mode.

SSP1_SSEL — Slave Select for SSP1.

TRACEDATA[0] — Trace data, bit 0.

n.c.

-

I/O

O

U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.

SSP1_MISO — Master In Slave Out for SSP1.

TRACEDATA[1] — Trace data, bit 1.

n.c.

-

I/O

O

U3_BAUD — <tbd> for USART3.

SSP1_MOSI — Master Out Slave in for SSP1.

TRACEDATA[2] — Trace data, bit 2.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

25 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

PF_8^[2]

PF_9^[2]

PF_10^[2]

PF_11^[2]

E6

D6

A3

A2

<tbd>

-

n.c.

I/O

I

U0_UCLK — Serial clock input/output for USART0 in synchronous mode.

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

O

-

TRACEDATA[3] — Trace data, bit 3.

n.c.

I/O

O

-

U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.

CTOUT_1 — SCT output 1. Match output 1 of timer 0.

n.c.

-

n.c.

O

I

U0_TXD — Transmitter output for USART0.

SDIO_WP — SD/MMC card write protect input.

-

n.c.

-

n.c.

I

U0_RXD — Receiver input for USART0.

O

-

SDIO_VOLT2 — SD/MMC bus voltage select output 2.

n.c.

Clock pins

CLK0^[4]

N5

<tbd>

O

-

EXTBUS_CLK0 — SDRAM clock 0.

CLKOUT — Clock output pin.

n.c.

-

n.c.

CLK1^[2]

CLK2^[2]

CLK3^[2]

T10 <tbd>

D14 <tbd>

P12 <tbd>

O

-

EXTBUS_CLK1 — SDRAM clock 1.

CLKOUT — Clock output pin.

n.c.

-

n.c.

O

-

EXTBUS_CLK3 — SDRAM clock 3.

CLKOUT — Clock output pin.

n.c.

-

n.c.

O

-

EXTBUS_CLK2 — SDRAM clock 2.

CLKOUT — Clock output pin.

n.c.

-

n.c.

Debug pins

DBGEN^[2]

TCK/SWDCLK^[2]

TRST^[2]

TMS/SWDIO^[2]

TDO/SWO^[2]

-

L4

J5

<tbd>

I

JTAG interface control signal. Also used for boundary scan.

Test Clock for JTAG interface (default) or Serial Wire (SW) clock.

Test Reset for JTAG interface.

I

M4

K6

K5

I

Test Mode Select for JTAG interface (default) or SW debug data input/output.

Test Data Out for JTAG interface (default) or SW trace output.

O

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

26 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

TDI^[2]

J4

<tbd>

I

Test Data In for JTAG interface.

I²C-bus pins

I2C0_SCL^[8]

I2C0_SDA^[8]

USB0 pins

USB0_DP^[5]

USB0_DM^[5]

USB0_VBUS^[5]

USB0_ID^[6]

L15 <tbd> I/O

L16 <tbd> I/O

I²C clock input/output. Open-drain output (for I²C-bus compliance).

I²C data input/output. Open-drain output (for I²C-bus compliance).

F2

G2

F1

H2

<tbd> I/O

USB0 bidirectional D+ line.

USB0 bidirectional D− line.

VBUS pin (power on USB cable).

<tbd>

I

Indicates to the transceiver whether connected a A-device (ID LOW) or

B-device (ID HIGH).

USB0_RREF^[6]

USB1 pins

H1

<tbd>

12.0 kΩ (accuracy 1 %) on-board resistor to ground for current reference.

USB1_DP^[7]

USB1_DM^[7]

F12 <tbd> I/O

G12 <tbd> I/O

USB1 bidirectional D+ line.

USB1 bidirectional D− line.

Reset and wake-up pins

RESET^[9]

D9

<tbd>

I

External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0.

WAKEUP0^[9]

WAKEUP1

WAKEUP2

WAKEUP3

A9

I

External wake-up input; can raise an interrupt and can cause wake-up from

any of the low power modes.

A10 <tbd>

External wake-up input; can raise an interrupt and can cause wake-up from

any of the low power modes.

C9

D8

<tbd>

External wake-up input; can raise an interrupt and can cause wake-up from

any of the low power modes.

External wake-up input; can raise an interrupt and can cause wake-up from

any of the low power modes.

ADC pins

ADC0^[6]

ADC1^[6]

ADC2^[6]

ADC3^[6]

ADC4^[6]

ADC5^[6]

ADC6^[6]

ADC7^[6]

E3

C3

A4

B5

C6

B3

A5

C5

<tbd>

ADC0/1 input channel 0. Shared between ADC0, ADC1, and DAC.

ADC0/1 input channel 1.

ADC0/1 input channel 2.

ADC0/1 input channel 3.

ADC0/1 input channel 4.

ADC0/1 input channel 5.

ADC0/1 input channel 6.

ADC0/1 input channel 7.

RTC

RTC_ALARM

RTCX1

A11

A8

-

RTC controlled output.

Input to the RTC 32 kHz ultra-low power oscillator circuit.

Output from the RTC 32 kHz ultra-low power oscillator circuit.

RTCX2

B8

Crystal oscillator pins

XTAL1^[6]

D1

-

I

Input to the oscillator circuit and internal clock generator circuits.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

27 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

XTAL2^[6]

E1

-

O

Output from the oscillator amplifier.

Power and ground pins

USB0_VDDA3V3_

DRIVER

F3

<tbd>

Separate analog 3.3 V power supply for driver.

USB0_VDDA3V3

G3

<tbd>

USB 3.3 V separate power supply voltage

USB0_VSSA_TERM H3

Dedicated analog ground for clean reference for termination resistors.

USB0_VSSA_REF

G1

Dedicated clean analog ground for generation of reference currents and

voltages.

VDDA

B4

-

Analog power supply.

VBAT

B10

RTC power supply: 3.3 V on this pin supplies power to the RTC.

Main regulator power supply

VDDREG

F10;

F9;

L8;

L7;

VPP

E8

OTP programming voltage

I/O power supply

VDDIO

F7;

J7;

N7;

L10;

E12;

N13;

L9;

H10;

G10;

D7;

J6;

F8;

K7

VSSA

VSS

B2

-

Ground

H7;

K8;

G9;

J11;

J10

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

28 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

Pin description …continued

Reset Type Description

state

[1]

VSSIO

G6;

J8;

Ground

J9;

K9;

K10;

P7;

M13;

P13;

D13;

G8;

H8;

G7;

C4;

H9

Pins not connected

-

B9

-

n.c.

[1] I = input, O = output, IA = inactive; PU = pull-up enabled; F = floating

[2] Digital I/O pin. Not 5 V tolerant.

[3] Digital I/O pin. 5 V tolerant.

[4] Digital high-speed I/O pin.

[5] 5 V tolerant analog I/O pin.

[6] 3.3 V tolerant analog I/O pin.

[7] 5 V tolerant USB I/O pin.

[8] I²C-bus 5 V tolerant open-drain pin.

[9] Reset input pin; <tbd>.

[10] Alarm output pin; <tbd>.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

29 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses allow for concurrent code and data

accesses from different slave ports.

The LPC1850/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M3

buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slaves ports of the matrix to be

accessed simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptable/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller with wake-up interrupt

controller, and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

30 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.3 AHB multilayer matrix

TEST/DEBUG

INTERFACE

ARM

CORTEX-M3

SD/

MMC

(1)

GPDMA

1

ETHERNET

USB0

USB1

LCD

masters

(1)

System

bus

I-code D-code

0

bus

slaves

32 kB ROM

64/96 kB LOCAL SRAM

40 kB LOCAL SRAM

32 kB AHB SRAM

(1)

16 kB AHB SRAM

EXTERNAL

MEMORY

CONTROLLER

AHB REGISTER

INTERFACES,

APB, RTC DOMAIN

PERIPHERALS

AHB MULTILAYER MATRIX

= master-slave connection

002aaf880

(1) Not available on all parts (see Table 2).

Fig 3. AHB multilayer matrix master and slave connections

7.4 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.4.1 Features

• Controls system exceptions and peripheral interrupts.

• In the LPC1850/30/20/10, the NVIC supports 32 vectored interrupts.

• 32 programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

31 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.4.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

7.5 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up

signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down,

and Deep power-down modes. Individual events can be configured as edge or level

sensitive and can be enabled or disabled in the event router. The event router can be

battery powered.

The following events if enabled in the event router can create a wake-up signal and/or an

interrupt:

• External pins WAKEUP0/1/2/3 and RESET

• Alarm timer, RTC, WWDT, BOD interrupts

• C_CAN and QEI interrupts

• Ethernet, USB0, USB1 signals

• Selected outputs of combined timers (SCT and timer0/1/3)

7.6 System Tick timer (SysTick)

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.7 On-chip static RAM

The LPC1850/30/20/10 support up to 200 kB SRAM with separate bus master access for

higher throughput and individual power control for low power operation.

7.8 Boot ROM

The internal ROM memory is used to store the boot code of the LPC1850/30/20/10. After

a reset, the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

• ROM memory size is 32 kB.

• Supports booting from UART interfaces and external static memory such as NOR

flash, SPI flash, quad SPI flash.

• Includes APIs for power control and OTP programming.

• Includes SPIFI and USB drivers.

AES capable parts also support:

• CMAC authentication on the boot image.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

32 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

• Secure booting from an encrypted image. In development mode booting from a plain

text image is possible. Development mode is terminated by programming the AES

key.

• API for AES programming.

Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If

the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is

determined by the states of the boot pins P2_8, P1_2, and P1_1.

Table 4.

Boot mode when OTP BOOT_SRC bits are programmed

BOOT_SRC BOOT_SRC BOOT_SRC Description

Boot mode

bit 2

bit 1

bit 0

Boot mode

defined by pin

state at reset

0

Boot source is defined by the

reset state of P1_1, P1_2, and

P2_8 pins. See Table 5.

UART

0

1

0

1

0

1

0

1

0

1

Boot from device connected to

USART0 using pins P2_0 and

P2_1.

SPIFI

Boot from Quad SPI flash

connected to the SPIFI interface

using pins P3_3 to P3_8.

EMC 8-bit

EMC 16-bit

EMC 32-bit

Boot from external static memory

(such as NOR flash) using CS0

and an 8-bit data bus.

Boot from external static memory

(such as NOR flash) using CS0

and a 16-bit data bus.

Boot from external static memory

(such as NOR flash) using CS0

and a 32-bit data bus.

Reserved

1

0

1

Do not use this option.

Table 5.

Boot mode

UART

Boot mode when OPT BOOT_SRC bits are zero

P2_8

P1_2

P1_1 Description

LOW

LOW Boot from device connected to USART0 using pins

P2_0 and P2_1.

SPIFI

LOW

HIGH

LOW

HIGH

LOW

HIGH Boot from Quad SPI flash connected to the SPIFI

interface on P3_3 to P3_8^[1].

EMC 8-bit

EMC 16-bit

EMC 32-bit

LOW Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

HIGH Boot from external static memory (such as NOR

flash) using CS0 and a 16-bit data bus.

LOW Boot from external static memory (such as NOR

flash) using CS0 and a 32-bit data bus.

Reserved

SPI

HIGH

LOW

HIGH

HIGH Do not use this option.

LOW Do not use this option.

HIGH Boot from SPI flash connected to the SSP0

interface on P3_3, P3_6, P3_7 and P3_8^[1].

[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

33 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.9 Memory mapping

LPC1850/30/20/10

4 GB

0xFFFF FFFF

reserved

0xE010 0000

ARM private bus

0xE000 0000

reserved

0x8800 0000

SPIFI data

0x8000 0000

256 MB dynamic external memory DYCS3

0x7000 0000

0x6000 0000

256 MB dynamic external memory DYCS2

reserved

0x4400 0000

0x4200 0000

0x4010 2000

peripheral bit band alias region

reserved

0x4010 1000

0x4010 0000

0x400F 2000

AES

0x400F 1000

0x400F 0000

0x400E 0000

0x400D 0000

0x400C 0000

high-speed GPIO

APB peripherals #3

reserved

APB peripherals #2

reserved

0x400B 0000

0x400A 0000

0x4009 0000

0x4008 0000

0x2000 0000

0x1F00 0000

0x1E00 0000

0x1D00 0000

0x1C00 0000

APB peripherals #1

16 MB static external memory CS3

reserved

16 MB static external memory CS2

16 MB static external memory CS1

APB peripherals #0

16 MB static external memory CS0

reserved

0x4006 0000

0x4005 0000

0x4004 0000

clocking/reset peripherals

RTC domain peripherals

reserved

0x4001 2000

0x4000 0000

reserved

AHB peripherals

1 GB

256 MB dynamic external memory DYCS1

128 MB dynamic external memory DYCS0

0x3000 0000

0x2800 0000

0x1040 8000

reserved

32 kB ROM

reserved

0x1040 0000

0x1008 A000

0x2400 0000

32 MB AHB SRAM bit banding

reserved

0x2200 0000

0x2001 0000

32 kB + 8 kB local SRAM

(LPC1850/30/20/10)

0x1008 0000

0x1001 8000

0x1001 0000

16 kB AHB SRAM (LPC1850/30/20)

16 kB AHB SRAM (LPC1850/30/20/10)

16 kB AHB SRAM (LPC1850/30/20)

reserved

0x2000 C000

0x2000 8000

32 kB local SRAM (LPC1850/30)

0x2000 4000

0x2000 0000

64 kB local SRAM

(LPC1850/30/20/10)

16 kB AHB SRAM (LPC1850/30/20/10)

0x1000 0000

local SRAM/

external static memory banks

0x1000 0000

256 MB shadow area

0x0000 0000

0 GB

002aaf228

Fig 4. LPC1850/30/20/10 Memory mapping (overview)

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

34 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.10 Security features

7.10.1 AES decryption engine

The hardware AES engine can decrypt data using the AES algorithm.

7.10.1.1 Features

• Decryption of external flash data connected to the quad SPI Flash Interface (SPIFI).

• Secure storage of decryption keys.

• Support for CMAC hash calculation to authenticate encrypted data.

• Data is processed in little endian mode. This means that the first byte read from flash

is integrated into the AES codeword as least significant byte. The 16th byte read from

flash is the most significant byte of the first AES codeword.

• AES engine performance of 1 byte/clock cycle.

• DMA transfers supported through the GPDMA.

7.10.2 One-Time Programmable (OTP) memory

The OTP provides two 128-bit non-volatile memories to store AES decryption keys or

other custom data.

7.11 General Purpose I/O (GPIO)

The LPC1850/30/20/10 provides 5 GPIO ports with up to 16 GPIO pins each.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

All GPIO pins default to inputs with pull-up resistors enabled on reset.

7.11.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

36 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.12 AHB peripherals

7.12.1 State Configurable Timer (SCT) subsystem

The SCT allows a wide variety of timing, counting, output modulation, and input capture

operations. The inputs and outputs of the SCT are shared with the capture and match

inputs/outputs of the 32-bit general purpose counter/timers.

The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the

two-counter case, in addition to the counter value the following operational elements are

independent for each half:

• State variable

• Limit, halt, stop, and start conditions

• Values of Match/Capture registers, plus reload or capture control values

In the two-counter case, the following operational elements are global to the SCT, but the

last three can use match conditions from either counter:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

7.12.1.1 Features

• Two 16-bit counters or one 32-bit counter.

• Counter(s) clocked by bus clock or selected input.

• Up counter(s) or up-down counter(s).

• State variable allows sequencing across multiple counter cycles.

• Event combines input or output condition and/or counter match in a specified state.

• Events control outputs and interrupts.

• Selected event(s) can limit, halt, start, or stop a counter.

• Supports:

– up to 8 inputs (one input connected internally)

– up to 16 outputs

– 16 match/capture registers

– 16 events

– 32 states

7.12.2 General Purpose DMA (GPDMA)

The DMA controller allows peripheral-to memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

37 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral for

master 1, but only memory for master 0.

7.12.2.1 Features

• Eight DMA channels. Each channel can support an unidirectional transfer.

• 16 DMA request lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers are supported.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

• Two AHB bus masters for transferring data. These interfaces transfer data when a

DMA request goes active. Master 1 can access memories and peripherals, master 0

can access memories only.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

• Internal four-word FIFO per channel.

• Supports 8, 16, and 32-bit wide transactions.

• Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.12.3 SPI Flash Interface (SPIFI)

The SPI Flash Interface (allows low-cost serial flash memories to be connected to the

ARM Cortex-M3 processor with little performance penalty compared to parallel flash

devices with higher pin count.

After a few commands configure the interface at startup, the entire flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Erasure and programming are handled by simple sequences of

commands.

Many serial flash devices use a half-duplex command-driven SPI protocol for device setup

and initialization and then move to a half-duplex, command-driven 4-bit protocol for

normal operation. Different serial flash vendors and devices accept or require different

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

38 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.12.3.1 Features

• Interfaces to serial flash memory in the main memory map.

• Supports classic and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Data rates of up to 40 MB per second total.

• Supports DMA access.

7.12.4 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:

• Secure Digital memory (SD version 3.0)

• Secure Digital I/O (SDIO version 2.0)

• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)

• Multimedia Cards (MMC version 4.4)

7.12.5 External Memory Controller (EMC)

The LPC1850/30/20/10 EMC is a Memory Controller peripheral offering support for

asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it

can be used as an interface with off-chip memory-mapped devices and peripherals.

7.12.5.1 Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and NOR flash,

with or without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16/32 data and 24 address lines wide static memory support. On parts LPC1820/10

only 8/16 data lines are available.

• 16 bit and 32 bit wide chip select SDRAM memory support.

• Static memory features include:

– Asynchronous page mode read

– Programmable Wait States

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

• Four chip selects for synchronous memory and four chip selects for static memory

devices.

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

39 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB

parts, with 4, 8, 16, or 32 data bits per device.

• Separate reset domains allow the for auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

7.12.6 High-speed USB Host/Device/OTG interface (USB0)

Remark: USB0 is not available on the LPC1810 (see Table 2).

The USB OTG module allows the part to connect directly to a USB host such as a PC (in

device mode) or to a USB device in host mode.

7.12.6.1 Features

• Complies with Universal Serial Bus specification 2.0.

• Complies with USB On-The-Go supplement.

• Complies with Enhanced Host Controller Interface Specification.

• Supports auto USB 2.0 mode discovery.

• Supports all high-speed USB-compliant peripherals.

• Supports all full-speed USB-compliant peripherals.

• Supports software Host Negotiation Protocol (HNP) and Session Request Protocol

(SRP) for OTG peripherals.

• Contains UTMI+ compliant transceiver (PHY).

• Supports interrupts.

• This module has its own, integrated DMA engine.

7.12.7 High-speed USB Host/Device interface with ULPI (USB1)

Remark: USB1 is not available on the LPC1820/10 (see Table 2).

The USB1 interface can operate as a full-speed USB host/device interface or can connect

to an external ULPI PHY for High-speed operation.

7.12.7.1 Features

• Complies with Universal Serial Bus specification 2.0.

• Complies with Enhanced Host Controller Interface Specification.

• Supports auto USB 2.0 mode discovery.

• Supports all high-speed USB-compliant peripherals if connected to external ULPI

PHY.

• Supports all full-speed USB-compliant peripherals.

• Supports interrupts.

• This module has its own, integrated DMA engine.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

40 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.12.8 LCD controller

The LCD controller provides all of the necessary control signals to interface directly to a

variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be operated. The display resolution is selectable and can be up to 1024 × 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the

displayed data) while still supporting a large number of colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other system functions. A built-in FIFO acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time needed to operate the display.

7.12.8.1 Features

• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.

• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

• Supports single and dual-panel color STN displays.

• Supports Thin Film Transistor (TFT) color displays.

• Programmable display resolution including, but not limited to: 320 × 200, 320 × 240,

640 × 200, 640 × 240, 640 × 480, 800 × 600, and 1024 × 768.

• Hardware cursor support for single-panel displays.

• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

• 16 bpp true-color non-palettized for color STN and TFT.

• 24 bpp true-color non-palettized for color TFT.

• Programmable timing for different display panels.

• 256 entry, 16-bit palette RAM, arranged as a 128 × 32-bit RAM.

• Frame, line, and pixel clock signals.

• AC bias signal for STN, data enable signal for TFT panels.

• Supports little and big-endian, and Windows CE data formats.

• LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

7.12.9 Ethernet

Remark: Ethernet is not available on the LPC1820/10 (see Table 2).

7.12.9.1 Features

• 10/100 Mbit/s

• TCP/IP hardware checksum

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

41 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

• IP checksum

• DMA support

• Power management remote wake-up frame and magic packet detection

• Supports both full-duplex and half-duplex operation

– Supports CSMA/CD Protocol for half-duplex operation.

– Supports IEEE 802.3x flow control for full-duplex operation.

– Optional forwarding of received pause control frames to the user application in

full-duplex operation.

– Back-pressure support for half-duplex operation.

– Automatic transmission of zero-quanta pause frame on deassertion of flow control

input in full-duplex operation.

7.13 Digital serial peripherals

7.13.1 UART1

The LPC1850/30/20/10 contain one UART with standard transmit and receive data lines,

UART1 also provides a full modem control handshake interface and support for

RS-485/9-bit mode allowing both software address detection and automatic address

detection using 9-bit mode.

UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd

can be achieved with any crystal frequency above 2 MHz.

7.13.1.1 Features

• Maximum UART data bit rate of <tbd> MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Equipped with standard modem interface signals. This module also provides full

support for hardware flow control (auto-CTS/RTS).

• Support for RS-485/9-bit/EIA-485 mode (UART1).

• DMA support.

7.13.2 USART0/2/3

The LPC1850/30/20/10 contain three USARTs. In addition to standard transmit and

receive data lines, the USARTs support a synchronous mode.

The USARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

42 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.13.2.1 Features

• Maximum UART data bit rate of <tbd> MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Support for RS-485/9-bit/EIA-485 mode.

• USART3 includes an IrDA mode to support infrared communication.

• All USARTs have DMA support.

• Support for synchronous mode.

• Smart card mode conforming to ISO7816 specification

7.13.3 SSP0/1 serial I/O controllers

The LPC1850/30/20/10 contain two SSP controllers. The SSP controller is capable of

operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data flowing from the master to the slave and from the slave to the master. In

practice, often only one of these data flows carries meaningful data.

7.13.3.1 Features

• Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.13.4 I²C0/1-bus interfaces

The LPC1850/30/20/10 each contain two I²C-bus controllers.

The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master connected to it.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

43 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.13.4.1 Features

• I²C0 is a standard I²C compliant bus interface with open-drain pins. I²C0 also

supports Fast mode plus with bit rates up to 1 Mbit/s.

• I²C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I²C-bus).

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

• All I²C-bus controllers support multiple address recognition and a bus monitor mode.

7.13.5 I²S interface

The I²S-bus provides a standard communication interface for digital audio applications.

The I²S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I²S-bus connection has one master, which is

always the master, and one slave. The I²S-bus interface provides a separate transmit and

receive channel, each of which can operate as either a master or a slave.

7.13.5.1 Features

• The interface has separate input/output channels each of which can operate in master

or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,

96) kHz.

• Support for an audio master clock.

• Configurable word select period in master mode (separately for I²S-bus input and

output).

• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

to the GPDMA block.

• Controls include reset, stop and mute options separately for I²S-bus input and I²S-bus

output.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

44 of 84

LPC1850/30/20/10

NXP Semiconductors

7.13.6 C_CAN

32-bit ARM Cortex-M3 microcontroller

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a very high level of security.

7.13.6.1 Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

• Provides programmable FIFO mode (concatenation of Message Objects).

• Provides maskable interrupts.

• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

• Provides programmable loop-back mode for self-test operation.

7.14 Counter/timers and motor control

7.14.1 General purpose 32-bit timers/external event counters

The LPC1850/30/20/10 include four 32-bit timer/counters. The timer/counter is designed

to count cycles of the system derived clock or an externally-supplied clock. It can

optionally generate interrupts, generate timed DMA requests, or perform other actions at

specified timer values, based on four match registers. Each timer/counter also includes

two capture inputs to trap the timer value when an input signal transitions, optionally

generating an interrupt.

7.14.1.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

45 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

• Up to two match registers can be used to generate timed DMA requests.

7.14.2 Motor control PWM

The motor control PWM is a specialized PWM supporting 3-phase motors and other

combinations. Feedback inputs are provided to automatically sense rotor position and use

that information to ramp speed up or down. An abort input is also provided that causes the

PWM to immediately release all motor drive outputs. At the same time, the motor control

PWM is highly configurable for other generalized timing, counting, capture, and compare

applications.

7.14.3 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two signals, the user can track the position, direction of rotation, and

velocity. In addition, a third channel, or index signal, can be used to reset the position

counter. The quadrature encoder interface decodes the digital pulses from a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In

addition, the QEI can capture the velocity of the encoder wheel.

7.14.3.1 Features

• Tracks encoder position.

• Increments/decrements depending on direction.

• Programmable for 2× or 4× position counting.

• Velocity capture using built-in timer.

• Velocity compare function with “less than” interrupt.

• Uses 32-bit registers for position and velocity.

• Three position compare registers with interrupts.

• Index counter for revolution counting.

• Index compare register with interrupts.

• Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

• Digital filter with programmable delays for encoder input signals.

• Can accept decoded signal inputs (clk and direction).

7.14.4 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 32-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.14.4.1 Features

• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.

• 32-bit compare value.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

46 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

• 32-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

7.14.5 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.14.5.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK)× 256 × 4) to (T_cy(WDCLK)× 2²⁴× 4) in

multiples of T_cy(WDCLK)× 4.

• The Watchdog Clock (WDCLK) uses the IRC as the clock source.

7.15 Analog peripherals

7.15.1 Analog-to-Digital Converter (ADC0/1)

7.15.1.1 Features

• 10-bit successive approximation analog to digital converter.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 to 3 V.

• Sampling frequency up to 400 kSamples/s.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer

outputs 8 or 15, or the PWM output MCOA2.

• Individual result registers for each A/D channel to reduce interrupt overhead.

• DMA support.

7.15.2 Digital-to-Analog Converter (DAC)

7.15.2.1 Features

• 10-bit resolution

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

47 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

• Integral Non-Linearity

• Differential Non-Linearity

• Monotonic by design (resistor string architecture)

• Controllable conversion speed

• Low power consumption

7.16 Peripherals in the RTC power domain

7.16.1 RTC

The Real Time Clock (RTC) is a set of counters for measuring time when system power is

on, and optionally when it is off. It uses very little power when its registers are not being

accessed by the CPU, especially reduced power modes. The RTC is clocked by a

separate 32 kHz oscillator that produces a 1 Hz internal time reference and is powered by

its own power supply pin, VBAT.

7.16.1.1 Features

• Measures the passage of time to maintain a calendar and clock. Provides seconds,

minutes, hours, day of month, month, year, day of week, and day of year.

• Ultra-low power design to support battery powered systems. Less than <tbd> required

for battery operation. Uses power from the CPU power supply when it is present.

• Dedicated battery power supply pin.

• RTC power supply is isolated from the rest of the chip.

• Calibration counter allows adjustment to better than ±1 sec/day with 1 sec resolution.

• Periodic interrupts can be generated from increments of any field of the time registers.

• Alarm interrupt can be generated for a specific date/time.

7.16.2 Alarm timer

The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating

alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00

and asserts an interrupt if enabled.

The alarm timer is part of the RTC power domain and can be battery powered.

7.17 System control

7.17.1 Configuration registers (CREG)

The following settings are controlled in the configuration register block:

• BOD trip settings

• Oscillator output

• DMA-to-peripheral muxing

• Ethernet mode

• Memory mapping

• Timer/USART inputs

• Enabling the USB controllers

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

48 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

In addition, the CREG block contains the part identification and part configuration

information.

7.17.2 System Control Unit (SCU)

The system control unit determines the function and electrical mode of the digital pins. By

default function 0 is selected for all pins with pull-up enabled.

Analog I/Os for the ADCs and the DAC as well as most USB pins are on separate pads

and are not controlled through the SCU.

7.17.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The base clocks may be

unrelated in frequency and phase and can have different clock sources within the CGU.

One CGU base clock is routed to the CLKOUT pins.

Derived from each base clock may be multiple branch clocks. The branch clocks offer

very flexible control for power-management purposes. All branch clocks are outputs of

one of two Clock Control Units (CCUs) and can be controlled independently. Branch

clocks derived from the same base clock are synchronous in frequency and phase.

7.17.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC1850/30/20/10 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.17.5 PLL0 (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

7.17.6 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop

to keep the CCO within its frequency range while the PLL is providing the desired output

frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output

clock. Since the minimum output divider value is 2, it is insured that the PLL output has a

50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be

enabled by software. The program must configure and activate the PLL, wait for the PLL

to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 μs.

7.17.7 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

49 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.17.8 Power control

The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep,

Power-down, and Deep power-down.

The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep

power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery

powered blocks in the RTC power domain.

7.18 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

50 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

Parameter

Conditions

Min

2.2^[2]

2.2

Max

3.6

Unit

V

V_DD(REG)(3V3)regulator supply voltage (3.3 V)

on pin VDD_REG

on pin VDDIO

on pin VDDA

for the RTC

V_DD(IO)

V_DDA(3V3)

V_BAT

I/O supply voltage

analog supply voltage (3.3 V)

battery supply voltage

polyfuse programming

voltage

V

2.0

V

2.2

V

V^prog(pf)

on pin VPP

2.7

V

V_IA

V_I

analog input voltage

input voltage

on ADC pins

0

V_DDA(3V3)

3.6

V

[3]

only valid when the

V_DD(IO)supply

2.0

voltage is present

[4]

I_DD

supply current

per supply pin

per ground pin

-

<tbd>

mA

I_SS

ground current

I/O latch-up current

I_latch

−(0.5V_DD(IO)) < V_I<

(1.5V_DD(IO));

T_j< 125 °C

[5]

[6]

T_stg

storage temperature

<tbd>

-

<tbd>

°C

P_tot(pack)

total power dissipation (per package)

based on package

heat transfer, not

device power

W

consumption

V_ESD

electrostatic discharge voltage

human body

<tbd>

V

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] 2.0 V if VBAT ≥ 2.2 V.

[3] Including voltage on outputs in 3-state mode; at 2.0 V the speed will be reduced.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] Dependent on package type.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

51 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

9. Thermal characteristics

The average chip junction temperature, T_j(°C), can be calculated using the following

equation:

T_j= T_amb+ (P_D× R_{th(j – a)}

)

(1)

• T_amb= ambient temperature (°C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (°C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 7.

Thermal characteristics

V_DD= 2.2 V to 3.6 V; T_amb= −40 °C to +85 °C unless otherwise specified;

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_j(max)

maximum junction

temperature

-

<tbd>

°C

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

52 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

10. Static characteristics

Table 8.

Static characteristics

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Supply pins

V_DD(IO)

I/O supply voltage

2.2

-

3.6

V

V_DD(REG)(3V3)

regulator supply voltage

(3.3 V)

V_DDA(3V3)

analog supply voltage

(3.3 V)

2.0

2.2

-

3.6

V

[2]

V_BAT

battery supply voltage

I_DD(REG)(3V3)

regulator supply current active mode; code

(3.3 V)

while(1){}

executed from <tbd>; all

peripherals disabled

[3]

CCLK = 12 MHz; PLL

disabled

-

<tbd>

-

mA

CCLK = 100 MHz; PLL

enabled

CCLK = 150 MHz; PLL

enabled

[3]

[3][4]

[3]

sleep mode

-

<tbd>

-

mA

μA

nA

deep sleep mode

power-down mode

deep power-down mode;

RTC not running

I_BAT

battery supply current

deep power-down mode;

RTC running

[5]

[6]

V_DD(REG)(3V3)present

-

<tbd>

-

nA

V_DD(REG)(3V3)not

present

<tbd>

-

nA

[7]

[8]

I_DD(IO)

I/O supply current

ADC supply current

deep sleep mode

-

power-down mode

deep power-down mode

deep sleep mode

I_DD(ADC)

power-down mode

deep power-down mode

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

53 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 8.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

Digital pins

I_IL

Parameter

Conditions

Min

Typ^[1]

Max

Unit

LOW-level input current V_I= 0 V; on-chip pull-up

resistor disabled

-

<tbd>

μA

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD(IO); on-chip

pull-down resistor

disabled

OFF-state output

current

V_O= 0 V; V_O= V_DD(IO)

on-chip pull-up/down

resistors disabled

;

-

<tbd>

μA

[9][10]

[11]

input voltage

pin configured to provide

a digital function

<tbd>

V

V_O

output voltage

output active

<tbd>

-

V_DD(IO)

-

V

V_IH

HIGH-level input

voltage

V_IL

LOW-level input voltage

hysteresis voltage

-

<tbd>

V

V_hys

V_OH

<tbd>

-

HIGH-level output

voltage

I_OH= −4 mA

V_DD(IO)

0.4

−

V_OL

I_OH

LOW-level output

voltage

I_OL= 4 mA

-

<tbd>

V

HIGH-level output

current

V_OH= V_DD(IO)− 0.4 V

V_OL= 0.4 V

<tbd>

-

mA

I_OL

LOW-level output

current

<tbd>

-

[12]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

-

<tbd>

LOW-level short-circuit V_OL= V_DD(IO)

output current

I_pd

I_pu

pull-down current

pull-up current

V_I= 3.6 V

<tbd>

μA

V_I= 0 V

V_DD(IO)< V_I< 3.6 V

Open-drain I²C0-bus pins

V_IH

HIGH-level input

<tbd>

-

V

voltage

V_IL

LOW-level input voltage

hysteresis voltage

-

<tbd>

-

V

V_hys

V_OL

<tbd>

-

LOW-level output

voltage

I_OLS= <tbd> mA

<tbd>

[13]

I_LI

input leakage current

V_I= V_DD(IO)

V_I= 5 V

-

<tbd>

μA

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

54 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 8.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Oscillator pins

V_i(XTAL1)

input voltage on pin

XTAL1

−0.5

-

1.2

V

V_o(XTAL2)

output voltage on pin

XTAL2

USB pins

V_IC

common-mode input

voltage

high-speed mode

<tbd>

-

<tbd>

mV

full-speed/low-speed

mode

chirp mode

<tbd>

-

<tbd>

mV

V_i(dif)

differential input voltage

<tbd>

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] The RTC typically fails when V_VBATdrops below 1.6 V.

[3] V_DD(REG)(3V3)= 3.3 V; T_amb= 25 °C for all power consumption measurements.

[4] Conditions <tbd>.

[5] On pin VBAT; I_DD(REG)(3V3)= <tbd> nA; V_DD(REG)(3V3)= 3.3 V; V_BAT< V_DD(REG)(3V3); T_amb= 25 °C.

[6] On pin VBAT; V_BAT= 3.3 V; T_amb= 25 °C.

[7] All internal pull-ups disabled. All pins configured as output and driven LOW. V_DD(3V3)= 3.3 V; T_amb= 25 °C.

[8] V_DDA(3V3)= 3.3 V; T_amb= 25 °C.

[9] Including voltage on outputs in 3-state mode.

[10] V_DD(3V3)supply voltages must be present.

[11] 3-state outputs go into 3-state mode in Deep power-down mode.

[12] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[13] To V_SS

.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

55 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

10.1 Electrical pin characteristics

001aab173

X

(X)

X

(X)

<tbd>

X

X (X)

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; standard

port pins.

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; standard

port pins.

Fig 6. Typical HIGH-level output voltage V_OHversus

HIGH-level output source current I_OH

Fig 7. Typical LOW-level output current I_OLversus

LOW-level output voltage V_OL

001aab173

X

(X)

X

<tbd>

X

X (X)

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; standard

port pins.

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; standard

port pins.

Fig 8. Typical pull-up current I_puversus input voltage

V_I

Fig 9. Typical pull-down current I_pdversus input

voltage V_I

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

56 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

10.2 Power consumption

001aab173

X

(X)

X

(X)

<tbd>

X

X (X)

Conditions: T_amb= 25 °C; V_{DD(REEG)(3V3)}= 3.3 V; <tbd>

Conditions: T_amb= 25 °C; V_{DD(REEG)(3V3)}= 3.3 V; <tbd>.

Fig 10. Typical supply current versus regulator supply

voltage V_{DD(REEG)(3V3)}in active mode

Fig 11. Typical supply current versus temperature in

active mode

001aab173

X

(X)

X

<tbd>

X

X (X)

Conditions: T_amb= 25 °C; <tbd>.

Conditions: T_amb= 25 °C; V; <tbd>.

Fig 12. Typical supply current versus temperature in

Sleep mode

Fig 13. Typical supply current versus temperature in

Deep-sleep mode

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

57 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

001aab173

X

(X)

X

(X)

X

<tbd>

X

X (X)

Conditions: T_amb= 25 °C; <tbd>.

Conditions: T_amb= 25 °C; V; <tbd>.

Fig 14. Typical supply current versus temperature in

Power-down mode

Fig 15. Typical supply current versus temperature in

Deep power-down mode

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

58 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 9.

Power consumption for individual peripherals

T_amb= 25 °C; V_DD

Peripheral

IRC

_(3V3)= 3.3 V.

(REEG)

[1]

Conditions

Typical I_DD

ADC

DAC

I2C0

I2C1

I2S

SSP0

SSP1

USART0

UART1

USART2

USART3

USB0

USB1

Ethernet

<tbd>

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

59 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

11. Dynamic characteristics

11.1 External clock

Table 10. Dynamic characteristic: external clock

_amb= −40 °C to +85 °C; V_DD(IO)over specified ranges.^[1]

T

Symbol Parameter

Conditions

Min

Typ^[2]

Max

25

Unit

MHz

ns

f_osc

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

1

-

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

-

T_cy(clk)× <tbd>

ns

T_cy(clk)× <tbd>

-

ns

-

<tbd>

ns

clock fall time

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 16. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

60 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

11.2 IRC and RTC oscillators

Table 11. Dynamic characteristic: IRC and RTC oscillators

T_amb= −40 °C to +85 °C; <tbd> ≤ V_DD(IO)≤ <tbd>.^[1]

Symbol Parameter

Conditions

Min

Typ^[2]

Max

Unit

f_osc(RC)internal RC oscillator

-

<tbd>

12.00

<tbd>

MHz

frequency

f_i(RTC)

RTC input frequency

-

32.768

-

kHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

001aab173

X

(X)

X

<tbd>

X

X (X)

Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for

2.7 V ≤ V_DD(IO)≤ 3.6 V and T_amb= −40 °C to +85 °C. Variations between parts may cause the IRC

to fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.

Fig 17. Internal RC oscillator frequency versus temperature

11.3 I²C-bus

Table 12. Dynamic characteristic: I²C-bus pins

_amb= −40 °C to +85 °C.^[1]

T

Symbol

f_SCL

Parameter

Conditions

Min

Max

100

400

1

Unit

kHz

MHz

ns

SCL clock frequency

Standard-mode

Fast-mode

0

-

Fast-mode Plus

[3][4][5][6]

t_f

fall time

of both SDA and

SCL signals

300

Standard-mode

Fast-mode

20 + 0.1 × C_b

300

120

ns

Fast-mode Plus

-

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

61 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 12. Dynamic characteristic: I²C-bus pins

T_amb= −40 °C to +85 °C.^[1]

Symbol

Parameter

Conditions

Min

4.7

1.3

0.5

4.0

0.6

0.26

0

Max

Unit

μs

ns

t_LOW

LOW period of the SCL clock

Standard-mode

Fast-mode

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

HIGH period of the SCL clock

data hold time

Fast-mode Plus

Standard-mode

Fast-mode

[2][3][7]

[8][9]

t_HD;DAT

0

Fast-mode Plus

Standard-mode

Fast-mode

0

t_SU;DAT

data set-up time

250

100

50

Fast-mode Plus

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[4] C_b= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[5] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[7] The maximum t_HD;DATcould be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t_VD;DATor

t

_VD;ACKby a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[9] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement t_SU;DAT= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

62 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

t

f

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 18. I²C-bus pins clock timing

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

63 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

11.4 SSP interface

Table 13. Dynamic characteristics: SSP pins in SPI mode

Symbol

T_cy(PCLK)

T_cy(clk)

SSP master

t_DS

Parameter

Conditions

Min

Max

Unit

ns

PCLK cycle time

clock cycle time

<tbd>

-

[1]

ns

[2]

data set-up time

in SPI mode

<tbd>

T_cy(clk)

<tbd>

ns

t_DH

data hold time

-

t_v(Q)

data output valid time

data output hold time

t_h(Q)

SSP slave

t_DS

[3][4]

data set-up time

data hold time

in SPI mode

<tbd>

-

ns

t_DH

<tbd> × T_cy(PCLK)+

<tbd>

[3][4]

t_v(Q)

t_h(Q)

data output valid time

data output hold time

in SPI mode

-

<tbd> × T_cy(PCLK)

<tbd>

+

ns

<tbd> × T_cy(PCLK)

<tbd>

[1] T_cy(clk)= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f_main. The clock cycle time derived from the SPI bit rate T_cy(clk)is a function of the

main clock frequency f_main, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).

[2]

[3] T_cy(clk)= 12 × T_cy(PCLK)

[4] T_amb= 25 °C; V_DD(REG)(3V3)= 3.3 V; V_DD(IO)= 3.3 V.

T_amb= −40 °C to 85 °C; V_DD(REG)(3V3)= 2.0 V to 3.6 V; V_DD(IO)= 2.0 V to 3.6 V.

.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

64 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

T

t

clk(L)

cy(clk)

clk(H)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

h(Q)

v(Q)

DATA VALID

CPHA = 1

t

DH

DS

DATA VALID

MISO

t

h(Q)

v(Q)

DATA VALID

t

MOSI

MISO

t

CPHA = 0

DS

DH

DATA VALID

002aae829

Fig 19. SSP master timing in SPI mode

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

65 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

T

t

clk(L)

cy(clk)

clk(H)

SCK (CPOL = 0)

SCK (CPOL = 1)

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

v(Q)

CPHA = 1

DATA VALID

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

CPHA = 0

v(Q)

DATA VALID

002aae830

Fig 20. SSP slave timing in SPI mode

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

66 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

11.5 USB interface

Table 14. Dynamic characteristics: USB pins (full-speed)

C_L= 50 pF; R_pu= 1.5 kΩ on D+ to V_DD(IO), unless otherwise specified.

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

t_r/ t_f

Min

Typ

Max

Unit

ns

t_r

<tbd>

-

<tbd>

t_f

ns

t_FRFM

differential rise and fall time

matching

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

<tbd>

-

<tbd>

V

t_FEOPT

t_FDEOP

see Figure 21

ns

source jitter for differential transition see Figure 21

to SE0 transition

t_JR1

receiver jitter to next transition

<tbd>

-

<tbd>

-

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

[1]

t_EOPR1

must reject as

EOP; see

Figure 21

t_EOPR2

EOP width at receiver

must accept as

EOP; see

<tbd>

-

ns

Figure 21

[1] Characterized but not implemented as production test. Guaranteed by design.

T

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × T

+ t

FDEOP

PERIOD

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 21. Differential data-to-EOP transition skew and EOP width

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

67 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

11.6 Dynamic external memory interface

Table 15. Dynamic characteristics: Dynamic external memory interface

C_L= 30 pF; T_amb= −40 °C to 85 °C; V_DD(REG)(3V3)and V_DD(IO)over specified ranges <tbd>; AHB clock = 1 MHz.

Symbol

Common

t_d(SV)

Parameter

Conditions

Min

Typ

Max

Unit

chip select valid delay time

chip select hold time

-

<tbd>

ns

t_h(S)

<tbd>

<tbd>

<tbd>

<tbd>

<tbd>

-

t_d(RASV)

t_h(RAS)

t_d(CASV)

t_h(CAS)

t_d(WV)

t_h(W)

row address strobe valid delay time

row address strobe hold time

column address strobe valid delay time

column address strobe hold time

write valid delay time

-

<tbd>

-

<tbd>

-

<tbd>

write hold time

-

t_d(GV)

output enable valid delay time

output enable hold time

-

<tbd>

t_h(G)

-

t_d(AV)

address valid delay time

address hold time

-

<tbd>

-

t_h(A)

Read cycle parameters

t_su(D)data input set-up time

t_h(D)data input hold time

Write cycle parameters

t_d(QV)data output valid delay time

t_h(Q)data output hold time

-

ns

-

<tbd>

-

ns

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

68 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

t

CSHOEH

CSLAV

CS

addr

data

t

h(D)

am

t

CSLOEL

t

OEHANV

OELAV

t

OELOEH

OE

t

CSHBLSH

t

BLSLAV

BLS

002aad955

Fig 22. Static external memory controller read access

CS

t

CSLAV

t

WELWEH

t

CSLWEL

t

BLSLBLSH

BLS/WE

addr

t

WEHANV

t

WELDV

CSLBLSL

t

BLSHANV

t

WEHDNV

t

CSLDV

t

BLSHDNV

data

OE

002aad956

Fig 23. Static external memory controller write access

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

71 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

12. ADC/DAC electrical characteristics

Table 17. ADC characteristics

V_DDA(3V3)over specified ranges; T_amb= −40 °C to +85 °C; ADC frequency 4.5 MHz; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

V_IA

C_ia

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

−

-

V_DDA(3V3)

<tbd>

pF

[1][2][3]

[1][4]

[1][5]

[1][6]

[1][7]

E_D

LSB

%

E_L(adj)

E_O

E_G

gain error

E_T

absolute error

LSB

kΩ

R_vsi

voltage source interface

resistance

[8][9]

R_i

input resistance

-

<tbd>

MΩ

f_clk(ADC)

f_c(ADC)

ADC clock frequency

ADC conversion frequency

MHz

kSamples/s

[1] Conditions: V_SSA= 0 V, V_DDA(3V3)= 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 24.

[4] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 24.

[5] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 24.

[6] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 24.

[7] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 24.

[8] T_amb= 25 °C; maximum sampling frequency f_s= 4.5 MHz and analog input capacitance C_ia= 1 pF.

[9] Input resistance R_idepends on the sampling frequency fs: R_i= 1 / (f_s× C_ia).

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

72 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

offset

error

gain

error

E

G

O

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

offset error

E

O

V

− V

DDA(3V3) SSA

1024

1 LSB =

002aaf959

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 24. 10-bit ADC characteristics

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

73 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 18. DAC electrical characteristics

V_DDA(3V3)over specified ranges; T_amb= −40 °C to +85 °C; unless otherwise specified

Symbol

E_D

Parameter

Conditions

Min

Typ

Max

Unit

LSB

%

differential linearity error

integral non-linearity

offset error

-

<tbd>

-

E_L(adj)

E_O

-

E_G

gain error

-

%

C_L

load capacitance

load resistance

-

pF

R_L

<tbd>

kΩ

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

74 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

13. Application information

13.1 LCD panel signal usage

Table 19. LCD panel connections for STN single panel mode

External pin

4-bit mono STN single panel

8-bit mono STN single panel

Color STN single panel

LPC18xx pin

used

LCD function LPC18xx pin

LCD function

LPC18xx pin

used

LCD function

used

LCDVD[23:8]

LCDVD7

LCDVD6

LCDVD5

LCDVD4

LCDVD3

LCDVD2

LCDVD1

LCDVD0

LCDLP

-

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

P4_4

P4_1

P7_6

P4_6

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

UD[2]

UD[1]

UD[0]

LCDLP

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

P4_4

P4_1

P7_6

P4_6

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

UD[2]

UD[1]

UD[0]

LCDLP

-

P4_2

P4_3

P4_4

P4_1

P7_6

P4_6

UD[3]

UD[2]

UD[1]

UD[0]

LCDLP

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDPWR

GP_CLKIN

CDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

Table 20. LCD panel connections for STN dual panel mode

External pin

4-bit mono STN dual panel

8-bit mono STN dual panel

Color STN dual panel

LPC18xx pin

used

LCD function LPC18xx pin

LCD function

LPC18xx pin

used

LCD function

used

LCDVD[23:16]

LCDVD15

LCDVD14

LCDVD13

LCDVD12

LCDVD11

LCDVD10

LCDVD9

-

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

P4_8

P7_5

LD[7]

LD[6]

LD[5]

LD[4]

LD[3]

LD[2]

LD[1]

LD[0]

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

P4_8

P7_5

P8_4

P8_5

P8_6

P8_7

P4_2

LD[7]

LD[6]

LD[5]

LD[4]

LD[3]

LD[2]

LD[1]

LD[0]

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

-

P4_9

LD[3]

P4_10

LD[2]

P4_8

LD[1]

LCDVD8

P7_5

LD[0]

LCDVD7

-

LCDVD6

-

P8_5

P8_6

P8_7

P4_2

LCDVD5

-

LCDVD4

-

LCDVD3

P4_2

UD[3]

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

75 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 20. LCD panel connections for STN dual panel mode

External pin

4-bit mono STN dual panel

8-bit mono STN dual panel

Color STN dual panel

LPC18xx pin

used

LCD function LPC18xx pin LCD function

LPC18xx pin

used

LCD function

used

P4_3

P4_4

P4_1

P7_6

P4_6

LCDVD2

LCDVD1

LCDVD0

LCDLP

P4_3

P4_4

P4_1

P7_6

P4_6

UD[2]

UD[1]

UD[0]

LCDLP

UD[2]

UD[1]

UD[0]

LCDLP

P4_3

P4_4

P4_1

P7_6

P4_6

UD[2]

UD[1]

UD[0]

LCDLP

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDPWR

GP_CLKIN

LCDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

Table 21. LCD panel connections for TFT panels

External

TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode)

TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC18xx

pin used

LCD

function

LPC18xx

pin used

LCD

function

LPC18xxpin LCD

LPC18xx

pin used

LCD

function

used

PB_0

PB_1

PB_2

PB_3

P7_1

P7_2

-

function

LCDVD23 PB_0

LCDVD22 PB_1

LCDVD21 PB_2

LCDVD20 PB_3

BLUE3

PB_0

PB_1

PB_2

PB_3

P7_1

-

BLUE4

BLUE3

BLUE2

BLUE1

BLUE0

-

BLUE4

BLUE3

BLUE2

BLUE1

BLUE0

intensity

-

BLUE7

BLUE6

BLUE5

BLUE4

BLUE3

BLUE2

BLUE1

BLUE0

GREEN7

GREEN6

GREEN5

GREEN4

GREEN3

GREEN2

GREEN1

GREEN0

RED7

BLUE2

BLUE1

BLUE0

LCDVD19

LCDVD18

LCDVD17

LCDVD16

-

P7_3

P7_4

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

P4_8

P7_5

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

P4_4

-

LCDVD15 PB_4

LCDVD14 PB_5

LCDVD13 PB_6

LCDVD12 P8_3

GREEN3

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

-

GREEN5

GREEN4

GREEN3

GREEN2

GREEN1

GREEN0

-

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

-

GREEN4

GREEN3

GREEN2

GREEN1

GREEN0

intensity

-

GREEN2

GREEN1

GREEN0

LCDVD11

LCDVD10

LCDVD9

LCDVD8

LCDVD7

LCDVD6

LCDVD5

LCDVD4

LCDVD3

LCDVD2

LCDVD1

-

P8_4

RED3

P8_4

P8_5

P8_6

P8_7

P4_2

-

RED4

RED3

RED2

RED1

RED0

-

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

-

RED4

RED3

RED2

RED1

RED0

intensity

-

P8_5

RED2

RED6

P8_6

RED1

RED5

P8_7

RED0

RED4

-

RED3

RED2

-

RED1

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

76 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 21. LCD panel connections for TFT panels

External

TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode)

TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC18xx

pin used

LCD

function

LPC18xx

pin used

LCD

function

LPC18xxpin LCD

LPC18xx

pin used

LCD

function

used

function

LCDVD0

LCDLP

-

P4_1

P7_6

RED0

P7_6

LCDLP

P7_6

LCDLP

P7_6

LCDLP

LCDENAB/ P4_6

LCDM

LCDENAB/ P4_6

LCDM

LCDENAB/ P4_6

LCDM

LCDENAB/ P4_6

LCDM

LCDENAB/

LCDM

LCDFP

LCDDCLK P4_7

LCDLE P7_0

P4_5

LCDFP

LCDDCLK P4_7

LCDLE P7_0

P4_5

LCDFP

P4_5

P4_7

P7_0

P7_7

LCDFP

LCDDCLK P4_7

LCDLE P7_0

P4_5

LCDFP

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDPWR P7_7

GP_CLKIN PF_4

LCDPWR P7_7

LCDCLKIN PF_4

LCDPWR

LCDPWR P7_7

LCDCLKIN PF_4

LCDPWR

LCDCLKIN

LCDCLKIN PF_4

13.2 XTAL1 input

The input voltage to the on-chip oscillators is limited to 1.2 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave

mode, a minimum of 200 mV (RMS) is needed. For more details see <tbd>.

LPC1xxx

XTAL1

C

i

C

g

100 pF

002aae835

Fig 25. Slave mode operation of the on-chip oscillator

13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1, C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_x1and C_x2should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

77 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

14. Package outline

LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm

SOT740-2

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

C

e

1

y

1 C

y

∅ v M

∅ w M

b

C

A

B

e

1/2 e

T

R

N

L

P

M

K

H

F

e

J

e

2

G

E

C

A

1/2 e

D

B

ball A1

index area

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

X

5

scale

10 mm

0

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.45

0.35

1.1

0.9

0.55 17.2 17.2

0.45 16.8 16.8

mm

1.55

1

15

0.25

0.1

0.12 0.35

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

05-06-16

05-08-04

SOT740-2

MO-192

- - -

Fig 26. Package outline LBGA256 package sot740_2

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

78 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

15. Abbreviations

Table 22. Abbreviations

Acronym

ADC

Description

Analog-to-Digital Converter

Advanced Encryption Standard

Advanced High-performance Bus

Advanced Peripheral Bus

Application Programming Interface

BrownOut Detection

AES

AHB

APB

API

BOD

CAN

Controller Area Network

CMAC

CSMA/CD

DAC

Cipher-based Message Authentication Code

Carrier Sense Multiple Access with Collision Detection

Digital-to-Analog Converter

Direct Memory Access

DMA

ETB

Embedded Trace Buffer

ETM

GPIO

IRC

Embedded Trace Macrocell

General Purpose Input/Output

Internal RC

IrDA

Infrared Data Association

JTAG

LCD

Joint Test Action Group

Liquid Crystal Display

LSB

Least Significant Bit

MAC

MCU

MIIM

n.c.

Media Access Control

MicroController Unit

Media Independent Interface Management

not connected

OTG

PHY

On-The-Go

PHYsical layer

PLL

Phase-Locked Loop

PWM

RMII

Pulse Width Modulator

Reduced Media Independent Interface

Synchronous Dynamic Random Access Memory

Serial Peripheral Interface

SDRAM

SPI

SSI

Serial Synchronous Interface

Synchronous Serial Port

SSP

TCP/IP

UART

ULPI

USART

USB

Transmission Control Protocol/Internet Protocol

Universal Asynchronous Receiver/Transmitter

UTMI+ Low Pin Interface

Universal Synchronous Asynchronous Receiver/Transmitter

Universal Serial Bus

UTMI

USB 2.0 Transceiver Macrocell Interface

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

79 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

16. Revision history

Table 23. Revision history

Document ID

Release date Data sheet status

20110103 Objective data sheet

Change notice Supersedes

LPC1850_30_20_10 v.1

-

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

80 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

17.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

81 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

82 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

19. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.13

7.13.1

Digital serial peripherals. . . . . . . . . . . . . . . . . 42

UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.13.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.13.2 USART0/2/3. . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.13.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.13.3 SSP0/1 serial I/O controllers . . . . . . . . . . . . . 43

7.13.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.13.4

I²C0/1-bus interfaces . . . . . . . . . . . . . . . . . . . 43

7.13.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.13.5

I²S interface . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.13.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.13.6 C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.13.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

7.2

7.3

Functional description . . . . . . . . . . . . . . . . . . 30

Architectural overview . . . . . . . . . . . . . . . . . . 30

ARM Cortex-M3 processor . . . . . . . . . . . . . . . 30

AHB multilayer matrix. . . . . . . . . . . . . . . . . . . 31

Nested Vectored Interrupt Controller (NVIC) . 31

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 32

Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 32

System Tick timer (SysTick) . . . . . . . . . . . . . . 32

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 32

Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Memory mapping . . . . . . . . . . . . . . . . . . . . . . 34

Security features. . . . . . . . . . . . . . . . . . . . . . . 36

AES decryption engine. . . . . . . . . . . . . . . . . . 36

7.14

7.14.1

Counter/timers and motor control . . . . . . . . . 45

General purpose 32-bit timers/external

event counters . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4

7.4.1

7.4.2

7.5

7.6

7.7

7.8

7.9

7.10

7.10.1

7.14.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.14.2

7.14.3

7.14.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.14.4 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 46

7.14.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.14.5 Windowed WatchDog Timer (WWDT) . . . . . . 47

7.14.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Motor control PWM . . . . . . . . . . . . . . . . . . . . 46

Quadrature Encoder Interface (QEI) . . . . . . . 46

7.15

7.15.1

Analog peripherals. . . . . . . . . . . . . . . . . . . . . 47

Analog-to-Digital Converter (ADC0/1) . . . . . . 47

7.10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.10.2

7.11

7.11.1

7.12

7.12.1

7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.12.2 General Purpose DMA (GPDMA). . . . . . . . . . 37

7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.12.3 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 38

7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

One-Time Programmable (OTP) memory . . . 36

General Purpose I/O (GPIO) . . . . . . . . . . . . . 36

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 37

State Configurable Timer (SCT) subsystem . . 37

7.15.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.15.2 Digital-to-Analog Converter (DAC). . . . . . . . . 47

7.15.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.16

7.16.1

7.16.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.16.2

7.17

7.17.1

7.17.2

7.17.3

7.17.4

7.17.5

7.17.6

7.17.7

7.17.8

7.18

Peripherals in the RTC power domain. . . . . . 48

RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 48

System control . . . . . . . . . . . . . . . . . . . . . . . . 48

Configuration registers (CREG). . . . . . . . . . . 48

System Control Unit (SCU) . . . . . . . . . . . . . . 49

Clock Generation Unit (CGU) . . . . . . . . . . . . 49

Internal RC oscillator (IRC) . . . . . . . . . . . . . . 49

PLL0 (for USB0). . . . . . . . . . . . . . . . . . . . . . . 49

System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 49

Reset Generation Unit (RGU) . . . . . . . . . . . . 49

Power control. . . . . . . . . . . . . . . . . . . . . . . . . 50

Emulation and debugging . . . . . . . . . . . . . . . 50

7.12.4

7.12.5

SD/MMC card interface . . . . . . . . . . . . . . . . . 39

External Memory Controller (EMC). . . . . . . . . 39

7.12.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.12.6

High-speed USB Host/Device/OTG interface

(USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.12.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.12.7

High-speed USB Host/Device interface with

ULPI (USB1). . . . . . . . . . . . . . . . . . . . . . . . . . 40

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 51

Thermal characteristics . . . . . . . . . . . . . . . . . 52

Static characteristics . . . . . . . . . . . . . . . . . . . 53

Electrical pin characteristics. . . . . . . . . . . . . . 56

7.12.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.12.8 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 41

7.12.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.12.9 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.12.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9

10

10.1

continued >>

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

83 of 84

LPC1850/30/20/10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

10.2

Power consumption . . . . . . . . . . . . . . . . . . . . 57

11

Dynamic characteristics . . . . . . . . . . . . . . . . . 60

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 60

IRC and RTC oscillators . . . . . . . . . . . . . . . . . 61

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 64

USB interface . . . . . . . . . . . . . . . . . . . . . . . . 67

Dynamic external memory interface. . . . . . . . 68

Static external memory interface . . . . . . . . . . 69

11.1

11.2

11.3

11.4

11.5

11.6

11.7

12

ADC/DAC electrical characteristics . . . . . . . . 72

13

Application information. . . . . . . . . . . . . . . . . . 75

LCD panel signal usage . . . . . . . . . . . . . . . . . 75

XTAL1 input . . . . . . . . . . . . . . . . . . . . . . . . . . 77

XTAL and RTCX Printed Circuit Board (PCB)

layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 77

13.1

13.2

13.3

14

15

16

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 79

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 80

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 81

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 81

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 82

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 82

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 January 2011

Document identifier: LPC1850_30_20_10


型号：	LPC1850FET256
厂家：	NXP
描述：	32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD 32位ARM Cortex-M3的MCU ;高达200 KB的SRAM ;以太网，两个高速USB ， LCD 静态存储器 CD 以太网
文件：	总84页 (文件大小：533K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC1850FET256 [NXP]

相关型号：

LPC1850FET256,551

LPC1850_1109

LPC1850_1112

LPC1850_13

LPC1853

LPC1853FET256

LPC1853FET256,551

LPC1853JBD208

LPC1853JBD208E

LPC1853JET256

LPC1853JET256,551

LPC1857