LPC18S37JET100_技术文档

LPC18S5x/S3x

32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB

SRAM; Ethernet, two High-speed USB, LCD, EMC, AES engine

Rev. 1.3 — 10 January 2020

Product data sheet

1. General description

The LPC18S5x/S3x are ARM Cortex-M3 based microcontrollers for embedded

applications. The ARM Cortex-M3 is a next generation core that offers system

enhancements such as low power consumption, enhanced debug features, and a high

level of support block integration.

The LPC18S5x/S3x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3

CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local

instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3

CPU also includes an internal prefetch unit that supports speculative branching.

The LPC18S5x/S3x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of

EEPROM memory, a quad SPI Flash Interface (SPIFI), a State-configurable Timer/PWM

(SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external

memory controller, and multiple digital and analog peripherals.

For additional documentation related to the LPC18xx parts, see Section 17 “References”.

2. Features and benefits

 Processor core

 ARM Cortex-M3 processor (version r2p1), running at CPU frequencies of up to

180 MHz.

 ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 On-chip memory

 Up to 1 MB on-chip dual bank flash memory with flash accelerator.

 16 kB on-chip EEPROM data memory.

 136 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access.

 64 kB ROM containing boot code and on-chip software drivers.

 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose

use.

 AES engine for encryption and decryption of the boot image and data with DMA

support and programmable via a ROM-based API.

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

 Clock generation unit

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and

voltage (1.5 % accuracy for T_amb= 0 °C to 85 °C).

 Ultra-low power RTC crystal oscillator.

 Three PLLs allow CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. The second PLL can be used with the High-speed USB,

the third PLL can be used as audio PLL.

 Clock output.

 Configurable digital peripherals:

 State Configurable Timer/PWM (SCTimer/PWM) subsystem on AHB.

 Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1.

 Serial interfaces:

 Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.

 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

 One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY (USB0).

 One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to an external high-speed PHY (USB1).

 USB interface electrical test software included in ROM USB stack.

 Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support UART synchronous mode and a

smart card interface conforming to ISO7816 specification.

 Up to two C_CAN 2.0B controllers with one channel each.

 Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

 One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I²C-bus specification. Supports data rates of up to

1 Mbit/s.

 One standard I²C-bus interface with monitor mode and standard I/O pins.

 Two I²S interfaces with DMA support, each with one input and one output.

 Digital peripherals:

 External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,

and SDRAM devices.

 LCD controller with DMA support and a programmable display resolution of up to

1024H  768V. Supports monochrome and color STN panels and TFT color panels;

supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel

mapping.

 SD/MMC card interface.

 Eight-channel General-Purpose DMA controller can access all memories on the

AHB and all DMA-capable AHB slaves.

 Up to 164 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors.

LPC18S5X_S3X

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Product data sheet

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32-bit ARM Cortex-M3 microcontroller

 GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

 Up to eight GPIO pins can be selected from all GPIO pins as edge and level

sensitive interrupt sources.

 Two GPIO group interrupt modules enable an interrupt based on a programmable

pattern of input states of a group of GPIO pins.

 Four general-purpose timer/counters with capture and match capabilities.

 One motor control PWM for three-phase motor control.

 One Quadrature Encoder Interface (QEI).

 Repetitive Interrupt timer (RI timer).

 Windowed watchdog timer.

 Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes

of battery powered backup registers.

 Event recorder with three inputs to record event identification and event time; can

be battery powered.

 Alarm timer; can be battery powered.

 Analog peripherals:

 One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

 Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.

Up to eight analog channels total. Each analog input is connected to both ADCs.

 Unique ID for each device.

 Power:

 Single 3.3 V (2.4 V to 3.6 V) power supply with on-chip internal voltage regulator for

the core supply and the RTC power domain.

 RTC power domain can be powered separately by a 3 V battery supply.

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

 Processor wake-up from Sleep mode via wake-up interrupts from various

peripherals.

 Wake-up from Deep-sleep, Power-down, and Deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the RTC

power domain.

 Brownout detect with four separate thresholds for interrupt and forced reset.

 Power-On Reset (POR).

 Available in LQFP208, LBGA256, LQFP144, and TFBGA100 packages.

3. Applications

 Industrial

 RFID readers

 e-Metering

 Consumer

 White goods

LPC18S5X_S3X

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Product data sheet

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3 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC18S57JET256 LBGA256

LPC18S57JBD208 LQFP208

LPC18S37JBD144 LQFP144

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT740-2

SOT459-1

SOT486-1

LPC18S37JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC18S5X_S3X

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Product data sheet

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

4.1 Ordering options

Table 2.

Ordering options

LPC18S57JET256

LPC18S57JBD208

LPC18S37JBD144

LPC18S37JET100

1 MB 512 kB

512 kB

136 kB yes yes yes yes/yes

yes yes

yes no

8

4

J

164

142

83

136 kB no

yes yes yes/yes

yes yes yes/no

no

49

[1] J = -40 °C to +105 °C; F = -40 °C to +85 °C.

LPC18S5X_S3X

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Product data sheet

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LPC18S5x/S3x

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32-bit ARM Cortex-M3 microcontroller

5. Block diagram

SWD/TRACE PORT/JTAG

LPC18S5x/S3x

64 kB ROM

HIGH-SPEED PHY

32 kB LOCAL SRAM

40 kB LOCAL SRAM

TEST/DEBUG

INTERFACE

ETM

HIGH-

(1)

ETHERNET

10/100

32 kB AHB SRAM

SPEED

(1)

USB1

DMA

(1)

USB0

(1)

16 kB +

16 kB AHB SRAM

MAC

LCD

SD/

MMC

HOST/

DEVICE

ARM

CORTEX-M3

HOST/

DEVICE/

OTG

IEEE 1588

16 kB EEPROM

512/256 kB FLASH A

masters

512/256 kB FLASH B

slaves

AHB MULTILAYER MATRIX

SPIFI

slaves

BRIDGE

BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

EMC

HS GPIO

SCT

2

MOTOR

RI TIMER

I C1

CGU

CCU1

CCU2

RGU

WWDT

ALARM TIMER

CONTROL

(1)

USART0

10-bit DAC

C_CAN0

BACKUP REGISTERS

POWER MODE CONTROL

PWM

USART2

USART3

TIMER2

TIMER3

SSP1

AES ENCRYPTION/

DECRYPTION

2

I C0

UART1

SSP0

2

I S0

10-bit ADC0

10-bit ADC1

CONFIGURATION

REGISTERS

2

I S1

TIMER0

EVENT ROUTER

OTP MEMORY

C_CAN1

TIMER1

SCU

(1)

QEI

RTC

RTC OSC

12 MHz IRC

GIMA

GPIO PIN

INTERRUPTS

GPIO GROUP0

INTERRUPT

EVENT MONITOR

RTC POWER DOMAIN

GPIO GROUP1

INTERRUPT

= connected to DMA

aaa-015601

(1) Not available on all parts. See Table 2.

Fig 1. LPC18S5x/S3x block diagram

LPC18S5X_S3X

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LPC18S5x/S3x

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32-bit ARM Cortex-M3 microcontroller

6. Pinning information

6.1 Pinning

LPC18S57JET256

ball A1

index area

ball A1

index area

LPC18S37JET100

2

4

6

8

10 12 14 16

11 13 15

1

3

5

7

9

1

2

3

4

5

6

7

8

9 10

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

A

B

C

D

E

F

G

H

J

K

aaa-016765

aaa-016766

Transparent top view

Fig 2. Pin configuration LBGA256 package

Fig 3. Pin configuration TFBGA100 package

157

208

104

109

144

72

LPC18S57JBD208

LPC18S37JBD144

37

53

aaa-016767

aaa-016768

Fig 4. Pin configuration LQFP208 package

Fig 5. Pin configuration LQFP144 package

6.2 Pin description

On the LPC18S5x/S3x, digital pins are grouped into 16 ports, named P0 to P9 and PA to

PF, with up to 20 pins used per port. Each digital pin can support up to eight different

digital functions, including General-Purpose I/O (GPIO), selectable through the SCU

registers.

The pin name is not indicative of the GPIO port assigned to it.

The parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of ADC0 and

ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel

0 inputs (named ADC0_0 and ADC1_0) are tied together and connected to both, channel

LPC18S5X_S3X

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LPC18S5x/S3x

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32-bit ARM Cortex-M3 microcontroller

0 on ADC0 and channel 0 on ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are

tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are

eight ADC channels total for the two ADCs.

Table 3.

Pin description

Pin name

Description

Multiplexed digital pins

[2]

P0_0

L3

G2

32

47

N;

PU

I/O GPIO0[0] — General purpose digital input/output pin.

I/O SSP1_MISO — Master In Slave Out for SSP1.

I

ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

R — Function reserved.

-

R — Function reserved.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

I/O I2S1_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

[2]

P0_1

M2

G1

34

50

N;

PU

I/O GPIO0[1] — General purpose digital input/output pin.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

I

ENET_COL — Ethernet Collision detect (MII interface).

R — Function reserved.

-

R — Function reserved.

ENET_TX_EN — Ethernet transmit enable (RMII/MII

interface).

I/O I2S1_TX_SDA — I²S1 transmit data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

[2]

P1_0

P2

H1

38

54

N;

I/O GPIO0[4] — General purpose digital input/output pin.

PU

I

CTIN_3 — SCTimer/PWM input 3. Capture input 1 of timer 1.

I/O EMC_A5 — External memory address line 5.

-

R — Function reserved.

I/O SSP0_SSEL — Slave Select for SSP0.

R — Function reserved.

I/O EMC_D12 — External memory data line 12.

-

LPC18S5X_S3X

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Table 3.

Pin description …continued

Pin name

Description

[2]

P1_1

R2

K2

42

58

N;

I/O GPIO0[8] — General purpose digital input/output pin. External

PU

boot pin (see Table 5).

O

CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer

1.

I/O EMC_A6 — External memory address line 6.

-

R — Function reserved.

I/O SSP0_MISO — Master In Slave Out for SSP0.

R — Function reserved.

-

I/O EMC_D13 — External memory data line 13.

[2]

P1_2

R3

K1

43

60

N;

I/O GPIO0[9] — General purpose digital input/output pin. External

PU

boot pin (see Table 5).

O

CTOUT_6 — SCTimer/PWM output 6. Match output 2 of timer

1.

I/O EMC_A7 — External memory address line 7.

-

R — Function reserved.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

R — Function reserved.

-

I/O EMC_D14 — External memory data line 14.

[2]

P1_3

P5

J1

44

61

N;

I/O GPIO0[10] — General purpose digital input/output pin.

PU

O

CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer

2.

-

R — Function reserved.

O

EMC_OE — LOW active Output Enable signal.

USB0_IND1 — USB0 port indicator LED control output 1.

I/O SSP1_MISO — Master In Slave Out for SSP1.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

[2]

P1_4

T3

J2

47

64

N;

I/O GPIO0[11] — General purpose digital input/output pin.

PU

O

CTOUT_9 — SCTimer/PWM output 9. Match output 3 of timer

3.

-

R — Function reserved.

O

EMC_BLS0 — LOW active Byte Lane select signal 0.

USB0_IND0 — USB0 port indicator LED control output 0.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

I/O EMC_D15 — External memory data line 15.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

LPC18S5X_S3X

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P1_5

R5

J4

48

65

N;

I/O GPIO1[8] — General purpose digital input/output pin.

PU

O

CTOUT_10 — SCTimer/PWM output 10. Match output 3 of

timer 3.

-

R — Function reserved.

O

I

EMC_CS0 — LOW active Chip Select 0 signal.

USB0_PWR_FAULT — Port power fault signal indicating

overcurrent condition; this signal monitors over-current on the

USB bus (external circuitry required to detect over-current

condition).

I/O SSP1_SSEL — Slave Select for SSP1.

-

R — Function reserved.

O

SD_POW — SD/MMC card power monitor output.

[2]

P1_6

T4

K4

49

67

N;

I/O GPIO1[9] — General purpose digital input/output pin.

PU

I

CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.

R — Function reserved.

-

O

-

EMC_WE — LOW active Write Enable signal.

R — Function reserved.

O

-

EMC_BLS0 — LOW active Byte Lane select signal 0.

R — Function reserved.

I/O SD_CMD — SD/MMC command signal.

[2]

P1_7

T5

G4

50

69

N;

I/O GPIO1[0] — General purpose digital input/output pin.

PU

I

U1_DSR — Data Set Ready input for UART1.

O

CTOUT_13 — SCTimer/PWM output 13. Match output 3 of

timer 3.

I/O EMC_D0 — External memory data line 0.

O

USB0_PPWR — VBUS drive signal (towards external charge

pump or power management unit); indicates that VBUS must

be driven (active HIGH). Add a pull-down resistor to disable the

power switch at reset. This signal has opposite polarity

compared to the USB_PPWR used on other NXP LPC parts.

-

R — Function reserved.

LPC18S5X_S3X

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Table 3.

Pin description …continued

Pin name

Description

[2]

P1_8

R7

T7

R8

T9

H5

51

52

53

55

71

73

75

77

N;

PU

I/O GPIO1[1] — General purpose digital input/output pin.

O

U1_DTR — Data Terminal Ready output for UART1.

CTOUT_12 — SCTimer/PWM output 12. Match output 3 of

timer 3.

I/O EMC_D1 — External memory data line 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT0 — SD/MMC bus voltage select output 0.

P1_9

J5

N;

PU

I/O GPIO1[2] — General purpose digital input/output pin.

O

U1_RTS — Request to Send output for UART1.

CTOUT_11 — SCTimer/PWM output 11. Match output 3 of

timer 2.

I/O EMC_D2 — External memory data line 2.

-

R — Function reserved.

I/O SD_DAT0 — SD/MMC data bus line 0.

P1_10

H6

N;

PU

I/O GPIO1[3] — General purpose digital input/output pin.

I

U1_RI — Ring Indicator input for UART1.

O

CTOUT_14 — SCTimer/PWM output 14. Match output 2 of

timer 3.

I/O EMC_D3 — External memory data line 3.

-

R — Function reserved.

I/O SD_DAT1 — SD/MMC data bus line 1.

P1_11

J7

N;

I/O GPIO1[4] — General purpose digital input/output pin.

PU

I

U1_CTS — Clear to Send input for UART1.

O

CTOUT_15 — SCTimer/PWM output 15. Match output 3 of

timer 3.

I/O EMC_D4 — External memory data line 4.

-

R — Function reserved.

I/O SD_DAT2 — SD/MMC data bus line 2.

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Table 3.

Pin description …continued

Pin name

Description

[2]

P1_12

P1_13

P1_14

P1_15

R9

K7

56

60

61

62

78

83

85

87

N;

PU

I/O GPIO1[5] — General purpose digital input/output pin.

I

U1_DCD — Data Carrier Detect input for UART1.

R — Function reserved.

-

I/O EMC_D5 — External memory data line 5.

I

T0_CAP1 — Capture input 1 of timer 0.

R — Function reserved.

-

R — Function reserved.

I/O SD_DAT3 — SD/MMC data bus line 3.

R10 H8

R11 J8

T12 K8

N;

PU

I/O GPIO1[6] — General purpose digital input/output pin.

O

-

U1_TXD — Transmitter output for UART1.

R — Function reserved.

I/O EMC_D6 — External memory data line 6.

I

-

I

T0_CAP0 — Capture input 0 of timer 0.

R — Function reserved.

SD_CD — SD/MMC card detect input.

N;

PU

I/O GPIO1[7] — General purpose digital input/output pin.

I

U1_RXD — Receiver input for UART1.

R — Function reserved.

-

I/O EMC_D7 — External memory data line 7.

O

-

T0_MAT2 — Match output 2 of timer 0.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

N;

I/O GPIO0[2] — General purpose digital input/output pin.

PU

O

-

U2_TXD — Transmitter output for USART2.

R — Function reserved.

I

ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

T0_MAT1 — Match output 1 of timer 0.

R — Function reserved.

O

-

I/O EMC_D8 — External memory data line 8.

R — Function reserved.

-

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Table 3.

Pin description …continued

Pin name

Description

[2]

[3]

[2]

P1_16

P1_17

P1_18

P1_19

M7

H9

64

90

93

95

96

N;

PU

I/O GPIO0[3] — General purpose digital input/output pin.

I

U2_RXD — Receiver input for USART2.

R — Function reserved.

-

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

T0_MAT0 — Match output 0 of timer 0.

R — Function reserved.

O

-

I/O EMC_D9 — External memory data line 9.

I

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII

interface).

M8

H10 66

N;

PU

I/O GPIO0[12] — General purpose digital input/output pin.

I/O U2_UCLK — Serial clock input/output for USART2 in

synchronous mode.

-

R — Function reserved.

I/O ENET_MDIO — Ethernet MIIM data input and output.

I

T0_CAP3 — Capture input 3 of timer 0.

CAN1_TD — CAN1 transmitter output.

R — Function reserved.

O

-

R — Function reserved.

N12 J10 67

N;

PU

I/O GPIO0[13] — General purpose digital input/output pin.

I/O U2_DIR — RS-485/EIA-485 output enable/direction control for

USART2.

-

R — Function reserved.

O

I

ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

T0_MAT3 — Match output 3 of timer 0.

CAN1_RD — CAN1 receiver input.

R — Function reserved.

-

I/O EMC_D10 — External memory data line 10.

M11 K9

68

N;

PU

I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit

Clock (MII interface) or Ethernet Reference Clock (RMII

interface).

I/O SSP1_SCK — Serial clock for SSP1.

-

R — Function reserved.

-

R — Function reserved.

O

-

CLKOUT — Clock output pin.

R — Function reserved.

O

I2S0_RX_MCLK — I²S receive master clock.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P1_20

M10 K10 70

100

N;

PU

I/O GPIO0[15] — General purpose digital input/output pin.

I/O SSP1_SSEL — Slave Select for SSP1.

-

R — Function reserved.

O

I

ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

T0_CAP2 — Capture input 2 of timer 0.

R — Function reserved.

-

R — Function reserved.

I/O EMC_D11 — External memory data line 11.

[2]

P2_0

T16 G10 75

108

N;

-

R — Function reserved.

PU

O

U0_TXD — Transmitter output for USART0. See Table 4 for

ISP mode.

I/O EMC_A13 — External memory address line 13.

O

USB0_PPWR — VBUS drive signal (towards external charge

pump or power management unit); indicates that VBUS must

be driven (active HIGH). Add a pull-down resistor to disable the

power switch at reset. This signal has opposite polarity

compared to the USB_PPWR used on other NXP LPC parts.

I/O GPIO5[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

ENET_MDC — Ethernet MIIM clock.

R — Function reserved.

O

-

[2]

P2_1

N15 G7

81

116

N;

PU

I

U0_RXD — Receiver input for USART0. See Table 4 for ISP

mode.

I/O EMC_A12 — External memory address line 12.

I

USB0_PWR_FAULT — Port power fault signal indicating

overcurrent condition; this signal monitors over-current on the

USB bus (external circuitry required to detect over-current

condition).

I/O GPIO5[1] — General purpose digital input/output pin.

-

I

R — Function reserved.

T3_CAP1 — Capture input 1 of timer 3.

R — Function reserved.

-

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P2_2

M15 F5

84

121

N;

-

R — Function reserved.

PU

I/O U0_UCLK — Serial clock input/output for USART0 in

synchronous mode.

I/O EMC_A11 — External memory address line 11.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O GPIO5[2] — General purpose digital input/output pin.

I

CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.

T3_CAP2 — Capture input 2 of timer 3.

EMC_CS1 — LOW active Chip Select 1 signal.

R — Function reserved.

I

O

-

[3]

P2_3

J12 D8

87

127

N;

PU

I/O I2C1_SDA — I²C1 data input/output (this pin does not use a

specialized I²C pad).

O

I

U3_TXD — Transmitter output for USART3. See Table 4 for

ISP mode.

CTIN_1 — SCTimer/PWM input 1. Capture input 1 of timer 0.

Capture input 1 of timer 2.

I/O GPIO5[3] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

USB0_PPWR — VBUS drive signal (towards external charge

pump or power management unit); indicates that VBUS must

be driven (active HIGH). Add a pull-down resistor to disable the

power switch at reset. This signal has opposite polarity

compared to the USB_PPWR used on other NXP LPC parts.

[3]

P2_4

K11 D9

88

128

N;

-

R — Function reserved.

PU

I/O I2C1_SCL — I²C1 clock input/output (this pin does not use a

specialized I²C pad).

I

U3_RXD — Receiver input for USART3. See Table 4 for ISP

mode.

CTIN_0 — SCTimer/PWM input 0. Capture input 0 of timer 0,

1, 2, 3.

I/O GPIO5[4] — General purpose digital input/output pin.

-

R — Function reserved.

O

I

T3_MAT1 — Match output 1 of timer 3.

USB0_PWR_FAULT — Port power fault signal indicating

overcurrent condition; this signal monitors over-current on the

USB bus (external circuitry required to detect over-current

condition).

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[3]

P2_5

K14 D10 91

131

N;

PU

-

I

R — Function reserved.

CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0.

USB1_VBUS — Monitors the presence of USB1 bus power.

Note: This signal must be HIGH for USB reset to occur.

ADCTRIG1 — ADC trigger input 1.

I

I/O GPIO5[5] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT2 — Match output 2 of timer 3.

USB0_IND0 — USB0 port indicator LED control

output 0.

[2]

P2_6

K16 G9

95

137

N;

-

R — Function reserved.

PU

I/O U0_DIR — RS-485/EIA-485 output enable/direction control for

USART0.

I/O EMC_A10 — External memory address line 10.

O

USB0_IND0 — USB0 port indicator LED control

output 0.

I/O GPIO5[6] — General purpose digital input/output pin.

I

CTIN_7 — SCTimer/PWM input 7.

I

T3_CAP3 — Capture input 3 of timer 3.

EMC_BLS1 — LOW active Byte Lane select signal 1.

O

[2]

P2_7

H14 C10 96

138

N;

PU

I/O GPIO0[7] — General purpose digital input/output pin. ISP

entry pin. If this pin is pulled LOW at reset, the part enters ISP

mode or boots from an external source (see Table 4 and

Table 5).

O

CTOUT_1 — SCTimer/PWM output 1. Match output 3 of timer

3.

I/O U3_UCLK — Serial clock input/output for USART3 in

synchronous mode.

I/O EMC_A9 — External memory address line 9.

-

R — Function reserved.

-

R — Function reserved.

O

-

T3_MAT3 — Match output 3 of timer 3.

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P2_8

J16 C6

98

140

N;

-

R — Function reserved. External boot pin (see Table 5)

PU

O

CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer

0.

I/O U3_DIR — RS-485/EIA-485 output enable/direction control for

USART3.

I/O EMC_A8 — External memory address line 8.

I/O GPIO5[7] — General purpose digital input/output pin.

-

R — Function reserved.

[2]

P2_9

H16 B10 102 144

N;

I/O GPIO1[10] — General purpose digital input/output pin.

PU

External boot pin (see Table 5).

O

CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer

0.

I/O U3_BAUD — Baud pin for USART3.

I/O EMC_A0 — External memory address line 0.

-

R — Function reserved.

[2]

P2_10

G16 E8

104 146

N;

I/O GPIO0[14] — General purpose digital input/output pin.

PU

O

CTOUT_2 — SCTimer/PWM output 2. Match output 2 of timer

0.

O

U2_TXD — Transmitter output for USART2.

I/O EMC_A1 — External memory address line 1.

-

R — Function reserved.

[2]

P2_11

F16 A9

105 148

N;

I/O GPIO1[11] — General purpose digital input/output pin.

PU

O

CTOUT_5 — SCTimer/PWM output 5. Match output 3 of timer

3.

I

U2_RXD — Receiver input for USART2.

I/O EMC_A2 — External memory address line 2.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P2_12

E15 B9

106 153

N;

I/O GPIO1[12] — General purpose digital input/output pin.

PU

O

CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer

3.

-

R — Function reserved.

I/O EMC_A3 — External memory address line 3.

-

R — Function reserved.

I/O U2_UCLK — Serial clock input/output for USART2 in

synchronous mode.

[2]

P2_13

C16 A10 108 156

N;

I/O GPIO1[13] — General purpose digital input/output pin.

PU

I

CTIN_4 — SCTimer/PWM input 4. Capture input 2 of timer 1.

R — Function reserved.

-

I/O EMC_A4 — External memory address line 4.

-

R — Function reserved.

I/O U2_DIR — RS-485/EIA-485 output enable/direction control for

USART2.

[2]

P3_0

F13 A8

112 161

N;

PU

I/O I2S0_RX_SCK — I²S receive clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

O

I2S0_RX_MCLK — I²S receive master clock.

I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

O

I2S0_TX_MCLK — I²S transmit master clock.

I/O SSP0_SCK — Serial clock for SSP0.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

[4]

P3_1

P3_2

P3_3

G11 F7

F11 G6

B14 A7

114 163

116 166

118 169

N;

PU

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

I/O I2S0_RX_WS — Receive Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

I

CAN0_RD — CAN receiver input.

O

USB1_IND1 — USB1 Port indicator LED control output 1.

I/O GPIO5[8] — General purpose digital input/output pin.

-

R — Function reserved.

LCD_VD15 — LCD data.

R — Function reserved.

O

-

OL; I/O I2S0_TX_SDA — I²S transmit data. It is driven by the

PU

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

I/O I2S0_RX_SDA — I²S Receive data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

O

CAN0_TD — CAN transmitter output.

USB1_IND0 — USB1 Port indicator LED control output 0.

I/O GPIO5[9] — General purpose digital input/output pin.

-

R — Function reserved.

LCD_VD14 — LCD data.

R — Function reserved.

O

-

N;

PU

-

I/O SSP0_SCK — Serial clock for SSP0.

O

-

SPIFI_SCK — Serial clock for SPIFI.

CGU_OUT1 — CGU spare clock output 1.

R — Function reserved.

O

I2S0_TX_MCLK — I²S transmit master clock.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P3_4

A15 B8

119 171

N;

I/O GPIO1[14] — General purpose digital input/output pin.

PU

-

R — Function reserved.

I/O SPIFI_SIO3 — I/O lane 3 for SPIFI.

U1_TXD — Transmitter output for UART1.

O

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

I/O I2S1_RX_SDA — I²S1 Receive data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

O

LCD_VD13 — LCD data.

[2]

P3_5

C12 B7

121 173

N;

I/O GPIO1[15] — General purpose digital input/output pin.

PU

-

R — Function reserved.

I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.

I

U1_RXD — Receiver input for UART1.

I/O I2S0_TX_SDA — I²S transmit data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

I/O I2S1_RX_WS — Receive Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

O

LCD_VD12 — LCD data.

I/O GPIO0[6] — General purpose digital input/output pin.

R — Function reserved.

[2]

P3_6

B13 C7

122 174

N;

PU

-

I/O SSP0_SSEL — Slave Select for SSP0.

I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.

-

R — Function reserved.

I/O SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

[2]

P3_7

C11 D7

123 176

N;

PU

I/O SSP0_MISO — Master In Slave Out for SSP0.

I/O SPIFI_MOSI — Input 0 in SPIFI quad mode; SPIFI output IO0.

I/O GPIO5[10] — General purpose digital input/output pin.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P3_8

C10 E7

124 179

N;

PU

-

R — Function reserved.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

I/O SPIFI_CS — SPIFI serial flash chip select.

I/O GPIO5[11] — General purpose digital input/output pin.

I/O SSP0_SSEL — Slave Select for SSP0.

-

R — Function reserved.

[2]

P4_0

D5

-

1

N;

I/O GPIO2[0] — General purpose digital input/output pin.

PU

O

I

MCOA0 — Motor control PWM channel 0, output A.

NMI — External interrupt input to NMI.

R — Function reserved.

-

R — Function reserved.

O

LCD_VD13 — LCD data.

I/O U3_UCLK — Serial clock input/output for USART3 in

synchronous mode.

-

R — Function reserved.

[5]

P4_1

A1

-

3

N;

I/O GPIO2[1] — General purpose digital input/output pin.

PU

O

CTOUT_1 — SCTimer/PWM output 1. Match output 3 of timer

3.

O

-

LCD_VD0 — LCD data.

R — Function reserved.

-

R — Function reserved.

O

I

LCD_VD19 — LCD data.

U3_TXD — Transmitter output for USART3.

ENET_COL — Ethernet Collision detect (MII interface).

AI ADC0_1 — ADC0 and ADC1, input channel 1. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

[2]

P4_2

D3

-

8

12

N;

I/O GPIO2[2] — General purpose digital input/output pin.

PU

O

CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer

0.

O

-

LCD_VD3 — LCD data.

R — Function reserved.

-

R — Function reserved.

O

I

LCD_VD12 — LCD data.

U3_RXD — Receiver input for USART3.

R — Function reserved.

-

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[5]

P4_3

C2

-

7

10

N;

I/O GPIO2[3] — General purpose digital input/output pin.

PU

O

CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer

0.

O

-

LCD_VD2 — LCD data.

R — Function reserved.

LCD_VD21 — LCD data.

-

O

I/O U3_BAUD — Baud pin for USART3.

R — Function reserved.

-

AI ADC0_0 — ADC0 and ADC1, input channel 0. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

[5]

P4_4

B1

-

9

14

N;

I/O GPIO2[4] — General purpose digital input/output pin.

PU

O

CTOUT_2 — SCTimer/PWM output 2. Match output 2 of timer

0.

O

-

LCD_VD1 — LCD data.

R — Function reserved.

LCD_VD20 — LCD data.

-

O

I/O U3_DIR — RS-485/EIA-485 output enable/direction control for

USART3.

-

R — Function reserved.

AO DAC — DAC output. Configure the pin as GPIO input and use

the analog function select register in the SCU to select the

DAC.

[2]

P4_5

D2

-

10

15

N;

I/O GPIO2[5] — General purpose digital input/output pin.

PU

O

CTOUT_5 — SCTimer/PWM output 5. Match output 3 of timer

3.

O

LCD_FP — Frame pulse (STN). Vertical synchronization pulse

(TFT).

-

R — Function reserved.

LPC18S5X_S3X

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Product data sheet

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P4_6

C1

-

11

17

N;

I/O GPIO2[6] — General purpose digital input/output pin.

PU

O

CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer

3.

O

LCD_ENAB/LCDM — STN AC bias drive or TFT data enable

input.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

[2]

P4_7

H4

-

14

21

O;

PU

O

I

LCD_DCLK — LCD panel clock.

GP_CLKIN — General-purpose clock input to the CGU.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

[2]

P4_8

E2

-

15

23

N;

-

R — Function reserved.

PU

I

CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.

LCD_VD9 — LCD data.

O

-

R — Function reserved.

I/O GPIO5[12] — General purpose digital input/output pin.

O

-

LCD_VD22 — LCD data.

CAN1_TD — CAN1 transmitter output.

R — Function reserved.

[2]

P4_9

L2

-

33

48

N;

-

R — Function reserved.

PU

I

CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.

LCD_VD11 — LCD data.

O

-

R — Function reserved.

I/O GPIO5[13] — General purpose digital input/output pin.

O

I

LCD_VD15 — LCD data.

CAN1_RD — CAN1 receiver input.

R — Function reserved.

-

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P4_10

P5_0

P5_1

M3

N3

P3

-

35

37

39

51

53

55

N;

PU

-

R — Function reserved.

I

CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0.

LCD_VD10 — LCD data.

O

-

R — Function reserved.

I/O GPIO5[14] — General purpose digital input/output pin.

O

-

LCD_VD14 — LCD data.

R — Function reserved.

-

N;

PU

I/O GPIO2[9] — General purpose digital input/output pin.

MCOB2 — Motor control PWM channel 2, output B.

I/O EMC_D12 — External memory data line 12.

O

-

I

R — Function reserved.

U1_DSR — Data Set Ready input for UART1.

T1_CAP0 — Capture input 0 of timer 1.

R — Function reserved.

I

-

R — Function reserved.

N;

PU

I/O GPIO2[10] — General purpose digital input/output pin.

MCI2 — Motor control PWM channel 2, input.

I/O EMC_D13 — External memory data line 13.

I

-

R — Function reserved.

O

U1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal

for UART1.

I

T1_CAP1 — Capture input 1 of timer 1.

R — Function reserved.

-

R — Function reserved.

[2]

P5_2

R4

-

46

63

N;

PU

I/O GPIO2[11] — General purpose digital input/output pin.

MCI1 — Motor control PWM channel 1, input.

I/O EMC_D14 — External memory data line 14.

I

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1.

I

T1_CAP2 — Capture input 2 of timer 1.

R — Function reserved.

-

R — Function reserved.

LPC18S5X_S3X

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Product data sheet

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P5_3

P5_4

P5_5

P5_6

T8

-

54

57

58

63

76

80

81

89

N;

PU

I/O GPIO2[12] — General purpose digital input/output pin.

MCI0 — Motor control PWM channel 0, input.

I/O EMC_D15 — External memory data line 15.

I

-

I

R — Function reserved.

U1_RI — Ring Indicator input for UART1.

T1_CAP3 — Capture input 3 of timer 1.

R — Function reserved.

I

-

R — Function reserved.

P9

N;

PU

I/O GPIO2[13] — General purpose digital input/output pin.

MCOB0 — Motor control PWM channel 0, output B.

I/O EMC_D8 — External memory data line 8.

O

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART1.

T1_MAT0 — Match output 0 of timer 1.

R — Function reserved.

O

-

R — Function reserved.

P10

N;

PU

I/O GPIO2[14] — General purpose digital input/output pin.

MCOA1 — Motor control PWM channel 1, output A.

I/O EMC_D9 — External memory data line 9.

O

-

R — Function reserved.

I

U1_DCD — Data Carrier Detect input for UART1.

T1_MAT1 — Match output 1 of timer 1.

R — Function reserved.

O

-

R — Function reserved.

T13

N;

PU

I/O GPIO2[15] — General purpose digital input/output pin.

MCOB1 — Motor control PWM channel 1, output B.

I/O EMC_D10 — External memory data line 10.

O

-

R — Function reserved.

O

-

U1_TXD — Transmitter output for UART1.

T1_MAT2 — Match output 2 of timer 1.

R — Function reserved.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P5_7

R12

-

65

91

N;

PU

I/O GPIO2[7] — General purpose digital input/output pin.

MCOA2 — Motor control PWM channel 2, output A.

I/O EMC_D11 — External memory data line 11.

O

-

R — Function reserved.

I

U1_RXD — Receiver input for UART1.

T1_MAT3 — Match output 3 of timer 1.

R — Function reserved.

O

-

R — Function reserved.

[2]

P6_0

M12 H7

73

105

N;

-

R — Function reserved.

PU

O

-

I2S0_RX_MCLK — I²S receive master clock.

R — Function reserved.

-

R — Function reserved.

I/O I2S0_RX_SCK — Receive Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

-

R — Function reserved.

[2]

P6_1

R15 G5

74

107

N;

PU

I/O GPIO3[0] — General purpose digital input/output pin.

EMC_DYCS1 — SDRAM chip select 1.

O

I/O U0_UCLK — Serial clock input/output for USART0 in

synchronous mode.

I/O I2S0_RX_WS — Receive Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

-

I

R — Function reserved.

T2_CAP0 — Capture input 2 of timer 2.

R — Function reserved.

-

R — Function reserved.

[2]

P6_2

L13 J9

78

111

N;

PU

I/O GPIO3[1] — General purpose digital input/output pin.

EMC_CKEOUT1 — SDRAM clock enable 1.

O

I/O U0_DIR — RS-485/EIA-485 output enable/direction control for

USART0.

I/O I2S0_RX_SDA — I²S Receive data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

-

I

R — Function reserved.

T2_CAP1 — Capture input 1 of timer 2.

R — Function reserved.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P6_3

P15

-

79

113

N;

I/O GPIO3[2] — General purpose digital input/output pin.

PU

O

USB0_PPWR — VBUS drive signal (towards external charge

pump or power management unit); indicates that VBUS must

be driven (active HIGH). Add a pull-down resistor to disable the

power switch at reset. This signal has opposite polarity

compared to the USB_PPWR used on other NXP LPC parts.

-

R — Function reserved.

O

-

EMC_CS1 — LOW active Chip Select 1 signal.

R — Function reserved.

I

T2_CAP2 — Capture input 2 of timer 2.

R — Function reserved.

-

R — Function reserved.

[2]

P6_4

R16 F6

80

114

N;

I/O GPIO3[3] — General purpose digital input/output pin.

PU

I

CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.

U0_TXD — Transmitter output for USART0.

EMC_CAS — LOW active SDRAM Column Address Strobe.

R — Function reserved.

O

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

[2]

P6_5

P16 F9

82

117

N;

I/O GPIO3[4] — General purpose digital input/output pin.

PU

O

CTOUT_6 — SCTimer/PWM output 6. Match output 2 of timer

1.

I

U0_RXD — Receiver input for USART0.

EMC_RAS — LOW active SDRAM Row Address Strobe.

R — Function reserved.

O

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

[2]

P6_6

L14

-

83

119

N;

I/O GPIO0[5] — General purpose digital input/output pin.

PU

O

-

EMC_BLS1 — LOW active Byte Lane select signal 1.

R — Function reserved.

I

USB0_PWR_FAULT — Port power fault signal indicating

overcurrent condition; this signal monitors over-current on the

USB bus (external circuitry required to detect over-current

condition).

-

I

R — Function reserved.

T2_CAP3 — Capture input 3 of timer 2.

R — Function reserved.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P6_7

P6_8

P6_9

P6_10

J13

-

85

86

97

123

125

139

N;

PU

-

R — Function reserved.

I/O EMC_A15 — External memory address line 15.

-

R — Function reserved.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O GPIO5[15] — General purpose digital input/output pin.

O

-

T2_MAT0 — Match output 0 of timer 2.

R — Function reserved.

-

R — Function reserved.

H13

-

N;

PU

-

R — Function reserved.

I/O EMC_A14 — External memory address line 14.

-

R — Function reserved.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O GPIO5[16] — General purpose digital input/output pin.

O

-

T2_MAT1 — Match output 1 of timer 2.

R — Function reserved.

-

R — Function reserved.

J15 F8

N;

PU

I/O GPIO3[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

-

EMC_DYCS0 — SDRAM chip select 0.

R — Function reserved.

O

-

T2_MAT2 — Match output 2 of timer 2.

R — Function reserved.

-

R — Function reserved.

H15

-

100 142

N;

I/O GPIO3[6] — General purpose digital input/output pin.

PU

O

-

MCABORT — Motor control PWM, LOW-active fast abort.

R — Function reserved.

O

EMC_DQMOUT1 — Data mask 1 used with SDRAM and static

devices.

-

R — Function reserved.

LPC18S5X_S3X

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28 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P6_11

H12 C9

101 143

N;

I/O GPIO3[7] — General purpose digital input/output pin.

PU

-

R — Function reserved.

-

R — Function reserved.

O

-

EMC_CKEOUT0 — SDRAM clock enable 0.

R — Function reserved.

O

-

T2_MAT3 — Match output 3 of timer 2.

R — Function reserved.

-

R — Function reserved.

[2]

P6_12

G15

-

103 145

N;

I/O GPIO2[8] — General purpose digital input/output pin.

PU

O

CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer

1.

-

R — Function reserved.

O

EMC_DQMOUT0 — Data mask 0 used with SDRAM and static

devices.

-

R — Function reserved.

[2]

P7_0

B16

-

110 158

N;

I/O GPIO3[8] — General purpose digital input/output pin.

PU

O

CTOUT_14 — SCTimer/PWM output 14. Match output 2 of

timer 3.

-

R — Function reserved.

LCD_LE — Line end signal.

R — Function reserved.

O

-

[2]

P7_1

C14

-

113 162

N;

I/O GPIO3[9] — General purpose digital input/output pin.

PU

O

CTOUT_15 — SCTimer/PWM output 15. Match output 3 of

timer 3.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

O

-

LCD_VD19 — LCD data.

LCD_VD7 — LCD data.

R — Function reserved.

O

-

U2_TXD — Transmitter output for USART2.

R — Function reserved.

LPC18S5X_S3X

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Product data sheet

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29 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P7_2

A16

-

115 165

N;

PU

I/O GPIO3[10] — General purpose digital input/output pin.

CTIN_4 — SCTimer/PWM input 4. Capture input 2 of timer 1.

I

I/O I2S0_TX_SDA — I²S transmit data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

O

-

LCD_VD18 — LCD data.

LCD_VD6 — LCD data.

R — Function reserved.

I

U2_RXD — Receiver input for USART2.

R — Function reserved.

-

[2]

P7_3

C13

-

117 167

N;

I/O GPIO3[11] — General purpose digital input/output pin.

PU

I

CTIN_3 — SCTimer/PWM input 3. Capture input 1 of timer 1.

R — Function reserved.

-

O

-

LCD_VD17 — LCD data.

LCD_VD5 — LCD data.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

[5]

P7_4

C8

-

132 189

N;

I/O GPIO3[12] — General purpose digital input/output pin.

PU

O

CTOUT_13 — SCTimer/PWM output 13. Match output 3 of

timer 3.

-

R — Function reserved.

O

-

LCD_VD16 — LCD data.

LCD_VD4 — LCD data.

TRACEDATA[0] — Trace data, bit 0.

R — Function reserved.

-

R — Function reserved.

AI ADC0_4 — ADC0 and ADC1, input channel 4. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[5]

P7_5

A7

-

133 191

N;

I/O GPIO3[13] — General purpose digital input/output pin.

PU

O

CTOUT_12 — SCTimer/PWM output 12. Match output 3 of

timer 3.

-

R — Function reserved.

O

-

LCD_VD8 — LCD data.

LCD_VD23 — LCD data.

TRACEDATA[1] — Trace data, bit 1.

R — Function reserved.

-

R — Function reserved.

AI ADC0_3 — ADC0 and ADC1, input channel 3. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

[2]

P7_6

C7

-

134 194

N;

I/O GPIO3[14] — General purpose digital input/output pin.

PU

O

CTOUT_11 — SCTimer/PWM output 1. Match output 3 of timer

2.

-

R — Function reserved.

O

LCD_LP — Line synchronization pulse (STN). Horizontal

synchronization pulse (TFT).

-

R — Function reserved.

O

-

TRACEDATA[2] — Trace data, bit 2.

R — Function reserved.

-

R — Function reserved.

[5]

P7_7

B6

-

140 201

N;

I/O GPIO3[15] — General purpose digital input/output pin.

PU

O

CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer

2.

-

R — Function reserved.

O

-

LCD_PWR — LCD panel power enable.

R — Function reserved.

O

-

TRACEDATA[3] — Trace data, bit 3.

ENET_MDC — Ethernet MIIM clock.

R — Function reserved.

AI ADC1_6 — ADC1 and ADC0, input channel 6. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[3]

P8_0

E5

-

2

N;

I/O GPIO4[0] — General purpose digital input/output pin.

PU

I

USB0_PWR_FAULT — Port power fault signal indicating

overcurrent condition; this signal monitors over-current on the

USB bus (external circuitry required to detect over-current

condition).

-

R — Function reserved.

I

MCI2 — Motor control PWM channel 2, input.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT0 — Match output 0 of timer 0.

[3]

[2]

P8_1

P8_2

P8_3

H5

K4

J3

-

34

36

37

N;

PU

I/O GPIO4[1] — General purpose digital input/output pin.

O

-

USB0_IND1 — USB0 port indicator LED control output 1.

R — Function reserved.

I

MCI1 — Motor control PWM channel 1, input.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT1 — Match output 1 of timer 0.

N;

PU

I/O GPIO4[2] — General purpose digital input/output pin.

O

-

USB0_IND0 — USB0 port indicator LED control output 0.

R — Function reserved.

I

MCI0 — Motor control PWM channel 0, input.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT2 — Match output 2 of timer 0.

N;

PU

I/O GPIO4[3] — General purpose digital input/output pin.

I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-

R — Function reserved.

O

-

LCD_VD12 — LCD data.

LCD_VD19 — LCD data.

R — Function reserved.

-

R — Function reserved.

O

T0_MAT3 — Match output 3 of timer 0.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P8_4

P8_5

P8_6

J2

J1

K3

-

39

40

43

N;

PU

I/O GPIO4[4] — General purpose digital input/output pin.

I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

R — Function reserved.

O

-

LCD_VD7 — LCD data.

LCD_VD16 — LCD data.

R — Function reserved.

-

R — Function reserved.

I

T0_CAP0 — Capture input 0 of timer 0.

N;

PU

I/O GPIO4[5] — General purpose digital input/output pin.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-

R — Function reserved.

O

-

LCD_VD6 — LCD data.

LCD_VD8 — LCD data.

R — Function reserved.

-

R — Function reserved.

I

T0_CAP1 — Capture input 1 of timer 0.

N;

I/O GPIO4[6] — General purpose digital input/output pin.

PU

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control

signal from the PHY.

-

R — Function reserved.

LCD_VD5 — LCD data.

O

LCD_LP — Line synchronization pulse (STN). Horizontal

synchronization pulse (TFT).

-

I

R — Function reserved.

T0_CAP2 — Capture input 2 of timer 0.

[2]

P8_7

K1

-

45

N;

I/O GPIO4[7] — General purpose digital input/output pin.

PU

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or

interrupt transfers to the PHY.

-

R — Function reserved.

O

-

LCD_VD4 — LCD data.

LCD_PWR — LCD panel power enable.

R — Function reserved.

-

R — Function reserved.

I

T0_CAP3 — Capture input 3 of timer 0.

LPC18S5X_S3X

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Product data sheet

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33 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P8_8

L1

-

49

N;

PU

-

I

R — Function reserved.

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock

generated by the PHY.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT0 — CGU spare clock output 0.

I2S1_TX_MCLK — I²S1 transmit master clock.

[2]

P9_0

T1

-

59

N;

I/O GPIO4[12] — General purpose digital input/output pin.

PU

O

-

MCABORT — Motor control PWM, LOW-active fast abort.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

R — Function reserved.

-

I/O SSP0_SSEL — Slave Select for SSP0.

[2]

P9_1

N6

-

66

N;

I/O GPIO4[13] — General purpose digital input/output pin.

PU

O

-

MCOA2 — Motor control PWM channel 2, output A.

R — Function reserved.

-

R — Function reserved.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

I

ENET_RX_ER — Ethernet receive error (MII interface).

R — Function reserved.

-

I/O SSP0_MISO — Master In Slave Out for SSP0.

[2]

P9_2

N8

-

70

N;

I/O GPIO4[14] — General purpose digital input/output pin.

PU

O

-

MCOB2 — Motor control PWM channel 2, output B.

R — Function reserved.

-

R — Function reserved.

I/O I2S0_TX_SDA — I²S transmit data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

I

ENET_RXD3 — Ethernet receive data 3 (MII interface).

R — Function reserved.

-

I/O SSP0_MOSI — Master Out Slave in for SSP0.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

P9_3

P9_4

P9_5

M6

-

79

92

98

N;

PU

I/O GPIO4[15] — General purpose digital input/output pin.

O

-

MCOA0 — Motor control PWM channel 0, output A.

USB1_IND1 — USB1 Port indicator LED control output 1.

R — Function reserved.

-

R — Function reserved.

I

ENET_RXD2 — Ethernet receive data 2 (MII interface).

R — Function reserved.

-

O

-

U3_TXD — Transmitter output for USART3.

R — Function reserved.

N10

-

N;

PU

O

-

MCOB0 — Motor control PWM channel 0, output B.

USB1_IND0 — USB1 Port indicator LED control output 0.

R — Function reserved.

I/O GPIO5[17] — General purpose digital input/output pin.

O

-

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

R — Function reserved.

I

U3_RXD — Receiver input for USART3.

R — Function reserved.

M9

69

N;

-

PU

O

MCOA1 — Motor control PWM channel 1, output A.

USB1_PPWR — VBUS drive signal (towards external charge

pump or power management unit); indicates that VBUS must

be driven (active HIGH). Add a pull-down resistor to disable the

power switch at reset. This signal has opposite polarity

compared to the USB_PPWR used on other NXP LPC parts.

-

R — Function reserved.

I/O GPIO5[18] — General purpose digital input/output pin.

O

-

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

R — Function reserved.

O

U0_TXD — Transmitter output for USART0.

[2]

P9_6

L11

-

72

103

N;

I/O GPIO4[11] — General purpose digital input/output pin.

PU

O

I

MCOB1 — Motor control PWM channel 1, output B.

USB1_PWR_FAULT — USB1 Port power fault signal

indicating over-current condition; this signal monitors

over-current on the USB1 bus (external circuitry required to

detect over-current condition).

-

I

R — Function reserved.

ENET_COL — Ethernet Collision detect (MII interface).

R — Function reserved.

-

I

U0_RXD — Receiver input for USART0.

LPC18S5X_S3X

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Product data sheet

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35 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

[3]

PA_0

PA_1

PA_2

PA_3

L12

J14

K15

H11

-

126

134

136

147

N;

PU

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

-

I2S1_RX_MCLK — I²S1 receive master clock.

CGU_OUT1 — CGU spare clock output 1.

R — Function reserved.

N;

PU

I/O GPIO4[8] — General purpose digital input/output pin.

I

QEI_IDX — Quadrature Encoder Interface INDEX input.

R — Function reserved.

-

O

-

U2_TXD — Transmitter output for USART2.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

N;

PU

I/O GPIO4[9] — General purpose digital input/output pin.

I

QEI_PHB — Quadrature Encoder Interface PHB input.

R — Function reserved.

-

I

U2_RXD — Receiver input for USART2.

R — Function reserved.

-

R — Function reserved.

N;

I/O GPIO4[10] — General purpose digital input/output pin.

PU

I

QEI_PHA — Quadrature Encoder Interface PHA input.

R — Function reserved.

-

R — Function reserved.

LPC18S5X_S3X

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Product data sheet

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36 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PA_4

PB_0

PB_1

G13

B15

A14

-

151

164

175

N;

PU

-

R — Function reserved.

O

CTOUT_9 — SCTimer/PWM output 9. Match output 3 of timer

3.

-

R — Function reserved.

I/O EMC_A23 — External memory address line 23.

I/O GPIO5[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

N;

PU

-

O

CTOUT_10 — SCTimer/PWM output 10. Match output 3 of

timer 3.

O

-

LCD_VD23 — LCD data.

R — Function reserved.

I/O GPIO5[20] — General purpose digital input/output pin.

-

I

R — Function reserved.

N;

PU

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP

data line direction.

O

-

LCD_VD22 — LCD data.

R — Function reserved.

I/O GPIO5[21] — General purpose digital input/output pin.

O

CTOUT_6 — SCTimer/PWM output 6. Match output 2 of timer

1.

-

R — Function reserved.

[2]

PB_2

B12

-

177

N;

PU

I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.

O

-

LCD_VD21 — LCD data.

R — Function reserved.

I/O GPIO5[22] — General purpose digital input/output pin.

O

CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer

1.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PB_3

A13

-

178

N;

-

R — Function reserved.

PU

I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.

O

-

LCD_VD20 — LCD data.

R — Function reserved.

I/O GPIO5[23] — General purpose digital input/output pin.

O

CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer

2.

-

R — Function reserved.

[2]

[5]

PB_4

PB_5

PB_6

B11

A12

A6

-

180

181

-

N;

PU

I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.

O

-

LCD_VD15 — LCD data.

R — Function reserved.

I/O GPIO5[24] — General purpose digital input/output pin.

I

CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.

R — Function reserved.

-

R — Function reserved.

N;

PU

R — Function reserved.

I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.

O

-

LCD_VD14 — LCD data.

R — Function reserved.

I/O GPIO5[25] — General purpose digital input/output pin.

I

CTIN_7 — SCTimer/PWM input 7.

LCD_PWR — LCD panel power enable.

R — Function reserved.

O

-

N;

-

R — Function reserved.

PU

I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.

O

-

LCD_VD13 — LCD data.

R — Function reserved.

I/O GPIO5[26] — General purpose digital input/output pin.

I

CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.

LCD_VD19 — LCD data.

O

-

R — Function reserved.

AI ADC0_6 and ADC1 — ADC0, input channel 6. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[5]

PC_0

D4

-

7

N;

PU

-

I

R — Function reserved.

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock

generated by the PHY.

-

R — Function reserved.

I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface).

O

-

LCD_DCLK — LCD panel clock.

R — Function reserved.

-

R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

AI ADC1_1 — ADC1 and ADC0, input channel 1. Configure the

pin as input (USB_ULPI_CLK) and use the ADC function select

register in the SCU to select the ADC.

[2]

PC_1

E4

-

9

N;

I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.

PU

-

R — Function reserved.

I

U1_RI — Ring Indicator input for UART1.

ENET_MDC — Ethernet MIIM clock.

O

I/O GPIO6[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

SD_VOLT0 — SD/MMC bus voltage select output 0.

O

[2]

PC_2

F6

-

13

N;

I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.

PU

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART1.

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

O

I/O GPIO6[1] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[5]

PC_3

F5

-

11

N;

I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.

PU

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O GPIO6[2] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

AI ADC1_0 — ADC1 and ADC0, input channel 0. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

[2]

PC_4

F4

-

16

N;

-

R — Function reserved.

PU

I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.

-

R — Function reserved.

ENET_TX_EN — Ethernet transmit enable (RMII/MII

interface).

I/O GPIO6[3] — General purpose digital input/output pin.

-

I

R — Function reserved.

T3_CAP1 — Capture input 1 of timer 3.

I/O SD_DAT0 — SD/MMC data bus line 0.

R — Function reserved.

I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.

[2]

PC_5

G4

-

20

N;

PU

-

R — Function reserved.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O GPIO6[4] — General purpose digital input/output pin.

-

I

R — Function reserved.

T3_CAP2 — Capture input 2 of timer 3.

I/O SD_DAT1 — SD/MMC data bus line 1.

R — Function reserved.

I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.

[2]

PC_6

H6

-

22

N;

PU

-

I

R — Function reserved.

ENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O GPIO6[5] — General purpose digital input/output pin.

-

I

R — Function reserved.

T3_CAP3 — Capture input 3 of timer 3.

I/O SD_DAT2 — SD/MMC data bus line 2.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PC_7

G5

-

N;

-

R — Function reserved.

PU

I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

I

R — Function reserved.

ENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O GPIO6[6] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

I/O SD_DAT3 — SD/MMC data bus line 3.

R — Function reserved.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

[2]

PC_8

N4

-

N;

PU

-

I

R — Function reserved.

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII

interface).

I/O GPIO6[7] — General purpose digital input/output pin.

-

R — Function reserved.

O

I

T3_MAT1 — Match output 1 of timer 3.

SD_CD — SD/MMC card detect input.

R — Function reserved.

[2]

PC_9

K2

-

N;

-

PU

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control

signal from the PHY.

-

I

R — Function reserved.

ENET_RX_ER — Ethernet receive error (MII interface).

I/O GPIO6[8] — General purpose digital input/output pin.

-

R — Function reserved.

O

-

T3_MAT2 — Match output 2 of timer 3.

SD_POW — SD/MMC power monitor output.

R — Function reserved.

[2]

PC_10

M5

-

N;

PU

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or

interrupt transfers to the PHY.

I

U1_DSR — Data Set Ready input for UART1.

R — Function reserved.

-

I/O GPIO6[9] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT3 — Match output 3 of timer 3.

I/O SD_CMD — SD/MMC command signal.

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PC_11

L5

-

N;

PU

-

I

R — Function reserved.

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP

data line direction.

I

U1_DCD — Data Carrier Detect input for UART1.

R — Function reserved.

-

I/O GPIO6[10] — General purpose digital input/output pin.

-

R — Function reserved.

I/O SD_DAT4 — SD/MMC data bus line 4.

[2]

PC_12

L6

-

N;

PU

-

R — Function reserved.

-

O

U1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal

for UART1.

-

R — Function reserved.

I/O GPIO6[11] — General purpose digital input/output pin.

-

R — Function reserved.

I/O I2S0_TX_SDA — I²S transmit data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

I/O SD_DAT5 — SD/MMC data bus line 5.

[2]

PC_13

M1

-

N;

-

R — Function reserved.

PU

-

R — Function reserved.

O

-

U1_TXD — Transmitter output for UART1.

R — Function reserved.

I/O GPIO6[12] — General purpose digital input/output pin.

R — Function reserved.

-

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

I/O SD_DAT6 — SD/MMC data bus line 6.

[2]

PC_14

N1

-

N;

PU

-

I

R — Function reserved.

U1_RXD — Receiver input for UART1.

R — Function reserved.

-

I/O GPIO6[13] — General purpose digital input/output pin.

-

R — Function reserved.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O SD_DAT7 — SD/MMC data bus line 7.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PD_0

N2

-

N;

-

R — Function reserved.

PU

O

CTOUT_15 — SCTimer/PWM output 15. Match output 3 of

timer 3.

O

-

EMC_DQMOUT2 — Data mask 2 used with SDRAM and static

devices.

R — Function reserved.

I/O GPIO6[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

[2]

PD_1

P1

-

N;

-

R — Function reserved.

PU

-

R — Function reserved.

O

-

EMC_CKEOUT2 — SDRAM clock enable 2.

R — Function reserved.

I/O GPIO6[15] — General purpose digital input/output pin.

O

-

SD_POW — SD/MMC power monitor output.

R — Function reserved.

-

R — Function reserved.

[2]

PD_2

R1

-

N;

-

R — Function reserved.

PU

O

CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer

1.

I/O EMC_D16 — External memory data line 16.

R — Function reserved.

I/O GPIO6[16] — General purpose digital input/output pin.

-

R — Function reserved.

-

[2]

PD_3

P4

-

N;

-

PU

O

CTOUT_6 — SCTimer/PWM output 7. Match output 2 of timer

1.

I/O EMC_D17 — External memory data line 17.

R — Function reserved.

I/O GPIO6[17] — General purpose digital input/output pin.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PD_4

PD_5

PD_6

PD_7

T2

P6

R6

T6

-

N;

PU

-

R — Function reserved.

O

CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer

2.

I/O EMC_D18 — External memory data line 18.

R — Function reserved.

I/O GPIO6[18] — General purpose digital input/output pin.

-

R — Function reserved.

-

N;

PU

-

O

CTOUT_9 — SCTimer/PWM output 9. Match output 3 of timer

3.

I/O EMC_D19 — External memory data line 19.

R — Function reserved.

I/O GPIO6[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

68

N;

PU

-

O

CTOUT_10 — SCTimer/PWM output 10. Match output 3 of

timer 3.

I/O EMC_D20 — External memory data line 20.

R — Function reserved.

I/O GPIO6[20] — General purpose digital input/output pin.

-

I

R — Function reserved.

72

N;

PU

R — Function reserved.

CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.

I/O EMC_D21 — External memory data line 21.

R — Function reserved.

I/O GPIO6[21] — General purpose digital input/output pin.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PD_8

P8

-

74

N;

PU

-

I

R — Function reserved.

CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.

I/O EMC_D22 — External memory data line 22.

R — Function reserved.

I/O GPIO6[22] — General purpose digital input/output pin.

-

R — Function reserved.

-

[2]

PD_9

T11

-

84

N;

-

PU

O

CTOUT_13 — SCTimer/PWM output 13. Match output 3 of

timer 3.

I/O EMC_D23 — External memory data line 23.

R — Function reserved.

I/O GPIO6[23] — General purpose digital input/output pin.

-

I

R — Function reserved.

[2]

PD_10

P11

-

86

N;

PU

CTIN_1 — SCTimer/PWM input 1. Capture input 1 of timer 0.

Capture input 1 of

timer 2.

O

-

EMC_BLS3 — LOW active Byte Lane select signal 3.

R — Function reserved.

I/O GPIO6[24] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

[2]

PD_11

N9

-

88

N;

-

R — Function reserved.

PU

-

R — Function reserved.

O

-

EMC_CS3 — LOW active Chip Select 3 signal.

R — Function reserved.

I/O GPIO6[25] — General purpose digital input/output pin.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

O

CTOUT_14 — SCTimer/PWM output 14. Match output 2 of

timer 3.

-

R — Function reserved.

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PD_12

N11

-

94

N;

-

R — Function reserved.

PU

-

R — Function reserved.

O

-

EMC_CS2 — LOW active Chip Select 2 signal.

R — Function reserved.

I/O GPIO6[26] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_10 — SCTimer/PWM output 10. Match output 3 of

timer 3.

-

I

R — Function reserved.

[2]

PD_13

T14

-

97

N;

PU

CTIN_0 — SCTimer/PWM input 0. Capture input 0 of timer 0,

1, 2, 3.

O

-

EMC_BLS2 — LOW active Byte Lane select signal 2.

R — Function reserved.

I/O GPIO6[27] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_13 — SCTimer/PWM output 13. Match output 3 of

timer 3.

-

R — Function reserved.

[2]

PD_14

R13

-

99

N;

-

R — Function reserved.

PU

-

R — Function reserved.

O

-

EMC_DYCS2 — SDRAM chip select 2.

R — Function reserved.

I/O GPIO6[28] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_11 — SCTimer/PWM output 11. Match output 3 of

timer 2.

-

R — Function reserved.

[2]

PD_15

T15

-

101

N;

PU

I/O EMC_A17 — External memory address line 17.

R — Function reserved.

I/O GPIO6[29] — General purpose digital input/output pin.

-

I

SD_WP — SD/MMC card write protect input.

O

CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer

2.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PD_16

R14

-

104

N;

PU

-

R — Function reserved.

I/O EMC_A16 — External memory address line 16.

R — Function reserved.

I/O GPIO6[30] — General purpose digital input/output pin.

-

O

SD_VOLT2 — SD/MMC bus voltage select output 2.

CTOUT_12 — SCTimer/PWM output 12. Match output 3 of

timer 3.

-

R — Function reserved.

[2]

PE_0

PE_1

PE_2

P14

N14

M14

-

106

112

115

N;

PU

I/O EMC_A18 — External memory address line 18.

I/O GPIO7[0] — General purpose digital input/output pin.

O

-

CAN1_TD — CAN1 transmitter output.

R — Function reserved.

-

R — Function reserved.

N;

PU

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O EMC_A19 — External memory address line 19.

I/O GPIO7[1] — General purpose digital input/output pin.

I

-

I

-

CAN1_RD — CAN1 receiver input.

R — Function reserved.

N;

PU

ADCTRIG0 — ADC trigger input 0.

CAN0_RD — CAN receiver input.

R — Function reserved.

I/O EMC_A20 — External memory address line 20.

I/O GPIO7[2] — General purpose digital input/output pin.

-

R — Function reserved.

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PE_3

PE_4

PE_5

K12

K13

N16

-

118

120

122

N;

PU

-

R — Function reserved.

O

I

CAN0_TD — CAN transmitter output.

ADCTRIG1 — ADC trigger input 1.

I/O EMC_A21 — External memory address line 21.

I/O GPIO7[3] — General purpose digital input/output pin.

-

I

R — Function reserved.

N;

PU

R — Function reserved.

NMI — External interrupt input to NMI.

R — Function reserved.

-

I/O EMC_A22 — External memory address line 22.

I/O GPIO7[4] — General purpose digital input/output pin.

-

R — Function reserved.

-

N;

-

PU

O

CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer

0.

O

U1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1.

I/O EMC_D24 — External memory data line 24.

I/O GPIO7[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

[2]

PE_6

M16

-

124

N;

-

PU

O

CTOUT_2 — SCTimer/PWM output 2. Match output 2 of timer

0.

I

U1_RI — Ring Indicator input for UART1.

I/O EMC_D25 — External memory data line 25.

I/O GPIO7[6] — General purpose digital input/output pin.

-

R — Function reserved.

LPC18S5X_S3X

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Product data sheet

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PE_7

F15

-

149

N;

-

R — Function reserved.

PU

O

CTOUT_5 — SCTimer/PWM output 5. Match output 3 of timer

3.

I

U1_CTS — Clear to Send input for UART1.

I/O EMC_D26 — External memory data line 26.

I/O GPIO7[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

[2]

PE_8

F14

-

150

N;

-

PU

O

CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer

3.

I

U1_DSR — Data Set Ready input for UART1.

I/O EMC_D27 — External memory data line 27.

I/O GPIO7[8] — General purpose digital input/output pin.

-

I

R — Function reserved.

[2]

PE_9

E16

-

152

N;

PU

R — Function reserved.

CTIN_4 — SCTimer/PWM input 4. Capture input 2 of timer 1.

U1_DCD — Data Carrier Detect input for UART1.

I

I/O EMC_D28 — External memory data line 28.

I/O GPIO7[9] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

[2]

PE_10

E14

-

154

N;

-

R — Function reserved.

PU

I

CTIN_3 — SCTimer/PWM input 3. Capture input 1 of timer 1.

O

U1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal

for UART1.

I/O EMC_D29 — External memory data line 29.

I/O GPIO7[10] — General purpose digital input/output pin.

-

R — Function reserved.

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Table 3.

Pin description …continued

Pin name

Description

[2]

PE_11

PE_12

PE_13

D16

D15

G14

-

N;

PU

-

R — Function reserved.

O

CTOUT_12 — SCTimer/PWM output 12. Match output 3 of

timer 3.

O

U1_TXD — Transmitter output for UART1.

I/O EMC_D30 — External memory data line 30.

I/O GPIO7[11] — General purpose digital input/output pin.

-

R — Function reserved.

-

N;

PU

-

O

CTOUT_11 — SCTimer/PWM output 11. Match output 3 of

timer 2.

I

U1_RXD — Receiver input for UART1.

I/O EMC_D31 — External memory data line 31.

I/O GPIO7[12] — General purpose digital input/output pin.

-

R — Function reserved.

-

N;

-

PU

O

CTOUT_14 — SCTimer/PWM output 14. Match output 2 of

timer 3.

I/O I2C1_SDA — I²C1 data input/output (this pin does not use a

specialized I²C pad).

O

EMC_DQMOUT3 — Data mask 3 used with SDRAM and static

devices.

I/O GPIO7[13] — General purpose digital input/output pin.

-

R — Function reserved.

EMC_DYCS3 — SDRAM chip select 3.

-

[2]

PE_14

C15

-

N;

-

PU

-

O

I/O GPIO7[14] — General purpose digital input/output pin.

-

R — Function reserved.

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PE_15

E13

-

N;

-

R — Function reserved.

PU

O

CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer

0.

I/O I2C1_SCL — I²C1 clock input/output (this pin does not use a

specialized I²C pad).

O

EMC_CKEOUT3 — SDRAM clock enable 3.

I/O GPIO7[15] — General purpose digital input/output pin.

-

R — Function reserved.

[2]

PF_0

PF_1

PF_2

D12

E11

D11

-

159

OL; I/O SSP0_SCK — Serial clock for SSP0.

PU

I

GP_CLKIN — General-purpose clock input to the CGU.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

-

I2S1_TX_MCLK — I²S1 transmit master clock.

-

N;

R — Function reserved.

PU

-

R — Function reserved.

I/O SSP0_SSEL — Slave Select for SSP0.

R — Function reserved.

I/O GPIO7[16] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

168

N;

-

R — Function reserved.

PU

O

U3_TXD — Transmitter output for USART3.

I/O SSP0_MISO — Master In Slave Out for SSP0.

R — Function reserved.

I/O GPIO7[17] — General purpose digital input/output pin.

-

R — Function reserved.

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[2]

PF_3

E10

-

170

N;

PU

-

I

R — Function reserved.

U3_RXD — Receiver input for USART3.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

R — Function reserved.

I/O GPIO7[18] — General purpose digital input/output pin.

-

R — Function reserved.

[2]

PF_4

D10 H4

120 172

OL; I/O SSP1_SCK — Serial clock for SSP1.

PU

I

GP_CLKIN — General-purpose clock input to the CGU.

TRACECLK — Trace clock.

O

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S0_TX_MCLK — I²S transmit master clock.

I/O I2S0_RX_SCK — I²S receive clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

[5]

PF_5

E9

-

190

N;

-

R — Function reserved.

PU

I/O U3_UCLK — Serial clock input/output for USART3 in

synchronous mode.

I/O SSP1_SSEL — Slave Select for SSP1.

O

TRACEDATA[0] — Trace data, bit 0.

I/O GPIO7[19] — General purpose digital input/output pin.

-

R — Function reserved.

AI ADC1_4 — ADC1 and ADC0, input channel 4. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[5]

PF_6

E7

-

192

N;

-

R — Function reserved.

PU

I/O U3_DIR — RS-485/EIA-485 output enable/direction control for

USART3.

I/O SSP1_MISO — Master In Slave Out for SSP1.

O

TRACEDATA[1] — Trace data, bit 1.

I/O GPIO7[20] — General purpose digital input/output pin.

-

R — Function reserved.

I/O I2S1_TX_SDA — I²S1 transmit data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I²S-bus specification.

AI ADC1_3 — ADC1 and ADC0, input channel 3. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

[5]

PF_7

B7

-

193

N;

-

R — Function reserved.

PU

I/O U3_BAUD — Baud pin USART3.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

O

TRACEDATA[2] — Trace data, bit 2.

I/O GPIO7[21] — General purpose digital input/output pin.

-

R — Function reserved.

I/O I2S1_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I²S-bus specification.

AI/ ADC1_7 — ADC1 and ADC0, input channel 7 or band gap

O

output. Configure the pin as GPIO input and use the ADC

function select register in the SCU to select the ADC.

[5]

PF_8

E6

-

N;

-

R — Function reserved.

PU

I/O U0_UCLK — Serial clock input/output for USART0 in

synchronous mode.

I

CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0.

TRACEDATA[3] — Trace data, bit 3.

O

I/O GPIO7[22] — General purpose digital input/output pin.

-

R — Function reserved.

AI ADC0_2 — ADC0 and ADC1, input channel 2. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[5]

PF_9

D6

-

203

N;

-

R — Function reserved.

PU

I/O U0_DIR — RS-485/EIA-485 output enable/direction control for

USART0.

O

-

CTOUT_1 — SCTimer/PWM output 1. Match output 3 of timer

3.

R — Function reserved.

I/O GPIO7[23] — General purpose digital input/output pin.

-

R — Function reserved.

AI ADC1_2 — ADC1 and ADC0, input channel 2. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

[5]

PF_10

A3

-

205

N;

-

R — Function reserved.

PU

O

-

U0_TXD — Transmitter output for USART0.

R — Function reserved.

-

R — Function reserved.

I/O GPIO7[24] — General purpose digital input/output pin.

-

I

R — Function reserved.

SD_WP — SD/MMC card write protect input.

R — Function reserved.

-

AI ADC0_5 — ADC0 and ADC1, input channel 5. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

[5]

PF_11

A2

-

207

N;

PU

-

I

R — Function reserved.

U0_RXD — Receiver input for USART0.

R — Function reserved.

-

R — Function reserved.

I/O GPIO7[25] — General purpose digital input/output pin.

-

R — Function reserved.

O

-

SD_VOLT2 — SD/MMC bus voltage select output 2.

R — Function reserved.

AI ADC1_5 — ADC1 and ADC0, input channel 5. Configure the

pin as GPIO input and use the ADC function select register in

the SCU to select the ADC.

Clock pins

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[4]

CLK0

N5

K3

45

62

O;

PU

O

-

EMC_CLK0 — SDRAM clock 0.

CLKOUT — Clock output pin.

R — Function reserved.

-

R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

EMC_CLK01 — SDRAM clock 0 and clock 1 combined.

I/O SSP1_SCK — Serial clock for SSP1.

O

I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit

Clock (MII interface) or Ethernet Reference Clock (RMII

interface).

[4]

CLK1

T10

-

O;

PU

O

-

EMC_CLK1 — SDRAM clock 1.

CLKOUT — Clock output pin.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

-

CGU_OUT0 — CGU spare clock output 0.

R — Function reserved.

O

-

I2S1_TX_MCLK — I²S1 transmit master clock.

EMC_CLK3 — SDRAM clock 3.

CLKOUT — Clock output pin.

R — Function reserved.

[4]

CLK2

D14 K6

99

141

O;

PU

-

R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

O

EMC_CLK23 — SDRAM clock 2 and clock 3 combined.

I2S0_TX_MCLK — I²S transmit master clock.

I/O I2S1_RX_SCK — Receive Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

[4]

CLK3

P12

-

O;

PU

O

-

EMC_CLK2 — SDRAM clock 2.

CLKOUT — Clock output pin.

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

-

CGU_OUT1 — CGU spare clock output 1.

R — Function reserved.

I/O I2S1_RX_SCK — Receive Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I²S-bus specification.

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

Debug pins

[2]

DBGEN

L4

A6

28

41

I

JTAG interface control signal. Also used for boundary scan. To

use the part in functional mode, connect this pin in one of the

following ways:

• Leave DBGEN open. The DBGEN pin is pulled up

internally by a 50 kΩ resistor.

• Tie DBGEN to VDDIO.

• Pull DBGEN up to VDDIO with an external pull-up resistor.

Test Clock for JTAG interface (default) or Serial Wire (SW)

clock.

[2]

TCK/SWDCLK J5

H2

27

38

I; F

[2]

TRST

M4

K6

B4

C4

29

30

42

44

I; PU I

Test Reset for JTAG interface.

TMS/SWDIO

Test Mode Select for JTAG interface (default) or SW debug

data input/output.

[2]

TDO/SWO

TDI

K5

J4

H3

G3

31

26

46

35

O

Test Data Out for JTAG interface (default) or SW trace output.

Test Data In for JTAG interface.

I; PU I

USB0 pins

USB0_DP

[6]

F2

G2

F1

H2

E1

E2

E3

F1

18

20

21

22

26

28

29

30

-

I/O USB0 bidirectional D+ line. Do not add an external series

resistor.

USB0_DM

USB0_VBUS

USB0_ID

I/O USB0 bidirectional D line. Do not add an external series

resistor.

[6]

[7]

I

VBUS pin (power on USB cable). This pin includes an internal

pull-down resistor of 70 k (typical)  30 k.

[8]

Indicates to the transceiver whether connected as an A-device

(USB0_ID LOW) or B-device (USB0_ID HIGH). For use with

OTG, this pin has an internal pull-up resistor.

[8]

USB0_RREF

H1

F3

24

89

32

-

12.0 k (accuracy 1 %) on-board resistor to ground for current

reference.

USB1 pins

[9]

USB1_DP

F12 E9

129

130

-

I/O USB1 bidirectional D+ line. Add an external series resistor of

33  +/- 2 %.

USB1_DM

G12 E10 90

I/O USB1 bidirectional D line. Add an external series resistor of

33  +/- 2 %.

I²C-bus pins

[10]

I2C0_SCL

L15 D6

L16 E6

92

93

132

133

I; F I/O I²C clock input/output. Open-drain output (for I²C-bus

compliance).

I; F I/O I²C data input/output. Open-drain output (for I²C-bus

compliance).

I2C0_SDA

Reset and wake-up pins

[11]

RESET

D9

B6

128 185

I; IA

I

External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states, and processor execution to begin at address 0. This pin

does not have an internal pull-up.

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[11]

WAKEUP0

WAKEUP1

WAKEUP2

A9

A4

130 187

I; IA

I

External wake-up input; can raise an interrupt and can cause

wake-up from any of the low-power modes. A pulse with a

duration of at least 45 ns wakes up the part.

Input 0 of the event monitor. No internal pull-up is enabled

when this pin is configured as input.

A10

C9

D8

-

External wake-up input; can raise an interrupt and can cause

wake-up from any of the low-power modes. A pulse with a

duration of at least 45 ns wakes up the part.

Input 1 of the event monitor. No internal pull-up is enabled

when this pin is configured as input.

External wake-up input; can raise an interrupt and can cause

wake-up from any of the low-power modes. A pulse with a

duration of at least 45 ns wakes up the part.

Input 2 of the event monitor. This pin does not have an internal

pull-up.

WAKEUP3

External wake-up input; can raise an interrupt and can cause

wake-up from any of the low-power modes. A pulse with a

duration of at least 45 ns wakes up the part. This pin does not

have an internal pull-up.

ADC pins

[8]

ADC0_0/

ADC1_0/DAC

E3

C3

A4

B5

C6

B3

A5

C5

A2

A1

B3

A3

-

6

2

8

4

AI;

IA

I

ADC input channel 0. Shared between 10-bit ADC0/1 and

DAC.

ADC0_1/

ADC1_1

AI;

IA

ADC input channel 1. Shared between 10-bit ADC0/1.

ADC input channel 2. Shared between 10-bit ADC0/1.

ADC input channel 3. Shared between 10-bit ADC0/1.

ADC input channel 4. Shared between 10-bit ADC0/1.

ADC input channel 5. Shared between 10-bit ADC0/1.

ADC input channel 6. Shared between 10-bit ADC0/1.

ADC input channel 7. Shared between 10-bit ADC0/1.

ADC0_2/

ADC1_2

143 206

139 200

138 199

144 208

142 204

136 197

AI;

IA

ADC0_3/

ADC1_3

AI;

IA

ADC0_4/

ADC1_4

AI;

IA

ADC0_5/

ADC1_5

-

AI;

IA

ADC0_6/

ADC1_6

-

AI;

IA

ADC0_7/

ADC1_7

-

AI;

IA

RTC pins

RTC_ALARM

RTCX1

[11]

[8]

A11 C3

129 186

125 182

126 183

-

O

I

RTC controlled output.

A8

B8

B9

A5

B5

-

Input to the RTC 32 kHz ultra-low power oscillator circuit.

Output from the RTC 32 kHz ultra-low power oscillator circuit.

Event monitor sample output.

[8]

RTCX2

-

O

[11]

SAMPLE

-

O

Crystal oscillator pins

[8]

XTAL1

D1

B1

12

18

-

I

Input to the oscillator circuit and internal clock generator

circuits.

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[8]

XTAL2

E1

C1

13

19

-

O

Output from the oscillator amplifier.

Power and ground pins

USB0_VDDA

3V3_DRIVER

F3

G3

H3

G1

B4

D1

D2

D3

F2

B2

16

17

19

23

24

25

27

31

-

Separate analog 3.3 V power supply for driver.

USB 3.3 V separate power supply voltage.

USB0

_VDDA3V3

USB0_VSSA

_TERM

Dedicated analog ground for clean reference for termination

resistors.

USB0_VSSA

_REF

Dedicated clean analog ground for generation of reference

currents and voltages.

VDDA

VBAT

137 198

127 184

-

Analog power supply and ADC reference voltage.

B10 C5

RTC power supply: 3.3 V on this pin supplies power to the

RTC.

VDDREG

F10, E4,

94, 135,

131, 188,

59, 195,

-

Main regulator power supply.

F9,

L8,

L7

E5,

F4

25

82,

33

[12]

VPP

E8

-

OTP programming voltage.

I/O power supply.

VDDIO

D7,

F10, 5,

6,

E12, K5

F7,

F8,

G10,

H10,

J6,

36, 52,

41, 57,

71, 102,

77, 110,

107, 155,

111, 160,

141 202

J7,

K7,

L9,

L10,

N7,

N13

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32-bit ARM Cortex-M3 microcontroller

Table 3.

Pin description …continued

Pin name

Description

[13]

VSS

G9, C8,

H7, D4,

J10, D5,

J11, G8,

-

Ground.

K8

J3,

J6

[13]

VSSIO

C4,

D13,

G6,

G7,

G8,

H8,

H9,

J8,

-

4,

5,

Ground.

40, 56,

76, 109,

109 157

J9,

K9,

K10,

M13,

P7,

P13

VSSA

B2

C2

135 196

-

Analog ground.

[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in

the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA

= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset

without boot code operation.

[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength.

[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V) providing digital I/O

functions with TTL levels, and hysteresis; high drive strength.

[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V) providing high-speed

digital I/O functions with TTL levels and hysteresis.

[5] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;

if VDDIO not present, do not exceed 3.6 V). When configured as an ADC input or DAC output, the pin is not 5 V tolerant. For analog

functionality, disable the digital section of the pad by setting the pin to an input function and by disabling the pull-up resistor through the

corresponding SFSP register.

[6] 5 V tolerant transparent analog pad.

[7] For maximum load C_L= 6.5 F and maximum resistance R_pd= 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS

= 0.2 V when it is no longer driven.

[8] Transparent analog pad. Not 5 V tolerant.

[9] Pad provides USB functions; It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only).

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I²C-bus Fast Mode Plus specification. This pad requires an external pull-up to

provide output functionality. When power is switched off, this pin connected to the I²C-bus is floating and does not disturb the I²C lines.

[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.

[12] On the LQFP208 package, VPP is internally connected to VDDIO.

[13] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane.

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32-bit ARM Cortex-M3 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses allow for concurrent code and data

accesses from different slave ports.

The LPC18S5x/S3x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses

and other bus masters to peripherals. Flexible connections allow different bus masters to

access peripherals that are on different slave ports of the matrix simultaneously.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and low-power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware division,

hardware single-cycle multiply, interruptable/continuable multiple load and store

instructions, automatic state save and restore for interrupts, tightly integrated interrupt

controller with wake-up interrupt controller, and multiple core buses capable of

simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual.

7.3 System Tick timer (SysTick)

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

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7.4 AHB multilayer matrix

TEST/DEBUG

INTERFACE

HIGH-SPEED PHY

ARM

SD/

MMC

CORTEX-M3

DMA

1

ETHERNET

USB0

USB1

LCD

masters

System

bus

I-code D-code

bus

0

bus

slaves

256/512 kB FLASH A

256/512 kB FLASH B

16 kB EEPROM

64 kB ROM

32 kB LOCAL SRAM

40 kB LOCAL SRAM

32 kB AHB SRAM

16 kB AHB SRAM

SPIFI

EXTERNAL

MEMORY

CONTROLLER

AHB REGISTER

INTERFACES,

APB, RTC DOMAIN

PERIPHERALS

AHB MULTILAYER MATRIX

= master-slave connection

002aag544

Fig 6. AHB multilayer matrix master and slave connections

7.5 Nested Vectored Interrupt Controller (NVIC)

The NVIC is part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt

latency and efficient processing of late arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

• On the LPC18S5x/S3x, the NVIC supports 53 vectored interrupts.

• Eight programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

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• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but can have several

interrupt flags. Individual interrupt flags can also represent more than one interrupt

source.

7.6 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event

router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,

Deep-sleep, Power-down, and Deep power-down modes. Individual events can be

configured as edge or level sensitive and can be enabled or disabled in the event router.

The event router can be battery powered.

The following events if enabled in the event router can create a wake-up signal from

sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt:

• External pins WAKEUP0/1/2/3 and RESET

• Alarm timer, RTC (32 kHz oscillator running)

The following events if enabled in the event router can create a wake-up signal from sleep

mode only and/or create an interrupt:

• WWDT, BOD interrupts

• C_CAN0/1 and QEI interrupts

• Ethernet, USB0, USB1 signals

• Selected outputs of combined timers (SCTimer/PWM and timer0/1/3)

Remark: Any interrupt can wake up the ARM Cortex-M3 from sleep mode if enabled in

the NVIC.

7.7 Global Input Multiplexer Array (GIMA)

The GIMA routes signals to event-driven peripheral targets like the SCTimer/PWM,

timers, event router, or the ADCs.

7.7.1 Features

• Single selection of a source.

• Signal inversion.

• Can capture a pulse if the input event source is faster than the target clock.

• Synchronization of input event and target clock.

• Single-cycle pulse generation for target.

7.8 On-chip static RAM

The LPC18S5x/S3x support up to 136 kB SRAM with separate bus master access for

higher throughput and individual power control for low-power operation.

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7.9 On-chip flash memory

The LPC18S5x/S3x contain up to 1 MB of dual-bank flash program memory. With

dual-bank flash memory, the user code can write or erase one flash bank while reading

the other flash bank without interruption. A two-port flash accelerator maximizes the flash

performance.

In-System Programming (ISP) and In-Application Programming (IAP) routines for

programming the flash memory are provided in the Boot ROM.

7.10 EEPROM

The LPC18S5x/S3x contain up to 16 kB of on-chip byte-erasable and byte-programmable

EEPROM memory.

The EEPROM memory is divided into 128 pages. The user can access pages 1 through

127. Page 128 is protected.

7.11 Boot ROM

The internal ROM memory is used to store the boot code of the LPC18S5x/S3x. After a

reset, the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

• The ROM memory size is 64 kB.

• Supports booting from external static memory such as NOR flash, SPI flash, quad SPI

flash, USB0, and USB1.

• Includes API for OTP and AES programming.

• Includes a flexible USB device stack that supports Human Interface Device (HID),

Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.

The default boot source is the flash memory. Several other boot modes are available if

P2_7 is LOW on reset depending on the values of the OTP bits BOOT_SRC. If the OTP

memory is not programmed or the BOOT_SRC bits are all zero, the states of the boot pins

P2_9, P2_8, P1_2, and P1_1 determine the boot mode.

Table 4.

Boot mode when OTP BOOT_SRC bits are programmed

Boot mode BOOT_SRC BOOT_SRC BOOT_SRC BOOT_SRC Description

bit 3

bit 2

bit 1

bit 0

Pin state

USART0

SPIFI

0

The reset state of P1_1, P1_2, P2_8, and P2_9

pins determines the boot source. See Table 5.

0

1

0

1

0

1

0

1

0

1

Enter ISP mode using USART0 functions on pins

P2_0 and P2_1.

Boot from Quad SPI flash connected to the SPIFI

interface using pins P3_3 to P3_8.

EMC 8-bit

EMC 16-bit

EMC 32-bit

Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

Boot from external static memory (such as NOR

flash) using CS0 and a 16-bit data bus.

Boot from external static memory (such as NOR

flash) using CS0 and a 32-bit data bus.

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Table 4.

Boot mode when OTP BOOT_SRC bits are programmed

Boot mode BOOT_SRC BOOT_SRC BOOT_SRC BOOT_SRC Description

bit 3

bit 2

bit 1

bit 0

USB0

0

1

0

1

0

1

0

Boot from USB0.

Boot from USB1.

USB1

SPI (SSP)

Boot from SPI flash connected to the SSP0

interface on P3_3 (function SSP0_SCK), P3_6

(function SSP0_SSEL), P3_7 (function

SSP0_MISO), and P3_8 (function SSP0_MOSI)^[1].

USART3

1

0

1

Enter ISP mode using USART3 functions on pins

P2_3 and P2_4.

[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.

Remark: Pin functions for SPIFI and SSP0 boot are different.

Table 5.

Boot mode when OPT BOOT_SRC bits are zero

Boot mode

Pins

P2_9

LOW

Description

P2_8

P1_2

P1_1

USART0

SPIFI

LOW

LOW Enter ISP mode using USART0 pins

P2_0 and P2_1.

LOW

HIGH

HIGH Boot from Quad SPI flash connected to

the SPIFI interface on P3_3 to P3_8^[1].

EMC 8-bit

LOW Boot from external static memory (such

as NOR flash) using CS0 and an 8-bit

data bus.

EMC 16-bit

EMC 32-bit

LOW

HIGH

LOW

HIGH Boot from external static memory (such

as NOR flash) using CS0 and a 16-bit

data bus.

LOW Boot from external static memory (such

as NOR flash) using CS0 and a 32-bit

data bus.

USB0

LOW

HIGH

LOW

HIGH

HIGH Boot from USB0

LOW Boot from USB1.

USB1

SPI (SSP)

HIGH Boot from SPI flash connected to the

SSP0 interface on P3_3 (function

SSP0_SCK), P3_6 (function

SSP0_SSEL), P3_7 (function

SSP0_MISO), and P3_8 (function

SSP0_MOSI)^[1].

USART3

HIGH

LOW

LOW Enter ISP mode using USART3 pins

P2_3 and P2_4.

[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.

Remark: Pin functions for SPIFI and SSP0 boot are different.

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7.12 Memory mapping

LPC18S5x/S3x

4 GB

0xFFFF FFFF

reserved

0xE010 0000

0xE000 0000

ARM private bus

reserved

0x8800 0000

0x8000 0000

0x7000 0000

0x6000 0000

128 MB SPIFI data

256 MB dynamic external memory DYCS3

256 MB dynamic external memory DYCS2

reserved

0x4400 0000

0x4200 0000

0x4010 2000

peripheral bit band alias region

reserved

0x4010 1000

0x4010 0000

reserved

high-speed GPIO

reserved

0x400F 8000

0x400F 4000

0x2000 0000

0x1F00 0000

0x1E00 0000

0x1D00 0000

0x1C00 0000

0x400F 2000

16 MB static external memory CS3

reserved

0x400F 1000

0x400F 0000

0x400E 0000

0x400D 0000

0x400C 0000

16 MB static external memory CS2

16 MB static external memory CS1

APB peripherals #3

reserved

16 MB static external memory CS0

APB peripherals #2

reserved

0x400B 0000

0x400A 0000

0x4009 0000

0x4008 0000

0x1B08 0000

0x1B04 0000

0x1B00 0000

APB peripherals #1

256 kB flash B

reserved

APB peripherals #0

reserved

0x4006 0000

0x4005 0000

0x4004 0000

0x1A08 0000

0x1A04 0000

0x1A00 0000

clocking/reset peripherals

RTC domain peripherals

reserved

256 kB flash A

reserved

0x4001 2000

0x4000 0000

AHB peripherals

0x1800 0000

0x1400 0000

1 GB

64 MB SPIFI data

reserved

256 MB dynamic external memory DYCS1

128 MB dynamic external memory DYCS0

0x3000 0000

0x2800 0000

0x1041 0000

64 kB ROM

reserved

0x1040 0000

0x1008 A000

0x2400 0000

0x2200 0000

32 MB AHB SRAM bit banding

reserved

32 kB + 8 kB local SRAM

0x1008 0000

0x2004 4000

0x2004 0000

16 kB EEPROM memory

reserved

0x1000 8000

0x1000 0000

0x2001 0000

0x2000 0000

4 x 16 kB AHB SRAM

32 kB local SRAM

local SRAM/flash/SPIFI data/ROM

external static memory banks

0x1000 0000

256 MB shadow memory area

0x0000 0000

0 GB

aaa-016674

Fig 7. LPC18S5x/S3x Memory mapping (overview)

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7.13 One-Time Programmable (OTP) memory

The OTP provides 64 bit+ 256 bit of memory for general-purpose use. 256 bit of OTP

memory are available to store two AES keys in two memory banks. One bank is

encrypted.

7.14 General-Purpose I/O (GPIO)

The LPC18S5x/S3x provides 8 GPIO ports with up to 31 GPIO pins each.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on

reset. The input buffer must be turned on in the system control block SFS register before

the GPIO input can be read.

7.14.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or

level-sensitive GPIO interrupt request.

• Two GPIO group interrupts can be triggered by any pin or pins in each port.

7.15 AHB peripherals

7.15.1 AES encryption/decryption

The hardware AES engine can decode and encode data using the AES algorithm in

conjunction with a 128-bit key.

The AES encryption and decryption features are accessible through the ROM-based AES

API.

7.15.2 Features

• On-chip API support for AES encryption and decryption.

• Two 128-bit OTP memories for AES key storage and customer use.One OTP memory

bank is encrypted.

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• Random number generator (RNG) accessible through AES API.

• Unique ID for each device.

• Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI).

• Secure storage of encryption and decryption keys.

• Support for CMAC hash calculation to authenticate encrypted data.

• AES engine supports the following modes:

– Electronic Code Block (ECB) mode (encryption and decryption) with 128-bit key.

– Cypher Block Chaining (CBC) mode (encryption and decryption) with 128-bit key.

• The AES engine is compliant with the FIPS (Federal Information Processing

Standard) Publication 197, Advanced Encryption Standard (AES).

• Random Number Generator (RNG) is supported by the AES API and passes the

following tests:

– diehard

– FIPS_140-1

– NIST

• Data is processed in little endian mode. This means that the first byte read from flash

is integrated into the AES codeword as least significant byte. The 16th byte read from

flash is the most significant byte of the first AES codeword.

• AES peak engine performance of 0.5 byte/clock cycle.

• DMA transfers supported through the GPDMA.

7.15.3 State Configurable Timer/PWM (SCTimer/PWM) subsystem

The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input

capture operations. The inputs and outputs of the SCTimer/PWM are shared with the

capture and match inputs/outputs of the 32-bit general-purpose counter/timers.

The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In

the two-counter case, in addition to the counter value the following operational elements

are independent for each half:

• State variable.

• Limit, halt, stop, and start conditions.

• Values of Match/Capture registers, plus reload or capture control values.

In the two-counter case, the following operational elements are global to the

SCTimer/PWM, but the last three can use match conditions from either counter:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

7.15.3.1 Features

• Two 16-bit counters or one 32-bit counter.

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• Counters clocked by bus clock or selected input.

• Up counters or up-down counters.

• State variable allows sequencing across multiple counter cycles.

• The following conditions define an event: a counter match condition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state.

• Events control outputs, interrupts, and DMA requests.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected events can limit, halt, start, or stop a counter.

• Supports:

– 8 inputs

– 16 outputs

– 16 match/capture registers

– 16 events

– 32 states

– Match register 0 to 5 support a fractional component for the dither engine

7.15.4 General-Purpose DMA

The DMA controller allows peripheral-to memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral for

master 1, but only memory for master 0.

7.15.4.1 Features

• Eight DMA channels. Each channel can support a unidirectional transfer.

• 16 DMA request lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers are supported.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

• Two AHB bus masters for transferring data. These interfaces transfer data when a

DMA request goes active. Master 1 can access memories and peripherals, master 0

can access memories only.

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• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

• Internal four-word FIFO per channel.

• Supports 8, 16, and 32-bit wide transactions.

• Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.15.5 SPI Flash Interface (SPIFI)

The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM

Cortex-M3 processor with little performance penalty compared to parallel flash devices

with higher pin count.

After a few commands configure the interface at startup, the entire flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Simple sequences of commands handle erasure and

programming.

Many serial flash devices use a half-duplex command-driven SPI protocol for device setup

and initialization and then move to a half-duplex, command-driven 4-bit protocol for

normal operation. Different serial flash vendors and devices accept or require different

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.15.5.1 Features

• Interfaces to serial flash memory in the main memory map.

• Supports classic and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.

• Supports DMA access.

7.15.6 SD/MMC card interface

The SD/MMC card interface supports the following modes:

• Secure Digital memory (SD version 3.0)

• Secure Digital I/O (SDIO version 2.0)

• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)

• Multimedia Cards (MMC version 4.4)

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7.15.7 External Memory Controller (EMC)

Remark: The EMC is available on all LPC18S5x/S3x parts. The following memory bus

widths are supported:

• LBGA256 packages: 32 bit

• TFBGA100 packages: 8 bit

• LQFP208 packages: 16 bit

• LQFP144 packages: 16 bit

The LPC18S5x/S3x EMC is a Memory Controller peripheral offering support for

asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it

can be used as an interface with off-chip memory-mapped devices and peripherals.

Table 6.

Function

A

EMC pinout for different packages

LBGA256

TFBGA100

EMC_A[13:0]

EMC_D[7:0]

EMC_BLS0

EMC_CS0

EMC_OE

LQFP208

LQFP144

EMC_A[23:0]

EMC_D[31:0]

EMC_BLS[3:0]

EMC_CS[3:0]

EMC_OE

EMC_A[23:0]

EMC_D[15:0]

EMC_BLS[1:0]

EMC_CS[1:0]

EMC_OE

EMC_A[15:0]

EMC_D[15:0]

EMC_BLS[1:0]

EMC_CS[1:0]

EMC_OE

D

BLS

CS

OE

WE

EMC_WE

CKEOUT

EMC_

CKEOUT[3:0]

CKEOUT[1:0]

CLK

EMC_CLK[3:0]; EMC_CLK0,

EMC_CLK0,

EMC_CLK3;

EMC_CLK01,

EMC_CLK23

EMC_CLK0,

EMC_CLK3;

EMC_CLK01,

EMC_CLK23

EMC_CLK01,

EMC_CLK23

EMC_CLK3;

EMC_CLK01,

EMC_CLK23

DQMOUT

DYCS

EMC_

DQMOUT[3:0]

-

EMC_

DQMOUT[1:0]

EMC_

DQMOUT[1:0]

EMC_

EMC_DYCS[1:0]

DYCS[3:0]

CAS

RAS

EMC_CAS

EMC_RAS

EMC_CAS

EMC_RAS

EMC_CAS

EMC_RAS

EMC_CAS

EMC_RAS

7.15.7.1 Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and NOR flash,

with or without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16/32 data and 24 address lines-wide static memory support.

• 16-bit and 32-bit wide chip select SDRAM memory support.

• Static memory features include:

– Asynchronous page mode read

– Programmable Wait States

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– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

• Four chip selects for synchronous memory and four chip selects for static memory

devices.

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Software-controlled dynamic memory self-refresh mode.

• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. Those are typically 512 MB, 256 MB, and

128 MB parts.

• Separate reset domains allow auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

7.15.8 High-speed USB Host/Device/OTG interface (USB0)

Remark: USB0 is available on the following parts: LPC185x, LPC183x, LPC182x. USB0

is not available on the LPC181x parts.

The USB OTG module allows the part to connect directly to a USB host such as a PC (in

device mode) or to a USB device in host mode.

7.15.8.1 Features

• On-chip UTMI+ compliant high-speed transceiver (PHY).

• Complies with Universal Serial Bus specification 2.0.

• Complies with USB On-The-Go supplement.

• Complies with Enhanced Host Controller Interface Specification.

• Supports auto USB 2.0 mode discovery.

• Supports all high-speed USB-compliant peripherals.

• Supports all full-speed USB-compliant peripherals.

• Supports software Host Negotiation Protocol (HNP) and Session Request Protocol

(SRP) for OTG peripherals.

• Supports interrupts.

• Supports Start Of Frame (SOF) frame length adjust.

• This module has its own, integrated DMA engine.

• USB interface electrical test software included in ROM USB stack.

7.15.9 High-speed USB Host/Device interface with ULPI (USB1)

Remark: USB1 is available on the following parts: LPC185x and LPC183x. USB1 is not

available on the LPC182x and LPC181x parts.

The USB1 interface can operate as a full-speed USB host/device interface or can connect

to an external ULPI PHY for High-speed operation.

7.15.9.1 Features

• Complies with Universal Serial Bus specification 2.0.

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• Complies with Enhanced Host Controller Interface Specification.

• Supports auto USB 2.0 mode discovery.

• Supports all high-speed USB-compliant peripherals if connected to external ULPI

PHY.

• Supports all full-speed USB-compliant peripherals.

• Supports interrupts.

• Supports Start Of Frame (SOF) frame length adjust.

• This module has its own, integrated DMA engine.

• USB interface electrical test software included in ROM USB stack.

7.15.10 LCD controller

Remark: The LCD controller is only available on parts LPC185x. LCD is not available on

parts LPC183x, LPC182x, and LPC181x.

The LCD controller provides all of the necessary control signals to interface directly to

various color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be operated. The display resolution is selectable and can be up to 1024  768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of

the displayed data) while still supporting many colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other system functions. A built-in FIFO acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time required to operate the display.

7.15.10.1 Features

• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.

• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

• Supports single and dual-panel color STN displays.

• Supports Thin Film Transistor (TFT) color displays.

• Programmable display resolution including, but not limited to: 320  200, 320  240,

640  200, 640  240, 640  480, 800  600, and 1024  768.

• Hardware cursor support for single-panel displays.

• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

• 16 bpp true-color non-palettized for color STN and TFT.

• 24 bpp true-color non-palettized for color TFT.

• Programmable timing for different display panels.

• 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.

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• Frame, line, and pixel clock signals.

• AC bias signal for STN, data enable signal for TFT panels.

• Supports little and big-endian, and Windows CE data formats.

• LCD panel clock can be generated from the peripheral clock, or from a clock input pin.

7.15.11 Ethernet

Remark: The ethernet controller is available on parts LPC185x and LPC183x. Ethernet is

not available on parts LPC182x and LPC181x.

7.15.11.1 Features

• 10/100 Mbit/s

• DMA support

• Power management remote wake-up frame and magic packet detection

• Supports both full-duplex and half-duplex operation

– Supports CSMA/CD Protocol for half-duplex operation.

– Supports IEEE 802.3x flow control for full-duplex operation.

– Optional forwarding of received pause control frames to the user application in

full-duplex operation.

– Back-pressure support for half-duplex operation.

– Automatic transmission of zero-quanta pause frame on deassertion of flow control

input in full-duplex operation.

• Support for IEEE 1588 time stamping and IEEE 1588 advanced time stamping (IEEE

1588-2008 v2).

7.16 Digital serial peripherals

7.16.1 UART

Remark: The LPC18S5x/S3x contain one UART with standard transmit and receive data

lines.

UART1 also provides a full modem control handshake interface and support for

RS-485/9-bit mode allowing both software address detection and automatic address

detection using 9-bit mode.

UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd

can be achieved with any crystal frequency above 2 MHz.

7.16.1.1 Features

• Maximum UART data bit rate of 8 MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

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• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Equipped with standard modem interface signals. This module also provides full

support for hardware flow control (auto-CTS/RTS).

• Support for RS-485/9-bit/EIA-485 mode (UART1).

• DMA support.

7.16.2 USART

Remark: The LPC18S5x/S3x contain three USARTs. In addition to standard transmit and

receive data lines, the USARTs support a synchronous mode and a smart card mode.

The USARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.16.2.1 Features

• Maximum UART data bit rate of 8 MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Support for RS-485/9-bit/EIA-485 mode.

• USART3 includes an IrDA mode to support infrared communication.

• All USARTs have DMA support.

• Support for synchronous mode at a data bit rate of up to 8 Mbit/s.

• Smart card mode conforming to ISO7816 specification

7.16.3 SSP serial I/O controller

Remark: The LPC18S5x/S3x contain two SSP controllers.

The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with

multiple masters and slaves on the bus. Only a single master and a single slave can

communicate on the bus during a given data transfer. The SSP supports full-duplex

transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and

from the slave to the master. In practice, often only one of these data flows carries

meaningful data.

7.16.3.1 Features

• Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s

(master) and 15 Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

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• Master or slave operation

• Eight-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• Connected to the GPDMA

7.16.4 I²C-bus interface

Remark: The LPC18S5x/S3x contain two I²C-bus interfaces.

The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example, an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I²C-bus interface is a

multi-master bus and can be controlled by more than one bus master connected to it.

7.16.4.1 Features

• I²C0 is a standard I²C-bus compliant bus interface with open-drain pins. I²C0 also

supports Fast mode plus with bit rates up to 1 Mbit/s.

• I²C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I²C-bus).

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

• All I²C-bus controllers support multiple address recognition and a bus monitor mode.

7.16.5 I²S interface

Remark: The LPC18S5x/S3x contain two I²S interfaces.

The I²S-bus provides a standard communication interface for digital audio applications.

The I²S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I²S-bus connection has one master, which is

always the master, and one slave. The I²S-bus interface provides a separate transmit and

receive channel, each of which can operate as either a master or a slave.

7.16.5.1 Features

• The interface has separate input/output channels each of which can operate in master

or slave mode.

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• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,

96, 192) kHz.

• Support for an audio master clock.

• Configurable word select period in master mode (separately for I²S-bus input and

output).

• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. The DMA requests are

connected to the GPDMA block.

• Controls include reset, stop and mute options separately for I²S-bus input and I²S-bus

output.

7.16.6 C_CAN

Remark: The LPC18S5x/S3x contain two C_CAN controllers.

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller can build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a high level of reliability.

7.16.6.1 Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

• Provides programmable FIFO mode (concatenation of Message Objects).

• Provides maskable interrupts.

• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

• Provides programmable loop-back mode for self-test operation.

7.17 Counter/timers and motor control

7.17.1 General purpose 32-bit timers/external event counter

Remark: The LPC18S5x/S3x include four 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an externally

supplied clock. It can optionally generate interrupts, generate timed DMA requests, or

perform other actions at specified timer values, based on four match registers. Each

timer/counter also includes two capture inputs to trap the timer value when an input signal

transitions, optionally generating an interrupt.

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7.17.1.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event can also generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• Up to two match registers can be used to generate timed DMA requests.

7.17.2 Motor control PWM

The motor control PWM is a specialized PWM supporting 3-phase motors and other

combinations. Feedback inputs are provided to automatically sense rotor position and use

that information to ramp speed up or down. An abort input causes the PWM to release all

motor drive outputs immediately . At the same time, the motor control PWM is highly

configurable for other generalized timing, counting, capture, and compare applications.

7.17.3 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two signals, the user code can track the position, direction of rotation,

and velocity. In addition, a third channel, or index signal, can be used to reset the position

counter. The quadrature encoder interface decodes the digital pulses from a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In

addition, the QEI can capture the velocity of the encoder wheel.

7.17.3.1 Features

• Tracks encoder position.

• Increments/decrements depending on direction.

• Programmable for 2 or 4 position counting.

• Velocity capture using built-in timer.

• Velocity compare function with “less than” interrupt.

• Uses 32-bit registers for position and velocity.

• Three position-compare registers with interrupts.

• Index counter for revolution counting.

• Index compare register with interrupts.

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• Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

• Digital filter with programmable delays for encoder input signals.

• Can accept decoded signal inputs (clk and direction).

7.17.4 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 32-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the timer

compare function can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.17.4.1 Features

• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.

• 32-bit compare value.

• 32-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This mechanism allows for combinations not possible

with a simple compare.

7.17.5 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.17.5.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2²⁴ 4) in

multiples of T_cy(WDCLK) 4.

• The Watchdog Clock (WDCLK) uses the IRC as the clock source.

7.18 Analog peripherals

7.18.1 Analog-to-Digital Converter

Remark: The LPC18S5x/S3x contain two 10-bit ADCs. All input channels are shared

between ADC0 and ADC1.

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7.18.1.1 Features

• 10-bit successive approximation analog to digital converter.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 to VDDA.

• Sampling frequency up to 400 kSamples/s.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer

outputs 8 or 15, or the PWM output MCOA2.

• Individual result registers for each A/D channel to reduce interrupt overhead.

• DMA support.

7.18.2 Digital-to-Analog Converter (DAC)

7.18.2.1 Features

• 10-bit resolution

• Monotonic by design (resistor string architecture)

• Controllable conversion speed

• Low power consumption

7.19 Peripherals in the RTC power domain

7.19.1 RTC

The Real-Time Clock (RTC) is a set of counters for measuring time when system power is

on, and optionally when it is off. It uses little power when the CPU does not access its

registers, especially in the reduced power modes. A separate 32 kHz oscillator clocks the

RTC. The oscillator produces a 1 Hz internal time reference and is powered by its own

power supply pin, VBAT.

7.19.1.1 Features

• Measures the passage of time to maintain a calendar and clock. Provides seconds,

minutes, hours, day of month, month, year, day of week, and day of year.

• Ultra-low power design to support battery powered systems. Uses power from the

CPU power supply when it is present.

• Dedicated battery power supply pin.

• RTC power supply is isolated from the rest of the chip.

• Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.

• Periodic interrupts can be generated from increments of any field of the time registers.

• Alarm interrupt can be generated for a specific date/time.

7.19.2 Event monitor/recorder

The event monitor/recorder allows recording and creating a time stamp of events related

to the WAKEUP pins. Sensors report changes to the state of the WAKEUP pins, and the

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event monitor/recorder stores records of such events. The event recorder can be

powered by the backup battery.

The event monitor/recorder can monitor the integrity of the device and record any

tampering events.

7.19.2.1 Features

• Supports three digital event inputs in the VBAT power domain.

• An event is defined as a level change at the digital event inputs.

• For each event channel, two timestamps mark the first and the last occurrence of an

event. Each channel also has a dedicated counter tracking the total number of events.

Timestamp values are taken from the RTC.

• Runs in VBAT power domain, independent of system power supply. The

event/recorder/monitor can therefore operate in Deep power-down mode.

• Low power consumption.

• Interrupt available if system is running.

• A qualified event can be used as a wake-up trigger.

• State of event interrupts accessible by software through GPIO.

7.19.3 Alarm timer

The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating

alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00

and asserts an interrupt, if enabled.

The alarm timer is part of the RTC power domain and can be battery powered.

7.20 System control

7.20.1 Configuration registers (CREG)

The following settings are controlled in the configuration register block:

• BOD trip settings

• Oscillator output

• DMA-to-peripheral muxing

• Ethernet mode

• Memory mapping

• Timer/USART inputs

• Enabling the USB controllers

In addition, the CREG block contains the part identification and part configuration

information.

7.20.2 System Control Unit (SCU)

The system control unit determines the function and electrical mode of the digital pins. By

default function 0 is selected for all pins with pull-up enabled. For pins that support a

digital and analog function, the ADC function select registers in the SCU enable the

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analog function.

A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are

located on separate pads and are not controlled through the SCU.

In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that

select the pin interrupts are located in the SCU.

7.20.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be

unrelated in frequency and phase and can have different clock sources within the CGU.

One CGU base clock is routed to the CLKOUT pins. The base clock that generates the

CPU clock is referred to as CCLK.

Multiple branch clocks are derived from each base clock. The branch clocks offer flexible

control for power-management purposes. All branch clocks are outputs of one of two

Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived

from the same base clock are synchronous in frequency and phase.

7.20.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1.5 %

accuracy for T_amb= 0 °C to 85 °C and 3% accuracy for T_amb= -40 °C to 0 °C and T_amb

85 °C to 105 °C.

=

Upon power-up or any chip reset, the LPC18S5x/S3x use the IRC as the clock source.

The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and the

PLL0USB or PLL0AUDIO as needed if an external boot source is selected.

7.20.5 PLL0USB (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

7.20.6 PLL0AUDIO (for audio)

The audio PLL PLL0AUDIO is a general-purpose PLL with a small step size. This PLL

accepts an input clock frequency derived from an external oscillator or internal IRC. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired

output frequency. The output frequency can be set as a multiple of the sampling frequency

f_sto 32f_s, 64f_s, 128  f_s, 256  f_s, 384  f_s, 512  f_sand the sampling frequency f_scan

range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other

frequencies are possible as well using the integrated fractional divider.

7.20.7 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz. This range is possible through an

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additional divider in the loop to keep the CCO within its frequency range while the PLL is

providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,

or 16 to produce the output clock. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset. After reset, software can enable the PLL. The program must

configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a

clock source. The PLL settling time is 100 s.

7.20.8 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals.

7.20.9 Power control

The LPC18S5x/S3x feature several independent power domains to control power to the

core and the peripherals (see Figure 9). The RTC and its associated peripherals (the

alarm timer, the CREG block, the OTP controller, the back-up registers, and the event

router) are located in the RTC power-domain. The main regulator or a battery supply can

power the RTC. A power selector switch ensures that the RTC block is always powered

on.

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LPC18xx

VDDIO

to I/O pads

to core

VSS

REGULATOR

to memories,

peripherals,

oscillators,

PLLs

VDDREG

MAIN POWER DOMAIN

to RTC

ULTRA LOW-POWER

REGULATOR

domain

VBAT

peripherals

RESET

WAKEUP0/1/2/3

RESET/WAKE-UP

to RTC I/O

pads (V

CONTROL

)

ps

BACKUP REGISTERS

REAL-TIME CLOCK

RTCX1

RTCX2

32 kHz

OSCILLATOR

ALARM

ALWAYS-ON/RTC POWER DOMAIN

DAC

VDDA

VSSA

ADC

ADC POWER DOMAIN

OTP

VPP

OTP POWER DOMAIN

USB0_VDDA3V3_DRIVER

USB0_VDDA3V3

USB0

USB0 POWER DOMAIN

002aag305

Fig 9. LPC18S5x/S3x Power domains

The LPC18S5x/S3x support four reduced power modes: Sleep, Deep-sleep, Power-down,

and Deep power-down.

The LPC18S5x/S3x can wake up from Deep-sleep, Power-down, and Deep power-down

modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in

the RTC power domain.

7.20.10 Code security (Code Read Protection - CRP)

CRP enables different levels of security so that access to the on-chip flash and use of the

JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by CRP.

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There are three levels of the Code Read Protection:

• In level CRP1, access to the chip via the JTAG is disabled. Partial flash updates are

allowed (excluding flash sector 0) using a limited set of the ISP commands. This level

is useful when CRP is required and flash field updates are needed. CRP1 does

prevent the user code from erasing all sectors.

• In level CRP2, access to the chip via the JTAG is disabled. Only a full flash erase and

update using a reduced set of the ISP commands is allowed.

• In level CRP3, any access to the chip via the JTAG pins or the ISP is disabled. This

mode also disables the ISP override using P2_7 pin. If necessary, the application

code must provide a flash update mechanism using the IAP calls or using the

reinvoke ISP command to enable flash update via USART0. See Table 5.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

7.21 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

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8. Limiting values

Table 7.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol Parameter Conditions

Min

Max

Unit

V_DD(REG)(3V3)regulator supply voltage on pin VDDREG

(3.3 V)

0.5

3.6

V

V_DD(IO)

input/output supply

voltage

on pin VDDIO

0.5

3.6

V

V_DDA(3V3)

analog supply voltage

(3.3 V)

on pin VDDA

V_BAT

battery supply voltage

on pin VBAT

on pin VPP

0.5

3.6

V

V_prog(pf)

polyfuse programming

voltage

[2]

V_I

input voltage

when V_DD(IO) 2.4 V

0.5

5.5

V

5 V tolerant digital I/O pins

ADC/DAC pins and digital I/O

pins configured for an analog

function

V_DDA(3V3)

USB0 pins USB0_DP;

USB0_DM; USB0_VBUS

0.3

5.2

3.6

5.2

V

USB0 pins USB0_ID;

USB0_RREF

USB1 pins USB1_DP and

USB1_DM

[3]

I_DD

supply current

per supply pin

-

100

mA

I_SS

ground current

I/O latch-up current

per ground pin

I_latch

(0.5V_DD(IO)) < V_I< (1.5V_DD(IO));

T_j< 125 C

[4]

[5]

T_stg

storage temperature

65

+150

1.5

C

P_tot(pack)

total power dissipation

(per package)

based on package heat transfer,

not device power consumption

-

W

V_ESD

electrostatic discharge

voltage

human body model; all pins



2000

V

[1] The following applies to the limiting values:

a) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

9. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T _j= T_amb+ P_D R_{th j – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DD(REG)(3V3)and V_DD(REG)(3V3). The I/O

power dissipation of the I/O pins is often small and many times can be negligible. However

it can be significant in some applications.

Table 8.

Symbol

T_j(max)

Thermal characteristics

Parameter

Min

Typ

Max

Unit

maximum junction

temperature

-

125

C

Table 9.

Thermal resistance (LQFP packages)

Conditions

Symbol Parameter

Thermal resistance in C/W ±15 %

LQFP144

LQFP208

R_th(j-a)

thermal resistance

JEDEC (4.5 in  4 in); still 38

31

from junction to

ambient

air

Single-layer (4.5 in  3 in); 50

still air

39

10

R_th(j-c)

thermal resistance

11

from junction to case

Table 10. Thermal resistance value (BGA packages)

Symbol Parameter Conditions

Thermal resistance in C/W ±15 %

LBGA256

TFBGA100

R_th(j-a)

thermal resistance from JEDEC (4.5 in  4 in); 29

46

junction to ambient

still air

8-layer (4.5 in  3 in); 24

still air

37

11

R_th(j-c)

thermal resistance from

junction to case

14

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

10. Static characteristics

Table 11. Static characteristics

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Supply pins

V_DD(IO)

input/output supply

voltage

2.4

-

3.6

V

[2]

V_DD(REG)(3V3)

V_DDA(3V3)

regulator supply voltage

(3.3 V)

analog supply voltage

(3.3 V)

on pin VDDA

2.4

3.0

-

3.6

V

on pins

3.3

USB0_VDDA3V3_

DRIVER and

USB0_VDDA3V3

[2]

[3]

V_BAT

battery supply voltage

2.4

2.7

-

3.6

V

V_prog(pf)

polyfuse programming on pin VPP (for OTP)

voltage

I_prog(pf)

polyfuse programming on pin VPP; OTP

-

30

mA

current

programming time 

1.6 ms

I_DD(REG)(3V3)

regulator supply current Active mode; code

(3.3 V)

while(1){}

executed from RAM; all

peripherals disabled;

PLL1 enabled

[4]

CCLK = 12 MHz

CCLK = 60 MHz

-

10

28

51

74

-

mA

CCLK = 120 MHz

-

CCLK = 180 MHz

I_DD(REG)(3V3)

regulator supply current all peripherals disabled

(3.3 V)

[4][5]

[4]

sleep mode

-

8.8

-

mA

A

deep-sleep mode

power-down mode

145

23

[4]

[4][6]

deep power-down

mode

0.05

[4]

[7]

deep power-down

mode; VBAT floating

-

3.0

-

A

I_BAT

battery supply current

V_BAT= 3.0 V;

_DD(REG)(3V3)= 3.3 V

0.1

V

Deep power-down mode;

RTC running;

V

_DD(REG)(3V3)floating;

_BAT= 3.3 V

-

3.0

1.5

-

A

V_DD(REG)(3V3)

_BAT= 3.3 V

=

V

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 11. Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

< 0.1

0.4

Max

Unit

A

I_DD(IO)

I/O supply current

deep sleep mode

power-down mode

deep power-down mode

on pin VDDA;

-

A

[9]

I_DDA

Analog supply current

deep sleep mode

power-down mode

A

[9]

-

0.4

-

deep power-down

mode

0.007

A

RESET pin

[8]

V_IH

HIGH-level input

voltage

0.8  (V_ps

0.35)



-

5.5

V

V_IL

LOW-level input voltage

0

0.3  (V_ps

0.1)

V_hys

hysteresis voltage

0.05  (V_ps

 0.35)

-

Standard I/O pins - normal drive strength

C_I

input capacitance

-

2

-

pF

nA

I_LL

LOW-level leakage

current

V_I= 0 V; on-chip pull-up

resistor disabled

3

I_LH

HIGH-level leakage

current

V_I= V_DD(IO); on-chip

pull-down resistor

disabled

-

3

-

nA

V_I= 5 V; T_amb= 25 °C

V_I= 5 V; T_amb= 105 °C

-

0.5

40

3

-

nA

I_OZ

OFF-state output

current

V_O= 0 V to V_DD(IO);

on-chip pull-up/down

resistors disabled;

absolute value

V_I

input voltage

pin configured to provide

a digital function;

0

-

5.5

V

V_DD(IO) 2.4 V

V

_DD(IO)= 0 V

0

-

3.6

V

V_O

output voltage

output active

V_DD(IO)

5.5

V_IH

HIGH-level input

voltage

0.7 

V_DD(IO)

V_IL

LOW-level input voltage

0

-

0.3 

V_DD(IO)

V

V_hys

V_OH

V_OL

I_OH

hysteresis voltage

0.1 

V_DD(IO)

-

V

HIGH-level output

voltage

I_OH= 6 mA

V_DD(IO)

0.4



-

V

LOW-level output

voltage

I_OL= 6 mA

-

0.4

-

V

HIGH-level output

current

V_OH= V_DD(IO) 0.4 V

6

mA

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Table 11. Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_OL

LOW-level output

current

V_OL= 0.4 V

6

-

mA

[10]

I_OHS

I_OLS

I_pd

HIGH-level short-circuit drive HIGH; connected to

output current ground

-

87

77

-

mA

A

LOW-level short-circuit drive LOW; connected to

-

output current

V_DD(IO)

[12]

[13]

[14]

pull-down current

V_I= 5 V

93

[12]

[13]

[14]

I_pu

pull-up current

V_I= 0 V

-

62

-

A

V

_DD(IO)< V_I 5 V

10

A

R_s

series resistance

on I/O pins with analog

function; analog function

enabled

200



I/O pins - high drive strength

C_I

input capacitance

-

5.2

-

pF

nA

I_LL

LOW-level leakage

current

V_I= 0 V; on-chip pull-up

resistor disabled

3

I_OZ

OFF-state output

current

V_O= 0 V to V_DD(IO)

;

-

3

-

nA

on-chip pull-up/down

resistors disabled;

absolute value

V_I

input voltage

pin configured to provide

a digital function;

V_DD(IO) 2.4 V

V_DD(IO)= 0 V

0

-

5.5

V

3.6

V_O

output voltage

output active

V_DD(IO)

5.5

V_IH

HIGH-level input

voltage

0.7 

V_DD(IO)

V_IL

V_hys

I_pd

LOW-level input voltage

hysteresis voltage

pull-down current

0

-

0.3 

V_DD(IO)

V

0.1 

V_DD(IO)

-

V

[12]

[13]

[14]

V_I= V_DD(IO)

-

62

A

[12]

[13]

[14]

I_pu

pull-up current

V_I= 0 V

62

-

A

V

_DD(IO)< V_I 5 V

10

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 11. Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I/O pins - high drive strength: standard drive mode

I_LH

HIGH-level leakage

current

V_I= V_DD(IO); on-chip

pull-down resistor

disabled

-

3

-

nA

V_I= 5 V; T_amb= 25 °C

V_I= 5 V; T_amb= 105 °C

V_OH= V_DD(IO) 0.4 V

-

0.6

65

-

nA

mA

-

I_OH

HIGH-level output

current

4

I_OL

LOW-level output

current

V_OL= 0.4 V

4

-

mA

[10]

I_OHS

I_OLS

HIGH-level short-circuit drive HIGH; connected to

output current ground

32

LOW-level short-circuit drive LOW; connected to

output current V_DD(IO)

-

I/O pins - high drive strength: medium drive mode

I_LH

HIGH-level leakage

current

V_I= V_DD(IO); on-chip

pull-down resistor

disabled

-

3

-

nA

V_I= 5 V; T_amb= 25 °C

V_I= 5 V; T_amb= 105 °C

V_OH= V_DD(IO) 0.4 V

-

0.7

70

-

nA

mA

-

I_OH

HIGH-level output

current

8

I_OL

LOW-level output

current

V_OL= 0.4 V

8

-

mA

[10]

I_OHS

I_OLS

HIGH-level short-circuit drive HIGH; connected to

output current ground

65

63

LOW-level short-circuit drive LOW; connected to

output current V_DD(IO)

-

I/O pins - high drive strength: high drive mode

I_LH

HIGH-level leakage

current

V_I= V_DD(IO); on-chip

pull-down resistor

disabled

-

3

-

nA

V_I= 5 V; T_amb= 25 °C

V_I= 5 V; T_amb= 105 °C

V_OH= V_DD(IO) 0.4 V

-

0.6

63

-

nA

mA

-

I_OH

HIGH-level output

current

14

I_OL

LOW-level output

current

V_OL= 0.4 V

14

-

mA

[10]

I_OHS

I_OLS

HIGH-level short-circuit drive HIGH; connected to

output current ground

113

110

LOW-level short-circuit drive LOW; connected to

output current V_DD(IO)

-

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 11. Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I/O pins - high drive strength: ultra-high drive mode

I_LH

HIGH-level leakage

current

V_I= V_DD(IO); on-chip

pull-down resistor

disabled

-

3

-

nA

V_I= 5 V; T_amb= 25 °C

V_I= 5 V; T_amb= 105 °C

V_OH= V_DD(IO) 0.4 V

-

0.6

63

-

nA

mA

-

I_OH

HIGH-level output

current

20

I_OL

LOW-level output

current

V_OL= 0.4 V

20

-

mA

[10]

I_OHS

I_OLS

HIGH-level short-circuit drive HIGH; connected to

output current ground

165

156

LOW-level short-circuit drive LOW; connected to

-

output current

V_DD(IO)

I/O pins - high-speed

C_I

input capacitance

-

2

-

pF

nA

I_LL

LOW-level leakage

current

V_I= 0 V; on-chip pull-up

resistor disabled

3

I_LH

HIGH-level leakage

current

V_I= V_DD(IO); on-chip

pull-down resistor

disabled

-

3

-

nA

V_I= 5 V; T_amb= 25 °C

V_I= 5 V; T_amb= 105 °C

-

0.5

40

3

-

nA

I_OZ

OFF-state output

current

V_O= 0 V to V_DD(IO);

on-chip pull-up/down

resistors disabled;

absolute value

V_I

input voltage

pin configured to provide

a digital function;

V_DD(IO) 2.4 V

V_DD(IO)= 0 V

0

-

5.5

V

3.6

V_O

output voltage

output active

V_DD(IO)

5.5

V_IH

HIGH-level input

voltage

0.7 

V_DD(IO)

V_IL

LOW-level input voltage

0

-

0.3 

V_DD(IO)

V

V_hys

V_OH

V_OL

I_OH

hysteresis voltage

0.1 

V_DD(IO)

-

V

HIGH-level output

voltage

I_OH= 8 mA

V_DD(IO)

0.4



-

V

LOW-level output

voltage

I_OL= 8 mA

-

0.4

-

V

HIGH-level output

current

V_OH= V_DD(IO) 0.4 V

8

mA

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 11. Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_OL

LOW-level output

current

V_OL= 0.4 V

8

-

mA

[10]

I_OHS

I_OLS

I_pd

HIGH-level short-circuit drive HIGH; connected to

output current ground

-

86

76

-

mA

A

LOW-level short-circuit drive LOW; connected to

-

output current

V_DD(IO)

[12]

[13]

[14]

pull-down current

V_I= V_DD(IO)

62

[12]

[13]

[14]

I_pu

pull-up current

V_I= 0 V

-

62

-

A

V

_DD(IO)< V_I 5 V

0

-

Open-drain I²C0-bus pins

V_IH

HIGH-level input

voltage

0.7 

V_DD(IO)

-

V

V_IL

LOW-level input voltage

0

0.14

0.3 

V_DD(IO)

V_hys

V_OL

I_LI

hysteresis voltage

0.1 

V_DD(IO)

-

LOW-level output

voltage

I_OLS= 3 mA

-

0.4

[11]

input leakage current

V_I= V_DD(IO)

V_I= 5 V

-

4.5

-

A

10

Oscillator pins

V_i(XTAL1)

input voltage on pin

XTAL1

0.5

-

1.2

0.8

V

V_o(XTAL2)

C_io

output voltage on pin

XTAL2

V

[15]

input/output

capacitance

pF

USB0 pins^[16]

V_I

input voltage

on pins USB0_DP;

USB0_DM; USB0_VBUS

V_DD(IO) 2.4 V

V_DD(IO)= 0 V

0

-

5.5

V

0

-

3.6

V

R_pd

V_IC

pull-down resistance

on pin USB0_VBUS

high-speed mode

48

50

800

64

200

-

80

k

mV

common-mode input

voltage

500

2500

full-speed/low-speed

mode

chirp mode

50

-

600

mV

V_i(dif)

differential input voltage

100

400

1100

USB1 pins (USB1_DP/USB1_DM)^[16]

[16]

I_OZ

OFF-state output

current

0 V < V_I< 3.3 V

-

10

A

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 11. Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

V_BUS

V_DI

Parameter

Conditions

Min

-

Typ^[1]

Max

5.25

-

Unit

V

[17]

bus supply voltage

-

differential input

(D+)  (D)

0.2

V

sensitivity voltage

V_CM

differential common

mode voltage range

includes V_DIrange

0.8

-

2.5

2.0

V

V_th(rs)se

single-ended receiver

switching threshold

voltage

V_OL

LOW-level output

voltage for

low-/full-speed

R_Lof 1.5 k to 3.6 V

R_Lof 15 k to GND

-

0.18

3.5

V

V_OH

HIGH-level output

voltage (driven) for

low-/full-speed

2.8

C_trans

Z_DRV

transceiver capacitance pin to GND

-

20

pF

[18]

driver output

with 33  series resistor;

steady state drive

36

44.1



impedance for driver

which is not high-speed

capable

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] The recommended operating condition for the battery supply is V_DD(REG)(3V3)> V_BAT+ 0.2 V. Special conditions for V_DD(REG)(3V3)apply

when writing to the flash and EEPROM. See Table 16 and Table 15.

[3] Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure

the same ramp-up time for both supply voltages.

[4] V_DD(REG)(3V3)= 3.3 V; V_DD(IO)= 3.3 V; T_amb= 25 C.

[5] PLL1 disabled; IRC running; CCLK = 12 MHz.

[6] V_BAT= 3.6 V.

[7] T_amb= -40 C to +105 C; V_DD(IO)= V_DDA= 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz; in active mode, sleep

mode; deep-sleep mode, power-down mode, and deep power-down mode.

[8] V_pscorresponds to the output of the power switch (see Figure 9) which is determined by the greater of V_BATand V_DD(Reg)(3V3)

.

[9] V_DDA(3V3)= 3.3 V; T_amb= 25 C.

[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[11] To V_SS

.

[12] The values specified are simulated and absolute values.

[13] The weak pull-up resistor is connected to the V_DD(IO)rail and pulls up the I/O pin to the V_DD(IO)level.

[14] The input cell disables the weak pull-up resistor when the applied input voltage exceeds V_DD(IO)

[15] The parameter value specified is a simulated value excluding bond capacitance.

[16] For USB operation 3.0 V  V_DD((IO) 3.6 V. Guaranteed by design.

[17] V_DD(IO)present.

.

[18] Includes external resistors of 33   1 % on D+ and D.

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

10.1 Power consumption

aaa-013045

100

I

DD(REG)(3V3)

(mA)

80

60

40

20

180 MHz

120 MHz

60 MHz

12 MHz

3

0

2.2

2.4

2.6

2.8

3.2

3.4

3.6

V

(V)

DD(REG)(3V3)

Conditions: T_amb= 25 C; executing code while (1){} from SRAM; system PLL enabled; IRC

enabled; all peripherals disabled; all peripheral clocks disabled.

Fig 10. Typical supply current versus regulator supply voltage V_DD(REG)(3V3)in active

mode

aaa-013044

100

I

DD(REG)(3V3)

(mA)

80

60

40

20

180 MHz

120 MHz

60 MHz

12 MHz

20

0

-40

-20

0

40

60

80

100

120

temperature (°C)

Conditions: V_DD(REG)(3V3)= 3.3 V; executing code while (1){} from SRAM; internal pull-up resistors

disabled; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks

disabled.

Fig 11. Typical supply current versus temperature in active mode

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aaa-013046

100

DD(REG)(3V3)

(mA)

+105 °C

+90 °C

+25 °C

0 °C

I

80

60

40

20

-40 °C

0

12

36

60

84

108

132

156

180

frequency (MHz)

Conditions: active mode entered executing code while (1){} from SRAM; V_DD(REG)(3V3)= 3.3 V;

system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled.

Fig 12. Typical supply current versus core frequency in active mode; code executed from

SRAM

aaa-013047

20

I

DD(REG)(3V3)

(mA)

15

10

5

0

-40

-20

0

20

40

60

80

100

120

temperature (°C)

Conditions: V_DD(REG)(3V3)= 3.3 V; internal pull-up resistors disabled; system PLL disabled; IRC

enabled; all peripherals disabled; all peripheral clocks disabled. CCLK = 12 MHz.

Fig 13. Typical supply current versus temperature in sleep mode

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002aah410

002aah412

1.6

300

DD(REG)(3V3)

(μA)(μA)

I

DD(REG)(3V3)

(μA) (mA)

240

180

120

60

1.2

0.8

0.4

0

-40

0

40

80

temperature (°C)

120

-40

0

40

80

120

temperature (°C)

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V.

Fig 14. Typical supply current versus temperature in

Deep-sleep mode

Fig 15. Typical supply current versus temperature in

Power-down mode

002aah424

002aah415

25

30

I

/I

IBBAATT

BAT

(μA)

DD(REG)(3V3) BAT

(μA)

25

20

15

10

5

20

15

10

5

IBATT

DD(REG)(3V3)

BAT

I

0

-40 -20

0

20

40

60

80 100 120

-40 -20

0

20

40

60

80 100 120

temperature (°C)

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V. V_BAT

V_DD(REG)(3V3)+ 0.4 V.

=

Conditions: V_BAT= 3.6 V. V_DD(REG)(3V3)not present.

Fig 16. Typical supply current versus temperature in

Deep power-down mode

Fig 17. Typical battery supply current versus

temperature

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002aah379

100

I

BAT

(μA)

80

60

40

20

0

-0.4

-0.2

0

0.2

0.4

0.6

V

BAT

- V

(V)

DD(REG)(3V3)

Conditions: V_DD(REG)(3V3)= 3.0 V; V_BAT= 2.6 V to 3.6 V; CCLK = 12 MHz.

Remark: The recommended operating condition for the battery supply is

V_DD(REG)(3V3)> V_BAT+ 0.2 V.

Fig 18. Typical battery supply current in Active mode

10.2 Peripheral power consumption

The typical power consumption at T = 25 C for each individual peripheral is measured as

follows:

1. Enable all branch clocks and measure the current I_DD(REG)(3V3)

.

2. Disable the branch clock to the peripheral to be measured and keep all other branch

clocks enabled.

3. Calculate the difference between measurement 1 and 2. The result is the peripheral

power consumption.

Table 12. Peripheral power consumption

Peripheral

Branch clock

I_DD(REG)(3V3)in mA

Branch clock

frequency = 48 MHz

frequency = 96 MHz

I2C1

CLK_APB3_I2C1

CLK_APB1_I2C0

CLK_APB3_DAC

CLK_APB3_ADC0

CLK_APB3_ADC1

CLK_APB3_CAN0

CLK_APB1_CAN1

CLK_APB1_MOTOCON

CLK_APB1_I2S

0.01

< 0.01

0.01

0.07

0.17

0.16

0.04

0.09

1.14

0.01

0.02

0.07

0.17

0.15

0.04

0.08

2.29

I2C0

DAC

ADC0

ADC1

CAN0

CAN1

MOTOCON

I2S

SPIFI

CLK_SPIFI,

CLK_M3_SPIFI

GPIO

CLK_M3_GPIO

0.72

1.43

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Table 12. Peripheral power consumption

Peripheral

Branch clock

I_DD(REG)(3V3)in mA

Branch clock

frequency = 48 MHz

frequency = 96 MHz

LCD

CLK_M3_LCD

0.91

1.06

0.24

1.82

2.15

0.43

ETHERNET

UART0

CLK_M3_ETHERNET

CLK_M3_UART0,

CLK_APB0_UART0

UART1

UART2

UART3

CLK_M3_UART1,

CLK_APB0_UART1

0.24

0.26

0.27

0.43

0.5

CLK_M3_UART2,

CLK_APB2_UART2

CLK_M3_USART3,

CLK_APB2_UART3

0.45

TIMER0

TIMER1

TIMER2

TIMER3

SDIO

CLK_M3_TIMER0

CLK_M3_TIMER1

CLK_M3_TIMER2

CLK_M3_TIMER3

0.08

0.09

0.1

0.15

0.19

0.16

1.17

0.08

0.66

CLK_M3_SDIO,

CLK_SDIO

SCTimer/PWM

SSP0

CLK_M3_SCT

0.66

0.13

1.3

CLK_M3_SSP0,

0.23

CLK_APB0_SSP0

SSP1

CLK_M3_SSP1,

0.14

0.27

CLK_APB2_SSP1

DMA

CLK_M3_DMA

CLK_M3_WWDT

CLK_M3_QEI

1.81

0.03

0.28

1.9

3.61

0.09

0.55

3.9

WWDT

QEI

USB0

CLK_M3_USB0,

CLK_USB0

USB1

CLK_M3_USB1,

CLK_USB1

3.02

5.69

RITIMER

EMC

CLK_M3_RITIMER

0.05

3.94

0.1

CLK_M3_EMC,

7.95

CLK_M3_EMC_DIV

SCU

CLK_M3_SCU

0.1

0.21

0.7

CREG

CLK_M3_CREG

CLK_M3_FLASHA

CLK_M3_FLASHB

0.35

1.47

1.4

Flash bank A

Flash bank B

2.97

2.84

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10.3 Electrical pin characteristics

002aah358

-40 °C

+25 °C

+85 °C

+105 °C

002aah359

15

12

9

3.6

3.2

2.8

2.4

2

I

V

OH

(V)

OL

(mA)

-40 °C

+25 °C

+85 °C

+105 °C

6

3

0

0.1

0.2

0.3

0.4

0.5

0.6

0

6

12

18

24

30

36

V

(V)

I

(mA)

OL

OH

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V.

Fig 19. Standard I/O pins; typical LOW level output

current I_OLversus LOW level output voltage

V_OL

Fig 20. Standard I/O pins; typical HIGH level output

voltage V_OLversus HIGH level output current

I_OH

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002aah360

-40 °C

+25 °C

+85 °C

+105 °C

002aah361

15

25

20

15

10

5

-40 °C

I

OL

(mA)

OL

+25 °C

+85 °C

+105 °C

(mA)

12

9

6

3

0

0.1

0.2

0.3

0.4

0.5

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

(V)

V

OL

Conditions:V_DD(REG)(3V3)= V_DD(IO)= 3.3 V;normal-drive;

EHD = 0x0.

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V;

medium-drive; EHD = 0x1.

002aah362

002aah363

40

60

45

30

15

0

-40 °C

I

OL

(mA)

OL

+25 °C

+85 °C

+105 °C

(mA)

+85 °C

+105 °C

32

24

16

8

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

OL

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; high-drive;

EHD = 0x2.

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; ultra

high-drive; EHD = 0x3.

Fig 21. High-drive pins; typical LOW level output current I_OLversus LOW level output voltage V_OL

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002aah364

002aah367

3.6

3.2

2.8

2.4

2

V

OH

(V)

OH

(V)

-40 °C

3.2

2.8

2.4

2

+25 °C

+85 °C

+105 °C

+25 °C

+85 °C

+105 °C

0

4

8

12

16

20

24

0

8

16

24

32

40

48

I

(mA)

I

(mA)

OH

Conditions:V_DD(REG)(3V3)= V_DD(IO)= 3.3 V;normal-drive;

EHD = 0x0.

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V;

medium-drive; EHD = 0x1.

002aah368

002aah369

3.6

3.2

2.8

2.4

2

V

OH

(V)

V

OH

(V)

-40 °C

3.2

2.8

2.4

2

+25 °C

+85 °C

+105 °C

+25 °C

+85 °C

+105 °C

0

16

32

48

64

80

96

0

20

40

60

80

100

120

I

(mA)

I

(mA)

OH

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; high-drive;

EHD = 0x2.

Conditions: V_DD(REG)(3V3)= V_DD(IO)= 3.3 V; ultra

high-drive; EHD = 0x3.

Fig 22. High-drive pins; typical HIGH level output voltage V_OHversus HGH level output current I_OH

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002aah422

20

0

Ipu

pu

(μA)

+105 °CCC

+25 °CC

-40 °CC

-20

-40

-60

-80

0

1

2

3

4

5

VI (V)

Conditions: V_DD(IO)= 3.3 V. Simulated data over process and temperature.

Fig 23. Pull-up current I_puversus input voltage V_I

002aah418

120

Ipd

pd

(μA)

-40 °CC

90

60

30

0

+25 °CC

+105 °CCC

0

1

2

3

4

5

V (V)

I

Conditions: V_DD(IO)= 3.3 V. Simulated data over process and temperature.

Fig 24. Pull-down current I_pdversus input voltage V_I

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10.4 BOD and band gap static characteristics

Table 13. BOD static characteristics^[1]

T_amb= 25 C; simulated values for nominal processing.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 0

assertion

-

2.25

2.33

-

V

de-assertion

interrupt level 1

assertion

-

2.35

2.43

-

V

de-assertion

interrupt level 2

assertion

-

2.95

3.03

-

V

de-assertion

interrupt level 3

assertion

-

3.05

3.13

-

V

de-assertion

reset level 0

assertion

-

1.9

-

V

de-assertion

reset level 1

assertion

1.98

-

2.0

-

V

de-assertion

reset level 2

assertion

2.08

-

2.1

-

V

de-assertion

reset level 3

assertion

2.18

-

2.2

-

V

de-assertion

2.28

[1] Interrupt and reset levels are selected by writing to the BODLV1/2 bits in the control register CREGE0, see

the LPC18xx user manual.

Table 14. Band gap characteristics

V_DDA(3V3)over specified ranges; T_amb= 40 C to +105 C; unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Unit

[1]

V_ref(bg)

band gap reference voltage

0.707

0.745

0.783

mV

[1] Based on characterization, not tested in production.

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11. Dynamic characteristics

11.1 Flash/EEPROM memory

Table 15. Flash characteristics

T_amb= 40 C to +105 C, unless otherwise specified. V_DD(REG)(3V3)= 2.4 V to 3.6 V for read

operations; V_DD(REG)(3V3)= 2.7 V to 3.6 V for erase/program operations.

Symbol Parameter

N_enduendurance

Conditions

Min

Typ

Max

Unit

[1]

sector erase/program

10000

1000

-

cycles

page erase/program; page

in large sector

page erase/program; page

in small sector

10000

-

cycles

t_ret

retention time powered

unpowered

10

-

years

ms

-

t_er

erase time

page, sector, or multiple

consecutive sectors

100

[2]

t_prog

programming

time

-

1

-

ms

[1] Number of erase/program cycles.

[2] Programming times are given for writing 512 bytes from RAM to the flash. Data must be written to the flash

in blocks of 512 bytes.

Table 16. EEPROM characteristics

T_amb= 40 C to +105 C; V_DD(REG)(3V3)= 2.7 V to 3.6 V.

Symbol

f_clk

Parameter

Conditions

Min

Typ

1500

-

Max

Unit

kHz

clock frequency

endurance

800

1600

N_endu

t_ret

100000

-

cycles

years

ns

retention time

T_amb= 40 C to +85 C

85 C < T_amb 105 C

read

20

10

-

t_a

access time

120

1.99

erase/program;

f_clk= 1500 kHz

-

ms

erase/program;

f_clk= 1600 kHz

-

1.87

-

ms

[1]

t_wait

wait time

read; RPHASE1

read; RPHASE2

write; PHASE1

write; PHASE2

write; PHASE3

35

70

20

40

10

-

ns

[1] See the LPC18xx user manual how to program the wait states for the different read (RPHASEx) and erase/program phases (PHASEx)

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11.2 Wake-up times

Table 17. Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep

power-down modes

T_amb= 40 C to +105 C

Symbol Parameter

Conditions

Min

Typ^[1]

3  T_cy(clk)5  T_cy(clk)

Max Unit

[2]

t_wake

wake-up time from Sleep mode

-

ns

from Deep-sleep and

Power-down mode

12

51

s

from Deep power-down mode

after reset

-

200

-

μs

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] T_cy(clk)= 1/CCLK with CCLK = CPU clock frequency.

11.3 External clock for oscillator in slave mode

Remark: The input voltage on the XTAL1/2 pins must be  1.2 V (see Table 11). For

connecting the oscillator to the XTAL pins, also see Section 13.2 and Section 13.4.

Table 18. Dynamic characteristic: external clock

T_amb= 40 C to +105 C; V_DD(IO)over specified ranges.^[1]

Symbol Parameter

Conditions

Min

Max

Unit

MHz

ns

f_osc

oscillator frequency

1

25

T_cy(clk)

t_CHCX

t_CLCX

clock cycle time

clock HIGH time

clock LOW time

40

1000

T_cy(clk) 0.4

T_cy(clk) 0.6

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

t

CHCX

t

CLCX

T

cy(clk)

002aag698

Fig 25. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

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11.4 Crystal oscillator

Table 19. Dynamic characteristic: oscillator

T_amb= 40 C to +105 C; V_DD(IO)over specified ranges; 2.4 V  V_DD(REG)(3V3) 3.6 V.^[1]

Symbol

Low-frequency mode (1-20 MHz)^[5]

t_jit(per)period jitter time

Parameter

Conditions

Min

Typ^[2]

Max

Unit

[3][4]

5 MHz crystal

10 MHz crystal

15 MHz crystal

-

13.2

6.6

-

ps

4.8

High-frequency mode (20 - 25 MHz)^[6]

t_jit(per)

period jitter time

20 MHz crystal

25 MHz crystal

-

4.3

3.7

-

ps

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] Indicates RMS period jitter.

[4] PLL-induced jitter is not included.

[5] Select HF = 0 in the XTAL_OSC_CTRL register.

[6] Select HF = 1 in the XTAL_OSC_CTRL register.

11.5 IRC oscillator

Table 20. Dynamic characteristic: IRC oscillator

2.4 V  V_DD(REG)(3V3) 3.6 V

Symbol Parameter Conditions

Min

Typ^[1]Max

Unit

f_osc(RC)internal RC -40 C  T_amb 0 C

12.0 - 3 %

12.0 - 1.5 %

12.0 12.0 + 3 %

MHz

oscillator

frequency

0 C  T_amb 85 C

12.0 12.0 + 1.5 % MHz

12.0 12.0 + 3 % MHz

85 C  T_amb 105 C 12.0 - 3 %

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

11.6 RTC oscillator

See Section 13.3 for connecting the RTC oscillator to an external clock source.

Table 21. Dynamic characteristic: RTC oscillator

T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V or 2.4 V  V_BAT 3.6 V^[1]

Symbol Parameter

Conditions

Min

Typ^[1]

32.768

280

Max

-

Unit

kHz

nA

f_i

input frequency

-

I_CC(osc)

oscillator supply

current

800

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

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11.7 GPCLKIN

Table 22. Dynamic characteristic: GPCLKIN

T_amb= 25 C; 2.4 V  V_DD(REG)(3V3) 3.6 V

Symbol Parameter

GP_CLKIN input frequency

Min

Typ

Max

Unit

-

25

MHz

11.8 I/O pins

For I/O pins that are configured as input only, there is no limitation on the rise and fall

times.

Table 23. Dynamic characteristic: I/O pins^[1]

T_amb= 40 C to +105 C; 2.7 V  V_DD(IO) 3.6 V.

Symbol Parameter Conditions

Min

Typ

Max Unit

Standard I/O pins - normal drive strength

[2][3]

t_r

t_f

t_r

t_f

rise time

fall time

rise time

fall time

pin configured as output; EHS = 1

pin configured as output; EHS = 0

1.0

0.9

1.9

-

2.5 ns

4.3 ns

4.0 ns

I/O pins - high drive strength

[2][5]

t_r

t_f

t_r

t_f

t_r

t_f

t_r

t_f

rise time

fall time

rise time

fall time

rise time

fall time

rise time

fall time

pin configured as output; standard

drive mode (EHD = 0x0)

4.3

4.7

3.2

2.9

2.5

2.8

2.4

-

7.9 ns

8.7 ns

5.7 ns

5.5 ns

4.9 ns

3.9 ns

4.7 ns

3.4 ns

pin configured as output; standard

drive mode (EHD = 0x0)

pin configured as output; medium

drive mode (EHD = 0x1)

pin configured as output; medium

drive mode (EHD = 0x1)

pin configured as output; high drive

mode (EHD = 0x2)

pin configured as output; high drive

mode (EHD = 0x2)

pin configured as output; ultra-high

drive mode (EHD = 0x3)

pin configured as output; ultra-high

drive mode (EHD = 0x3)

I/O pins - high-speed

[2][3]

t_r

t_f

t_r

t_f

rise time

fall time

rise time

fall time

pin configured as output; EHS = 1

pin configured as output; EHS = 0

350

450

1.0

-

670 ps

730 ps

1.9 ns

2.0 ns

[1] Simulated data.

[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between

80 % and 20 % of the full output signal level.

[3] The slew rate is configured in the system control block in the SFSP registers using the EHS bit. See the

LPC43xx user manual.

[4] C_L= 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.

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[5] The drive modes are configured in the system control block in the SFSP registers using the EHD bit. See

the LPC18xx user manual.

11.9 I²C-bus

Table 24. Dynamic characteristic: I²C-bus pins

T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V.^[1]

Symbol

Parameter

Conditions

Min

Max

100

400

1

Unit

kHz

MHz

ns

f_SCL

SCL clock frequency

Standard-mode

Fast-mode

0

-

Fast-mode Plus

[3][4][5][6]

t_f

fall time

of both SDA and

SCL signals

300

Standard-mode

Fast-mode

20 + 0.1  C_b

300

ns

s

ns

Fast-mode Plus

Standard-mode

Fast-mode

-

120

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

data hold time

4.7

1.3

0.5

4.0

0.6

0.26

0

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

Fast-mode Plus

Standard-mode

Fast-mode

[2][3][7]

[8][9]

t_HD;DAT

0

Fast-mode Plus

Standard-mode

Fast-mode

0

t_SU;DAT

data set-up time

250

100

50

Fast-mode Plus

[1] Parameters are valid over operating temperature range unless otherwise specified. See the I²C-bus specification UM10204 for details.

[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[4] C_b= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[5] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[7] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t_VD;DATor

t_VD;ACKby a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[9] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement t_SU;DAT= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

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t

SU;DAT

f

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 26. I²C-bus pins clock timing

11.10 I²S-bus interface

Table 25. Dynamic characteristics: I²S-bus interface pins

T_amb= 40 C to 105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V; C_L= 20 pF.

Conditions and data refer to I2S0 and I2S1 pins. Simulated values.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

common to input and output

t_r

rise time

-

4

-

ns

t_f

fall time

-

t_WH

pulse width HIGH

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

36

t_WL

pulse width LOW

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

36

-

ns

output

[1]

t_v(Q)

data output valid time on pin I2Sx_TX_SDA

on pin I2Sx_TX_WS

-

4.4

4.3

-

ns

input

[1]

t_su(D)

data input set-up time on pin I2Sx_RX_SDA

on pin I2Sx_RX_WS

-

0

-

ns

0.20

3.7

3.9

t_h(D)

data input hold time

on pin I2Sx_RX_SDA

on pin I2Sx_RX_WS

-

[1] Clock to the I²S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I²S-bus interface

PCLK = BASE_APB1_CLK / 12. I²S clock cycle time T_cy(clk)= 79.2 ns, corresponds to the SCK signal in the

I²S-bus specification.

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T

t

f

t

r

cy(clk)

I2Sx_TX_SCK

t

WL

WH

I2Sx_TX_SDA

I2Sx_TX_WS

t

v(Q)

002aag497

t

v(Q)

Fig 27. I²S-bus timing (transmit)

T

t

f

t

r

cy(clk)

I2Sx_RX_SCK

I2Sx_RX_SDA

I2Sx_RX_WS

t

WL

WH

t

h(D)

su(D)

002aag498

t

su(D)

Fig 28. I²S-bus timing (receive)

11.11 USART interface

Table 26. USART dynamic characteristics

T_amb= 40 C to 105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V; C_L= 20 pF. EHS = 1

for all pins. Simulated values.

Symbol

Parameter

Min

Max

Unit

USART master (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

data input set-up time

26.6

0

-

ns

data input hold time

data output valid time

-

0

10.4

USART slave (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

data input set-up time

2.4

0

-

ns

data input hold time

data output valid time

-

4.3

24.3

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T

cy(clk)

CLK (FES = 1)

CLK (FES = 0)

t

vQ)

v(Q)

START

BIT0

BIT1

TXD

t

su(D) h(D)

BIT1

START

BIT0

RXD

aaa-016717

Fig 29. USART timing

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11.12 SSP interface

Table 27. Dynamic characteristics: SSP pins in SPI mode

T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V; C_L= 20 pF; sampled at 10 % and 90 % of

the signal level; EHS = 1 for all pins. Simulated values.

Symbol Parameter

SSP master

Conditions

Min

Typ

Max

Unit

[1]

T_cy(clk)

clock cycle time

full-duplex mode

1/(25.5  10⁶)

1/(51  10⁶)

-

s

when only transmitting

-

s

t_DS

data set-up time in SPI mode

data hold time in SPI mode

12.2

3.6

-

ns

t_DH

t_v(Q)

-

data output valid in SPI mode

time

6.7

t_h(Q)

t_lead

data output hold in SPI mode

time

1.7

-

ns

lead time

continuous transfer mode

T

_cy(clk)+ 3.3

T_cy(clk)+ 8.2

SPI mode; CPOL = 0;

CPHA = 0

SPI mode; CPOL = 0;

CPHA = 1

0.5  T_cy(clk)+ 3.3 -

T_cy(clk)+ 3.3

0.5  T_cy(clk)+ 8.2 ns

T_cy(clk)+ 8.2 ns

SPI mode; CPOL = 1;

CPHA = 0

-

SPI mode; CPOL = 1;

CPHA = 1

0.5  T_cy(clk)+ 3.3 -

0.5  T_cy(clk)+ 8.2 ns

synchronous serial

frame mode

microwire frame format

T_cy(clk)+ 3.3

-

T_cy(clk)+ 8.2

-

ns

t_lag

lag time

continuous transfer mode

0.5  T_cy(clk)

SPI mode; CPOL = 0;

CPHA = 0

SPI mode; CPOL = 0;

CPHA = 1

T_cy(clk)

-

ns

SPI mode; CPOL = 1;

CPHA = 0

0.5  T_cy(clk)

T_cy(clk)

SPI mode; CPOL = 1;

CPHA = 1

synchronous serial

frame mode

T_cy(clk)

microwire frame format

0.5  T_cy(clk)

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Table 27. Dynamic characteristics: SSP pins in SPI mode

T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V; C_L= 20 pF; sampled at 10 % and 90 % of

the signal level; EHS = 1 for all pins. Simulated values.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

t_d

delay time

continuous transfer mode

-

0.5  T_cy(clk)

-

ns

SPI mode; CPOL = 0;

CPHA = 0

SPI mode; CPOL = 0;

CPHA = 1

-

n/a

-

ns

SPI mode; CPOL = 1;

CPHA = 0

0.5  T_cy(clk)

n/a

SPI mode; CPOL = 1;

CPHA = 1

synchronous serial

frame mode

T_cy(clk)

n/a

microwire frame format

SSP slave

PCLK

Peripheral clock

frequency

-

180

MHz

[2]

T_cy(clk)

t_DS

clock cycle time

1/(11 10⁶)

-

s

data set-up time in SPI mode

data hold time in SPI mode

1.5

2

ns

t_DH

t_v(Q)

data output valid in SPI mode

time

-

[4  (1/PCLK)] + 1 ns

t_h(Q)

t_lead

data output hold in SPI mode

time

4.5

-

ns

lead time

continuous transfer mode

T_cy(clk)

SPI mode; CPOL = 0;

CPHA = 0

SPI mode; CPOL = 0;

CPHA = 1

0.5  T_cy(clk)

T_cy(clk)

-

ns

SPI mode; CPOL = 1;

CPHA = 0

SPI mode; CPOL = 1;

CPHA = 1

0.5  T_cy(clk)

T_cy(clk)

synchronous serial

frame mode

microwire frame format

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Table 27. Dynamic characteristics: SSP pins in SPI mode

T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V; C_L= 20 pF; sampled at 10 % and 90 % of

the signal level; EHS = 1 for all pins. Simulated values.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

t_lag

lag time

continuous transfer mode

0.5 x T_cy(clk)+ 1.5 -

-

ns

SPI mode; CPOL = 0;

CPHA = 0

SPI mode; CPOL = 0;

CPHA = 1

T_cy(clk)+ 1.5

-

ns

SPI mode; CPOL = 1;

CPHA = 0

0.5  T_cy(clk)+ 1.5 -

SPI mode; CPOL = 1;

CPHA = 1

T_cy(clk)+ 1.5

-

synchronous serial

frame mode

microwire frame format

0.5  T_cy(clk)

-

ns

t_d

delay time

continuous transfer mode

-

0.5  T_cy(clk)

SPI mode; CPOL = 0;

CPHA = 0

SPI mode; CPOL = 0;

CPHA = 1

-

n/a

-

ns

SPI mode; CPOL = 1;

CPHA = 0

0.5  T_cy(clk)

n/a

SPI mode; CPOL = 1;

CPHA = 1

synchronous serial

frame mode

T_cy(clk)

n/a

microwire frame format

[1] T_cy(clk)= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f_main. The clock cycle time derived from the SPI bit rate T_cy(clk)is a function of the

main clock frequency f_main, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).

[2] T_cy(clk)12  T_cy(PCLK)

.

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

h(Q)

v(Q)

DATA VALID

CPHA = 1

t

DH

DS

DATA VALID

MISO

t

h(Q)

v(Q)

DATA VALID

t

MOSI

MISO

t

CPHA = 0

DS

DH

DATA VALID

002aae829

Fig 30. SSP master timing in SPI mode

T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

v(Q)

CPHA = 1

DATA VALID

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

CPHA = 0

v(Q)

DATA VALID

002aae830

Fig 31. SSP slave timing in SPI mode

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11.13 External memory interface

Table 28. Dynamic characteristics: Static asynchronous external memory interface

C_L= 22 pF for EMC_Dn C_L= 20 pF for all others; T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V;

2.7 V  V_DD(IO) 3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a

normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses.

Symbol

Read cycle parameters

Parameter^[1]

Conditions

Min

Typ

Max

Unit

t_CSLAV

CS LOW to address valid

time

3.1

-

1.6

ns

[2]

t_CSLOEL

CS LOW to OE LOW time

0.6 + T_cy(clk)

WAITOEN



1.3 + T_cy(clk)

WAITOEN



t_CSLBLSL

t_OELOEH

CS LOW to BLS LOW time PB = 1

OE LOW to OE HIGH time

0.7

-

1.8

ns

0.6 +

0.4 +

(WAITRD 

WAITOEN + 1) 

(WAITRD 

WAITOEN + 1) 

T_cy(clk)

t_am

memory access time

data input hold time

-

16 +

ns

(WAITRD 

WAITOEN +1) 

T_cy(clk)

t_h(D)

16

-

ns

t_CSHBLSHCS HIGH to BLS HIGH time PB = 1

0.4

2.0

1.9

1.4

2.6

0

t_CSHOEH

t_OEHANV

t_CSHEOR

CS HIGH to OE HIGH time

OE HIGH to address invalid PB = 1

[3]

[4]

CS HIGH to end of read

time

t_CSLSOR

CS LOW to start of read

time

0

-

1.8

ns

Write cycle parameters

t_CSLAV

CS LOW to address valid

time

3.1

1.6

1.5

t_CSLDV

CS LOW to data valid time

CS LOW to WE LOW time

-

ns

t_CSLWEL

PB = 1

1.5 +

0.2 +

(WAITWEN + 1)

 T_cy(clk)

(WAITWEN + 1)

 T_cy(clk)

t_CSLBLSL

t_WELWEH

CS LOW to BLS LOW time PB = 1

WE LOW to WE HIGH time PB = 1

0.7

-

1.8

ns

[2]

0.6 +

0.4 +

(WAITWR 

WAITWEN + 1) 

T_cy(clk)

(WAITWR 

WAITWEN + 1) 

T_cy(clk)

t_WEHDNV

WE HIGH to data invalid

time

PB = 1

PB = 0

0.9 + T_cy(clk)

-

2.3 + T_cy(clk)

ns

[2]

[5]

t_WEHEOWWE HIGH to end of write

time

0.4 + T_cy(clk)

0.3 + T_cy(clk)

t_CSLBLSL

CS LOW to BLS LOW

0.7 +

1.8 +

(WAITWEN + 1)

 T_cy(clk)

(WAITWEN + 1)

 T_cy(clk)

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Table 28. Dynamic characteristics: Static asynchronous external memory interface …continued

C_L= 22 pF for EMC_Dn C_L= 20 pF for all others; T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V;

2.7 V  V_DD(IO) 3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a

normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses.

Symbol

Parameter^[1]

Conditions

Min

Typ

Max

Unit

[2]

t_BLSLBLSHBLS LOW to BLS HIGH time PB = 0

0.9 +

-

0.1 +

ns

(WAITWR 

WAITWEN + 1) 

T_cy(clk)

(WAITWR 

WAITWEN + 1) 

T_cy(clk)

[2]

[5]

t_BLSHEOWBLS HIGH to end of write

time

PB = 0

1.9 + T_cy(clk)

2.5 + T_cy(clk)

2.0

-

0.5 + T_cy(clk)

1.4 + T_cy(clk)

0

ns

[2]

t_BLSHDNVBLS HIGH to data invalid

time

[5]

t_CSHEOW

CS HIGH to end of write

time

t_BLSHDNVBLS HIGH to data invalid

time

PB = 1

2.5

1.4

t_WEHANV

WE HIGH to address invalid PB = 1

time

0.9 + T_cy(clk)

2.4 + T_cy(clk)

[1] Parameters specified for 40 % of V_DD(IO)for rising edges and 60 % of V_DD(IO)for falling edges.

[2] T_cy(clk)= 1/CCLK (see LPC18xx User manual).

[3] End Of Read (EOR): longest of t_CSHOEH, t_OEHANV, t_CSHBLSH

[4] Start Of Read (SOR): longest of t_CSLAV, t_CSLOEL, t_CSLBLSL

.

[5] End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH.

EMC_An

t

CSLAV

t

CSHEOW

t

CSLAV

OEHANV

EMC_CSn

EMC_OE

t

CSLOEL

t

OELOEH

t

BLSHEOW

CSHOEH

t

CSLBLSL BLSLBLSH

EMC_BLSn

EMC_WE

t

CSLDV

am

t

CSHEOR

BLSHDNV

t

CSLSOR

t

h(D)

EMC_Dn

EOW

SOR

EOR

002aag699

Fig 32. External static memory read/write access (PB = 0)

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EMC_An

t

CSLAV

t

CSLAV

OEHANV

t

CSHEOW

EMC_CSn

EMC_OE

t

CSLOEL

t

OELOEH

t

CSLBLSL

CSHOEH

t

CSLBLSL

EMC_BLSn

EMC_WE

t

CSHBLSH

t

CSLWEL WELWEH

t

WEHEOW

t

BLSHDNV

am

t

CSHEOR

t

CSLDV

t

h(D)

WEHDNV

t

CSLSOR

EMC_Dn

EOR

SOR

EOW

002aag700

Fig 33. External static memory read/write access (PB = 1)

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Table 29. Dynamic characteristics: Dynamic external memory interface

Simulated data over temperature and process range; C_L= 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE,

EMC_An; C_L= 9 pF for EMC_Dn; C_L= 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; T_amb= 40 C to +105 C;

2.4 V  V_DD(REG)(3V3) 3.6 V; V_DD(IO)=3.3 V  10 %; RD = 1 (see LPC18xx User manual); EMC_CLKn delays CLK0_DELAY

= CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.

Symbol

Parameter

Min

Typ

Max

Unit

T_cy(clk)

clock cycle time

8.4

-

ns

Common to read and write cycles

t_d(DYCSV)

t_h(DYCS)

t_d(RASV)

t_h(RAS)

dynamic chip select valid delay time

-

3.1 + 0.5  T_cy(clk)

5.1 + 0.5  T_cy(clk)ns

ns

4.9 + 0.5  T_cy(clk)ns

ns

4.6 + 0.5  T_cy(clk)ns

ns

5.9 + 0.5  T_cy(clk)ns

ns

5.0 + 0.5  T_cy(clk)ns

ns

6.3 + 0.5  T_cy(clk)ns

ns

5.1 + 0.5  T_cy(clk)ns

dynamic chip select hold time

row address strobe valid delay time

row address strobe hold time

column address strobe valid delay time

column address strobe hold time

write enable valid delay time

write enable hold time

0.3 + 0.5  T_cy(clk)0.9 + 0.5  T_cy(clk)

3.1 + 0.5  T_cy(clk)

0.5 + 0.5  T_cy(clk)1.1 + 0.5  T_cy(clk)

2.9 + 0.5  T_cy(clk)

0.3 + 0.5  T_cy(clk)0.9 + 0.5  T_cy(clk)

3.2 + 0.5  T_cy(clk)

1.3 + 0.5  T_cy(clk)1.4 + 0.5  T_cy(clk)

3.1 + 0.5  T_cy(clk)

0.2 + 0.5  T_cy(clk)0.8 + 0.5  T_cy(clk)

3.8 + 0.5  T_cy(clk)

0.3 + 0.5  T_cy(clk)0.9 + 0.5  T_cy(clk)

-

t_d(CASV)

t_h(CAS)

t_d(WEV)

t_h(WE)

-

t_d(DQMOUTV)DQMOUT valid delay time

-

t_h(DQMOUT)

t_d(AV)

DQMOUT hold time

address valid delay time

address hold time

-

t_h(A)

-

t_d(CKEOUTV)CKEOUT valid delay time

t_h(CKEOUT)CKEOUT hold time

Read cycle parameters

t_su(D)data input set-up time

t_h(D)data input hold time

Write cycle parameters

t_d(QV)data output valid delay time

t_h(Q)data output hold time

-

3.1 + 0.5  T_cy(clk)

0.7 + 0.5  T_cy(clk)

0.5  T_cy(clk)

-

ns

1.5

0.5

-

ns

2.2

0.8

-

3.8 + 0.5  T_cy(clk)

0.7 + 0.5  T_cy(clk)

6.2 + 0.5  T_cy(clk)ns

ns

0.5  T_cy(clk)

-

Table 30. Dynamic characteristics: Dynamic external memory interface; EMC_CLK[3:0]

delay values

T_amb= 40 C to 105 C; V_DD(IO)=3.3 V  10 %; 2.4 V  V_DD(REG)(3V3) 3.6 V.

Symbol Parameter

t_ddelay time

Conditions

delay value

Min

Typ

Max

Unit

[1]

CLKn_DELAY = 0

CLKn_DELAY = 1

CLKn_DELAY = 2

CLKn_DELAY = 3

CLKn_DELAY = 4

CLKn_DELAY = 5

CLKn_DELAY = 6

CLKn_DELAY = 7

0.0

0.4

0.7

1.1

1.4

1.7

2.1

2.5

0.0

0.5

1.0

1.6

2.0

2.6

3.1

3.6

0.0

0.8

1.7

2.5

3.3

4.1

4.9

5.8

ns

[1]

[1] Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC18xx User manual).

The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY =

CLK2_DELAY = CLK3_DELAY.

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EMC_CLKn

delay > 0

EMC_CLKn delay t ; programmable CLKn_DELAY

d

T

cy(clk)

EMC_CLKn

delay = 0

t

- t

d

t

- t

d

d(xV)

h(x)

t

EMC_DYCSn,

EMC_RAS,

d(xV)

h(x)

EMC_CAS,

EMC_WE,

EMC_CKEOUTn,

EMC_A[22:0],

EMC_DQMOUTn

t

- t

d

t

- t

d

d(QV)

h(Q)

t

d(QV)

t

h(Q)

EMC_D[31:0]

write

t

su(D)

h(D)

EMC_D[31:0]

read; delay > 0

t

su(D)

h(D)

EMC_D[31:0]

read; delay = 0

002aag703

For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 30.

Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK

register.

Fig 34. SDRAM timing

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11.14 USB interface

Table 31. Dynamic characteristics: USB0 and USB1 pins (full-speed)

C_L= 50 pF; R_pu= 1.5 k on D+ to V_DD(IO), unless otherwise specified; 3.0 V  V_DD(IO) 3.6 V.

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

t_r/ t_f

Min

8.5

7.7

-

Typ

Max

13.8

13.7

109

Unit

ns

t_r

-

t_f

ns

t_FRFM

differential rise and fall time

matching

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

1.3

160

2

-

2.0

175

+5

V

t_FEOPT

t_FDEOP

see Figure 35

ns

source jitter for differential transition see Figure 35

to SE0 transition

t_JR1

receiver jitter to next transition

18.5

9

-

+18.5

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

+9

-

[1]

t_EOPR1

must reject as

EOP; see

Figure 35

40

t_EOPR2

EOP width at receiver

must accept as

EOP; see

82

-

ns

Figure 35

[1] Characterized but not implemented as production test. Guaranteed by design.

T

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × T

+ t

PERIOD

FDEOP

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 35. Differential data-to-EOP transition skew and EOP width

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Table 32. Static characteristics: USB0 PHY pins^[1]

Symbol Parameter

High-speed mode

Conditions

Min

Typ

Max

Unit

[2]

[3]

P_cons

power consumption

-

68

-

mW

I_DDA(3V3)analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;

total supply current

during transmit

-

18

31

14

7

-

mA

during receive

with driver tri-stated

I_DDD

Full-speed/low-speed mode

P_conspower consumption

digital supply current

[2]

-

15

-

mW

I_DDA(3V3)analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;

total supply current

during transmit

-

3.5

5

-

mA

during receive

3

with driver tri-stated

3

I_DDD

digital supply current

3

Suspend mode

I_DDA(3V3)analog supply current (3.3 V)

-

24

3

-

A

mA

A

with driver tri-stated

with OTG functionality enabled

I_DDD

digital supply current

30

VBUS detector outputs

V_th

threshold voltage

hysteresis voltage

for VBUS valid

for session end

for A valid

4.4

0.2

0.8

2

-

V

-

0.8

2

V

-

V

for B valid

-

4

V

V_hys

for session end

A valid

-

150

200

10

mV

-

B valid

-

[1] Characterized but not implemented as production test.

[2] Total average power consumption.

[3] The driver is active only 20 % of the time.

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11.15 Ethernet

Table 33. Dynamic characteristics: Ethernet

T_amb= 40 C to +105 C, 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V. Values guaranteed

by design.

Symbol Parameter

RMII mode

Conditions

Min

Max

Unit

[1]

f_clk

_clk

t_su

clock frequency for ENET_RX_CLK

clock duty cycle

-

50

-

MHz

%

[1]

50

4

[1][2]

set-up time

for ENET_TXDn, ENET_TX_EN,

ns

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

t_h

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

2

-

ns

MII mode

[1]

f_clk

_clk

t_su

clock frequency for ENET_TX_CLK

clock duty cycle

-

25

50

-

MHz

%

[1]

50

4

[1][2]

set-up time

for ENET_TXDn, ENET_TX_EN,

ns

ENET_TX_ER

[1][2]

t_h

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

2

-

ns

[1]

f_clk

_clk

t_su

clock frequency for ENET_RX_CLK

clock duty cycle

-

25

50

-

MHz

%

[1]

50

4

[1][2]

set-up time

for ENET_RXDn, ENET_RX_ER,

ns

ENET_RX_DV

[1][2]

t_h

hold time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

2

-

ns

[1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input

capacitance of the receiving device.

[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or

output level.

ENET_RX_CLK

ENET_TX_CLK

t

su

t

h

ENET_RXD[n]

ENET_RX_DV

ENET_RX_ER

ENET_TXD[n]

ENET_TX_EN

ENET_TX_ER

002aag210

Fig 36. Ethernet timing

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11.16 SD/MMC

Table 34. Dynamic characteristics: SD/MMC

T_amb= 40 C to +105 C, 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V, C_L= 20 pF.

Simulated values. SAMPLE_DELAY = 0x8, DRV_DELAY = 0xF in the SDDELAY register (see the

LPC18xx user manual UM10430).

Symbol Parameter

Conditions

Min

-

Max Unit

f_clk

clock frequency

on pin SD_CLK; data transfer mode

on pins SD_DATn as inputs

on pins SD_CMD as inputs

on pins SD_DATn as inputs

on pins SD_CMD as inputs

on pins SD_DATn as outputs

on pins SD_CMD as outputs

on pins SD_DATn as outputs

on pins SD_CMD as outputs

52

-

MHz

ns

t_su(D)

data input set-up time

-5.2

7

-

ns

t_h(D)

data input hold time

0.2

1

-

ns

t_d(QV)

data output valid delay

time

15.7 ns

15.9 ns

-

t_h(Q)

data output hold time

3.5

-

ns

T

cy(clk)

SD_CLK

t

h(Q)

d(QV)

SD_CMD (O)

SD_DATn (O)

t

su(D)

h(D)

SD_CMD (I)

SD_DATn (I)

002aag204

Fig 37. SD/MMC timing

11.17 LCD

Table 35. Dynamic characteristics: LCD

T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V; C_L= 20 pF.

Simulated values.

Symbol Parameter

Conditions

Min

Typ

50

-

Max Unit

f_clk

clock frequency

on pin LCD_DCLK

-

MHz

ns

t_d(QV)

data output valid

delay time

17

t_h(Q)

data output hold time

8.5

-

ns

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11.18 SPIFI

32-bit ARM Cortex-M3 microcontroller

Table 36. Dynamic characteristics: SPIFI

T_amb= 40 C to +105 C; 2.4 V  V_DD(REG)(3V3) 3.6 V; 2.7 V  V_DD(IO) 3.6 V. C_L=20 pF.

Sampled at 90 % and 10 % of the signal level. EHS = 1 for all pins. Simulated values.

Symbol

T_cy(clk)

t_DS

Parameter

Min

9.6

3.2



Max

Unit

ns

clock cycle time

data set-up time

data hold time

-

ns

t_DH

-

ns

t_v(Q)

data output valid time

data output hold time

-

3.2

-

ns

t_h(Q)

0.6

ns

T

cy(clk)

SPIFI_SCK

t

h(Q)

v(Q)

DATA VALID

SPIFI data out

SPIFI data in

t

DH

DS

DATA VALID

002aah409

Fig 38. SPIFI timing (Mode 0)

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12. ADC/DAC electrical characteristics

Table 37. ADC characteristics

V_DDA(3V3)over specified ranges; T_amb= 40 C to +105 C; unless otherwise specified.

Symbol Parameter

Conditions

Min Typ

Max

Unit

V

V_IA

C_ia

E_D

analog input voltage

0

-

V_DDA(3V3)

analog input capacitance

differential linearity error

-

2

-

pF

[1][2]

[3]

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

see Figure 40

0.8

1.0

0.8

1.5

0.15

0.3

0.35

3

LSB

%

E_L(adj)

integral non-linearity

offset error

[4]

E_O

[5]

E_G

gain error

%

[6]

E_T

absolute error

LSB

k

4

R_vsi

R_i

voltage source interface

resistance

-

1/(7  f_clk(ADC)

C_ia)

[7][8]

input resistance

-

1.2

4.5

400

M

f_clk(ADC)ADC clock frequency

f_ssampling frequency

MHz

10-bit resolution; 11 clock

cycles

kSamples/s

2-bit resolution; 3 clock

cycles

1.5

MSamples/s

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 39.

[3] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 39.

[4] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 39.

[5] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 39.

[6] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 39.

[7] T_amb= 25 C.

[8] Input resistance R_idepends on the sampling frequency fs: R_i= 2 k + 1 / (f_s C_ia).

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offset

error

gain

error

E

G

O

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

offset error

E

O

V

− V

SSA

DDA(3V3)

1 LSB =

1024

002aaf959

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 39. 10-bit ADC characteristics

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R

vsi

LPC18xx

2 kΩ (analog pin)

2.2 kΩ (multiplexed pin)

ADC0_n/ADC1_n

R

s

ADC

COMPARATOR

C

= 2 pF

ia

V

EXT

V

SS

002aag697

R_s< 1/((7  f_clk(ADC) C_ia)  2 k

Fig 40. ADC interface to pins

Table 38. DAC characteristics

V_DDA(3V3)over specified ranges; T_amb= 40 C to +105 C; unless otherwise specified

Symbol Parameter

Conditions

Min

Typ

Max

Unit

LSB

[1]

E_D

differential linearity error 2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

-

0.8

1.0

-

E_L(adj)

integral non-linearity

code = 0 to 975

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

2.7 V  V_DDA(3V3) 3.6 V

2.4 V  V_DDA(3V3)< 2.7 V

-

1

1.5

0.8

1.0

0.3

1.0

-

LSB

%

[1]

E_O

E_G

offset error

gain error

-

%

C_L

R_L

t_s

load capacitance

load resistance

settling time

200

-

pF

-

k

s

[1]

0.4

[1] In the DAC CR register, bit BIAS = 0 (see the LPC18xx user manual).

[2] Settling time is calculated within 1/2 LSB of the final value.

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13. Application information

13.1 LCD panel signal usage

Table 39. LCD panel connections for STN single panel mode

External pin

4-bit mono STN single panel

8-bit mono STN single panel

Color STN single panel

LPC18xx pin

used

LCD function LPC18xx pin

LCD function

LPC18xx pin

used

LCD function

used

LCD_VD[23:8]

LCD_VD7

LCD_VD6

LCD_VD5

LCD_VD4

LCD_VD3

LCD_VD2

LCD_VD1

LCD_VD0

LCD_LP

-

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

P4_4

P4_1

P7_6

P4_6

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

UD[2]

UD[1]

UD[0]

LCDLP

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

P4_4

P4_1

P7_6

P4_6

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

UD[2]

UD[1]

UD[0]

LCDLP

-

P4_2

P4_3

P4_4

P4_1

P7_6

P4_6

UD[3]

UD[2]

UD[1]

UD[0]

LCDLP

LCD_ENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCD_FP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

LCD_DCLK

LCD_LE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCD_PWR

GP_CLKIN

CDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

Table 40. LCD panel connections for STN dual panel mode

External pin

4-bit mono STN dual panel

8-bit mono STN dual panel

Color STN dual panel

LPC18xx pin

used

LCD function LPC18xx pin

LCD function

LPC18xx pin

used

LCD function

used

LCD_VD[23:16]

LCD_VD15

LCD_VD14

LCD_VD13

LCD_VD12

LCD_VD11

LCD_VD10

LCD_VD9

LCD_VD8

LCD_VD7

LCD_VD6

LCD_VD5

LCD_VD4

LCD_VD3

-

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

P4_8

P7_5

LD[7]

LD[6]

LD[5]

LD[4]

LD[3]

LD[2]

LD[1]

LD[0]

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

P4_8

P7_5

P8_4

P8_5

P8_6

P8_7

P4_2

LD[7]

LD[6]

LD[5]

LD[4]

LD[3]

LD[2]

LD[1]

LD[0]

UD[7]

UD[6]

UD[5]

UD[4]

UD[3]

-

P4_9

LD[3]

P4_10

LD[2]

P4_8

LD[1]

P7_5

LD[0]

-

P8_5

P8_6

P8_7

P4_2

-

P4_2

UD[3]

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Table 40. LCD panel connections for STN dual panel mode

External pin

4-bit mono STN dual panel

8-bit mono STN dual panel

Color STN dual panel

LPC18xx pin

used

LCD function LPC18xx pin LCD function

LPC18xx pin

used

LCD function

used

P4_3

P4_4

P4_1

P7_6

P4_6

LCD_VD2

LCD_VD1

LCD_VD0

LCD_LP

P4_3

P4_4

P4_1

P7_6

P4_6

UD[2]

UD[1]

UD[0]

LCDLP

UD[2]

UD[1]

UD[0]

LCDLP

P4_3

P4_4

P4_1

P7_6

P4_6

UD[2]

UD[1]

UD[0]

LCDLP

LCD_ENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCDENAB/

LCDM

LCD_FP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

P4_5

P4_7

P7_0

P7_7

PF_4

LCDFP

LCD_DCLK

LCD_LE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCD_PWR

GP_CLKIN

LCDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

LCDPWR

LCDCLKIN

Table 41. LCD panel connections for TFT panels

External

TFT 12 bit (4:4:4

mode)

TFT 16 bit (5:6:5 mode)

TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC18xx LCD

LPC18xx

pin used

LCD

function

LPC18xxpin LCD

LPC18xx

pin used

LCD

function

pin used

function

used

PB_0

PB_1

PB_2

PB_3

P7_1

P7_2

-

function

LCD_VD23 PB_0

LCD_VD22 PB_1

LCD_VD21 PB_2

LCD_VD20 PB_3

BLUE3

PB_0

PB_1

PB_2

PB_3

P7_1

-

BLUE4

BLUE3

BLUE2

BLUE1

BLUE0

-

BLUE4

BLUE3

BLUE2

BLUE1

BLUE0

intensity

-

BLUE7

BLUE6

BLUE5

BLUE4

BLUE3

BLUE2

BLUE1

BLUE0

GREEN7

GREEN6

GREEN5

GREEN4

GREEN3

GREEN2

GREEN1

GREEN0

RED7

BLUE2

BLUE1

BLUE0

LCD_VD19

LCD_VD18

LCD_VD17

LCD_VD16

-

P7_3

P7_4

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

P4_8

P7_5

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

P4_4

-

LCD_VD15 PB_4

LCD_VD14 PB_5

LCD_VD13 PB_6

LCD_VD12 P8_3

GREEN3

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

-

GREEN5

GREEN4

GREEN3

GREEN2

GREEN1

GREEN0

-

PB_4

PB_5

PB_6

P8_3

P4_9

P4_10

-

GREEN4

GREEN3

GREEN2

GREEN1

GREEN0

intensity

-

GREEN2

GREEN1

GREEN0

LCD_VD11

LCD_VD10

LCD_VD9

LCD_VD8

LCD_VD7

LCD_VD6

LCD_VD5

LCD_VD4

LCD_VD3

LCD_VD2

LCD_VD1

-

P8_4

RED3

P8_4

P8_5

P8_6

P8_7

P4_2

-

RED4

RED3

RED2

RED1

RED0

-

P8_4

P8_5

P8_6

P8_7

P4_2

P4_3

-

RED4

RED3

RED2

RED1

RED0

intensity

-

P8_5

RED2

RED6

P8_6

RED1

RED5

P8_7

RED0

RED4

-

RED3

RED2

-

RED1

LPC18S5X_S3X

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LPC18S5x/S3x

NXP Semiconductors

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Table 41. LCD panel connections for TFT panels

External

TFT 12 bit (4:4:4

mode)

TFT 16 bit (5:6:5 mode)

TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC18xx LCD

LPC18xx

pin used

LCD

function

LPC18xxpin LCD

LPC18xx

pin used

LCD

function

pin used

function

used

function

LCD_VD0

LCD_LP

-

P4_1

P7_6

RED0

P7_6

LCDLP

P7_6

LCDLP

P7_6

LCDLP

LCD_ENAB P4_6

/LCDM

LCDENAB/ P4_6

LCDM

LCDENAB/ P4_6

LCDM

LCDENAB/ P4_6

LCDM

LCDENAB/

LCDM

LCD_FP

LCD_DCLK P4_7

LCD_LE P7_0

P4_5

LCDFP

LCDDCLK P4_7

LCDLE P7_0

P4_5

LCDFP

P4_5

P4_7

P7_0

P7_7

LCDFP

LCDDCLK P4_7

LCDLE P7_0

P4_5

LCDFP

LCDDCLK

LCDLE

LCDDCLK

LCDLE

LCD_PWR P7_7

GP_CLKIN PF_4

LCDPWR P7_7

LCDCLKIN PF_4

LCDPWR

LCDPWR P7_7

LCDCLKIN PF_4

LCDPWR

LCDCLKIN

LCDCLKIN PF_4

13.2 Crystal oscillator

The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see

LPC18xx user manual).

The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL.

The oscillator can operate in one of two modes: slave mode and oscillation mode.

• In slave mode, couple the input clock signal with a capacitor of 100 pF (C_Cin

Figure 41), with an amplitude of at least 200 mV (RMS). The XTAL2 pin in this

configuration can be left unconnected.

• External components and models used in oscillation mode are shown in Figure 42,

and in Table 42 and Table 43. Since the feedback resistance is integrated on chip,

only a crystal and the capacitances CX1 and CX2 need to be connected externally in

case of fundamental mode oscillation (L, CL and RS represent the fundamental

frequency). Capacitance C_Pin Figure 42 represents the parallel package capacitance

and must not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the

crystal manufacturer.

Table 42. Recommended values for C_X1/X2in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency

Maximum crystal series

resistance R_S

External load capacitors

_X1, C_X2

C

2 MHz

4 MHz

8 MHz

< 200 

33 pF, 33 pF

39 pF, 39 pF

56 pF, 56 pF

18 pF, 18 pF

39 pF, 39 pF

56 pF, 56 pF

18 pF, 18 pF

39 pF, 39 pF

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Product data sheet

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LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 42. Recommended values for C_X1/X2in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency

Maximum crystal series

resistance R_S

External load capacitors

_X1, C_X2

C

12 MHz

16 MHz

20 MHz

< 160 

< 120 

< 80 

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

33 pF, 33 pF

18 pF, 18 pF

33 pF, 33 pF

< 100 

< 80 

Table 43. Recommended values for C_X1/X2in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation

frequency

Maximum crystal series

resistance R_S

External load capacitors C_X1

C_X2

,

15 MHz

20 MHz

< 80 

< 100 

18 pF, 18 pF

39 pF, 39 pF

47 pF, 47 pF

LPC1xxx

XTAL1

C

i

C

g

100 pF

002aae835

Fig 41. Slave mode operation of the on-chip oscillator

LPC18xx

L

XTAL1

XTAL2

C

L

C

P

=

XTAL

R

S

C

X2

C

X1

002aag031

Fig 42. Oscillator modes with external crystal model used for C_X1/C_X2evaluation

LPC18S5X_S3X

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Product data sheet

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133 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

13.3 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances C_RTCX1and

C_RTCX2need to be connected externally. Typical capacitance values for C_RTCX1and

C_RTCX2are C_RTCX1/2= 20 (typical)  4 pF.

An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended

amplitude of the clock signal is V_i(RMS)= 100 mV to 200 mV with a coupling capacitance of

5 pF to 10 pF.

LPC18xx

RTCX1

RTCX2

XTAL

C

RTCX2

RTCX1

002aah066

Fig 43. RTC 32 kHz oscillator circuit

13.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines

Connect the crystal on the PCB as close as possible to the oscillator input and output pins

of the chip. Take care that the load capacitors C_X1, C_X2, and C_X3in case of third overtone

crystal usage have a common ground plane. Also connect the external components to the

ground plain. To keep the noise coupled in via the PCB as small as possible, make loops

and parasitics as small as possible. Choose smaller values of C_X1and C_X2if parasitics

increase in the PCB layout.

Ensure no high-speed or high-drive signals are near the RTCX1/2 signals.

13.5 Standard I/O pin configuration

Figure 44 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver enabled/disabled

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Digital input: Input buffer enabled/disabled

• Analog input

The default configuration for standard I/O pins is input buffer disabled and pull-up

enabled. The weak MOS devices provide a drive capability equivalent to pull-up and

pull-down resistors.

LPC18S5X_S3X

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Product data sheet

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134 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

VDDIO

ESD

enable output driver

data output from core

slew rate bit EHS

input buffer enable bit EZI

data input to core

glitch

filter

filter select bit ZIF

pull-up enable bit EPUN

ESD

pull-down enable bit EPD

analog I/O

VSSIO

002aah028

The glitch filter rejects pulses of typical 12 ns width.

Fig 44. Standard I/O pin configuration with analog input

13.6 Reset pin configuration

V

ps

V

ps

V

ps

R

pu

ESD

20 ns RC

GLITCH FILTER

reset

ESD

V

SS

002aag702

Fig 45. Reset pin configuration

13.7 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 46) or

bus-powered device (see Figure 47).

LPC18S5X_S3X

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Product data sheet

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135 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

On the LPC18S5x/S3x, USBn_VBUS pins are 5 V tolerant only when VDDIO is applied

and at operating voltage level. Therefore, if the USBn_VBUS function is connected to the

USB connector and the device is self-powered, the USBn_VBUS pins must be protected

for situations when VDDIO = 0 V.

If VDDIO is always at operating level while VBUS = 5 V, the USBn_VBUS pin can be

connected directly to the VBUS pin on the USB connector.

For systems where VDDIO can be 0 V and VBUS is directly applied to the USBn_VBUS

pins, precautions must be taken to reduce the voltage to below 3.6 V, which is the

maximum allowable voltage on the USBn_VBUS pins in this case.

One method is to use a voltage divider to connect the USBn_VBUS pins to VBUS on the

USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be

greater than 0.7VDDIO to indicate a logic HIGH while below the 3.6 V allowable maximum

voltage.

For the following operating conditions

VBUS_max= 5.25 V

VDDIO = 3.6 V,

the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.

For bus-powered devices, a regulator powered by USB can provide 3.3 V to VDDIO

whenever bus power is present and ensure that power to the USBn_VBUS pins is always

present when the 5 V VBUS signal is applied. See Figure 47.

Remark: Applying 5 V to the USBn_VBUS pins for a short time while the regulator ramps

up might compromise the long-term reliability of the part but does not affect its function.

LPC18xx

VDDIO

R2

R3

USBn_VBUS

VBUS

USB-B

connector

USB

aaa-013015

Fig 46. USB interface on a self-powered device where USBn_VBUS = 5 V

LPC18S5X_S3X

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Product data sheet

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136 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

LPC18xx

VDDIO

REGULATOR

USBn_VBUS

VBUS

USB-B

connector

USB

aaa-013016

Fig 47. USB interface on a bus-powered device

Remark: If the VBUS function of the USB1 interface is not connected, configure the pin

function for GPIO using the function control bits in the SYSCON block.

VDDIO

R1

LPC18xx

T2

T1

R2

R3

USBn_VBUS

VBUS

USB-B

connector

USB

aaa-013017

Fig 48. USB interface if the USB operates in OTG mode

Remark: In OTG mode, it is important to be able to detect the VBUS level and to charge

and discharge VBUS. This requires adding active devices that disconnect the link when

VDDIO is not present.

LPC18S5X_S3X

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Product data sheet

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137 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

14. Package outline

LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm

SOT740-2

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

C

e

1

y

1 C

y

∅ v M

∅ w M

b

C

A

B

e

1/2 e

T

R

N

L

P

M

K

H

F

e

J

e

2

G

E

C

A

1/2 e

D

B

ball A1

index area

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

X

5

scale

10 mm

0

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.45

0.35

1.1

0.9

0.55 17.2 17.2

0.45 16.8 16.8

mm

1.55

1

15

0.25

0.1

0.12 0.35

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

05-06-16

05-08-04

SOT740-2

MO-192

- - -

Fig 49. Package outline of the LBGA256 package

LPC18S5X_S3X

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Product data sheet

Rev. 1.3 — 10 January 2020

138 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm

SOT926-1

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

C

M

∅ v

∅ w

C

A

B

b

e

1/2 e

y

M

C

1

K

J

H

G

F

e

2

E

D

C

B

A

1/2 e

ball A1

index area

1

2

3

4

5

6

7

8

9

10

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.4

0.3

0.8

0.65

0.5

0.4

9.1

8.9

9.1

8.9

mm

1.2

0.8

7.2

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

05-12-09

05-12-22

SOT926-1

- - -

Fig 50. Package outline of the TFBGA100 package

LPC18S5X_S3X

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Product data sheet

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139 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm

SOT459-1

y

X

A

105

104

156

157

Z

E

e

H

E

(A )

3

A

2

A

1

w M

p

θ

L

b

p

detail X

pin 1 index

53

208

1

52

v

M

B

A

Z

w M

D

b

p

e

D

B

H

v

M

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 28.1 28.1

0.17 0.09 27.9 27.9

30.15 30.15

29.85 29.85

0.75

0.45

1.43 1.43

1.08 1.08

mm

1.6

0.25

1

0.12 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-02-06

03-02-20

SOT459-1

136E30

MS-026

Fig 51. Package outline of the LQFP208 package

LPC18S5X_S3X

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Product data sheet

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140 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

y

X

A

108

109

73

72

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w

p

M

L

p

b

L

pin 1 index

detail X

37

144

1

36

v

M

A

Z

w

M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

E

L

p

v

w

y

Z

E

θ

1

2

3

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

mm

1.6

0.25

1

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

Fig 52. Package outline of the LQFP100 package

LPC18S5X_S3X

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Product data sheet

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141 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

15. Soldering

Footprint information for reflow soldering of LBGA256 package

SOT740-2

Hx

P

Hy

see detail X

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste deposit

solder land plus solder paste

SL

SP

SR

occupied area

solder resist

detail X

DIMENSIONS in mm

P

SL

SP

SR

Hx

Hy

1.00

0.450 0.450 0.600 17.500 17.500

sot740-2_fr

Fig 53. Reflow soldering for the LBGA256 package

LPC18S5X_S3X

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Product data sheet

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142 of 152

LPC18S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Footprint information for reflow soldering of TFBGA100 package

SOT926-1

Hx

P

Hy

see detail X

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste deposit

solder land plus solder paste

SL

SP

SR

occupied area

solder resist

detail X

DIMENSIONS in mm

P

SL

SP

SR

Hx

Hy

0.80

0.330 0.400 0.480 9.400 9.400

sot926-1_fr

Fig 54. Reflow soldering for the TFBGA100 package

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Footprint information for reflow soldering of LQFP208 package

SOT459-1

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 31.300 31.300 28.300 28.300 1.500 0.280 0.400 28.500 28.500 31.550 31.550

sot459-1_fr

Fig 55. Reflow soldering for the LQFP208 package

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Footprint information for reflow soldering of LQFP144 package

SOT486-1

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550

sot486-1_fr

Fig 56. Reflow soldering for the LQFP144 package

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16. Abbreviations

Table 44. Abbreviations

Acronym

ADC

AHB

Description

Analog-to-Digital Converter

Advanced High-performance Bus

Advanced Peripheral Bus

Application Programming Interface

BrownOut Detection

APB

API

BOD

BGA

CAN

CMAC

CSMA/CD

DAC

DMA

EOP

ETB

Ball Grid Array

Controller Area Network

Cipher-based Message Authentication Code

Carrier Sense Multiple Access with Collision Detection

Digital-to-Analog Converter

Direct Memory Access

End Of Packet

Embedded Trace Buffer

ETM

GPIO

IRC

Embedded Trace Macrocell

General-Purpose Input/Output

Internal RC

IrDA

Infrared Data Association

Joint Test Action Group

JTAG

LCD

Liquid Crystal Display

LSB

Least Significant Bit

LQFP

MAC

MCU

MIIM

n.c.

Low Quad Flat Package

Media Access Control

MicroController Unit

Media Independent Interface Management

not connected

OTG

PHY

On-The-Go

PHYsical layer

PLL

Phase-Locked Loop

PWM

RMII

SDRAM

SPI

Pulse Width Modulator

Reduced Media Independent Interface

Synchronous Dynamic Random Access Memory

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

SSI

SSP

TCP/IP

TTL

Transmission Control Protocol/Internet Protocol

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

UTMI+ Low Pin Interface

UART

ULPI

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Table 44. Abbreviations …continued

Acronym Description

USART

USB

Universal Synchronous Asynchronous Receiver/Transmitter

Universal Serial Bus

UTMI

USB 2.0 Transceiver Macrocell Interface

17. References

[1] LPC18xx User manual UM10430:

http://www.nxp.com/documents/user_manual/UM10430.pdf

[2] LPC18xx Errata sheet:

http://www.nxp.com/documents/errata_sheet/ES_LPC18XX.pdf

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18. Revision history

Table 45. Revision history

Document ID

Release date Data sheet status

20200109 Product data sheet

Change notice Supersedes

LPC18S5X_S3Xv.1.3

Modifications:

-

LPC18S5X_S3Xv.1.2

• Updated Section 11.8 “I/O pins” for rise and fall times for I/O pins configured as input

only.

LPC18S5X_S3Xv.1.2

Modifications:

20160303

Product data sheet

-

LPC18S5X_S3Xv.1.1

• Updated Table 29 “Dynamic characteristics: Dynamic external memory interface”:

Read cycle parameters t_h(D)min value is 2.2 ns and max value is “-”.

LPC18S5X_S3Xv.1.1

Modifications:

<tbd>

Product data sheet

2015110041

LPC18S5X_S3Xv.1.0

• Updated Table 2 “Ordering options”: TFBGA100 package does not support ULPI

interface.

• Updated USART timing figure. See Figure 29 “USART timing”.

• Updated SSP slave and SSP master values in Table 27 “Dynamic characteristics:

SSP pins in SPI mode”. Updated footnote 2 to: T_cy(clk)12  T_cy(PCLK)

.

–

removed t_v(Q), data output valid time in SPI mode, minimum value of 3 ´ (1/PCLK)

from SSP slave mode.

–

added units to t_d, delay time, for SSP slave and master mode.

• Added GPCLKIN section and table. See Section 11.7 “GPCLKIN” and Table 22

“Dynamic characteristic: GPCLKIN”.

LPC18S5X_S3Xv.1.0

20150212

Product data sheet

-

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

19.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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21. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.15.10 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 73

7.15.10.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.15.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.15.11.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

4

4.1

5

7.16

7.16.1

Digital serial peripherals. . . . . . . . . . . . . . . . . 74

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.16.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.16.2 USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.16.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.16.3 SSP serial I/O controller. . . . . . . . . . . . . . . . . 75

7.16.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.16.4

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . 76

7.16.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.16.5

I²S interface . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.16.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.16.6 C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.16.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7

7.1

7.2

7.3

7.4

7.5

7.5.1

7.5.2

7.6

Functional description . . . . . . . . . . . . . . . . . . 60

Architectural overview. . . . . . . . . . . . . . . . . . . 60

ARM Cortex-M3 processor . . . . . . . . . . . . . . . 60

System Tick timer (SysTick) . . . . . . . . . . . . . . 60

AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 61

Nested Vectored Interrupt Controller (NVIC) . 61

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 62

Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Global Input Multiplexer Array (GIMA) . . . . . . 62

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 62

On-chip flash memory. . . . . . . . . . . . . . . . . . . 63

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Memory mapping . . . . . . . . . . . . . . . . . . . . . . 65

One-Time Programmable (OTP) memory. . . . 67

General-Purpose I/O (GPIO) . . . . . . . . . . . . . 67

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 67

AES encryption/decryption . . . . . . . . . . . . . . . 67

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

State Configurable Timer/PWM (SCTimer/PWM)

subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.17

7.17.1

Counter/timers and motor control. . . . . . . . . . 77

General purpose 32-bit timers/external event

counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.7

7.7.1

7.8

7.17.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.17.2

7.17.3

Motor control PWM . . . . . . . . . . . . . . . . . . . . 78

Quadrature Encoder Interface (QEI) . . . . . . . 78

7.9

7.17.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.17.4 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 79

7.17.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.17.5 Windowed WatchDog Timer (WWDT) . . . . . . 79

7.17.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.10

7.11

7.12

7.13

7.14

7.14.1

7.15

7.15.1

7.15.2

7.15.3

7.18

7.18.1

Analog peripherals . . . . . . . . . . . . . . . . . . . . . 79

Analog-to-Digital Converter . . . . . . . . . . . . . . 79

7.18.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.18.2 Digital-to-Analog Converter (DAC). . . . . . . . . 80

7.18.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.19

7.19.1

Peripherals in the RTC power domain . . . . . . 80

RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.15.4 General-Purpose DMA . . . . . . . . . . . . . . . . . 69

7.15.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.15.5 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 70

7.15.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.19.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.19.2 Event monitor/recorder. . . . . . . . . . . . . . . . . . 80

7.19.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

7.19.3

7.20

Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 81

System control . . . . . . . . . . . . . . . . . . . . . . . . 81

Configuration registers (CREG) . . . . . . . . . . . 81

System Control Unit (SCU) . . . . . . . . . . . . . . 81

Clock Generation Unit (CGU). . . . . . . . . . . . . 82

Internal RC oscillator (IRC) . . . . . . . . . . . . . . 82

PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 82

PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 82

System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 82

Reset Generation Unit (RGU) . . . . . . . . . . . . 83

7.15.6

7.15.7

SD/MMC card interface . . . . . . . . . . . . . . . . . 70

External Memory Controller (EMC). . . . . . . . . 71

7.20.1

7.20.2

7.20.3

7.20.4

7.20.5

7.20.6

7.20.7

7.20.8

7.15.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.15.8

High-speed USB Host/Device/OTG interface

(USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.15.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.15.9

High-speed USB Host/Device interface with ULPI

(USB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.15.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

continued >>

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NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

7.20.9

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 83

19.4

20

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 150

Contact information . . . . . . . . . . . . . . . . . . . 150

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

7.20.10 Code security (Code Read Protection - CRP) 84

7.21

Emulation and debugging. . . . . . . . . . . . . . . . 85

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 86

Thermal characteristics. . . . . . . . . . . . . . . . . . 87

21

8

9

10

Static characteristics. . . . . . . . . . . . . . . . . . . . 88

Power consumption . . . . . . . . . . . . . . . . . . . . 95

Peripheral power consumption . . . . . . . . . . . . 98

Electrical pin characteristics . . . . . . . . . . . . . 100

BOD and band gap static characteristics . . . 104

10.1

10.2

10.3

10.4

11

11.1

11.2

11.3

11.4

11.5

11.6

11.7

Dynamic characteristics . . . . . . . . . . . . . . . . 105

Flash/EEPROM memory . . . . . . . . . . . . . . . 105

Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 106

External clock for oscillator in slave mode . . 106

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 107

IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107

GPCLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

I²S-bus interface. . . . . . . . . . . . . . . . . . . . . . 110

USART interface. . . . . . . . . . . . . . . . . . . . . . 111

SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 113

External memory interface . . . . . . . . . . . . . . 117

USB interface . . . . . . . . . . . . . . . . . . . . . . . . 122

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

11.8

11.9

11.10

11.11

11.12

11.13

11.14

11.15

11.16

11.17

11.18

12

ADC/DAC electrical characteristics . . . . . . . 127

13

Application information. . . . . . . . . . . . . . . . . 130

LCD panel signal usage . . . . . . . . . . . . . . . . 130

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 132

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 134

XTAL and RTCX Printed Circuit Board (PCB)

layout guidelines. . . . . . . . . . . . . . . . . . . . . . 134

Standard I/O pin configuration . . . . . . . . . . . 134

Reset pin configuration. . . . . . . . . . . . . . . . . 135

Suggested USB interface solutions . . . . . . . 135

13.1

13.2

13.3

13.4

13.5

13.6

13.7

14

15

16

17

18

Package outline . . . . . . . . . . . . . . . . . . . . . . . 138

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 146

References . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Revision history. . . . . . . . . . . . . . . . . . . . . . . 148

19

Legal information. . . . . . . . . . . . . . . . . . . . . . 149

Data sheet status . . . . . . . . . . . . . . . . . . . . . 149

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 149

19.1

19.2

19.3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 January 2020

Document identifier: LPC18S5X_S3X


型号：	LPC18S37JET100
厂家：	NXP
描述：	32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC, AES engine CD 静态存储器
文件：	总152页 (文件大小：2802K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC18S37JET100 [NXP]

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