LPC2132FHN64_技术文档

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB

ISP/IAP ﬂash with 10-bit ADC and DAC

Rev. 04 — 16 October 2007

Product data sheet

1. General description

The LPC2131/32/34/36/38 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU

with real-time emulation and embedded trace support, that combine the microcontroller

with 32 kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high-speed ﬂash memory. A

128-bit wide memory interface and a unique accelerator architecture enable 32-bit code

execution at maximum clock rate. For critical code size applications, the alternative 16-bit

Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, these microcontrollers are ideal for

applications where miniaturization is a key requirement, such as access control and

point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM

options of 8 kB, 16 kB, and 32 kB, they are very well suited for communication gateways

and protocol converters, soft modems, voice recognition and low-end imaging, providing

both large buffer size and high processing power. Various 32-bit timers, single or dual

10-bit 8-channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine

edge or level sensitive external interrupt pins make these microcontrollers particularly

suitable for industrial control and medical systems.

2. Features

2.1 Enhancements brought by LPC213x/01 devices

I Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original

LPC213x. They also allow for a port pin to be read at any time regardless of its

function.

I Dedicated result registers for ADC(s) reduce interrupt overhead.

I UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake ﬂow-control fully implemented in hardware.

I Additional BOD control enables further reduction of power consumption.

2.2 Key features common for LPC213x and LPC213x/01

I 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 or HVQFN package.

I 8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip ﬂash program

memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation.

I In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader

software. Single ﬂash sector or full chip erase in 400 ms and programming of 256 B in

1 ms.

I EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software and high-speed tracing of instruction execution.

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

I One (LPC2131/32) or two (LPC2134/36/38) 8-channel 10-bit ADCs provide a total of

up to 16 analog inputs, with conversion times as low as 2.44 µs per channel.

I Single 10-bit DAC provides variable analog output (LPC2132/34/36/38).

I Two 32-bit timers/external event counters (with four capture and four compare

channels each), PWM unit (six outputs) and watchdog.

I Low power Real-time clock with independent power and dedicated 32 kHz clock input.

I Multiple serial interfaces including two UARTs (16C550), two Fast I²C-bus (400 kbit/s),

SPI and SSP with buffering and variable data length capabilities.

I Vectored interrupt controller with conﬁgurable priorities and vector addresses.

I Up to forty-seven 5 V tolerant general purpose I/O pins in tiny LQFP64 or HVQFN

package.

I Up to nine edge or level sensitive external interrupt pins available.

I 60 MHz maximum CPU clock available from programmable on-chip PLL with settling

time of 100 µs.

I On-chip integrated oscillator operates with external crystal in range of 1 MHz to

30 MHz and with external oscillator up to 50 MHz.

I Power saving modes include Idle and Power-down.

I Individual enable/disable of peripheral functions as well as peripheral clock scaling

down for additional power optimization.

I Processor wake-up from Power-down mode via external interrupt or BOD.

I Single power supply chip with POR and BOD circuits:

N CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

pads.

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2131FBD64

LQFP64

plastic low proﬁle quad ﬂat package; 64 leads;

SOT314-2

body 10 × 10 × 1.4 mm

LPC2131FBD64/01 LQFP64

LPC2132FBD64 LQFP64

LPC2132FBD64/01 LQFP64

LPC2132FHN64

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

SOT314-2

SOT804-2

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

HVQFN64 plastic thermal enhanced very thin quad ﬂat

package; no leads; 64 terminals; body

9 × 9 × 0.85 mm

LPC2132FHN64/01 HVQFN64 plastic thermal enhanced very thin quad ﬂat

package; no leads; 64 terminals; body

SOT804-2

9 × 9 × 0.85 mm

LPC2134FBD64

LQFP64

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

SOT314-2

LPC2134FBD64/01 LQFP64

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

2 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

Table 1.

Ordering information …continued

Type number

Package

Name

Description

Version

LPC2136FBD64

LQFP64

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

SOT314-2

SOT804-2

LPC2136FBD64/01 LQFP64

LPC2138FBD64 LQFP64

LPC2138FBD64/01 LQFP64

LPC2138FHN64

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

HVQFN64 plastic thermal enhanced very thin quad ﬂat

package; no leads; 64 terminals; body

9 × 9 × 0.85 mm

LPC2138FHN64/01 HVQFN64 plastic thermal enhanced very thin quad ﬂat

package; no leads; 64 terminals; body

SOT804-2

9 × 9 × 0.85 mm

3.1 Ordering options

Table 2.

Ordering options

Type number

Flash

RAM ADC DAC Enhanced UARTs, Temperature

memory

ADC, Fast I/Os, and range

BOD

LPC2131FBD64

32 kB

8 kB

1

2

-

no

yes

no

−40 °C to +85 °C

LPC2131FBD64/01 32 kB

LPC2132FBD64 64 kB

LPC2132FBD64/01 64 kB

LPC2132FHN64 64 kB

LPC2132FHN64/01 64 kB

LPC2134FBD64 128 kB

LPC2134FBD64/01 128 kB

LPC2136FBD64 256 kB

LPC2136FBD64/01 256 kB

LPC2138FBD64 512 kB

LPC2138FBD64/01 512 kB

LPC2138FHN64 512 kB

LPC2138FHN64/01 512 kB

8 kB

-

16 kB

32 kB

1

yes

no

yes

no

yes

no

yes

no

yes

no

yes

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

3 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

4. Block diagram

(3)

TMS

(3)

TDI

(3)

trace

signals

XTAL2

(3)

XTAL1

RESET

TRST

TCK

TDO

LPC2131, LPC2131/01

LPC2132, LPC2132/01

LPC2134, LPC2134/01

LPC2136, LPC2136/01

LPC2138, LPC2138/01

TEST/DEBUG

INTERFACE

SYSTEM

FUNCTIONS

PLL

ARM7TDMI-S

system

clock

VECTORED

INTERRUPT

CONTROLLER

P0[31:0]

FAST GENERAL

PURPOSE I/O

AHB BRIDGE

P1[31:16]

AMBA AHB

(Advanced High-performance Bus)

ARM7 local bus

INTERNAL

SRAM

INTERNAL

FLASH

CONTROLLER

AHB

DECODER

32/64/128/

256/512 kB

FLASH

8/16/32 kB

SRAM

AHB TO APB

BRIDGE

APB

DIVIDER

APB (ARM

peripheral bus)

SCL0,1

SDA0,1

2

EXTERNAL

INTERRUPTS

I C SERIAL

EINT[3:0]

INTERFACES 0 AND 1

8 × CAP

CAPTURE/

COMPARE

TIMER 0/TIMER 1

SCK0,1

MOSI0,1

MISO0,1

SSEL0,1

SPI AND SSP

SERIAL INTERFACES

8 × MAT

AD0[7:0]

A/D CONVERTERS

TXD0,1

RXD0,1

(1)

0 AND 1

(1)

AD1[7:0]

UART0/UART1

(1)

DSR1 ,CTS1

(1)

RTS1 , DTR1

(2)

(1)

AOUT

D/A CONVERTER

DCD1 , RI1

RTCX1

RTCX2

VBAT

REAL TIME CLOCK

P0[31:0]

GENERAL

PURPOSE I/O

P1[31:16]

WATCHDOG

TIMER

PWM[6:1]

PWM0

SYSTEM

CONTROL

002aab067

(1) LPC2134/36/38 only.

(2) LPC2132/34/36/38 only.

(3) Pins shared with GPIO.

Fig 1. Block diagram

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

4 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

5. Pinning information

5.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

RTCX1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/EINT2

3

4

P1.19/TRACEPKT3

RTCX2

5

P1.21/PIPESTAT0

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4

P0.14/EINT1/SDA1

P1.22/PIPESTAT1

P0.13/MAT1.1

LPC2131

LPC2131/01

9

10

11

12

13

14

15

16

P0.26/AD0.5

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.12/MAT1.0

P0.11/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.10/CAP1.0

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4

002aab068

Fig 2. LPC2131 LQFP64 pinning

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

5 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

RTCX1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/EINT2

3

4

P1.19/TRACEPKT3

RTCX2

5

P1.21/PIPESTAT0

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

P0.14/EINT1/SDA1

P1.22/PIPESTAT1

P0.13/MAT1.1

LPC2132

LPC2132/01

9

10

11

12

13

14

15

16

P0.26/AD0.5

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.12/MAT1.0

P0.11/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.10/CAP1.0

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4

002aab406

Fig 3. LPC2132 LQFP64 pin conﬁguration

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

6 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/AD1.6/CAP1.3

P0.22/AD1.7/CAP0.0/MAT0.0

RTCX1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/RI1/EINT2/AD1.5

P1.21/PIPESTAT0

3

4

P1.19/TRACEPKT3

RTCX2

5

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

P0.14/DCD1/EINT1/SDA1

P1.22/PIPESTAT1

LPC2134, LPC2134/01

LPC2136, LPC2136/01

LPC2138, LPC2138/01

9

10

11

12

13

14

15

16

P0.26/AD0.5

P0.13/DTR1/MAT1.1/AD1.4

P0.12/DSR1/MAT1.0/AD1.3

P0.11/CTS1/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.10/RTS1/CAP1.0/AD1.2

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4/AD1.1

002aab407

Fig 4. LPC2134/36/38 LQFP64 pin conﬁguration

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

7 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

terminal 1

index area

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/AD1.6/CAP1.3

P0.22/AD1.7/CAP0.0/MAT0.0

RTCX1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/RI1/EINT2/AD1.5

P1.21/PIPESTAT0

3

4

P1.19/TRACEPKT3

RTCX2

5

6

V

SS

V

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

P0.14/DCD1/EINT1/SDA1

P1.22/PIPESTAT1

LPC2132/2138

9

10

11

12

13

14

15

16

P0.26/AD0.5

P0.13/DTR1/MAT1.1/AD1.4

P0.12/DSR1/MAT1.0/AD1.3

P0.11/CTS1/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.10/RTS1/CAP1.0/AD1.2

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4/AD1.1

Transparent top view

002aab943

AD1.7 to AD1.0 only available on LPC2134/36/38.

Fig 5. LPC2132/38 HVQFN64 pin conﬁguration

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

8 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

5.2 Pin description

Table 3.

Symbol

Pin description

Type

Description

P0.0 to P0.31

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.

Total of 31 pins of the Port 0 can be used as a general purpose bidirectional

digital I/Os while P0.31 is output only pin. The operation of port 0 pins

depends upon the pin function selected via the pin connect block.

Pin P0.24 is not available.

P0.0/TXD0/

PWM1

19^[1]

21^[2]

O

I

TXD0 — Transmitter output for UART0.

PWM1 — Pulse Width Modulator output 1.

P0.1/RXD0/

RXD0 — Receiver input for UART0.

PWM3/EINT0

O

I

PWM3 — Pulse Width Modulator output 3.

EINT0 — External interrupt 0 input.

P0.2/SCL0/

CAP0.0

22^[3]

26^[3]

I/O

I

SCL0 — I²C0 clock input/output. Open drain output (for I²C-bus compliance).

CAP0.0 — Capture input for Timer 0, channel 0.

SDA0 — I²C0 data input/output. Open drain output (for I²C-bus compliance).

MAT0.0 — Match output for Timer 0, channel 0.

EINT1 — External interrupt 1 input.

P0.3/SDA0/

MAT0.0/EINT1

I/O

O

I

P0.4/SCK0/

CAP0.1/AD0.6

27^[4]

I/O

I

SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

CAP0.1 — Capture input for Timer 0, channel 1.

AD0.6 — ADC 0, input 6. This analog input is always connected to its pin.

I

P0.5/MISO0/

29^[4]

I/O

MISO0 — Master In Slave V_DD= 3.6 V for SPI0. Data input to SPI master or

MAT0.1/AD0.7

data output from SPI slave.

O

I

MAT0.1 — Match output for Timer 0, channel 1.

AD0.7 — ADC 0, input 7. This analog input is always connected to its pin.

P0.6/MOSI0/

30^[4]

I/O

MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

CAP0.2/AD1.0

input to SPI slave.

I

CAP0.2 — Capture input for Timer 0, channel 2.

AD1.0 — ADC 1, input 0. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.7/SSEL0/

PWM2/EINT2

31^[2]

I

SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

PWM2 — Pulse Width Modulator output 2.

EINT2 — External interrupt 2 input.

O

I

P0.8/TXD1/

PWM4/AD1.1

33^[4]

O

I

TXD1 — Transmitter output for UART1.

PWM4 — Pulse Width Modulator output 4.

AD1.1 — ADC 1, input 1. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.9/RXD1/

34^[2]

I

RXD1 — Receiver input for UART1.

PWM6/EINT3

O

I

PWM6 — Pulse Width Modulator output 6.

EINT3 — External interrupt 3 input.

P0.10/RTS1/

CAP1.0/AD1.2

35^[4]

O

I

RTS1 — Request to Send output for UART1. Available in LPC2134/36/38.

CAP1.0 — Capture input for Timer 1, channel 0.

I

AD1.2 — ADC 1, input 2. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

9 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

Table 3.

Symbol

Pin description …continued

Type

Description

P0.11/CTS1/

CAP1.1/SCL1

37^[3]

I

CTS1 — Clear to Send input for UART1. Available in LPC2134/36/38.

I

CAP1.1 — Capture input for Timer 1, channel 1.

I/O

SCL1 — I²C1 clock input/output. Open drain output (for I²C-bus compliance)

DSR1 — Data Set Ready input for UART1. Available in LPC2134/36/38.

MAT1.0 — Match output for Timer 1, channel 0.

P0.12/DSR1/

38^[4]

I

MAT1.0/AD1.3

O

I

AD1.3 — ADC 1, input 3. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.13/DTR1/

39^[4]

O

DTR1 — Data Terminal Ready output for UART1. Available in

MAT1.1/AD1.4

LPC2134/36/38.

O

I

MAT1.1 — Match output for Timer 1, channel 1.

AD1.4 — ADC 1, input 4. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.14/DCD1/

EINT1/SDA1

41^[3]

I

DCD1 — Data Carrier Detect input for UART1. Available in LPC2134/36/38.

I

EINT1 — External interrupt 1 input.

I/O

SDA1 — I²C1 data input/output. Open drain output (for I²C-bus compliance).

RI1 — Ring Indicator input for UART1. Available in LPC2134/36/38.

EINT2 — External interrupt 2 input.

P0.15/RI1/

45^[4]

I

EINT2/AD1.5

AD1.5 — ADC 1, input 5. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.16/EINT0/

46^[2]

I

EINT0 — External interrupt 0 input.

MAT0.2/CAP0.2

O

I

MAT0.2 — Match output for Timer 0, channel 2.

CAP0.2 — Capture input for Timer 0, channel 2.

CAP1.2 — Capture input for Timer 1, channel 2.

SCK1 — Serial Clock for SSP. Clock output from master or input to slave.

MAT1.2 — Match output for Timer 1, channel 2.

CAP1.3 — Capture input for Timer 1, channel 3.

P0.17/CAP1.2/ 47^[1]

SCK1/MAT1.2

I

I/O

O

I

P0.18/CAP1.3/ 53^[1]

MISO1/MAT1.3

I/O

MISO1 — Master In Slave Out for SSP. Data input to SPI master or data

output from SSP slave.

O

MAT1.3 — Match output for Timer 1, channel 3.

MAT1.2 — Match output for Timer 1, channel 2.

P0.19/MAT1.2/ 54^[1]

MOSI1/CAP1.2

O

I/O

MOSI1 — Master Out Slave In for SSP. Data output from SSP master or data

input to SSP slave.

I

CAP1.2 — Capture input for Timer 1, channel 2.

MAT1.3 — Match output for Timer 1, channel 3.

SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.

EINT3 — External interrupt 3 input.

P0.20/MAT1.3/ 55^[2]

SSEL1/EINT3

O

I

P0.21/PWM5/

AD1.6/CAP1.3

1^[4]

O

I

PWM5 — Pulse Width Modulator output 5.

AD1.6 — ADC 1, input 6. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

I

CAP1.3 — Capture input for Timer 1, channel 3.

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

10 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

Table 3.

Symbol

Pin description …continued

Type

Description

P0.22/AD1.7/

2^[4]

I

AD1.7 — ADC 1, input 7. This analog input is always connected to its pin.

CAP0.0/MAT0.0

Available in LPC2134/36/38 only.

I

CAP0.0 — Capture input for Timer 0, channel 0.

O

I/O

I

MAT0.0 — Match output for Timer 0, channel 0.

P0.23

58^[1]

9^[5]

General purpose digital input/output pin.

P0.25/AD0.4/

AOUT

AD0.4 — ADC 0, input 4. This analog input is always connected to its pin.

AOUT — DAC output. Not available in LPC2131.

O

I

P0.26/AD0.5

10^[4]

11^[4]

AD0.5 — ADC 0, input 5. This analog input is always connected to its pin.

AD0.0 — ADC 0, input 0. This analog input is always connected to its pin.

CAP0.1 — Capture input for Timer 0, channel 1.

P0.27/AD0.0/

CAP0.1/MAT0.1

I

O

I

MAT0.1 — Match output for Timer 0, channel 1.

P0.28/AD0.1/

CAP0.2/MAT0.2

13^[4]

14^[4]

15^[4]

17^[6]

AD0.1 — ADC 0, input 1. This analog input is always connected to its pin.

CAP0.2 — Capture input for Timer 0, channel 2.

I

O

I

MAT0.2 — Match output for Timer 0, channel 2.

P0.29/AD0.2/

CAP0.3/MAT0.3

AD0.2 — ADC 0, input 2. This analog input is always connected to its pin.

CAP0.3 — Capture input for Timer 0, channel 3.

I

O

I

MAT0.3 — Match output for Timer 0, channel 3.

P0.30/AD0.3/

EINT3/CAP0.0

AD0.3 — ADC 0, input 3. This analog input is always connected to its pin.

EINT3 — External interrupt 3 input.

I

CAP0.0 — Capture input for Timer 0, channel 0.

P0.31

O

General purpose digital output only pin.

Important: This pin MUST NOT be externally pulled LOW when RESET pin

is LOW or the JTAG port will be disabled.

P1.0 to P1.31

I/O

Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 1 pins depends upon the pin function

selected via the pin connect block. Pins 0 through 15 of port 1 are not

available.

P1.16/

TRACEPKT0

16^[6]

12^[6]

8^[6]

O

TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1.17/

TRACEPKT1

P1.18/

TRACEPKT2

P1.19/

TRACEPKT3

4^[6]

P1.20/

TRACESYNC

48^[6]

TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up. LOW on TRACESYNC while RESET is LOW enables pins P1.25:16

to operate as Trace port after reset.

P1.21/

PIPESTAT0

44^[6]

40^[6]

36^[6]

O

PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

P1.22/

PIPESTAT1

P1.23/

PIPESTAT2

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Single-chip 16/32-bit microcontrollers

Table 3.

Symbol

Pin description …continued

Type

Description

P1.24/

32^[6]

O

TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

TRACECLK

P1.25/EXTIN0 28^[6]

I

EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

P1.26/RTCK

24^[6]

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bidirectional pin with internal pull-up. LOW on RTCK while RESET is LOW

enables pins P1.31:26 to operate as Debug port after reset.

P1.27/TDO

P1.28/TDI

P1.29/TCK

P1.30/TMS

P1.31/TRST

RESET

64^[6]

60^[6]

56^[6]

52^[6]

20^[6]

57^[7]

O

I

TDO — Test Data out for JTAG interface.

TDI — Test Data in for JTAG interface.

TCK — Test Clock for JTAG interface.

TMS — Test Mode Select for JTAG interface.

TRST — Test Reset for JTAG interface.

I

External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

RTCX1

RTCX2

V_SS

62^[8]

61^[8]

3^[8]

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator ampliﬁer.

O

I

Input to the RTC oscillator circuit.

5^[8]

O

I

Output from the RTC oscillator circuit.

Ground: 0 V reference.

6, 18, 25, 42,

50

V_SSA

V_DD

59

I

Analog ground: 0 V reference. This should nominally be the same voltage

as V_SS, but should be isolated to minimize noise and error.

23, 43, 51

7

3.3 V power supply: This is the power supply voltage for the core and I/O

ports.

V_DDA

Analog 3.3 V power supply: This should be nominally the same voltage as

V_DDbut should be isolated to minimize noise and error. This voltage is used

to power the on-chip PLL.

VREF

VBAT

63

49

I

ADC reference: This should be nominally the same voltage as V_DDbut

should be isolated to minimize noise and error. Level on this pin is used as a

reference for A/D and D/A convertor(s).

RTC power supply: 3.3 V on this pin supplies the power to the RTC.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If conﬁgured for an input

function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[3] Open drain 5 V tolerant digital I/O I²C-bus 400 kHz speciﬁcation compatible pad. It requires external pull-up to provide an output

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If conﬁgured

for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When conﬁgured as an ADC input, digital

section of the pad is disabled.

[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When

conﬁgured as the DAC output, digital section of the pad is disabled.

[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.

[7] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

[8] Pad provides special analog functionality.

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Single-chip 16/32-bit microcontrollers

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip ﬂash program memory

The LPC2131/32/34/36/38 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB ﬂash

memory system respectively. This memory may be used for both code and data storage.

Programming of the ﬂash memory may be accomplished in several ways. It may be

programmed In System via the serial port. The application program may also erase and/or

program the ﬂash while the application is running, allowing a great degree of ﬂexibility for

data storage ﬁeld ﬁrmware upgrades, etc. When the LPC2131/32/34/36/38 on-chip

bootloader is used, 32/64/128/256/500 kB of ﬂash memory is available for user code.

The LPC2131/32/34/36/38 ﬂash memory provides a minimum of 100000 erase/write

cycles and 20 years of data-retention.

6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bit, 16-bit, and 32-bit. The LPC2131, LPC2132/34, and LPC2136/38

provide 8 kB, 16 kB and 32 kB of static RAM respectively.

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6.4 Memory map

The LPC2131/32/34/36/38 memory map incorporates several distinct regions, as shown

in Figure 6.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

ﬂash memory (the default) or on-chip static RAM. This is described in Section 6.18

“System control”.

4.0 GB

0xFFFF FFFF

AHB PERIPHERALS

0xF000 0000

0xE000 0000

3.75 GB

3.5 GB

VPB PERIPHERALS

0xC000 0000

3.0 GB

RESERVED ADDRESS SPACE

0x8000 0000

2.0 GB

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY

RESERVED ADDRESS SPACE

0x4001 8000

0x4000 7FFF

TOTAL OF 32 kB ON-CHIP STATIC RAM (LPC2136/38)

TOTAL OF 16 kB ON-CHIP STATIC RAM (LPC2132/34)

TOTAL OF 8 kB ON-CHIP STATIC RAM (LPC2131)

RESERVED ADDRESS SPACE

0x4000 4000

0x4000 3FFF

0x4000 2000

0x4000 1FFF

1.0 GB

0x4000 0000

0x0008 0000

0x0007 FFFF

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2138)

0x0004 0000

0x0003 FFFF

TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2136)

0x0002 0000

0x0001 FFFF

TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2134)

0x0001 0000

0x0000 FFFF

TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2132)

0x0000 8000

0x0000 7FFF

TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2131)

0x0000 0000

0.0 GB

002aab069

Fig 6. LPC2131/32/34/36/38 memory map

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6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as deﬁned by programmable settings. The programmable assignment

scheme means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then

the FIQ service routine can simply start dealing with that device. But if more than one

request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC

that identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are requesting, the

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several

internal interrupt ﬂags. Individual interrupt ﬂags may also represent more than one

interrupt source.

Table 4.

Block

Interrupt sources

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

0

1

2

3

4

-

Reserved for software interrupts only

EmbeddedICE, DbgCommRX

ARM Core

TIMER0

EmbeddedICE, DbgCommTX

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

RX Line Status (RLS)

TIMER1

UART0

5

6

Transmit Holding Register empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

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Single-chip 16/32-bit microcontrollers

Table 4.

Interrupt sources …continued

Flag(s)

Block

VIC channel #

UART1

RX Line Status (RLS)

7

Transmit Holding Register empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI) (Available in LPC2134/36/38

only)

PWM0

Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

SI (state change)

8

I²C0

SPI0

SSP

9

SPIF, MODF

10

11

TX FIFO at least half empty (TXRIS)

RX FIFO at least half full (RXRIS)

Receive Timeout (RTRIS)

Receive Overrun (RORRIS)

PLL

PLL Lock (PLOCK)

12

13

14

15

16

17

18

19

20

21

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

System Control External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

External Interrupt 2 (EINT2)

External Interrupt 3 (EINT3)

AD0

I2C1

BOD

AD1

ADC 0

SI (state change)

Brown Out Detect

ADC 1 (Available in LPC2134/36/38 only)

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

6.7 General purpose parallel I/O and Fast I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.7.1 Features

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

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6.7.2 Fast I/O features available in LPC213x/01 only

• Fast I/O registers are located on the ARM local bus for the fastest possible I/O timing.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Mask registers allow single instruction to set or clear any number of bits in one port.

6.8 10-bit ADC

The LPC2131/32 contain one and the LPC2134/36/38 contain two ADCs. These

converters are single 10-bit successive approximation ADCs with eight multiplexed

channels.

6.8.1 Features

• Measurement range of 0 V to 3.3 V.

• Each converter capable of performing more than 400000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

• Global Start command for both converters (LPC2134/36/38 only).

6.8.2 ADC features available in LPC213x/01 only

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Every analog input can generate an interrupt once the conversion is completed.

6.9 10-bit DAC

This peripheral is available in the LPC2132/34/36/38 only. The DAC enables the

LPC2132/34/36/38 to generate variable analog output.

6.9.1 Features

• 10-bit digital to analog converter.

• Buffered output.

• Power-down mode available.

• Selectable speed versus power.

6.10 UARTs

The LPC2131/32/34/36/38 each contain two UARTs. In addition to standard transmit and

receive data lines, the LPC2134/36/38 UART1 also provides a full modem control

handshake interface.

6.10.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

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• Built-in baud rate generator.

• Standard modem interface signals included on UART1. (LPC2134/36/38 only)

• The LPC2131/32/34/36/38 transmission FIFO control enables implementation of

software (XON/XOFF) ﬂow control on both UARTs and hardware (CTS/RTS) ﬂow

control on the LPC2134/36/38 UART1 only.

6.10.2 UART features available in LPC213x/01 only

• Fractional baud rate generator enables standard baud rates such as 115200 to be

achieved with any crystal frequency above 2 MHz.

• Auto-bauding.

• Auto-CTS/RTS ﬂow-control fully implemented in hardware (LPC2134/36/38 only).

6.11 I²C-bus serial I/O controller

The LPC2131/32/34/36/38 each contain two I²C-bus controllers.

The I²C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory)). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

This I²C-bus implementation supports bit rates up to 400 kbit/s (Fast I²C).

6.11.1 Features

• Standard I²C compliant bus interface.

• Easy to conﬁgure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus may be used for test and diagnostic purposes.

6.12 SPI serial I/O controller

The LPC2131/32/34/36/38 each contain one SPI controller. The SPI is a full duplex serial

interface, designed to be able to handle multiple masters and slaves connected to a given

bus. Only a single master and a single slave can communicate on the interface during a

given data transfer. During a data transfer the master always sends a byte of data to the

slave, and the slave always sends a byte of data to the master.

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6.12.1 Features

• Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

• Synchronous, Serial, Full Duplex, Communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.13 SSP serial I/O controller

The LPC2131/32/34/36/38 each contain one Serial Synchronous Port controller (SSP).

The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. However, only a single master and a

single slave can communicate on the bus during a given data transfer. The SSP supports

full duplex transfers, with frames of 4 bits to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master. Often only one of these data ﬂows carries

meaningful data.

6.13.1 Features

• Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire

buses.

• Synchronous Serial Communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.14 General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock, and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

At any given time only one of peripheral’s capture inputs can be selected as an external

event signal source, i.e., timer’s clock. The rate of external events that can be successfully

counted is limited to PCLK/2. In this conﬁguration, unused capture lines can be selected

as regular timer capture inputs.

6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• External Event Counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

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– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T_cy(PCLK)× 256 × 4) to (T_cy(PCLK)× 2³²× 4) in multiples of

T

_cy(PCLK)× 4.

6.16 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider

allows ﬁne adjustment of the RTC.

• Dedicated power supply pin can be connected to a battery or the main 3.3 V.

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6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2131/32/34/36/38. The Timer is designed

to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or

perform other actions when speciﬁed timer values occur, based on seven match registers.

The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

With double edge controlled PWM outputs, speciﬁc match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.17.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

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Single-chip 16/32-bit microcontrollers

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.18 System control

6.18.1 Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 30 MHz

and with external oscillator up to 50 MHz. The oscillator output frequency is called f_oscand

the ARM processor clock frequency is referred to as CCLK for purposes of rate equations,

etc. f_oscand CCLK are the same value unless the PLL is running and connected. Refer to

Section 6.18.2 “PLL” for additional information.

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must conﬁgure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100 µs.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2131/32/34/36/38: the RESET pin and watchdog reset.

The RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of

chip reset by any source starts the wake-up timer (see wake-up timer description below),

causing the internal chip reset to remain asserted until the external reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash

controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the wake-up timer.

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Single-chip 16/32-bit microcontrollers

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DDramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 Brownout detector

The LPC2131/32/34/36/38 include 2-stage monitoring of the voltage on the V_DDpins. If

this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the Vectored Interrupt

Controller. This signal can be enabled for interrupt; if not, software can monitor the signal

by reading dedicated register.

The second stage of low-voltage detection asserts reset to inactivate the

LPC2131/32/34/36/38 when the voltage on the V_DDpins falls below 2.6 V. This reset

prevents alteration of the ﬂash as operation of the various elements of the chip would

otherwise become unreliable due to low voltage. The BOD circuit maintains this reset

down below 1 V, at which point the POR circuitry maintains the overall reset.

Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event

loop to sense the condition.

Features available only in LPC213x/01 parts include ability to put the BOD in power-down

mode, turn it on or off and to control when the BOD will reset the LPC213x/01

microcontroller. This can be used to further reduce power consumption when a low power

mode (such as Power Down) is invoked.

6.18.5 Code security

This feature of the LPC2131/32/34/36/38 allow an application to control whether it can be

debugged or protected from observation.

If after reset on-chip bootloader detects a valid checksum in ﬂash and reads 0x8765 4321

from address 0x1FC in ﬂash, debugging will be disabled and thus the code in ﬂash will be

protected from observation. Once debugging is disabled, it can be enabled only by

performing a full chip erase using the ISP.

6.18.6 External interrupt inputs

The LPC2131/32/34/36/38 include up to nine edge or level sensitive External Interrupt

Inputs as selectable pin functions. When the pins are combined, external events can be

processed as four independent interrupt signals. The External Interrupt Inputs can

optionally be used to wake up the processor from Power-down mode.

6.18.7 Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

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Single-chip 16/32-bit microcontrollers

6.18.8 Power Control

The LPC2131/32/34/36/38 support two reduced power modes: Idle mode and

Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip

RTC will enable the microcontroller to have the RTC active during Power-down mode.

Power-down current is increased with RTC active. However, it is signiﬁcantly lower than in

Idle mode.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.18.9 VPB bus

The VPB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via VPB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be

slowed down to ¹⁄₂to ¹⁄₄of the processor clock rate. Because the VPB bus must work

properly at power-up (and its timing cannot be altered if it does not work since the VPB

divider control registers reside on the VPB bus), the default condition at reset is for the

VPB bus to run at ¹⁄₄of the processor clock rate. The second purpose of the VPB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the VPB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

6.19 Emulation and debugging

The LPC2131/32/34/36/38 support emulation and debugging via a JTAG serial port. A

trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on Port 1. This means that all communication, timer and

interface peripherals residing on Port 0 are available during the development and

debugging phase as they are when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

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Single-chip 16/32-bit microcontrollers

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

6.19.2 Embedded trace

Since the LPC2131/32/34/36/38 have signiﬁcant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the

external pins. The Embedded Trace Macrocell provides real-time trace capability for

deeply embedded processor cores. It outputs information about processor execution to

the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code can not be traced

because of this restriction.

6.19.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2131/32/34/36/38 contain a speciﬁc

conﬁguration of RealMonitor software programmed into the on-chip ﬂash memory.

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Single-chip 16/32-bit microcontrollers

7. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD

Parameter

Conditions

Min

Max

+3.6

+4.6

+5.1

Unit

V

supply voltage (core and external rail)

analog 3.3 V pad supply voltage

input voltage on pin VBAT

input voltage on pin VREF

analog input voltage

−0.5

V_DDA

V

V_i(VBAT)

V_i(VREF)

V_IA

for the RTC

V

on ADC related

pins

V

[2]

V_I

input voltage

5 V tolerant I/O

pins; only valid

when the V_DD

supply voltage is

present

−0.5

+6.0

V

[2]

[5]

other I/O pins

per supply pin

per ground pin

−0.5

V_DD+ 0.5^[3]

100^[4]

V

I_DD

supply current

-

mA

°C

W

I_SS

ground current

-

T_stg

storage temperature

total power dissipation (per package)

−40

+125

P_tot(pack)

based on package

heat transfer, not

device power

-

1.5

consumption

[6]

V_esd

electrostatic discharge voltage

human body model

all pins

−4000

+4000

V

[1] The following applies to the Limiting values:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] Dependent on package type.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

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Single-chip 16/32-bit microcontrollers

8. Static characteristics

Table 6.

Static characteristics

T_amb= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_DD

supply voltage (core and

3.0

3.3

3.6

V

external rail)

V_DDA

analog 3.3 V pad supply

voltage

2.5

3.3

3.6

V

V_i(VBAT)

V_i(VREF)

input voltage on pin VBAT

input voltage on pin VREF

2.0^[2]

3.0

3.3

3.6

V

Standard port pins, RESET, RTCK

I_IL

LOW-level input current

HIGH-level input current

V_I= 0 V; no pull-up

-

3

µA

I_IH

I_OZ

V_I= V_DD; no-pull-down

OFF-state output current V_O= 0 V; V_O= V_DD; no

pull-up/down

I_latch

V_I

I/O latch-up current

−(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 °C

-

100

5.5

mA

V

[3][4][5]

input voltage

pin conﬁgured to provide a

digital function

0

V_O

output voltage

output active

0

-

V_DD

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

-

V

-

0.8

V

V_hys

V_OH

V_OL

I_OH

I_OL

0.4

-

V

[6]

[7]

HIGH-level output voltage I_OH= −4 mA

LOW-level output voltage I_OL= −4 mA

HIGH-level output current V_OH= V_DD− 0.4 V

LOW-level output current V_OL= 0.4 V

V_DD− 0.4

-

V

-

0.4

-

V

−4

4

-

mA

-

I_OHS

HIGH-level short-circuit

current

V_OH= 0 V

−45

[7]

I_OLS

LOW-level short-circuit

current

V_OL= V_DDA

-

50

mA

[8]

[9]

[8]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

−15

0

50

−50

0

150

−85

0

µA

V_I= 0 V

V_DD< V_I< 5 V

I_DD(act)

active mode supply

current

V_DD= 3.3 V; T_amb= 25 °C;

code

while(1){}

executed from ﬂash, no active

peripherals

CCLK = 10 MHz

CCLK = 60 MHz

-

10

-

mA

µA

40

-

I_DD(pd)

Power-down mode supply V_DD= 3.3 V; T_amb= 25 °C

60

-

current

V_DD= 3.3 V; T_amb= 85 °C

200

500

µA

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Single-chip 16/32-bit microcontrollers

Table 6.

Static characteristics …continued

T_amb= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_BATpd

Power-down mode battery RTC clock = 32 kHz

supply current^[10]

(from RTCX pins);

T

_amb= 25 °C

V_DD= 3.0 V; V_i(VBAT)= 2.5 V

V_DD= 3.0 V; V_i(VBAT)= 3.0 V

V_DD= 3.3 V; V_i(VBAT)= 3.3 V

V_DD= 3.6 V; V_i(VBAT)= 3.6 V

-

14

16

18

20

-

µA

I_BATact

active mode battery

supply current^[10]

CCLK = 60 MHz;

PCLK = 15 MHz;

PCLK enabled to RTCK;

RTC clock = 32 kHz

(from RTCX pins);

T

_amb= 25 °C

V_DD= 3.0 V; V_i(VBAT)= 3.0 V

V_DD= 3.3 V; V_i(VBAT)= 3.3 V

V_DD= 3.6 V; V_i(VBAT)= 3.6 V

-

78

80

82

-

µA

I_BATact(opt)optimized active mode

battery supply

PCLK disabled to RTCK in the

PCONP register;

RTC clock = 32 kHz

(from RTCX pins);

current^[10][11]

T

_amb= 25 °C; V_i(VBAT)= 3.3 V

CCLK = 6 MHz

-

21

23

27

30

-

µA

CCLK = 25 MHz

CCLK = 50 MHz

CCLK = 60 MHz

I²C-bus pins

[12]

V_IH

V_IL

V_hys

V_OL

I_LI

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

0.7V_DD

-

V

-

0.3V_DD

V

0.5V_DD

-

V

[6]

[13]

LOW-level output voltage I_OLS= 3 mA

-

0.4

4

V

input leakage current

V_I= V_DD

V_I= 5 V

2

µA

10

22

Oscillator pins

V_i(XTAL1)input voltage on pin

XTAL1

0

-

1.8

V

V_o(XTAL2)output voltage on pin

XTAL2

V_i(RTCX1)input voltage on pin

RTCX1

V_o(RTCX2)output voltage on pin

RTCX2

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] The RTC typically fails when V_i(VBAT)drops below 1.6 V.

[3] Including voltage on outputs in 3-state mode.

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NXP Semiconductors

Single-chip 16/32-bit microcontrollers

[4] V_DDsupply voltages must be present.

[5] 3-state outputs go into 3-state mode when V_DDis grounded.

[6] Accounts for 100 mV voltage drop in all supply lines.

[7] Only allowed for a short time period.

[8] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[9] Applies to P1.16 to P1.25.

[10] On pin VBAT.

[11] Optimized for low battery consumption.

[12] The input threshold voltage of I²C-bus pins meets the I²C-bus speciﬁcation, so an input voltage below 1.5 V will be recognized as a

logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.

[13] To V_SS

.

Table 7.

ADC static characteristics

V_DDA= 2.5 V to 3.6 V; T_amb= −40 °C to +85 °C, unless otherwise speciﬁed; ADC frequency 4.5 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

analog input voltage

0

-

C_ia

analog input

capacitance

pF

[1][2]

[3]

E_D

differential linearity error V_SSA= 0 V, V_DDA= 3.3 V

-

±1

LSB

%

E_L(adj)

E_O

integral non-linearity

offset error

V_SSA= 0 V, V_DDA= 3.3 V

±2

[4]

±3

[5]

E_G

gain error

±0.5

±4

[6]

E_T

absolute error

LSB

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 7.

[3] The integral no-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 7.

[4] The offset error (E_O) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 7.

[5] The gain error (E_G) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 7.

[6] The absolute voltage error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated A/D and the ideal transfer curve. See Figure 7.

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Single-chip 16/32-bit microcontrollers

offset

error

gain

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

V

− V

DDA SSA

1 LSB =

1024

002aac046

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 7. ADC characteristics

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LPC2131/32/34/36/38

R

vsi

20 kΩ

ADx.y

SAMPLE

3 pF

5 pF

V

EXT

V

SS

002aad452

Fig 8. Suggested ADC interface - LPC2131/32/34/36/38 ADx.y pin

9. Dynamic characteristics

Table 8.

Dynamic characteristics

T_amb= −40 °C to +85 °C for commercial applications, V_DDover speciﬁed ranges.^[1]

Symbol

External clock

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

10

40

-

25

100

-

MHz

ns

T_cy(clk)

t_CHCX

T

-

_cy(clk)× 0.4

ns

t_CLCX

_cy(clk)× 0.4

-

ns

t_CLCH

5

ns

t_CHCL

clock fall time

-

5

ns

Port pins (except P0.2 and P0.3)

t_r(o)

t_f(o)

output rise time

-

10

-

ns

output fall time

I²C-bus pins (P0.2 and P0.3)

[3]

t_f(o)output fall time

V_IHto V_IL

20 + 0.1 × C_b

-

ns

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[3] Bus capacitance C_bin pF, from 10 pF to 400 pF.

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LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

9.1 Timing

V

DD

− 0.5 V

0.2V

+ 0.9 V

DD

0.2V

− 0.1 V

DD

0.45 V

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

V_DD= 1.8 V.

Fig 9. External clock timing

9.2 LPC2138 power consumption measurements

002aab404

40

(1)

(2)

(3)

(4)

(5)

I

(mA)

DD

30

20

10

0

10

20

30

40

50

60

frequency (MHz)

Test conditions: code executed from ﬂash; all peripherals are enabled in PCONP register; PCLK = CCLK/4.

(1) V_DD= 3.6 V at −60 °C (max)

(2) V_DD= 3.6 V at 140 °C

(3) V_DD= 3.6 V at 25 °C

(4) V_DD= 3.3 V at 25 °C (typical)

(5) V_DD= 3.3 V at 95 °C (typical)

Fig 10. I_DD(act)measured at different frequencies (CCLK) and temperatures

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

32 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

002aab403

15

I

(mA)

10

DD

(1)

(2)

(3)

(4)

(5)

5

0

10

20

30

40

50

60

frequency (MHz)

Test conditions: Idle mode entered executing code from ﬂash; all peripherals are enabled in PCONP register;

PCLK = CCLK/4.

(1) V_DD= 3.6 V at 140 °C (max)

(2) V_DD= 3.6 V at −60 °C

(3) V_DD= 3.6 V at 25 °C

(4) V_DD= 3.3 V at 25 °C (typical)

(5) V_DD= 3.3 V at 95 °C (typical)

Fig 11. I_DDidle measured at different frequencies (CCLK) and temperatures

002aab405

500

I

(µA)

(1)

(2)

(3)

(4)

DD

400

300

200

100

0

−60

−20

20

60

100

140

temp °(C)

Test conditions: Power-down mode entered executing code from ﬂash; all peripherals are enabled in PCONP register.

(1) V_DD= 3.6 V

(2) V_DD= 3.3 V (max)

(3) V_DD= 3.0 V

(4) V_DD= 3.3 V (typical)

Fig 12. I_DD(pd)measured at different temperatures

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

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LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

10. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 13. Package outline SOT314-2 (LQFP64)

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

34 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals;

body 9 x 9 x 0.85 mm

SOT804-2

B

D

1

A

terminal 1

index area

A

4

A

E

1

c

A

1

detail X

C

e

1

y

v

M

C

A

B

C

1

b

e

1/2 e

w M

17

32

L

33

16

e

E

2

h

1/2 e

1

48

terminal 1

index area

49

64

X

D

h

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

c

D

E

e

L

v

w

y

1

2

1

4

1

h

1

h

max.

0.05 0.80 0.30

0.00 0.65 0.18

9.05 8.95 7.25 9.05 8.95 7.25

8.95 8.55 6.95 8.95 8.55 6.95

0.5

0.3

mm

1

0.2

0.5

7.5

0.1

0.05 0.05

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

04-03-25

SOT804-2

- - -

MO-220

- - -

Fig 14. Package outline SOT804-2 (HVQFN64)

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

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LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

11. Abbreviations

Table 9.

Acronym list

Description

Acronym

ADC

Analog-to-Digital Converter

BrownOut Detection

BOD

CPU

Central Processing Unit

Digital-to-Analog Converter

DAC

DCC

FIFO

GPIO

JTAG

PLL

Debug Communications Channel

First In, First Out

General Purpose Input/Output

Joint Test Action Group

Phase-Locked Loop

POR

PWM

RAM

SPI

Power-On Reset

Pulse Width Modulator

Random Access Memory

Serial Peripheral Interface

Static Random Access Memory

Synchronous Serial Port

Universal Asynchronous Receiver/Transmitter

VLSI Peripheral Bus

SRAM

SSP

UART

VPB

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

36 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

12. Revision history

Table 10. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC2131_32_34_36_38_4 20071016

Product data sheet

-

LPC2131_32_34_36_38_3

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Figure 1: changed incorrect character font

• Figure 5: added ﬁgure note

• Table 3: description for function AD1.3, pin 38, changed LPC2138 into LPC2134/36/38

• Figure 7: added

• Figure 9: added ﬁgure note

LPC2131_32_34_36_38_3 20060921

Product data sheet

-

LPC2131_32_34_36_38_2

LPC2131_32_34_36_38_2 20050318

Preliminary data sheet

LPC2131_2132_2138_1

-

LPC2131_2132_2138_1

20041118

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

37 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

13. Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

13.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

38 of 39

LPC2131/32/34/36/38

NXP Semiconductors

Single-chip 16/32-bit microcontrollers

15. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

6.18.1

6.18.2

6.18.3

6.18.4

6.18.5

6.18.6

6.18.7

6.18.8

6.18.9

6.19

Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 22

PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reset and wake-up timer . . . . . . . . . . . . . . . . 22

Brownout detector . . . . . . . . . . . . . . . . . . . . . 23

Code security . . . . . . . . . . . . . . . . . . . . . . . . . 23

External interrupt inputs. . . . . . . . . . . . . . . . . 23

Memory Mapping Control. . . . . . . . . . . . . . . . 23

Power Control. . . . . . . . . . . . . . . . . . . . . . . . . 24

VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Emulation and debugging. . . . . . . . . . . . . . . . 24

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 24

Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 25

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2

2.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Enhancements brought by LPC213x/01

devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features common for LPC213x and

2.2

LPC213x/01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3

3.1

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.19.1

6.19.2

6.19.3

6

6.1

6.2

6.3

6.4

6.5

6.5.1

6.6

6.7

6.7.1

6.7.2

6.8

6.8.1

6.8.2

6.9

6.9.1

6.10

6.10.1

6.10.2

6.11

6.11.1

6.12

6.12.1

6.13

6.13.1

6.14

Functional description . . . . . . . . . . . . . . . . . . 13

Architectural overview. . . . . . . . . . . . . . . . . . . 13

On-chip ﬂash program memory . . . . . . . . . . . 13

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 13

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 15

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 16

General purpose parallel I/O and Fast I/O . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Fast I/O features available in LPC213x/01 only 17

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ADC features available in LPC213x/01 only. . 17

10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

UART features available in LPC213x/01 only . 18

I²C-bus serial I/O controller . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SSP serial I/O controller . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General purpose timers/external event

7

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

Static characteristics . . . . . . . . . . . . . . . . . . . 27

9

9.1

9.2

Dynamic characteristics. . . . . . . . . . . . . . . . . 31

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

LPC2138 power consumption measurements 32

10

11

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 34

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 36

Revision history . . . . . . . . . . . . . . . . . . . . . . . 37

13

Legal information . . . . . . . . . . . . . . . . . . . . . . 38

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 38

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38

13.1

13.2

13.3

13.4

14

15

Contact information . . . . . . . . . . . . . . . . . . . . 38

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pulse width modulator . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

System control . . . . . . . . . . . . . . . . . . . . . . . . 22

6.14.1

6.15

6.15.1

6.16

6.16.1

6.17

6.17.1

6.18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 October 2007

Document identifier: LPC2131_32_34_36_38_4


型号：	LPC2132FHN64
厂家：	NXP
描述：	Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB ISP/IAP flash with 10-bit ADC and DAC 单芯片16位/ 32位微控制器; 32/64/128/256/512 KB ISP / IAP闪存与10位ADC和DAC 闪存微控制器
文件：	总39页 (文件大小：703K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC2132FHN64 [NXP]

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