LPC2142FBD64-S_技术文档

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB ﬂash

with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC

Rev. 04 — 17 November 2008

Product data sheet

1. General description

The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S

CPU with real-time emulation and embedded trace support, that combine the

microcontroller with embedded high-speed ﬂash memory ranging from 32 kB to 512 kB. A

128-bit wide memory interface and a unique accelerator architecture enable 32-bit code

execution at the maximum clock rate. For critical code size applications, the alternative

16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for

applications where miniaturization is a key requirement, such as access control and

point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device,

multiple UARTs, SPI, SSP to I²C-bus and on-chip SRAM of 8 kB up to 40 kB, make these

devices very well suited for communication gateways and protocol converters, soft

modems, voice recognition and low end imaging, providing both large buffer size and high

processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM

channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt

pins make these microcontrollers suitable for industrial control and medical systems.

2. Features

2.1 Key features

I 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

I 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip ﬂash memory.

128-bit wide interface/accelerator enables high-speed 60 MHz operation.

I In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot

loader software. Single ﬂash sector or full chip erase in 400 ms and programming of

256 B in 1 ms.

I EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software and high-speed tracing of instruction execution.

I USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.

In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA.

I One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14

analog inputs, with conversion times as low as 2.44 µs per channel.

I Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).

I Two 32-bit timers/external event counters (with four capture and four compare

channels each), PWM unit (six outputs) and watchdog.

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

I Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.

I Multiple serial interfaces including two UARTs (16C550), two Fast I²C-bus (400 kbit/s),

SPI and SSP with buffering and variable data length capabilities.

I Vectored Interrupt Controller (VIC) with conﬁgurable priorities and vector addresses.

I Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

I Up to 21 external interrupt pins available.

I 60 MHz maximum CPU clock available from programmable on-chip PLL with settling

time of 100 µs.

I On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz.

I Power saving modes include Idle and Power-down.

I Individual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization.

I Processor wake-up from Power-down mode via external interrupt or BOD.

I Single power supply chip with POR and BOD circuits:

N CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

pads.

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2141FBD64 LQFP64

LPC2142FBD64

plastic low proﬁle quad ﬂat package; 64 leads; SOT314-2

body 10 × 10 × 1.4 mm

LPC2144FBD64

LPC2146FBD64

LPC2148FBD64

3.1 Ordering options

Table 2.

Ordering options

Type number

Flash

memory

RAM

Endpoint

USB RAM

ADC (channels

overall)

DAC

Temperature

range

LPC2141FBD64

LPC2142FBD64

LPC2144FBD64

LPC2146FBD64

32 kB

8 kB

2 kB

1 (6 channels)

2 (14 channels)

-

−40 °C to +85 °C

64 kB

16 kB

1

128 kB

256 kB

32 kB + 8 kB shared with 2 kB

USB DMA^[1]

LPC2148FBD64

512 kB

32 kB + 8 kB shared with 2 kB

USB DMA^[1]

2 (14 channels)

1

−40 °C to +85 °C

[1] While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general

purpose RAM for data and code storage.

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

2 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

4. Block diagram

(1)

TMS

(1)

TDI

(1)

XTAL2

(1)

TRST

TCK

TDO

XTAL1

RST

LPC2141/42/44/46/48

PLL0

PLL1

TEST/DEBUG

INTERFACE

P0[31:28] and

P0[25:0]

SYSTEM

FUNCTIONS

system

clock

FAST GENERAL

PURPOSE I/O

ARM7TDMI-S

P1[31:16]

AHB BRIDGE

VECTORED

INTERRUPT

CONTROLLER

USB

clock

ARM7 local bus

AMBA AHB

(Advanced High-performance Bus)

INTERNAL

SRAM

CONTROLLER

INTERNAL

FLASH

CONTROLLER

AHB

DECODER

8 kB RAM

8 kB/16 kB/

32 kB

SRAM

32 kB/64 kB/128 kB/

256 kB/512 kB

FLASH

AHB TO APB

BRIDGE

APB

DIVIDER

SHARED WITH

(3)

USB DMA

D+

D−

UP_LED

CONNECT

VBUS

USB 2.0 FULL-SPEED

DEVICE CONTROLLER

EXTERNAL

INTERRUPTS

EINT3 to EINT0

(3)

WITH DMA

4 × CAP0

4 × CAP1

8 × MAT0

SCL0, SCL1

SDA0, SDA1

CAPTURE/COMPARE

(W/EXTERNAL CLOCK)

TIMER 0/TIMER 1

2

I C-BUS SERIAL

INTERFACES 0 AND 1

8 × MAT1

AD0[7:6] and

AD0[4:1]

SCK0, SCK1

A/D CONVERTERS

SPI AND SSP

SERIAL INTERFACES

MOSI0, MOSI1

MISO0, MISO1

SSEL0, SSEL1

(2)

0 AND 1

AD1[7:0]

TXD0, TXD1

RXD0, RXD1

(4)

D/A CONVERTER

UART0/UART1

AOUT

(2)

DSR1 ,CTS1

,

(2)

RTS1 , DTR1

(2)

DCD1 ,RI1

P0[31:28] and

P0[25:0]

RTXC1

RTXC2

VBAT

GENERAL

PURPOSE I/O

REAL-TIME CLOCK

P1[31:16]

WATCHDOG

TIMER

PWM6 to PWM0

PWM0

SYSTEM

CONTROL

002aab560

(1) Pins shared with GPIO.

(2) LPC2144/46/48 only.

(3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/48 only.

(4) LPC2142/44/46/48 only.

Fig 1. Block diagram

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

3 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

5. Pinning information

5.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

RTCX1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/EINT2

3

4

P1.19/TRACEPKT3

RTCX2

5

P1.21/PIPESTAT0

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4

P0.14/EINT1/SDA1

P1.22/PIPESTAT1

P0.13/MAT1.1

LPC2141

9

10

11

12

13

14

15

16

D+

D−

P0.12/MAT1.0

P1.17/TRACEPKT1

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.11/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.10/CAP1.0

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4

002aab733

Fig 2. LPC2141 pinning

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

4 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

RTCX1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/EINT2

3

4

P1.19/TRACEPKT3

RTCX2

5

P1.21/PIPESTAT0

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

D+

P0.14/EINT1/SDA1

P1.22/PIPESTAT1

P0.13/MAT1.1

LPC2142

9

10

11

12

13

14

15

16

D−

P0.12/MAT1.0

P1.17/TRACEPKT1

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.11/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.10/CAP1.0

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4

002aab734

Fig 3. LPC2142 pinning

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

5 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/AD1.6/CAP1.3

P0.22/AD1.7/CAP0.0/MAT0.0

RTCX1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/RI1/EINT2/AD1.5

P1.21/PIPESTAT0

3

4

P1.19/TRACEPKT3

RTCX2

5

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

D+

P0.14/DCD1/EINT1/SDA1

P1.22/PIPESTAT1

LPC2144/2146/2148

9

10

11

12

13

14

15

16

P0.13/DTR1/MAT1.1/AD1.4

P0.12/DSR1/MAT1.0/AD1.3

P0.11/CTS1/CAP1.1/SCL1

P1.23/PIPESTAT2

D−

P1.17/TRACEPKT1

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.10/RTS1/CAP1.0/AD1.2

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4/AD1.1

002aab735

Fig 4. LPC2144/46/48 pinning

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

6 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

5.2 Pin description

Table 3.

Symbol

Pin description

Type

Description

P0.0 to P0.31

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.

Total of 31 pins of the Port 0 can be used as a general purpose bidirectional

digital I/Os while P0.31 is output only pin. The operation of port 0 pins

depends upon the pin function selected via the pin connect block.

Pins P0.24, P0.26 and P0.27 are not available.

P0.0 — General purpose input/output digital pin (GPIO).

TXD0 — Transmitter output for UART0.

P0.0/TXD0/

PWM1

19^[1]

I/O

O

PWM1 — Pulse Width Modulator output 1.

P0.1/RXD0/

PWM3/EINT0

21^[2]

I/O

I

P0.1 — General purpose input/output digital pin (GPIO).

RXD0 — Receiver input for UART0.

O

PWM3 — Pulse Width Modulator output 3.

I

EINT0 — External interrupt 0 input.

P0.2/SCL0/

CAP0.0

22^[3]

I/O

I

P0.2 — General purpose input/output digital pin (GPIO).

SCL0 — I²C0 clock input/output. Open-drain output (for I²C-bus compliance).

CAP0.0 — Capture input for Timer 0, channel 0.

P0.3 — General purpose input/output digital pin (GPIO).

SDA0 — I²C0 data input/output. Open-drain output (for I²C-bus compliance).

MAT0.0 — Match output for Timer 0, channel 0.

EINT1 — External interrupt 1 input.

P0.3/SDA0/

MAT0.0/EINT1

26^[3]

I/O

O

I

P0.4/SCK0/

CAP0.1/AD0.6

27^[4]

I/O

I

P0.4 — General purpose input/output digital pin (GPIO).

SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

CAP0.1 — Capture input for Timer 0, channel 1.

AD0.6 — ADC 0, input 6.

I

P0.5/MISO0/

MAT0.1/AD0.7

29^[4]

I/O

P0.5 — General purpose input/output digital pin (GPIO).

MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data

output from SPI slave.

O

MAT0.1 — Match output for Timer 0, channel 1.

AD0.7 — ADC 0, input 7.

I

P0.6/MOSI0/

CAP0.2/AD1.0

30^[4]

I/O

P0.6 — General purpose input/output digital pin (GPIO).

MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.

I

CAP0.2 — Capture input for Timer 0, channel 2.

AD1.0 — ADC 1, input 0. Available in LPC2144/46/48 only.

P0.7 — General purpose input/output digital pin (GPIO).

SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

PWM2 — Pulse Width Modulator output 2.

I

P0.7/SSEL0/

PWM2/EINT2

31^[2]

I/O

I

O

I

EINT2 — External interrupt 2 input.

P0.8/TXD1/

PWM4/AD1.1

33^[4]

I/O

O

I

P0.8 — General purpose input/output digital pin (GPIO).

TXD1 — Transmitter output for UART1.

PWM4 — Pulse Width Modulator output 4.

AD1.1 — ADC 1, input 1. Available in LPC2144/46/48 only.

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

7 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3.

Symbol

Pin description …continued

Type

Description

P0.9/RXD1/

PWM6/EINT3

34^[2]

I/O

I

P0.9 — General purpose input/output digital pin (GPIO).

RXD1 — Receiver input for UART1.

O

I

PWM6 — Pulse Width Modulator output 6.

EINT3 — External interrupt 3 input.

P0.10/RTS1/

CAP1.0/AD1.2

35^[4]

37^[3]

38^[4]

39^[4]

41^[3]

I/O

O

I

P0.10 — General purpose input/output digital pin (GPIO).

RTS1 — Request to Send output for UART1. LPC2144/46/48 only.

CAP1.0 — Capture input for Timer 1, channel 0.

I

AD1.2 — ADC 1, input 2. Available in LPC2144/46/48 only.

P0.11 — General purpose input/output digital pin (GPIO).

CTS1 — Clear to Send input for UART1. Available in LPC2144/46/48 only.

CAP1.1 — Capture input for Timer 1, channel 1.

SCL1 — I²C1 clock input/output. Open-drain output (for I²C-bus compliance)

P0.12 — General purpose input/output digital pin (GPIO).

DSR1 — Data Set Ready input for UART1. Available in LPC2144/46/48 only.

MAT1.0 — Match output for Timer 1, channel 0.

P0.11/CTS1/

CAP1.1/SCL1

I/O

I

I/O

I

P0.12/DSR1/

MAT1.0/AD1.3

O

I

AD1.3 — ADC 1 input 3. Available in LPC2144/46/48 only.

P0.13 — General purpose input/output digital pin (GPIO).

DTR1 — Data Terminal Ready output for UART1. LPC2144/46/48 only.

MAT1.1 — Match output for Timer 1, channel 1.

P0.13/DTR1/

MAT1.1/AD1.4

I/O

O

I

AD1.4 — ADC 1 input 4. Available in LPC2144/46/48 only.

P0.14 — General purpose input/output digital pin (GPIO).

DCD1 — Data Carrier Detect input for UART1. LPC2144/46/48 only.

EINT1 — External interrupt 1 input.

P0.14/DCD1/

EINT1/SDA1

I/O

I

I/O

SDA1 — I²C1 data input/output. Open-drain output (for I²C-bus compliance).

Note: LOW on this pin while RESET is LOW forces on-chip boot loader to

take over control of the part after reset.

P0.15/RI1/

EINT2/AD1.5

45^[4]

I/O

P0.15 — General purpose input/output digital pin (GPIO).

RI1 — Ring Indicator input for UART1. Available in LPC2144/46/48 only.

EINT2 — External interrupt 2 input.

I

AD1.5 — ADC 1, input 5. Available in LPC2144/46/48 only.

P0.16 — General purpose input/output digital pin (GPIO).

EINT0 — External interrupt 0 input.

P0.16/EINT0/

46^[2]

I/O

I

MAT0.2/CAP0.2

O

I

MAT0.2 — Match output for Timer 0, channel 2.

CAP0.2 — Capture input for Timer 0, channel 2.

P0.17/CAP1.2/ 47^[1]

SCK1/MAT1.2

I/O

I

P0.17 — General purpose input/output digital pin (GPIO).

CAP1.2 — Capture input for Timer 1, channel 2.

I/O

O

SCK1 — Serial Clock for SSP. Clock output from master or input to slave.

MAT1.2 — Match output for Timer 1, channel 2.

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

8 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3.

Symbol

P0.18/CAP1.3/ 53^[1]

MISO1/MAT1.3

Pin description …continued

Type

I/O

I

Description

P0.18 — General purpose input/output digital pin (GPIO).

CAP1.3 — Capture input for Timer 1, channel 3.

I/O

MISO1 — Master In Slave Out for SSP. Data input to SPI master or data

output from SSP slave.

O

MAT1.3 — Match output for Timer 1, channel 3.

P0.19 — General purpose input/output digital pin (GPIO).

MAT1.2 — Match output for Timer 1, channel 2.

P0.19/MAT1.2/ 54^[1]

MOSI1/CAP1.2

I/O

O

I/O

MOSI1 — Master Out Slave In for SSP. Data output from SSP master or data

input to SSP slave.

I

CAP1.2 — Capture input for Timer 1, channel 2.

P0.20 — General purpose input/output digital pin (GPIO).

MAT1.3 — Match output for Timer 1, channel 3.

SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.

EINT3 — External interrupt 3 input.

P0.20/MAT1.3/ 55^[2]

SSEL1/EINT3

I/O

O

I

P0.21/PWM5/

AD1.6/CAP1.3

1^[4]

I/O

P0.21 — General purpose input/output digital pin (GPIO).

PWM5 — Pulse Width Modulator output 5.

O

I

AD1.6 — ADC 1, input 6. Available in LPC2144/46/48 only.

CAP1.3 — Capture input for Timer 1, channel 3.

P0.22 — General purpose input/output digital pin (GPIO).

AD1.7 — ADC 1, input 7. Available in LPC2144/46/48 only.

CAP0.0 — Capture input for Timer 0, channel 0.

MAT0.0 — Match output for Timer 0, channel 0.

P0.23 — General purpose input/output digital pin (GPIO).

V_BUS— Indicates the presence of USB bus power.

Note: This signal must be HIGH for USB reset to occur.

P0.25 — General purpose input/output digital pin (GPIO).

AD0.4 — ADC 0, input 4.

I

P0.22/AD1.7/

2^[4]

I/O

CAP0.0/MAT0.0

I

O

I/O

I

P0.23/V_BUS

58^[1]

P0.25/AD0.4/

AOUT

9^[5]

I/O

I

O

AOUT — DAC output. Available in LPC2142/44/46/48 only.

P0.28 — General purpose input/output digital pin (GPIO).

AD0.1 — ADC 0, input 1.

P0.28/AD0.1/

13^[4]

I/O

CAP0.2/MAT0.2

I

CAP0.2 — Capture input for Timer 0, channel 2.

MAT0.2 — Match output for Timer 0, channel 2.

P0.29 — General purpose input/output digital pin (GPIO).

AD0.2 — ADC 0, input 2.

O

P0.29/AD0.2/

14^[4]

I/O

CAP0.3/MAT0.3

I

CAP0.3 — Capture input for Timer 0, channel 3.

MAT0.3 — Match output for Timer 0, channel 3.

P0.30 — General purpose input/output digital pin (GPIO).

AD0.3 — ADC 0, input 3.

O

P0.30/AD0.3/

15^[4]

I/O

EINT3/CAP0.0

I

EINT3 — External interrupt 3 input.

CAP0.0 — Capture input for Timer 0, channel 0.

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

9 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3.

Symbol

P0.31/UP_LED/ 17^[6]

CONNECT

Pin description …continued

Type

O

Description

P0.31 — General purpose output only digital pin (GPO).

O

UP_LED — USB GoodLink LED indicator. It is LOW when device is

conﬁgured (non-control endpoints enabled). It is HIGH when the device is not

conﬁgured or during global suspend.

O

CONNECT — Signal used to switch an external 1.5 kΩ resistor under the

software control. Used with the SoftConnect USB feature.

Important: This is an digital output only pin. This pin MUST NOT be

externally pulled LOW when RESET pin is LOW or the JTAG port will be

disabled.

P1.0 to P1.31

I/O

Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 1 pins depends upon the pin function

selected via the pin connect block. Pins 0 through 15 of port 1 are not

available.

P1.16/

TRACEPKT0

16^[6]

12^[6]

8^[6]

P1.16 — General purpose input/output digital pin (GPIO). Standard I/O port

with internal pull-up.

O

TRACEPKT0 — Trace Packet, bit 0.

P1.17/

TRACEPKT1

I/O

P1.17 — General purpose input/output digital pin (GPIO). Standard I/O port

with internal pull-up.

O

TRACEPKT1 — Trace Packet, bit 1.

P1.18/

I/O

P1.18 — General purpose input/output digital pin (GPIO). Standard I/O port

TRACEPKT2

with internal pull-up.

O

TRACEPKT2 — Trace Packet, bit 2.

P1.19/

4^[6]

I/O

P1.19 — General purpose input/output digital pin (GPIO). Standard I/O port

TRACEPKT3

with internal pull-up.

O

TRACEPKT3 — Trace Packet, bit 3.

P1.20/

48^[6]

I/O

P1.20 — General purpose input/output digital pin (GPIO). Standard I/O port

TRACESYNC

with internal pull-up.

O

TRACESYNC — Trace Synchronization.

Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to

operate as Trace port after reset.

P1.21/

PIPESTAT0

44^[6]

40^[6]

36^[6]

32^[6]

I/O

P1.21 — General purpose input/output digital pin (GPIO). Standard I/O port

with internal pull-up.

O

PIPESTAT0 — Pipeline Status, bit 0.

P1.22/

PIPESTAT1

I/O

P1.22 — General purpose input/output digital pin (GPIO). Standard I/O port

with internal pull-up.

O

PIPESTAT1 — Pipeline Status, bit 1.

P1.23/

PIPESTAT2

I/O

P1.23 — General purpose input/output digital pin (GPIO). Standard I/O port

with internal pull-up.

O

PIPESTAT2 — Pipeline Status, bit 2.

P1.24/

I/O

P1.24 — General purpose input/output digital pin (GPIO). Standard I/O port

TRACECLK

with internal pull-up.

O

TRACECLK — Trace Clock.

P1.25/EXTIN0 28^[6]

I/O

P1.25 — General purpose input/output digital pin (GPIO). Standard I/O port

with internal pull-up.

I

EXTIN0 — External Trigger Input.

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Single-chip 16-bit/32-bit microcontrollers

Table 3.

Pin description …continued

Symbol

24^[6]

Type

I/O

Description

P1.26/RTCK

P1.26 — General purpose input/output digital pin (GPIO).

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bidirectional pin with internal pull-up.

Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate

as Debug port after reset.

P1.27/TDO

P1.28/TDI

P1.29/TCK

64^[6]

60^[6]

56^[6]

I/O

O

P1.27 — General purpose input/output digital pin (GPIO).

TDO — Test Data out for JTAG interface.

I/O

I

P1.28 — General purpose input/output digital pin (GPIO).

TDI — Test Data in for JTAG interface.

I/O

I

P1.29 — General purpose input/output digital pin (GPIO).

TCK — Test Clock for JTAG interface. This clock must be slower than ¹⁄₆of

the CPU clock (CCLK) for the JTAG interface to operate.

P1.30/TMS

P1.31/TRST

52^[6]

20^[6]

I/O

I

P1.30 — General purpose input/output digital pin (GPIO).

TMS — Test Mode Select for JTAG interface.

P1.31 — General purpose input/output digital pin (GPIO).

TRST — Test Reset for JTAG interface.

USB bidirectional D+ line.

I/O

I

D+

10^[7]

11^[7]

57^[8]

I/O

I

D−

USB bidirectional D− line.

RESET

External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

RTCX1

RTCX2

V_SS

62^[9]

61^[9]

3^[9]

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator ampliﬁer.

O

I

Input to the RTC oscillator circuit.

5^[9]

O

I

Output from the RTC oscillator circuit.

Ground: 0 V reference.

6, 18, 25, 42,

50

V_SSA

V_DD

59

I

Analog ground: 0 V reference. This should nominally be the same voltage

as V_SS, but should be isolated to minimize noise and error.

23, 43, 51

7

3.3 V power supply: This is the power supply voltage for the core and I/O

ports.

V_DDA

Analog 3.3 V power supply: This should be nominally the same voltage as

V_DDbut should be isolated to minimize noise and error. This voltage is only

used to power the on-chip ADC(s) and DAC.

VREF

VBAT

63

49

I

ADC reference voltage: This should be nominally less than or equal to the

V_DDvoltage but should be isolated to minimize noise and error. Level on this

pin is used as a reference for ADC(s) and DAC.

RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC.

[1] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If

conﬁgured for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[3] Open-drain 5 V tolerant digital I/O I²C-bus 400 kHz speciﬁcation compatible pad. It requires external pull-up to provide an output

functionality.

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[4] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog

input function. If conﬁgured for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When

conﬁgured as an ADC input, digital section of the pad is disabled.

[5] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog

output function. When conﬁgured as the DAC output, digital section of the pad is disabled.

[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value typically ranges from 60 kΩ to 300 kΩ.

[7] Pad is designed in accordance with the Universal Serial Bus (USB) speciﬁcation, revision 2.0 (Full-speed and Low-speed mode only).

[8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

[9] Pad provides special analog functionality.

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6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers (CISC). This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective processor

core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

The particular ﬂash implementation in the LPC2141/42/44/46/48 allows for full speed

execution also in ARM mode. It is recommended to program performance critical and

short code sections (such as interrupt service routines and DSP algorithms) in ARM

mode. The impact on the overall code size will be minimal but the speed can be increased

by 30 % over Thumb mode.

6.2 On-chip ﬂash program memory

The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB ﬂash

memory system respectively. This memory may be used for both code and data storage.

Programming of the ﬂash memory may be accomplished in several ways. It may be

programmed In System via the serial port. The application program may also erase and/or

program the ﬂash while the application is running, allowing a great degree of ﬂexibility for

data storage ﬁeld ﬁrmware upgrades, etc. Due to the architectural solution chosen for an

on-chip boot loader, ﬂash memory available for user’s code on LPC2141/42/44/46/48 is

32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.

The LPC2141/42/44/46/48 ﬂash memory provides a minimum of 100000 erase/write

cycles and 20 years of data-retention.

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6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48

provide 8 kB, 16 kB and 32 kB of static RAM respectively.

In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the

USB can also be used as a general purpose RAM for data storage and code storage and

execution.

6.4 Memory map

The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown

in Figure 5.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either

ﬂash memory (the default) or on-chip static RAM. This is described in Section 6.19

“System control”.

4.0 GB

0xFFFF FFFF

AHB PERIPHERALS

0xF000 0000

0xE000 0000

3.75 GB

3.5 GB

VPB PERIPHERALS

3.0 GB

2.0 GB

RESERVED ADDRESS SPACE

0xC000 0000

0x8000 0000

0x7FFF FFFF

BOOT BLOCK (12 kB REMAPPED FROM

ON-CHIP FLASH MEMORY

0x7FFF D000

0x7FFF CFFF

RESERVED ADDRESS SPACE

0x7FD0 2000

0x7FD0 1FFF

8 kB ON-CHIP USB DMA RAM (LPC2146/2148)

RESERVED ADDRESS SPACE

0x7FD0 0000

0x7FCF FFFF

0x4000 8000

0x4000 7FFF

32 kB ON-CHIP STATIC RAM (LPC2146/2148)

16 kB ON-CHIP STATIC RAM (LPC2142/2144)

8 kB ON-CHIP STATIC RAM (LPC2141)

RESERVED ADDRESS SPACE

0x4000 4000

0x4000 3FFF

0x4000 2000

0x4000 1FFF

0x4000 0000

0x3FFF FFFF

1.0 GB

0x0008 0000

0x0007 FFFF

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2148)

0x0004 0000

0x0003 FFFF

TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2146)

0x0002 0000

0x0001 FFFF

TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2144)

0x0001 0000

0x0000 FFFF

TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2142)

0x0000 8000

0x0000 7FFF

TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2141)

0x0000 0000

0.0 GB

002aab558

Fig 5. LPC2141/42/44/46/48 memory map

Rev. 04 — 17 November 2008

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6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as deﬁned by programmable settings. The programmable assignment

scheme means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then

the FIQ service routine does not need to branch into the interrupt service routine but can

run from the interrupt vector location. If more than one request is assigned to the FIQ

class, the FIQ service routine will read a word from the VIC that identiﬁes which FIQ

source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC

provides the address of the highest-priority requesting IRQs service routine, otherwise it

provides the address of a default routine that is shared by all the non-vectored IRQs. The

default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt

Controller, but may have several internal interrupt ﬂags. Individual interrupt ﬂags may also

represent more than one interrupt source.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

The Pin Control Module with its pin select registers deﬁnes the functionality of the

microcontroller in a given hardware environment.

After reset all pins of Port 0 and Port 1 are conﬁgured as input with the following

exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if

trace is enabled, the Trace pins will assume their trace functionality. The pins associated

with the I²C0 and I²C1 interface are open drain.

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6.7 Fast general purpose parallel I/O (GPIO)

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices:

• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.8 10-bit ADC

The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital

converters. These converters are single 10-bit successive approximation analog to digital

converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total

number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.

6.8.1 Features

• 10 bit successive approximation analog to digital converter.

• Measurement range of 0 V to VREF (2.0 V ≤ VREF ≤ V_DDA).

• Each converter capable of performing more than 400000 10-bit samples per second.

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or timer match signal.

• Global Start command for both converters (LPC2142/44/46/48 only).

6.9 10-bit DAC

The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The

maximum DAC output voltage is the VREF voltage.

6.9.1 Features

• 10-bit DAC.

• Buffered output.

• Power-down mode available.

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• Selectable speed versus power.

6.10 USB 2.0 device controller

The USB is a 4-wire serial bus that supports communication between a host and a

number (127 max) of peripherals. The host controller allocates the USB bandwidth to

attached devices through a token based protocol. The bus supports hot plugging,

unplugging, and dynamic conﬁguration of the devices. All transactions are initiated by the

host controller.

The LPC2141/42/44/46/48 is equipped with a USB device controller that enables

12 Mbit/s data exchange with a USB host controller. It consists of a register interface,

serial interface engine, endpoint buffer memory and DMA controller. The serial interface

engine decodes the USB data stream and writes data to the appropriate end point buffer

memory. The status of a completed USB transfer or error condition is indicated via status

registers. An interrupt is also generated if enabled.

A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint

buffer and the USB RAM.

6.10.1 Features

• Fully compliant with USB 2.0 Full-speed speciﬁcation.

• Supports 32 physical (16 logical) endpoints.

• Supports control, bulk, interrupt and isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint maximum packet size selection (up to USB maximum speciﬁcation) by

software at run time.

• RAM message buffer size based on endpoint realization and maximum packet size.

• Supports SoftConnect and GoodLink LED indicator. These two functions are sharing

one pin.

• Supports bus-powered capability with low suspend current.

• Supports DMA transfer on all non-control endpoints (LPC2146/48 only).

• One duplex DMA channel serves all endpoints (LPC2146/48 only).

• Allows dynamic switching between CPU controlled and DMA modes (only in

LPC2146/48).

• Double buffer implementation for bulk and isochronous endpoints.

6.11 UARTs

The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and

receive data lines, the LPC2144/46/48 UART1 also provides a full modem control

handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48

introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers

to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz.

In addition, auto-CTS/RTS ﬂow-control functions are fully implemented in hardware

(UART1 in LPC2144/46/48 only).

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6.11.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Transmission FIFO control enables implementation of software (XON/XOFF) ﬂow

control on both UARTs.

• LPC2144/46/48 UART1 equipped with standard modem interface signals. This

module also provides full support for hardware ﬂow control (auto-CTS/RTS).

6.12 I²C-bus serial I/O controller

The LPC2141/42/44/46/48 each contain two I²C-bus controllers.

The I²C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory)). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I²C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s

(Fast I²C-bus).

6.12.1 Features

• Compliant with standard I²C-bus interface.

• Easy to conﬁgure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

6.13 SPI serial I/O controller

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial

interface, designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends a byte of data to the slave, and

the slave always sends a byte of data to the master.

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6.13.1 Features

• Compliant with SPI speciﬁcation.

• Synchronous, Serial, Full Duplex, Communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.14 SSP serial I/O controller

The LPC2141/42/44/46/48 each contain one Serial Synchronous Port controller (SSP).

The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. However, only a single master and a

single slave can communicate on the bus during a given data transfer. The SSP supports

full duplex transfers, with data frames of 4 bits to 16 bits of data ﬂowing from the master to

the slave and from the slave to the master. Often only one of these data ﬂows carries

meaningful data.

6.14.1 Features

• Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s

Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.15 General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

6.15.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• External event counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

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– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.16 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.16.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T_cy(PCLK)× 256 × 4) to (T_cy(PCLK)× 2³²× 4) in multiples of

T

_cy(PCLK)× 4.

6.17 Real-time clock

The RTC is designed to provide a set of counters to measure time when normal or idle

operating mode is selected. The RTC has been designed to use little power, making it

suitable for battery powered systems where the CPU is not running continuously (Idle

mode).

6.17.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. Programmable reference clock divider

allows ﬁne adjustment of the RTC.

• Dedicated power supply pin can be connected to a battery or the main 3.3 V.

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6.18 Pulse width modulator

The PWM is based on the standard timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed

to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or

perform other actions when speciﬁed timer values occur, based on seven match registers.

The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

With double edge controlled PWM outputs, speciﬁc match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.18.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.19 System control

6.19.1 Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz.

The oscillator output frequency is called f_oscand the ARM processor clock frequency is

referred to as CCLK for purposes of rate equations, etc. f_oscand CCLK are the same value

unless the PLL is running and connected. Refer to Section 6.19.2 “PLL” for additional

information.

6.19.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and

bypassed following a chip reset and may be enabled by software. The program must

conﬁgure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a

clock source. The PLL settling time is 100 µs.

6.19.3 Reset and wake-up timer

Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset.

The RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of

chip reset by any source starts the Wake-up Timer (see Wake-up Timer description

below), causing the internal chip reset to remain asserted until the external reset is

de-asserted, the oscillator is running, a ﬁxed number of clocks have passed, and the

on-chip ﬂash controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is important at power on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

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Single-chip 16-bit/32-bit microcontrollers

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DDramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.19.4 Brownout detector

The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the V_DDpins. If

this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal

can be enabled for interrupt; if not, software can monitor the signal by reading dedicated

register.

The second stage of low voltage detection asserts reset to inactivate the

LPC2141/42/44/46/48 when the voltage on the V_DDpins falls below 2.6 V. This reset

prevents alteration of the ﬂash as operation of the various elements of the chip would

otherwise become unreliable due to low voltage. The BOD circuit maintains this reset

down below 1 V, at which point the POR circuitry maintains the overall reset.

Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event

loop to sense the condition.

6.19.5 Code security

This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be

debugged or protected from observation.

If after reset on-chip boot loader detects a valid checksum in ﬂash and reads 0x8765 4321

from address 0x1FC in ﬂash, debugging will be disabled and thus the code in ﬂash will be

protected from observation. Once debugging is disabled, it can be enabled only by

performing a full chip erase using the ISP.

6.19.6 External interrupt inputs

The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt

Inputs as selectable pin functions. When the pins are combined, external events can be

processed as four independent interrupt signals. The External Interrupt Inputs can

optionally be used to wake-up the processor from Power-down mode.

Additionally capture input pins can also be used as external interrupts without the option

to wake the device up from Power-down mode.

6.19.7 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

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6.19.8 Power control

The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and

Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip

RTC will enable the microcontroller to have the RTC active during Power-down mode.

Power-down current is increased with RTC active. However, it is signiﬁcantly lower than in

Idle mode.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings during active

and Idle mode.

6.19.9 APB bus

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the APB bus may be

slowed down to ¹⁄₂to ¹⁄₄of the processor clock rate. Because the APB bus must work

properly at power-up (and its timing cannot be altered if it does not work since the APB

divider control registers reside on the APB bus), the default condition at reset is for the

APB bus to run at ¹⁄₄of the processor clock rate. The second purpose of the APB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the APB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

6.20 Emulation and debugging

The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A

trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on Port 1. This means that all communication, timer and

interface peripherals residing on Port 0 are available during the development and

debugging phase as they are when the application is run in the embedded system itself.

6.20.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote

debug protocol commands to the JTAG data needed to access the ARM core.

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Single-chip 16-bit/32-bit microcontrollers

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC

allows a program running on the target to communicate with the host debugger or another

separate host without stopping the program ﬂow or even entering the debug state. The

DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S

core. The DCC allows the JTAG port to be used for sending and receiving data without

affecting the normal program ﬂow. The DCC data and control registers are mapped in to

addresses in the EmbeddedICE logic.

This clock must be slower than ¹⁄₆of the CPU clock (CCLK) for the JTAG interface to

operate.

6.20.2 Embedded trace

Since the LPC2141/42/44/46/48 have signiﬁcant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the

external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability

for deeply embedded processor cores. It outputs information about processor execution to

the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code can not be traced

because of this restriction.

6.20.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2141/42/44/46/48 contain a speciﬁc

conﬁguration of RealMonitor software programmed into the on-chip ﬂash memory.

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Single-chip 16-bit/32-bit microcontrollers

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD

Parameter

Conditions

Min

Max

+3.6

+4.6

+5.1

Unit

V

supply voltage (core and external rail)

analog 3.3 V pad supply voltage

input voltage on pin VBAT

input voltage on pin VREF

analog input voltage

−0.5

V_DDA

V

V_i(VBAT)

V_i(VREF)

V_IA

for the RTC

V

on ADC related

pins

V

[2]

V_I

input voltage

5 V tolerant I/O

pins; only valid

when the V_DD

supply voltage is

present

−0.5

+6.0

V

[2][3]

[4]

other I/O pins

per supply pin

per ground pin

−0.5

V_DD+ 0.5

100

V

I_DD

supply current

-

mA

°C

W

[4]

I_SS

ground current

-

100

[5]

T_stg

storage temperature

total power dissipation (per package)

−65

+150

1.5

P_tot(pack)

based on package

heat transfer, not

device power

-

consumption

[6]

V_esd

electrostatic discharge voltage

human body model

all pins

−4000

+4000

V

[1] The following applies to the Limiting values:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] Dependent on package type.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

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LPC2141/42/44/46/48

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Single-chip 16-bit/32-bit microcontrollers

8. Static characteristics

Table 5.

Static characteristics

T_amb= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol

V_DD

Parameter

Conditions

Min

3.0

2.0

Typ^[1]

3.3

Max

3.6

Unit

V

[2]

[3]

supply voltage

analog supply voltage

V_DDA

3.3 V pad

3.3

V

V_i(VBAT)

input voltage on pin

VBAT

3.3

V

V_i(VREF)

input voltage on pin

VREF

2.5

3.3

V_DDA

V

Standard port pins, RESET, RTCK

I_IL

LOW-level input current V_I= 0 V; no pull-up

HIGH-level input current V_I= V_DD; no pull-down

-

3

µA

I_IH

I_OZ

OFF-state output

current

V_O= 0 V; V_O= V_DD; no

pull-up/down

I_latch

I/O latch-up current

−(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 °C

-

100

5.5

mA

V

[4][5][6]

[7]

V_I

input voltage

pin conﬁgured to provide a

digital function

0

V_O

output voltage

output active

0

-

V_DD

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

-

0.8

V_hys

V_OH

0.4

-

[8]

[9]

HIGH-level output

voltage

I_OH= −4 mA

V

_DD− 0.4

V_OL

I_OH

LOW-level output

voltage

I_OL= −4 mA

-

0.4

-

V

HIGH-level output

current

V_OH= V_DD− 0.4 V

V_OL= 0.4 V

−4

4

-

mA

I_OL

LOW-level output

current

-

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

−45

50

LOW-level short-circuit V_OL= V_DDA

output current

-

[10]

[11]

[10]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

−15

0

50

−50

0

150

−85

0

µA

V_I= 0 V

V_DD< V_I< 5 V

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LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 5.

Static characteristics …continued

T_amb= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_DD(act)

active mode supply

current

V_DD= 3.3 V; T_amb= 25 °C;

code

-

15

50

while(1){}

executed from ﬂash, no active

peripherals

CCLK = 10 MHz

CCLK = 60 MHz

mA

-

40

27

70

V_DD= 3.3 V; T_amb= 25 °C;

code executed from ﬂash; USB

enabled and active; all other

peripherals disabled

CCLK = 12 MHz

mA

µA

CCLK = 60 MHz

-

57

90

I_DD(pd)

Power-down mode

supply current

V_DD= 3.3 V; T_amb= 25 °C

V_DD= 3.3 V; T_amb= 85 °C

40

100

500

30

250

15

µA

[12]

I_BATpd

Power-down mode

RTC clock = 32 kHz

(from RTCX pins);

_amb= 25 °C

battery supply current

T

V_DD= 3.0 V; V_i(VBAT)= 2.5 V

V_DD= 3.0 V; V_i(VBAT)= 3.0 V

µA

-

20

78

40

-

I_BATact

active mode battery

supply current

CCLK = 60 MHz;

PCLK = 15 MHz;

PCLK enabled to RTCK;

RTC clock = 32 kHz

(from RTCX pins);

T

_amb= 25 °C

V_DD= 3.0 V; V_i(VBAT)= 3.0 V

µA

[12][13]

I_BATact(opt)optimized active mode

battery supply current

PCLK disabled to RTCK in the

PCONP register;

RTC clock = 32 kHz

(from RTCX pins);

-

23

30

-

T

_amb= 25 °C; V_i(VBAT)= 3.3 V

CCLK = 25 MHz

µA

CCLK = 60 MHz

I²C-bus pins

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

0.7V_DD

-

V

-

0.3V_DD

V_hys

V_OL

0.5V_DD

-

[8]

LOW-level output

voltage

I_OLS= 3 mA

0.4

[14]

I_LI

input leakage current

V_I= V_DD

V_I= 5 V

-

2

4

µA

10

22

Oscillator pins

V_i(XTAL1)input voltage on pin

XTAL1

0

-

1.8

V

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LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 5.

Static characteristics …continued

T_amb= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_o(XTAL2)

output voltage on pin

XTAL2

0

-

1.8

V

V_i(RTCX1)

input voltage on pin

RTCX1

0

-

1.8

V

V_o(RTCX2)output voltage on pin

RTCX2

USB pins

I_OZ

OFF-state output

current

0 V < V_I< 3.3 V

-

±10

5.25

-

µA

V

V_BUS

V_DI

V_CM

V_th(rs)se

V_BUSline input voltage

on the USB connector

-

differential input

sensitivity

|(D+) − (D−)|

0.2

0.8

V

differential

common-mode range

includes V_DIrange

2.5

2.0

V

single-ended receiver

switching threshold

voltage

V

V_OL

LOW output level

HIGH output level

R_Lof 1.5 kΩ to 3.6 V

R_Lof 15 kΩ to GND

-

0.3

3.6

20

V

V_OH

2.8

-

V

C_trans

Z_DRV

transceiver capacitance pin to GND

pF

Ω

[15]

driver output impedance steady state drive

for driver which is not

29

44

high-speed capable

R_pu

pull-up resistance

SoftConnect = ON

1.1

-

1.9

kΩ

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] Core and external rail.

[3] The RTC typically fails when V_i(VBAT)drops below 1.6 V.

[4] Including voltage on outputs in 3-state mode.

[5] V_DDsupply voltages must be present.

[6] 3-state outputs go into 3-state mode when V_DDis grounded.

[7] Please also see the errata note mentioned in errata sheet.

[8] Accounts for 100 mV voltage drop in all supply lines.

[9] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[10] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[11] Applies to P1.16 to P1.31.

[12] On pin VBAT.

[13] Optimized for low battery consumption.

[14] To V_SS

.

[15] Includes external resistors of 18 Ω 1 % on D+ and D−.

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LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 6.

ADC static characteristics

V_DDA= 2.5 V to 3.6 V; T_amb= −40 °C to +85 °C unless otherwise speciﬁed; ADC frequency 4.5 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

C_ia

pF

[1][2]

[3]

E_D

V_SSA= 0 V, V_DDA= 3.3 V

±1

LSB

%

E_L(adj)

E_O

±2

[4]

±3

[5]

E_G

gain error

±0.5

±4

[6]

E_T

absolute error

LSB

kΩ

[7]

R_vsi

voltage source interface

resistance

40

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 6.

[3] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 6.

[4] The offset error (E_O) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 6.

[5] The gain error (E_G) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 6.

[6] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC

and the ideal transfer curve. See Figure 6.

[7] See Figure 7.

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offset

error

gain

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

ia

(LSB

)

ideal

offset error

E

O

V

− V

DDA SSA

1 LSB =

1024

002aab136

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 6. ADC characteristics

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LPC2141/42/44/46/48

R

vsi

20 kΩ

ADx.y

SAMPLE

3 pF

5 pF

V

EXT

V

SS

002aab834

Fig 7. Suggested ADC interface - LPC2141/42/44/46/48 ADx.y pin

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Product data sheet

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9. Dynamic characteristics

Table 7.

Dynamic characteristics of USB pins (full-speed)

C_L= 50 pF; R_pu= 1.5 kΩ on D+ to V_DD, unless otherwise speciﬁed.

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

(t_r/t_f)

Min

4

Typ

Max

20

Unit

ns

t_r

-

t_f

4

20

ns

t_FRFM

differential rise and fall time

matching

90

110

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

1.3

160

−2

-

2.0

175

+5

V

t_FEOPT

t_FDEOP

see Figure 9

ns

source jitter for differential transition see Figure 9

to SE0 transition

t_JR1

receiver jitter to next transition

−18.5

−9

-

+18.5

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

+9

-

[1]

t_EOPR1

must reject as

EOP; see

Figure 9

40

t_EOPR2

EOP width at receiver

must accept as

EOP; see

82

-

ns

Figure 9

[1] Characterized but not implemented as production test. Guaranteed by design.

Table 8.

Dynamic characteristics

T_amb= −40 °C to +85 °C for commercial applications, V_DDover speciﬁed ranges^[1]

Symbol

External clock

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

10

40

-

25

100

-

MHz

ns

T_cy(clk)

t_CHCX

T

-

_cy(clk)× 0.4

ns

t_CLCX

_cy(clk)× 0.4

-

ns

t_CLCH

5

ns

t_CHCL

clock fall time

-

5

ns

Port pins (P0.2, P0.3, P0.11, and P0.14)

t_r(o)

t_f(o)

output rise time

-

10

-

ns

output fall time

I²C-bus pins (P0.2, P0.3, P0.11, and P0.14)

[3]

t_f(o)output fall time

V_IHto V_IL

20 + 0.1 × C_b

-

ns

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[3] Bus capacitance C_bin pF, from 10 pF to 400 pF.

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Product data sheet

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

9.1 Timing

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 8. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

t

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × t

+ t

PERIOD

FDEOP

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 9. Differential data-to-EOP transition skew and EOP width

10. Application information

10.1 Suggested USB interface solutions

V

DD

CONNECT

soft-connect switch

LPC2141/42/

44/46/48

R1

1.5 kΩ

VBUS

R

= 33 Ω

USB-B

connector

S

D+

R

S

D−

V

SS

002aab563

Fig 10. LPC2141/42/44/46/48 USB interface using the CONNECT function on pin 17

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Product data sheet

Rev. 04 — 17 November 2008

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LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

V

DD

R2

LPC2141/42/

44/46/48

R1

1.5 kΩ

UP_LED

VBUS

USB-B

connector

R

= 33 Ω

S

D+

R

S

D−

V

SS

002aab562

Fig 11. LPC2141/42/44/46/48 USB interface using the UP_LED function on pin 17

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Product data sheet

Rev. 04 — 17 November 2008

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

11. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v M

D

A

e

w M

b

p

D

B

H

v M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 12. Package outline SOT314-2 (LQFP64)

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Product data sheet

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

12. Abbreviations

Table 9.

Acronym list

Description

Acronym

ADC

APB

Analog-to-Digital Converter

Advanced Peripheral Bus

Brown-Out Detection

BOD

CPU

DAC

Central Processing Unit

Digital-to-Analog Converter

DCC

DMA

EOP

FIFO

GPIO

PLL

Debug Communications Channel

Direct Memory Access

End Of Packet

First In, First Out

General Purpose Input/Output

Phase-Locked Loop

POR

PWM

RAM

SE0

Power-On Reset

Pulse Width Modulator

Random Access Memory

Single Ended Zero

SPI

Serial Peripheral Interface

Static Random Access Memory

Synchronous Serial Port

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus

SRAM

SSP

UART

USB

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Product data sheet

Rev. 04 — 17 November 2008

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

13. Revision history

Table 10. Revision history

Document ID

Release date

20081117

Data sheet status

Change notice Supersedes

LPC2141_42_44_46_48_4

Modiﬁcations:

Product data sheet

-

LPC2141_42_44_46_48_3

• Replaced all occurrences of VPB with APB.

• Table 3: clariﬁed which pins do/don’t have internal pull-ups.

• Table 4: changed storage temperature range from −40 °C/125 °C to −65 °C/150 °C.

• Table 5: added Table note 7 to input voltage spec.

• Table 5: modiﬁed Table note 9.

• Table 5: moved hysteresis voltage (0.4 V) from typ to min column.

• Figure 8: updated ﬁgure and ﬁgure title, removed note

LPC2141_42_44_46_48_3

LPC2141_42_44_46_48_2

LPC2141_42_44_46_48_1

20071019

20060828

20051003

Product data sheet

Preliminary data sheet

-

LPC2141_42_44_46_48_2

LPC2141_42_44_46_48_1

-

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

38 of 40

LPC2141/42/44/46/48

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

14.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

I²C-bus — logo is a trademark of NXP B.V.

SoftConnect — is a trademark of NXP B.V.

GoodLink — is a trademark of NXP B.V.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

LPC2141_42_44_46_48_4

Product data sheet

Rev. 04 — 17 November 2008

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Single-chip 16-bit/32-bit microcontrollers

16. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

6.19.5

6.19.6

6.19.7

6.19.8

6.19.9

6.20

6.20.1

6.20.2

6.20.3

Code security . . . . . . . . . . . . . . . . . . . . . . . . . 23

External interrupt inputs. . . . . . . . . . . . . . . . . 23

Memory mapping control . . . . . . . . . . . . . . . . 23

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 24

APB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Emulation and debugging. . . . . . . . . . . . . . . . 24

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 24

Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 25

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2

2.1

3

3.1

4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

Static characteristics . . . . . . . . . . . . . . . . . . . 27

Dynamic characteristics. . . . . . . . . . . . . . . . . 33

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Application information . . . . . . . . . . . . . . . . . 34

Suggested USB interface solutions . . . . . . . . 34

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37

Revision history . . . . . . . . . . . . . . . . . . . . . . . 38

6

6.1

6.2

6.3

6.4

6.5

6.5.1

6.6

6.7

6.7.1

6.8

6.8.1

6.9

6.9.1

6.10

6.10.1

6.11

6.11.1

6.12

6.12.1

6.13

6.13.1

6.14

6.14.1

6.15

Functional description . . . . . . . . . . . . . . . . . . 13

Architectural overview. . . . . . . . . . . . . . . . . . . 13

On-chip ﬂash program memory . . . . . . . . . . . 13

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 14

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 15

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 15

Fast general purpose parallel I/O (GPIO). . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

USB 2.0 device controller . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

I²C-bus serial I/O controller . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SSP serial I/O controller . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General purpose timers/external event

8

9

9.1

10

10.1

11

12

13

14

Legal information . . . . . . . . . . . . . . . . . . . . . . 39

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 39

14.1

14.2

14.3

14.4

15

16

Contact information . . . . . . . . . . . . . . . . . . . . 39

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pulse width modulator . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

System control . . . . . . . . . . . . . . . . . . . . . . . . 22

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 22

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reset and wake-up timer . . . . . . . . . . . . . . . . 22

Brownout detector. . . . . . . . . . . . . . . . . . . . . . 23

6.15.1

6.16

6.16.1

6.17

6.17.1

6.18

6.18.1

6.19

6.19.1

6.19.2

6.19.3

6.19.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 November 2008

Document identifier: LPC2141_42_44_46_48_4


型号：	LPC2142FBD64-S
厂家：	NXP
描述：	Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC - ADCs: 6-ch 10-bit ; Category: ARM7TDMI-S (TM) Core ; Clock type: N/A ; External interrupt: 4 ; Function: 16/32-bit uController ; I/O pins: 45 ; Memory size: 64KB kBits; Memory type: FLASH ; Number of pins: 64 ; Operating frequency: 0~60 MHz; Operating temperature: -40 to +85 Cel; Power supply: 3.3V ; PWMs: 6-ch PWM ; RAM: 16KB bytes; Reset active: Low ; Serial interface: USB 2.02xUART2xI2C2xSPI ; Series: LPC2100 family ; Special features: USB 2.0POR, BOD ; System frequen 闪存微控制器
文件：	总40页 (文件大小：193K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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