LPC2194HBD64/00,15_技术文档

LPC2194

Single-chip 16/32-bit microcontroller; 256 kB ISP/IAP flash

with 10-bit ADC and CAN

Rev. 6 — 14 June 2011

Product data sheet

1. General description

The LPC2194 is based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and

embedded trace support, together with 256 kB of embedded high-speed flash memory. A

128-bit wide memory interface and a unique accelerator architecture enable 32-bit code

execution at maximum clock rate. For critical code size applications, the alternative 16-bit

Thumb mode reduces code by more than 30 % with minimal performance penalty.

With its compact 64-pin package, low power consumption, various 32-bit timers,

4-channel 10-bit ADC, four advanced CAN channels, PWM channels and 46 fast GPIO

lines with up to nine external interrupt pins this microcontroller is particularly suitable for

automotive applications such as a CAN gateway that connects several CAN busses or a

CAN bridge between sub networks at different speeds. Sensors with CAN interface or

debugging via CAN are additional applications that need more than two CAN interfaces. It

is also an adequate solution for industrial control, medical systems and fault-tolerant

maintenance buses. With a wide range of additional serial communications interfaces, it is

also suited for communication gateways and protocol converters as well as many other

general-purpose applications.

Remark: Throughout the data sheet, the term LPC2194 will apply to devices with and

without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate from

other devices only when necessary.

2. Features and benefits

2.1 Key features brought by LPC2194/01 devices

 Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.

They also allow for a port pin to be read at any time regardless of its function.

 Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are

5 V tolerant when configured for digital I/O function(s).

 UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake flow-control fully implemented in hardware.

 Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.

 SPI programmable data length and master mode enhancement.

 Diversified Code Read Protection (CRP) enables different security levels to be

implemented. This feature is available in LPC2194/00 devices as well.

 General purpose timers can operate as external event counters.

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

2.2 Key features common for all devices

 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

 16 kB on-chip SRAM and 256 kB on-chip flash program memory. 128-bit wide

interface/accelerator enables high speed 60 MHz operation.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or

full chip erase takes 400 ms.

 EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with

on-chip RealMonitor software as well as high speed real-time tracing of instruction

execution.

 Four interconnected CAN interfaces with advanced acceptance filters. Additional serial

interfaces are two UARTs (16C550), Fast I²C-bus (400 kbit/s) and two SPIs.

 Four channel 10-bit ADC with conversion time as low as 2.44 s.

 Two 32-bit timers (with four capture and four compare channels), PWM unit (six

outputs), Real-Time Clock and Watchdog.

 Vectored Interrupt Controller with configurable priorities and vector addresses.

 Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive

external interrupt pins available.

 Operating temperature range from 40 C to +125 C.

 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

Loop with settling time of 100 s.

 On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.

 Two low power modes, Idle and Power-down.

 Processor wake-up from Power-down mode via external interrupt.

 Individual enable/disable of peripheral functions for power optimization.

 Dual power supply:

 CPU operating voltage range of 1.65 V to 1.95 V (1.8 V  0.15 V).

 I/O power supply range of 3.0 V to 3.6 V (3.3 V  10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2194HBD64

LQFP64

plastic low profile quad flat package; 64 leads;

SOT314-2

body 10  10  1.4 mm

LPC2194HBD64/00 LQFP64

LPC2194HBD64/01 LQFP64

plastic low profile quad flat package; 64 leads;

body 10  10  1.4 mm

SOT314-2

plastic low profile quad flat package; 64 leads;

body 10  10  1.4 mm

LPC2194

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Product data sheet

Rev. 6 — 14 June 2011

2 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

4. Block diagram

(2)

TMS

(2)

TDI

(2)

RTCK

(2)

XTAL2

TRST

TCK

TDO

XTAL1

RESET

TEST/DEBUG

INTERFACE

V

LPC2194

DD(3V3)

DD(1V8)

SS

SYSTEM

FUNCTIONS

PLL

ARM7TDMI-S

system

clock

P0[30:27],

P0[25:0]

HIGH-SPEED

VECTORED

INTERRUPT

CONTROLLER

(3)

GPI/O

AHB BRIDGE

46 PINS TOTAL

P1[31:16]

AMBA Advanced High-performance

Bus (AHB)

ARM7 LOCAL BUS

INTERNAL

SRAM

FLASH

CONTROLLER

AHB TO APB

BRIDGE

APB

DIVIDER

AHB

DECODER

(1)

16 kB

SRAM

256 kB

FLASH

SCL

2

I C-BUS SERIAL

INTERFACE

(1)

SDA

(1)

SCK1

(1)

(3)

MOSI1

MISO1

SSEL1

SPI1/SSP SERIAL

EXTERNAL

INTERRUPTS

(1)

EINT[3:0]

INTERFACE

(1)

4 × CAP0

4 × CAP1

4 × MAT0

4 × MAT1

SCK0

CAPTURE/

COMPARE

TIMER 0/TIMER 1

(1)

MOSI0

MISO0

SSEL0

SPI0 SERIAL

INTERFACE

(1)

TXD[1:0]

A/D CONVERTER

AIN[3:0]

(1)

UART0/UART1

RXD[1:0]

(1)

DSR1 , CTS1

,

(1)

RTS1 , DTR1

DCD1 , RI1

,

P0[30:27],

P0[25:0]

(1)

GENERAL

PURPOSE I/O

WATCHDOG

TIMER

P1[31:16]

SYSTEM

CONTROL

(1)

PWM[6:1]

PWM0

(1)

RD[4:1]

CAN INTERFACE 1, 2, 3 AND 4

ACCEPTANCE FILTERS

REAL-TIME CLOCK

(1)

TD[4:1]

002aad178

(1) Shared with GPIO.

(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.

(3) SSP interface and high-speed GPIO are available on LPC2194/01 only.

Fig 1. Block diagram

LPC2194

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Product data sheet

Rev. 6 — 14 June 2011

3 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

5. Pinning information

5.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0[21]/PWM5/RD3/CAP1[3]

P0[22]/TD3/CAP0[0]/MAT0[0]

P0[23]/RD2

P1[20]/TRACESYNC

P0[17]/CAP1[2]/SCK1/MAT1[2]

P0[16]/EINT0/MAT0[2]/CAP0[2]

P0[15]/RI1/EINT2

3

4

P1[19]/TRACEPKT3

P0[24]/TD2

5

P1[21]/PIPESTAT0

6

V

SS

DDA(3V3)

DD(3V3)

SS

LPC2194

LPC2194/00

LPC2194/01

7

V

8

P1[18]/TRACEPKT2

P0[25]/RD1

P0[14]/DCD1/EINT1

9

P1[22]/PIPESTAT1

10

11

12

13

14

15

16

TD1

P0[13]/DTR1/MAT1[1]/TD4

P0[12]/DSR1/MAT1[0]/RD4

P0[11]/CTS1/CAP1[1]

P1[23]/PIPESTAT2

P0[27]/AIN0/CAP0[1]/MAT0[1]

P1[17]/TRACEPKT1

P0[28]/AIN1/CAP0[2]/MAT0[2]

P0[29]/AIN2/CAP0[3]/MAT0[3]

P0[30]/AIN3/EINT3/CAP0[0]

P1[16]/TRACEPKT0

P0[10]/RTS1/CAP1[0]

P0[9]/RXD1/PWM6/EINT3

P0[8]/TXD1/PWM4

002aad179

Fig 2. Pin configuration

LPC2194

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Product data sheet

Rev. 6 — 14 June 2011

4 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

5.2 Pin description

Table 2.

Pin description

Symbol

Type Description

P0[0] to P0[31]

I/O

Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit.

The operation of port 0 pins depends upon the pin function selected via the Pin

Connect Block. Pins 26 and 31 of port 0 are not available.

P0[0]/TXD0/

PWM1

19

21

O

I

TXD0 — Transmitter output for UART0.

PWM1 — Pulse Width Modulator output 1.

P0[1]/RXD0/

RXD0 — Receiver input for UART0.

PWM3/EINT0

O

I

PWM3 — Pulse Width Modulator output 3.

EINT0 — External interrupt 0 input.

P0[2]/SCL/

CAP0[0]

22

26

I/O

I

SCL — I²C-bus clock input/output. Open-drain output (for I²C-bus compliance).

CAP0[0] — Capture input for Timer 0, channel 0.

SDA — I²C-bus data input/output. Open-drain output (for I²C-bus compliance).

MAT0[0] — Match output for Timer 0, channel 0.

EINT1 — External interrupt 1 input.

P0[3]/SDA/

MAT0[0]/EINT1

I/O

O

I

P0[4]/SCK0/

CAP0[1]

27

29

I/O

I

SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

CAP0[1] — Capture input for Timer 0, channel 1.

P0[5]/MISO0/

MAT0[1]

I/O

MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data output

from SPI slave.

O

MAT0[1] — Match output for Timer 0, channel 1.

P0[6]/MOSI0/

CAP0[2]

30

31

I/O

MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input

to SPI slave.

I

CAP0[2] — Capture input for Timer 0, channel 2.

SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

PWM2 — Pulse Width Modulator output 2.

EINT2 — External interrupt 2 input.

P0[7]/SSEL0/

PWM2/EINT2

I

O

I

P0[8]/TXD1/

PWM4

33

34

O

I

TXD1 — Transmitter output for UART1.

PWM4 — Pulse Width Modulator output 4.

RXD1 — Receiver input for UART1.

P0[9]/RXD1/

PWM6/EINT3

O

I

PWM6 — Pulse Width Modulator output 6.

EINT3 — External interrupt 3 input.

P0[10]/RTS1/

CAP1[0]

35

37

38

O

I

RTS1 — Request to Send output for UART1.

CAP1[0] — Capture input for Timer 1, channel 0.

CTS1 — Clear to Send input for UART1.

CAP1[1] — Capture input for Timer 1, channel 1.

DSR1 — Data Set Ready input for UART1.

MAT1[0] — Match output for Timer 1, channel 0.

RD4 — CAN4 receiver input.

P0[11]/CTS1/

CAP1[1]

I

P0[12]/DSR1/

MAT1[0]/RD4

I

O

P0[13]/DTR1/

MAT1[1]/TD4

39

DTR1 — Data Terminal Ready output for UART1.

MAT1[1] — Match output for Timer 1, channel 1.

TD4 — CAN4 transmitter output.

LPC2194

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Product data sheet

Rev. 6 — 14 June 2011

5 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

Table 2.

Symbol

Pin description …continued

Type Description

P0[14]/DCD1/

EINT1

41

I

DCD1 — Data Carrier Detect input for UART1.

EINT1 — External interrupt 1 input.

Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take

control of the part after reset.

P0[15]/RI1/EINT2 45

I

RI1 — Ring Indicator input for UART1.

I

EINT2 — External interrupt 2 input.

P0[16]/EINT0/

MAT0[2]/CAP0[2]

46

47

I

EINT0 — External interrupt 0 input.

O

MAT0[2] — Match output for Timer 0, channel 2.

CAP0[2] — Capture input for Timer 0, channel 2.

CAP1[2] — Capture input for Timer 1, channel 2.

I

P0[17]/CAP1[2]/

SCK1/MAT1[2]

I

I/O

SCK1 — Serial Clock for SPI1/SSP^[1]. SPI clock output from master or input to

slave.

O

I

MAT1[2] — Match output for Timer 1, channel 2.

P0[18]/CAP1[3]/

MISO1/MAT1[3]

53

54

CAP1[3] — Capture input for Timer 1, channel 3.

MISO1 — Master In Slave Out for SPI1/SSP^[1]. Data input to SPI master or data

output from SPI slave.

I/O

O

MAT1[3] — Match output for Timer 1, channel 3.

P0[19]/MAT1[2]/

MOSI1/CAP1[2]

O

MAT1[2] — Match output for Timer 1, channel 2.

MOSI1 — Master Out Slave In for SPI1/SSP^[1]. Data output from SPI master or data

I/O

input to SPI slave.

I

CAP1[2] — Capture input for Timer 1, channel 2.

MAT1[3] — Match output for Timer 1, channel 3.

SSEL1 — Slave Select for SPI1/SSP^[1]. Selects the SPI interface as a slave.

EINT3 — External interrupt 3 input.

P0[20]/MAT1[3]/

SSEL1/EINT3

55

1

O

I

P0[21]/PWM5/

RD3/CAP1[3]

O

I

PWM5 — Pulse Width Modulator output 5.

RD3 — CAN3 receiver input.

I

CAP1[3] — Capture input for Timer 1, channel 3.

TD3 — CAN3 transmitter output.

P0[22]/TD3/

2

O

I

CAP0[0]/MAT0[0]

CAP0[0] — Capture input for Timer 0, channel 0.

MAT0[0] — Match output for Timer 0, channel 0.

CAN2 receiver input.

O

I

P0[23]/RD2

P0[24]/TD2

P0[25]/RD1

3

5

O

I

CAN2 transmitter output.

9

CAN1 receiver input.

P0[27]/AIN0/

11

AIN0 — A/D converter, input 0. This analog input is always connected to its pin.

CAP0[1] — Capture input for Timer 0, channel 1.

MAT0[1] — Match output for Timer 0, channel 1.

AIN1 — A/D converter, input 1. This analog input is always connected to its pin.

CAP0[2] — Capture input for Timer 0, channel 2.

MAT0[2] — Match output for Timer 0, channel 2.

AIN2 — A/D converter, input 2. This analog input is always connected to its pin.

CAP0[3] — Capture input for Timer 0, Channel 3.

MAT0[3] — Match output for Timer 0, channel 3.

CAP0[1]/MAT0[1]

I

O

I

P0[28]/AIN1/

CAP0[2]/MAT0[2]

13

14

I

O

I

P0[29]/AIN2/

CAP0[3]/MAT0[3]

I

O

LPC2194

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Product data sheet

Rev. 6 — 14 June 2011

6 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

Table 2.

Symbol

Pin description …continued

Type Description

P0[30]/AIN3/

EINT3/CAP0[0]

15

I

AIN3 — A/D converter, input 3. This analog input is always connected to its pin.

EINT3 — External interrupt 3 input.

I

CAP0[0] — Capture input for Timer 0, channel 0.

P1[0] to P1[31]

I/O

Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.

The operation of port 1 pins depends upon the pin function selected via the Pin

Connect Block. Pins 0 through 15 of port 1 are not available.

P1[16]/

TRACEPKT0

16

12

8

O

Trace Packet, bit 0. Standard I/O port with internal pull-up.

Trace Packet, bit 1. Standard I/O port with internal pull-up.

Trace Packet, bit 2. Standard I/O port with internal pull-up.

Trace Packet, bit 3. Standard I/O port with internal pull-up.

Trace Synchronization. Standard I/O port with internal pull-up.

P1[17]/

TRACEPKT1

P1[18]/

TRACEPKT2

P1[19]/

TRACEPKT3

4

P1[20]/

48

TRACESYNC

Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as

Trace port after reset.

P1[21]/

PIPESTAT0

44

40

36

32

O

Pipeline Status, bit 0. Standard I/O port with internal pull-up.

Pipeline Status, bit 1. Standard I/O port with internal pull-up.

Pipeline Status, bit 2. Standard I/O port with internal pull-up.

Trace Clock. Standard I/O port with internal pull-up.

P1[22]/

PIPESTAT1

P1[23]/

PIPESTAT2

P1[24]/

TRACECLK

P1[25]/EXTIN0

P1[26]/RTCK

28

24

I

External Trigger Input. Standard I/O with internal pull-up.

I/O

Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger

synchronization when processor frequency varies. Bidirectional pin with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as

Debug port after reset.

P1[27]/TDO

P1[28]/TDI

P1[29]/TCK

64

60

56

O

I

Test Data out for JTAG interface.

Test Data in for JTAG interface.

Test Clock for JTAG interface. This clock must be slower than ¹⁄₆of the CPU clock

I

(CCLK) for the JTAG interface to operate.

P1[30]/TMS

P1[31]/TRST

TD1

52

20

10

57

I

Test Mode Select for JTAG interface.

Test Reset for JTAG interface.

CAN1 transmitter output.

I

O

I

RESET

external reset input; a LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

V_SS

62

61

I

input to the oscillator circuit and internal clock generator circuits.

output from the oscillator amplifier.

O

I

6, 18, 25,

42, 50

ground: 0 V reference.

LPC2194

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Product data sheet

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7 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

Table 2.

Symbol

V_SSA

Pin description …continued

Type Description

59

I

analog ground; 0 V reference. This should nominally be the same voltage as V_SS

but should be isolated to minimize noise and error.

,

V_SSA(PLL)

58

I

PLL analog ground; 0 V reference. This should nominally be the same voltage as

V_SS, but should be isolated to minimize noise and error.

V_DD(1V8)

17, 49

63

I

1.8 V core power supply; this is the power supply voltage for internal circuitry.

V_DDA(1V8)

analog 1.8 V core power supply; this is the power supply voltage for internal

circuitry. This should be nominally the same voltage as V_DD(1V8)but should be

isolated to minimize noise and error.

V_DD(3V3)

23, 43, 51

7

I

3.3 V pad power supply; this is the power supply voltage for the I/O ports.

V_DDA(3V3)

analog 3.3 V pad power supply; this should be nominally the same voltage as

V_DD(3V3)but should be isolated to minimize noise and error.

[1] SSP interface available on LPC2194/01 only.

LPC2194

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Product data sheet

Rev. 6 — 14 June 2011

8 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

6. Functional description

Details of the LPC2194 systems and peripheral functions are described in the following

sections.

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip flash program memory

The LPC2194 incorporates a 256 kB flash memory system. This memory may be used for

both code and data storage. Programming of the flash memory may be accomplished in

several ways. It may be programmed In System via the serial port. The application

program may also erase and/or program the flash while the application is running,

allowing a great degree of flexibility for data storage field firmware upgrades, etc. When

on-chip bootloader is used, 248 kB of flash memory is available for user code.

The LPC2194 flash memory provides a minimum of 100000 erase/write cycles and 20

years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the

LPC2194 on-chip flash memory. When the CRP is enabled, the JTAG debug port and ISP

commands accessing either the on-chip RAM or flash memory are disabled. However, the

LPC2194

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Product data sheet

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LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

ISP flash erase command can be executed at any time (no matter whether the CRP is on

or off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off,

full access to the chip via the JTAG and/or ISP is restored.

6.3 On-chip SRAM

On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed

as 8 bit, 16 bit, and 32 bit. The LPC2194 provides 16 kB of SRAM.

6.4 Memory map

The LPC2194 memory maps incorporate several distinct regions, as shown in Figure 3.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

flash memory (the default) or on-chip SRAM. This is described in Section 6.18 “System

control”.

LPC2194

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Product data sheet

Rev. 6 — 14 June 2011

10 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

4.0 GB

3.75 GB

3.5 GB

0xFFFF FFFF

AHB PERIPHERALS

APB PERIPHERALS

0xF000 0000

0xEFFF FFFF

0xE000 0000

0xDFFF FFFF

0xC000 0000

3.0 GB

RESERVED ADDRESS SPACE

0x8000 0000

0x7FFF FFFF

2.0 GB

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

0x7FFF E000

0x7FFF DFFF

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM

0x4000 4000

0x4000 3FFF

0x4000 0000

0x3FFF FFFF

1.0 GB

RESERVED ADDRESS SPACE

0x0004 0000

0x0003 FFFF

256 kB ON-CHIP FLASH MEMORY

0x0000 0000

0.0 GB

002aad180

Fig 3. LPC2194 memory map

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as defined by programmable settings. The programmable assignment

scheme means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classified as FIQ, because then

the FIQ service routine can simply start dealing with that device. But if more than one

request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC

that identifies which FIQ source(s) is (are) requesting an interrupt.

LPC2194

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Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are requesting, the

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 3 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several

internal interrupt flags. Individual interrupt flags may also represent more than one

interrupt source.

Table 3.

Block

Interrupt sources

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

0

1

2

3

4

-

Reserved for software interrupts only

EmbeddedICE, DbgCommRx

EmbeddedICE, DbgCommTx

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Rx Line Status (RLS)

ARM Core

Timer 0

Timer 1

UART0

5

6

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Rx Line Status (RLS)

UART1

7

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

Match 0 to 3 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

SI (state change)

PWM0

I²C-bus

SPI0

8

9

SPIF, MODF

10

11

12

13

SPI1 and SSP^[1]SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS

PLL

PLL Lock (PLOCK)

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

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Table 3.

Block

Interrupt sources …continued

Flag(s)

VIC channel #

System Control External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

14

15

External Interrupt 2 (EINT2)

16

External Interrupt 3 (EINT3)

17

ADC

CAN

A/D Converter

18

1 ORed CAN Acceptance Filter

CAN1 (Tx int, Rx int)

CAN2 (Tx int, Rx int)

CAN3 (Tx int, Rx int)

CAN4 (Tx int, Rx int)

19

20,21

22,23

24,25

26,27

[1] SSP interface available on LPC2194/01 only.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undefined.

6.7 General purpose parallel I/O (GPIO) and Fast I/O

Device pins that are not connected to a specific peripheral function are controlled by the

parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.7.2 Features added with the Fast GPIO set of registers available on LPC2194/01

only

• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

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• Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

6.8 10-bit ADC

The LPC2194 each contain a single 10-bit successive approximation ADC with four

multiplexed channels.

6.8.1 Features

• Measurement range of 0 V to 3 V.

• Capable of performing more than 400000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

6.8.2 ADC features available in LPC2194/01 only

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Every analog input can generate an interrupt once the conversion is completed.

• The ADC pads are 5 V tolerant when configured for digital I/O function(s).

6.9 CAN controllers and acceptance filter

The LPC2194 contains four CAN controllers. The CAN is a serial communications

protocol which efficiently supports distributed real-time control with a very high level of

security. Its domain of application ranges from high-speed networks to low-cost multiplex

wiring.

6.9.1 Features

• Data rates up to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit Rx identifiers for all CAN buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard identifiers.

6.10 UARTs

The LPC2194 each contain two UARTs. In addition to standard transmit and receive data

lines, the UART1 also provides a full modem control handshake interface.

6.10.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

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• Transmission FIFO control enables implementation of software (XON/XOFF) flow

control on both UARTs.

• UART1 is equipped with standard modem interface signals. This module also

provides full support for hardware flow control (auto-CTS/RTS).

6.10.2 UART features available in LPC2194/01 only

Compared to previous LPC2000 microcontrollers, UARTs in LPC2194/01 introduce a

fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve

standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In

addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.

• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be

achieved with any crystal frequency above 2 MHz.

• Auto-bauding.

• Auto-CTS/RTS flow-control fully implemented in hardware.

6.11 I²C-bus serial I/O controller

The I²C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock

line (SCL), and a serial data line (SDA). Each device is recognized by a unique address

and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with

the capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus; it can be

controlled by more than one bus master connected to it.

The I²C-bus implemented in LPC2194 supports a bit rate up to 400 kbit/s (Fast I²C-bus).

6.11.1 Features

• Standard I²C-bus compliant interface.

• Easy to configure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus may be used for test and diagnostic purposes.

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6.12 SPI serial I/O controller

The LPC2194 each contain two SPIs. The SPI is a full duplex serial interface, designed to

be able to handle multiple masters and slaves connected to a given bus. Only a single

master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends a byte of data to the slave, and the slave

always sends a byte of data to the master.

6.12.1 Features

• Compliant with Serial Peripheral Interface (SPI) specification.

• Synchronous, Serial, Full Duplex communication.

• Combined SPI master and slave.

• Maximum data bit rate of ¹⁄₈of the input clock rate.

6.12.2 Features available in LPC2194/01 only

• Eight to 16 bits per frame.

• When the SPI interface is used in Master mode, the SSELn pin is not needed (can be

used for a different function).

6.13 SSP controller (LPC2194/01 only)

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. Data transfers are in

principle full duplex, with frames of four to 16 bits of data flowing from the master to the

slave and from the slave to the master.

While the SSP and SPI1 peripherals share the same physical pins, it is not possible to

have both of these two peripherals active at the same time. The application can switch on

the fly from SPI1 to SSP and back.

6.13.1 Features

• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four to 16 bits per frame.

6.14 General purpose timers

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

specified timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

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6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Timer or external event counter operation

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.14.2 Features available in LPC2194/01 only

The LPC2194/01 can count external events on one of the capture inputs if the external

pulse lasts at least one half of the period of the PCLK. In this configuration, unused

capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied

clock.

• When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to

PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter

than 1 / (2PCLK).

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

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• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T_cy(PCLK) 256  4) to (T_cy(PCLK) 2³² 4) in multiples of

T_cy(PCLK) 4.

6.16 Real-time clock

The RTC is designed to provide a set of counters to measure time when normal or idle

operating mode is selected. The RTC has been designed to use little power, making it

suitable for battery powered systems where the CPU is not running continuously (Idle

mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

• Programmable reference clock divider allows adjustment of the RTC to match various

crystal frequencies.

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2194. The Timer is designed to count

cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other

actions when specified timer values occur, based on seven match registers. The PWM

function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

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With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.17.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.18 System control

6.18.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output

frequency is called f_oscand the ARM processor clock frequency is referred to as CCLK for

purposes of rate equations, etc. f_oscand CCLK are the same value unless the PLL is

running and connected. Refer to Section 6.18.2 “PLL” for additional information.

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

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by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and

bypassed following a chip Reset and may be enabled by software. The program must

configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a

clock source. The PLL settling time is 100 s.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2194: the RESET pin and Watchdog Reset. The

RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip

Reset by any source starts the Wake-up Timer (see Wake-up Timer description below),

causing the internal chip reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a fixed number of clocks have passed, and the on-chip flash

controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is the Reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is important at power on, all types of Reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufficient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DDramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2194/01 allows the user to enable different levels of security in the

system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.

When needed, CRP is invoked by programming a specific pattern into a dedicated flash

location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

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CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Remark: Devices without the /00 or /01 suffixes have only a security level equivalent to

CRP2 available.

6.18.5 External interrupt inputs

The LPC2194 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake-up the processor from Power-down mode.

6.18.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

flash memory, or to the on-chip SRAM. This allows code running in different memory

spaces to have control of the interrupts.

6.18.7 Power control

The LPC2194 support two reduced power modes: Idle mode and Power-down mode. In

Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a Reset or certain specific interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.18.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to ¹⁄₂to ¹⁄₄of the processor clock rate. Because the APB must work properly at

power-up (and its timing cannot be altered if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at ¹⁄₄of the

processor clock rate. The second purpose of the APB divider is to allow power savings

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when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.19 Emulation and debugging

The LPC2194 support emulation and debugging via a JTAG serial port. A trace port allows

tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on Port 1. This means that all communication, timer and interface peripherals

residing on Port 0 are available during the development and debugging phase as they are

when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program flow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program flow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than ¹⁄₆of the CPU clock (CCLK) for the JTAG

interface to operate.

6.19.2 Embedded trace macrocell

Since the LPC2194 have significant amounts of on-chip memory, it is not possible to

determine how the processor core is operating simply by observing the external pins. The

Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply

embedded processor cores. It outputs information about processor execution to the trace

port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the flow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is significantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code can not be traced

because of this restriction.

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6.19.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC (Debug

Communications Channel), which is present in the EmbeddedICE logic. The LPC2194

contain a specific configuration of RealMonitor software programmed into the on-chip

flash memory.

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7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD(1V8)

V_DD(3V3)

V_DDA(3V3)

V_IA

Parameter

Conditions

Min

0.5

-

Max

Unit

V

[2]

[3]

supply voltage (1.8 V)

supply voltage (3.3 V)

analog supply voltage (3.3 V)

analog input voltage

input voltage

+2.5

+3.6

V

+4.6

V

+5.1

V

[4][5]

[4][6]

[7][8]

[8][9]

V_I

5 V tolerant I/O pins

other I/O pins

+6.0

V

V_DD(3V3)+ 0.5

100

V

I_DD

supply current

mA

C

W

I_SS

ground current

-

100

T_j

junction temperature

storage temperature

-

150

[10]

[11]

T_stg

P_tot(pack)

65

-

+150

1.5

total power dissipation (per

package)

based on package heat

transfer, not device

power consumption

V_ESD

electrostatic discharge voltage human body model

all pins

2000

+2000

V

[1] The following applies to Table 4:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] Only valid when the V_DD(3V3)supply voltage is present.

[6] Not to exceed 4.6 V.

[7] Per supply pin.

[8] The peak current is limited to 25 times the corresponding maximum current.

[9] Per ground pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

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Single-chip 16/32-bit microcontroller

8. Static characteristics

Table 5.

Static characteristics

T_amb= 40 C to +125 C for industrial applications, unless otherwise specified.

Symbol Parameter

Conditions

Min

1.65

3.0

Typ^[1]

1.8

Max

1.95

3.6

Unit

V

[2]

[3]

V_DD(1V8)

V_DD(3V3)

supply voltage (1.8 V)

supply voltage (3.3 V)

3.3

V

V_DDA(3V3)analog supply voltage

(3.3 V)

2.5

3.3

3.6

V

Standard port pins, RESET, RTCK

I_IL

LOW-level input current

HIGH-level input current

V_I= 0 V; no pull-up

-

3

A

I_IH

I_OZ

V_I= V_DD(3V3); no pull-down

OFF-state output current V_O= 0 V; V_O= V_DD(3V3)

;

no pull-up/down

I_latch

I/O latch-up current

(0.5V_DD(3V3)) < V_I<

100

-

mA

(1.5V_DD(3V3)); T_j< 125 C

[4][5][6]

V_I

input voltage

0

-

5.5

V

V_O

output voltage

output active

0

V_DD(3V3)

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

-

V

0.8

V

V_hys

V_OH

V_OL

I_OH

I_OL

0.4

-

V

[7]

[8]

HIGH-level output voltage I_OH= 4 mA

LOW-level output voltage I_OL= 4 mA

HIGH-level output current V_OH= V_DD(3V3) 0.4 V

LOW-level output current V_OL= 0.4 V

V_DD(3V3) 0.4 -

-

V

-

0.4

-

V

4

4

-

mA

-

I_OHS

HIGH-level short-circuit

output current

V_OH= 0 V

45

[8]

I_OLS

LOW-level short-circuit

output current

V_OL= V_DD(3V3)

-

50

mA

[9]

[10]

[9]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

15

0

50

50

0

150

85

0

A

V_I= 0 V

V_DD(3V3)< V_I< 5 V

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Single-chip 16/32-bit microcontroller

Table 5.

Static characteristics …continued

T_amb= 40 C to +125 C for industrial applications, unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

Power consumption LPC2194

I_DD(act)

active mode supply

current

V_DD(1V8)= 1.8 V;

CCLK = 60 MHz;

-

60

-

mA

T

_amb= 25 C; code

while(1){}

executed from flash; all

peripherals enabled via

PCONP^[11]register but not

configured to run

I_DD(pd)

Power-down mode supply V_DD(1V8)= 1.8 V;

-

10

-

A

current

T_amb= 25 C

V_DD(1V8)= 1.8 V;

110

300

500

1000

T

_amb= 85 C

V_DD(1V8)= 1.8 V;

T_amb= 125 C

Power consumption LPC2194/01

I_DD(act)

active mode supply

current

V_DD(1V8)= 1.8 V;

CCLK = 60 MHz;

T_amb= 25 C; code

-

43.5

-

mA

while(1){}

executed from flash; all

peripherals enabled via

PCONP^[11]register but not

configured to run

I_DD(idle)

Idle mode supply current V_DD(1V8)= 1.8 V;

CCLK = 60 MHz;

-

11.5

-

mA

T_amb= 25 C;

executed from flash; all

peripherals enabled via

PCONP^[11]register but not

configured to run

I_DD(pd)

Power-down mode supply V_DD(1V8)= 1.8 V;

current _amb= 25 C

-

10

-

A

T

V_DD(1V8)= 1.8 V;

T_amb= 85 C

110

300

500

1000

V

_DD(1V8)= 1.8 V;

T_amb= 125 C

I²C-bus pins

V_IH

V_IL

V_hys

V_OL

I_LI

HIGH-level input voltage

0.7V_DD(3V3)

-

V

LOW-level input voltage

hysteresis voltage

-

0.3V_DD(3V3)

V

0.05V_DD(3V3)

-

V

[7]

LOW-level output voltage I_OLS= 3 mA

-

0.4

4

V

[12]

input leakage current

V_I= V_DD(3V3)

V_I= 5 V

2

A

10

22

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Single-chip 16/32-bit microcontroller

Table 5.

Static characteristics …continued

T_amb= 40 C to +125 C for industrial applications, unless otherwise specified.

Symbol Parameter

Oscillator pins

Conditions

Min

Typ^[1]

Max

Unit

V_i(XTAL1)

input voltage on pin

XTAL1

0

-

1.8

V

V_o(XTAL2)output voltage on pin

XTAL2

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5]

V_DD(3V3)supply voltages must be present.

[6] 3-state outputs go into 3-state mode when V_DD(3V3)is grounded.

[7] Accounts for 100 mV voltage drop in all supply lines.

[8] Only allowed for a short time period.

[9] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[10] Applies to P1[25:16].

[11] See LPC2119/2129/2194/2292/2294 User Manual.

[12] To V_SS

.

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Single-chip 16/32-bit microcontroller

Table 6.

ADC static characteristics

V_DDA= 2.5 V to 3.6 V; T_amb= 40 C to +125 C unless otherwise specified; ADC frequency 4.5 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

analog input voltage

0

-

C_ia

analog input

capacitance

pF

[1][2][3]

E_D

differential linearity

error

-

1

LSB

[1][4]

[1][5]

[1][6]

[1][7]

E_L(adj)

E_O

integral non-linearity

offset error

-

2

LSB

%

3

E_G

gain error

0.5

4

E_T

absolute error

LSB

[1] Conditions: V_SSA= 0 V, V_DDA= 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 4.

[4] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 4.

[6] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 4.

[7] The absolute voltage error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated ADC and the ideal transfer curve. See Figure 4.

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Single-chip 16/32-bit microcontroller

gain

error

offset

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

V

− V

SSA

DDA

1 LSB =

offset

error

1024

002aaa668

E

O

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 4. ADC characteristics

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Single-chip 16/32-bit microcontroller

8.1 Power consumption measurements for LPC2194/01

The power consumption measurements represent typical values for the given conditions.

The peripherals were enabled through the PCONP register, but for these measurements,

the peripherals were not configured to run. Peripherals were disabled through the PCONP

register. Refer to the LPC2119/2129/2194/2292/2294 User Manual for a description of the

PCONP register.

002aad118

45

I

DD(act)

(mA)

all peripherals enabled

all peripherals disabled

35

25

15

5

12

20

28

36

44

52

60

frequency (MHz)

Test conditions: Active mode entered executing code from on-chip flash; PCLK = ^CCLK⁄₄;

T_amb= 25 C; core voltage 1.8 V.

Fig 5. Typical LPC2194/01 I_DD(act)measured at different frequencies

002aad119

50

60 MHz

48 MHz

I

DD(act)

(mA)

40

30

20

10

0

12 MHz

1.65

1.80

1.95

voltage (V)

Test conditions: Active mode entered executing code from on-chip flash; PCLK = ^CCLK⁄₄;

T_amb= 25 C; core voltage 1.8 V; all peripherals enabled.

Fig 6. Typical LPC2194/01 I_DD(act)measured at different voltages

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Single-chip 16/32-bit microcontroller

002aad120

45

I

DD(act)

(mA)

60 MHz

48 MHz

35

25

15

5

12 MHz

1.65

1.80

1.95

voltage (V)

Test conditions: Active mode entered executing code from on-chip flash; PCLK = ^CCLK⁄₄;

Temp = 25 C; core voltage 1.8 V; all peripherals disabled.

Fig 7. Typical LPC2194/01 I_DD(act)measured at different voltages

002aad121

15.0

I

DD(idle)

(mA)

all peripherals enabled

all peripherals disabled

10.0

5.0

0.0

12

20

28

36

44

52

60

frequency (MHz)

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ^CCLK⁄₄;

T_amb= 25 C; core voltage 1.8 V.

Fig 8. Typical LPC2194/01 I_DD(idle)measured at different frequencies

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Single-chip 16/32-bit microcontroller

002aad122

15.0

60 MHz

48 MHz

I

DD(idle)

(mA)

10.0

5.0

12 MHz

0.0

1.65

1.80

1.95

voltage (V)

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ^CCLK⁄₄;

T_amb= 25 C; core voltage 1.8 V; all peripherals enabled.

Fig 9. Typical LPC2194/01 I_DD(idle)measured at different voltages

002aad123

8.0

I

DD(idle)

(mA)

60 MHz

48 MHz

6.0

4.0

2.0

0.0

12 MHz

1.65

1.80

1.95

voltage (V)

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ^CCLK⁄₄;

Temp = 25 C; core voltage 1.8 V; all peripherals disabled.

Fig 10. Typical LPC2194/01 I_DD(idle)measured at different voltages

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Single-chip 16/32-bit microcontroller

002aad124

500

I

DD(pd)

(μA)

1.95 V

1.8 V

400

300

200

100

0

1.65 V

-40

-25

-10

5

20

35

50

65

80

95

110

125

temperature (°C)

Test conditions: Power-down mode entered executing code from on-chip flash.

Fig 11. Typical LPC2194/01 core power-down current I_DD(pd)measured at different temperatures

002aad125

45

I

60 MHz

48 MHz

DD(act)

(mA)

35

25

15

5

12 MHz

50

-40

-25

-10

5

20

35

65

80

95

110

125

temperature (°C)

Test conditions: code executed from on-chip flash; PCLK = ^CCLK⁄₄;

core voltage 1.8 V; all peripherals disabled.

Fig 12. Typical LPC2194/01 I_DD(act)measured at different temperatures

LPC2194

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Single-chip 16/32-bit microcontroller

002aad126

7.0

I

DD(idle)

(mA)

60 MHz

48 MHz

6.0

5.0

4.0

3.0

2.0

1.0

12 MHz

65

-40

-25

-10

5

20

35

50

80

95

110

125

temperature (°C)

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ^CCLK⁄₄;

core voltage 1.8 V; all peripherals disabled.

Fig 13. Typical LPC2194/01 I_DD(idle)measured at different temperatures

Table 7.

Typical LPC2194/01 peripheral power consumption in active mode

Core voltage 1.8 V; T_amb= 25 C; all measurements in A; PCLK = ^CCLK⁄₄.

Peripheral

Timer0

Timer1

UART0

UART1

PWM0

I²C-bus

SPI0/1

RTC

CCLK = 12 MHz

CCLK = 48 MHz

CCLK = 60 MHz

43

46

98

103

9

141

150

320

351

341

37

184

180

398

421

407

53

6

27

29

16

33

230

55

78

ADC

128

769

167

912

CAN1/2/3/4

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Single-chip 16/32-bit microcontroller

9. Dynamic characteristics

Table 8.

T

Dynamic characteristics

_amb= 40 C to +125 C for industrial applications; V_DD(1V8), V_DD(3V3)over specified ranges.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

External clock

f_osc

oscillator frequency

supplied by an external

oscillator (signal generator)

1

-

50

30

MHz

external clock frequency

supplied by an external

crystal oscillator

external clock frequency if

on-chip PLL is used

10

-

25

MHz

external clock frequency if

on-chip bootloader is used

for initial code download

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

20

-

1000

ns

T_cy(clk) 0.4

-

T_cy(clk) 0.4

-

5

Port pins (except P0[2] and P0[3])

t_r

t_f

rise time

fall time

-

10

-

ns

I²C-bus pins (P0[2] and P0[3])

[2]

t_ffall time

V_IHto V_IL

20 + 0.1  C_b

-

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Bus capacitance C_bin pF, from 10 pF to 400 pF.

9.1 Timing

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 14. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

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Single-chip 16/32-bit microcontroller

10. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 15. Package outline SOT314-2 (LQFP64)

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Single-chip 16/32-bit microcontroller

11. Abbreviations

Table 9.

Abbreviations

Description

Analog-to-Digital Converter

Acronym

ADC

AMBA

APB

Advanced Microcontroller Bus Architecture

Advanced Peripheral Bus

Controller Area Network

CAN

CPU

DCC

FIFO

GPIO

I/O

Central Processing Unit

Debug Communications Channel

First In, First Out

General Purpose Input/Output

Input/Output

JTAG

PLL

Joint Test Action Group

Phase-Locked Loop

PWM

RAM

SPI

Pulse Width Modulator

Random Access Memory

Serial Peripheral Interface

Static Random Access Memory

Synchronous Serial Interface

Synchronous Serial Port

SRAM

SSI

SSP

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

UART

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Single-chip 16/32-bit microcontroller

12. Revision history

Table 10. Revision history

Document ID

LPC2194 v.6

Modifications:

Release date

20110614

Data sheet status

Change notice

Supersedes

Product data sheet

201004021F

LPC2194 v.5

• Table 5 “Static characteristics”; Changed /01 Power-down mode supply current (I_DD(pd)

from 180 A to 500 A for industrial temperature range, and 430 A to 1000 A for

extended temperature range.

)

• Table 5 “Static characteristics”; Moved V_hysvoltage from typical to minimum.

• Table 5 “Static characteristics”; Changed I²C pad hysteresis from 0.5V_DD(3V3)to

0.05V_DD(3V3)

20071210

• Type number LPC2194HBD64/01 has been added.

.

LPC2194 v.5

Modifications:

Product data sheet

-

LPC2194 v.4

• Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP)

and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added.

• Power consumption measurements for LPC2194/01 added.

• Description of JTAG pin TCK has been updated.

LPC2194 v.4

LPC2194 v.3

LPC2194 v.2

LPC2194 v.1

20061016

20060714

20041222

20040206

Product data sheet

Product data

-

LPC2194 v.3

LPC2194 v.2

LPC2194 v.1

-

Preliminary data

LPC2194

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13. Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

13.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

13.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

LPC2194

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 14 June 2011

39 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

14. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC2194

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 14 June 2011

40 of 41

LPC2194

NXP Semiconductors

Single-chip 16/32-bit microcontroller

15. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

6.18.1

6.18.2

6.18.3

6.18.4

6.18.5

6.18.6

6.18.7

6.18.8

6.19

Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 19

PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reset and wake-up timer. . . . . . . . . . . . . . . . 20

Code security (Code Read Protection - CRP) 20

External interrupt inputs. . . . . . . . . . . . . . . . . 21

Memory mapping control . . . . . . . . . . . . . . . . 21

Power control. . . . . . . . . . . . . . . . . . . . . . . . . 21

APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Emulation and debugging . . . . . . . . . . . . . . . 22

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 22

Embedded trace macrocell . . . . . . . . . . . . . . 22

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2

2.1

2.2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Key features brought by LPC2194/01 devices . 1

Key features common for all devices . . . . . . . . 2

3

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.19.1

6.19.2

6.19.3

6

Functional description . . . . . . . . . . . . . . . . . . . 9

Architectural overview . . . . . . . . . . . . . . . . . . . 9

On-chip flash program memory . . . . . . . . . . . . 9

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 10

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 11

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 13

General purpose parallel I/O (GPIO) and

6.1

6.2

6.3

6.4

6.5

6.5.1

6.6

6.7

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 24

8

8.1

Static characteristics . . . . . . . . . . . . . . . . . . . 25

Power consumption measurements for

LPC2194/01. . . . . . . . . . . . . . . . . . . . . . . . . . 30

9

Dynamic characteristics. . . . . . . . . . . . . . . . . 35

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 36

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37

Revision history . . . . . . . . . . . . . . . . . . . . . . . 38

9.1

10

11

12

Fast I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Features added with the Fast GPIO set of

6.7.1

6.7.2

registers available on LPC2194/01 only. . . . . 13

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ADC features available in LPC2194/01 only. . 14

CAN controllers and acceptance filter . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

UART features available in LPC2194/01 only 15

I²C-bus serial I/O controller . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Features available in LPC2194/01 only . . . . . 16

SSP controller (LPC2194/01 only) . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

General purpose timers . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features available in LPC2194/01 only . . . . . 17

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pulse width modulator . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

System control . . . . . . . . . . . . . . . . . . . . . . . . 19

13

Legal information . . . . . . . . . . . . . . . . . . . . . . 39

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.8

13.1

13.2

13.3

13.4

6.8.1

6.8.2

6.9

6.9.1

6.10

6.10.1

6.10.2

6.11

6.11.1

6.12

6.12.1

6.12.2

6.13

6.13.1

6.14

6.14.1

6.14.2

6.15

6.15.1

6.16

14

15

Contact information . . . . . . . . . . . . . . . . . . . . 40

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.16.1

6.17

6.17.1

6.18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 June 2011

Document identifier: LPC2194


型号：	LPC2194HBD64/00,15
厂家：	NXP
描述：	LPC2194HBD64 PC
文件：	总41页 (文件大小：231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC2194HBD64/00,15 [NXP]

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