LPC2212FBD101 [NXP]
Single-chip 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC; 单芯片16位/ 32位ARM微控制器; 128/256 KB ISP / IAP闪存与10位ADC型号: | LPC2212FBD101 |
厂家: | NXP |
描述: | Single-chip 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC |
文件: | 总47页 (文件大小:322K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers; 128/256 kB
ISP/IAP flash with 10-bit ADC and external memory interface
Rev. 5 — 14 June 2011
Product data sheet
1. General description
The LPC2212/2214 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation
and embedded trace support, together with 128/256 kB of embedded high-speed flash
memory. A 128-bit wide memory interface and a unique accelerator architecture enable
32-bit code execution at maximum clock rate. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel
10-bit ADC, PWM channels and up to nine external interrupt pins these microcontrollers
are particularly suitable for industrial control, medical systems, access control and
point-of-sale. Number of available fast GPIOs ranges from up to 76 pins (with external
memory) through up to 112 pins (single-chip). With a wide range of serial communications
interfaces, they are also very well suited for communication gateways, protocol converters
and embedded soft modems as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2212/2214 will apply to devices with
and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate
from other devices only when necessary.
2. Features and benefits
2.1 Key features brought by LPC2212/2214/01 devices
Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
SPI programmable data length and master mode enhancement.
Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2212/2214/00 devices as well.
General purpose timers can operate as external event counters.
2.2 Key features common for all devices
16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
16 kB on-chip static RAM and 128/256 kB on-chip flash program memory. 128-bit wide
interface/accelerator enables high speed 60 MHz operation.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or
full chip erase takes 400 ms.
EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software as well as high speed real-time tracing of instruction
execution.
Eight-channel 10-bit ADC with conversion time as low as 2.44 s.
Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock and Watchdog.
Multiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s) and
two SPIs.
Vectored Interrupt Controller with configurable priorities and vector addresses.
Configurable external memory interface with up to four banks, each up to 16 MB and
8/16/32-bit data width.
Up to 112 general purpose I/O pins (5 V tolerant). Up to nine edge or level sensitive
external interrupt pins available.
60 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop with settling time of 100 s.
On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
Two low power modes, Idle and Power-down.
Processor wake-up from Power-down mode via external interrupt.
Individual enable/disable of peripheral functions for power optimization.
Dual power supply:
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V 0.15 V).
I/O power supply range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC2212FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; SOT486-1
body 20 20 1.4 mm
LPC2214FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; SOT486-1
body 20 20 1.4 mm
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
2 of 47
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
3.1 Ordering options
Table 2.
Ordering options
Type number
Flash memory RAM
Fast GPIO/
SSP/
Temperature range
Enhanced
UART, ADC,
Timer
LPC2212FBD144/01
LPC2214FBD144/01
128 kB
256 kB
16 kB
16 kB
yes
yes
40 C to +85 C
40 C to +85 C
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
3 of 47
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
4. Block diagram
(2)
(2)
TMS
(2)
TDI
(2)
RTCK
(2)
XTAL2
TRST
TCK
TDO
XTAL1
RESET
TEST/DEBUG
INTERFACE
V
V
V
LPC2212
LPC2214
DD(3V3)
DD(1V8)
SS
SYSTEM
FUNCTIONS
PLL
ARM7TDMI-S
system
clock
HIGH-SPEED
VECTORED
INTERRUPT
CONTROLLER
(3)
P0, P1
GPI/O
AHB BRIDGE
48 PINS TOTAL
AMBA Advanced High-performance
Bus (AHB)
ARM7 LOCAL BUS
INTERNAL
INTERNAL
SRAM
FLASH
CONTROLLER
CONTROLLER
AHB
DECODER
(1)
CS[3:0]
A[23:0]
16 kB
SRAM
128/256 kB
FLASH
AHB TO APB
BRIDGE
APB
DIVIDER
(1)
EXTERNAL MEMORY
CONTROLLER
(1)
BLS[3:0]
(1)
OE, WE
(1)
D[31:0]
EXTERNAL
(1)
EINT[3:0]
INTERRUPTS
(1)
SCL
2
I C-BUS SERIAL
INTERFACE
(1)
(1)
(1)
(1)
4 × CAP0
4 × CAP1
4 × MAT0
4 × MAT1
(1)
SDA
CAPTURE/
COMPARE
TIMER 0/TIMER 1
(1)
SCK1
(1)
(3)
MOSI1
MISO1
SSEL1
SPI1/SSP SERIAL
(1)
(1)
INTERFACE
(1)
(1)
AIN[3:0]
AIN[7:4]
A/D CONVERTER
(1)
SCK0
P0[30:27],
P0[25:0]
(1)
(1)
(1)
MOSI0
MISO0
SSEL0
SPI0 SERIAL
INTERFACE
P1[31:16],
P1[1:0]
GENERAL
PURPOSE I/O
P2[31:0]
P3[31:0]
(1)
TXD[1:0]
(1)
UART0/UART1
RXD[1:0]
(1)
(1)
DSR1 , CTS1
RTS1 , DTR1
DCD1 , RI1
,
(1)
PWM[6:1]
PWM0
(1)
(1)
,
(1)
(1)
WATCHDOG
TIMER
SYSTEM CONTROL
REAL-TIME CLOCK
002aad181
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) SSP interface and high-speed GPIO are available on LPC2212/01 and LPC2214/01 only.
Fig 1. Block diagram
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
4 of 47
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
5. Pinning information
5.1 Pinning
1
108
LPC2212
LPC2214(1)
36
73
002aad182
(1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 2. Pin configuration (LQFP144)
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
5 of 47
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
5.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type Description
P0[0] to P0[31]
I/O
Port 0 is a 32-bit bidirectional I/O port with individual direction controls for
each bit. The operation of port 0 pins depends upon the pin function selected
via the Pin Connect Block.
Pins 26 and 31 of port 0 are not available.
TXD0 — Transmitter output for UART0.
PWM1 — Pulse Width Modulator output 1.
RXD0 — Receiver input for UART0.
PWM3 — Pulse Width Modulator output 3.
EINT0 — External interrupt 0 input
P0[0]/TXD0/PWM1
42
49
O
O
I
P0[1]/RXD0/PWM3/
EINT0
O
I
P0[2]/SCL/CAP0[0]
50
58
I/O
SCL — I2C-bus clock input/output. Open-drain output (for I2C-bus
compliance).
I
CAP0[0] — Capture input for Timer 0, channel 0.
SDA — I2C-bus data input/output. Open-drain output (for I2C-bus
compliance).
P0[3]/SDA/MAT0[0]/
EINT1
I/O
O
I
MAT0[0] — Match output for Timer 0, channel 0.
EINT1 — External interrupt 1 input.
P0[4]/SCK0/CAP0[1]
P0[5]/MISO0/MAT0[1]
59
61
I/O
I
SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
CAP0[1] — Capture input for Timer 0, channel 1.
I/O
MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data
output from SPI slave.
O
MAT0[1] — Match output for Timer 0, channel 1.
P0[6]/MOSI0/CAP0[2]
68
69
I/O
MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave.
I
CAP0[2] — Capture input for Timer 0, channel 2.
SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
PWM2 — Pulse Width Modulator output 2.
EINT2 — External interrupt 2 input.
P0[7]/SSEL0/PWM2/
EINT2
I
O
I
P0[8]/TXD1/PWM4
75
76
O
O
I
TXD1 — Transmitter output for UART1.
PWM4 — Pulse Width Modulator output 4.
RXD1 — Receiver input for UART1.
P0[9]/RXD1/PWM6/
EINT3
O
I
PWM6 — Pulse Width Modulator output 6.
EINT3 — External interrupt 3 input.
P0[10]/RTS1/CAP1[0]
P0[11]/CTS1/CAP1[1]
P0[12]/DSR1/MAT1[0]
P0[13]/DTR1/MAT1[1]
78
83
84
85
O
I
RTS1 — Request to Send output for UART1.
CAP1[0] — Capture input for Timer 1, channel 0.
CTS1 — Clear to Send input for UART1.
I
I
CAP1[1] — Capture input for Timer 1, channel 1.
DSR1 — Data Set Ready input for UART1.
MAT1[0] — Match output for Timer 1, channel 0.
DTR1 — Data Terminal Ready output for UART1.
MAT1[1] — Match output for Timer 1, channel 1.
I
O
O
O
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
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LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
Table 3.
Pin description …continued
Symbol
Pin
Type Description
P0[14]/DCD1/EINT1
92
I
I
DCD1 — Data Carrier Detect input for UART1.
EINT1 — External interrupt 1 input.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take
over control of the part after reset.
P0[15]/RI1/EINT2
99
I
RI1 — Ring Indicator input for UART1.
I
EINT2 — External interrupt 2 input.
P0[16]/EINT0/MAT0[2]/ 100
CAP0[2]
I
EINT0 — External interrupt 0 input.
O
MAT0[2] — Match output for Timer 0, channel 2.
CAP0[2] — Capture input for Timer 0, channel 2.
CAP1[2] — Capture input for Timer 1, channel 2.
I
P0[17]/CAP1[2]/SCK1/
MAT1[2]
101
I
I/O
SCK1 — Serial Clock for SPI1/SSP[1]. SPI clock output from master or input
to slave.
O
I
MAT1[2] — Match output for Timer 1, channel 2.
P0[18]/CAP1[3]/MISO1/ 121
MAT1[3]
CAP1[3] — Capture input for Timer 1, channel 3.
MISO1 — Master In Slave Out for SPI1/SSP[1]. Data input to SPI master or
I/O
data output from SPI slave.
O
MAT1[3] — Match output for Timer 1, channel 3.
P0[19]/MAT1[2]/MOSI1/ 122
CAP1[2]
O
MAT1[2] — Match output for Timer 1, channel 2.
MOSI1 — Master Out Slave In for SPI1/SSP[1]. Data output from SPI master
I/O
or data input to SPI slave.
I
CAP1[2] — Capture input for Timer 1, channel 2.
MAT1[3] — Match output for Timer 1, channel 3.
SSEL1 — Slave Select for SPI1/SSP[1]. Selects the SPI interface as a slave.
EINT3 — External interrupt 3 input.
P0[20]/MAT1[3]/SSEL1/ 123
EINT3
O
I
I
P0[21]/PWM5/CAP1[3]
4
O
I
PWM5 — Pulse Width Modulator output 5.
CAP1[3] — Capture input for Timer 1, channel 3.
CAP0[0] — Capture input for Timer 0, channel 0.
MAT0[0] — Match output for Timer 0, channel 0.
General purpose bidirectional digital port only.
P0[22]/CAP0[0]/MAT0[0] 5
I
O
I/O
I/O
I/O
I
P0[23]
P0[24]
P0[25]
6
8
General purpose bidirectional digital port only.
21
23
General purpose bidirectional digital port only.
P0[27]/AIN0/CAP0[1]/
MAT0[1]
AIN0 — ADC, input 0. This analog input is always connected to its pin.
CAP0[1] — Capture input for Timer 0, channel 1.
MAT0[1] — Match output for Timer 0, channel 1.
AIN1 — ADC, input 1. This analog input is always connected to its pin.
CAP0[2] — Capture input for Timer 0, channel 2.
MAT0[2] — Match output for Timer 0, channel 2.
AIN2 — ADC, input 2. This analog input is always connected to its pin.
CAP0[3] — Capture input for Timer 0, Channel 3.
MAT0[3] — Match output for Timer 0, channel 3.
I
O
I
P0[28]/AIN1/CAP0[2]/
MAT0[2]
25
32
I
O
I
P0[29]/AIN2/CAP0[3]/
MAT0[3]
I
O
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
7 of 47
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
Table 3.
Symbol
Pin description …continued
Pin
Type Description
P0[30]/AIN3/EINT3/
CAP0[0]
33
I
AIN3 — ADC, input 3. This analog input is always connected to its pin.
EINT3 — External interrupt 3 input.
I
I
CAP0[0] — Capture input for Timer 0, channel 0.
P1[0] to P1[31]
P1[0]/CS0
I/O
Port 1 is a 32-bit bidirectional I/O port with individual direction controls for
each bit. The operation of port 1 pins depends upon the pin function selected
via the Pin Connect Block.
Pins 2 through 15 of port 1 are not available.
91
O
LOW-active Chip Select 0 signal.
(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)
LOW-active Output Enable signal.
P1[1]/OE
90
34
24
15
7
O
O
O
O
O
O
P1[16]/TRACEPKT0
P1[17]/TRACEPKT1
P1[18]/TRACEPKT2
P1[19]/TRACEPKT3
P1[20]/TRACESYNC
Trace Packet, bit 0. Standard I/O port with internal pull-up.
Trace Packet, bit 1. Standard I/O port with internal pull-up.
Trace Packet, bit 2. Standard I/O port with internal pull-up.
Trace Packet, bit 3. Standard I/O port with internal pull-up.
Trace Synchronization; standard I/O port with internal pull-up.
102
Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to
operate as Trace port after reset.
P1[21]/PIPESTAT0
P1[22]/PIPESTAT1
P1[23]/PIPESTAT2
P1[24]/TRACECLK
P1[25]/EXTIN0
95
86
82
70
60
52
O
O
O
O
I
Pipeline Status, bit 0. Standard I/O port with internal pull-up.
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
Trace Clock. Standard I/O port with internal pull-up.
External Trigger Input. Standard I/O with internal pull-up.
P1[26]/RTCK
I/O
Returned Test Clock output. Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin
with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to
operate as Debug port after reset.
P1[27]/TDO
P1[28]/TDI
P1[29]/TCK
144
140
126
O
I
Test Data out for JTAG interface.
Test Data in for JTAG interface.
Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU
I
clock (CCLK) for the JTAG interface to operate.
P1[30]/TMS
113
43
I
Test Mode Select for JTAG interface.
Test Reset for JTAG interface.
P1[31]/TRST
P2[0] to P2[31]
I
I/O
Port 2 is a 32-bit bidirectional I/O port with individual direction controls for
each bit. The operation of port 2 pins depends upon the pin function selected
via the Pin Connect Block.
P2[0]/D0
P2[1]/D1
P2[2]/D2
P2[3]/D3
P2[4]/D4
P2[5]/D5
P2[6]/D6
98
I/O
I/O
I/O
I/O
I/O
I/O
I/O
External memory data line 0.
External memory data line 1.
External memory data line 2.
External memory data line 3.
External memory data line 4.
External memory data line 5.
External memory data line 6.
105
106
108
109
114
115
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
8 of 47
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
Table 3.
Pin description …continued
Type Description
External memory data line 7.
External memory data line 8.
Symbol
Pin
116
117
118
120
124
125
127
129
130
131
132
133
134
136
137
1
P2[7]/D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
P2[8]/D8
P2[9]/D9
External memory data line 9.
External memory data line 10.
External memory data line 11.
External memory data line 12.
External memory data line 13.
External memory data line 14.
External memory data line 15.
External memory data line 16.
External memory data line 17.
External memory data line 18.
External memory data line 19.
External memory data line 20.
External memory data line 21.
External memory data line 22.
External memory data line 23.
External memory data line 24.
External memory data line 25.
D26 — External memory data line 26.
P2[10]/D10
P2[11]/D11
P2[12]/D12
P2[13]/D13
P2[14]/D14
P2[15]/D15
P2[16]/D16
P2[17]/D17
P2[18]/D18
P2[19]/D19
P2[20]/D20
P2[21]/D21
P2[22]/D22
P2[23]/D23
P2[24]/D24
P2[25]/D25
P2[26]/D26/BOOT0
10
11
12
13
BOOT0 — While RESET is LOW, together with BOOT1 controls booting and
internal operation. Internal pull-up ensures HIGH state if pin is left
unconnected.
P2[27]/D27/BOOT1
16
I/O
I
D27 — External memory data line 27.
BOOT1 — While RESET is LOW, together with BOOT0 controls booting and
internal operation. Internal pull-up ensures HIGH state if pin is left
unconnected.
BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.
BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.
BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.
BOOT1:0 = 11 selects internal flash memory.
External memory data line 28.
P2[28]/D28
17
18
19
I/O
I/O
I/O
I
P2[29]/D29
External memory data line 29.
P2[30]/D30/AIN4
D30 — External memory data line 30.
AIN4 — ADC, input 4. This analog input is always connected to its pin.
D31 — External memory data line 31.
P2[31]/D31/AIN5
P3[0] to P3[31]
20
I/O
I
AIN5 — ADC, input 5. This analog input is always connected to its pin.
I/O
Port 3 is a 32-bit bidirectional I/O port with individual direction controls for
each bit. The operation of port 3 pins depends upon the pin function selected
via the Pin Connect Block.
P3[0]/A0
P3[1]/A1
P3[2]/A2
89
88
87
O
O
O
External memory address line 0.
External memory address line 1.
External memory address line 2.
LPC2212_2214
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
9 of 47
LPC2212/2214
NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
Table 3.
Pin description …continued
Type Description
External memory address line 3.
External memory address line 4.
Symbol
Pin
81
80
74
73
72
71
66
65
64
63
62
56
55
53
48
47
46
45
44
41
40
P3[3]/A3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P3[4]/A4
P3[5]/A5
External memory address line 5.
P3[6]/A6
External memory address line 6.
P3[7]/A7
External memory address line 7.
P3[8]/A8
External memory address line 8.
P3[9]/A9
External memory address line 9.
P3[10]/A10
P3[11]/A11
P3[12]/A12
P3[13]/A13
P3[14]/A14
P3[15]/A15
P3[16]/A16
P3[17]/A17
P3[18]/A18
P3[19]/A19
P3[20]/A20
P3[21]/A21
P3[22]/A22
P3[23]/A23/XCLK
External memory address line 10.
External memory address line 11.
External memory address line 12.
External memory address line 13.
External memory address line 14.
External memory address line 15.
External memory address line 16.
External memory address line 17.
External memory address line 18.
External memory address line 19.
External memory address line 20.
External memory address line 21.
External memory address line 22.
A23 — External memory address line 23.
XCLK — Clock output.
P3[24]/CS3
P3[25]/CS2
P3[26]/CS1
36
35
30
LOW-active Chip Select 3 signal.
(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)
LOW-active Chip Select 2 signal.
O
O
(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)
LOW-active Chip Select 1 signal.
(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)
LOW-active Write enable signal.
P3[27]/WE
29
28
O
O
I
P3[28]/BLS3/AIN7
BLS3 — LOW-active Byte Lane Select signal (Bank 3).
AIN7 — ADC, input 7. This analog input is always connected to its pin.
BLS2 — LOW-active Byte Lane Select signal (Bank 2).
AIN6 — ADC, input 6. This analog input is always connected to its pin.
LOW-active Byte Lane Select signal (Bank 1).
LOW-active Byte Lane Select signal (Bank 0).
Pin not connected.
P3[29]/BLS2/AIN6
27
O
I
P3[30]/BLS1
P3[31]/BLS0
n.c.
97
O
O
96
22
RESET
135
I
external reset input; a LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1
XTAL2
142
141
I
input to the oscillator circuit and internal clock generator circuits.
output from the oscillator amplifier.
O
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Table 3.
Symbol
VSS
Pin description …continued
Pin
Type Description
3, 9, 26,
38, 54, 67,
79, 93,
I
ground: 0 V reference
103, 107,
111, 128
VSSA
139
I
I
analog ground; 0 V reference. This should nominally be the same voltage as
VSS, but should be isolated to minimize noise and error.
VSSA(PLL)
138
PLL analog ground; 0 V reference. This should nominally be the same voltage
as VSS, but should be isolated to minimize noise and error.
VDD(1V8)
37, 110
143
I
I
1.8 V core power supply; this is the power supply voltage for internal circuitry.
VDDA(1V8)
analog 1.8 V core power supply; this is the power supply voltage for internal
circuitry. This should be nominally the same voltage as VDD(1V8) but should be
isolated to minimize noise and error.
VDD(3V3)
2, 31, 39,
51, 57, 77,
94, 104,
I
I
3.3 V pad power supply; this is the power supply voltage for the I/O ports
112, 119
VDDA(3V3)
14
analog 3.3 V pad power supply; this should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error
[1] SSP interface is available on LPC2212/01 and LPC2214/01 only.
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6. Functional description
Details of the LPC2212/2214 systems and peripheral functions are described in the
following sections.
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-chip flash program memory
The LPC2212/2214 incorporate a 128 kB and 256 kB flash memory system respectively.
This memory may be used for both code and data storage. Programming of the flash
memory may be accomplished in several ways. It may be programmed In System via the
serial port. The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field firmware
upgrades, etc. When on-chip bootloader is used, 120/248 kB of flash memory is available
for user code.
The LPC2212/2214 flash memory provides a minimum of 100000 erase/write cycles and
20 years of data retention.
On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2212/2214 on-chip flash memory. When the CRP is enabled, the JTAG debug port,
external memory boot and ISP commands accessing either the on-chip RAM or flash
memory are disabled. However, the ISP flash erase command can be executed at any
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time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of
full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is
restored.
6.3 On-chip static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8 bit, 16 bit, and 32 bit. The LPC2212/2214 provide 16 kB of static RAM.
6.4 Memory map
The LPC2212/2214 memory maps incorporate several distinct regions, as shown in the
following figures.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.18
“System control”.
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4.0 GB
3.75 GB
3.5 GB
0xFFFF FFFF
AHB PERIPHERALS
0xF000 0000
0xEFFF FFFF
APB PERIPHERALS
0xE000 0000
0xDFFF FFFF
0xC000 0000
3.0 GB
RESERVED ADDRESS SPACE
0x8000 0000
0x7FFF FFFF
2.0 GB
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY)
0x7FFF E000
0x7FFF DFFF
RESERVED ADDRESS SPACE
16 kB ON-CHIP STATIC RAM
0x4000 4000
0x4000 3FFF
0x4000 0000
0x3FFF FFFF
1.0 GB
RESERVED ADDRESS SPACE
0x0004 0000
0x0003 FFFF
256 kB ON-CHIP FLASH MEMORY (LPC2214)
128 kB ON-CHIP FLASH MEMORY (LPC2212)
0x0002 0000
0x0001 FFFF
0x0000 0000
0.0 GB
002aad183
Fig 3. LPC2212/2214 memory map
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt ReQuest (IRQ), and
non-vectored IRQ as defined by programmable settings. The programmable assignment
scheme means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.
The FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.
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Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.
Table 4.
Block
Interrupt sources
Flag(s)
VIC channel #
WDT
Watchdog Interrupt (WDINT)
0
1
2
3
4
5
6
-
Reserved for software interrupts only
EmbeddedICE, DbgCommRx
EmbeddedICE, DbgCommTx
Match 0 to 3 (MR0, MR1, MR2, MR3)
Match 0 to 3 (MR0, MR1, MR2, MR3)
Rx Line Status (RLS)
ARM Core
ARM Core
Timer 0
Timer 1
UART0
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Rx Line Status (RLS)
UART1
7
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
SI (state change)
PWM0
I2C-bus
SPI0
8
9
SPIF, MODF
10
11
12
13
14
15
16
17
18
SPI1 and SSP[1] SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS
PLL
PLL Lock (PLOCK)
RTC
RTCCIF (Counter Increment), RTCALF (Alarm)
System Control External Interrupt 0 (EINT0)
External Interrupt 1 (EINT1)
External Interrupt 2 (EINT2)
External Interrupt 3 (EINT3)
ADC
ADC
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[1] SSP interface available on LPC2212/01 and LPC2214/01 only.
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
6.7 External memory controller
The external Static Memory Controller (SMC) is a module which provides an interface
between the system bus and external (off-chip) memory devices. It provides support for
up to four independently configurable memory banks (16 MB each with byte lane enable
control) simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash
EPROM, burst ROM memory, or some external I/O devices.
Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
6.8 General purpose parallel I/O (GPIO) and Fast I/O
Device pins that are not connected to a specific peripheral function are controlled by the
parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
6.8.1 Features
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.8.2 Features added with the Fast GPIO set of registers available on
LPC2212/2214/01 only
• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O
timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All Fast GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
• Ports are accessible via either the legacy group of registers (GPIOs) or the group of
registers providing accelerated port access (Fast GPIOs).
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6.9 10-bit ADC
The LPC2212/2214 each contain a single 10-bit successive approximation ADC with four
multiplexed channels.
6.9.1 Features
• Measurement range of 0 V to 3 V.
• Capable of performing more than 400000 10-bit samples per second.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
6.9.2 ADC features available in LPC2212/2214/01 only
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Every analog input can generate an interrupt once the conversion is completed.
• The ADC pads are 5 V tolerant when configured for digital I/O function(s).
6.10 UARTs
The LPC2212/2214 each contain two UARTs. In addition to standard transmit and receive
data lines, the UART1 also provides a full modem control handshake interface.
6.10.1 Features
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
• UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
6.10.2 UART features available in LPC2212/2214/01 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2212/2214/01 introduce
a fractional baud rate generator for both UARTs, enabling these microcontrollers to
achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz.
In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.
• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
• Auto-bauding.
• Auto-CTS/RTS flow-control fully implemented in hardware.
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6.11 I2C-bus serial I/O controller
The I2C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock
line (SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus; it can be
controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2212/2214 supports a bit rate up to 400 kbit/s (Fast
I2C-bus).
6.11.1 Features
• Standard I2C-bus compliant interface.
• Easy to configure as Master, Slave, or Master/Slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus may be used for test and diagnostic purposes.
6.12 SPI serial I/O controller
The LPC2212/2214 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
6.12.1 Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex communication.
• Combined SPI master and slave.
• Maximum data bit rate of 1⁄8 of the input clock rate.
6.12.2 Features available in LPC2212/2214/01 only
• Eight to 16 bits per frame.
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• When the SPI interface is used in Master mode, the SSEL pin is not needed (can be
used for a different function).
6.13 SSP controller (LPC2212/2214/01 only)
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI1 to SSP and back.
6.13.1 Features
• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• Four to 16 bits per frame.
6.14 General purpose timers
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.14.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
• Timer or external event counter operation
• Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs per timer corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
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– Toggle on match.
– Do nothing on match.
6.14.2 Features available in LPC2212/2214/01 only
The LPC2212/2214/01 can count external events on one of the capture inputs if the
external pulse lasts at least one half of the period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs, or used as external
interrupts.
• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied
clock.
• When counting cycles of an externally supplied clock, only one of the timer’s capture
inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK / 4. Duration of high/low levels on the selected CAP input cannot be shorter
than 1 / (2PCLK).
6.15 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined
amount of time.
6.15.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal prescaler.
• Selectable time period from (Tcy(PCLK) 256 4) to (Tcy(PCLK) 232 4) in multiples of
Tcy(PCLK) 4.
6.16 Real-time clock
The RTC is designed to provide a set of counters to measure time when normal or idle
operating mode is selected. The RTC has been designed to use little power, making it
suitable for battery powered systems where the CPU is not running continuously (Idle
mode).
6.16.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
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• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
• Programmable reference clock divider allows adjustment of the RTC to match various
crystal frequencies.
6.17 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2212/2214. The Timer is designed to
count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform
other actions when specified timer values occur, based on seven match registers. The
PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
6.17.1 Features
• Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
• The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
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• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
6.18 System control
6.18.1 Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output
frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for
purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is
running and connected. Refer to Section 6.18.2 “PLL” for additional information.
6.18.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and
bypassed following a chip Reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a
clock source. The PLL settling time is 100 s.
6.18.3 Reset and wake-up timer
Reset has two sources on the LPC2212/2214: the RESET pin and Watchdog Reset. The
RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip
Reset by any source starts the Wake-up Timer (see Wake-up Timer description below),
causing the internal chip reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the on-chip flash
controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The Wake-up Timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute instructions.
This is important at power on, all types of Reset, and whenever any of the aforementioned
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functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.18.4 Code security (Code Read Protection - CRP)
This feature of the LPC2212/2214 allows the user to enable different levels of security in
the system so that access to the on-chip flash and use of the JTAG and ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
Remark: Devices without the suffix /00 or /01 have only a security level equivalent to
CRP2 available.
6.18.5 External interrupt inputs
The LPC2212/2214 include up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be processed
as four independent interrupt signals. The External Interrupt Inputs can optionally be used
to wake up the processor from Power-down mode.
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6.18.6 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
6.18.7 Power control
The LPC2212/2214 support two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
6.18.8 APB
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB may be slowed
down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB bus must work properly at
power-up (and its timing cannot be altered if it does not work since the APB divider control
registers reside on the APB), the default condition at reset is for the APB to run at 1⁄4 of the
processor clock rate. The second purpose of the APB divider is to allow power savings
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.
6.19 Emulation and debugging
The LPC2212/2214 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only
with GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are available during the development and debugging phase as they are
when the application is run in the embedded system itself.
6.19.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
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The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG
interface to operate.
6.19.2 Embedded trace macrocell
Since the LPC2212/2214 have significant amounts of on-chip memory, it is not possible to
determine how the processor core is operating simply by observing the external pins. The
Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply
embedded processor cores. It outputs information about processor execution to the trace
port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code can not be traced
because of this restriction.
6.19.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC (Debug
Communications Channel), which is present in the EmbeddedICE logic. The
LPC2212/2214 contain a specific configuration of RealMonitor software programmed into
the on-chip flash memory.
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7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
VDD(1V8)
VDD(3V3)
VDDA(3V3)
VIA
Parameter
Conditions
Min
0.5
0.5
0.5
0.5
0.5
0.5
-
Max
Unit
V
[2]
[3]
supply voltage (1.8 V)
supply voltage (3.3 V)
analog supply voltage (3.3 V)
analog input voltage
input voltage
+2.5
+3.6
V
+4.6
V
+5.1
V
[4][5]
[4][6]
[7][8]
[8][9]
VI
5 V tolerant I/O pins
other I/O pins
+6.0
V
VDD(3V3) + 0.5
100
V
IDD
supply current
mA
mA
C
C
W
ISS
ground current
-
100
Tj
junction temperature
storage temperature
-
150
[10]
Tstg
Ptot(pack)
65
-
+150
1.5
total power dissipation (per
package)
based on package heat
transfer, not device
power consumption
[11]
[12]
Vesd
electrostatic discharge voltage human body model
all pins
2000
200
+2000
+200
V
V
machine model
all pins
[1] The following applies to Table 5:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] Only valid when the VDD(3V3) supply voltage is present.
[6] Not to exceed 4.6 V.
[7] Per supply pin.
[8] The peak current is limited to 25 times the corresponding maximum current.
[9] Per ground pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[12] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 series resistor.
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8. Static characteristics
Table 6.
Static characteristics
Tamb = 40 C to +85 C for industrial applications, unless otherwise specified.
Symbol Parameter
Conditions
Min
1.65
3.0
Typ[1]
1.8
Max
1.95
3.6
Unit
V
[2]
[3]
VDD(1V8) supply voltage (1.8 V)
VDD(3V3) supply voltage (3.3 V)
3.3
V
VDDA(3V3) analog supply voltage
(3.3 V)
2.5
3.3
3.6
V
Standard port pins, RESET, RTCK
IIL
LOW-level input current
HIGH-level input current
VI = 0 V; no pull-up
-
-
-
-
3
3
A
A
IIH
VI = VDD(3V3); no
pull-down
IOZ
OFF-state output current
I/O latch-up current
VO = 0 V; VO = VDD(3V3)
no pull-up/down
;
-
-
-
3
-
A
Ilatch
(0.5VDD(3V3)) < VI <
100
mA
(1.5VDD(3V3)); Tj < 125 C
[4][5][6]
VI
input voltage
0
-
-
-
-
-
5.5
V
VO
output voltage
output active
0
VDD(3V3)
V
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
hysteresis voltage
2.0
-
-
V
0.8
V
Vhys
VOH
VOL
IOH
IOL
0.4
-
V
[7]
[7]
[7]
[7]
[8]
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
LOW-level output current
IOH = 4 mA
IOL = 4 mA
VDD(3V3) 0.4 -
-
V
-
-
-
-
-
0.4
-
V
VOH = VDD(3V3) 0.4 V
VOL = 0.4 V
4
4
-
mA
mA
mA
-
IOHS
HIGH-level short-circuit
output current
VOH = 0 V
45
[8]
IOLS
LOW-level short-circuit
output current
VOL = VDD(3V3)
-
-
50
mA
[9]
[10]
[9]
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
10
15
0
50
50
0
150
85
0
A
A
A
VI = 0 V
VDD(3V3) < VI < 5 V
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Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C for industrial applications, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Power consumption LPC2212, LPC2212/00, LPC2214, LPC2214/00
IDD(act)
active mode supply current VDD(1V8) = 1.8 V;
CCLK = 60 MHz;
-
60
-
mA
T
amb = 25 C; code
while(1){}
executed from flash; all
peripherals enabled via
PCONP[11] register but not
configured to run
IDD(pd)
Power-down mode supply VDD(1V8) = 1.8 V;
-
-
10
-
A
A
current
Tamb = 25 C
VDD(1V8) = 1.8 V;
110
500
T
amb = 85 C
Power consumption LPC2212/01 and LPC2214/01
IDD(act)
active mode supply current VDD(1V8) = 1.8 V;
CCLK = 60 MHz;
-
41
-
mA
Tamb = 25 C; code
while(1){}
executed from flash; all
peripherals enabled via
PCONP[11] register but not
configured to run
IDD(idle)
Idle mode supply current
VDD(1V8) = 1.8 V;
CCLK = 60 MHz;
Tamb = 25 C;
-
6.5
-
mA
executed from flash; all
peripherals enabled via
PCONP[11] register but not
configured to run
IDD(pd)
Power-down mode supply VDD(1V8) = 1.8 V;
-
-
10
-
A
A
current
Tamb = 25 C
VDD(1V8) = 1.8 V;
110
500
T
amb = 85 C
I2C-bus pins
VIH
VIL
HIGH-level input voltage
0.7VDD(3V3)
-
-
V
LOW-level input voltage
hysteresis voltage
-
-
-
-
-
-
0.3VDD(3V3)
V
Vhys
VOL
ILI
0.05VDD(3V3)
-
V
[7]
LOW-level output voltage
input leakage current
IOLS = 3 mA
VI = VDD(3V3)
VI = 5 V
-
0.4
4
V
[12]
2
A
A
10
22
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Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C for industrial applications, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Oscillator pins
Vi(XTAL1) input voltage on pin XTAL1
0
0
-
-
1.8
1.8
V
V
Vo(XTAL2) output voltage on pin
XTAL2
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5]
VDD(3V3) supply voltages must be present.
[6] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[7] Accounts for 100 mV voltage drop in all supply lines.
[8] Only allowed for a short time period.
[9] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[10] Applies to P1[25:16].
[11] See the LPC2114/2124/2212/2214 User Manual.
[12] To VSS
.
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Table 7.
ADC static characteristics
VDDA = 2.5 V to 3.6 V unless otherwise specified; Tamb = 40 C to +85 C unless otherwise specified. ADC frequency
4.5 MHz.
Symbol
VIA
Parameter
Conditions
Min
Typ
Max
VDDA
1
Unit
V
analog input voltage
0
-
-
-
Cia
analog input
capacitance
pF
[1][2][3]
ED
differential linearity
error
-
-
1
LSB
[1][4]
[1][5]
[1][6]
[1][7]
EL(adj)
EO
integral non-linearity
offset error
-
-
-
-
-
-
-
-
2
LSB
LSB
%
3
EG
gain error
0.5
4
ET
absolute error
LSB
[1] Conditions: VSSA = 0 V, VDDA = 3.3 V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 4.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 4.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 4.
[7] The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the
non-calibrated ADC and the ideal transfer curve. See Figure 4.
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gain
error
offset
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
(LSB
)
ideal
IA
V
− V
SSA
DDA
1 LSB =
offset
error
1024
002aaa668
E
O
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 4. ADC characteristics
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8.1 Power consumption measurements for LPC2212/01 and LPC2214/01
The power consumption measurements represent typical values for the given conditions.
The peripherals were enabled through the PCONP register, but for these measurements,
the peripherals were not configured to run. Peripherals were disabled through the PCONP
register. For a description of the PCONP register refer to the LPC2114/2124/2212/2214
User Manual.
002aad140
50
I
DD(act)
(mA)
40
30
20
10
0
all peripherals enabled
all peripherals disabled
12
20
28
36
44
52
60
frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V.
Fig 5. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different frequencies
002aad142
55
I
DD(act)
(mA)
45
35
25
15
5
60 MHz
48 MHz
12 MHz
1.65
1.80
1.95
voltage (V)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V; all peripherals enabled.
Fig 6. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different voltages
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002aad141
45
60 MHz
48 MHz
I
DD(act)
(mA)
35
25
15
5
12 MHz
1.65
1.80
1.95
voltage (V)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Temp = 25 C; core voltage 1.8 V; all peripherals disabled.
Fig 7. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different voltages
002aad143
8
I
DD(idle)
(mA)
6
all peripherals enabled
all peripherals disabled
4
2
0
12
20
28
36
44
52
60
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V.
Fig 8. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different frequencies
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002aad145
8
I
DD(idle)
(mA)
60 MHz
48 MHz
6
4
2
0
12 MHz
1.65
1.80
1.95
voltage (V)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V; all peripherals enabled.
Fig 9. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different voltages
002aad144
8
I
DD(idle)
(mA)
60 MHz
48 MHz
6
4
2
0
12 MHz
1.65
1.80
1.95
voltage (V)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Temp = 25 C; core voltage 1.8 V; all peripherals disabled.
Fig 10. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different voltages
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002aad146
45
60 MHz
48 MHz
I
DD(act)
(mA)
35
25
15
5
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
core voltage 1.8 V; all peripherals disabled.
Fig 11. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different temperatures
002aad147
6.0
I
DD(idle)
(mA)
5.0
4.0
3.0
2.0
1.0
60 MHz
48 MHz
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
core voltage 1.8 V; all peripherals disabled.
Fig 12. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different temperatures
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002aad148
200
I
DD(pd)
(μA)
1.95 V
1.8 V
160
120
80
1.65 V
40
0
-40
-15
10
35
60
85
temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip flash.
Fig 13. Typical LPC2212/01 and LPC2214/01 core power-down current IDD(pd) measured at different temperatures
Table 8.
Typical LPC2212/01 and LPC2214/01 peripheral power consumption in active
mode
Core voltage 1.8 V; Tamb = 25 C; all measurements in A; PCLK = CCLK⁄4.
Peripheral
Timer0
Timer1
UART0
UART1
PWM0
I2C-bus
SPI0/1
RTC
CCLK = 12 MHz
CCLK = 48 MHz
CCLK = 60 MHz
43
46
98
103
103
9
141
150
320
351
341
37
184
180
398
421
407
53
6
27
29
16
33
306
55
78
ADC
128
994
167
1205
EMC
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9. Dynamic characteristics
Table 9.
T
Dynamic characteristics
amb = 40 C to +85 C for industrial applications; VDD(1V8), VDD(3V3) over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External clock
fosc
oscillator frequency
supplied by an external
oscillator (signal generator)
1
1
-
-
50
30
MHz
MHz
external clock frequency
supplied by an external
crystal oscillator
external clock frequency if
on-chip PLL is used
10
10
-
-
25
25
MHz
MHz
external clock frequency if
on-chip bootloader is used
for initial code download
Tcy(clk)
tCHCX
tCLCX
tCLCH
tCHCL
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
20
-
-
-
-
-
1000
ns
ns
ns
ns
ns
Tcy(clk) 0.4
-
Tcy(clk) 0.4
-
-
-
5
5
Port pins (except P0[2] and P0[3])
tr
tf
rise time
fall time
-
-
10
10
-
-
ns
ns
I2C-bus pins (P0[2] and P0[3])
[2]
tf fall time
VIH to VIL
20 + 0.1 Cb
-
-
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Bus capacitance Cb in pF, from 10 pF to 400 pF.
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Table 10. External memory interface dynamic characteristics
CL = 25 pF; Tamb = 40 C.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Common to read and write cycles
tCHAV
XCLK HIGH to address valid
time
-
-
10
ns
tCHCSL
tCHCSH
XCLK HIGH to CS LOW time
-
-
-
-
10
10
ns
ns
XCLK HIGH to CS HIGH
time
tCHANV
XCLK HIGH to address
invalid time
-
-
10
ns
Read cycle parameters
tCSLAV CS LOW to address valid
[1]
[1]
5
5
5
-
-
+10
+10
ns
ns
time
tOELAV
OE LOW to address valid
time
tCSLOEL
tam
CS LOW to OE LOW time
memory access time
-
-
+5
-
ns
ns
[2][3]
[2][3]
[2][4]
[5]
(Tcy(CCLK) (2 + WST1)) +
(20)
tam(ibr)
tam(sbr)
memory access time (initial
burst-ROM)
(Tcy(CCLK) (2 + WST1)) +
(20)
-
-
-
-
ns
ns
memory access time
Tcy(CCLK) + (20)
(subsequent burst-ROM)
th(D)
data input hold time
0
-
-
-
-
ns
ns
ns
tCSHOEH
tOEHANV
CS HIGH to OE HIGH time
5
5
+5
+5
OE HIGH to address invalid
time
tCHOEL
tCHOEH
XCLK HIGH to OE LOW time
5
5
-
-
+5
+5
ns
ns
XCLK HIGH to OE HIGH
time
Write cycle parameters
[1]
tAVCSL
address valid to CS LOW
Tcy(CCLK) 10
-
-
ns
time
tCSLDV
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
5
-
-
-
-
-
-
+5
+5
+5
+5
+5
ns
ns
ns
ns
ns
ns
tCSLWEL
tCSLBLSL
tWELDV
tCSLDV
5
5
5
5
[2]
[2]
[2]
tWELWEH
Tcy(CCLK) (1 + WST2) 5
Tcy(CCLK) (1 +
WST2) + 5
tBLSLBLSH BLS LOW to BLS HIGH time
Tcy(CCLK) (1 + WST2) 5
Tcy(CCLK) 5
-
-
Tcy(CCLK)
(1 + WST2) + 5
ns
ns
tWEHANV
tWEHDNV
WE HIGH to address invalid
time
Tcy(CCLK) + 5
[2]
[2]
WE HIGH to data invalid time
(2 Tcy(CCLK)) 5
Tcy(CCLK) 5
-
-
(2 Tcy(CCLK)) + 5 ns
Tcy(CCLK) + 5 ns
tBLSHANV BLS HIGH to address invalid
time
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Table 10. External memory interface dynamic characteristics …continued
CL = 25 pF; Tamb = 40 C.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
[2]
tBLSHDNV BLS HIGH to data invalid
time
(2 Tcy(CCLK)) 5
-
-
-
-
-
-
-
(2 Tcy(CCLK)) + 5 ns
tCHDV
XCLK HIGH to data valid
time
-
-
-
-
-
-
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
tCHWEL
tCHBLSL
tCHWEH
tCHBLSH
tCHDNV
XCLK HIGH to WE LOW
time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
[1] Except on initial access, in which case the address is set up Tcy(CCLK) earlier.
1
[2] Tcy(CCLK)
=
⁄
CCLK.
[3] Latest of address valid, CS LOW, OE LOW to data valid.
[4] Address valid to data valid.
[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.
Table 11. Standard read access specifications
Access cycle
Max frequency
WST[1] setting
Memory access time requirement
WST 0; round up to
integer
standard read
2 + WST1
tRAM + 20 ns
tRAM + 20 ns
tRAM tcyCCLK 2 + WST1 – 20 ns
tWRITE tcyCCLK 1 + WST2 – 5 ns
tINIT tcyCCLK 2 + WST1 – 20 ns
tROM tcyCCLK – 20 ns
-------------------------------
fMAX
-------------------------------
WST1
WST2
– 2
tcyCCLK
standard write
1 + WST2
t
– tCYC + 5
--W-----R---I--T---E----------------------------
---------------------------------
fMAX
tWRITE + 5 ns
tcyCCLK
burst read - initial
burst read - subsequent 3
2 + WST1
tINIT + 20 ns
-------------------------------
fMAX
-------------------------------
WST1
– 2
tINIT + 20 ns
tcyCCLK
N/A
1
--------------------------------
fMAX
tROM + 20 ns
[1] See the LPC2114/2124/2212/2214 User Manual for a description of the WSTn bits.
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9.1 Timing
XCLK
t
t
CSHOEH
CSLAV
CS
addr
data
t
t
h(D)
am
t
CSLOEL
t
t
OEHANV
OELAV
OE
t
t
CHOEH
CHOEL
002aaa749
Fig 14. External memory read access
XCLK
CS
t
CSLDV
t
AVCSL
t
WELWEH
t
CSLWEL
t
BLSLBLSH
BLS/WE
t
WEHANV
t
t
WELDV
CSLBLSL
t
BLSHANV
addr
data
t
t
WEHDNV
BLSHDNV
t
CSLDV
OE
002aaa750
Fig 15. External memory write access
LPC2212_2214
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t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 16. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
LPC2212_2214
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10. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
y
X
A
108
109
73
72
Z
E
e
H
A
E
2
A
E
(A )
3
A
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
37
144
1
36
v
M
A
Z
w M
D
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
E
L
L
p
v
w
y
Z
Z
E
θ
1
2
3
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 20.1 20.1
0.17 0.09 19.9 19.9
22.15 22.15
21.85 21.85
0.75
0.45
1.4
1.1
1.4
1.1
mm
1.6
0.25
1
0.2 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-03-14
03-02-20
SOT486-1
136E23
MS-026
Fig 17. Package outline SOT486-1 (LQFP144)
LPC2212_2214
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11. Abbreviations
Table 12. Abbreviations
Acronym
ADC
AMBA
APB
Description
Analog-to-Digital Converter
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
Central Processing Unit
CPU
DCC
EMC
FIFO
GPIO
JTAG
PLL
Debug Communications Channel
External Memory Controller
First In, First Out
General Purpose Input/Output
Joint Test Action Group
Phase-Locked Loop
POR
PWM
RAM
SPI
Power-On Reset
Pulse Width Modulator
Random Access Memory
Serial Peripheral Interface
Static Random Access Memory
Synchronous Serial Interface
Synchronous Serial Port
SRAM
SSI
SSP
TTL
Transistor-Transistor Logic
Universal Asynchronous Receiver/Transmitter
UART
LPC2212_2214
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12. Revision history
Table 13. Revision history
Document ID
Release date
20110614
Data sheet status
Change notice
Supersedes
LPC2212_2214 v.5
Modifications:
Product data sheet
201004021F
LPC2212_2214 v.4
• Table 6 “Static characteristics”; Changed /01 Power-down mode supply current (IDD(pd)
)
from 180 A to 500 A for industrial temperature range.
• Table 6 “Static characteristics”; Moved Vhys voltage from typical to minimum.
• Table 6 “Static characteristics”; Changed I2C pad hysteresis from 0.5VDD(3V3) to
0.05VDD(3V3)
.
LPC2212_2214 v.4
Modifications:
20080103
Product data sheet
-
LPC2212_2214 v.3
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Type number LPC2212FBD144/01 has been added.
• Type number LPC2214FBD144/01 has been added.
• Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP)
and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added.
• Power consumption measurements for LPC2212/01 and LPC2214/01 added.
• Description of JTAG pin TCK has been updated.
LPC2212_2214 v.3
LPC2212_2214 v.2
LPC2212_2214 v.1
20060719
20041223
20040202
Product data sheet
-
-
-
LPC2212_2214 v.2
Product data
LPC2212_2214 v.1
-
Preliminary data
LPC2212_2214
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13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
13.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
13.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
LPC2212_2214
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NXP Semiconductors
Single-chip 16/32-bit ARM microcontrollers
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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15. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
6.17
6.17.1
6.18
Pulse width modulator . . . . . . . . . . . . . . . . . . 21
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
System control . . . . . . . . . . . . . . . . . . . . . . . . 22
Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 22
PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset and wake-up timer. . . . . . . . . . . . . . . . 22
Code security (Code Read Protection - CRP) 23
External interrupt inputs. . . . . . . . . . . . . . . . . 23
Memory mapping control . . . . . . . . . . . . . . . . 24
Power control. . . . . . . . . . . . . . . . . . . . . . . . . 24
APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Emulation and debugging . . . . . . . . . . . . . . . 24
EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 24
Embedded trace macrocell . . . . . . . . . . . . . . 25
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2
2.1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Key features brought by LPC2212/2214/01
devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key features common for all devices . . . . . . . . 1
6.18.1
6.18.2
6.18.3
6.18.4
6.18.5
6.18.6
6.18.7
6.18.8
6.19
2.2
3
3.1
4
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.19.1
6.19.2
6.19.3
6
Functional description . . . . . . . . . . . . . . . . . . 12
Architectural overview . . . . . . . . . . . . . . . . . . 12
On-chip flash program memory . . . . . . . . . . . 12
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 13
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 14
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15
Pin connect block . . . . . . . . . . . . . . . . . . . . . . 16
External memory controller. . . . . . . . . . . . . . . 16
General purpose parallel I/O (GPIO) and
6.1
6.2
6.3
6.4
6.5
6.5.1
6.6
6.7
6.8
7
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26
8
8.1
Static characteristics . . . . . . . . . . . . . . . . . . . 27
Power consumption measurements for
LPC2212/01 and LPC2214/01. . . . . . . . . . . . 32
9
Dynamic characteristics. . . . . . . . . . . . . . . . . 37
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . 44
9.1
10
11
12
Fast I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Features added with the Fast GPIO set of
6.8.1
6.8.2
registers available on LPC2212/2214/01 only 16
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ADC features available in LPC2212/2214/01
only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
UART features available in LPC2212/2214/01
only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2C-bus serial I/O controller . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features available in LPC2212/2214/01 only. 18
SSP controller (LPC2212/2214/01 only). . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
General purpose timers . . . . . . . . . . . . . . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features available in LPC2212/2214/01 only. 20
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
13
Legal information . . . . . . . . . . . . . . . . . . . . . . 45
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 45
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.9
6.9.1
6.9.2
13.1
13.2
13.3
13.4
6.10
6.10.1
6.10.2
14
15
Contact information . . . . . . . . . . . . . . . . . . . . 46
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.11
6.11.1
6.12
6.12.1
6.12.2
6.13
6.13.1
6.14
6.14.1
6.14.2
6.15
6.15.1
6.16
6.16.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 June 2011
Document identifier: LPC2212_2214
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