LPC2214FBD144_技术文档

LPC2212/LPC2214

16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP Flash

with 10-bit ADC and external memory interface

Rev. 02 — 23 December 2004

Product data

1. General description

The LPC2212/LPC2214 are based on a 16/32 bit ARM7TDMI-S™ CPU with real-time

emulation and embedded trace support, together with 128/256 kilobytes (kB) of

embedded high speed ﬂash memory. A 128-bit wide memory interface and a unique

accelerator architecture enable 32-bit code execution at maximum clock rate. For

critical code size applications, the alternative 16-bit Thumb^®Mode reduces code by

more than 30 % with minimal performance penalty.

With their 144 pin package, low power consumption, various 32-bit timers, 8-channel

10-bit ADC, PWM channels and up to 9 external interrupt pins these microcontrollers

are particularly suitable for industrial control, medical systems, access control and

point-of-sale. Number of available GPIOs ranges from 76 (with external memory)

through 112 pins (single-chip). With a wide range of serial communications

interfaces, they are also very well suited for communication gateways, protocol

converters and embedded soft modems as well as many other general-purpose

applications.

2. Features

2.1 Key features

■ 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.

■ 16 kB on-chip Static RAM and 128/256 kB on-chip Flash Program Memory.

128-bit wide interface/accelerator enables high speed 60 MHz operation.

■ In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

boot-loader software. Flash programming takes 1 ms per 512 byte line. Single

sector or full chip erase takes 400 ms.

■ EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with

the on-chip RealMonitor™ software as well as high speed real-time tracing of

instruction execution.

■ Eight channel 10-bit A/D converter with conversion time as low as 2.44 µs.

■ Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs),

Real Time Clock and Watchdog.

■ Multiple serial interfaces including two UARTs (16C550), Fast I²C (400 kbits/s)

and two SPIs.

■ Vectored Interrupt Controller with conﬁgurable priorities and vector addresses.

■ Conﬁgurable external memory interface with up to four banks, each up to 16 Mb

and 8/16/32 bit data width.

■ Up to 112 general purpose I/O pins (5 V tolerant). Up to 9 edge or level sensitive

external interrupt pins available.

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

■ 60 MHz maximum CPU clock available from programmable on-chip

Phase-Locked Loop with settling time of 100 µs.

■ On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.

■ Two low power modes, Idle and Power-down.

■ Processor wake-up from Power-down mode via external interrupt.

■ Individual enable/disable of peripheral functions for power optimization.

■ Dual power supply:

◆ CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).

◆ I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

pads. 16/32-bit ARM7TDMI-S processor.

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

LPC2212FBD144 LQFP144 plastic low-proﬁle quad ﬂat package; 144

SOT486-1

leads; body 20 × 20 × 1.4 mm

LPC2214FBD144 LQFP144 plastic low-proﬁle quad ﬂat package; 144

SOT486-1

leads; body 20 × 20 × 1.4 mm

3.1 Ordering options

Table 2:

Part options

Type number

Flash memory RAM

CAN

Temperature

range (°C)

LPC2212FBD144

LPC2214FBD144

128 kB

256 kB

16 kB

-

−40 to +85

9397 750 13149

Product data

Rev. 02 — 23 December 2004

2 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

4. Block diagram

TEST/DEBUG

INTERFACE

SYSTEM

PLL

FUNCTIONS

ARM7TDMI-S

system

clock

VECTORED INTERRUPT

CONTROLLER

AHB BRIDGE

ARM7 LOCAL BUS

AMBA AHB

(Advanced High-performance Bus)

INTERNAL SRAM

CONTROLLER

INTERNAL

FLASH

AHB

CONTROLLER

DECODER

CS3:0*

AHB TO VPB

BRIDGE

VPB

DIVIDER

16 kB

SRAM

A23:0*

BLS3:0*

OE, WE*

D31:0*

128/256 kB

FLASH

EXTERNAL MEMORY

CONTROLLER

VPB (VLSI

peripheral bus)

SCL

SDA

2

EINT3:0

EXTERNAL

INTERRUPTS

I C SERIAL

INTERFACE

SCK0,1

MOSI0,1

MISO0,1

SSEL0,1

8 x CAP0

8 x MAT

CAPTURE/

COMPARE

TIMER 0 & 1

SPI SERIAL

INTERFACES 0 & 1

TxD0,1

RxD0,1

Ain3:0

Ain7:4

A/D

CONVERTER

UART 0 & 1

DSR1,CTS1,

DCD1, RI1

P0.30:0

P1.31:16, 1:0

P2.31:0

GENERAL

PURPOSE I/O

P3.31:0

PWM6:1

PWM0

WATCHDOG

TIMER

REAL TIME

CLOCK

SYSTEM

CONTROL

002aaa732

*Shared with GPIO

(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.

Fig 1. Block diagram.

9397 750 13149

Product data

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3 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

5. Pinning information

5.1 Pinning

handbook, full pagewidth

P2.22/D22

1

2

3

4

5

6

7

8

9

108 P2.3/D3

V

3

107 V

SS

106 P2.2/D2

V

SS

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

P0.23

105 P2.1/D1

104

103

V

3

SS

P1.19/TRACEPKT3

P0.24

102 P1.20/TRACESYNC

101 P0.17/CAP1.2/SCK1/MAT1.2

100 P0.16/EINT0/MAT0.2/CAP0.2

99 P0.15/RI1/EINT2

98 P2.0/D0

V

SS

P2.23/D23 10

P2.24/D24 11

P2.25/D25 12

97 P3.30/BLS1

P2.26/D26/BOOT0 13

96 P3.31/BLS0

V

14

95 P1.21/PIPESTAT0

3A

P1.18/TRACEPKT2 15

P2.27/D27/BOOT1 16

P2.28/D28 17

94

93

V

3

SS

92 P0.14/DCD1/EINT1

91 P1.0/CS0

P2.29/D29 18

LPC2212/LPC2214

P2.30/D30/AIN4 19

P2.31/D31/AIN5 20

P0.25 21

90 P1.1/OE

89 P3.0/A0

88 P3.1/A1

NC 22

87 P3.2/A2

P0.27/AIN0/CAP0.1/MAT0.1 23

P1.17/TRACEPKT1 24

P0.28/AIN1/CAP0.2/MAT0.2 25

86 P1.22/PIPESTAT1

85 P0.13/DTR1/MAT1.1

84 P0.12/DSR1/MAT1.0

83 P0.11/CTS1/CAP1.1

82 P1.23/PIPESTAT2

81 P3.3/A3

V

26

SS

P3.29/BLS2/AIN6 27

P3.28/BLS3/AIN7 28

P3.27/WE 29

80 P3.4/A4

P3.26/CS1 30

79

78 P0.10/RTS1/CAP1.0

77

V

SS

V

31

3

P0.29/AIN2/CAP0.3/MAT0.3 32

P0.30/AIN3/EINT3/CAP0.0 33

P1.16/TRACEPKT0 34

P3.25/CS2 35

V

3

76 P0.9/RxD1/PWM6/EINT3

75 P0.8/TxD1/PWM4

74 P3.5/A5

P3.24/CS3 36

73 P3.6/A6

002aaa733

Fig 2. LQFP144 pinning.

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Product data

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4 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

5.2 Pin description

Table 3:

Pin description

Symbol

Type

Description

P0.0 to P0.31

I/O

Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction

controls for each bit. The operation of port 0 pins depends upon the pin

function selected via the Pin Connect Block.

Pins 26 and 31 of port 0 are not available.

TxD0 — Transmitter output for UART0.

P0.0

P0.1

42

49

O

I

PWM1 — Pulse Width Modulator output 1.

RxD0 — Receiver input for UART0.

O

I

PWM3 — Pulse Width Modulator output 3.

EINT0 — External interrupt 0 input

P0.2

P0.3

50

58

I/O

I

SCL — I²C clock input/output. Open drain output (for I²C compliance).

CAP0.0 — Capture input for Timer0, channel 0.

SDA — I²C data input/output. Open drain output (for I²C compliance).

MAT0.0 — Match output for Timer0, channel 0.

EINT1 — External interrupt 1 input.

I/O

O

I

P0.4

P0.5

P0.6

P0.7

59

61

68

69

I/O

SCK0 — Serial clock for SPI0. SPI™ clock output from master or input to

slave.

I

CAP0.1 — Capture input for Timer0, channel 1.

I/O

MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data

output from SPI slave.

O

MAT0.1 — Match output for Timer0, channel 1.

I/O

MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.

I

CAP0.2 — Capture input for Timer0, channel 2.

SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

PWM2 — Pulse Width Modulator output 2.

EINT2 — External interrupt 2 input.

I

O

I

P0.8

P0.9

75

76

O

I

TxD1 — Transmitter output for UART1.

PWM4 — Pulse Width Modulator output 4.

RxD1 — Receiver input for UART1.

O

I

PWM6 — Pulse Width Modulator output 6.

EINT3 — External interrupt 3 input.

P0.10

P0.11

P0.12

78

83

84

O

I

RTS1 — Request to Send output for UART1.

CAP1.0 — Capture input for Timer1, channel 0.

CTS1 — Clear to Send input for UART1.

CAP1.1 — Capture input for Timer1, channel 1.

DSR1 — Data Set Ready input for UART1.

I

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LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

Table 3:

Symbol

Pin description…continued

Type

Description

O

I

MAT1.0 — Match output for Timer1, channel 0.

DTR1 — Data Terminal Ready output for UART1.

MAT1.1 — Match output for Timer1, channel 1.

DCD1 — Data Carrier Detect input for UART1.

EINT1 — External interrupt 1 input.

P0.13

P0.14

85

92

I

Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to

take over control of the part after reset.

P0.15

P0.16

99

I

RI1 — Ring Indicator input for UART1.

I

EINT2 — External interrupt 2 input.

100

I

EINT0 — External interrupt 0 input.

O

I

MAT0.2 — Match output for Timer0, channel 2.

CAP0.2 — Capture input for Timer0, channel 2.

CAP1.2 — Capture input for Timer1, channel 2.

SCK1 — Serial Clock for SPI1. SPI clock output from master or input to slave.

MAT1.2 — Match output for Timer1, channel 2.

CAP1.3 — Capture input for Timer1, channel 3.

P0.17

P0.18

101

121

I

I/O

O

I

I/O

MISO1 — Master In Slave Out for SPI1. Data input to SPI master or data

output from SPI slave.

O

MAT1.3 — Match output for Timer1, channel 3.

MAT1.2 — Match output for Timer1, channel 2.

P0.19

P0.20

122

123

O

I/O

MOSI1 — Master Out Slave In for SPI1. Data output from SPI master or data

input to SPI slave.

I

CAP1.2 — Capture input for Timer1, channel 2.

MAT1.3 — Match output for Timer1, channel 3.

SSEL1 — Slave Select for SPI1. Selects the SPI interface as a slave.

EINT3 — External interrupt 3 input.

O

I

P0.21

P0.22

4

5

O

I

PWM5 — Pulse Width Modulator output 5.

CAP1.3 — Capture input for TIMER1, channel 3.

CAP0.0 — Capture input for Timer0, channel 0.

MAT0.0 — Match output for Timer0, channel 0.

General purpose bidirectional digital port only.

I

O

I/O

I

P0.23

P0.24

P0.25

P0.27

6

8

21

23

AIN0 — A/D converter, input 0. This analog input is always connected to its

pin.

I

CAP0.1 — Capture input for Timer0, channel 1.

MAT0.1 — Match output for Timer0, channel 1.

O

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6 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

Table 3:

Symbol

P0.28

Pin description…continued

Type

Description

25

I

AIN1 — A/D converter, input 1. This analog input is always connected to its

pin.

I

CAP0.2 — Capture input for Timer0, channel 2.

MAT0.2 — Match output for Timer0, channel 2.

O

I

P0.29

P0.30

32

33

AIN2 — A/D converter, input 2. This analog input is always connected to its

pin.

I

CAP0.3 — Capture input for Timer0, Channel 3.

MAT0.3 — Match output for Timer0, channel 3.

O

I

AIN3 — A/D converter, input 3. This analog input is always connected to its

pin.

I

EINT3 — External interrupt 3 input.

I

CAP0.0 — Capture input for Timer0, channel 0.

P1.0 to P1.31

P1.0

I/O

Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction

controls for each bit. The operation of port 1 pins depends upon the pin

function selected via the Pin Connect Block.

Pins 0 through 15 of port 1 are not available.

91

O

CS0 — Low-active Chip Select 0 signal.

(Bank 0 addresses range 8000 0000 - 80FF FFFF)

P1.1

90

34

24

15

7

O

OE — Low-active Output Enable signal.

P1.16

P1.17

P1.18

P1.19

P1.20

TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

102

TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1.25:16 to

operate as Trace port after reset.

P1.21

P1.22

P1.23

P1.24

P1.25

P1.26

95

86

82

70

60

52

O

I

PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bi-directional pin with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1.31:26 to

operate as Debug port after reset.

P1.27

P1.28

P1.29

P1.30

P1.31

144

140

126

113

43

O

I

TDO — Test Data out for JTAG interface.

TDI — Test Data in for JTAG interface.

TCK — Test Clock for JTAG interface.

TMS — Test Mode Select for JTAG interface.

TRST — Test Reset for JTAG interface.

I

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LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

Table 3:

Pin description…continued

Symbol

Type

Description

P2.0 to P2.31

I/O

Port 2 — Port 2 is a 32-bit bi-directional I/O port with individual direction

controls for each bit. The operation of port 2 pins depends upon the pin

function selected via the Pin Connect Block.

P2.0

98

I/O

I

D0 — External memory data line 0.

D1 — External memory data line 1.

D2 — External memory data line 2.

D3 — External memory data line 3.

D4 — External memory data line 4.

D5 — External memory data line 5.

D6 — External memory data line 6.

D7 — External memory data line 7.

D8 — External memory data line 8.

D9 — External memory data line 9.

D10 — External memory data line 10.

D11 — External memory data line 11.

D12 — External memory data line 12.

D13 — External memory data line 13.

D14 — External memory data line 14.

D15 — External memory data line 15.

D16 — External memory data line 16.

D17 — External memory data line 17.

D18 — External memory data line 18.

D19 — External memory data line 19.

D20 — External memory data line 20.

D21 — External memory data line 21.

D22 — External memory data line 22.

D23 — External memory data line 23.

D24 — External memory data line 24.

D25 — External memory data line 25.

D26 — External memory data line 26.

P2.1

105

106

108

109

114

115

116

117

118

120

124

125

127

129

130

131

132

133

134

136

137

1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

P2.16

P2.17

P2.18

P2.19

P2.20

P2.21

P2.22

P2.23

P2.24

P2.25

P2.26

10

11

12

13

BOOT0 — While RESET is low, together with BOOT1 controls booting and

internal operation. Internal pull-up ensures high state if pin is left

unconnected.

P2.27

16

I/O

I

D27 — External memory data line 27.

BOOT1 — While RESET is low, together with BOOT0 controls booting and

internal operation. Internal pull-up ensures high state if pin is left

unconnected.

BOOT1:0=00 selects 8-bit memory on CS0 for boot.

BOOT1:0=01 selects 16-bit memory on CS0 for boot.

BOOT1:0=10 selects 32-bit memory on CS0 for boot.

BOOT1:0=11 selects Internal Flash memory.

D28 — External memory data line 28.

P2.28

17

I/O

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LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

Table 3:

Symbol

P2.29

Pin description…continued

18

Type

I/O

I

Description

D29 — External memory data line 29.

D30 — External memory data line 30.

P2.30

19

AIN4 — A/D converter, input 4. This analog input is always connected to its

pin.

P2.31

20

I/O

I

D31 — External memory data line 31.

AIN5 — A/D converter, input 5. This analog input is always connected to its

pin.

P3.0 to P3.31

I/O

Port 3 — Port 3 is a 32-bit bi-directional I/O port with individual direction

controls for each bit. The operation of port 3 pins depends upon the pin

function selected via the Pin Connect Block.

P3.0

89

88

87

81

80

74

73

72

71

66

65

64

63

62

56

55

53

48

47

46

45

44

41

40

O

A0 — External memory address line 0.

A1 — External memory address line 1.

A2 — External memory address line 2.

A3 — External memory address line 3.

A4 — External memory address line 4.

A5 — External memory address line 5.

A6 — External memory address line 6.

A7 — External memory address line 7.

A8 — External memory address line 8.

A9 — External memory address line 9.

A10 — External memory address line 10.

A11 — External memory address line 11.

A12 — External memory address line 12.

A13 — External memory address line 13.

A14 — External memory address line 14.

A15 — External memory address line 15.

A16 — External memory address line 16.

A17 — External memory address line 17.

A18 — External memory address line 18.

A19 — External memory address line 19.

A20 — External memory address line 20.

A21 — External memory address line 21.

A22 — External memory address line 22.

A23 — External memory address line 23.

XCLK — Clock output.

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

P3.10

P3.11

P3.12

P3.13

P3.14

P3.15

P3.16

P3.17

P3.18

P3.19

P3.20

P3.21

P3.22

P3.23

P3.24

P3.25

P3.26

P3.27

36

35

30

29

CS3 — Low-active Chip Select 3 signal.

(Bank 3 addresses range 8300 0000 - 83FF FFFF)

CS2 — Low-active Chip Select 2signal.

(Bank 2 addresses range 8200 0000 - 82FF FFFF)

CS1 — Low-active Chip Select 1 signal.

(Bank 1 addresses range 8100 0000 - 81FF FFFF)

WE — Low-active Write enable signal.

O

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LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

Table 3:

Symbol

P3.28

Pin description…continued

Type

Description

28

O

I

BLS3 — Low-active Byte Lane Select signal (Bank 3).

AIN7 — A/D converter, input 7. This analog input is always connected to its

pin.

P3.29

27

O

I

BLS2 — Low-active Byte Lane Select signal (Bank 2).

AIN6 — A/D converter, input 6. This analog input is always connected to its

pin.

P3.30

P3.31

NC

97

O

BLS1 — Low-active Byte Lane Select signal (Bank 1).

BLS0 — Low-active Byte Lane Select signal (Bank 0).

Pin not connected.

96

22

RESET

135

I

External Reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

V_SS

142

141

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator ampliﬁer.

O

I

3, 9, 26, 38,

54, 67, 79,

93, 103, 107,

111, 128

Ground: 0 V reference.

V_SSA

139

I

Analog Ground: 0 V reference. This should nominally be the same voltage

as V_SS, but should be isolated to minimize noise and error.

V_{SSA_PLL}

V₁₈

138

PLL Analog Ground: 0 V reference. This should nominally be the same

voltage as V_SS, but should be isolated to minimize noise and error.

37, 110

143

1.8 V Core Power Supply: This is the power supply voltage for internal

circuitry.

V_18A

Analog 1.8 V Core Power Supply: This is the power supply voltage for

internal circuitry. This should be nominally the same voltage as V₁₈but should

be isolated to minimize noise and error.

V₃

2, 31, 39, 51,

57, 77, 94,

104, 112, 119

I

3.3 V Pad Power Supply: This is the power supply voltage for the I/O ports.

V_3A

14

Analog 3.3 V Pad Power Supply: This should be nominally the same voltage

as V₃but should be isolated to minimize noise and error.

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10 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

6. Functional description

Details of the LPC2212/LPC2214 systems and peripheral functions are described in

the following sections.

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM^®architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and

related decode mechanism are much simpler than those of microprogrammed

Complex Instruction Set Computers. This simplicity results in a high instruction

throughput and impressive real-time interrupt response from a small and

cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory

systems can operate continuously. Typically, while one instruction is being executed,

its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb

code operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-Chip Flash program memory

The LPC2212/LPC2214 incorporate a 128 kB and 256 kB Flash memory system

respectively. This memory may be used for both code and data storage.

Programming of the Flash memory may be accomplished in several ways. It may be

programmed In System via the serial port. The application program may also erase

and/or program the Flash while the application is running, allowing a great degree of

ﬂexibility for data storage ﬁeld ﬁrmware upgrades, etc. When on-chip bootloader is

used, 120/248 kB of Flash memory is available for user code.

The LPC2212/LPC2214 Flash memory provides a minimum of 100,000 erase/write

cycles and 20 years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the

LPC2212/LPC2214 on-chip Flash memory. When the CRP is enabled, the JTAG

debug port, external memory boot and ISP commands accessing either the on-chip

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RAM or Flash memory are disabled. However, the ISP Flash Erase command can be

executed at any time (no matter whether the CRP is on or off). Removal of CRP is

achieved by erasure of full on-chip user Flash. With the CRP off, full access to the

chip via the JTAG and/or ISP is restored.

6.3 On-Chip static RAM

On-Chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bits, 16-bits, and 32-bits. The LPC2212/LPC2214 provide 16 kB of

static RAM.

6.4 Memory map

The LPC2212/LPC2214 memory maps incorporate several distinct regions, as shown

in the following ﬁgures.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in

either Flash memory (the default) or on-chip static RAM. This is described in Section

6.20 “System control”.

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16/32-bit ARM microcontrollers with external memory interface

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4.0 GB

0xFFFF FFFF

AHB PERIPHERALS

VPB PERIPHERALS

0xF000 0000

0xEFFF FFFF

3.75 GB

3.5 GB

0xE000 0000

0xDFFF FFFF

0xC000 0000

3.0 GB

RESERVED ADDRESS SPACE

0x8000 0000

0x7FFF FFFF

2.0 GB

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY

0x7FFF E000

0x7FFF DFFF

RESERVED ADDRESS SPACE

16 KBYTE ON-CHIP STATIC RAM

0x4004 0000

0x4000 3FFF

0x4000 0000

0x3FFF FFFF

1.0 GB

RESERVED ADDRESS SPACE

0x0004 0000

0x0003 FFFF

256 KBYTE ON-CHIP FLASH MEMORY (LPC2214)

128 KBYTE ON-CHIP FLASH MEMORY (LPC2212)

0x0002 0000

0x0001 FFFF

0x0000 0000

0.0 GB

002aaa751

Fig 3. LPC2212/LPC2214 memory map.

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as deﬁned by

programmable settings. The programmable assignment scheme means that priorities

of interrupts from the various peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is

assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the

ARM processor. The fastest possible FIQ latency is achieved when only one request

is classiﬁed as FIQ, because then the FIQ service routine can simply start dealing

with that device. But if more than one request is assigned to the FIQ class, the FIQ

service routine can read a word from the VIC that identiﬁes which FIQ source(s) is

(are) requesting an interrupt.

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Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be

assigned to this category. Any of the interrupt requests can be assigned to any of the

16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the

lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to

produce the IRQ signal to the ARM processor. The IRQ service routine can start by

reading a register from the VIC and jumping there. If any of the vectored IRQs are

requesting, the VIC provides the address of the highest-priority requesting IRQs

service routine, otherwise it provides the address of a default routine that is shared by

all the non-vectored IRQs. The default routine can read another VIC register to see

what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device

has one interrupt line connected to the Vectored Interrupt Controller, but may have

several internal interrupt ﬂags. Individual interrupt ﬂags may also represent more than

one interrupt source.

Table 4:

Block

Interrupt sources

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

0

1

2

3

4

5

6

-

Reserved for software interrupts only

Embedded ICE, DbgCommRx

Embedded ICE, DbgCommTx

Match 0 - 3 (MR0, MR1, MR2, MR3)

Rx Line Status (RLS)

ARM Core

Timer0

Timer1

UART0

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Rx Line Status (RLS)

UART1

7

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

SI (state change)

PWM0

I²C

8

9

SPI0

SPI1

PLL

SPIF, MODF

10

11

12

13

SPIF, MODF

PLL Lock (PLOCK)

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

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Table 4:

Block

Interrupt sources…continued

Flag(s)

VIC channel #

System Control External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

14

15

16

17

18

External Interrupt 2 (EINT2)

External Interrupt 3 (EINT3)

A/D

A/D Converter

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than

one function. Conﬁguration registers control the multiplexers to allow connection

between the pin and the on chip peripherals. Peripherals should be connected to the

appropriate pins prior to being activated, and prior to any related interrupt(s) being

enabled. Activity of any enabled peripheral function that is not mapped to a related

pin should be considered undeﬁned.

The Pin Control Module contains three registers as shown in Table 5.

Table 5:

Address

Name

Description

Access

0xE002C000

0xE002C004

0xE002C014

PINSEL0

PINSEL1

PINSEL2

Pin function select register 0

Pin function select register 1

Pin function select register 2

Read/Write

6.7 Pin function select register 0 (PINSEL0 - 0xE002C000)

The PINSEL0 register controls the functions of the pins as per the settings listed in

Table 6. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions, direction is controlled automatically.

Settings other than those shown in Table 6 are reserved, and should not be used

Table 6:

PINSEL0

1:0

Pin function select register 0 (PINSEL0 - 0xE002C000)

Pin name Value

Function

Value after Reset

P0.0

P0.1

P0.2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GPIO Port 0.0

TxD (UART0)

PWM1

0

Reserved

3:2

5:4

GPIO Port 0.1

RxD (UART0)

PWM3

0

EINT0

GPIO Port 0.2

SCL (I²C)

Capture 0.0 (Timer0)

Reserved

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Table 6:

Pin function select register 0 (PINSEL0 - 0xE002C000)…continued

PINSEL0

Pin name Value

Function

Value after Reset

7:6

P0.3

P0.4

P0.5

P0.6

P0.7

P0.8

P0.9

P0.10

P0.11

P0.12

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GPIO Port 0.3

SDA (I²C)

0

Match 0.0 (Timer0)

EINT1

9:8

GPIO Port 0.4

SCK (SPI0)

0

Capture 0.1 (Timer0)

Reserved

11:10

13:12

15:14

17:16

19:18

21:20

23:22

25:24

GPIO Port 0.5

MISO (SPI0)

Match 0.1 (Timer0)

Reserved

GPIO Port 0.6

MOSI (SPI0)

Capture 0.2 (Timer0)

Reserved

GPIO Port 0.7

SSEL (SPI0)

PWM2

EINT2

GPIO Port 0.8

TxD UART1

PWM4

Reserved

GPIO Port 0.9

RxD (UART1)

PWM6

EINT3

GPIO Port 0.10

RTS (UART1)

Capture 1.0 (Timer1)

Reserved

GPIO Port 0.11

CTS (UART1)

Capture 1.1 (Timer1)

Reserved

GPIO Port 0.12

DSR (UART1)

Match 1.0 (Timer1)

Reserved

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Table 6:

Pin function select register 0 (PINSEL0 - 0xE002C000)…continued

PINSEL0

Pin name Value

Function

Value after Reset

27:26

P0.13

P0.14

P0.15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GPIO Port 0.13

DTR (UART1)

Match 1.1 (Timer1)

Reserved

0

29:28

31:30

GPIO Port 0.14

DCD (UART1)

EINT1

0

Reserved

GPIO Port 0.15

RI (UART1)

EINT2

Reserved

6.8 Pin function select register 1 (PINSEL1 - 0xE002C004)

The PINSEL1 register controls the functions of the pins as per the settings listed in

Table 7. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions direction is controlled automatically.

Settings other than those shown in the table are reserved, and should not be used.

Table 7:

Pin function select register 1 (PINSEL1 - 0xE002C004)

PINSEL1

Pin Name

Value

Function

Value after

Reset

1:0

3:2

5:4

7:6

9:8

P0.16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GPIO Port 0.16

EINT0

0

Match 0.2 (Timer0)

Capture 0.2 (Timer0)

GPIO Port 0.17

Capture 1.2 (Timer1)

SCK (SPI1)

P0.17

P0.18

P0.19

P0.20

Match 1.2 (Timer1)

GPIO Port 0.18

Capture 1.3 (Timer1)

MISO (SPI1)

Match 1.3 (Timer1)

GPIO Port 0.19

Match 1.2 (Timer1)

MOSI (SPI1)

Capture 1.2 (Timer1)

GPIO Port 0.20

Match 1.3 (Timer1)

SSEL (SPI1)

EINT3

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16/32-bit ARM microcontrollers with external memory interface

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Table 7:

Pin function select register 1 (PINSEL1 - 0xE002C004)…continued

PINSEL1

Pin Name

Value

Function

Value after

Reset

11:10

P0.21

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GPIO Port 0.21

PWM5

0

1

Reserved

Capture 1.3 (Timer1)

GPIO Port 0.22

Reserved

13:12

15:14

17:16

19:18

21:20

23:22

25:24

27:26

29:28

P0.22

P0.23

P0.24

P0.25

P0.26

P0.27

P0.28

P0.29

P0.30

Capture 0.0 (Timer0)

Match 0.0 (Timer0)

GPIO Port 0.23

Reserved

GPIO Port 0.24

Reserved

GPIO Port 0.25

Reserved

GPIO Port 0.27

AIN0 (A/D input 0)

Capture 0.1 (Timer0)

Match 0.1 (Timer0)

GPIO Port 0.28

AIN1 (A/D input 1)

Capture 0.2 (Timer0)

Match 0.2 (Timer0)

GPIO Port 0.29

AIN2 (A/D input 2)

Capture 0.3 (Timer0)

Match 0.3 (Timer0)

GPIO Port 0.30

AIN3 (A/D input 0)

EINT3

Capture 0.0 (Timer0)

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Table 7:

Pin function select register 1 (PINSEL1 - 0xE002C004)…continued

PINSEL1

Pin Name

Value

Function

Value after

Reset

31:30

P0.31

0

1

0

1

0

1

Reserved

0

6.9 Pin function select register 2 (PINSEL2 - 0xE002C014)

The PINSEL2 register controls the functions of the pins as per the settings listed in

Table 8. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions direction is controlled automatically.

Settings other than those shown in the table are reserved, and should not be used.

Table 8:

Pin function select register 2 (PINSEL2 - 0xE002C014)

PINSEL2 bits

Description

Reset value

1:0

2

Reserved.

-

When 0, pins P1.36:26 are used as GPIO pins. When 1, P1.31:26 are used as a P1.26/RTCK

Debug port.

3

When 0, pins P1.25:16 are used as GPIO pins. When 1, P1.25:16 are used as a P1.20/

Trace port.

TRACESYNC

5:4

Controls the use of the data bus and strobe pins:

BOOT1:0

Pins P2.7:0

Pin P1.0

11 = P2.7:0

0x or 10 = D7:0

0x or 10 = CS0

0x or 10 = OE

0x or 10 = BLS0

01 or 10 = D15:8

01 or 10 = BLS1

10 = D27:16

11 = P1.0

Pin P1.1

11 = P1.1

Pin P3.31

11 = P3.31

Pins P2.15:8

Pin P3.30

00 or 11 = P2.15:8

00 or 11 = P3.30

Pins P2.27:16

Pins P2.29:28

Pins P2.31:30

Pins P3.29:28

0x or 11 = P2.27:16

0x or 11 = P2.29:28 or reserved

0x or 11 = P2.31:30 or AIN5:4

0x or 11 = P3.29:28 or AIN6:7

10 = D29:28

10 = D31:30

10 = BLS2:3

6

7

If bits 5:4 are not 10, controls the use of pin P3.29: 0 enables P3.29, 1 enables

AIN6.

1

If bits 5:4 are not 10, controls the use of pin P3.28: 0 enables P3.28, 1 enables

AIN7.

8

Controls the use of pin P3.27: 0 enables P3.27, 1 enables WE.

0

-

10:9

11

12

13

Reserved.

Controls the use of pin P3.26: 0 enables P3.26, 1 enables CS1.

Reserved.

0

-

If bits 25:23 are not 111, controls the use of pin P3.23/A23/XCLK: 0 enables

P3.23, 1 enables XCLK.

0

15:14

17:16

Controls the use of pin P3.25: 00 enables P3.25, 01 enables CS2, 10 and 11

are reserved values.

00

Controls the use of pin P3.24: 00 enables P3.24, 01 enables CS3, 10 and 11

are reserved values.

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Table 8:

PINSEL2 bits

19:18

Pin function select register 2 (PINSEL2 - 0xE002C014)…continued

Description

Reset value

Reserved.

-

20

If bits 5:4 are not 10, controls the use of pin P2.29:28: 0 enables P2.29:28, 1 is

reserved

0

1

21

22

23

If bits 5:4 are not 10, controls the use of pin P2.30: 0 enables P2.30, 1 enables

AIN4.

If bits 5:4 are not 10, controls the use of pin P2.31: 0 enables P2.31, 1 enables

AIN5.

Controls whether P3.0/A0 is a port pin (0) or an address line (1).

1 if BOOT1:0=00

at RESET=0,

0 otherwise

24

Controls whether P3.1/A1 is a port pin (0) or an address line (1).

BOOT1 during

Reset

27:25

Controls the number of pins among P3.23/A23/XCLK and P3.22:2/A2.22:2 that 000 if

are address lines:

BOOT1:0=11 at

Reset, 111

otherwise

000 = None

100 = A11:2 are address lines.

101 = A15:2 are address lines.

001 = A3:2 are address

lines.

010 = A5:2 are address

lines.

110 = A19:2 are address lines.

111 = A23:2 are address lines.

011 = A7:2 are address

lines.

31:28

Reserved.

6.10 External memory controller

The external Static Memory Controller is a module which provides an interface

between the system bus and external (off-chip) memory devices. It provides support

for up to four independently conﬁgurable memory banks (16 MBytes each with byte

lane enable control) simultaneously. Each memory banks is capable of supporting

SRAM, ROM, Flash EPROM, Burst ROM memory, or some external I/O devices.

Each memory bank may be 8, 16, or 32 bits wide.

6.11 General purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by

the GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs.

Separate registers allow setting or clearing any number of outputs simultaneously.

The value of the output register may be read back, as well as the current state of the

port pins.

6.11.1 Features

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

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6.12 10-bit A/D converter

The LPC2212/LPC2214 each contain single 10-bit successive approximation analog

to digital converter with eight multiplexed channels.

6.12.1 Features

• Measurement range of 0 V to 3 V.

• Capable of performing more than 400,000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

6.13 UARTs

The LPC2212/LPC2214 each contain two UARTs. One UART provides a full modem

control handshake interface, the other provides only transmit and receive data lines.

6.13.1 Features

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

• Built-in baud rate generator.

• Standard modem interface signals included on UART1.

6.14 I²C serial I/O controller

I²C is a bi-directional bus for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address

and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter

with the capability to both receive and send information (such as memory).

Transmitters and/or receivers can operate in either master or slave mode, depending

on whether the chip has to initiate a data transfer or is only addressed. I²C is a

multi-master bus, it can be controlled by more than one bus master connected to it.

I²C implemented in LPC2212/LPC2214 supports bit rate up to 400 kbit/s (Fast I²C).

6.14.1 Features

• Standard I²C compliant bus interface.

• Easy to conﬁgure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate

via one serial bus.

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• Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer.

• The I²C bus may be used for test and diagnostic purposes.

6.15 SPI serial I/O controller

The LPC2212/LPC2214 each contain two SPIs. The SPI is a full duplex serial

interface, designed to be able to handle multiple masters and slaves connected to a

given bus. Only a single master and a single slave can communicate on the interface

during a given data transfer. During a data transfer the master always sends a byte of

data to the slave, and the slave always sends a byte of data to the master.

6.15.1 Features

• Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

• Synchronous, Serial, Full Duplex, Communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.16 General purpose timers

The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally

generate interrupts or perform other actions at speciﬁed timer values, based on four

match registers. It also includes four capture inputs to trap the timer value when an

input signal transitions, optionally generating an interrupt. Multiple pins can be

selected to perform a single capture or match function, providing an application with

‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

6.16.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

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6.17 Watchdog timer

The purpose of the Watchdog is to reset the microcontroller within a reasonable

amount of time if it enters an erroneous state. When enabled, the Watchdog will

generate a system reset if the user program fails to ‘feed’ (or reload) the Watchdog

within a predetermined amount of time.

6.17.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to

be disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate Watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (t_pclk× 256 × 4) to (t_pclk× 2³²× 4) in multiples of

t

_pclk× 4.

6.18 Real time clock

The Real Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use

little power, making it suitable for battery powered systems where the CPU is not

running continuously (Idle mode).

6.18.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra Low Power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

• Programmable Reference Clock Divider allows adjustment of the RTC to match

various crystal frequencies.

6.19 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features,

although only the PWM function is pinned out on the LPC2212/LPC2214. The Timer

is designed to count cycles of the peripheral clock (PCLK) and optionally generate

interrupts or perform other actions when speciﬁed timer values occur, based on

seven match registers. The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to

be used for more applications. For instance, multi-phase motor control typically

requires three non-overlapping PWM outputs with individual control of all three pulse

widths and positions.

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Two match registers can be used to provide a single edge controlled PWM output.

One match register (MR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single

edge controlled PWM outputs require only one match register each, since the

repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM

outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0

match occurs.

Three match registers can be used to provide a PWM output with both edges

controlled. Again, the MR0 match register controls the PWM cycle rate. The other

match registers control the two PWM edge positions. Additional double edge

controlled PWM outputs require only two match registers each, since the repetition

rate is the same for all PWM outputs.

With double edge controlled PWM outputs, speciﬁc match registers control the rising

and falling edge of the output. This allows both positive going PWM pulses (when the

rising edge occurs prior to the falling edge), and negative going PWM pulses (when

the falling edge occurs prior to the rising edge).

6.19.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs.

Single edge controlled PWM outputs all go HIGH at the beginning of each cycle

unless the output is a constant LOW. Double edge controlled PWM outputs can

have either edge occur at any position within a cycle. This allows for both positive

going and negative going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs

will occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive

going or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation

of erroneous pulses. Software must ‘release’ new match values before they can

become effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

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6.20 System control

6.20.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator

output frequency is called f_oscand the ARM processor clock frequency is referred to

as cclk for purposes of rate equations, etc. f_oscand cclk are the same value unless

the PLL is running and connected. Refer to Section 6.20.2 “PLL” for additional

information.

6.20.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The

input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in

practice, the multiplier value cannot be higher than 6 on this family of microcontrollers

due to the upper frequency limit of the CPU). The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO

within its frequency range while the PLL is providing the desired output frequency.

The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock.

Since the minimum output divider value is 2, it is insured that the PLL output has a

50 % duty cycle.The PLL is turned off and bypassed following a chip Reset and may

be enabled by software. The program must conﬁgure and activate the PLL, wait for

the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is

100 µs.

6.20.3 Reset and wake-up timer

Reset has two sources on the LPC2212/LPC2214: the RESET pin and Watchdog

Reset. The RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter.

Assertion of chip Reset by any source starts the Wake-up Timer (see Wake-up Timer

description below), causing the internal chip reset to remain asserted until the

external Reset is de-asserted, the oscillator is running, a ﬁxed number of clocks have

passed, and the on-chip Flash controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0,

which is the Reset vector. At that point, all of the processor and peripheral registers

have been initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute

instructions. This is important at power on, all types of Reset, and whenever any of

the aforementioned functions are turned off for any reason. Since the oscillator and

other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether

it is safe to begin code execution. When power is applied to the chip, or some event

caused the chip to exit Power-down mode, some time is required for the oscillator to

produce a signal of sufﬁcient amplitude to drive the clock logic. The amount of time

depends on many factors, including the rate of V_DDramp (in the case of power on),

the type of crystal and its electrical characteristics (if a quartz crystal is used), as well

as any other external circuitry (e.g. capacitors), and the characteristics of the

oscillator itself under the existing ambient conditions.

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6.20.4 External interrupt inputs

The LPC2212/LPC2214 include up to nine edge or level sensitive External Interrupt

Inputs as selectable pin functions. When the pins are combined, external events can

be processed as four independent interrupt signals. The External Interrupt Inputs can

optionally be used to wake up the processor from Power-down mode.

6.20.5 Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x00000000. Vectors may be mapped to the bottom of the

on-chip Flash memory, or to the on-chip static RAM. This allows code running in

different memory spaces to have control of the interrupts.

6.20.6 Power Control

The LPC2212/LPC2214 support two reduced power modes: Idle mode and

Power-down mode. In Idle mode, execution of instructions is suspended until either a

Reset or interrupt occurs. Peripheral functions continue operation during Idle mode

and may generate interrupts to cause the processor to resume execution. Idle mode

eliminates power used by the processor itself, memory systems and related

controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal

clocks. The processor state and registers, peripheral registers, and internal SRAM

values are preserved throughout Power-down mode and the logic levels of chip

output pins remain static. The Power-down mode can be terminated and normal

operation resumed by either a Reset or certain speciﬁc interrupts that are able to

function without clocks. Since all dynamic operation of the chip is suspended,

Power-down mode reduces chip power consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.20.7 VPB bus

The VPB divider determines the relationship between the processor clock (CCLK)

and the clock used by peripheral devices (PCLK). The VPB divider serves two

purposes. The ﬁrst is to provide peripherals with the desired PCLK via VPB bus so

that they can operate at the speed chosen for the ARM processor. In order to achieve

this, the VPB bus may be slowed down to ¹⁄₂to ¹⁄₄of the processor clock rate.

Because the VPB bus must work properly at power-up (and its timing cannot be

altered if it does not work since the VPB divider control registers reside on the VPB

bus), the default condition at reset is for the VPB bus to run at ¹⁄₄of the processor

clock rate. The second purpose of the VPB divider is to allow power savings when an

application does not require any peripherals to run at the full processor rate. Because

the VPB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.21 Emulation and debugging

The LPC2212/LPC2214 support emulation and debugging via a JTAG serial port. A

trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on Port 1. This means that all communication, timer and

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interface peripherals residing on Port 0 are available during the development and

debugging phase as they are when the application is run in the embedded system

itself.

6.21.1 Embedded ICE

Standard ARM EmbeddedICE^®logic provides on-chip debug support. The debugging

of the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the

Remote Debug Protocol commands to the JTAG data needed to access the ARM

core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with

the host debugger or another separate host without stopping the program ﬂow or

even entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving

data without affecting the normal program ﬂow. The debug communication channel

data and control registers are mapped in to addresses in the EmbeddedICE logic.

6.21.2 Embedded trace

Since the LPC2212/LPC2214 have signiﬁcant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the

external pins. The Embedded Trace Macrocell™ provides real-time trace capability

for deeply embedded processor cores. It outputs information about processor

execution to the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system

bus. It compresses the trace information and exports it through a narrow trace port.

An external trace port analyzer must capture the trace information under software

debugger control. Instruction trace (or PC trace) shows the ﬂow of execution of the

processor and provides a list of all the instructions that were executed. Instruction

trace is signiﬁcantly compressed by only broadcasting branch addresses as well as a

set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace

information generation can be controlled by selecting the trigger resource. Trigger

resources include address comparators, counters and sequencers. Since trace

information is compressed the software debugger requires a static image of the code

being executed. Self-modifying code can not be traced because of this restriction.

6.21.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which

enables real time debug. It is a lightweight debug monitor that runs in the background

while users debug their foreground application. It communicates with the host using

the DCC (Debug Communications Channel), which is present in the EmbeddedICE

logic. The LPC2212/LPC2214 contain a speciﬁc conﬁguration of RealMonitor

software programmed into the on-chip Flash memory.

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7. Limiting values

Table 9:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

+2.5

+3.6

4.6

Unit

V

V₁₈

V₃

Supply voltage, internal rail

−0.5

Supply voltage, external rail

V

V_3A

AV_IN

Analog 3.3 V pad supply voltage

V

Analog input voltage on A/D related

pins

5.1

V

V_i

DC input voltage, 5 V tolerant I/O

pins^[3][4]

−0.5

6.0

V

V_i

DC input voltage, other I/O pins^[2][3]

DC supply current per supply pin^[5]

DC ground current per ground pin^[5]

Storage temperature^[6]

−0.5

-

V₃+ 0.5 V

I

100

150

-

mA

I

-

mA

°C

W

T_stg

P

−65

1.5

Power dissipation (based on

package heat transfer, not device

power consumption)

[1] The following applies to the Limiting values:

a) Stresses above those listed under Limiting values may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any conditions other

than those described in Section 8 “Static characteristics” and Section 9 “Dynamic characteristics”

of this speciﬁcation is not implied.

b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from

the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional

precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages

are with respect to V_SSunless otherwise noted.

[2] Not to exceed 4.6 V.

[3] Including voltage on outputs in 3-state mode.

[4] Only valid when the V₃supply voltage is present.

[5] The peak current is limited to 25 times the corresponding maximum current.

[6] Dependent on package type.

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8. Static characteristics

Table 10: Static characteristics

T_amb= −40 °C to +85 °C for commercial, unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

1.65

3.0

Typ^[1]

1.8

Max

1.95

3.6

Unit

V

V₁₈

V₃

Supply voltage

External rail supply voltage

3.3

V

V_3A

Analog 3.3 V pad supply

voltage

2.5

3.3

3.6

V

Standard Port pins, RESET, RTCK

I_IL

Low level input current, no

pull-up

V_i= 0

-

3

-

µA

mA

I_IH

High level input current, no V_i= V₃

pull down

-

I_OZ

3-state output leakage, no

pull-up/down

V_o= 0, V_o= V₃

-

I_latchup

I/O latch-up current

−(0.5 V₃) < V < (1.5 V₃)

T_j< 125 °C

100

V_i

Input voltage^[3][4][5]

0

-

5.5

V₃

-

V

V_o

Output voltage, output active

High level input voltage

Low level input voltage

Hysteresis voltage

High level output voltage^[6]

Low level output voltage^[6]

High level output current^[6]

Low level output current^[6]

0

-

V

V_IH

V_IL

V_hys

V_OH

V_OL

I_OH

I_OL

I_OH

2.0

-

V

-

0.8

-

V

-

0.4

V

I_OH= −4 mA

I_OL= −4 mA

V_OH= V₃− 0.4 V

V_OL= 0.4 V

V_OH= 0

V₃− 0.4

-

V

-

0.4

-

V

−4

4

-

mA

-

High level short circuit

current^[7]

−45

I_OL

Low level short circuit

current^[7]

V_OL= V₃

-

50

mA

I_PD

I_PU

Pull-down current

V_i= 5 V^[8]

V_i= 0

V₃< V_i< 5 V^[8]

10

−15

0

50

−50

0

150

−85

0

µA

mA

Pull-up current (applies to

P1.16 - P1.25)

I₁₈

Active Mode

V₁₈= 1.8 V, cclk = 60 MHz,

-

60

-

T_amb= 25 °C, code

while(1){}

executed from FLASH, no active

peripherals

Power-down Mode

V₁₈= 1.8 V, T_amb= +25 °C,

V₁₈= 1.8 V, T_amb= +85 °C

-

10

-

µA

110

500

I²C pins

V_IH

High level input voltage

Low level input voltage

Hysteresis voltage

V_TOLis from 4.5 V to 5.5 V

0.7 V_TOL

-

V

V_IL

-

0.3 V_TOL

-

V_hys

0.5 V_TOL

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Table 10: Static characteristics…continued

T_amb= −40 °C to +85 °C for commercial, unless otherwise speciﬁed.

Symbol Parameter

Conditions

I_OL= 3 mA

V_i= V₃

Min

Typ^[1]

Max

0.4

4

Unit

V

V_OL

I_lkg

Low level output voltage^[6]

-

Input leakage to V_SS

2

µA

V_i= 5 V

10

22

Oscillator pins

X1 input Voltages

0

-

V₁₈

X2 output Voltages

On-chip Flash program memory

endurance (write and erase)

data retention

100,000

20

-

cycles

years

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), nominal supply voltages.

[2] Pin capacitance is characterized but not tested.

[3] Including voltage on outputs in 3-state mode.

[4] V₃supply voltages must be present.

[5] 3-state outputs go into 3-state mode when V₃is grounded.

[6] Accounts for 100 mV voltage drop in all supply lines.

[7] Only allowed for a short time period.

[8] Minimum condition for V_i= 4.5 V, maximum condition for V_i= 5.5 V.

Table 11: A/D converter DC electrical characteristics

V_3A= 2.5 V to 3.6 V unless otherwise speciﬁed; T_amb= −40 °C to +85 °C unless otherwise speciﬁed; A/D converter frequency

4.5 MHz.

Symbol

AV_IN

C_IN

Parameter

Min

Max

V_3A

1

Unit

V

Analog input voltage

Analog input capacitance

Differential non-linearity^[1][2][3]

Integral non-linearity^[1][4]

Offset error^[1][5]

0

-

pF

DL_e

IL_e

±1

LSB

%

±2

OS_e

G_e

±3

Gain error^[1][6]

Absolute error^[1][7]

±0.5

±4

A_e

LSB

[1] Conditions: V_SSA= 0 V, V_3A= 3.3 V.

[2] The A/D is monotonic, there are no missing codes.

[3] The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 4.

[4] The integral no-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5] The offset error (OSe) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 4.

[6] The gain error (Ge) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 4.

[7] The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated A/D and the ideal transfer curve. See Figure 4.

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gain

error

offset

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

IA

ideal

V

− V

SSA

DDA

1 LSB =

offset

error

1024

002aaa668

E

O

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential non-linearity (DL_e).

(4) Integral non-linearity (IL_e).

(5) Center of a step of the actual transfer curve.

Fig 4. A/D conversion characteristics.

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9. Dynamic characteristics

Table 12: Characteristics

T_amb= 0 °C to +70 °C for commercial, −40 °C to +85 °C for industrial, V₁₈, V₃over speciﬁed ranges^[1]

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

External Clock

f_osc

Oscillator frequency supplied by an

external oscillator (signal generator)

1

-

50

30

25

MHz

External clock frequency supplied by

an external crystal oscillator

1

External clock frequency if on-chip

PLL is used

10

External clock frequency if ISP is

used for initial code download

t_C

Oscillator clock period

Clock high time

Clock low time

20

-

1000

ns

t_CHCX

t_CLCX

t_CLCH

t_CHCL

Port Pins

t_RISE

t_c× 0.4

-

t_c× 0.4

-

Clock rise time

Clock fall time

-

5

Port output rise time (except P0.2,

P0.3)

-

10

-

ns

t_FALL

Port output fall time (except P0.2,

P0.3)

I²C pins

t_f

Output fall time from V_IHto V_IL

20 +

0.1 × C_b

-

ns

[2]

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Bus capacitance C_bin pF, from 10 pF to 400 pF.

Table 13: External memory interface AC characteristics. C_L= 25 pF. T_amb= 40 °C

Symbol

Description

Min

Max

Unit

Common to Read and Write Cycles

t_CHAVR

t_CHCSL

t_CHCSH

t_CHANV

XCLK HIGH to Address Valid

-

10

ns

XCLK HIGH to CS LOW

XCLK HIGH to CS HIGH

XCLK HIGH to Address Invalid

Read Cycle Parameters

t_CSLAV

t_OELAVR

t_CSLOEL

t_AVDV

CS LOW to Address Valid

−5^[1]

−5

10

5

ns

OE LOW to Address Valid

CS LOW to OE LOW

Memory Access Time (latest of Address (t_CYC*(2 + WST1)) + (−20) -

Valid, CS LOW, OE LOW to Data Valid)

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Table 13: External memory interface AC characteristics. C_L= 25 pF. T_amb= 40 °C…continued

Symbol

Description

Min

Max

Unit

t_AVDV

Burst-ROM Initial Memory Access Time (t_CYC*(2 + WST1)) + (−20) -

(latest of Address Valid, CS LOW, OE

ns

LOW to Data Valid)

t_AVDV

Burst-ROM Subsequent Memory Access t_CYC+ (−20)

Time (Address Valid to Data Valid)

-

ns

t_STHDNV

Data Hold Time (earliest of CS HIGH, OE

HIGH, Address Change to Data Invalid)

0

t_CSHOEH

t_OEHANV

t_CHOEL

CS HIGH to OE HIGH

−5

5

ns

OE HIGH to Address Invalid

XCLK HIGH to OE LOW

XCLK HIGH to OE HIGH

t_CHOEH

Write Cycle Parameters

t_AVCSLW

t_CSLDVW

t_CSLWEL

t_CSLBLSL

t_WELDV

Address Valid to CS LOW

t

_CYC− 10 ^[1]

-

ns

CS LOW to Data Valid

−5

5

CS LOW to WE LOW

5

CS LOW to BLS LOW

5

WE LOW to Data Valid

CS LOW to Data Valid

5

t_CSLDV

5

t_WELWEH

t_WEHANV

t_WEHDNV

t_BLSHANV

t_BLSHDNV

t_CHDV

WE LOW to WE HIGH

BLS LOW to BLS HIGH

WE HIGH to Address Invalid

WE HIGH to Data Invalid

BLS HIGH to Address Invalid

BLS HIGH to Data Invalid

XCLK HIGH to Data Valid

XCLK HIGH to WE LOW

XCLK HIGH to BLS LOW

XCLK HIGH to WE HIGH

XCLK HIGH to BLS HIGH

XCLK HIGH to Data Invalid

t

_CYC× (1 + WST2) − 5

t_CYC*(1 + WST2) + 5

_CYC× (1 + WST2) − 5

_CYC−5

t_CYC*(1 + WST2) + 5

t_CYC+ 5

(2 × t_CYC)−5

_CYC−5

(2 × t_CYC) + 5

t

t_CYC+ 5

(2 × t_CYC)−5

(2 × t_CYC) + 5

-

10

t_CHWEL

t_CHHBLSL

t_AVCSL

[1] Except on initial access, in which case the address is set up t_CYCearlier.

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Table 14: Standard read access speciﬁcations

Access cycle

Max frequency

WST setting

Memory access time

requirement

WST ≥ 0; round up to

integer

Standard read

2 + WST1

_RAM+ 20ns

t_RAM+ 20ns

t_RAM≤ t_CYC× (2 + WST1) – 20ns

f _MAX

≤

------------------------------

WST1 ≥

WST2 ≥

– 2

------------------------------

t

t_CYC

Standard write

1 + WST2

t

_WRITE– t_CYC+ 5

t_WRITE≤ t_CYC× (1 + WST2) – 5ns

≤

--------------------------------

-------------------------------------------

t

_WRITE+ 5ns

t_CYC

Burst read - initial

Burst read - subsequent 3×

2 + WST1

t_INIT+ 20ns

t_INIT≤ t_CYC× (2 + WST1) – 20ns

≤

------------------------------

WST1 ≥

– 2

------------------------------

t_INIT+ 20ns

t_CYC

N/A

1

t

_ROM≤ t_CYC– 20ns

------------------------------

t_ROM+ 20ns

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34 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

9.1 Timing

XCLK

CS

t

CSHOEH

t

CLSAV

Addr

Data

OE

t

AVDV

STHDNV

t

CSLOEL

t

OEHANV

OELAVR

t

CHOEH

CHOEL

002aaa749

Fig 5. External memory read access.

XCLK

CS

t

CSLDVW

t

AVCSLW

t

WELWEH

t

BLSLBLSH

BLS/WE

Addr

t

CSLWEL

t

WEHANV

t

CSLBLSL

t

WELDV

BLSHANV

t

WEHDNV

t

CSLDV

t

Data

BLSHDNV

OE

002aaa750

Fig 6. External memory write access.

9397 750 13149

Product data

Rev. 02 — 23 December 2004

35 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

V

- 0.5 V

0.45 V

DD

0.2 V

+ 0.9

DD

- 0.1 V

0.2 V

DD

t

CHCX

t

CLCX

t

CHCL

CLCH

t

C

002aaa416

Fig 7. External clock timing.

9397 750 13149

Product data

Rev. 02 — 23 December 2004

36 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

10. Package outline

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

y

X

A

108

109

73

72

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

L

pin 1 index

detail X

37

144

1

36

v M

Z

A

w M

D

b

p

e

D

B

H

v M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

mm

1.6

0.25

1

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

Fig 8. SOT486-1 (LQFP144).

9397 750 13149

Product data

Rev. 02 — 23 December 2004

37 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

11. Revision history

Table 15: Revision history

Rev Date

CPCN

-

Description

02 20041223

Product data (9397 750 13149)

Modiﬁcations:

• Section 6.2 “On-Chip Flash program memory” on page 11; updated text.

• Section 6.20.2 “PLL” on page 25; updated text.

• Section 6.20.7 “VPB bus” on page 26; updated text.

• Table 9 “Limiting values” on page 28; updated storage temperature specs.

• Table 10 “Static characteristics” on page 29; adjusted I₁₈typical value; added On-chip

Flash program memory specs.

01 20040202

-

Preliminary data (9397 750 12747)

9397 750 13149

Product data

Rev. 02 — 23 December 2004

38 of 40

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

12. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

performance. When the product is in full production (status ‘Production’),

13. Deﬁnitions

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

15. Licenses

Purchase of Philips I²C components

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Purchase of Philips I²C components conveys a license

under the Philips’ I²C patent to use the components in the

I²C system provided the system conforms to the I²C

speciﬁcation deﬁned by Philips. This speciﬁcation can be

ordered using the code 9398 393 40011.

14. Disclaimers

16. Trademarks

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

ARM — is a registered trademark of ARM, Inc.

ARM7TDMI-S — is a trademark of ARM, Inc.

EmbeddedICE — is a registered trademark of ARM, Inc.

Embedded Trace Macrocell — is a trademark of ARM, Inc.

RealMonitor — is a trademark of ARM, Inc.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

SPI — is a trademark of Motorola, Inc.

Thumb — is a registered trademark of ARM, Inc.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

39 of 40

9397 750 13149

Product data

Rev. 02 — 23 December 2004

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Philips Semiconductors

Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.20.7

6.21

6.21.1

6.21.2

6.21.3

VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Emulation and debugging. . . . . . . . . . . . . . . . 26

Embedded ICE. . . . . . . . . . . . . . . . . . . . . . . . 27

Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 27

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2

2.1

3

3.1

4

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28

Static characteristics . . . . . . . . . . . . . . . . . . . 29

Dynamic characteristics. . . . . . . . . . . . . . . . . 32

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37

Revision history . . . . . . . . . . . . . . . . . . . . . . . 38

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 39

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

9

9.1

10

11

12

13

14

15

16

6

Functional description . . . . . . . . . . . . . . . . . . 11

Architectural overview. . . . . . . . . . . . . . . . . . . 11

On-Chip Flash program memory . . . . . . . . . . 11

On-Chip static RAM . . . . . . . . . . . . . . . . . . . . 12

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 13

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 14

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 15

Pin function select register 0 (PINSEL0

6.1

6.2

6.3

6.4

6.5

6.5.1

6.6

6.7

- 0xE002C000). . . . . . . . . . . . . . . . . . . . . . . . 15

Pin function select register 1 (PINSEL1

- 0xE002C004). . . . . . . . . . . . . . . . . . . . . . . . 17

Pin function select register 2 (PINSEL2

6.8

6.9

- 0xE002C014). . . . . . . . . . . . . . . . . . . . . . . . 19

External memory controller. . . . . . . . . . . . . . . 20

General purpose parallel I/O. . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10-bit A/D converter . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I²C serial I/O controller . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

General purpose timers . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Real time clock . . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Pulse width modulator . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

System control . . . . . . . . . . . . . . . . . . . . . . . . 25

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 25

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset and wake-up timer . . . . . . . . . . . . . . . . 25

External interrupt inputs . . . . . . . . . . . . . . . . . 26

Memory Mapping Control . . . . . . . . . . . . . . . . 26

Power Control . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.10

6.11

6.11.1

6.12

6.12.1

6.13

6.13.1

6.14

6.14.1

6.15

6.15.1

6.16

6.16.1

6.17

6.17.1

6.18

6.18.1

6.19

6.19.1

6.20

6.20.1

6.20.2

6.20.3

6.20.4

6.20.5

6.20.6

Printed in the U.S.A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 23 December 2004

Document order number: 9397 750 13149


型号：	LPC2214FBD144
厂家：	NXP
描述：	16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP Flash with 10-bit ADC and external memory interface 16位/ 32位ARM微控制器; 128/256 KB ISP / IAP闪存与10位ADC和外部存储器接口闪存存储微控制器和处理器外围集成电路时钟
文件：	总40页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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