LPC2458FET180,529 [NXP]
LPC2458 - Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface BGA 180-Pin;
| 型号： | LPC2458FET180,529 |
| 厂家： | 
NXP |
| 描述： | LPC2458 - Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface BGA 180-Pin PC |
| 文件： | 总81页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPC2458
Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 4.1 — 15 October 2013
Product data sheet
1. General description
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This
flash memory includes a special 128-bit wide memory interface and accelerator
architecture that enables the CPU to execute sequential instructions from flash memory at
the maximum 72 MHz system clock rate. This feature is available only on the LPC2000
ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and
16-bit Thumb instructions. Support for the two instruction sets means engineers can
choose to optimize their application for either performance or code size at the sub-routine
level. When the core executes instructions in Thumb state it can reduce code size by
more than 30 % with only a small loss in performance while executing instructions in ARM
state maximizes core performance.
The LPC2458 microcontroller is ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C
interfaces, and an I2S interface. Supporting this collection of serial communications
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered interrupts. All of these features make the LPC2458
particularly suitable for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz.
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
16 kB SRAM for general purpose DMA use also accessible by the USB.
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, USB DMA, and program execution from on-chip flash with no contention.
EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as Single Data Rate SDRAM.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,
I2S, and SD/MM interface as well as for memory-to-memory transfers.
Serial Interfaces:
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and
associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels.
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
Three I2C-bus interfaces (one with open-drain and two with standard port pins).
I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
Other peripherals:
SD/MMC memory card interface.
136 General purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC.
Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
RTC with separate power domain, clock source can be the RTC oscillator or the
APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
2 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Two independent power domains allow fine tuning of power consumption based on
needed features.
Each peripheral has its own clock divider for further power saving. These dividers help
reduce active power by 20 % to 30 %.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip power-on reset.
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
Boundary scan for simplified board testing.
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
3. Applications
Industrial control
Medical systems
Protocol converter
Communications
4. Ordering information
Table 1.
Ordering information
Package
Name
Type number
Description
Version
LPC2458FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm
SOT570-3
4.1 Ordering options
Table 2.
Ordering options
Type number
Flash
(kB)
SRAM (kB)
External
bus
Ethernet USB
OTG/
SD/
MMC DMA
GP
Temp
range
OHC/
DEV
+ 4 kB
FIFO
LPC2458FET180
512
64 16 16 2 98 16-bit
MII/
RMII
yes
2
yes
yes
8
1
40 C to
+85 C
LPC2458
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
3 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
5. Block diagram
XTAL1
V
XTAL2
DD(3V3)
DDA
TMS TDI
trace signals
V
TRST TCK TDO
RESET
EXTIN0 DBGEN
VREF
SYSTEM
FUNCTIONS
LPC2458
PLL
V
V
, V
V
P0, P1, P2,
SSA SSIO, SSCORE
64 kB
SRAM
512 kB
FLASH
TEST/DEBUG
INTERFACE
DD(DCDC)(3V3)
P3, P4
system
clock
INTERNAL RC
OSCILLATOR
HIGH-SPEED
GPIO
136 PINS
TOTAL
INTERNAL
CONTROLLERS
ARM7TDMI-S
SRAM FLASH
D[15:0]
A[19:0]
EXTERNAL
MEMORY
CONTROLLER
16 kB
SRAM
VIC
control lines
AHB1
AHB2
AHB
BRIDGE
AHB
BRIDGE
V
BUS
USB DEVICE/
HOST/OTG WITH
4 kB RAM AND DMA
16 kB
SRAM
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
ETHERNET
MAC WITH
DMA
port 1
port 2
MII/RMII
AHB TO
GPDMA
CONTROLLER
APB BRIDGE
EINT3 to EINT0
P0, P2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
EXTERNAL INTERRUPTS
2
I S INTERFACE
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT3,
2 × MAT1/MAT0
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SPI, SSP0 INTERFACE
SSP1 INTERFACE
6 × PWM0, PWM1
PWM0, PWM1
1 × PCAP0,
2 × PCAP1
SCK1
MOSI1
MISO1
SSEL1
LEGACY GPI/O
64 PINS TOTAL
P0, P1
MCICLK, MCIPWR
SD/MMC CARD
INTERFACE
8 × AD0
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
MCICMD,
MCIDAT[3:0]
AOUT
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
UART0, UART2, UART3
UART1
VBAT
TXD1
RXD1
DTR1, RTS1
power domain 2
REAL-
TIME
RTCX1
RTCX2
RTC
OSCILLATOR
DSR1, CTS1, DCD1,
RI1
CLOCK
ALARM
RD1, RD2
TD1, TD2
CAN1, CAN2
WATCHDOG TIMER
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
2
2
2
I C0, I C1, I C2
SYSTEM CONTROL
002aad093
Fig 1. LPC2458 block diagram
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
4 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
6. Pinning information
6.1 Pinning
ball A1
index area
LPC2458
1
2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
002aad094
Transparent top view
Fig 2. LPC2458 pinning TFBGA180 package
Table 3.
Pin allocation table
Pin Symbol
Row A
Pin Symbol
Pin Symbol
Pin Symbol
1
5
P3[12]/D12
2
6
P3[2]/D2
P3[8]/D8
3
7
P0[3]/RXD0
P1[10]/ENET_RXD1
4
8
P3[9]/D9
P1[1]/ENET_TXD1
P1[15]/
ENET_REF_CLK/
ENET_RX_CLK
9
P1[3]/ENET_TXD3/
MCICMD/PWM0[2]
10 VSSCORE
11 P0[4]/I2SRX_CLK/RD2/ 12 P1[11]/ENET_RXD2/
CAP2[0]
MCIDAT2/PWM0[6]
13 P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
14 P1[12]/ENET_RXD3/
MCIDAT3/PCAP0[0]
15
-
16
-
Row B
1
5
TDO
2
6
P3[11]/D11
3
7
P3[10]/D10
4
8
VSSIO
P1[0]/ENET_TXD0
P1[8]/ENET_CRS_DV/
ENET_CRS
P1[2]/ENET_TXD2/
MCICLK/PWM0[1]
P1[16]/ENET_MDC
9
P4[29]/
MAT2[1]/RXD3
10 P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
11 P0[5]/I2SRX_WS/TD2/ 12 P0[7]/I2STX_CLK/SCK1
CAP2[1]
/MAT2[1]
13 P1[5]/ENET_TX_ER/
MCIPWR/PWM0[3]
14 P4[13]/A13
15
-
16
-
Row C
1
5
9
P3[13]/D13
2
6
TMS
3
7
TDI
4
8
RTCK
VDD(3V3)
P1[4]/ENET_TX_EN
P4[30]/CS0
P4[24]/OE
P1[17]/ENET_MDIO
10 P4[15]/A15
11 VSSIO
12 P0[8]/I2STX_WS/
MISO1/MAT2[2]
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
5 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 3.
Pin allocation table …continued
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
13 P1[7]/ENET_COL/
MCIDAT1/PWM0[5]
14 P2[1]/PWM1[2]/RXD1/
PIPESTAT0
15
-
16
-
Row D
1
P0[26]/AD0[3]/
AOUT/RXD3
2
6
TCK
3
7
P3[4]/D4
4
8
TRST
5
9
P0[2]/TXD0
P4[25]/WE
P3[0]/D0
P1[9]/ENET_RXD0
P1[14]/ENET_RX_ER
10 P4[28]/
MAT2[0]/TXD3
11 P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
12 P2[0]/PWM1[1]/TXD1/
TRACECLK
13 VSSIO
14 P1[13]/ENET_RX_DV
15
-
16
-
Row E
1
P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
2
6
VDD(3V3)
P3[1]/D1
3
7
P3[5]/D5
4
8
P0[25]/AD0[2]/
I2SRX_SDA/TXD3
5
9
DBGEN
P4[31]/CS1
P4[14]/A14
VDD(DCDC)(3V3)
10 VDD(3V3)
11 P2[2]/PWM1[3]/
CTS1/PIPESTAT1
12 VDD(3V3)
13 P2[3]/PWM1[4]/
DCD1/PIPESTAT2
14 P2[4]/PWM1[5]/
DSR1/TRACESYNC
15
-
16
-
Row F
1
5
P3[14]/D14
2
6
VDDA
3
7
VSSA
4
8
P3[6]/D6
P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0]
9
10 P4[12]/A12
14 P4[27]/BLS1
11 P4[11]/A11
12 P2[5]/PWM1[6]/
DTR1/TRACEPKT0
13 P2[6]/PCAP1[0]/
RI1/TRACEPKT1
15
-
16
-
Row G
1
5
9
VDD(DCDC)(3V3)
P3[3]/D3
2
6
VREF
3
7
P3[7]/D7
4
8
P3[15]/D15
10 n.c.
11 P2[7]/RD2/
RTS1/TRACEPKT2
12 P4[10]/A10
13 VSSIO
14 P2[8]/TD2/
15
-
16
-
TXD2/TRACEPKT3
Row H
1
5
9
n.c.
2
6
RSTOUT
3
7
VSSCORE
4
8
VSSIO
ALARM
10 P4[5]/A5
11 P2[9]/
USB_CONNECT1/
12 P4[9]/A9
RXD2/EXTIN0
13 P0[15]/TXD1/
SCK0/SCK
14 P0[16]/RXD1/
SSEL0/SSEL
15
-
16
-
Row J
1
RESET
2
6
RTCX1
3
7
RTCX2
4
8
P0[12]/USB_PPWR2/
MISO1/AD0[6]
5
P0[13]/USB_UP_LED2/
MOSI1/AD0[7]
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
6 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 3. Pin allocation table …continued
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
9
10 P0[19]/DSR1/
MCICLK/SDA1
11 P4[8]/A8
12 P0[17]/CTS1/
MISO0/MISO
13 P0[18]/DCD1/
MOSI0/MOSI
14 VDD(3V3)
15
-
16
-
Row K
1
5
9
VBAT
2
6
P1[31]/USB_OVRCR2/
SCK1/AD0[5]
3
7
P1[30]/USB_PWRD2/
VBUS/AD0[4]
4
8
XTAL2
P0[29]/USB_D+1
P4[3]/A3
P1[20]/USB_TX_DP1/
PWM1[2]/SCK0
P3[26]/MAT0[1]/
PWM1[3]
VDD(3V3)
10 P4[6]/A6
11 P0[21]/RI1/
MCIPWR/RD1
12 P4[7]/A7
13 P4[26]/BLS0
14 P0[20]/DTR1/
MCICMD/SCL1
15
-
16
-
Row L
1
5
P2[29]/DQMOUT1
2
6
XTAL1
3
7
P0[27]/SDA0
4
8
VDD(3V3)
VSSCORE
P1[18]/USB_UP_LED1/
PWM1[1]/CAP1[0]
P4[0]/A0
P1[25]/USB_LS1/
USB_HSTEN1/MAT1[1]
9
VSSIO
10 P0[10]/TXD2/SDA2/
MAT3[0]
11 VDD(3V3)
12 n.c.
13 VSSIO
14 P0[22]/RTS1/
MCIDAT0/TD1
15
-
16
-
Row M
1
P0[28]/SCL0
2
6
P2[28]/DQMOUT0
3
7
P3[25]/MAT0[0]/
PWM1[2]
4
8
P3[23]/CAP0[0]/
PCAP1[0]
5
P0[14]/USB_HSTEN2/
USB_CONNECT2/
SSEL1
P1[22]/USB_RCV1/
USB_PWRD1/MAT1[0]
P4[1]/A1
P4[2]/A2
9
P1[27]/USB_INT1/
USB_OVRCR1/CAP0[1]
10 P0[0]/RD1/TXD3/SDA1 11 P2[13]/EINT3/
MCIDAT3/I2STX_SDA
12 P2[11]/EINT1/
MCIDAT1/I2STX_CLK
13 P2[10]/EINT0
14 P4[19]/A19
15
-
16
-
Row N
1
5
9
P0[31]/USB_D+2
P2[19]/CLKOUT1
VDD(DCDC)(3V3)
2
6
USB_D2
3
7
P3[24]/CAP0[1]/
PWM1[1]
4
8
P0[30]/USB_D1
P1[21]/USB_TX_DM1/
PWM1[3]/SSEL0
P1[23]/USB_RX_DP1/
PWM1[4]/MISO0
P2[21]/DYCS1
10 P1[29]/USB_SDA1/
PCAP1[1]/MAT0[1]
11 P0[1]/TD1/RXD3/SCL1 12 P4[16]/A16
13 P4[17]/A17
14 P2[12]/EINT2/
15
-
16
-
MCIDAT2/I2STX_WS
Row P
1
5
P2[24]/CKEOUT0
2
6
P2[25]/CKEOUT1
P2[20]/DYCS0
3
7
P2[18]/CLKOUT0
4
8
VSSIO
P1[19]/USB_TX_E1/
USB_PPWR1/CAP1[1]
P1[24]/USB_RX_DM1/
PWM1[5]/MOSI0
P1[26]/USB_SSPND1/
PWM1[6]/CAP0[0]
9
P2[16]/CAS
10 P1[28]/USB_SCL1/
PCAP1[0]/MAT0[0]
11 P2[17]/RAS
12 P0[11]/RXD2/SCL2/
MAT3[1]
13 P4[4]/A4
14 P4[18]/A18
15
-
16
-
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
7 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
6.2 Pin description
Table 4.
Symbol
Pin description
Ball
Type
Description
P0[0] to P0[31]
I/O
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the Pin
Connect block.
P0[0]/RD1/
TXD3/SDA1
M10[1]
I/O
I
P0[0] — General purpose digital input/output pin.
RD1 — CAN1 receiver input.
O
TXD3 — Transmitter output for UART3.
I/O
I/O
O
SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0[1] — General purpose digital input/output pin.
TD1 — CAN1 transmitter output.
P0[1]/TD1/RXD3/
SCL1
N11[1]
I
RXD3 — Receiver input for UART3.
I/O
I/O
O
SCL1 — I2C1 clock input/output (this is not an open-drain pin).
P0[2] — General purpose digital input/output pin.
TXD0 — Transmitter output for UART0.
P0[2]/TXD0
P0[3]/RXD0
D5[1]
A3[1]
A11[1]
I/O
I
P0[3] — General purpose digital input/output pin.
RXD0 — Receiver input for UART0.
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
I/O
I/O
P0[4] — General purpose digital input/output pin.
I2SRX_CLK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
I
RD2 — CAN2 receiver input.
I
CAP2[0] — Capture input for Timer 2, channel 0.
P0[5] — General purpose digital input/output pin.
P0[5]/
I2SRX_WS/
TD2/CAP2[1]
B11[1]
D11[1]
B12[1]
C12[1]
I/O
I/O
I2SRX_WS — Receive Word Select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I2S-bus specification.
O
TD2 — CAN2 transmitter output.
I
CAP2[1] — Capture input for Timer 2, channel 1.
P0[6] — General purpose digital input/output pin.
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
I/O
I/O
I2SRX_SDA — Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
O
SSEL1 — Slave Select for SSP1.
MAT2[0] — Match output for Timer 2, channel 0.
P0[7] — General purpose digital input/output pin.
P0[7]/
I2STX_CLK/
SCK1/MAT2[1]
I/O
I/O
I2STX_CLK — Transmit Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
I/O
O
SCK1 — Serial Clock for SSP1.
MAT2[1] — Match output for Timer 2, channel 1.
P0[8] — General purpose digital input/output pin.
P0[8]/
I/O
I/O
I2STX_WS/
MISO1/MAT2[2]
I2STX_WS — Transmit Word Select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I2S-bus specification.
I/O
O
MISO1 — Master In Slave Out for SSP1.
MAT2[2] — Match output for Timer 2, channel 2.
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
8 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 4.
Symbol
Pin description …continued
Ball
Type
I/O
Description
P0[9]/
A13[1]
P0[9] — General purpose digital input/output pin.
I2STX_SDA/
MOSI1/MAT2[3]
I/O
I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
O
MOSI1 — Master Out Slave In for SSP1.
MAT2[3] — Match output for Timer 2, channel 3.
P0[10] — General purpose digital input/output pin.
TXD2 — Transmitter output for UART2.
P0[10]/TXD2/
SDA2/MAT3[0]
L10[1]
P12[1]
J4[2]
I/O
O
I/O
O
SDA2 — I2C2 data input/output (this is not an open-drain pin).
MAT3[0] — Match output for Timer 3, channel 0.
P0[11] — General purpose digital input/output pin.
RXD2 — Receiver input for UART2.
P0[11]/RXD2/
SCL2/MAT3[1]
I/O
I
I/O
O
SCL2 — I2C2 clock input/output (this is not an open-drain pin).
MAT3[1] — Match output for Timer 3, channel 1.
P0[12] — General purpose digital input/output pin.
USB_PPWR2 — Port Power enable signal for USB port 2.
MISO1 — Master In Slave Out for SSP1.
P0[12]/
I/O
O
USB_PPWR2/
MISO1/AD0[6]
I/O
I
AD0[6] — A/D converter 0, input 6.
P0[13]/
USB_UP_LED2/
MOSI1/AD0[7]
J5[2]
I/O
O
P0[13] — General purpose digital input/output pin.
USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is
configured (non-control endpoints enabled), or when host is enabled and has
detected a device on the bus. It is HIGH when the device is not configured, or
when host is enabled and has not detected a device on the bus, or during global
suspend. It transitions between LOW and HIGH (flashes) when host is enabled
and detects activity on the bus.
I/O
I
MOSI1 — Master Out Slave In for SSP1.
AD0[7] — A/D converter 0, input 7.
P0[14]/
M5[1]
I/O
O
P0[14] — General purpose digital input/output pin.
USB_HSTEN2 — Host Enabled status for USB port 2.
USB_HSTEN2/
USB_CONNECT2/
SSEL1
O
USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch
an external 1.5 k resistor under software control. Used with the SoftConnect
USB feature.
I/O
I/O
O
SSEL1 — Slave Select for SSP1.
P0[15]/TXD1/
SCK0/SCK
H13[1]
P0[15] — General purpose digital input/output pin.
TXD1 — Transmitter output for UART1.
SCK0 — Serial clock for SSP0.
I/O
I/O
I/O
I
SCK — Serial clock for SPI.
P0[16]/RXD1/
SSEL0/SSEL
H14[1]
P0[16] — General purpose digital input/output pin.
RXD1 — Receiver input for UART1.
SSEL0 — Slave Select for SSP0.
I/O
I/O
SSEL — Slave Select for SPI.
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
9 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 4.
Symbol
Pin description …continued
Ball
Type
I/O
I
Description
P0[17]/CTS1/
MISO0/MISO
J12[1]
P0[17] — General purpose digital input/output pin.
CTS1 — Clear to Send input for UART1.
I/O
I/O
I/O
I
MISO0 — Master In Slave Out for SSP0.
MISO — Master In Slave Out for SPI.
P0[18]/DCD1/
MOSI0/MOSI
J13[1]
J10[1]
K14[1]
K11[1]
L14[1]
F5[2]
P0[18] — General purpose digital input/output pin.
DCD1 — Data Carrier Detect input for UART1.
MOSI0 — Master Out Slave In for SSP0.
I/O
I/O
I/O
I
MOSI — Master Out Slave In for SPI.
P0[19]/DSR1/
MCICLK/SDA1
P0[19] — General purpose digital input/output pin.
DSR1 — Data Set Ready input for UART1.
MCICLK — Clock output line for SD/MMC interface.
SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0[20] — General purpose digital input/output pin.
DTR1 — Data Terminal Ready output for UART1.
MCICMD — Command line for SD/MMC interface.
SCL1 — I2C1 clock input/output (this is not an open-drain pin).
P0[21] — General purpose digital input/output pin.
RI1 — Ring Indicator input for UART1.
O
I/O
I/O
O
P0[20]/DTR1/
MCICMD/SCL1
I/O
I/O
I/O
I
P0[21]/RI1/
MCIPWR/RD1
O
MCIPWR — Power Supply Enable for external SD/MMC power supply.
RD1 — CAN1 receiver input.
I
P0[22]/RTS1/
MCIDAT0/TD1
I/O
O
P0[22] — General purpose digital input/output pin.
RTS1 — Request to Send output for UART1.
MCIDAT0 — Data line 0 for SD/MMC interface.
TD1 — CAN1 transmitter output.
I/O
O
P0[23]/AD0[0]/
I2SRX_CLK/
CAP3[0]
I/O
I
P0[23] — General purpose digital input/output pin.
AD0[0] — A/D converter 0, input 0.
I/O
I2SRX_CLK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
I
CAP3[0] — Capture input for Timer 3, channel 0.
P0[24] — General purpose digital input/output pin.
AD0[1] — A/D converter 0, input 1.
P0[24]/AD0[1]/
I2SRX_WS/
CAP3[1]
E1[2]
I/O
I
I/O
I2SRX_WS — Receive Word Select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I2S-bus specification.
I
CAP3[1] — Capture input for Timer 3, channel 1.
P0[25] — General purpose digital input/output pin.
AD0[2] — A/D converter 0, input 2.
P0[25]/AD0[2]/
I2SRX_SDA/
TXD3
E4[2]
I/O
I
I/O
I2SRX_SDA — Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
O
TXD3 — Transmitter output for UART3.
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
10 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 4.
Symbol
Pin description …continued
Ball
Type
I/O
I
Description
P0[26]/AD0[3]/
AOUT/RXD3
D1[2][3]
P0[26] — General purpose digital input/output pin.
AD0[3] — A/D converter 0, input 3.
O
AOUT — D/A converter output.
I
RXD3 — Receiver input for UART3.
P0[27]/SDA0
L3[4]
M1[4]
K5[5]
N4[5]
N1[5]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P0[27] — General purpose digital input/output pin. Output is open-drain.
SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance).
P0[28] — General purpose digital input/output pin. Output is open-drain.
SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
P0[29] — General purpose digital input/output pin.
USB_D+1 — USB port 1 bidirectional D+ line.
P0[28]/SCL0
P0[29]/USB_D+1
P0[30]/USB_D1
P0[31]/USB_D+2
P1[0] to P1[31]
P0[30] — General purpose digital input/output pin.
USB_D1 — USB port 1 bidirectional D line.
P0[31] — General purpose digital input/output pin.
USB_D+2 — USB port 2 bidirectional D+ line.
Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 1 pins depends upon the pin function selected via the Pin
Connect block.
P1[0]/
ENET_TXD0
B5[1]
A5[1]
B7[1]
I/O
O
P1[0] — General purpose digital input/output pin.
ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).
P1[1] — General purpose digital input/output pin.
ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
P1[2] — General purpose digital input/output pin.
ENET_TXD2 — Ethernet transmit data 2 (MII interface).
MCICLK — Clock output line for SD/MMC interface.
PWM0[1] — Pulse Width Modulator 0, output 1.
P1[1]/
ENET_TXD1
I/O
O
P1[2]/
I/O
O
ENET_TXD2/
MCICLK/
PWM0[1]
O
O
P1[3]/
A9[1]
I/O
O
P1[3] — General purpose digital input/output pin.
ENET_TXD3 — Ethernet transmit data 3 (MII interface).
MCICMD — Command line for SD/MMC interface.
PWM0[2] — Pulse Width Modulator 0, output 2.
ENET_TXD3/
MCICMD/
PWM0[2]
I/O
O
P1[4]/
ENET_TX_EN
C6[1]
I/O
O
P1[4] — General purpose digital input/output pin.
ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface).
P1[5] — General purpose digital input/output pin.
ENET_TX_ER — Ethernet Transmit Error (MII interface).
MCIPWR — Power Supply Enable for external SD/MMC power supply.
PWM0[3] — Pulse Width Modulator 0, output 3.
P1[5]/
B13[1]
I/O
O
ENET_TX_ER/
MCIPWR/
PWM0[3]
O
O
P1[6]/
B10[1]
I/O
I
P1[6] — General purpose digital input/output pin.
ENET_TX_CLK — Ethernet Transmit Clock (MII interface).
MCIDAT0 — Data line 0 for SD/MMC interface.
ENET_TX_CLK/
MCIDAT0/
PWM0[4]
I/O
O
PWM0[4] — Pulse Width Modulator 0, output 4.
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
11 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 4.
Symbol
Pin description …continued
Ball
C13[1]
Type
I/O
I
Description
P1[7]/
P1[7] — General purpose digital input/output pin.
ENET_COL — Ethernet Collision detect (MII interface).
MCIDAT1 — Data line 1 for SD/MMC interface.
PWM0[5] — Pulse Width Modulator 0, output 5.
P1[8] — General purpose digital input/output pin.
ENET_COL/
MCIDAT1/
PWM0[5]
I/O
O
P1[8]/
ENET_CRS_DV/
ENET_CRS
B6[1]
I/O
I
ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid (RMII
interface)/ Ethernet Carrier Sense (MII interface).
P1[9]/
ENET_RXD0
D7[1]
A7[1]
A12[1]
I/O
I
P1[9] — General purpose digital input/output pin.
ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).
P1[10] — General purpose digital input/output pin.
ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
P1[11] — General purpose digital input/output pin.
ENET_RXD2 — Ethernet Receive Data 2 (MII interface).
MCIDAT2 — Data line 2 for SD/MMC interface.
P1[10]/
ENET_RXD1
I/O
I
P1[11]/
I/O
I
ENET_RXD2/
MCIDAT2/
PWM0[6]
I/O
O
I/O
I
PWM0[6] — Pulse Width Modulator 0, output 6.
P1[12]/
A14[1]
P1[12] — General purpose digital input/output pin.
ENET_RXD3 — Ethernet Receive Data (MII interface).
MCIDAT3 — Data line 3 for SD/MMC interface.
ENET_RXD3/
MCIDAT3/
PCAP0[0]
I/O
I
PCAP0[0] — Capture input for PWM0, channel 0.
P1[13] — General purpose digital input/output pin.
ENET_RX_DV — Ethernet Receive Data Valid (MII interface).
P1[14] — General purpose digital input/output pin.
ENET_RX_ER — Ethernet receive error (RMII/MII interface).
P1[15] — General purpose digital input/output pin.
P1[13]/
ENET_RX_DV
D14[1]
D8[1]
A8[1]
I/O
I
P1[14]/
ENET_RX_ER
I/O
I
P1[15]/
ENET_REF_CLK/
ENET_RX_CLK
I/O
I
ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII interface)/
Ethernet Receive Clock (MII interface).
P1[16]/
ENET_MDC
B8[1]
C9[1]
L5[1]
I/O
O
P1[16] — General purpose digital input/output pin.
ENET_MDC — Ethernet MIIM clock.
P1[17]/
ENET_MDIO
I/O
I/O
I/O
O
P1[17] — General purpose digital input/output pin.
ENET_MDIO — Ethernet MI data input and output.
P1[18] — General purpose digital input/output pin.
P1[18]/
USB_UP_LED1/
PWM1[1]/
CAP1[0]
USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is
configured (non-control endpoints enabled), or when host is enabled and has
detected a device on the bus. It is HIGH when the device is not configured, or
when host is enabled and has not detected a device on the bus, or during global
suspend. It transitions between LOW and HIGH (flashes) when host is enabled
and detects activity on the bus.
O
I
PWM1[1] — Pulse Width Modulator 1, channel 1 output.
CAP1[0] — Capture input for Timer 1, channel 0.
P1[19]/
P5[1]
I/O
O
O
I
P1[19] — General purpose digital input/output pin.
USB_TX_E1/
USB_PPWR1/
CAP1[1]
USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver).
USB_PPWR1 — Port Power enable signal for USB port 1.
CAP1[1] — Capture input for Timer 1, channel 1.
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
12 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 4.
Symbol
Pin description …continued
Ball
K6[1]
Type
I/O
O
Description
P1[20]/
USB_TX_DP1/
PWM1[2]/SCK0
P1[20] — General purpose digital input/output pin.
USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).
PWM1[2] — Pulse Width Modulator 1, channel 2 output.
SCK0 — Serial clock for SSP0.
O
I/O
I/O
O
P1[21]/
USB_TX_DM1/
PWM1[3]/SSEL0
N6[1]
M6[1]
N7[1]
P7[1]
L7[1]
P1[21] — General purpose digital input/output pin.
USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver).
PWM1[3] — Pulse Width Modulator 1, channel 3 output.
SSEL0 — Slave Select for SSP0.
O
I/O
I/O
I
P1[22]/
P1[22] — General purpose digital input/output pin.
USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).
USB_PWRD1 — Power Status for USB port 1 (host power switch).
MAT1[0] — Match output for Timer 1, channel 0.
USB_RCV1/
USB_PWRD1/
MAT1[0]
I
O
P1[23]/
USB_RX_DP1/
PWM1[4]/MISO0
I/O
I
P1[23] — General purpose digital input/output pin.
USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).
PWM1[4] — Pulse Width Modulator 1, channel 4 output.
MISO0 — Master In Slave Out for SSP0.
O
I/O
I/O
I
P1[24]/
USB_RX_DM1/
PWM1[5]/MOSI0
P1[24] — General purpose digital input/output pin.
USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver).
PWM1[5] — Pulse Width Modulator 1, channel 5 output.
MOSI0 — Master Out Slave in for SSP0.
O
I/O
I/O
O
P1[25]/
P1[25] — General purpose digital input/output pin.
USB_LS1 — Low-speed status for USB port 1 (OTG transceiver).
USB_HSTEN1 — Host Enabled status for USB port 1.
MAT1[1] — Match output for Timer 1, channel 1.
USB_LS1/
USB_HSTEN1/
MAT1[1]
O
O
P1[26]/
P8[1]
M9[1]
P10[1]
N10[1]
I/O
O
P1[26] — General purpose digital input/output pin.
USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver).
PWM1[6] — Pulse Width Modulator 1, channel 6 output.
CAP0[0] — Capture input for Timer 0, channel 0.
P1[27] — General purpose digital input/output pin.
USB_INT1 — USB port 1 OTG transceiver interrupt.
USB_OVRCR1 — USB port 1 Over-Current status.
CAP0[1] — Capture input for Timer 0, channel 1.
P1[28] — General purpose digital input/output pin.
USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver).
PCAP1[0] — Capture input for PWM1, channel 0.
MAT0[0] — Match output for Timer 0, channel 0.
USB_SSPND1/
PWM1[6]/
CAP0[0]
O
I
P1[27]/
I/O
I
USB_INT1/
USB_OVRCR1/
CAP0[1]
I
I
P1[28]/
I/O
I/O
I
USB_SCL1/
PCAP1[0]/
MAT0[0]
O
P1[29]/
I/O
I/O
I
P1[29] — General purpose digital input/output pin.
USB_SDA1 — USB port 1 I2C serial data (OTG transceiver).
PCAP1[1] — Capture input for PWM1, channel 1.
MAT0[1] — Match output for Timer 0, channel 0.
USB_SDA1/
PCAP1[1]/
MAT0[1]
O
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
13 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 4.
Symbol
Pin description …continued
Ball
Type
Description
P1[30]/
USB_PWRD2/
VBUS/AD0[4]
K3[2]
I/O
P1[30] — General purpose digital input/output pin.
USB_PWRD2 — Power Status for USB port 2.
VBUS — Monitors the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.
AD0[4] — A/D converter 0, input 4.
I
I
I
P1[31]/
USB_OVRCR2/
SCK1/AD0[5]
K2[2]
I/O
I
P1[31] — General purpose digital input/output pin.
USB_OVRCR2 — Over-Current status for USB port 2.
SCK1 — Serial Clock for SSP1.
I/O
I
AD0[5] — A/D converter 0, input 5.
P2[0] to P2[31]
I/O
Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 2 pins depends upon the pin function selected via the Pin
Connect block.
Pins P2[14:15], P2[22:23], P[26:27] and P2[30:31] are not available.
P2[0] — General purpose digital input/output pin.
PWM1[1] — Pulse Width Modulator 1, channel 1 output.
TXD1 — Transmitter output for UART1.
P2[0]/PWM1[1]/
TXD1/
TRACECLK
D12[1]
C14[1]
E11[1]
E13[1]
E14[1]
F12[1]
I/O
O
O
O
I/O
O
I
TRACECLK — Trace Clock.
P2[1]/PWM1[2]/
RXD1/
PIPESTAT0
P2[1] — General purpose digital input/output pin.
PWM1[2] — Pulse Width Modulator 1, channel 2 output.
RXD1 — Receiver input for UART1.
O
I/O
O
I
PIPESTAT0 — Pipeline Status, bit 0.
P2[2]/PWM1[3]/
CTS1/
PIPESTAT1
P2[2] — General purpose digital input/output pin.
PWM1[3] — Pulse Width Modulator 1, channel 3 output.
CTS1 — Clear to Send input for UART1.
O
I/O
O
I
PIPESTAT1 — Pipeline Status, bit 1.
P2[3]/PWM1[4]/
DCD1/
PIPESTAT2
P2[3] — General purpose digital input/output pin.
PWM1[4] — Pulse Width Modulator 1, channel 4 output.
DCD1 — Data Carrier Detect input for UART1.
PIPESTAT2 — Pipeline Status, bit 2.
O
I/O
O
I
P2[4]/PWM1[5]/
DSR1/
TRACESYNC
P2[4] — General purpose digital input/output pin.
PWM1[5] — Pulse Width Modulator 1, channel 5 output.
DSR1 — Data Set Ready input for UART1.
TRACESYNC — Trace Synchronization.
O
I/O
O
O
O
I/O
I
P2[5]/PWM1[6]/
DTR1/
TRACEPKT0
P2[5] — General purpose digital input/output pin.
PWM1[6] — Pulse Width Modulator 1, channel 6 output.
DTR1 — Data Terminal Ready output for UART1.
TRACEPKT0 — Trace Packet, bit 0.
P2[6]/PCAP1[0]/RI1/ F13[1]
TRACEPKT1
P2[6] — General purpose digital input/output pin.
PCAP1[0] — Capture input for PWM1, channel 0.
RI1 — Ring Indicator input for UART1.
I
O
TRACEPKT1 — Trace Packet, bit 1.
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
14 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 4.
Symbol
Pin description …continued
Ball
G11[1]
Type
I/O
I
Description
P2[7]/RD2/
RTS1/
TRACEPKT2
P2[7] — General purpose digital input/output pin.
RD2 — CAN2 receiver input.
O
RTS1 — Request to Send output for UART1.
TRACEPKT2 — Trace Packet, bit 2.
O
P2[8]/TD2/
TXD2/
TRACEPKT3
G14[1]
I/O
O
P2[8] — General purpose digital input/output pin.
TD2 — CAN2 transmitter output.
O
TXD2 — Transmitter output for UART2.
TRACEPKT3 — Trace Packet, bit 3.
O
P2[9]/
USB_CONNECT1/
RXD2/
H11[1]
I/O
O
P2[9] — General purpose digital input/output pin.
USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an
external 1.5 k resistor under the software control. Used with the SoftConnect
USB feature.
EXTIN0
I
RXD2 — Receiver input for UART2.
I
EXTIN0 — External Trigger Input.
P2[10]/EINT0
M13[6]
M12[6]
I/O
P2[10] — General purpose digital input/output pin.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take
over control of the part after a reset.
I
EINT0 — External interrupt 0 input.
P2[11]/EINT1/
MCIDAT1/
I2STX_CLK
I/O
I
P2[11] — General purpose digital input/output pin.
EINT1 — External interrupt 1 input.
I/O
I/O
MCIDAT1 — Data line 1 for SD/MMC interface.
I2STX_CLK — Transmit Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
P2[12]/EINT2/
MCIDAT2/
I2STX_WS
N14[6]
I/O
I
P2[12] — General purpose digital input/output pin.
EINT2 — External interrupt 2 input.
I/O
I/O
MCIDAT2 — Data line 2 for SD/MMC interface.
I2STX_WS — Transmit Word Select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I2S-bus specification.
P2[13]/EINT3/
MCIDAT3/
I2STX_SDA
M11[6]
I/O
I
P2[13] — General purpose digital input/output pin.
EINT3 — External interrupt 3 input.
I/O
I/O
MCIDAT3 — Data line 3 for SD/MMC interface.
I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
P2[16]/CAS
P2[17]/RAS
P9[1]
P11[1]
P3[1]
N5[1]
I/O
O
P2[16] — General purpose digital input/output pin.
CAS — LOW active SDRAM Column Address Strobe.
P2[17] — General purpose digital input/output pin.
RAS — LOW active SDRAM Row Address Strobe.
P2[18] — General purpose digital input/output pin.
CLKOUT0 — SDRAM clock 0.
I/O
O
P2[18]/
CLKOUT0
I/O
O
P2[19]/
CLKOUT1
I/O
O
P2[19] — General purpose digital input/output pin.
CLKOUT1 — SDRAM clock 1.
LPC2458
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Single-chip 16-bit/32-bit micro
Table 4.
Pin description …continued
Symbol
Ball
P6[1]
Type
I/O
O
Description
P2[20]/DYCS0
P2[20] — General purpose digital input/output pin.
DYCS0 — SDRAM chip select 0.
P2[21]/DYCS1
N8[1]
P1[1]
P2[1]
M2[1]
L1[1]
I/O
O
P2[21] — General purpose digital input/output pin.
DYCS1 — SDRAM chip select 1.
P2[24]/
CKEOUT0
I/O
O
P2[24] — General purpose digital input/output pin.
CKEOUT0 — SDRAM clock enable 0.
P2[25]/
CKEOUT1
I/O
O
P2[25] — General purpose digital input/output pin.
CKEOUT1 — SDRAM clock enable 1.
P2[28]/
DQMOUT0
I/O
O
P2[28] — General purpose digital input/output pin.
DQMOUT0 — Data mask 0 used with SDRAM and static devices.
P2[29] — General purpose digital input/output pin.
DQMOUT1 — Data mask 1 used with SDRAM and static devices.
P2[29]/
DQMOUT1
I/O
O
P3[0] to P3[31]
I/O
Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 3 pins depends upon the pin function selected via the Pin
Connect block.
Pins P3[16:22] and P3[27:31] are not available.
P3[0] — General purpose digital input/output pin.
D0 — External memory data line 0.
P3[0]/D0
P3[1]/D1
P3[2]/D2
P3[3]/D3
P3[4]/D4
P3[5]/D5
P3[6]/D6
P3[7]/D7
P3[8]/D8
P3[9]/D9
P3[10]/D10
P3[11]/D11
D6[1]
E6[1]
A2[1]
G5[1]
D3[1]
E3[1]
F4[1]
G3[1]
A6[1]
A4[1]
B3[1]
B2[1]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P3[1] — General purpose digital input/output pin.
D1 — External memory data line 1.
P3[2] — General purpose digital input/output pin.
D2 — External memory data line 2.
P3[3] — General purpose digital input/output pin.
D3 — External memory data line 3.
P3[4] — General purpose digital input/output pin.
D4 — External memory data line 4.
P3[5] — General purpose digital input/output pin.
D5 — External memory data line 5.
P3[6] — General purpose digital input/output pin.
D6 — External memory data line 6.
P3[7] — General purpose digital input/output pin.
D7 — External memory data line 7.
P3[8] — General purpose digital input/output pin.
D8 — External memory data line 8.
P3[9] — General purpose digital input/output pin.
D9 — External memory data line 9.
P3[10] — General purpose digital input/output pin.
D10 — External memory data line 10.
P3[11] — General purpose digital input/output pin.
D11 — External memory data line 11.
LPC2458
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Single-chip 16-bit/32-bit micro
Table 4.
Pin description …continued
Symbol
Ball
A1[1]
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
P3[12]/D12
P3[12] — General purpose digital input/output pin.
D12 — External memory data line 12.
P3[13]/D13
P3[14]/D14
P3[15]/D15
C1[1]
F1[1]
G4[1]
M4[1]
P3[13] — General purpose digital input/output pin.
D13 — External memory data line 13.
P3[14] — General purpose digital input/output pin.
D14 — External memory data line 14.
P3[15] — General purpose digital input/output pin.
D15 — External memory data line 15.
P3[23]/CAP0[0]/
PCAP1[0]
P3[23] — General purpose digital input/output pin.
CAP0[0] — Capture input for Timer 0, channel 0.
PCAP1[0] — Capture input for PWM1, channel 0.
P3[24] — General purpose digital input/output pin.
CAP0[1] — Capture input for Timer 0, channel 1.
PWM1[1] — Pulse Width Modulator 1, output 1.
P3[25] — General purpose digital input/output pin.
MAT0[0] — Match output for Timer 0, channel 0.
PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26] — General purpose digital input/output pin.
MAT0[1] — Match output for Timer 0, channel 1.
PWM1[3] — Pulse Width Modulator 1, output 3.
I
P3[24]/CAP0[1]/
PWM1[1]
N3[1]
M3[1]
K7[1]
I/O
I
O
P3[25]/MAT0[0]/
PWM1[2]
I/O
O
O
P3[26]/MAT0[1]/
PWM1[3]
I/O
O
O
P4[0] to P4[31]
I/O
Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 4 pins depends upon the pin function selected via the Pin
Connect block.
Pins P4[20:23] are not available.
P4[0]/A0
P4[1]/A1
P4[2]/A2
P4[3]/A3
P4[4]/A4
P4[5]/A5
P4[6]/A6
P4[7]/A7
L6[1]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P4[0] — General purpose digital input/output pin.
A0 — External memory address line 0.
M7[1]
M8[1]
K9[1]
P4[1] — General purpose digital input/output pin.
A1 — External memory address line 1.
P4[2] — General purpose digital input/output pin.
A2 — External memory address line 2.
P4[3] — General purpose digital input/output pin.
A3 — External memory address line 3.
P13[1]
H10[1]
K10[1]
K12[1]
P4[4] — General purpose digital input/output pin.
A4 — External memory address line 4.
P4[5] — General purpose digital input/output pin.
A5 — External memory address line 5.
P4[6] — General purpose digital input/output pin.
A6 — External memory address line 6.
P4[7] — General purpose digital input/output pin.
A7 — External memory address line 7.
LPC2458
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Single-chip 16-bit/32-bit micro
Table 4.
Symbol
P4[8]/A8
Pin description …continued
Ball
J11[1]
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
P4[8] — General purpose digital input/output pin.
A8 — External memory address line 8.
P4[9]/A9
H12[1]
G12[1]
F11[1]
F10[1]
B14[1]
E8[1]
P4[9] — General purpose digital input/output pin.
A9 — External memory address line 9.
P4[10]/A10
P4[11]/A11
P4[12]/A12
P4[13]/A13
P4[14]/A14
P4[15]/A15
P4[16]/A16
P4[17]/A17
P4[18]/A18
P4[19]/A19
P4[24]/OE
P4[25]/WE
P4[26]/BLS0
P4[27]/BLS1
P4[10] — General purpose digital input/output pin.
A10 — External memory address line 10.
P4[11] — General purpose digital input/output pin.
A11 — External memory address line 11.
P4[12] — General purpose digital input/output pin.
A12 — External memory address line 12.
P4[13] — General purpose digital input/output pin.
A13 — External memory address line 13.
P4[14] — General purpose digital input/output pin.
A14 — External memory address line 14.
C10[1]
N12[1]
N13[1]
P14[1]
M14[1]
C8[1]
P4[15] — General purpose digital input/output pin.
A15 — External memory address line 15.
P4[16] — General purpose digital input/output pin.
A16 — External memory address line 16.
P4[17] — General purpose digital input/output pin.
A17 — External memory address line 17.
P4[18] — General purpose digital input/output pin.
A18 — External memory address line 18.
P4[19] — General purpose digital input/output pin.
A19 — External memory address line 19.
P4[24] — General purpose digital input/output pin.
OE — LOW active Output Enable signal.
D9[1]
I/O
O
P4[25] — General purpose digital input/output pin.
WE — LOW active Write Enable signal.
K13[1]
F14[1]
D10[1]
I/O
O
P4[26] — General purpose digital input/output pin.
BLS0 — LOW active Byte Lane select signal 0.
P4[27] — General purpose digital input/output pin.
BLS1 — LOW active Byte Lane select signal 1.
P4[28] — General purpose digital input/output pin.
MAT2[0] — Match output for Timer 2, channel 0.
TXD3 — Transmitter output for UART3.
I/O
O
P4[28]/MAT2[0]/
TXD3
I/O
O
O
P4[29]/MAT2[1]/
RXD3
B9[1]
C7[1]
I/O
O
P4[29] — General purpose digital input/output pin.
MAT2[1] — Match output for Timer 2, channel 1.
RXD3 — Receiver input for UART3.
I
P4[30]/CS0
I/O
O
P4[30] — General purpose digital input/output pin.
CS0 — LOW active Chip Select 0 signal.
LPC2458
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Product data sheet
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Single-chip 16-bit/32-bit micro
Table 4.
Pin description …continued
Symbol
Ball
E7[1]
Type
I/O
O
Description
P4[31]/CS1
P4[31] — General purpose digital input/output pin.
CS1 — LOW active Chip Select 1 signal.
ALARM
H5[7]
O
ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC
alarm is generated.
USB_D2
DBGEN
TDO
N2
I/O
USB_D2 — USB port 2 bidirectional D line.
DBGEN — JTAG interface control signal. Also used for boundary scan.
TDO — Test Data Out for JTAG interface.
E5[1][8]
B1[1][9]
C3[1][8]
C2[1][8]
D4[1][8]
D2[1][9]
I
O
I
TDI
TDI — Test Data In for JTAG interface.
TMS
I
TMS — Test Mode Select for JTAG interface.
TRST
TCK
I
TRST — Test Reset for JTAG interface.
TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the
I
CPU clock (CCLK) for the JTAG interface to operate.
RTCK
C4[1][8]
I/O
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to
operate as Trace port after reset.
RSTOUT
RESET
H2
O
I
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2458 being in
Reset state.
J1[10]
external reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1
XTAL2
RTCX1
RTCX2
VSSIO
L2[7][11]
K4[7][11]
J2[7][12]
J3[7][12]
I
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
O
I
Input to the RTC oscillator circuit.
O
I
Output from the RTC oscillator circuit.
H4, P4,
L9, L13,
G13,
ground: 0 V reference for the digital IO pins.
D13,
C11,
B4[13]
VSSCORE
VSSA
H3, L8,
A10[13]
F3[14]
I
I
I
ground: 0 V reference for the core.
analog ground: 0 V reference. This should nominally be the same voltage as
VSSIO/VSSCORE, but should be isolated to minimize noise and error.
VDD(3V3)
E2, L4,
K8, L11,
J14, E12,
E10,
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
C5[15]
n.c.
H1, L12,
G10[16]
I
I
not connected pins: These pins must be left unconnected (floating).
VDD(DCDC)(3V3)
G1, N9,
E9[17]
3.3 V DC-to-DC converter supply voltage: This is the power supply for the
on-chip DC-to-DC converter.
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Single-chip 16-bit/32-bit micro
Table 4.
Symbol
VDDA
Pin description …continued
Ball
Type
Description
F2[18]
I
analog 3.3 V pad supply voltage: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. This voltage is used
to power the ADC and DAC.
VREF
VBAT
G2[18]
I
I
ADC reference: This should be nominally the same voltage as VDD(3V3) but
should be isolated to minimize noise and error. The level on this pin is used as a
reference for ADC and DAC.
K1[18]
RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7] Pad provides special analog functionality.
[8] This pin has a built-in pull-up resistor.
[9] This pin has no built-in pull-up and no built-in pull-down resistor.
[10] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
[12] If the RTC is not used, these pins can be left floating.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
[15] Pad provides special analog functionality.
[16] Pad provides special analog functionality.
[17] Pad provides special analog functionality.
[18] Pad provides special analog functionality.
7. Functional description
7.1 Architectural overview
The LPC2458 microcontroller consists of an ARM7TDMI-S CPU with emulation support,
the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip
memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external
memory, and the AMBA APB for connection to other on-chip peripheral functions. The
microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte
order.
The LPC2458 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the VIC, GPDMA controller, and EMC.
LPC2458
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The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,
and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2
are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB. The
AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a
2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is
allocated a 16 kB address space within the APB address space.
The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers
high performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed complex
instruction set computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• the standard 32-bit ARM set
• a 16-bit Thumb set
The Thumb set’s 16-bit instruction length allows it to approach higher density compared to
standard ARM code while retaining most of the ARM’s performance.
7.2 On-chip flash programming memory
The LPC2458 incorporates 512 kB flash memory system. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port (UART0). The
application program may also erase and/or program the flash while the application is
running, allowing a great degree of flexibility for data storage field and firmware upgrades.
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at speeds of 72 MHz.
LPC2458
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Single-chip 16-bit/32-bit micro
7.3 On-chip SRAM
The LPC2458 includes a SRAM memory of 64 kB reserved for the ARM processor
exclusive use. This RAM may be used for code and/or data storage and may be accessed
as 8 bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM
associated with the second AHB can be used both for data and code storage. The 2 kB
RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and
retains the content in the absence of the main power supply.
7.4 Memory map
The LPC2458 memory map incorporates several distinct regions as shown in Table 5 and
Figure 3.
In addition, the CPU interrupt vectors may be remapped to allow them to reside in either
flash memory (default), boot ROM, or SRAM (see Section 7.26.6).
Table 5.
LPC2458 memory usage and details
Address range General use
Address range details and description
0x0000 0000 to on-chip
0x0000 0000 to 0x0007 FFFF
flash memory (512 kB)
0x3FFF FFFF
non-volatile
memory and fast
I/O
0x3FFF C000 to 0x3FFF FFFF fast GPIO registers
0x4000 0000 to on-chip RAM
0x7FFF FFFF
0x4000 0000 to 0x4000 FFFF
RAM (64 kB)
0x7FE0 0000 to 0x7FE0 3FFF Ethernet RAM (16 kB)
0x7FD0 0000 to 0x7FD0 3FFF USB RAM (16 kB)
0x8000 0000 to off-chip memory two static memory banks, 1 MB each
0xBFFF FFFF
0x8000 0000 to 0x800F FFFF
0x8100 0000 to 0x810F FFFF
static memory bank 0
static memory bank 1
two dynamic memory banks, 256 MB each
0xA000 0000 to 0xAFFF FFFF dynamic memory bank 0
0xB000 0000 to 0xBFFF FFFF dynamic memory bank 1
0xE000 0000 to APB peripherals 36 peripheral blocks, 16 kB each
0xEFFF FFFF
0xF000 0000 to AHB peripherals
0xFFFF FFFF
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Single-chip 16-bit/32-bit micro
4.0 GB
0xFFFF FFFF
0xF000 0000
AHB PERIPHERALS
APB PERIPHERALS
3.75 GB
3.5 GB
0xE000 0000
0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
0xBFFF FFFF
EXTERNAL STATIC AND DYNAMIC MEMORY
2.0 GB
0x8000 0000
0x7FFF FFFF
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
RESERVED ADDRESS SPACE
ON-CHIP STATIC RAM
SPECIAL REGISTERS
1.0 GB
0x4000 0000
0x3FFF FFFF
0x3FFF 8000
RESERVED ADDRESS SPACE
ON-CHIP NON-VOLATILE MEMORY
0.0 GB
0x0000 0000
002aad657
Fig 3. LPC2458 memory map
7.5 Interrupt controller
The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast
Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be
programmed as FIQ or vectored IRQ types. The programmable assignment scheme
means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.
FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs
the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ
latency is achieved when only one request is classified as FIQ, because then the FIQ
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Single-chip 16-bit/32-bit micro
service routine can simply start dealing with that device. But if more than one request is
assigned to the FIQ class, the FIQ service routine can read a word from the VIC that
identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a
programmable interrupt priority. When more than one interrupt is assigned the same
priority and occur simultaneously, the one connected to the lowest numbered VIC channel
will be serviced first.
The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the
ARM processor. The IRQ service routine can start by reading a register from the VIC and
jumping to the address supplied by that register.
7.5.1 Interrupt sources
Each peripheral device has one interrupt line connected to the VIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both. Such
interrupt request coming from port 0 and/or port 2 will be combined with the EINT3
interrupt requests.
7.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.7 External memory controller
The LPC2458 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering
support for asynchronous static memory devices such as RAM, ROM, and flash. In
addition, it can be used as an interface with off-chip memory-mapped devices and
peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
peripheral.
7.7.1 Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8/16 data and 20 address lines wide static memory support.
• 16 bit wide chip select SDRAM memory support.
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• Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Two chip selects for synchronous memory and two chip selects for static memory
devices.
• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, and 16 data bits per device.
• Separate reset domains allow auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
7.8 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2458
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
7.8.1 Features
• Two DMA channels. Each channel can support a unidirectional transfer.
• The GPDMA can transfer data between the 16 kB SRAM, external memory, and
peripherals such as the SD/MMC, two SSPs, and the I2S interface.
• Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time, the channel with the
highest priority is serviced first.
• AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
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• One AHB master for transferring data. This interface transfers data when a DMA
request goes active.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
• Internal four-word FIFO per channel.
• Supports 8-bit, 16-bit, and 32-bit wide transactions.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be
masked.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.9 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC2458 use accelerated GPIO functions:
• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All GPIO registers are byte and half-word addressable.
• Entire port value can be written in one instruction.
Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an
analog input/output can be programmed to generate an interrupt on a rising edge, a falling
edge, or both. The edge detection is asynchronous, so it may operate when clocks are not
present such as during Power-down mode. Each enabled interrupt can be used to wake
the chip up from Power-down mode.
7.9.1 Features
• Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• Backward compatibility with other earlier devices is maintained with legacy port 0 and
port 1 registers appearing at the original addresses on the APB.
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7.10 Ethernet
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access
the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic
in the LPC2458 takes place on a different AHB subsystem, effectively separating Ethernet
activity from the rest of the system. The Ethernet DMA can also access off-chip memory
via the EMC, as well as the SRAM located on another AHB. However, using memory
other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to
memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
7.10.1 Features
• Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
• Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
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• Physical interface:
– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
7.11 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The Host Controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
Host Controller.
The LPC2458 USB interface includes a device, Host, and OTG Controller. Details on
typical USB interfacing solutions can be found in Section 14.1 “Suggested USB interface
solutions” on page 65
7.11.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host Controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.11.1.1 Features
• Fully compliant with USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• While USB is in the Suspend mode, LPC2458 can enter one of the reduced power
modes and wake up on USB activity.
• Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
• Allows dynamic switching between CPU-controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.11.2 USB Host Controller
The Host Controller enables full- and low-speed data exchange with USB devices
attached to the bus. It consists of a register interface, a serial interface engine and a DMA
controller. The register interface complies with the OHCI specification.
7.11.2.1 Features
• OHCI compliant.
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• Two downstream ports.
• Supports per-port power switching.
7.11.3 USB OTG Controller
USB OTG is a supplement to the USB 2.0 specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the Host Controller, device controller, and a master-only
I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface
controls an external OTG transceiver.
7.11.3.1 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.12 CAN controller and acceptance filters
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router between two of CAN buses in industrial
or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.12.1 Features
• Two CAN controllers and buses.
• Data rates to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.
• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
• FullCAN messages can generate interrupts.
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7.13 10-bit ADC
The LPC2458 contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.13.1 Features
• 10-bit successive approximation ADC
• Input multiplexing among 8 pins
• Power-down mode
• Measurement range 0 V to Vi(VREF)
• 10-bit conversion time 2.44 s
• Burst conversion mode for single or multiple inputs
• Optional conversion on transition of input pin or Timer Match signal
• Individual result registers for each ADC channel to reduce interrupt overhead
7.14 10-bit DAC
The DAC allows the LPC2458 to generate a variable analog output. The maximum output
value of the DAC is Vi(VREF)
.
7.14.1 Features
• 10-bit DAC
• Resistor string architecture
• Buffered output
• Power-down mode
• Selectable output drive
7.15 UARTs
The LPC2458 contains four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.15.1 Features
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
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• UART3 includes an IrDA mode to support infrared communication.
7.16 SPI serial I/O controller
The LPC2458 contains one SPI controller. SPI is a full duplex serial interface designed to
handle multiple masters and slaves connected to a given bus. Only a single master and a
single slave can communicate on the interface during a given data transfer. During a data
transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave
always sends 8 bits to 16 bits of data to the master.
7.16.1 Features
• Compliant with SPI specification
• Synchronous, Serial, Full Duplex Communication
• Combined SPI master and slave
• Maximum data bit rate of one eighth of the input clock rate
• 8 bits to 16 bits per transfer
7.17 SSP serial I/O controller
The LPC2458 contains two SSP controllers. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the
bus. Only a single master and a single slave can communicate on the bus during a given
data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of
data flowing from the master to the slave and from the slave to the master. In practice,
often only one of these data flows carries meaningful data.
7.17.1 Features
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave
mode) of the input clock rate
• DMA transfers supported by GPDMA
7.18 SD/MMC card interface
The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11.
7.18.1 Features
• The MCI interface provides all functions specific to the SD/MMC memory card. These
include the clock generation unit, power management control, and command and data
transfer.
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• Conforms to Multimedia Card Specification v2.11.
• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
• Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
• DMA supported through the GPDMA controller.
7.19 I2C-bus serial I/O controller
The LPC2458 contains three I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus and can
be controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2458 supports bit rates up to 400 kbit/s (Fast I2C-bus).
7.19.1 Features
• I2C0 is a standard I2C compliant bus interface with open-drain pins.
• I2C1 and I2C2 use standard I/O pins and do not support powering off of individual
devices connected to the same bus lines.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
7.20 I2S-bus serial I/O controllers
The I2S-bus provides a standard communication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S connection has one master, which is always the
master, and one slave. The I2S interface on the LPC2458 provides a separate transmit
and receive channel, each of which can operate as either a master or a slave.
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7.20.1 Features
• The interface has separate input/output channels each of which can operate in master
or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
• Configurable word select period in master mode (separately for I2S input and output).
• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S input and I2S output.
7.21 General purpose 32-bit timers/external event counters
The LPC2458 includes four 32-bit Timer/Counters. The Timer/Counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. The Timer/Counter also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
7.21.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
• Counter or Timer operation.
• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
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7.22 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2458. The Timer is designed to count
cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. A
dedicated match register controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, a dedicated match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
7.22.1 Features
• LPC2458 has two PWMs with the same operational features. These may be operated
in a synchronized fashion by setting them both up to run at the same rate, then
enabling both simultaneously. PWM0 acts as the master and PWM1 as the slave for
this use.
• Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).
• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
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• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
7.23 Watchdog timer (WDT)
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
7.23.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 232 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the
Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of
potential timing choices of Watchdog operation under different power reduction
conditions. It also provides the ability to run the WDT from an entirely internal source
that is not dependent on an external crystal and its associated components and
wiring, for increased reliability.
7.24 RTC and battery RAM
The RTC is a set of counters for measuring time when system power is on, and optionally
when power is off. It uses little power in Power-down and Deep power-down modes. On
the LPC2458, the RTC can be clocked by a separate 32.768 kHz oscillator or by a
programmable prescale divider based on the APB clock. The RTC is powered by its own
power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply
used by the rest of the device.
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The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power is removed, the RTC
can supply an alarm output that can be used by external hardware to restore chip power
and resume operation.
7.24.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
• Dedicated 32 kHz oscillator or programmable prescaler from APB clock.
• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
• An alarm output pin is included to assist in waking up when the chip has had power
removed to all functions except the RTC and Battery RAM.
• Periodic interrupts can be generated from increments of any field of the time registers,
and selected fractional second values. This enhancement enables the RTC to be
used as a System Timer.
• 2 kB data SRAM powered by VBAT.
• RTC and Battery RAM power supply is isolated from the rest of the chip.
7.25 Clocking and power control
7.25.1 Crystal oscillators
The LPC2458 includes three independent oscillators. These are the Main Oscillator, the
Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than
one purpose as required in a particular application. Any of the three clock sources can be
chosen by software to drive the PLL and ultimately the CPU.
Following reset, the LPC2458 will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
7.25.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is
trimmed to 1 % accuracy.
Upon power-up or any chip reset, the LPC2458 uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.25.1.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can
be boosted to a higher frequency, up to the maximum CPU operating frequency, by the
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
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PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to Section 7.25.2 for additional information.
7.25.1.3 RTC oscillator
The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the
RTC oscillator can be used to drive the PLL and the CPU.
7.25.2 PLL
The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value
‘N’, which may be in the range of 1 to 256. This input division provides a wide range of
output frequencies from the same input frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only. The program must configure and activate the PLL,
wait for the PLL to lock, then connect to the PLL as a clock source.
7.25.3 Wake-up timer
The LPC2458 begins operation at power-up and when awakened from Power-down and
Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This
allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down and Deep power-down
modes, any wake-up of the processor from Power-down modes makes use of the
Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some event caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
sufficient amplitude to drive the clock logic. The amount of time depends on many factors,
including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry
(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
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7.25.4 Power control
The LPC2458 supports a variety of power control features. There are four special modes
of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, Peripheral power control allows shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Each of the peripherals
has its own clock divider which provides even better power control.
The LPC2458 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the RTC and a small SRAM,
referred to as the Battery RAM.
7.25.4.1 Idle mode
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.25.4.2 Sleep mode
In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The
32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
The Sleep mode can be terminated and normal operation resumed by either a Reset or
certain specific interrupts that are able to function without clocks. Since all dynamic
operation of the chip is suspended, Sleep mode reduces chip power consumption to a
very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.
On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the
code execution and peripherals activities will resume after 4 cycles expire. If the main
external oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
7.25.4.3 Power-down mode
Power-down mode does everything that Sleep mode does, but also turns off the IRC
oscillator and the flash memory. This saves more power, but requires waiting for
resumption of flash operation before execution of code or data access in the flash memory
can be accomplished.
On the wake-up from Power-down mode, if the IRC was used before entering
Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire
before the code execution can then be resumed if the code was running from SRAM. In
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the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the
100 s flash start-up time. When it times out, access to the flash will be allowed. The
customers need to reconfigure the PLL and clock dividers accordingly.
7.25.4.4 Deep power-down mode
Deep power-down mode is similar to the Power-down mode, but now the on-chip
regulator that supplies power to the internal logic is also shut off. This produces the lowest
possible power consumption without removing power from the entire chip. Since the Deep
power-down mode shuts down the on-chip logic power supply, there is no register or
memory retention, and resumption of operation involves the same activities as a full chip
reset.
If power is supplied to the LPC2458 during Deep power-down mode, wake-up can be
caused by the RTC Alarm interrupt or by external Reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2458 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the Battery RAM, as long as the external power
to the VBAT pin is maintained.
7.25.4.5 Power domains
The LPC2458 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the RTC and the Battery RAM.
On the LPC2458, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the
V
DD(DCDC)(3V3) pins power the on-chip DC-to-DC converter which in turn provides power to
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and
a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-DC
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
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7.26 System control
7.26.1 Reset
Reset has four sources on the LPC2458: the RESET pin, the Watchdog reset, power-on
reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable
level, starts the Wake-up timer (see description in Section 7.25.3 “Wake-up timer”),
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the flash controller has completed its
initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.26.2 Brownout detection
The LPC2458 includes 2-stage monitoring of the voltage on the VDD(DCDC)(3V3) pins. If this
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
The second stage of low-voltage detection asserts Reset to inactivate the LPC2458 when
the voltage on the VDD(DCDC)(3V3) pins falls below 2.65 V. This Reset prevents alteration of
the flash as operation of the various elements of the chip would otherwise become
unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at
which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
7.26.3 Code security (Code Read Protection - CRP)
This feature of the LPC2458 allows user to enable different levels of security in the system
so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When
needed, CRP is invoked by programming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
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CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
7.26.4 AHB
The LPC2458 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB
SRAM.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters
with access to AHB2 are the ARM7 and the Ethernet block.
7.26.5 External interrupt inputs
The LPC2458 includes up to 68 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
7.26.6 Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM, the SRAM, or external memory. This allows code running in different memory
spaces to have control of the interrupts.
7.27 Emulation and debugging
The LPC2458 support emulation and debugging via a JTAG serial port. A trace port allows
tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface
peripherals residing on other pins are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
7.27.1 EmbeddedICE
The EmbeddedICE logic provides on-chip debug support. The debugging of the target
system requires a host computer running the debugger software and an EmbeddedICE
protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug
Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present
on the target system.
The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC
allows a program running on the target to communicate with the host debugger or another
separate host without stopping the program flow or even entering the debug state. The
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DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core.
The DCC allows the JTAG port to be used for sending and receiving data without affecting
the normal program flow. The DCC data and control registers are mapped in to addresses
in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG
interface to operate.
7.27.2 Embedded trace
Since the LPC2458 have significant amounts of on-chip memories, it is not possible to
determine how the processor core is operating simply by observing the external pins. The
ETM provides real-time trace capability for deeply embedded processor cores. It outputs
information about processor execution to a trace port. A software debugger allows
configuration of the ETM using a JTAG interface and displays the trace information that
has been captured.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
Trace Port Analyzer captures the trace information under software debugger control. The
trace port can broadcast the Instruction trace information. Instruction trace (or PC trace)
shows the flow of execution of the processor and provides a list of all the instructions that
were executed. Instruction trace is significantly compressed by only broadcasting branch
addresses as well as a set of status signals that indicate the pipeline status on a cycle by
cycle basis. Trace information generation can be controlled by selecting the trigger
resource. Trigger resources include address comparators, counters and sequencers.
Since trace information is compressed the software debugger requires a static image of
the code being executed. Self-modifying code can not be traced because of this
restriction.
7.27.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real-time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC, which is
present in the EmbeddedICE logic. The LPC2458 contain a specific configuration of
RealMonitor software programmed into the on-chip ROM memory.
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8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
VDD(3V3)
supply voltage (3.3 V)
core and external
rail
3.0
3.6
V
VDD(DCDC)(3V3) DC-to-DC converter supply voltage
(3.3 V)
3.0
3.6
V
VDDA
analog 3.3 V pad supply voltage
input voltage on pin VBAT
input voltage on pin VREF
analog input voltage
0.5
0.5
0.5
0.5
+4.6
+4.6
+4.6
+5.1
V
V
V
V
Vi(VBAT)
Vi(VREF)
VIA
for the RTC
on ADC related
pins
[2]
VI
input voltage
5 V tolerant I/O
pins; only valid
when the VDD(3V3)
supply voltage is
present
0.5
+6.0
V
[2][3]
other I/O pins
0.5
VDD(3V3)
0.5
+
V
[4]
[4]
[5]
IDD
supply current
per supply pin
per ground pin
non-operating
-
100
100
+150
1.5
mA
mA
C
ISS
ground current
-
Tstg
storage temperature
total power dissipation (per package)
65
Ptot(pack)
based on package
heat transfer, not
device power
-
W
consumption
[6]
VESD
electrostatic discharge voltage
human body
2500
+2500
V
model; all pins
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSSIO/VSSCORE
unless otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Not to exceed 4.6 V.
[4] The peak current is limited to 25 times the corresponding maximum current.
[5] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
Tj = Tamb + PD Rthj – a
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 7.
Thermal characteristics
VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tj(max)
maximum junction
temperature
-
-
125
C
Table 8.
Thermal resistance value (C/W): ±15 %
VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified
TFBGA180
ja
JEDEC (4.5 in 4 in)
0 m/s
45.5
38.3
33.8
1 m/s
2.5 m/s
8-layer (4.5 in 3 in)
0 m/s
1 m/s
2.5 m/s
jc
38
33.5
29.8
8.9
12
jb
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10. Static characteristics
Table 9.
Static characteristics
Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
Symbol
VDD(3V3)
VDD(DCDC)(3V3)
Parameter
Conditions
Min
3.0
3.0
Typ[1]
3.3
Max
3.6
Unit
V
supply voltage (3.3 V) core and external rail
DC-to-DC converter
supply voltage (3.3 V)
3.3
3.6
V
VDDA
analog 3.3 V pad
supply voltage
3.0
2.0
2.5
3.3
3.3
3.3
3.6
V
V
V
[2]
Vi(VBAT)
Vi(VREF)
input voltage on pin
VBAT
3.6
input voltage on pin
VREF
VDDA
IDD(DCDC)act(3V3) active mode DC-to-DC VDD(DCDC)(3V3) = 3.3 V;
converter supply
current (3.3 V)
Tamb = 25 C; code
while(1){}
executed from flash; no
peripherals enabled;
PCLK = CCLK
CCLK = 10 MHz
CCLK = 72 MHz
-
-
15
63
-
-
mA
mA
all peripherals enabled;
PCLK = CCLK / 8
CCLK = 10 MHz
CCLK = 72 MHz
-
-
21
92
-
-
mA
mA
all peripherals enabled;
PCLK = CCLK
CCLK = 10 MHz
CCLK = 72 MHz
-
-
27
-
-
mA
mA
125
[3]
[3]
IDD(DCDC)pd(3V3) Power-down mode
DC-to-DC converter
VDD(DCDC)(3V3) = 3.3 V;
Tamb = 25 C
supply current (3.3 V)
-
113
-
A
IDD(DCDC)dpd(3V3) Deep power-down
mode DC-to-DC
converter supply
current (3.3 V)
-
20
-
A
[4]
[3]
IBATact
IBAT
active mode battery
supply current
-
-
20
20
-
-
A
A
battery supply current Deep power-down mode
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Table 9.
Static characteristics …continued
Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Standard port pins, RESET, RTCK
IIL
LOW-level input
current
VI = 0 V; no pull-up
-
-
-
-
-
-
-
-
3
A
A
A
mA
IIH
HIGH-level input
current
VI = VDD(3V3); no pull-down
3
IOZ
Ilatch
OFF-state output
current
VO = 0 V; VO = VDD(3V3)
no pull-up/down
;
3
I/O latch-up current
(0.5VDD(3V3)) < VI <
100
(1.5VDD(3V3));
Tj < 125 C
[5][6][7]
[8]
VI
input voltage
pin configured to provide a
digital function
0
-
5.5
V
VO
output voltage
output active
0
-
-
VDD(3V3)
-
V
V
VIH
HIGH-level input
voltage
2.0
VIL
LOW-level input
voltage
-
-
0.8
V
Vhys
VOH
hysteresis voltage
0.4
-
-
-
-
V
V
[9]
[9]
HIGH-level output
voltage
IOH = 4 mA
VDD(3V3)
0.4
VOL
IOH
LOW-level output
voltage
IOL = 4 mA
-
-
-
-
-
0.4
V
[9]
HIGH-level output
current
VOH = VDD(3V3) 0.4 V
VOL = 0.4 V
4
4
-
-
mA
mA
mA
[9]
IOL
LOW-level output
current
-
[10]
IOHS
HIGH-level
VOH = 0 V
45
short-circuit output
current
[10]
[11]
IOLS
LOW-level short-circuit VOL = VDDA
output current
-
-
50
mA
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
10
15
0
50
50
0
150
85
0
A
A
A
VI = 0 V
[11]
VDD(3V3) < VI < 5 V
I2C-bus pins (P0[27] and P0[28])
VIH
HIGH-level input
voltage
0.7VDD(3V3)
-
-
-
-
V
V
VIL
LOW-level input
voltage
0.3VDD(3V3)
Vhys
VOL
hysteresis voltage
-
-
0.05VDD(3V3)
-
-
V
V
[9]
LOW-level output
voltage
IOLS = 3 mA
0.4
[12]
ILI
input leakage current VI = VDD(3V3)
VI = 5 V
-
-
2
4
A
A
10
22
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 9.
Static characteristics …continued
Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Oscillator pins
Vi(XTAL1)
input voltage on pin
XTAL1
0.5
0.5
0.5
0.5
1.8
1.8
1.8
1.8
1.95
1.95
1.95
1.95
V
V
V
V
Vo(XTAL2)
Vi(RTCX1)
Vo(RTCX2)
output voltage on pin
XTAL2
input voltage on pin
RTCX1
output voltage on pin
RTCX2
USB pins
IOZ
OFF-state output
current
0 V < VI < 3.3 V
-
-
10
A
VBUS
VDI
bus supply voltage
-
-
-
5.25
-
V
V
differential input
(D+) (D)
0.2
sensitivity voltage
VCM
differential common
mode voltage range
includes VDI range
0.8
0.8
-
-
2.5
2.0
V
V
Vth(rs)se
single-ended receiver
switching threshold
voltage
VOL
LOW-level output
voltage for
low-/full-speed
RL of 1.5 k to 3.6 V
RL of 15 k to GND
pin to GND
-
-
-
0.18
3.5
V
V
VOH
HIGH-level output
voltage (driven) for
low-/full-speed
2.8
Ctrans
ZDRV
transceiver
capacitance
-
-
-
20
pF
[13]
driver output
with 33 series resistor;
36
44.1
impedance for driver
which is not
steady state drive
high-speed capable
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages
[2] The RTC typically fails when Vi(VBAT) drops below 1.6 V.
[3] VDD(DCDC)(3V3) = 3.3 V; VDD(3V3) = 3.3 V; Vi(VBAT) = 3.3 V; Tamb = 25 C.
[4] On pin VBAT.
[5] Including voltage on outputs in 3-state mode.
[6]
VDD(3V3) supply voltages must be present.
[7] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[8] Please also see the errata note mentioned in errata sheet.
[9] Accounts for 100 mV voltage drop in all supply lines.
[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[11] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[12] To VSSIO
.
[13] Includes external resistors of 33 1 % on D+ and D.
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
10.1 Power-down mode
002aae049
4
I
DD(IO)
(μA)
2
0
V
= 3.3 V
= 3.0 V
DD(3V3)
V
DD(3V3)
−2
−4
−40
−15
10
35
60
85
temperature (°C)
Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C.
Fig 4. I/O maximum supply current IDD(IO) versus temperature in Power-down mode
002aae050
40
I
BAT
(μA)
30
V
= 3.3 V
= 3.0 V
i(VBAT)
V
i(VBAT)
20
10
0
−40
−15
10
35
60
85
temperature (°C)
VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C.
Fig 5. RTC battery maximum supply current IBAT versus temperature in Power-down
mode
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
002aae051
800
I
DD(DCDC)pd(3v3)
(μA)
600
400
200
V
= 3.3 V
= 3.0 V
DD(DCDC)(3V3)
V
DD(DCDC)(3V3)
0
−40
−15
10
35
60
85
temperature (°C)
VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C.
Fig 6. Total DC-to-DC converter supply current IDD(DCDC)pd(3V3) at different temperatures
in Power-down mode
10.2 Deep power-down mode
002aae046
300
I
DD(IO)
(μA)
200
100
0
V
V
= 3.3 V
= 3.0 V
DD(3V3)
DD(3V3)
−40
−15
10
35
60
85
temperature (°C)
VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C.
Fig 7. I/O maximum supply current IDD(IO) versus temperature in Deep power-down
mode
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
002aae047
40
I
BAT
(μA)
30
V
V
= 3.3 V
= 3.0 V
i(VBAT)
i(VBAT)
20
10
0
−40
−15
10
35
60
85
temperature (°C)
VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C
Fig 8. RTC battery maximum supply current IBAT versus temperature in Deep
power-down mode
002aae048
100
I
DD(DCDC)dpd(3v3)
(μA)
80
60
V
= 3.3 V
= 3.0 V
DD(DCDC)(3V3)
40
20
0
V
DD(DCDC)(3V3)
−40
−15
10
35
60
85
temperature (°C)
VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C.
Fig 9. Total DC-to-DC converter maximum supply current IDD(DCDC)dpd(3V3) versus
temperature in Deep power-down mode
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
10.3 Electrical pin characteristics
002aaf112
3.6
V
OH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2.0
0
8
16
24
I
(mA)
OH
Conditions: VDD(3V3) = 3.3 V; standard port pins.
Fig 10. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
002aaf111
15
I
OL
T = 85 °C
25 °C
−40 °C
(mA)
10
5
0
0
0.2
0.4
0.6
V
(V)
OL
Conditions: VDD(3V3) = 3.3 V; standard port pins.
Fig 11. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
11. Dynamic characteristics
Table 10. Dynamic characteristics
T
amb = 40 C to +85 C for commercial applications; VDD(3V3) over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
External clock
fosc
oscillator frequency
clock cycle time
clock HIGH time
clock LOW time
clock rise time
1
-
-
-
-
-
-
25
MHz
ns
Tcy(clk)
tCHCX
40
1000
Tcy(clk) 0.4
-
ns
tCLCX
Tcy(clk) 0.4
-
ns
tCLCH
-
-
5
5
ns
tCHCL
clock fall time
ns
I2C-bus pins (P0[27] and P0[28])
[3]
tf(o)
output fall time
VIH to VIL
20 + 0.1 Cb
-
-
-
ns
ns
SSP interface
tsu(SPI_MISO)
SPI_MISO set-up time
Tamb = 25 C;
measured in
SPI Master
mode; see
Figure 16
-
11
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.
t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 12. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
11.1 Internal oscillators
Table 11. Dynamic characteristic: Internal oscillators
Tamb = 40 C to +85 C; 3.0 V VDD(3V3) 3.6 V.[1]
Symbol
fosc(RC)
fi(RTC)
Parameter
Conditions
Min
3.96
-
Typ[2]
4.02
Max
4.04
-
Unit
MHz
kHz
internal RC oscillator frequency
RTC input frequency
-
-
32.768
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
11.2 I/O pins
Table 12. Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.
Symbol
Parameter
rise time
fall time
Conditions
Min
3.0
2.5
Typ
Max
Unit
ns
tr
tf
pin configured as output
pin configured as output
-
-
5.0
5.0
ns
[1] Applies to standard I/O pins and RESET pin.
11.3 USB interface
Table 13. Dynamic characteristics of USB pins
CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3),unless otherwise specified.
Symbol
Parameter
rise time
fall time
Conditions
10 % to 90 %
10 % to 90 %
tr / tf
Min
8.5
7.7
-
Typ
Max
Unit
ns
tr
-
-
-
13.8
13.7
109
tf
ns
tFRFM
differential rise and fall time
matching
%
VCRS
output signal crossover voltage
source SE0 interval of EOP
1.3
160
2
-
-
-
2.0
175
+5
V
tFEOPT
tFDEOP
see Figure 15
ns
ns
source jitter for differential transition see Figure 15
to SE0 transition
tJR1
receiver jitter to next transition
18.5
9
-
-
-
+18.5
ns
ns
ns
tJR2
receiver jitter for paired transitions
EOP width at receiver
10 % to 90 %
+9
-
[1]
[1]
tEOPR1
must reject as
EOP; see
Figure 15
40
tEOPR2
EOP width at receiver
must accept as
EOP; see
82
-
-
ns
Figure 15
[1] Characterized but not implemented as production test. Guaranteed by design.
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Product data sheet
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53 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
11.4 Flash memory
Table 14. Dynamic characteristics of flash
Tamb = 40 C to +85 C, unless otherwise specified; VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to
ground.
Symbol
Nendu
tret
Parameter
endurance
Conditions
Min
10000
10
Typ
Max
Unit
[1]
[2]
100000
-
cycles
years
years
ms
retention time
powered; < 100 cycles
-
-
unpowered; < 100 cycles
20
-
-
ter
erase time
sector or multiple
95
100
105
consecutive sectors
[2]
tprog
programming time
0.95
1
1.05
ms
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
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Product data sheet
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54 of 81
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
11.5 Static external memory interface
Table 15. Dynamic characteristics: Static external memory interface
CL = 30 pF, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Common to read and write cycles[1]
tCSLAV
CS LOW to address valid
time
0.29
0.20
2.54
ns
Read cycle parameters[1][2]
tOELAV
OE LOW to address valid
0.29
0.20
2.54
ns
time
tCSLOEL
tam
CS LOW to OE LOW time
memory access time
0.78 + Tcy(CCLK) WAITOEN 0 + Tcy(CCLK) WAITOEN
0.49 + Tcy(CCLK) WAITOEN ns
[3][4]
[5]
(WAITRD WAITOEN + 1) (WAITRD WAITOEN + 1) (WAITRD WAITOEN + 1) ns
Tcy(CCLK) 12.70
Tcy(CCLK) 9.57
Tcy(CCLK) 8.11
th(D)
data input hold time
0
-
-
ns
ns
ns
tCSHOEH CS HIGH to OE HIGH time
0.49
0.20
0
0.20
2.44
tOEHANV OE HIGH to address invalid
time
0.20
tOELOEH OE LOW to OE HIGH time
0.59 + (WAITRD
0 + (WAITRD WAITOEN + 0.10 + (WAITRD
WAITOEN + 1) Tcy(CCLK)
1) Tcy(CCLK)
WAITOEN + 1) Tcy(CCLK)
tBLSLAV
BLS LOW to address valid
time
0.39
0.88
0
2.54
0.68
ns
ns
tCSHBLSH CS HIGH to BLS HIGH time
0.49
Write cycle parameters[1][6]
tCSLWEL
CS LOW to WE LOW time
0.88 + Tcy(CCLK) (1 +
0.10 + Tcy(CCLK) (1 +
0.20 + Tcy(CCLK) (1 +
ns
WAITWEN)
WAITWEN)
WAITWEN)
tCSLBLSL CS LOW to BLS LOW time
0.88
0.68
0
0.49
0.98
5.86
4.79
ns
ns
ns
ns
tWELDV
tCSLDV
WE LOW to data valid time
CS LOW to data valid time
2.54
2.64
[3]
[3]
[3]
tWELWEH WE LOW to WE HIGH time
0.78 + Tcy(CCLK)
0 + Tcy(CCLK) (WAITWR
0.10 + Tcy(CCLK)
(WAITWR WAITWEN + 1)
(WAITWR WAITWEN + 1) WAITWEN + 1)
0.88 + Tcy(CCLK) 0 + Tcy(CCLK) (WAITWR
(WAITWR WAITWEN + 3) WAITWEN + 3)
0 + Tcy(CCLK) 0.20 + Tcy(CCLK)
tBLSLBLSH BLS LOW to BLS HIGH
time
0.59 + Tcy(CCLK)
(WAITWR WAITWEN + 3)
ns
ns
tWEHANV WE HIGH to address invalid
time
2.74 + Tcy(CCLK)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 15. Dynamic characteristics: Static external memory interface …continued
CL = 30 pF, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[3]
[3]
[3]
tWEHDNV WE HIGH to data invalid
time
0.78 + Tcy(CCLK)
2.54 + Tcy(CCLK)
5.96 + Tcy(CCLK)
ns
tBLSHANV BLS HIGH to address
invalid time
0.29
0.20
2.54
2.54
5.37
ns
ns
tBLSHDNV BLS HIGH to data invalid
time
0
[1] VOH = 2.5 V, VOL = 0.2 V.
[2] VIH = 2.5 V, VIL = 0.5 V.
[3]
T .
cy(CCLK) = 1⁄CCLK
[4] Latest of address valid, CS LOW, OE LOW to data valid.
[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.
[6] Byte lane state bit (PB) = 1.
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
11.6 Dynamic external memory interface
Table 16. Dynamic characteristics: Dynamic external memory interface
CL = 30 pF, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, EMC Dynamic Read Config Register = 0x0
(RD = 00)
Symbol
Common
td(SV)
Parameter
Conditions
Min
Typ
Max
Unit
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
chip select valid delay time
chip select hold time
-
1.05
1.02
1.51
1.51
0.98
0.97
0.84
0.84
0.95
1
1.76
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(S)
0.1
-
-
td(RASV)
th(RAS)
td(CASV)
th(CAS)
td(WV)
th(W)
row address strobe valid delay time
row address strobe hold time
column address strobe valid delay time
column address strobe hold time
write valid delay time
1.95
0.5
-
-
1.27
0.1
-
-
1.95
write hold time
0.1
-
-
td(GV)
output enable valid delay time
output enable hold time
1.86
th(G)
0.1
-
-
td(AV)
address valid delay time
address hold time
0.87
0.81
1.95
-
th(A)
0.1
Read cycle parameters
tsu(D) data input set-up time
th(D) data input hold time
Write cycle parameters
td(QV) data output valid delay time
th(Q) data output hold time
[1]
[1]
0.51
0.57
2.24
2.41
-
-
ns
ns
[1]
[1]
-
2.65
2.61
4.36
-
ns
ns
0.49
[1] See Figure 17.
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Table 17. Dynamic characteristics: Dynamic external memory interface
CL = 30 pF on all pins, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.3 V, EMC Dynamic Read Config Register = 0x1
(RD = 01), Tcy(CCLK) = 1/CCLK
Symbol
Common
td(SV)
Parameter
Conditions
Min
Typ
Max
Unit
[1]
chip select valid delay
time
-
3 + Tcy(CCLK)
1.5 + Tcy(CCLK) ns
[1]
[1]
th(S)
chip select hold time
4 + Tcy(CCLK)
3 + Tcy(CCLK)
3 + Tcy(CCLK)
-
ns
td(RASV)
row address strobe valid
delay time
-
1.5 + Tcy(CCLK) ns
[1]
[1]
[1]
th(RAS)
td(CASV)
th(CAS)
row address strobe hold
time
3 + Tcy(CCLK)
2.3 + Tcy(CCLK)
-
ns
column address strobe
valid delay time
-
3.4 + Tcy(CCLK) 2.1 + Tcy(CCLK) ns
3 + Tcy(CCLK) ns
3.4 + Tcy(CCLK) 2.1 + Tcy(CCLK) ns
column address strobe
hold time
4 + Tcy(CCLK)
-
[1]
[1]
[1]
td(WV)
th(W)
write valid delay time
write hold time
-
4 + Tcy(CCLK)
3 + Tcy(CCLK)
3 + Tcy(CCLK)
-
ns
td(GV)
output enable valid delay
time
-
1.3 + Tcy(CCLK) ns
[1]
[1]
[1]
th(G)
td(AV)
th(A)
output enable hold time
address valid delay time
address hold time
4 + Tcy(CCLK)
2.1 + Tcy(CCLK)
-
ns
-
2.6 + Tcy(CCLK) 1.4 + Tcy(CCLK) ns
4 + Tcy(CCLK)
2.3 + Tcy(CCLK)
-
ns
Read cycle parameters
tsu(D) data input set-up time
th(D) data input hold time
Write cycle parameters
td(QV) data output valid delay
[1]
[1]
2.6 + Tcy(CCLK) 1.5 + Tcy(CCLK)
2.6 + Tcy(CCLK) 1.3 + Tcy(CCLK)
-
-
ns
ns
[1]
[1]
-
2.6 + Tcy(CCLK)/2 4.8 + Tcy(CCLK)/2 ns
time
th(Q)
data output hold time
3.8 + Tcy(CCLK) 3.4 + Tcy(CCLK)
-
ns
[1] See Figure 17.
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Product data sheet
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LPC2458
NXP Semiconductors
11.7 Timing
Single-chip 16-bit/32-bit micro
t
t
CSHOEH
CSLAV
CS
addr
data
t
t
h(D)
am
t
CSLOEL
t
t
OEHANV
OELAV
t
OELOEH
OE
t
CSHBLSH
t
BLSLAV
BLS
002aad955
Fig 13. External memory read access
CS
t
CSLAV
t
WELWEH
t
CSLWEL
t
BLSLBLSH
BLS/WE
addr
t
WEHANV
t
t
WELDV
CSLBLSL
t
BLSHANV
t
WEHDNV
t
CSLDV
t
BLSHDNV
data
OE
002aad956
Fig 14. External memory write access
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Product data sheet
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LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
T
PERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: t
FEOPT
differential data to
SE0/EOP skew
n × T
+ t
PERIOD
FDEOP
receiver EOP width: t
, t
EOPR1 EOPR2
002aab561
Fig 15. Differential data-to-EOP transition skew and EOP width
shifting edges
SCK
sampling edges
MOSI
MISO
t
su(SPI_MISO)
002aad326
Fig 16. MISO line set-up time in SSP Master mode
reference
clock
t
t
h(XXX)
d(XXX)
output signal (O)
t
t
su(D)
h(D)
input signal (I)
002aad636
Fig 17. Signal timing
LPC2458
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Single-chip 16-bit/32-bit micro
12. ADC electrical characteristics
Table 18. ADC static characteristics
VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
VDDA
1
Unit
V
VIA
Cia
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
[1][2][3]
[1][4]
[1][5]
[1][6]
[1][7]
[8]
ED
1
LSB
LSB
LSB
%
EL(adj)
EO
2
3
EG
gain error
0.5
4
ET
absolute error
LSB
k
Rvsi
voltage source interface
resistance
40
[1] Conditions: VSSA = 0 V, VDDA = 3.3 V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 18.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 18.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 18.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 18.
[7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 18.
[8] See Figure 19.
LPC2458
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NXP Semiconductors
Single-chip 16-bit/32-bit micro
offset
error
gain
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
(LSB
)
ideal
IA
offset error
E
O
V
− V
SSA
i(VREF)
1 LSB =
1024
002aae604
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 18. ADC characteristics
LPC2458
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Single-chip 16-bit/32-bit micro
LPC2XXX
R
vsi
20 kΩ
AD0[y]
AD0[y]
SAMPLE
3 pF
5 pF
V
EXT
V
V
SSIO, SSCORE
002aad586
Fig 19. Suggested ADC interface - LPC2458 AD0[y] pin
LPC2458
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Single-chip 16-bit/32-bit micro
13. DAC electrical characteristics
Table 19. DAC electrical characteristics
VDDA = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
1
Max
Unit
LSB
LSB
%
ED
differential linearity error
integral non-linearity
offset error
-
-
-
-
-
-
-
-
EL(adj)
EO
1.5
0.6
0.6
200
-
-
EG
gain error
-
%
CL
load capacitance
load resistance
-
pF
RL
1
k
LPC2458
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14. Application information
14.1 Suggested USB interface solutions
V
DD(3V3)
USB_UP_LED
USB_CONNECT
LPC24XX
soft-connect switch
R1
1.5 kΩ
V
BUS
R
R
= 33 Ω
= 33 Ω
S
USB-B
connector
USB_D+
S
USB_D−
V
V
SSIO, SSCORE
002aad587
Fig 20. LPC2458 USB interface on a self-powered device
V
DD(3V3)
R2
LPC24XX
R1
1.5 kΩ
USB_UP_LED
V
BUS
USB-B
connector
R
R
= 33 Ω
= 33 Ω
S
USB_D+
S
USB_D−
V
V
SSIO, SSCORE
002aad588
Fig 21. LPC2458 USB interface on a bus-powered device
LPC2458
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Single-chip 16-bit/32-bit micro
V
DD
R1
R2
R3
R4
V
BUS
RSTOUT
RESET_N
ADR/PSW
OE_N/INT_N
SPEED
ID
33 Ω
DP
V
DD
Mini-AB
33 Ω
connector
DM
ISP1302
SUSPEND
R4
R5
R6
V
SSIO,
SCL
SDA
USB_SCL1
USB_SDA1
USB_INT1
V
SSCORE
INT_N
USB_D+1
USB_D−1
V
DD
USB_UP_LED1
R7
LPC24XX
5 V
V
DD
IN
ENA
OUTA
FLAGA
LM3526-L
USB_PPWR2
USB_OVRCR2
V
USB_PWRD2
USB_D+2
BUS
33 Ω
33 Ω
D+
USB-A
connector
D−
USB_D−2
V
SSIO,
SSCORE
15 kΩ
15 kΩ
V
V
DD
USB_UP_LED2
R8
002aad589
Fig 22. LPC2458 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host
LPC2458
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Single-chip 16-bit/32-bit micro
V
DD
RSTOUT
RESET_N
OE_N/INT_N
DAT_VP
USB_TX_E1
USB_TX_DP1
USB_TX_DM1
SE0_VM
RCV
VP
USB_RCV1
V
BUS
USB_RX_DP1
USB_RX_DM1
VM
ID
V
DD
33 Ω
33 Ω
USB MINI-AB
connector
DP
DM
ISP1302
LPC24XX
ADR/PSW
SPEED
V
SSIO,
SSCORE
V
SUSPEND
USB_SCL1
USB_SDA1
USB_INT1
SCL
SDA
INT_N
V
DD
USB_UP_LED1
002aad590
Fig 23. LPC2458 USB OTG port configuration: VP_VM mode
LPC2458
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Single-chip 16-bit/32-bit micro
V
DD
USB_UP_LED1
V
SSIO,
SSCORE
V
33 Ω
33 Ω
D+
USB_D+1
USB_D−1
D−
USB-A
connector
15 kΩ
15 kΩ
V
DD
V
USB_PWRD1
USB_OVRCR1
BUS
USB_PPWR1
FLAGA
OUTA
ENA
5 V
LM3526-L
IN
LPC24XX
V
DD
USB_UP_LED2
V
DD
USB_CONNECT2
V
SSIO,
SSCORE
V
33 Ω
33 Ω
USB_D+2
D+
USB-B
connector
D−
USB_D−2
V
BUS
V
BUS
002aad595
Fig 24. LPC2458 USB OTG port configuration: USB port 2 device, USB port 1 host
LPC2458
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Single-chip 16-bit/32-bit micro
V
DD
USB_UP_LED1
V
SSIO,
SSCORE
V
33 Ω
D+
USB_D+1
33 Ω
USB_D−1
D−
USB-A
connector
15 kΩ
15 kΩ
V
DD
V
USB_PWRD1
USB_OVRCR1
BUS
USB_PPWR1
FLAGA
OUTA
ENA
5 V
V
DD
IN
LM3526-L
OUTB
LPC24XX
USB_PPWR2
ENB
FLAGB
USB_OVRCR2
USB_PWRD2
V
BUS
USB-A
connector
33 Ω
33 Ω
USB_D+2
D+
D−
USB_D−2
V
SSIO,
SSCORE
15 kΩ
15 kΩ
V
V
DD
USB_UP_LED2
002aad596
Fig 25. LPC2458 USB OTG port configuration: USB port 1 host, USB port 2 host
14.2 Crystal oscillator XTAL input and component selection
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci / (Ci + Cg). In
slave mode, a minimum of 200 mV (RMS) is needed.
LPC2xxx
XTAL1
C
i
C
g
100 pF
002aae718
Fig 26. Slave mode operation of the on-chip oscillator
LPC2458
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Single-chip 16-bit/32-bit micro
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 26), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTAL2 pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 27 and in
Table 20 and Table 21. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 27 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
LPC2xxx
L
XTAL1
XTAL2
C
L
C
P
=
XTAL
R
S
C
X2
C
X1
002aag469
Fig 27. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 20. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): low frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1/CX2
1 MHz to 5 MHz
10 pF
< 300
< 300
< 300
< 300
< 200
< 100
< 160
< 60
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
20 pF
30 pF
5 MHz to 10 MHz
10 pF
20 pF
30 pF
10 MHz to 15 MHz
15 MHz to 20 MHz
10 pF
20 pF
10 pF
< 80
LPC2458
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Single-chip 16-bit/32-bit micro
Table 21. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): high frequency mode
Fundamental oscillation Crystal load
Maximum crystal
series resistance RS
External load
capacitors CX1,
CX2
frequency FOSC
capacitance CL
15 MHz to 20 MHz
10 pF
< 180
< 100
< 160
< 80
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
39 pF, 39 pF
20 pF
20 MHz to 25 MHz
10 pF
20 pF
14.3 RTC 32 kHz oscillator component selection
LPC2xxx
L
RTCX1
RTCX2
C
L
C
P
=
32 kHz XTAL
R
S
C
X2
C
X1
002aaf495
Fig 28. RTC oscillator modes and models: oscillation mode of operation and external
crystal model used for CX1/CX2 evaluation
The RTC external oscillator circuit is shown in Figure 28. Since the feedback resistance is
integrated on chip, only a crystal, the capacitances CX1 and CX2 need to be connected
externally to the microcontroller.
Table 22 gives the crystal parameters that should be used. CL is the typical load
capacitance of the crystal and is usually specified by the crystal manufacturer. The actual
CL influences oscillation frequency. When using a crystal that is manufactured for a
different load capacitance, the circuit will oscillate at a slightly different frequency
(depending on the quality of the crystal) compared to the specified one. Therefore for an
accurate time reference it is advised to use the load capacitors as specified in Table 22
that belong to a specific CL. The value of external capacitances CX1 and CX2 specified in
this table are calculated from the internal parasitic capacitances and the CL. Parasitics
from PCB and package are not taken into account.
Table 22. Recommended values for the RTC external 32 kHz oscillator CX1/CX2 components
Crystal load capacitance Maximum crystal series
External load capacitors CX1/CX2
CL
resistance RS
11 pF
13 pF
15 pF
< 100 k
18 pF, 18 pF
22 pF, 22 pF
27 pF, 27 pF
< 100 k
< 100 k
LPC2458
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Single-chip 16-bit/32-bit micro
14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
14.5 Standard I/O pin configuration
Figure 29 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Analog input (for ADC input channels)
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
V
DD
output enable
ESD
pin configured
as digital output
driver
output
PIN
ESD
V
V
DD
SS
weak
pull-up
pull-up enable
weak
pull-down
pin configured
as digital input
pull-down enable
data input
select analog input
pin configured
as analog input
analog input
002aaf496
Fig 29. Standard I/O pin configuration with analog input
LPC2458
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Single-chip 16-bit/32-bit micro
14.6 Reset pin configuration
V
DD
V
DD
V
DD
R
pu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
V
SS
002aaf274
Fig 30. Reset pin configuration
LPC2458
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Single-chip 16-bit/32-bit micro
15. Package outline
TFBGA180: thin fine-pitch ball grid array package; 180 balls
SOT570-3
D
B
A
ball A1
index area
A
2
E
A
A
1
detail X
e
1
C
M
M
∅ v
∅ w
C
C
A
B
e
1/2 e
b
y
1
y
C
P
N
M
K
H
L
J
e
e
2
G
E
F
1/2 e
D
B
C
A
ball A1
index area
1
3
5
7
9
11
13
2
4
6
8
10
12
14
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max 1.20 0.40 0.80 0.50 12.1 12.1
nom 1.06 0.35 0.71 0.45 12.0 12.0
mm
0.8
10.4 10.4 0.15 0.05 0.12
0.1
min
0.95 0.30 0.65 0.40 11.9 11.9
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
08-07-09
10-04-15
SOT570-3
Fig 31. Package outline SOT570-3 (TFBGA180)
LPC2458
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Single-chip 16-bit/32-bit micro
16. Soldering
Footprint information for reflow soldering of TFBGA180 package
SOT570-3
Hx
P
P
Hy
see detail X
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
SL
SP
SR
occupied area
solder resist
detail X
DIMENSIONS in mm
P
SL
SP
SR
Hx
Hy
0.80
0.400 0.400 0.550 12.575 12.575
sot570-3_fr
Fig 32. Reflow soldering of the TFBGA180 package
LPC2458
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Single-chip 16-bit/32-bit micro
17. Abbreviations
Table 23. Acronym list
Acronym
ADC
AHB
AMBA
APB
Description
Analog-to-Digital Converter
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
BrownOut Detection
BOD
CAN
DAC
DCC
DMA
EOP
ETM
GPIO
IrDA
Controller Area Network
Digital-to-Analog Converter
Debug Communication Channel
Direct Memory Access
End Of Packet
Embedded Trace Macrocell
General Purpose Input/Output
Infrared Data Association
Joint Test Action Group
Media Independent Interface
Open Host Controller
JTAG
MII
OHC
OHCI
OTG
PHY
PLL
Open Host Controller Interface
On-The-Go
PHYsical Layer
Phase-Locked Loop
PWM
RMII
SD/MMC
SE0
Pulse Width Modulator
Reduced Media Independent Interface
Secure Digital/MultiMediaCard
Single Ended Zero
SPI
Serial Peripheral Interface
Synchronous Serial Interface
Synchronous Serial Port
Transistor-Transistor Logic
SSI
SSP
TTL
UART
USB
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
LPC2458
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Single-chip 16-bit/32-bit micro
18. Revision history
Table 24. Revision history
Document ID
LPC2458 v.4.1
Modifications:
Release date
20131015
Data sheet status
Change notice
Supersedes
Product data sheet
-
LPC2458 v.4
• Table 4 “Pin description”, Table note 6: Changed glitch filter spec from 5 ns to 10 ns.
• Table 10 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40.
• Table 17 “Dynamic characteristics: Dynamic external memory interface”: Changed td(QV) typ
and max.
• SOT570-2 obsolete; replaced with SOT570-3.
LPC2458 v.4
Modifications:
20110901
Product data sheet
-
LPC2458 v.3
• Table 4 “Pin description”: Updated description for USB_UP_LED1 and USB_UP_LED2.
• Table 6 “Limiting values”: Added “non-operating” to conditions column of Tstg
• Table 6 “Limiting values”: Updated Table note [5].
.
• Table 8 “Thermal resistance value (C/W): ±15 %”: Added new table.
• Table 9 “Static characteristics”: Changed Vhys typ value from 0.5VDD(3V3) to 0.05VDD(3V3)
.
• Table 14 “Dynamic characteristics of flash”: Updated table.
• Table 15 “Dynamic characteristics: Static external memory interface”: Removed “AHB clock
= 1 MHz”.
• Table 15 “Dynamic characteristics: Static external memory interface”: Swapped min/max
values for tam
.
• Table 15 “Dynamic characteristics: Static external memory interface”: Updated tWEHDNV
spec.
• Table 16 “Dynamic characteristics: Dynamic external memory interface”: Removed “AHB
clock = 1 MHz”.
• Table 17 “Dynamic characteristics: Dynamic external memory interface”: Added new table.
• Section 14.5 “Standard I/O pin configuration” Updated bullets.
LPC2458 v.3
LPC2458 v.2
LPC2458 v.1
20101005
20081125
20080623
Product data sheet
Product data sheet
Product data sheet
-
-
-
LPC2458 v.2
LPC2458 v.1
-
LPC2458
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NXP Semiconductors
Single-chip 16-bit/32-bit micro
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
78 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
19.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
79 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
21. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.19.1
7.20
7.20.1
7.21
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I2S-bus serial I/O controllers . . . . . . . . . . . . . 32
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General purpose 32-bit timers/external event
counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pulse width modulator . . . . . . . . . . . . . . . . . . 34
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Watchdog timer (WDT) . . . . . . . . . . . . . . . . . 35
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
RTC and battery RAM . . . . . . . . . . . . . . . . . . 35
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clocking and power control . . . . . . . . . . . . . . 36
Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 36
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
4.1
5
7.21.1
7.22
7.22.1
7.23
7.23.1
7.24
7.24.1
7.25
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
7
7.1
7.2
7.3
7.4
7.5
7.5.1
7.6
7.7
7.7.1
7.8
7.8.1
7.9
7.9.1
7.10
7.10.1
7.11
7.11.1
Functional description . . . . . . . . . . . . . . . . . . 20
Architectural overview . . . . . . . . . . . . . . . . . . 20
On-chip flash programming memory . . . . . . . 21
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 23
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24
Pin connect block . . . . . . . . . . . . . . . . . . . . . . 24
External memory controller. . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
General purpose DMA controller . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fast general purpose parallel I/O . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 28
USB device controller . . . . . . . . . . . . . . . . . . . 28
7.25.1
7.25.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 36
7.25.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 36
7.25.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37
7.25.2
7.25.3
7.25.4
7.25.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.25.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.25.4.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 38
7.25.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 39
7.25.4.5 Power domains . . . . . . . . . . . . . . . . . . . . . . . 39
PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 37
Power control. . . . . . . . . . . . . . . . . . . . . . . . . 38
7.26
System control . . . . . . . . . . . . . . . . . . . . . . . . 40
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Brownout detection . . . . . . . . . . . . . . . . . . . . 40
Code security (Code Read Protection - CRP) 40
AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
External interrupt inputs. . . . . . . . . . . . . . . . . 41
Memory mapping control . . . . . . . . . . . . . . . . 41
Emulation and debugging . . . . . . . . . . . . . . . 41
EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 41
Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 42
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.26.1
7.26.2
7.26.3
7.26.4
7.26.5
7.26.6
7.27
7.27.1
7.27.2
7.27.3
7.11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.11.2 USB Host Controller . . . . . . . . . . . . . . . . . . . . 28
7.11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.11.3 USB OTG Controller. . . . . . . . . . . . . . . . . . . . 29
7.11.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12
7.12.1
7.13
7.13.1
7.14
7.14.1
7.15
7.15.1
7.16
7.16.1
7.17
CAN controller and acceptance filters . . . . . . 29
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SSP serial I/O controller . . . . . . . . . . . . . . . . . 31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SD/MMC card interface . . . . . . . . . . . . . . . . . 31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I2C-bus serial I/O controller . . . . . . . . . . . . . . 32
8
9
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal characteristics . . . . . . . . . . . . . . . . . 44
10
Static characteristics . . . . . . . . . . . . . . . . . . . 45
Power-down mode. . . . . . . . . . . . . . . . . . . . . 48
Deep power-down mode . . . . . . . . . . . . . . . . 49
Electrical pin characteristics. . . . . . . . . . . . . . 51
10.1
10.2
10.3
11
Dynamic characteristics. . . . . . . . . . . . . . . . . 52
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 53
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 53
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1
11.2
11.3
11.4
7.17.1
7.18
7.18.1
7.19
continued >>
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
80 of 81
LPC2458
NXP Semiconductors
Single-chip 16-bit/32-bit micro
11.5
11.6
11.7
Static external memory interface . . . . . . . . . . 55
Dynamic external memory interface. . . . . . . . 57
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12
13
ADC electrical characteristics . . . . . . . . . . . . 61
DAC electrical characteristics . . . . . . . . . . . . 64
14
14.1
14.2
Application information. . . . . . . . . . . . . . . . . . 65
Suggested USB interface solutions . . . . . . . . 65
Crystal oscillator XTAL input and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
RTC 32 kHz oscillator component selection. . 71
XTAL and RTCX Printed Circuit Board (PCB)
layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 72
Standard I/O pin configuration . . . . . . . . . . . . 72
Reset pin configuration. . . . . . . . . . . . . . . . . . 73
14.3
14.4
14.5
14.6
15
16
17
18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 74
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 76
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 77
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 78
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 78
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 79
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 October 2013
Document identifier: LPC2458
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