LPC51U68JBD48E_技术文档

LPC51U68

32-bit ARM Cortex-M0+ MCU; 96 KB SRAM; 256 KB flash,

Crystal-less USB operation, Flexcomm Interface, 32-bit

counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC,

Temperature sensor

Rev. 1.3 — 18 May 2018

Product data sheet

1. General description

The LPC51U68 are ARM Cortex-M0+ based microcontrollers for embedded applications.

These devices include 96 KB of on-chip SRAM, 256 KB on-chip flash, full-speed USB

device interface, an I2S, three general-purpose timers, one versatile timer with PWM and

many other capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate

Timer (MRT), a Windowed Watchdog Timer (WWDT), eight flexible serial communication

peripherals (each of which can be a USART, SPIs, or I²C interface), and one 12-bit 5.0

Msamples/sec ADC, and a temperature sensor.

The LPC51U68 LQFP64 devices are pin-function compatible with LPC5410x and

LPC5411x devices in the same package/pinout versions.

2. Features and benefits

 ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz.

 Single cycle multiplier.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) with a selection of sources.

 Serial Wire Debug (SWD) with 4 breakpoints and 2 watchpoints.

 System tick timer.

 On-Chip memory:

 256 KB on-chip flash programming memory with flash accelerator and 256 Byte

page write and erase.

 Up to 96 KB total SRAM composed of up to 64 KB main SRAM, plus an additional

32 KB SRAM.

 ROM API support:

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

 ROM-based USB drivers (HID, CDC, MSC, DFU). Flash updates via USB.

 Booting from valid user code in flash, USART, SPI, and I²C.

 Legacy, Single, and Dual image boot.

LPC51U68

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

 Serial interfaces:

 Eight Flexcomm Interface serial peripherals. Each can be selected by software to

be a USART, SPI, or I²C interface. Two Flexcomm Interfaces also include an I2S

interface, for a total of 2 channel pairs. Each Flexcomm Interface includes a FIFO

that supports USART, SPI, and I²S if supported by that Flexcomm Interface. A

variety of clocking options are available to each Flexcomm Interface, and include a

shared Fractional Rate Generator.

 I²C supports Fast mode and Fast-mode Plus with data rates of up to 1 Mbit/s and

with multiple address recognition and monitor mode. Two sets of true open drain

I²C pins also support high-speed Mode (up to 3.4 Mbit/s) as a slave.

 USB 2.0 full-speed host or device controller with on-chip PHY and dedicated DMA

controller supporting crystal-less operation in device mode using software library.

See Technical note TN00035 for more details.

 Digital peripherals:

 DMA controller with 18 channels and 16 programmable triggers, able to access all

memories and DMA-capable peripherals.

 Up to 48 General-Purpose I/O (GPIO) pins. Most GPIOs have configurable

pull-up/pull-down resistors, open-drain mode, and input inverter.

 GPIO registers are located on AHB for fast access.

 Up to four GPIOs can be selected as pin interrupts (PINT), triggered by rising,

falling or both input edges.

 Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

 CRC engine.

 Analog peripherals:

 12-bit ADC with 12 input channels and with multiple internal and external trigger

inputs and sample rates of up to 5.0 MS/s. The ADC supports two independent

conversion sequences.

 Integrated temperature sensor connected to the ADC.

 Timers

 Three standard general purpose timers/counters, four of which support up to 4

capture inputs and 4 compare outputs, PWM mode, and external count input.

Specific timer events can be selected to generate DMA requests.

 One SCTimer/PWM (SCT) 8 input and 8 output functions (including capture and

match). Inputs and outputs can be routed to/from external pins and internally

to/from selected peripherals. Internally, the SCT supports 10 captures/matches, 10

events and 10 states.

 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power

domain. A timer in the RTC can be used for wake-up from all low power modes

including deep power-down, with 1 ms resolution.

 Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

 Windowed Watchdog timer (WWDT).

 Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be

used to wake up the device from most low power modes.

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Product data sheet

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 Clock generation:

 Internal FRO oscillator, factory trimmed for accuracy, that can optionally be used as

a system clock as well as other purposes. This oscillator provides a selectable 48

MHz or 96 MHz output, and a 12 MHz output (divided down from the selected

higher frequency) that can optionally be used as a system clock as well as other

purposes.

 External clock input for up to 25 MHz.

 Watchdog oscillator with a frequency range of 6 kHz to 1.5 MHz.

 32 kHz low-power RTC oscillator.

 System PLL allows CPU operation up to the maximum CPU rate without the need

for a high-frequency external clock. May be run from the internal FRO 12 MHz

output, the external clock input CLKIN, or the RTC oscillator.

 Clock output function with divider that can reflect many internal clocks.

 Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption.

 Reduced power modes: sleep mode, deep-sleep mode, and deep power-down

mode.

 Wake-up from deep-sleep mode on activity on USART, SPI, and I²C peripherals

when operating as slaves.

 Wake-up from sleep, deep-sleep and deep power-down modes from the RTC

alarm.

 The Micro-tick Timer can wake-up the device from most reduced power modes by

using the watchdog oscillator when no other on-chip resources are running, for

ultra-low power wake-up.

 Power-On Reset (POR).

 Brownout detect.

 JTAG boundary scan supported.

 Unique device serial number for identification.

 Single power supply 1.62 V to 3.6 V.

 Operating temperature range of -40°C to +105°C.

 Available as LQFP64 and LQFP48 packages.

LPC51U68

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Product data sheet

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3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC51U68JBD48

LPC51U68JBD64

LQFP48

LQFP64

plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm

plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm

SOT313-2

SOT314-2

3.1 Ordering options

Table 2.

Ordering options

Type number

Flash in KB

SRAM in KB

GPIO

SRAMX

32

SRAM0

64

Total

96

LPC51U68JBD48

LPC51U68JBD64

256

37

48

32

64

96

4. Marking

Terminal 1

index area

n

1

Terminal 1 index area

aaa-011231

aaa-015675

Fig 1. LQFP48 and LQFP64 package marking

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The LPC51U68 LQFP48 and LQFP64 packages have the following top-side marking:

• First line: LPC51U68

• Second line: JBD48

• Third line: xx xx

• Fourth line: xxxyy

• Fifth: wwxR[x]

– yyww: Date code with yy = year and ww = week.

– xR = Boot code version and device revision.

• First line: LPC51U68

• Second line: JBD64

• Third line: xxxxxxxxxxxx

• Fourth line: xxxyywwx[R]x

– yyww: Date code with yy = year and ww = week.

– xR = Boot code version and device revision.

Table 3.

Device revision table

Device revision

0A

Revision description

Initial device revision with boot code version 18.0.

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Product data sheet

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5. Block diagram

JTAG

boundary scan

Serial Wire

Debug

CLKIN

CLKOUT

RESET

USB bus

DEBUG INTERFACE

POWER-ON-RESET

BROWNOUT DETECT

INTERNAL OSCILLATOR

SYSTEM PLL

CLOCK GENERATION,

POWER CONTROL,

AND OTHER

USB FS

DEVICE

CONTROLLER

SYSTEM

DMA

CONTROLLER

ARM

CORTEX M0+

SYSTEM FUNCTIONS

FLASH

ACCELERATOR

FLASH

256 KB

BOOT AND DRIVER

ROM 32 KB

SRAMX

32 KB

SRAM0

64 KB

DMA

REGISTERS

GPIO

SCTIMER/PWM

USB

REGISTERS

FLEXCOMM Interfaces

(1)

0 THROUGH 4

CRC

ENGINE

FLEXCOMM Interfaces

(1)

5 THROUGH 7

ADC: 5 Ms/s, 12 BIT, 12 ch.

TEMPERATURE SENSOR

MULTILAYER AHB MATRIX

2x 32-BIT TIMER (TIMER 3)

ASYNC APB

BRIDGE

APB

BRIDGE 0

APB

BRIDGE 1

PMU REGISTERS

GPIO PIN INTERRUPTS

SYSTEM FUNCTIONS: CLOCKING,

RESET, POWER, FLASH, ETC.

2x 32-BIT TIMER (TIMER 0, 1)

FLASH REGISTERS

I/O CONFIGURATION

GPIO GROUP INTERRUPTS 0 AND 1

PERIPHERAL INPUT MUXES

MULTI-RATE TIMER

WATCHDOG

OSCILLATOR

WINDOWED

WATCHDOG

RTC Power Domain

MICRO TICK

TIMER

REAL TIME

CLOCK,

ALARM AND

WAKEUP

32.768 kHz

OSCILLATOR

FREQUENCY MEASUREMENT UNIT

FRACTIONAL RATE GENERATOR

aaa-028910

Fig 2. LPC51U68 Block diagram

LPC51U68

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6. Pinning information

6.1 Pinning

PIO0_14 49

32 PIO0_1

31 PIO0_0

30 PIO1_10

29 PIO1_9

28 PIO1_8

27 PIO1_7

26 PIO1_6

25 VSS

PIO0_15 50

PIO1_12 51

SWCLK/ PIO0_16 52

SWDIO/ PIO0_17 53

PIO1_13 54

VSS 55

VDD 56

LPC51U68

PIO1_14 57

PIO0_18 58

PIO0_19 59

PIO0_20 60

PIO0_21 61

PIO1_15 62

PIO0_22 63

RESET 64

24 VDD

23 VDDA

22 VREFP

21 VREFN

20 VSSA

19 PIO1_5

18 PIO1_4

17 PIO1_3

aaa-028915

Fig 3. LQFP64 Pin configuration

LPC51U68

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1

2

36

35

34

33

32

31

30

29

28

27

26

25

PIO0_23

PIO0_24

PIO0_25

PIO0_26

USB_DP

USB_DM

PIO0_29

PIO0_30

PIO0_31

PIO1_0

PIO0_13

PIO0_12

PIO0_11

PIO0_10

PIO0_9

PIO0_8

PIO0_7

PIO0_6

PIO0_5

PIO0_4

RTCXOUT

RTCXIN

3

4

5

6

LPC51U68

7

8

9

10

11

12

PIO1_1

PIO1_2

aaa-028916

Fig 4. LQFP48 Pin configuration

LPC51U68

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6.2 Pin description

On the LPC51U68, digital pins are grouped into two ports. Each digital pin may support up

to four different digital functions and one analog function, including General Purpose I/O

(GPIO).

Table 4.

Symbol

Pin description

Description

[2]

PIO0_0

31 23

PU I/O PIO0_0 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm Interface 0 USART RXD

function.

I/O FC0_RXD_SDA_MOSI — Flexcomm Interface 0: USART RXD, I2C SDA, SPI

MOSI.

I/O FC3_CTS_SDA_SSEL0 — Flexcomm Interface 3: USART CTS, I2C SDA, SPI

SSEL0.

I

CTimer0_CAP0 — 32-bit CTimer0 capture input 0.

R — Reserved.

O

SCT0_OUT3 — SCT0 output 3. PWM output 3.

[2]

PIO0_1

32 24

PU I/O PIO0_1 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm Interface 0 USART TXD

function.

I/O FC0_TXD_SCL_MISO — Flexcomm Interface 0: USART TXD, I2C SCL, SPI MISO.

I/O FC3_RTS_SCL_SSEL1 — Flexcomm Interface 3: USART RTS, I2C SCL, SPI

SSEL1.

I

CTimer0_CAP1 — 32-bit CTimer0 capture input 1.

R — Reserved.

O

SCT0_OUT1 — SCT0 output 1. PWM output 1.

[2]

PIO0_2

PIO0_3

36

37

-

PU I/O PIO0_2 — General-purpose digital input/output pin.

I/O FC0_CTS_SDA_SSEL0 — Flexcomm Interface 0: USART CTS, I2C SDA, SPI

SSEL0.

I/O FC3_SSEL3 — Flexcomm Interface 3: SPI SSEL3.

PU I/O PIO0_3 — General-purpose digital input/output pin.

I/O FC0_RTS_SCL_SSEL1 — Flexcomm Interface 0: USART RTS, I2C SCL, SPI

SSEL1.

I/O FC2_SSEL2 — Flexcomm Interface 2: SPI SSEL2.

O

CTimer1_MAT3 — 32-bit CTimer1 match output 3.

[2]

PIO0_4

38 27

PU I/O PIO0_4 — General-purpose digital input/output pin.

Remark: The state of this pin at Reset in conjunction with PIO0_31 and PIO1_6 will

determine the boot source for the part or if ISP handler is invoked. See the Boot

Process chapter in UM11071 for more details.

I/O FC0_SCK — Flexcomm Interface 0: USART or SPI clock.

I/O FC3_SSEL2 — Flexcomm Interface 3: SPI SSEL2.

I

CTimer0_CAP2 — 32-bit CTimer0 capture input 2.

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Product data sheet

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Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_5

PIO0_6

39 28

PU I/O PIO0_5 — General-purpose digital input/output pin.

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm Interface 6: USART RXD, I2C SDA,

SPI MOSI, I2S data.

O

SCT0_OUT6 — SCT0 output 6. PWM output 6.

CTimer0_MAT0 — 32-bit CTimer0 match output 0.

[2]

40 29

PU I/O PIO0_6 — General-purpose digital input/output pin.

I/O FC6_TXD_SCL_MISO_WS — Flexcomm Interface 6: USART TXD, I2C SCL, SPI

MISO, I2S WS.

R — Reserved.

O

I

CTimer0_MAT1 — 32-bit CTimer0 match output 1.

R — Reserved.

UTICK_CAP0 — Micro-tick timer capture input 0.

[2]

PIO0_7

41 30

PU I/O PIO0_7 — General-purpose digital input/output pin.

I/O FC6_SCK — Flexcomm Interface 6: USART, SPI, or I2S clock.

O

SCT0_OUT0 — SCT0 output 0. PWM output 0.

CTimer0_MAT2 — 32-bit CTimer0 match output 2.

R — Reserved.

I

CTimer0_CAP2 — 32-bit CTimer0 capture input 2.

[2]

PIO0_8

PIO0_9

43 31

PU I/O PIO0_8 — General-purpose digital input/output pin.

I/O FC2_RXD_SDA_MOSI — Flexcomm Interface 2: USART RXD, I2C SDA, SPI

MOSI.

O

SCT0_OUT1 — SCT0 output 1. PWM output 1.

CTimer0_MAT3 — 32-bit CTimer0 match output 3.

[2]

44 32

PU I/O PIO0_9 — General-purpose digital input/output pin.

I/O FC2_TXD_SCL_MISO — Flexcomm Interface 2: USART TXD, I2C SCL, SPI MISO.

O

I

SCT0_OUT2 — SCT0 output 2. PWM output 2.

CTimer3_CAP0 — 32-bit CTimer3 capture input 0.

R — Reserved.

I/O FC3_CTS_SDA_SSEL0 — Flexcomm Interface 3: USART CTS, I2C SDA, SPI

SSEL0.

[2]

PIO0_10

PIO0_11

45 33

PU I/O PIO0_10 — General-purpose digital input/output pin.

I/O FC2_SCK — Flexcomm Interface 2: USART or SPI clock.

O

SCT0_OUT3 — SCT0 output 3. PWM output 3.

CTimer3_MAT0 — 32-bit CTimer3 match output 0.

46 34

PU I/O PIO0_11 — General-purpose digital input/output pin. In ISP mode, this pin is set to

the Flexcomm 3 SPI SCK function.

I/O FC3_SCK — Flexcomm Interface 3: USART or SPI clock.

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm Interface 6: USART RXD, I2C SDA,

SPI MOSI, I2S DATA.

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Product data sheet

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Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_12

PIO0_13

47 35

PU I/O PIO0_12 — General-purpose digital input/output pin. In ISP mode, this pin is set to

the Flexcomm 3 SPI MOSI function.

I/O FC3_RXD_SDA_MOSI — Flexcomm Interface 3: USART RXD, I2C SDA, SPI

MOSI.

I/O FC6_TXD_SCL_MISO_WS — Flexcomm Interface 6: USART TXD, I2C SCL, SPI

MISO, I2S WS.

[2]

48 36

PU I/O PIO0_13 — General-purpose digital input/output pin. In ISP mode, this pin is set to

the Flexcomm 3 SPI MISO function.

I/O FC3_TXD_SCL_MISO — Flexcomm Interface 3: USART TXD, I2C SCL, SPI MISO.

O

SCT0_OUT4 — SCT0 output 4. PWM output 4.

PIO0_14/

TCK

49 37

PU I/O PIO0_14 — General-purpose digital input/output pin. In boundary scan mode: TCK

(Test Clock In). In ISP mode, this pin is set to the Flexcomm 3 SPI SSELN0 function.

I/O FC3_CTS_SDA_SSEL0 — Flexcomm Interface 3: USART CTS, I2C SDA, SPI

SSEL0.

O

SCT0_OUT5 — SCT0 output 5. PWM output 5.

R — Reserved.

I/O FC1_SCK — Flexcomm Interface 1: USART or SPI clock.

[2]

PIO0_15/

TDO

50 38

PU I/O PIO0_15 — General-purpose digital input/output pin. In boundary scan mode: TDO

(Test Data Out).

I/O FC3_RTS_SCL_SSEL1 — Flexcomm Interface 3: USART RTS, I2C SCL, SPI

SSEL1.

R — Reserved.

I/O FC4_SCK — Flexcomm Interface 4: USART or SPI clock.

PU I/O PIO0_16 — General-purpose digital input/output pin.

I/O FC3_SSEL2 — Flexcomm Interface 3: SPI SSEL2.

[2]

SWCLK/

PIO0_16

52 39

I/O FC6_CTS_SDA_SSEL0 — Flexcomm Interface 6: USART CTS, I2C SDA, SPI

SSEL0.

O

CTimer3_MAT1 — 32-bit CTimer3 match output 1.

R — Reserved.

I/O SWCLK — Serial Wire Clock. JTAG Test Clock. This is the default function after

booting.

R — Reserved.

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Table 4.

Symbol

Pin description …continued

Description

[2]

SWDIO/

PIO0_17

53 40

PU I/O PIO0_17 — General-purpose digital input/output pin.

I/O FC3_SSEL3 — Flexcomm Interface 3: SPI SSEL3.

I/O FC6_RTS_SCL_SSEL1 — Flexcomm Interface 6: USART RTS, I2C SCL, SPI

SSEL1.

O

CTimer3_MAT2 — 32-bit CTimer3 match output 2.

R — Reserved.

I/O SWDIO — Serial Wire Debug I/O. This is the default function after booting.

[2]

PIO0_18/

TRST

58 43

59 44

60 45

PU I/O PIO0_18 — General-purpose digital input/output pin. In boundary scan mode: TRST

(Test Reset).

I/O FC5_TXD_SCL_MISO — Flexcomm Interface 5: USART TXD, I2C SCL, SPI MISO.

O

SCT0_OUT0 — SCT0 output 0. PWM output 0.

CTimer0_MAT0 — 32-bit CTimer0 match output 0.

PIO0_19/

TDI

PU I/O PIO0_19 — General-purpose digital input/output pin. In boundary scan mode: TDI

(Test Data In).

I/O FC5_SCK — Flexcomm Interface 5: USART or SPI clock.

O

SCT0_OUT1 — SCT0 output 1. PWM output 1.

CTimer0_MAT1 — 32-bit CTimer0 match output 1.

PIO0_20/

TMS

PU I/O PIO0_20 — General-purpose digital input/output pin. In boundary scan mode: TMS

(Test Mode Select).

I/O FC5_RXD_SDA_MOSI — Flexcomm Interface 5: USART RXD, I2C SDA, SPI

MOSI.

I/O FC0_SCK — Flexcomm Interface 0: USART or SPI clock.

I

CTimer3_CAP0 — 32-bit CTimer3 capture input 0.

PU I/O PIO0_21 — General-purpose digital input/output pin.

CLKOUT — Clock output.

I/O FC0_TXD_SCL_MISO — Flexcomm Interface 0: USART TXD, I2C SCL, SPI MISO.

CTimer3_MAT0 — 32-bit CTimer3 match output 0.

PU I/O PIO0_22 — General-purpose digital input/output pin.

CLKIN — Clock input.

[2]

PIO0_21

PIO0_22

61 46

O

63 47

I

I/O FC0_RXD_SDA_MOSI — Flexcomm Interface 0: USART RXD, I2C SDA, SPI

MOSI.

O

CTimer3_MAT3 — 32-bit CTimer3 match output 3.

[3]

PIO0_23

1

Z

I/O PIO0_23 — General-purpose digital input/output pin. In ISP mode, this pin is set to

the Flexcomm 1 I2C SCL function.

I/O FC1_RTS_SCL_SSEL1 — Flexcomm Interface 1: USART CTS, I2C SCL, SPI

SSEL1.

R — Reserved.

I

CTimer0_CAP0 — 32-bit CTimer0 capture input 0.

R — Reserved.

UTICK_CAP1 — Micro-tick timer capture input 1.

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Product data sheet

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Table 4.

Symbol

Pin description …continued

Description

[3]

PIO0_24

PIO0_25

PIO0_26

2

Z

I/O PIO0_24 — General-purpose digital input/output pin. In ISP mode, this pin is set to

the Flexcomm 1 I2C SDA function.

I/O FC1_CTS_SDA_SSEL0 — Flexcomm Interface 1: USART CTS, I2C SDA, SPI

SSEL0.

R — Reserved.

I

CTimer0_CAP1 — 32-bit CTimer0 capture input 1.

R — Reserved.

O

CTimer0_MAT0 — 32-bit CTimer0 match output 0.

[3]

3

I/O PIO0_25 — General-purpose digital input/output pin.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm Interface 4: USART CTS, I2C SCL, SPI

SSEL1.

I/O FC6_CTS_SDA_SSEL0 — Flexcomm Interface 6: USART CTS, I2C SDA, SPI

SSEL0.

I

CTimer0_CAP2 — 32-bit CTimer0 capture input 2.

R — Reserved.

CTimer1_CAP1 — 32-bit CTimer1 capture input 1.

[3]

4

7

I/O PIO0_26 — General-purpose digital input/output pin.

I/O FC4_CTS_SDA_SSEL0 — Flexcomm Interface 4: USART CTS, I2C SDA, SPI

SSEL0.

R — Reserved.

I

CTimer0_CAP3 — 32-bit CTimer0 capture input 3.

PU I/O; PIO0_29/ADC0_0 — General-purpose digital input/output pin. ADC input channel 0

AI if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

[4]

PIO0_29/

ADC0_0

11

I/O FC1_RXD_SDA_MOSI — Flexcomm Interface 1: USART RXD, I2C SDA, SPI

MOSI.

O

SCT0_OUT2 — SCT0 output 2. PWM output 2.

CTimer0_MAT3 — 32-bit CTimer0 match output 3.

R — Reserved.

I

CTimer0_CAP1 — 32-bit CTimer0 capture input 1.

R — Reserved.

O

CTimer0_MAT1 — 32-bit CTimer0 match output 1.

[4]

PIO0_30/

ADC0_1

12

8

PU I/O; PIO0_30/ADC0_1 — General-purpose digital input/output pin. ADC input channel 1

AI if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC1_TXD_SCL_MISO — Flexcomm Interface 1: USART TXD, I2C SCL, SPI MISO.

O

SCT0_OUT3 — SCT0 output 3. PWM output 3.

CTimer0_MAT2 — 32-bit CTimer0 match output 2.

R — Reserved.

I

CTimer0_CAP2 — 32-bit CTimer0 capture input 2.

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Table 4.

Symbol

Pin description …continued

Description

[4]

PIO0_31/

ADC0_2

13

9

PU I/O; PIO0_31/ADC0_2 — General-purpose digital input/output pin. ADC input channel 2

AI

if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

Remark: This pin is also used to invoke ISP mode after device reset. Secondary

selection of boot source for ISP mode also uses PIO0_4 and PIO1_6. See the Boot

Process chapter in UM11071 for more details.

R — Reserved.

I/O FC2_CTS_SDA_SSEL0 — Flexcomm Interface 2: USART CTS, I2C SDA, SPI

SSEL0.

R — Reserved.

I

CTimer0_CAP3 — 32-bit CTimer0 capture input 3.

CTimer0_MAT3 — 32-bit CTimer0 match output 3.

O

[4]

PIO1_0/

ADC0_3

14 10

PU I/O; PIO1_0/ADC0_3 — General-purpose digital input/output pin. ADC input channel 3 if

AI

the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC2_RTS_SCL_SSEL1 — Flexcomm Interface 2: USART RTS, I2C SCL, SPI

SSEL1.

O

I

CTimer3_MAT1 — 32-bit CTimer3 match output 1.

R — Reserved.

CTimer0_CAP0 — 32-bit CTimer0 capture input 0.

[4]

PIO1_1/

ADC0_4

15 11

PU I/O; PIO1_1/ADC0_4 — General-purpose digital input/output pin. ADC input channel 4 if

AI

the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

O

SCT0_OUT4 — SCT0 output 4. PWM output 4.

I/O FC5_SSEL2 — Flexcomm Interface 5: SPI SSEL2.

I/O FC4_TXD_SCL_MISO — Flexcomm Interface 4: USART TXD, I2C SCL, SPI MISO.

PU I/O; PIO1_2/ADC0_5 — General-purpose digital input/output pin. ADC input channel 5 if

[4]

PIO1_2/

ADC0_5

16 12

AI

the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

I/O FC7_SSEL3 — Flexcomm Interface 7: SPI SSEL3.

O

SCT0_OUT5 — SCT0 output 5. PWM output 5.

I/O FC5_SSEL3 — Flexcomm Interface 5: SPI SSEL3.

I/O FC4_RXD_SDA_MOSI — Flexcomm Interface 4: USART RXD, I2C SDA, SPI

MOSI.

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Table 4.

Symbol

Pin description …continued

Description

[4]

PIO1_3/

ADC0_6

17 13

PU I/O; PIO1_3/ADC0_6 — General-purpose digital input/output pin. ADC input channel 6 if

AI

the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC7_SSEL2 — Flexcomm Interface 7: SPI SSEL2.

O

SCT0_OUT6 — SCT0 output 6. PWM output 6.

R — Reserved.

I/O FC3_SCK — Flexcomm Interface 3: USART or SPI clock.

I

CTimer0_CAP1 — 32-bit CTimer0 capture input 1.

O

USB_UP_LED — USB port 2 GoodLink LED indicator. It is LOW when the device is

configured (non-control endpoints enabled). It is HIGH when the device is not

configured or during global suspend.

[4]

PIO1_4/

ADC0_7

18 14

PU I/O; PIO1_4/ADC0_7 — General-purpose digital input/output pin. ADC input channel 7 if

AI

the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC7_RTS_SCL_SSEL1 — Flexcomm Interface 7: USART RTS, I2C SCL, SPI

SSEL1.

O

SCT0_OUT7 — SCT0 output 7. PWM output 7.

R — Reserved.

I/O FC3_TXD_SCL_MISO — Flexcomm Interface 3: USART TXD, I2C SCL, SPI MISO.

CTimer0_MAT1 — 32-bit CTimer0 match output 1.

PU I/O; PIO1_5/ADC0_8 — General-purpose digital input/output pin. ADC input channel 8 if

O

[4]

PIO1_5/

ADC0_8

19 15

AI

the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC7_CTS_SDA_SSEL0 — Flexcomm Interface 7: USART CTS, I2C SDA, SPI

SSEL0.

I

CTimer1_CAP0 — 32-bit CTimer1 capture input 0.

R — Reserved.

O

CTimer1_MAT3 — 32-bit CTimer1 match output 3.

R — Reserved.

USB_FRAME — USB start-of-frame signal derived from host signaling.

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Table 4.

Symbol

Pin description …continued

Description

[4]

PIO1_6/

ADC0_9

26 20

PU I/O; PIO1_6/ADC0_9 — General-purpose digital input/output pin. ADC input channel 9 if

AI

the DIGIMODE bit is set to 0 in the IOCON register for this pin.

Remark: This pin is also used as part of secondary selection of boot source for ISP

mode after device reset, in connection with PIO0_31 and PIO0_4. See the Boot

Process chapter in UM11071 for more details.

R — Reserved.

I/O FC7_SCK — Flexcomm Interface 7: USART, SPI, or I2S clock.

I

CTimer1_CAP2 — 32-bit CTimer1 capture input 2.

R — Reserved.

O

I

CTimer1_MAT2 — 32-bit CTimer1 match output 2.

R — Reserved.

USB_VBUS — Monitors the presence of USB bus power. This signal must be HIGH

for USB reset to occur.

[4]

[2]

PIO1_7/

ADC0_10

27 21

PU I/O; PIO1_7/ADC0_10 — General-purpose digital input/output pin. ADC input channel

AI

10 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm Interface 7: USART RXD, I2C SDA,

SPI MOSI, I2S DATA.

O

I

CTimer1_MAT2 — 32-bit CTimer1 match output 2.

R — Reserved.

CTimer1_CAP2 — 32-bit CTimer1 capture input 2.

PIO1_8/

ADC0_11

28 22

PU I/O; PIO1_8/ADC0_11 — General-purpose digital input/output pin. ADC input channel 11

AI

if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm Interface 7: USART TXD, I2C SCL, SPI

MISO, I2S WS.

O

CTimer1_MAT3 — 32-bit CTimer1 match output 3.

R — Reserved.

I

CTimer1_CAP3 — 32-bit CTimer1 capture input 3.

PIO1_9

29

-

PU I/O PIO1_9 — General-purpose digital input/output pin.

R — Reserved.

I/O FC3_RXD_SDA_MOSI — Flexcomm Interface 3: USART RXD, I2C SDA, SPI

MOSI.

I

CTimer0_CAP2 — 32-bit CTimer0 capture input 2.

R — Reserved.

O

USB_UP_LED — USB port 2 GoodLink LED indicator. It is LOW when the device is

configured (non-control endpoints enabled). It is HIGH when the device is not

configured or during global suspend.

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Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_10

30

-

PU I/O PIO1_10 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_TXD_SCL_MISO_WS — Flexcomm Interface 6: USART TXD, I2C SCL, SPI

MISO, I2S WS.

O

SCT0_OUT4 — SCT0 output 4. PWM output 4.

I/O FC1_SCK — Flexcomm Interface 1: USART or SPI clock.

R — Reserved.

I

USB_FRAME — USB start-of-frame signal derived from host signaling.

[2]

PIO1_11

42

-

PU I/O PIO1_11 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_RTS_SCL_SSEL1 — Flexcomm Interface 6: USART RTS, I2C SCL, SPI

SSEL1.

I

CTimer1_CAP0 — 32-bit CTimer1 capture input 0.

I/O FC4_SCK — Flexcomm Interface 4: USART or SPI clock.

R — Reserved.

I

USB_VBUS — Monitors the presence of USB bus power. This signal must be HIGH

for USB reset to occur.

[2]

PIO1_12

51

-

PU I/O PIO1_12 — General-purpose digital input/output pin.

R — Reserved.

I/O FC5_RXD_SDA_MOSI — Flexcomm Interface 5: USART RXD, I2C SDA, SPI

MOSI.

O

CTimer1_MAT0 — 32-bit CTimer1 match output 0.

I/O FC7_SCK — Flexcomm Interface 7: USART, SPI, or I2S clock.

UTICK_CAP2 — Micro-tick timer capture input 2.

I

[2]

PIO1_13

PIO1_14

54

57

-

PU I/O PIO1_13 — General-purpose digital input/output pin.

R — Reserved.

I/O FC5_TXD_SCL_MISO — Flexcomm Interface 5: USART TXD, I2C SCL, SPI MISO.

O

CTimer1_MAT1 — 32-bit CTimer1 match output 1.

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm Interface 7: USART RXD, I2C SDA,

SPI MOSI, I2S DATA.

[2]

PU I/O PIO1_14 — General-purpose digital input/output pin.

R — Reserved.

I/O FC2_RXD_SDA_MOSI — Flexcomm Interface 2: USART RXD, I2C SDA, SPI

MOSI.

O

SCT0_OUT7 — SCT0 output 7. PWM output 7.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm Interface 7: USART TXD, I2C SCL, SPI

MISO, I2S WS.

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Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_15

PIO1_16

PIO1_17

62

-

PU I/O PIO1_15 — General-purpose digital input/output pin.

R — Reserved.

O

I

SCT0_OUT5 — SCT0 output 5. PWM output 5.

CTimer1_CAP3 — 32-bit CTimer1 capture input 3.

I/O FC7_CTS_SDA_SSEL0 — Flexcomm Interface 7: USART CTS, I2C SDA, SPI

SSEL0.

7

PU I/O PIO1_16 — General-purpose digital input/output pin.

R — Reserved.

O

I

CTimer0_MAT0 — 32-bit CTimer0 match output 0.

CTimer0_CAP0 — 32-bit CTimer0 capture input 0.

I/O FC7_RTS_SCL_SSEL1 — Flexcomm Interface 7: USART RTS, I2C SCL, SPI

SSEL1.

10

PU I/O PIO1_17 — General-purpose digital input/output pin.

R — Reserved.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

I

UTICK_CAP3 — Micro-tick timer capture input 3.

[6]

[5]

USB_DP

USB_DM

RESETN

5

6

5

6

F

I/O USB0 bidirectional D+ line.

I/O USB0 bidirectional D- line.

F

64 48

PU

I

External reset input: A LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. Wakes up the part from deep power-down mode.

RTCXIN

33 25

-

RTC oscillator input.

RTC oscillator output.

RTCXOUT 35 26

VREFP

22

-

ADC positive reference voltage. On LQFP48, VREFP is internally tied to the VDDA

pin.

VREFN

21

-

ADC negative reference voltage. On LQFP48, VREFN is internally tied to the VDDA

pin.

V_DDA

V_DD

23 17

-

Analog supply voltage.

8, 18,

24, 42

34,

Single 1.62 V to 3.6 V power supply powers internal digital functions and I/Os.

56

V_SS

9, 19,

25, 41

55

-

Ground.

V_SSA

20 16

Analog ground.

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[1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to V_DD). Z = high impedance; pull-up or pull-down disabled, AI = analog

input, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation. For pin states in the

different power modes, see Section 6.2.2 “Pin states in different power modes”. For termination on unused pins, see Section 6.2.1

“Termination of unused pins”.

[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if V_DDpresent; if V_DDnot present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength. See Figure 29. Pulse width of spikes or glitches suppressed by input

filter is from 3 ns to 16 ns (simulated value).

[3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode

Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not

disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

[4] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[5] Reset pad.5 V tolerant pad with glitch filter with hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to

20 ns (simulated value)

[6] 5 V tolerant transparent analog pad.

6.2.1 Termination of unused pins

Table 5shows how to terminate pins that are not used in the application. In many cases,

unused pins should be connected externally or configured correctly by software to

minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with their

internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the

GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0

to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

Table 5.

Termination of unused pins

Default Recommended termination of unused pins

state^[1]

RESET

I; PU

The RESET pin can be left unconnected if the application does not use it.

all PIOn_m (not open-drain) I; PU

Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain)

USB_DP

IA

F

Can be left unconnected if driven LOW and configured as GPIO output by software.

If USB interface is not used, pin can be left unconnected except in deep

power-down mode where it must be externally pulled low.

USB_DM

F

If USB interface is not used, pin can be left unconnected except in deep

power-down mode where it must be externally pulled low.

RTCXIN

RTCXOUT

VREFP

VREFN

V_DDA

-

Connect to ground. When grounded, the RTC oscillator is disabled.

Can be left unconnected.

Tie to V_DD

.

Tie to V_SS

.

Tie to V_DD

.

V_SSA

Tie to V_SS.

[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating

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6.2.2 Pin states in different power modes

Table 6.

Pin states in different power modes

Active

Sleep

Deep-sleep

Deep power-down

PIOn_m pins (not I2C)

As configured in the IOCON^[1]. Default: internal pull-up enabled. Floating.

PIO0_23 to PIO0_26 (open-drain As configured in the IOCON^[1].

I2C-bus pins)

Floating.

RESET

Reset function enabled. Default: input, internal pull-up enabled.

[1] Default and programmed pin states are retained in sleep and deep-sleep modes.

7. Functional description

7.1 ARM Cortex-M0+ co-processor

The ARM Cortex-M0+ co-processor offers high performance and very low power

consumption. This processor uses a 2-stage pipeline von Neumann architecture and a

small but powerful instruction set providing high-end processing hardware. The processor

includes a single-cycle multiplier, an NVIC with 32 interrupts, and a separate system tick

timer.

7.2 Nested Vectored Interrupt Controller (NVIC) for Cortex-M0+

The NVIC is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for

low interrupt latency and efficient processing of late arriving interrupts.

7.2.1 Features

• Controls system exceptions and peripheral interrupts.

• 32 vectored interrupt slots.

• Four programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table using VTOR.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.2.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

7.3 System Tick timer (SysTick)

The ARM Cortex-M0+ cores include a system tick timer (SysTick) that is intended to

generate a dedicated SYSTICK exception. The clock source for the SysTick can be the

system clock or the SYSTICK clock.

7.4 On-chip static RAM

The LPC51U68 supports 96 KB SRAM with separate bus master access for higher

throughput and individual power control for low-power operation.

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7.5 On-chip flash

The LPC51U68 supports 256 KB of on-chip flash memory.

7.6 On-chip ROM

The 32 KB on-chip ROM contains the boot loader and the following Application

Programming Interfaces (API):

• In-System Programming (ISP) and In-Application Programming (IAP) support for flash

programming.

• ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB is

supported.

• Supports booting from valid user code in flash, USART, SPI, and I²C.

• Legacy, Single, and Dual image boot.

7.7 Memory mapping

The LPC51U68 incorporates several distinct memory regions. The APB peripheral area is

64 KB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated

4 KB of space simplifying the address decoding.

Figure 5 shows the overall map of the entire address space from the user program

viewpoint following reset.

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Memory space

APB peripherals

0x400A 1000

0x400A 0000

0x4009 D000

0x4009 C000

0x4009 9000

0x4009 8000

0x4009 7000

0x4009 6000

0x4009 5000

0x4009 1000

0x4009 0000

0x4008 C000

0x4008 B000

0x4008 A000

0x4008 9000

0x4008 8000

0x4008 7000

0x4008 6000

0x4008 5000

0x4008 4000

0x4008 3000

0x4008 2000

0x4008 1000

0xFFFF FFFF

0xE010 0000

0xE000 0000

0x4400 0000

ADC

(reserved)

private peripheral bus

(reserved)

(1)

(reserved)

ISP-AP interface

(reserved)

Flexcomm Interface 7

Flexcomm Interface 6

Flexcomm Interface 5

CRC engine

0x4200 0000

0x400A 1000

(reserved)

AHB

peripherals

0x4008 0000

0x4006 0000

(reserved)

Asynchronous

APB peripherals

High Speed GPIO

(reserved)

0x4004 0000

0x4002 0000

see APB

memory

map figure

APB peripherals on

APB bridge 1

Flexcomm Interface 4

Flexcomm Interface 3

Flexcomm Interface 2

Flexcomm Interface 1

APB peripherals on

APB bridge 0

0x4000 0000

0x2400 0000

(reserved)

Flexcomm Interface 0

SCTimer / PWM

FS USB device

(reserved)

0x2200 0000

0x2002 8000

DMA controller

(reserved)

0x2002 0000

0x2001 0000

(reserved)

SRAM0

(64 KB)

0x2000 0000

0x0400 8000

(reserved)

SRAMX

(32 KB)

0x0400 0000

0x0300 8000

(reserved)

Boot ROM

(reserved)

0x0300 0000

0x0004 0000

Flash memory

256 KB

0x0000 0000

0x0000 00C0

0x0000 0000

active interrupt vectors

aaa-028911

[1] The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.

[2] The total size of flash and SRAM is part dependent. See Table 1 on page 4.

Fig 5. LPC51U68 Memory mapping

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APB bridge 0

APB bridge 1

0x4001 FFFF

0x4003 FFFF

(reserved)

Micro-tick timer

Multi-rate timer

Watchdog timer

(reserved)

Flash controller

(reserved)

RTC

31-15

31-21

20

0x4000 F000

0x4000 E000

0x4000 D000

0x4000 C000

0x4000 A000

0x4000 9000

0x4000 8000

0x4000 6000

0x4000 5000

0x4000 4000

0x4000 3000

0x4000 2000

0x4000 1000

0x4000 0000

0x4003 5000

0x4003 4000

0x4002 D000

0x4002 C000

0x4002 9000

0x4002 8000

0x4002 0000

14

13

12

11-10

9

19-13

12

(reserved)

11-9

8

CTIMER 1

CTIMER 0

(reserved)

8

7-0

(reserved)

7-6

5

Input muxes

Pin Interrupts (PINT)

GINT 1

4

Asynchronous APB bridge

3

0x4005 FFFF

GINT 0

(reserved)

2

31-10

0x4004 A000

0x4004 9000

0x4004 8000

0x4004 1000

0x4004 0000

aaa-028913

IOCON

1

9

8

Syscon

CTIMER 3

2

(reserved)

7-1

0

Asynch. Syscon

Fig 6. LPC51U68 APB Memory map

7.8 System control

7.8.1 Clock sources

The LPC51U68 supports two external and three internal clock sources:

• The Free Running Oscillator (FRO).

• Watchdog oscillator (WDTOSC).

• External clock source from the digital I/O pin CLKIN.

• External RTC 32.768 kHz clock.

• Output of the system PLL.

7.8.1.1 FRO

The internal FRO can be used as a CPU clock or a clock source to the system PLL. On

power-up, or any chip reset, the LPC51U68 uses an internal 12 MHz FRO as the clock

source. Software may later switch to one of the available clock sources. A selectable 48

MHz or 96 MHz FRO is also available as a clock source.

The 48 MHz FRO can be used as a clock source to the USB.

The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.

7.8.1.2 Watchdog oscillator (WDTOSC)

The watchdog oscillator is a low-power internal oscillator. The WDTOSC can be used to

provide a clock to the WWDT and to the entire chip. The watchdog oscillator has a

selectable frequency in the range of 6 kHz to 1.5 MHz.

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7.8.1.3 Clock input

An external square-wave clock source (up to 25 MHz) can be supplied on the digital I/O

pin CLKIN.

7.8.1.4 RTC Oscillator

An external RTC (32.768 kHz) can be used to create the main clock when the PLL input or

output is selected as the clock source to the main clock.

7.8.1.5 System PLL

The system PLL allows CPU operation up to the maximum CPU rate without the need for

a high-frequency external clock. The system PLL can run from the internal FRO 12 MHz

output, the external clock input CLKIN, or the RTC oscillator.

The system PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO) The PLL can be enabled or disabled by software.

7.8.2 Clock Generation

The system control block facilitates the clock generation. Many clocking variations are

possible. Figure 7 gives an overview of the potential clock options.

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system clock to

CPU, AHB bus,

fro_12m

00

10

11

main_clk

(1)

clk_in

01

pll_clk

32k_clk

Sync APB, etc.

CPU CLOCK

wdt_clk

10

DIVIDER

fro_hf

11

(1)

main_clk

pll_clk

fro_hf

AHBCLKDIV

000

Main clock select B

MAINCLKSELB[1:0]

001

010

111

Main clock select A

MAINCLKSELA[1:0]

to ADC

ADC CLOCK

DIVIDER

“none”

fro_12m

000

001

010

011

111

ADCCLKDIV

clk_in

wdt_clk

32k_clk

“none”

ADC clock select

ADCCLKSEL[2:0]

SYSTEM PLL

(PLL0)

fro_hf

System PLL

settings

000

001

010

111

pll_clk

main_clk

“none”

to FS USB

USB CLOCK

DIVIDER

PLL clock select

SYSPLLCLKSEL[2:0]

USBCLKDIV

USB clock select

USBCLKSEL[2:0]

to async

APB bridge

main_clk

fro_12m

00

01

fro_hf

(1)

000

001

010

111

MCLK pin

(output)

pll_clk

main_clk

“none”

MCLK

DIVIDER

APB clock select B

ASYNCAPBCLKSELB[1:0]

MCLKDIV

MCLK clock select

MCLKCLKSEL[2:0]

(1): synchronized multiplexer,

see register descriptions for details.

to CLK32K of all

Flexcomm Interfaces

32k_clk

(1 per device)

(1 per Flexcomm Interface)

fro_12

main_clk

000

main_clk

pll_clk

fro_12m

fro_hf

clk_in

001

000

001

010

011

100

111

fcn_fclk

fro_hf

pll_clk

wdt_clk

010

(function clock

of Flexcomm [n]

001

010

011

111

fro_hf

011

CLKOUT

mclk_in

frg_clk

“none”

pll_clk

fro_12m

(up to 8 Flexcomm

interfaces on

these devices)

DIVIDER

100

101

110

111

“none”

FRG CLOCK

DIVIDER

32k_clk

“none”

CLKOUTDIV

FRGCTRL[15:0]

FRG clock select

FRGCLKSEL[2:0]

Function clock select

FXCOMCLKSEL[n][2:0]

CLKOUT select

CLKOUTSELA[2:0]

aaa-028912

Fig 7. LPC51U68 clock generation

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Table 9 describes signals on the clocking diagram.

Table 7.

Name

Clocking diagram signal name descriptions

Description

32k_clk

clk_in

The 32 kHz output of the RTC oscillator. The 32 kHz clock must be enabled in the RTCOSCCTRL register.

This is the internal clock that comes from the main CLK_IN pin function. That function must be connected to the

pin by selecting it in the IOCON block.

frg_clk

The output of the Fractional Rate Generator.

fro_12m The 12 MHz output of the currently selected on-chip FRO oscillator.

fro_hf The currently selected FRO high speed output. This may be either 96 MHz or 48 MHz.

main_clk The main clock used by the CPU and AHB bus, and potentially many others.

mclk_in

pll_clk

The MCLK input function, when it is connected to a pin by selecting it in the IOCON block.

The output of the PLL.

wdt_clk

The output of the watchdog oscillator, which has a selectable target frequency. It must also be enabled in the

PDRINCFG0 register.

“none”

A tied-off source that should be selected to save power when the output of the related multiplexer is not used.

7.8.3 Brownout detection

The LPC51U68 includes a monitor for the voltage level on the V_DDpin. If this voltage falls

below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In

addition, a separate threshold levels can be selected to cause chip reset and interrupt.

7.8.4 Safety

The LPC51U68 includes a Windowed WatchDog Timer (WWDT), which can be enabled

by software after reset. Once enabled, the WWDT remains locked and cannot be modified

in any way until a reset occurs.

7.9 Code security (Code Read Protection - CRP)

This feature of the LPC51U68 allows user to enable different levels of security in the

system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry can be invoked by pulling a pin on the LPC51U68 LOW on reset.

This pin is called the ISP entry pin.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. CRP3 fully disables any access to the chip via SWD and ISP. It is up to the user’s

application to provide (if needed) flash update mechanism using IAP calls or a call to

reinvoke ISP command to enable a flash update via USART.

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4. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code

can be disabled (No_ISP mode). For details, see the LPC51U68 user manual.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

7.10 Power control

The LPC51U68 support a variety of power control features. In Active mode, when the chip

is running, power and clocks to selected peripherals can be adjusted for power

consumption. In addition, there are four special modes of processor power reduction with

different peripherals running: sleep mode, deep-sleep mode, and deep power-down

mode, activated by the power mode configure API.

7.10.1 Sleep mode

In sleep mode, the system clock to the CPU is stopped and execution of instructions is

suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be

clocked can continue operation during Sleep mode and may generate interrupts to cause

the processor to resume execution. Sleep mode eliminates dynamic power used by the

processor itself, memory systems and related controllers, internal buses, and unused

peripherals. The processor state and registers, peripheral registers, and internal SRAM

values are maintained, and the logic levels of the pins remain static.

7.10.2 Deep-sleep mode

In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All

analog blocks are powered down by default but can be selected to keep running through

the power API if needed as wake-up sources. The main clock and all peripheral clocks are

disabled. The FRO is disabled. The flash memory is put in standby mode.

Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power

used by the processor itself, memory systems and related controllers, and internal buses.

The processor state and registers, peripheral registers, and internal SRAM values are

maintained, and the logic levels of the pins remain static.

GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB, SPI,

I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left running in deep sleep

mode The FRO, RTC oscillator, and the watchdog oscillator can be left running. In some

cases, DMA can operate in deep-sleep mode. For more details, see LPC51U68 user

manual.

7.10.3 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the RTC power

domain and the RESET pin. The LPC51U68 can wake up from deep power-down mode

via the RESET pin and the RTC alarm. The ALARM1HZ flag in RTC control register

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generates an RTC wake-up interrupt request, which can wake up the part. During deep

power-down mode, the contents of the SRAM and registers are not retained. All functional

pins are tri-stated in deep power-down mode.

Table 8 shows the peripheral configuration in reduced power modes.

Table 8.

Peripheral configuration in reduced power modes

Reduced power mode

Peripheral

Sleep

Deep-sleep

Deep power-down

FRO

Flash

BOD

PLL

Software configured Software configured

Software configured Standby

Off

Software configured Software configured

Software configured Off

Watchdog osc and

WWDT

Software configured Software configured

Micro-tick Timer

DMA

Software configured Software configured

Off

Active

Configurable some for operations, see Section 7.8.2

USART

Software configured Off; but can create a wake-up interrupt in synchronous Off

slave mode or 32 kHz clock mode

SPI

I2C

Software configured Off; but can create a wake-up interrupt in slave mode Off

USB

Software configured Software configured

Off

Other digital peripherals Software configured Off

RTC oscillator Software configured Software configured

Off

Software configured

Table 9 shows the wake-up sources for reduced power modes.

Table 9.

Wake-up sources for reduced power modes

Power mode Wake-up source

Conditions

Sleep

Any interrupt

HWWAKE

Enable interrupt in NVIC.

Certain Flexcomm Interface activity.

Deep-sleep

Pin interrupts

BOD interrupt

Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers.

• Enable interrupt in NVIC and STARTER0 registers.

• Enable interrupt in BODCTRL register.

• Configure the BOD to keep running in this mode with the power API.

BOD reset

Enable reset in BODCTRL register.

Watchdog interrupt

• Enable the watchdog oscillator in the PDRUNCFG0 register.

• Enable the watchdog interrupt in NVIC and STARTER0 registers.

• Enable the watchdog in the WWDT MOD register and feed.

• Enable interrupt in WWDT MOD register.

• Configure the WDTOSC to keep running in this mode with the power API.

• Enable the watchdog oscillator in the PDRUNCFG0 register.

• Enable the watchdog and watchdog reset in the WWDT MOD register and feed.

Always available.

Watchdog reset

Reset pin

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Table 9.

Wake-up sources for reduced power modes

Power mode Wake-up source

RTC 1 Hz alarm timer

Conditions

• Enable the RTC 1 Hz oscillator in the RTCOSCCTRL register.

• Enable the RTC bus clock in the AHBCLKCTRL0 register.

• Start RTC alarm timer by writing a time-out value to the RTC COUNT register.

• Enable the RTCALARM interrupt in the STARTER0 register.

RTC 1 kHz timer

time-out and alarm

• Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL

register.

• Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.

• Enable the RTC wake-up interrupt in the STARTER0 register.

• Enable the watchdog oscillator in the PDRUNCFG0 register.

• Enable the Micro-tick timer clock by writing to the AHBCLKCTRL1 register.

• Start the Micro-tick timer by writing UTICK CTRL register.

• Enable the Micro-tick timer interrupt in the STARTER0 register.

Interrupt from I²C in slave mode.

Micro-tick timer

(intended for ultra-low

power wake-up from

deep-sleep mode

I²C interrupt

SPI interrupt

USART interrupt

Interrupt from SPI in slave mode.

Interrupt from USART in slave or 32 kHz mode.

USB need clock

interrupt

Interrupt from USB when activity is detected that requires a clock.

HWWAKE

Certain Flexcomm Interface activity.

Deep

power-down

RTC 1 Hz alarm timer

• Enable the RTC 1 Hz oscillator in the RTC CTRL register.

• Start RTC alarm timer by writing a time-out value to the RTC COUNT register.

RTC 1 kHz timer

time-out and alarm

• Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the

RTCOSCCTRL register.

• Enable the RTC bus clock in the AHBCLKCTRL0 register.

• Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.

Always available.

Reset pin

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7.11 General Purpose I/O (GPIO)

The LPC51U68 provides two GPIO ports with a total of 48 GPIO pins.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The current level

of a port pin can be read back no matter what peripheral is selected for that pin.

See Table 4 for the default state on reset.

7.11.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set, clear, and toggle registers allow a single instruction set, clear or toggle of

any number of bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt

request.

• One GPIO group interrupt can be triggered by a combination of any pin or pins.

7.12 Pin interrupt/pattern engine

The pin interrupt block configures up to eight pins from all digital pins for providing four

external interrupts connected to the NVIC. The pattern match engine can be used in

conjunction with software to create complex state machines based on pin inputs. Any

digital pin, independent of the function selected through the switch matrix can be

configured through the SYSCON block as an input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the I/O+ bus for fast single-cycle access.

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7.12.1 Features

• Pin interrupts:

– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as

edge-sensitive or level-sensitive interrupt requests. Each request creates a

separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH-active or LOW-active.

– Pin interrupts can wake up the device from sleep mode and deep-sleep mode.

• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute

to a boolean expression. The boolean expression consists of specified levels

and/or transitions on various combinations of these pins.

– Each bit slice minterm (product term) comprising of the specified boolean

expression can generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can also be programmed to generate an RXEV

notification to the CPU. The RXEV signal can be connected to a pin.

– Pattern match can be used in conjunction with software to create complex state

machines based on pin inputs.

– Pattern match engine facilities wake-up only from active and sleep modes.

7.13 AHB peripherals

7.13.1 DMA controller

The DMA controller allows peripheral-to memory, memory-to-peripheral, and

memory-to-memory transactions. Each DMA stream provides unidirectional DMA

transfers for a single source and destination.

7.13.1.1 Features

• 18 channels, 16 of which are connected to peripheral DMA requests. These come

from the Flexcomm Interfaces (USART, SPI, I²C, and I2S).

• DMA operations can be triggered by on-chip or off-chip events.

• Priority is user selectable for each channel (up to eight priority levels).

• Continuous priority arbitration.

• Address cache with four entries.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.

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7.14 Digital serial peripherals

7.14.1 USB 2.0 device controller

7.14.1.1 Features

• USB2.0 full-speed device controller.

• Supports ten physical (five logical) endpoints including one control endpoint.

• Supports Single and double-buffering.

• Supports Crystal-less operation and calibration of FRO using USB frames.

• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

• Link Power Management (LPM) supported.

7.14.2 Flexcomm Interface serial communication

Each Flexcomm Interface provides a choice of peripheral functions, one of which the user

must choose before the function can be configured and used.

7.14.2.1 Features

• USART with asynchronous operation or synchronous master or slave operation.

• SPI master or slave, with up to four slave selects.

• I²C, including separate master, slave, and monitor functions.

• Flexcomm Interfaces 6 and 7 support I²S function.

• Data for USART, SPI, and I²S traffic uses the Flexcomm Interface FIFO. The I²C

function does not use the FIFO.

7.14.3 USART

7.14.3.1 Features

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Maximum bit rates of 6.25 Mbit/s in asynchronous mode.

• Maximum data rates of 20 Mbit/s in synchronous master mode and 16 Mbit/s in

synchronous slave mode.

• Multiprocessor/multidrop (9-bit) mode with software address compare.

• RS-485 transceiver output enable.

• Autobaud mode for automatic baud rate detection.

• Parity generation and checking: odd, even, or none.

• Software selectable oversampling from 5 to 16 clocks in asynchronous mode.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register.

• Break generation and detection.

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• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

• Interrupts available for FIFO receive level reached, FIFO transmit level reached,

Transmit Idle, change in receiver break detect, Framing error, Parity error, Overrun,

Underrun, Delta CTS detect, and receiver sample noise detected.

• Loopback mode for testing of data and flow control.

• In synchronous slave mode, wakes up the part from deep-sleep mode.

• Special operating mode allows operation at up to 9600 baud using the 32.768 kHz

RTC oscillator as the UART clock. This mode can be used while the device is in

deep-sleep mode and can wake-up the device when a character is received.

• USART transmit and receive functions work with the system DMA controller.

• Activity on the USART synchronous slave mode allows wake-up from deep-sleep

mode on any enabled interrupt

7.14.4 SPI serial I/O controller

7.14.4.1 Features

• Master and slave operation.

• Maximum data rate of 71 Mbit/s in master mode and 15 Mbit/s in slave mode for SPI

functions.

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or

DMA set-up.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• Four Slave Select input/outputs with selectable polarity and flexible usage.

• Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any

enabled interrupt.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

7.14.5 I²C-bus interface

The I²C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example, an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I²C is a multi-master bus and

can be controlled by more than one bus master connected to it.

7.14.6 Features

• Independent Master, Slave, and Monitor functions.

• Bus speeds supported:

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– Standard mode, up to 100 kbits/s.

– Fast-mode, up to 400 kbits/s.

– Fast-mode Plus, up to 1 Mbits/s (on specific I²C pins).

– High speed mode, 3.4 Mbits/s as a Slave only (on specific I²C pins).

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I2C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I²C bus addresses.

• 10-bit addressing supported with software assist.

• Supports System Management Bus (SMBus).

• Separate DMA requests for Master, Slave, and Monitor functions.

• No chip clocks are required in order to receive and compare an address as a Slave,

so this event can wake up the device from deep-sleep mode.

7.14.7 I²S-bus interface

The I²S bus provides a standard communication interface for streaming data transfer

applications such as digital audio or data collection. The I²S bus specification defines a

3-wire serial bus, having one data, one clock, and one word select/frame trigger signal,

providing single or dual (mono or stereo) audio data transfer as well as other

configurations. In the LPC51U68, the I²S function is included in Flexcomm Interface 6 and

Flexcomm Interface 7. Each of these Flexcomm Interfaces implement four I²S channel

pairs.

The I²S interface within one Flexcomm Interface provides at least one channel pair that

can be configured as a master or a slave. Other channel pairs, if present, always operate

as slaves. All of the channel pairs within one Flexcomm Interface share one set of I²S

signals, and are configured together for either transmit or receive operation, using the

same mode, same data configuration and frame configuration. All such channel pairs can

participate in a time division multiplexing (TDM) arrangement. For cases requiring an

MCLK input and/or output, this is handled outside of the I²S block in the system level

clocking scheme.

7.14.7.1 Features

• A Flexcomm Interface may implement one or more I²S channel pairs, the first of which

could be a master or a slave, and the rest of which would be slaves. All channel pairs

are configured together for either transmit or receive and other shared attributes. The

number of channel pairs is defined for each Flexcomm Interface, and may be from 0

to 4.

• Configurable data size for all channels within one Flexcomm Interface, from 4 bits to

32 bits. Each channel pair can also be configured independently to act as a single

channel (mono as opposed to stereo operation).

• All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and

word select/frame trigger (WS), and data line (SDA).

• Data for all I²S traffic within one Flexcomm Interface uses the Flexcomm Interface

FIFO. The FIFO depth is 8 entries.

• Left justified and right justified data modes.

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• DMA support using FIFO level triggering.

• TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is

supported. Each channel pair can act as any data slot. Multiple channel pairs can

participate as different slots on one TDM data line.

• The bit clock and WS can be selectively inverted.

• Sampling frequencies supported depends on the specific device configuration and

applications constraints (e.g. system clock frequency, PLL availability, etc.) but

generally supports standard audio data rates. See the data rates section in I2S

chapter (UM11071) to calculate clock and sample rates.

Remark: The Flexcomm Interface function clock frequency should not be above 48 MHz.

7.15 Standard counter/timers (CTimer 0, 1, 3)

The LPC51U68 includes three general-purpose 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture inputs to trap the timer value when

an input signal transitions, optionally generating an interrupt.

7.15.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer

value when an input signal transitions. A capture event may also generate an

interrupt.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs per timer corresponding to match registers with the

following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• Up to two match registers can be used to generate timed DMA requests.

• PWM mode using up to three match channels for PWM output.

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7.15.2 SCTimer/PWM subsystem

The SCTimer/PWM is a flexible timer module capable of creating complex PWM

waveforms and performing other advanced timing and control operations with minimal or

no CPU intervention.

The SCTimer/PWM can operate as a single 32-bit counter or as two independent, 16-bit

counters in uni-directional or bi-directional mode. It supports a selection of match registers

against which the count value can be compared, and capture registers where the current

count value can be recorded when some pre-defined condition is detected.

The SCTimer/PWM module supports multiple separate events that can be defined by the

user based on some combination of parameters including a match on one of the match

registers, and/or a transition on one of the SCTimer/PWM inputs or outputs, the direction

of count, and other factors.

Every action that the SCTimer/PWM block can perform occurs in direct response to one of

these user-defined events without any software overhead. Any event can be enabled to:

• Start, stop, or halt the counter.

• Limit the counter which means to clear the counter in unidirectional mode or change

its direction in bi-directional mode.

• Set, clear, or toggle any SCTimer/PWM output.

• Force a capture of the count value into any capture registers.

• Generate an interrupt of DMA request.

7.15.2.1 Features

• The SCTimer/PWM Supports:

– Eight inputs.

– Eight outputs.

– Ten match/capture registers.

– Ten events.

– Ten states.

• Counter/timer features:

– Each SCTimer/PWM is configurable as two 16-bit counters or one 32-bit counter.

– Counters clocked by system clock or selected input.

– Configurable number of match and capture registers. Up to five match and capture

registers total.

– Ten events.

– Ten states.

– Upon match and/or an input or output transition create the following events:

interrupt; stop, limit, halt the timer or change counting direction; toggle outputs;

change the state.

– Counter value can be loaded into capture register triggered by a match or

input/output toggle.

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• PWM features:

– Counters can be used in conjunction with match registers to toggle outputs and

create time-proportioned PWM signals.

– Up to eight single-edge or four dual-edge PWM outputs with independent duty

cycle and common PWM cycle length.

• Event creation features:

– The following conditions define an event: a counter match condition, an input (or

output) condition such as an rising or falling edge or level, a combination of match

and/or input/output condition.

– Selected events can limit, halt, start, or stop a counter or change its direction.

– Events trigger state changes, output toggles, interrupts, and DMA transactions.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• State control features:

– A state is defined by events that can happen in the state while the counter is

running.

– A state changes into another state as a result of an event.

– Each event can be assigned to one or more states.

– State variable allows sequencing across multiple counter cycles.

7.15.3 Windowed WatchDog Timer (WWDT)

The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a

programmable time if it enters an erroneous state. When enabled, a watchdog reset is

generated if the user program fails to feed (reload) the Watchdog within a predetermined

amount of time.

7.15.3.1 Features

• Internally resets chip if not reloaded during the programmable time-out period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Programmable 24-bit timer with internal fixed pre-scaler.

• Selectable time period from 1,024 watchdog clocks (T_WDCLK× 256 × 4) to over 67

million watchdog clocks (T_WDCLK× 2²⁴× 4) in increments of four watchdog clocks.

• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog

reset to be disabled.

• Incorrect feed sequence causes immediate watchdog event if enabled.

• The watchdog reload value can optionally be protected such that it can only be

changed after the “warning interrupt” time is reached.

• Flag to indicate Watchdog reset.

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• The Watchdog clock (WDCLK) source is a selectable frequency in the range of 6 kHz

to 1.5 MHz. The accuracy of this clock is limited to +/- 40% over temperature, voltage,

and silicon processing variations.

• The Watchdog timer can be configured to run in deep-sleep mode.

• Debug mode.

7.15.4 RTC timer

The RTC block has two timers: main RTC timer, and high-resolution/wake-up timer. The

main RTC timer is a 32-bit timer that uses a 1 Hz clock and is intended to run continuously

as a real-time clock. When the timer value reaches a match value, an interrupt is raised.

The alarm interrupt can also wake up the part from any low power mode, if enabled.

The high-resolution or wake-up timer is a 16-bit timer that uses a 1 kHz clock and

operates as a one-shot down timer. When the timer is loaded, it starts counting down to 0

at which point an interrupt is raised. The interrupt can be used to wake-up the part from

any low power modes. This timer is intended to be used for timed wake-up from

deep-sleep or deep power-down modes. The high-resolution wake-up timer can be

disabled to conserve power if not used.

The RTC timer uses the 32.768 kHz clock input to create a 1 Hz or 1 kHz clock.

7.15.4.1 Features

• The RTC oscillator has the following clock outputs:

– 32.768 kHz clock, selectable for system clock and CLKOUT pin.

– 1 Hz clock for RTC timing.

– 1 kHz clock for high-resolution RTC timing.

• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.

• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution

with a more that one minute maximum time-out period.

• RTC alarm and high-resolution/wake-up timer time-out each generate independent

interrupt requests. Either time-out can wake up the part from any of the low power

modes, including deep power-down.

7.15.5 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

7.15.5.1 Features

• 24-bit interrupt timer.

• Four channels independently counting down from individually set values.

• Repeat interrupt, one-shot interrupt, and one-shot bus stall modes.

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7.15.6 Micro-tick timer (UTICK)

The ultra-low power Micro-tick Timer, running from the Watchdog oscillator, can be used

to wake up the device from low power modes.

7.15.6.1 Features

• Ultra simple timer.

• Write once to start.

• Interrupt or software polling.

• Four capture registers that can be triggered by external pin transitions.

7.16 12-bit Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12-bit and fast conversion rates of up to 5.0

Msamples/s. Sequences of analog-to-digital conversions can be triggered by multiple

sources. Possible trigger sources are the SCTimer/PWM, external pins, and the ARM

TXEV interrupt.

The ADC supports a variable clocking scheme with clocking synchronous to the system

clock or independent, asynchronous clocking for high-speed conversions

The ADC includes a hardware threshold compare function with zero-crossing detection.

The threshold crossing interrupt is connected internally to the SCTimer/PWM inputs for

tight timing control between the ADC and the SCTimer/PWM.

7.16.1 Features

• 12-bit successive approximation analog to digital converter.

• Input multiplexing up to 12 pins.

• Two configurable conversion sequences with independent triggers.

• Optional automatic high/low threshold comparison and “zero crossing” detection.

• Measurement range V_REFNto V_REFP(not to exceed V_DDAvoltage level).

• 12-bit conversion rate of 5.0 MHz. Options for reduced resolution at higher conversion

rates.

• Burst conversion mode for single or multiple inputs.

• Synchronous or asynchronous operation. Asynchronous operation maximizes

flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger

latency and can eliminate uncertainty and jitter in response to a trigger.

• A temperature sensor is connected as an alternative input for ADC channel 0.

7.17 Temperature sensor

The temperature sensor transducer uses an intrinsic pn-junction diode reference and

outputs a Complement To Absolute Temperature (V_CTAT) voltage. The output voltage

varies inversely with device temperature with an absolute accuracy of better than 3 C

over the full temperature range (-40 C to +105 C). The temperature sensor is only

approximately linear with a slight curvature. The output voltage is measured over different

ranges of temperatures and fit with linear-least-square lines.

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After power-up, the temperature sensor output must be allowed to settle to its stable value

before it can be used as an accurate ADC input.

For an accurate measurement of the temperature sensor by the ADC, the ADC must be

configured in single-channel burst mode. The last value of a nine-conversion (or more)

burst provides an accurate result.

7.18 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M0+. Serial wire debug

and trace functions are supported. The ARM Cortex-M0+ is configured to support up to

four breakpoints and two watch points. In addition, JTAG boundary scan mode is

provided.

The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,

execute the boot code, restart from address 0x0000 0000, and break at the user entry

point.

The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the

SWD functions by default.

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8. Limiting values

Table 10. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

Parameter

Conditions

Min

Max

Unit

[2]

V_DD

supply voltage (core and on pin V_DD

external rail)

0.5

+4.6

V

V_DDA

V_ref

V_I

analog supply voltage

reference voltage

input voltage

on pin V_DDA

0.5

+4.6

+5.0

V

on pin VREFP

-

[6][7]

[5]

only valid when the V_DD> 1.8 V;

5 V tolerant I/O pins

on I2C open-drain pins

USB_DM,

V_I

input voltage

0.5

+5.0

V

USB_DP pins

[8][9]

V_IA

analog input voltage

on digital pins configured for an

analog function

0.5

V_DD

V

[3]

I_DD

total supply current

total ground current

I/O latch-up current

per supply pin

-

60

mA

I_SS

per ground pin

60

I_latch

(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 C

100

[2]

[9]

V_i(rtcx)

32.768 kHz oscillator

input voltage

0.5

+4.6

V

T_stg

storage temperature

65

+150

C

T_j(max)

maximum junction

temperature

-

P_tot(pack)

V_ESD

total power dissipation

(per package)

based on package heat transfer,

not device power consumption

-

1.5

W

V

[3]

electrostatic discharge

voltage

human body model; all pins

2000

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 20.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 20) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[5] V_DDpresent or not present. Compliant with the I²C-bus standard. 5.5 V can be applied to this pin when V_DDis powered down.

[6] Applies to all 5 V tolerant I/O pins except true open-drain pins.

[7] Including the voltage on outputs in 3-state mode.

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[8] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 10⁶s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

9. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T_j= T_amb+ P_D R_{thj – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 11. Thermal resistance

Symbol Parameter

LQFP64 Package

Conditions

Max/Min

Unit

R_th(j-a)

thermal resistance from

JEDEC (4.5 in  4 in); still air

58  15 % C/W

junction to ambient

Single-layer (4.5 in  3 in); still air 81  15 % C/W

18  15 % C/W

R_th(j-c)

thermal resistance from

junction to case

LQFP48 Package

R_th(j-a)thermal resistance from

JEDEC (4.5 in  4 in); still air

67  15 % C/W

junction to ambient

Single-layer (4.5 in  3 in); still air 81  15 % C/W

15  15 % C/W

R_th(j-c)

thermal resistance from

junction to case

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10. Static characteristics

10.1 General operating conditions

Table 12. General operating conditions

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

-

Typ^[1]

Max

100

Unit

MHz

f_clk

clock frequency

internal CPU/system clock

-

For USB full-speed device

operation

12

V_DD

supply voltage (core

and external rail)

1.62

3.0

-

3.6

V

For USB operation only

3.6

V_DDA

V_refp

analog supply voltage

1.62

2.0

3.6

ADC positive reference V_DDA2 V

voltage

V_DDA

V_DDA< 2 V

V_DDA

RTC oscillator pins

V_i(rtcx)32.768 kHz oscillator

on pin RTCXIN

0.5

-

+3.6

V

input voltage

V_o(rtcx)

32.768 kHz oscillator

output voltage

on pin RTCXOUT

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

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10.2 CoreMark data

Table 13. CoreMark score

_amb= 25C, V_DD= 3.3V

T

Parameter Conditions

ARM Cortex-M0+ in active mode

Typ

Unit

CoreMark score

CoreMark code executed from SRAMX;

[1][2][3][5][6]

CCLK = 12 MHz

2.0

(Iterations/s) / MHz

CCLK = 48 MHz

CCLK = 96 MHz

CoreMark code executed from flash;

CCLK = 12 MHz; 1 system clock flash

access time.

[1][2][3][4][6]

2.0

1.9

(Iterations/s) / MHz

CCLK = 48 MHz; 3 system clock flash

access time.

[1][2][3][4][6]

CCLK = 96 MHz; 6 system clock flash

access time.

1.7

(Iterations/s) / MHz

[1] Clock source FRO. PLL disabled.

[2] Characterized through bench measurements using typical samples.

[3] Compiler settings: Keil µVision v.5.17., optimization level 3, optimized for time ON.

[4] See the FLASHCFG register in the LPC51U68 User Manual for system clock flash access time settings.

[5] Flash is powered down

[6] SRAM0 and SRAMX powered.

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Conditions: V_DD= 3.3 V; T_amb= 25 °C; active mode; all peripherals disabled; BOD disabled; See

the FLASHCFG register in the LPC51U68, UM11071 User Manual for system clock flash access

time settings. Measured with Keil uVision 5.17. Optimization level 3, optimized for time ON.

12 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.

24 MHz, 36 MHz, 60 MHz, 72 MHz, 84 MHz, and 100 MHz: FRO enabled; PLL enabled.

Fig 8. Typical CoreMark score

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10.3 Power consumption

Power measurements in active, sleep, and deep-sleep modes were performed under the

following conditions:

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

• Configure GPIO pins as outputs using the GPIO DIR register.

• Write 1 to the GPIO CLR register to drive the outputs LOW.

• All peripherals disabled.

Table 14. Static characteristics: Power consumption in active mode

T_amb= 40 C to +105 C, unless otherwise specified.1.62 V  V_DD 3.6 V.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

ARM Cortex-M0+ in active mode

I_DD

supply current

CoreMark code executed from

SRAMX; flash powered down:

[2][3][4][6][7]

[2][3][4][6]

CCLK = 12 MHz

-

1.1

3.0

7.1

-

mA

CCLK = 48 MHz

CCLK = 96 MHz

I_DD

supply current

CoreMark code executed from flash;

CCLK = 12 MHz; 1 system clock

flash access time.

[2][3][4][5][7]

-

1.3

3.6

-

mA

CCLK = 48 MHz; 3 system clock

flash access time.

[2][3][4][5]

CCLK = 96 MHz; 7 system clock

flash access time.

-

8.0

-

mA

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.

[2] Clock source FRO. PLL disabled.

[3] Characterized through bench measurements using typical samples.

[4] Compiler settings: Keil µVision 5.17., optimization level 0, optimized for time off.

[5] Prefetch disabled in FLASHCFG register. SRAM0 powered. SRAMX powered down. All peripheral clocks disabled.

[6] Flash is powered down; SRAM0 and SRAMX are powered. All peripheral clocks disabled.

[7] Characterized using low power regulation mode.

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Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled; Prefetch disabled in FLASHCFG

register. See the FLASHCFG register in the LPC51U68, UM11071 User Manual for system clock flash access time settings.

SRAM0 and SRAMX powered. Measured with Keil uVision 5.17. Optimization level 0, optimized for time OFF.

12 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.

24 MHz, 36 MHz, 60 MHz, 72 MHz, 84 MHz, and 100 MHz: FRO enabled; PLL enabled.

Fig 9. CoreMark power consumption: typical A/MHz

Table 15. Static characteristics: Power consumption in sleep mode

T_amb= 40 C to +105 C, unless otherwise specified.1.62 V  V_DD 3.6 V.

Symbol

ARM Cortex-M0+ in sleep mode

I_DDsupply current

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[2][3]

CCLK = 12 MHz

CCLK = 48 MHz

CCLK = 96 MHz

-

900

1.6

3.0

-

A

mA

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.

[2] Characterized through bench measurements using typical samples.

[3] Clock source FRO. PLL disabled. All SRAM powered. Compiler settings: Keil µVision 5.17., optimization level 0, optimized for time off.

Table 16. Static characteristics: Power consumption in deep-sleep and deep power-down modes

T_amb= 40 C to +105 C, 1.62 V . V_DD 2.0 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1][2]Max^[3]Unit

I_DD

supply current

Deep-sleep mode. Flash is powered down.

SRAM0 (64 KB) powered. T_amb= 25 C

SRAM0 (64 KB) powered. T_amb= 105 C

Deep power-down mode;

-

10

17

A

167

RTC oscillator input grounded (RTC oscillator disabled).

T_amb= 25 C

-

290

-

330

nA

A

nA

T_amb= 105 C

6

-

RTC oscillator running with external crystal.

390

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[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).

[2] Characterized through bench measurements using typical samples. V_DD= 1.62 V.

[3] Guaranteed by characterization, not tested in production. V_DD= 2.0 V.

Table 17. Static characteristics: Power consumption in deep-sleep and deep power-down modes

T_amb= 40 C to +105 C, 2.7 V . V_DD 3.6 V; unless otherwise specified.

Symbol Parameter

I_DD

Conditions

Min Typ^[1][2]Max^[3]Unit

supply current Deep-sleep mode. Flash is powered down.

SRAM0 (64 KB) powered. T_amb= 25 C

SRAM0 (64 KB) powered. T_amb= 105 C

Deep power-down mode;

-

12

-

19

A

182

RTC oscillator input grounded (RTC oscillator disabled).

_amb= 25 C

T

-

360

-

470

10

-

nA

A

nA

T_amb= 105 C

RTC oscillator running with external crystal.

450

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).

[2] Characterized through bench measurements using typical samples. V_DD= 3.3 V.

[3] Tested in production, V_DD= 3.6 V.

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Conditions: SRAM0 disabled except SRAMX (32 KB).

Fig 10. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

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Conditions: RTC disabled (RTC oscillator input grounded)

Fig 11. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD

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32-bit ARM Cortex-M0+ microcontroller

Table 18. Typical peripheral power consumption^[1][2][3]

V_DD= 3.3 V; T_amb= 25 °C

Peripheral

I_DDin uA

100.0

2.0

FRO (12 MHz, 48 MHz, 96 MHz)

WDT OSC

Flash

200.0

2.0

BOD

[1] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using PDRUNCFG0/1 registers. All other blocks are

disabled and no code accessing the peripheral is executed.

[2] The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and 96 MHz.

[3] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

Table 19. Typical AHB/APB peripheral power consumption ^[3][4][5]

T_amb= 25 °C, V_DD= 3.3 V;

Peripheral

I_DDin uA/MHz

AHB peripheral

CPU: 12 MHz, sync

APB bus: 12 MHz

CPU: 48 MHz, sync

APB bus: 48 MHz

CPU: 96MHz, sync

APB bus: 96 MHz

USB

2.09

0.02

0.65

0.56

0.34

0.50

1.65

4.01

1.1

2.09

0.01

0.65

0.56

0.43

0.54

1.67

4.05

1.2

2.09

0.01

0.65

0.56

0.43

0.54

1.67

4.04

1.2

Temperature sensor

[1]

GPIO0

GPIO1

DMA

CRC

ADC0

SCTimer/PWM

Flexcomm Interface 0 (USART, SPI, I²C)

Flexcomm Interface1 (USART, SPI, I²C)

Flexcomm Interface 2 (USART, SPI, I²C)

Flexcomm Interface 3 (USART, SPI, I²C)

Flexcomm Interface 4 (USART, SPI, I²C)

Flexcomm Interface 5 (USART, SPI, I²C)

Flexcomm Interface 6 (USART, SPI, I²C, I²S)

Flexcomm Interface 7 (USART, SPI, I²C, I²S)

Sync APB peripheral

1.2

1.1

1.2

1.3

1.4

CPU: 12 MHz, sync

APB bus: 12 MHz

CPU: 48 MHz, sync

APB bus: 48 MHz

CPU: 96MHz, sync

APB bus: 96 MHz

[1]

INPUTMUX

IOCON

PINT

0.87

5.04

1.26

1.20

0.28

0.65

0.26

0.13

0.93

5.12

1.26

1.20

0.32

0.65

0.34

0.16

0.93

5.12

1.26

1.20

0.32

0.66

0.34

0.16

GINT

WWDT

RTC

MRT

UTICK

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Table 19. Typical AHB/APB peripheral power consumption ^[3][4][5]

T_amb= 25 °C, V_DD= 3.3 V;

Peripheral

I_DDin uA/MHz

0.52

I_DDin uA/MHz

0.50

I_DDin uA/MHz

0.50

CTimer0

CTimer1

0.39

0.46

0.47

Fractional Rate Generator

Async APB peripheral

0.46

0.44

CPU: 12 MHz, Async CPU: 48 MHz, sync

APB bus: 12 MHz

CPU: 96MHz,

Async APB bus: 12

MHz^[2]

APB bus: 12 MHz^[2]

CTimer3

0.36

[1] Turn off the peripheral when the configuration is done.

[2] For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a

higher frequency.

[3] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1, and

PDRUNCFG0 registers. All other blocks are disabled and no code accessing the peripheral is executed.

[4] The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and 96 MHz.

[5] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

10.4 Pin characteristics

Table 20. Static characteristics: pin characteristics

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

RESET pin

Conditions

Min

Typ^[1]Max

Unit

V_IH

V_IL

HIGH-level input voltage

0.8  V_DD

0.5

-

5.0

V

LOW-level input voltage

hysteresis voltage

0.3  V_DD

[1][14]

V_hys

0.05  V_DD

-

Standard I/O pins

Input characteristics

I_IL

I_IH

V_I

LOW-level input current

V_I= 0 V; on-chip pull-up resistor

disabled.

-

3.0

180

nA

HIGH-level input current V_I= V_DD; V_DD= 3.6 V; for RESETN

pin.

HIGH-level input current V_I= V_DD; on-chip pull-down resistor

disabled

[3]

input voltage

pin configured to provide a digital

function;

V_DD 1.8 V

0

-

5.0

3.6

5.0

+0.4

+0.8

-

V

V_DD= 0 V

0

V_IH

V_IL

HIGH-level input voltage 1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

1.5

2.0

LOW-level input voltage 1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

0.5

0.1  V_DD

[14]

V_hys

hysteresis voltage

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Table 20. Static characteristics: pin characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

Output characteristics

V_O

I_OZ

output voltage

output active

0

-

V_DD

180

V

OFF-state output current V_O= 0 V; V_O= V_DD; on-chip

pull-up/pull-down resistors disabled

3

nA

V_OH

V_OL

I_OH

HIGH-level output voltage I_OH= 4 mA; 1.62 V  V_DD< 2.7 V

I_OH= 6 mA; 2.7 V  V_DD 3.6 V

V_DD 0.4

-

V

V_DD 0.4

LOW-level output voltage I_OL= 4 mA; 1.62 V  V_DD< 2.7 V

I_OL= 6 mA; 2.7 V  V_DD3.6 V

-

0.4

-

V

-

V

HIGH-level output current V_OH= V_DD 0.4 V;

1.62 V  V_DD< 2.7 V

4.0

mA

V_OH= V_DD 0.4 V;

2.7 V  V_DD 3.6 V

6.0

-

mA

I_OL

LOW-level output current V_OL= 0.4 V; 1.62 V  V_DD< 2.7 V

V_OL= 0.4 V; 2.7 V  V_DD 3.6 V

4.0

6.0

-

mA

-

[2][4]

I_OHS

HIGH-level short-circuit

output current

1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

35

drive HIGH; connected to

ground;

-

87

30

77

mA

I_OLS

LOW-level short-circuit

output current

drive LOW; connected to

V_DD

Weak input pull-up/pull-down characteristics

I_pd

pull-down current

V_I= V_DD

25

80

25

6

80

A

[2]

V_I= 5 V

100

80

30

I_pu

pull-up current

V_I= 0 V

[2][7]

V_DD< V_I< 5 V

Open-drain I²C pins

V_IH

HIGH-level input voltage

1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

0.7  V_DD

-

V

0.7  V_DD

-

V

V_IL

LOW-level input voltage

0

-

0.3  V_DD

V

0

-

0.3  V_DD

V

V_hys

I_LI

hysteresis voltage

0.1  V_DD

-

V

[5]

input leakage current

V_I= V_DD

V_I= 5 V

-

2.5

5.5

-

3.5

10

-

A

mA

-

I_OL

LOW-level output

current

V_OL= 0.4 V; pin configured for

standard mode or fast mode

4.0

V_OL= 0.4V; pin configured for

20

-

mA

Fast-mode Plus

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Table 20. Static characteristics: pin characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

USB_DM and USB_DP pins

V_I

input voltage

0

-

V_DD

-

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

-

V

0.8

-

V

V_hys

Z_out

V_OH

V_OL

I_OH

0.4

33.0

2.8

-

V

[11]

[12]

output impedance

44

-

Ω

HIGH-level output voltage

LOW-level output voltage

V

[13]

0.3

74

9.0

74

9.0

100

V

[9][10]

[10][11]

[9][10]

[10][11]

[10]

HIGH-level output current V_OH= V_DD 0.3 V

V_OH= V_DD 0.3 V

38

6.0

38

6.0

-

mA

I_OL

LOW-level output current V_OL= 0.3 V

V_OL= 0.3 V

-

I_OLS

I_OHS

LOW-level short-circuit

output current

drive LOW; pad connected to

ground

-

[10]

HIGH-level short-circuit

output current

drive HIGH; pad connected to

ground

-

100

mA

Pin capacitance

C_io

input/output capacitance I²C-bus pins

[8]

[6]

-

6.0

2.0

7.0

pF

pins with digital functions only

Pins with digital and analog

functions

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.

[2] Based on characterization. Not tested in production.

[3] With respect to ground.

[4] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[5] To V_SS

.

[6] The values specified are simulated and absolute values, including package/bondwire capacitance.

[7] The weak pull-up resistor is connected to the V_DDrail and pulls up the I/O pin to the V_DDlevel.

[8] The value specified is a simulated value, excluding package/bondwire capacitance.

[9] Without 33 Ω  2 % series external resistor.

[10] The parameter values specified are simulated and absolute values.

[11] With 33 Ω  2 % series external resistor.

[12] With 15 KΩ  5 % resistor to V_SS

.

[13] With 1.5 KΩ  5% resistor to 3.6 V external pull-up.

[14] Guaranteed by design, not tested in production.

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V

DD

I

OL

pd

+

-

pin PIO0_n

A

I

OH

Ipu

-

+

A

aaa-010819

Fig 12. Pin input/output current measurement

10.4.1 Electrical pin characteristics

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ꢁꢆ

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ꢆ

ꢄꢆ

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2/

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2/

ꢁꢐ&

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ꢏꢂꢆ&

ꢁꢐ&&

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ꢆ

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2/

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9

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9

ꢊꢋ9ꢌ

2/

Conditions: V_DD= 1.8 V; on pins PIO0_23 to PIO0_26.

Conditions: V_DD= 3.3 V; on pins PIO0_23 to PIO0_26.

Fig 13. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus LOW-level output voltage

V_OL

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DDDꢀꢁꢅꢆꢈꢅꢅ

DDDꢀꢁꢅꢆꢈꢅꢂ

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ꢈ

ꢏꢂꢆ&

ꢁꢐ&&

,

2/

ꢋP$ꢌ

2/

ꢋP$ꢌ

ꢈꢆ&&

ꢀꢆ

ꢅ

ꢀꢆꢐꢐ&&

ꢏꢂꢆ&

ꢈꢆ&

ꢁꢐ&

ꢀꢆꢐ&

ꢄ

ꢂ

ꢃ

ꢁ

ꢆ

ꢆꢉꢀ

ꢆꢉꢁ

ꢆꢉꢃ

ꢆꢉꢂ

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ꢆ

ꢆꢉꢀ

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ꢆꢉꢐ

ꢆꢉꢄ

9

2/

ꢊꢋ9ꢌ

9

ꢊꢋ9ꢌ

2/

Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 14. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

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DDDꢀꢁꢅꢆꢈꢅꢉ

ꢀꢉꢅ

2+

ꢃꢉꢐ

9

2+

ꢋ9ꢌ

9

ꢋ9ꢌ

ꢀꢉꢇ

ꢀꢉꢄ

ꢀꢉꢐ

ꢀꢉꢂ

ꢀꢉꢃ

ꢀꢉꢁ

ꢃꢉꢁ

ꢁꢉꢈ

ꢁꢉꢄ

ꢁꢉꢃ

ꢁ

ꢏꢂꢆ&

ꢁꢐ&

ꢏꢂꢆ&

ꢁꢐ&&

ꢈꢆ&&

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ꢀꢆꢐ&

ꢀꢆꢐꢐ&&

ꢆ

ꢁꢉꢂ

ꢂꢉꢅ

ꢇꢉꢁ

ꢈꢉꢄ

ꢊꢋP$ꢌ

ꢀꢁ

ꢆ

ꢇ

ꢀꢂ

ꢁꢀ

ꢁꢅ

ꢊꢋP$ꢌ

ꢃꢐ

,

2+

Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 15. Typical HIGH-level output voltage V_OHversus HIGH-level output source current I_OH

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DDDꢀꢁꢅꢆꢈꢅꢊ

DDDꢀꢁꢅꢆꢈꢅꢇ

ꢂꢆ

ꢐꢆ

ꢃꢆ

ꢀꢆ

,

SX

ꢋ$ꢌ

SX

ꢋ$ꢌ

ꢁꢆ

ꢆ

ꢏꢀꢆ

ꢏꢃꢆ

ꢏꢐꢆ

ꢏꢇꢆ

ꢏꢂꢆ&

ꢁꢐ&

ꢏꢂꢆ&

ꢁꢐ&&

ꢈꢆ&

ꢈꢆ&&

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ꢀꢆꢐꢐ&&

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ꢁꢉꢐ

ꢃꢉꢆ

9 ꢊꢋ9ꢌ

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ꢃꢉꢆ

ꢂꢉꢆ

9 ꢊꢋ9ꢌ

ꢐꢉꢆ

,

Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 16. Typical pull-up current I_PUversus input voltage V_I

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DDDꢀꢁꢅꢆꢈꢅꢃ

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,

SG

ꢋ$ꢌ

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ꢂꢁ

ꢁꢅ

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9 ꢊꢋ9ꢌ

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ꢀ

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ꢃ

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ꢐ

9 ꢊꢋ9ꢌ

,

Conditions: V_DD= 1.8V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 17. Typical pull-down current I_PDversus input voltage V_I

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11. Dynamic characteristics

11.1 Flash memory

Table 21. Flash characteristics

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V unless otherwise

specified.

Symbol Parameter

N_enduendurance

Conditions

Min

Typ^[1]

Max

Unit

[2]

sector erase/program

10000

1000

-

cycles

page erase/program; page

in a sector

t_ret

retention time powered

unpowered

10

-

years

ms

-

t_er

erase time

page, sector, or multiple

consecutive sectors

100

[3]

t_prog

programming

time

-

1

-

ms

[1] Typical ratings are not guaranteed.

[2] Number of erase/program cycles.

[3] Programming times are given for writing 256 bytes from RAM to the flash.

11.2 I/O pins

Table 22. Dynamic characteristic: I/O pins^[1]

T_amb= 40 C to +85 C unless otherwise specified; 1.62 V  V_DD 3.6 V unless otherwise

specified.

Symbol Parameter Conditions

Min

Typ Max Unit

Standard I/O pins - normal drive strength

[2][3]

t_r

t_f

t_r

t_f

rise time

fall time

rise time

fall time

pin configured as output; SLEW = 1 (fast

mode);

2.7 V  V_DD 3.6 V

1.0

1.6

-

2.5

3.8

ns

1.62 V  V_DD 1.98 V

pin configured as output; SLEW = 1 (fast

mode);

2.7 V  V_DD 3.6 V

1.62 V V_DD 1.98 V

0.9

1.7

-

2.5

4.1

ns

pin configured as output; SLEW = 0

(standard mode);

2.7 V  V_DD 3.6 V

1.9

2.9

-

4.3

7.8

ns

1.62 V  V_DD 1.98 V

pin configured as output; SLEW = 0

(standard mode);

2.7 V  V_DD 3.6 V

1.62 V  V_DD 1.98 V

pin configured as input

1.9

2.7

0.3

0.2

-

4.0

6.7

1.3

1.2

ns

[4]

t_r

t_f

rise time

fall time

[1] Simulated data.

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[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between

80 % and 20 % of the full output signal level.

[3] The slew rate is configured in the IOCON block the SLEW bit. See the LPC51U68 UM11071 user manual.

[4] C_L= 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.

11.3 Wake-up process

Table 23. Dynamic characteristic: Typical wake-up times from low power modes

V_DD= 3.3 V;T_amb= 25 C; using FRO as the system clock.

Symbol Parameter Conditions

Min Typ^[1]

Max Unit

[2][3]

[2][3][5]

[4][5]

t_wake

wake-up

time

from Sleep mode

-

2.0

19

-

s

ms

from Deep-sleep mode

from deep power-down mode;

RTC disabled; using RESET pin.

1.2

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler.

[3] FRO enabled, all peripherals off. PLL disabled.

[4] RTC disabled. Wake up from deep power-down causes the part to go through entire reset

process. The wake-up time measured is the time between when the RESET pin is triggered to wake the

device up and when a GPIO output pin is set in the reset handler.

[5] FRO disabled.

11.4 System PLL

Table 24. PLL lock times and current

T_amb= 40 C to +105 C. V_DD= 1.62 V to 3.6 V.

Symbol

Parameter

Conditions

Min Typ Max

Unit

PLL configuration: input frequency 12 MHz; output frequency 75 MHz

[2]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

PLL set-up procedure followed

when locked

-

400

550

s

[1][3]

A

PLL configuration: input frequency 12 MHz; output frequency 100 MHz

[2]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

PLL set-up procedure followed

when locked

-

400

750

s

[1][3]

A

PLL configuration: input frequency 32.768 kHz; output frequency 75 MHz

[1]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

-

6250

450

s

[1][3]

when locked

A

PLL configuration: input frequency 32.768 kHz; output frequency 100 MHz

[1]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

-

6250

560

s

[1][3]

when locked

A

[1] Data based on characterization results, not tested in production.

[2] PLL set-up requires high-speed start-up and transition to normal mode. Lock times are only valid when

high-speed start-up settings are applied followed by normal mode settings. The procedure for setting up the

PLL is described in the LPC51U68 user manual.

[3] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

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Table 25. Dynamic characteristics of the PLL^[1]

T_amb= 40 C to +105 C. V_DD= 1.62 V to 3.6 V.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Reference clock input

F_in

input frequency

-

32.768 kHz

-

25 MHz

-

Clock output

[2]

[3]

f_o

output frequency

output duty cycle

CCO frequency

for PLL clkout output

1.2

46

-

150

54

MHz

%

d_o

for PLL clkout output

-

f_CCO

150

MHz

Lock detector output

_lock(PFD)PFD lock criterion

-

1

2

4

ns

Dynamic parameters at f_out= f_CCO= 100 MHz; standard bandwidth settings

[4][5]

J_rms-interval

J_pp-period

RMS interval jitter

f_ref= 10 MHz

-

15

40

30

80

ps

[4][5]

peak-to-peak, period jitter f_ref= 10 MHz

[1] Data based on characterization results, not tested in production.

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.

[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion

means lock output is HIGH.

[4] Actual jitter dependent on amplitude and spectrum of substrate noise.

[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

11.5 FRO

The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.

Table 26. Dynamic characteristic: FRO

T_amb= 40 C to +105 C; 1.62 V  V_DD 3.6 V

Symbol

f_osc(FRO)

Parameter

Min^[2]

11.88

47.52

95.04

Typ^[1]

12

Max^[2]

12.12

48.48

96.96

Unit

MHz

FRO clock frequency

48

96

[1] Tested in production.The values listed are at room temperature (25 C).

[2] Data based on characterization results, not tested in production.

11.6 RTC oscillator

See Section 13.5 for connecting the RTC oscillator to an external clock source.

Table 27. Dynamic characteristic: RTC oscillator

T_amb= 40 C to +105 C; 1.62 V  V_DD 3.6 V^[1]

Symbol

Parameter

Min

Typ

Max

Unit

f_i

input frequency

-

32.768

-

kHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

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11.7 Watchdog oscillator

Table 28. Dynamic characteristics: Watchdog oscillator

_amb= 40 C to +105 C; 1.62 V V_DD 3.6 V

T

Symbol

Parameter

Min

Typ^[1]

Max

Unit

[2]

f_osc(int)

internal watchdog oscillator

frequency

6

-

1500

kHz

D_clkout

J_PP-CC

t_start

clkout duty cycle

peak-peak period jitter

start-up time

48

-

52

20

-

%

[3][4]

[4]

1

4

ns

s

-

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +105 C) is 40 %.

[3] Actual jitter dependent on amplitude and spectrum of substrate noise.

[4] Guaranteed by design. Not tested in production samples.

11.8 I²C-bus

Table 29. Dynamic characteristic: I²C-bus pins^[1]

T_amb= 40 C to +105 C; 1.62 V  V_DD 3.6 V^[2]

Symbol Parameter

f_SCLSCL clock frequency

Conditions

Min

Max

100

400

1

Unit

kHz

MHz

ns

Standard-mode

Fast-mode

0

-

Fast-mode Plus

of both SDA and SCL signals

Standard-mode

Fast-mode

[4][5][6][7]

t_f

fall time

300

20 + 0.1  C_b

300

ns

s

ns

Fast-mode Plus

Standard-mode

Fast-mode

-

120

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

1.3

0.5

4.0

0.6

0.26

0

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

Fast-mode Plus

Standard-mode

Fast-mode

[3][4][8]

[9][10]

t_HD;DATdata hold time

t_SU;DATdata set-up time

0

Fast-mode Plus

Standard-mode

Fast-mode

0

250

100

50

Fast-mode Plus

[1] Guaranteed by design. Not tested in production.

[2] Parameters are valid over operating temperature range unless otherwise specified. See the I²C-bus specification UM10204 for details.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

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[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[8] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t_VD;DATor

t

_VD;ACKby a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement t_SU;DAT= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

t

SU;DAT

f

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 18. I²C-bus pins clock timing

11.9 I²S-bus interface

Table 30. Dynamic characteristics: I²S-bus interface pins ^[1][4]

T_amb= 40 C to 105 C; V_DD= 1.62 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ^[3]Max

Unit

Common to master and slave

t_WH

pulse width HIGH

pulse width LOW

on pins I2Sx_TX_SCK and I2Sx_RX_SCK^[5]

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

(T_cyc/2)-1 -

(T_cyc/2) +1 ns

(T_cyc/2)-1 -

(T_cyc/2) +1 ns

t_WL

on pins I2Sx_TX_SCK and I2Sx_RX_SCK^[5]

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

(T_cyc/2)-1 -

(T_cyc/2) +1 ns

(T_cyc/2)-1 -

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Table 30. Dynamic characteristics: I²S-bus interface pins ^[1][4]

T_amb= 40 C to 105 C; V_DD= 1.62 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ^[3]Max

Unit

Master; 1.62 V  VDD  2.0 V

[2]

t_v(Q)

data output valid time on pin I2Sx_TX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

32.7

29.9

29.0

-

56.6

48.9

47.2

ns

on pin I2Sx_WS

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

35.1

31.9

31.0

-

61.1

51.8

49.7

ns

[2]

t_su(D)

data input set-up time on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

t_h(D)

data input hold time

on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

Slave; 1.62 V  VDD  2.0 V

[2]

t_v(Q)

data output valid time on pin I2Sx_TX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

25.8

23.0

22.2

-

47.0

38.9

37.1

ns

t_su(D)

data input set-up time on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

on pin I2Sx_RX_WS

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

[2]

t_h(D)

data input hold time

on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

1.0

-

ns

on pin I2Sx_RX_WS

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

2.0

-

ns

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Table 30. Dynamic characteristics: I²S-bus interface pins ^[1][4]

T_amb= 40 C to 105 C; V_DD= 1.62 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ^[3]Max

Unit

Master; 2.7 V  VDD  3.6 V

[2]

t_v(Q)

data output valid time on pin I2Sx_TX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

24.2

22.0

21.3

-

40.8

32.2

30.3

ns

on pin I2Sx_WS

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

24.9

22.6

21.8

-

44.3

34.0

31.7

ns

[2]

t_su(D)

data input set-up time on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

t_h(D)

data input hold time

on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

1.7

1.4

1.2

-

ns

Slave; 2.7 V  VDD  3.6 V

[2]

t_v(Q)

data output valid time on pin I2Sx_TX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

17.4

15.2

14.5

-

33.8

25.1

23.0

ns

t_su(D)

data input set-up time on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

on pin I2Sx_RX_WS

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

[2]

t_h(D)

data input hold time

on pin I2Sx_RX_SDA

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0.0

-

ns

on pin I2Sx_RX_WS

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

1.0

-

ns

[1] Based on characterization; not tested in production.

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[2] Clock Divider register (DIV) = 0x0.

[3] Typical ratings are not guaranteed.

[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section

in the I²S chapter (UM10912) to calculate clock and sample rates.

[5] Based on simulation. Not tested in production.

T

t

f

t

r

cy(clk)

I2Sx_SCK

t

WL

WH

I2Sx_TX_SDA

t

v(Q)

I2Sx_RX_SDA

I2Sx_WS

t

h(D)

su(D)

t

aaa-026799

v(Q)

Fig 19. I²S-bus timing (master)

T

t

f

t

r

cy(clk)

I2Sx_SCK

t

WL

WH

I2Sx_TX_SDA

t

v(Q)

I2Sx_RX_SDA

I2Sx_WS

t

su(D)

t

h(D)

t

h(D)

su(D)

aaa-026800

Fig 20. I²S-bus timing (slave)

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11.10 SPI interfaces

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode is 71 Mbit/s, and the maximum supported bit rate for SPI slave mode is 15 Mbit/s.

Table 31. SPI dynamic characteristics^[1]

T_amb= 40 C to 105 C; V_DD= 1.62 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol

Parameter

Conditions

Min

Typ^[2]

Max

Unit

SPI master 1.62 V  V_DD 2.0 V

t_DS

data set-up time

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

7

0

-

ns

-

t_DH

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

-

t_v(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

5

3

2

SPI slave 1.62 V  V_DD 2.0 V

t_DS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

1

-

ns

1

-

1

-

t_DH

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

2

-

3

-

3

-

t_v(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

30

23

21

58

48

45

SPI master 2.7 V  V_DD 3.6 V

t_DS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

3

-

ns

4

-

4

-

t_DH

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

11

10

0

-

t_v(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

5

3

0

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Table 31. SPI dynamic characteristics^[1]

T_amb= 40 C to 105 C; V_DD= 1.62 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol

Parameter

Conditions

Min

Typ^[2]

Max

Unit

SPI slave 2.7 V  V_DD 3.6 V

t_DS

data set-up time

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

2

-

ns

1

-

1

-

t_DH

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

1

-

1

-

1

-

t_v(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

20

15

13

44

32

30

[1] Based on characterization; not tested in production.

[2] Typical ratings are not guaranteed.

T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

MISO (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MOSI (CPHA = 1)

MISO (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

IDLE

DATA VALID (LSB)

DATA VALID

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014969

Fig 21. SPI master timing

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

MOSI (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MISO (CPHA = 1)

MOSI (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

IDLE

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014970

Fig 22. SPI slave timing

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11.11 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master synchronous mode is 20 Mbit/s, and the maximum supported bit rate for USART

slave synchronous mode is 16 Mbit/s

Table 32. USART dynamic characteristics^[1]

T_amb= 40 C to 105 C; V_DD= 1.62 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ^[2]

Max

Unit

USART master (in synchronous mode) 1.62 V  V_DD 2.0 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

45

-

ns

CCLK = 48 MHz to 60 MHz 39

-

CCLK = 96 MHz

38

0

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

-

0

-

0

-

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

2

9

5

4

1

USART slave (in synchronous mode) 1.62 V  V_DD 2.0 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

1

-

ns

1

-

CCLK = 96 MHz

1

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

2

-

3

-

3

-

CCLK = 1 MHz to 12 MHz

30

55

46

CCLK = 48 MHz to 60 MHz 23

CCLK = 96 MHz

USART master (in synchronous mode) 2.7 V  V_DD 3.6 V

22

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

35

-

ns

CCLK = 48 MHz to 60 MHz 27

-

CCLK = 96 MHz

25

0

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

-

0

-

0

-

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

2

9

5

4

2

1

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Table 32. USART dynamic characteristics^[1]

T_amb= 40 C to 105 C; V_DD= 1.62 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ^[2]

Max

Unit

USART slave (in synchronous mode) 2.7 V  V_DD 3.6 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

2

-

ns

1

-

CCLK = 96 MHz

1

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

2

-

1

-

1

-

CCLK = 1 MHz to 12 MHz

19

42

31

28

CCLK = 48 MHz to 60 MHz 14

CCLK = 96 MHz 13

[1] Based on characterization; not tested in production.

[2] Typical ratings are not guaranteed.

T

cy(clk)

Un_SCLK (CLKPOL = 0)

Un_SCLK (CLKPOL = 1)

TXD

t

vQ)

v(Q)

START

BIT0

BIT1

t

su(D) h(D)

BIT1

START

BIT0

RXD

aaa-015074

Fig 23. USART timing

11.12 SCTimer/PWM output timing

Table 33. SCTimer/PWM output dynamic characteristics

_amb= 40 C to 105 C; 1.62 V  V_DD 3.6 V C_L= 30 pF. Simulated skew (over process, voltage,

T

and temperature) of any two SCT fixed-pin output signals; sampled at 10 % and 90 % of the signal

level; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_sk(o)

output skew time

-

2.7

ns

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11.13 USB interface characteristics

Table 34. Dynamic characteristics: USB pins (Full-Speed)

C_L= 50 pF; R_pu= 1.5 k on D+ to V_DD, unless otherwise specified; 3.0 V  V_DD 3.6 V.

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

t_r/ t_f

Min

4.0

90

Typ

Max

20

Unit

ns

t_r

-

t_f

20

ns

t_FRFM

differential rise and fall time match-

ing

111.11

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

1.3

160

2

-

2.0

175

+5

V

t_FEOPT

t_FDEOP

see Figure 26

ns

source jitter for differential transition see Figure 26

to SE0 transition

t_JR1

receiver jitter to next transition

18.5

9

-

+18.5

+9

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

[1]

t_EOPR1

must reject as

EOP; see

Figure 26

40

t_EOPR2

EOP width at receiver

must accept as

EOP; see

82

-

ns

Figure 26

[1] Characterized but not implemented as production test. Guaranteed by design.

T

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × T

+ t

PERIOD

FDEOP

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 24. Differential data-to-EOP transition skew and EOP width

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12. Analog characteristics

12.1 BOD

Table 35. BOD static characteristics

T_amb= 25 C; based on characterization; not tested in production.

Symbol

Parameter

Conditions

interrupt level 0

assertion

Min

Typ

Max

Unit

V_th

threshold voltage

-

1.97

2.11

-

V

de-assertion

interrupt level 1

assertion

V_th

threshold voltage

-

2.36

2.51

-

V

de-assertion

reset level 1

assertion

-

1.77

1.92

-

V

de-assertion

interrupt level 2

assertion

-

2.66

2.80

-

V

de-assertion

reset level 2

assertion

-

1.92

2.06

-

V

de-assertion

interrupt level 3

assertion

-

2.95

3.09

-

V

de-assertion

reset level 3

assertion

-

2.21

2.36

-

V

de-assertion

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12.2 12-bit ADC characteristics

Table 36. 12-bit ADC static characteristics

_amb= 40 C to +105 C; 1.62 V  V_DD 3.6 V; V_SSA= VREFN = GND. ADC calibrated at T_amb= 25C.

T

Symbol

Parameter

Conditions

Min

Typ^[2]

Max

Unit

[3]

[4]

V_IA

analog input

voltage

0

-

V_DDA

V

C_ia

analog input

capacitance

5

-

pF

f_clk(ADC)

f_s

ADC clock

frequency

-

80

5.0

-

MHz

sampling

frequency

-

Msamples/s

LSB

[1][5]

E_D

differential linearity 1.62 V  V_DDA 3.6 V

error

3.0

1.62 V  VREFP  3.6 V

f_clk(ADC)=  72 MHz

2.0 V  V_DDA 3.6 V

2.0 V  VREFP  3.6 V

f_clk(ADC)= 80 MHz

-

3.0

-

LSB

[1][5]

[1][6]

V_DDA= VREFP = 1.62 V

f_clk(ADC)= 80 MHz

-

7.1

5.0

-

LSB

E_L(adj)

integral

non-linearity

1.62 V  V_DDA 3.6 V

1.62 V  VREFP  3.6 V

f_clk(ADC) 72 MHz

[1][6]

2.0 V  V_DDA 3.6 V

2.0 V  VREFP  3.6 V

f_clk(ADC)= 80 MHz

-

4.0

9.0

-

LSB

V_DDA= VREFP = 1.62 V

-

f_clk(ADC)= 80 MHz

[1][7]

[1][8]

E_O

offset error

calibration enabled

-

1.2

3.5

mV

V_err(FS)

full-scale error

voltage

1.62 V  V_DDA 2.0 V

LSB

1.62 V  VREFP  2.0 V

2.0 V  V_DDA 3.6 V

-

2.0

LSB

2.0 V  VREFP  3.6 V

[9][10]

Z_i

input impedance

f_s= 5.0 Msamples/s

17.0

-

k

[1] Based on characterization; not tested in production.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5.

[4] C_iarepresents the external capacitance on the analog input channel for sampling speeds of

5.0 Msamples/s. No parasitic capacitances included.

[5] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width.

See Figure 25.

[6] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 25.

[7] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 25.

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[8] The full-scale error voltage or gain error (E_G) is the difference between the straight-line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 25.

[9] T_amb= 25 C; maximum sampling frequency f_s= 5.0 Msamples/s and analog input capacitance C_ia= 5 pF.

[10] Input impedance Z_iis inversely proportional to the sampling frequency and the total input capacity including

C_iaand C_io: Z_i 1 / (f_s C_i). See Table 20 for C_io. See Figure 26.

offset

error

O

gain

error

E

G

4095

4094

4093

4092

4091

4090

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

VREFP - VREFN

1 LSB =

4096

aaa-016908

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 25. 12-bit ADC characteristics

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Table 37. ADC sampling times ^[1]

T_amb= -40 C to 85 C; 1.62 V  V_DDA 3.6 V; 1.62 V  V_DD 3.6 V

Symbol Parameter Conditions Min

Typ Max Unit

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

20

23

26

31

47

75

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 10 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

15

18

20

24

38

62

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 8 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

12

13

15

19

30

48

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 6 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

9

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

10

11

13

22

36

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

43

46

50

56

74

105

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

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[1]

Table 37. ADC sampling times …continued

T_amb= -40 C to 85 C; 1.62 V  V_DDA 3.6 V; 1.62 V  V_DD 3.6 V

Symbol Parameter Conditions Min

Typ Max Unit

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

35

38

40

46

61

86

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

27

29

32

36

48

69

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

20

22

23

26

36

51

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

[1] Characterized through simulation. Not tested in production.

[2] The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output

impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum

sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.

[3] Z_o= analog source output impedance.

12.2.1 ADC input impedance

Figure 26 shows the ADC input impedance. In this figure:

• ADCx represents slow ADC input channels 6 to 11.

• ADCy represents fast ADC input channels 0 to 5.

• R₁and R_sware the switch-on resistance on the ADC input channel.

• If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through

R

_swto the sampling capacitor (C_ia).

• If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through

R₁+ R_swto the sampling capacitor (C_ia).

• Typical values, R₁= 487 , R_sw= 278 

• See Table 20 for C_io.

• See Table 36 for C_ia.

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ADC

R

1

ADCx

ADCy

C

io

C

ia

R

sw

DAC

C

io

aaa-017600

Fig 26. ADC input impedance

12.3 Temperature sensor

Table 38. Temperature sensor static and dynamic characteristics

V_DD= V_DDA= 1.62 V to 3.6 V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

DT_sen

sensor

temperature

accuracy

T_amb= 40 C to +105 C

-

3

C

E_L

linearity error

T_amb= 40 C to +105 C

-

3

C

s

t_s(pu)

power-up

settling time

to 99% of temperature

sensor output value

10

15

[1] Absolute temperature accuracy.

[2] Based on simulation.

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Table 39. Temperature sensor Linear-Least-Square (LLS) fit parameters

_{DD =}V_DDA= 1.62 V to 3.6 V

V

Fit parameter

LLS slope

Range

Min

Typ

-2.0

590.0

-

Max

Unit

mV/C

mV

[1]

[2]

T_amb= 40 C to +105 C

-

LLS intercept at 0 C

Value at 30 C

T

_amb= 40 C to +105 C

-

521.0

540.0

mV

[1] Measured over typical samples.

[2] Measured for samples over process corners.

DDDꢀꢁꢂꢉꢁꢁꢄ

ꢅꢆꢆ

9

R

ꢋP9ꢌꢌ

//66ꢊꢊILW

ꢄꢆꢆ

ꢂꢆꢆ

ꢁꢆꢆ

ꢆ

ꢏꢂꢆ

ꢏꢀꢆ

ꢁꢆ

ꢐꢆ

ꢅꢆ

7HPSHUDWXUHꢊꢋꢊ&ꢌ

ꢀꢀꢆ

V_DD= V_DDA3.3 V; measured on matrix samples.

Fig 27. LLS fit of the temperature sensor output voltage

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13. Application information

13.1 Start-up behavior

Figure 30 shows the start-up timing after reset. The FRO 12 MHz oscillator provides the

default clock at Reset and provides a clean system clock shortly after the supply pins

reach operating voltage.

FRO

starts

FRO status

internal reset

V

DD

valid threshold

= 1.62 V

t

a

μs

t μs

b

GND

boot time

supply ramp-up

time

user code

t

c

μs

processor status

boot code

execution

finishes;

user code starts

aaa-023995

Fig 28. Start-up timing

Table 40. Typical start-up timing parameters

Parameter Description

Value

 20 s

151 s

931 s

904

t_a

t_b

t_c

FRO start time

Internal reset de-asserted

Legacy image

Single image without CRC

Dual image without CRC

952

13.2 Standard I/O pin configuration

Figure 29 shows the possible pin modes for standard I/O pins:

• Digital output driver: enabled/disabled.

• Digital input: Pull-up enabled/disabled.

• Digital input: Pull-down enabled/disabled.

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• Digital input: Repeater mode enabled/disabled.

• Z mode; High impedance (no cross-bar currents for floating inputs).

The default configuration for standard I/O pins is Z mode. The weak MOS devices provide

a drive capability equivalent to pull-up and pull-down resistors.

V

DD

open-drain enable

output enable

data output

strong

pull-up

ESD

pin configured

as digital output

strong

pull-down

ESD

V

DD

weak

pull-up

pull-up enable

weak

pull-down

repeater

mode enable

pin configured

as digital input

pull-down enable

digital

input

glitch filter

enable

input invert

enable

filter

enable

analog input

pin configured

as analog input

analog

input

aaa-017273

The glitch filter rejects pulses of typical 12 ns width.

Fig 29. Standard I/O and RESET pin configuration

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13.3 Connecting power, clocks, and debug functions

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3.3 V

SWD connector

(4)

(6)

~10 kΩ - 100 kΩ

SWDIO/PIO0_17

1

2

~10 kΩ - 100 kΩ

SWCLK/PIO0_16

(6)

3

5

4

6

n.c.

7

9

n.c.

8

RTCXIN

RESETN

10

C3

C4

(1)

V

SS

RTCXOUT

DGND

V

(2)

V

DD

(2 to 4 pins)

SSA

3.3 V

0.1 ꢀF

0.01 ꢀF

AGND

LPC51U68

DGND

PIO0_4

(3)

V

DDA

3.3 V

PIO0_31

PIO1_6

ISP select pins

(5)

0.1 ꢀF

10 ꢀF

ADCx

DGND

(3)

VREFP

3.3 V

0.1 ꢀF

10 ꢀF

0.1 ꢀF

VREFN

AGND

DGND

aaa-028919

(1) See Section 13.5 “RTC oscillator” for the values of C3 and C4.

(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the V_DDpin. Add one set of decoupling

capacitors to each V_DDpin.

(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and V_DDApins. The 10 μF bypass capacitor

filters the power line. Tie V_DDAand VREFP to V_DDif the ADC is not used. Tie VREFN to V_SSif ADC is not used.

(4) Uses the ARM 10-pin interface for SWD.

(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 1.

(6) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by

default.

Fig 30. Power, clock, and debug connections

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13.4 I/O power consumption

I/O pins can contribute to the overall static and dynamic power consumption of the part.

If pins are configured as digital inputs with the pull-up resistor enabled, a static current can

flow depending on the voltage level at the pin. This current can be obtained using the

parameters I_puand I_pdgiven in Table 20.

If pins are configured as digital outputs, the static current is obtained from parameters IOH

and IOL shown in Table 20, and any external load connected to the pin.

When an I/O pin switches in an application, it contributes to the dynamic power

consumption because the V_DDsupply provides the current to charge and discharge all

internal and external capacitive loads connected to the pin.

The contribution from the I/O switching current I_swcan be calculated as follows for any

given switching frequency f_swif the external capacitive load (C_ext) is known (see Table 20

for the internal I/O capacitance):

I_sw= V_DDx f_swx (C_io+ C_ext

)

13.5 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances C_X1and C_X2

need to be connected externally on RTCXIN and RTCXOUT. See Figure 31.

LPC51U68

L

RTCXIN

RTCXOUT

C

R

C

P

=

L

XTAL

S

C

X2

X1

aaa-018147

Fig 31. RTC oscillator components

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (CL), series resistance (RS), and drive level (DL) are important

parameters to consider while choosing the crystal. After selecting the proper crystal, the

external load capacitor C_X1and C_X2values can also be generally determined by the

following expression:

C

_X1= C_X2= 2C_L (C_Pad+ C_Parasitic

)

Where:

C_L- Crystal load capacitance

_Pad- Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF).

C

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C_Parasitic– Parasitic or stray capacitance of external circuit.

Although C_Parasiticcan be ignored in general, the actual board layout and placement of

external components influences the optimal values of external load capacitors. Therefore,

it is recommended to fine tune the values of external load capacitors on actual hardware

board to get the accurate clock frequency. For fine tuning, output the RTC Clock to one of

the GPIOs and optimize the values of external load capacitors for minimum frequency

deviation.

13.5.1 RTC Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to

the oscillator input and output pins of the chip.

• The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal

usage, have a common ground plane.

• Loops must be made as small as possible to minimize the noise coupled in through

the PCB and to keep the parasitics as small as possible.

• Lay out the ground (GND) pattern under crystal unit.

• Do not lay out other signal lines under crystal unit for multi-layered PCB.

13.6 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 32) or

bus-powered device (see Figure 33).

On the LPC51U68, the USB_VBUS pin is 5 V tolerant only when V_DDis applied and at

operating voltage level. Therefore, if the USB_VBUS function is connected to the USB

connector and the device is self-powered, the USB_VBUS pin must be protected for

situations when V_DD= 0 V.

If V_DDis always at operating level while VBUS = 5 V, the USB_VBUS pin can be

connected directly to the VBUS pin on the USB connector.

For systems where V_DDcan be 0 V and VBUS is directly applied to the VBUS pin,

precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum

allowable voltage on the USB_VBUS pin in this case.

One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the

USB connector. The voltage divider ratio should be such that the USB_VBUS pin is

greater than 0.7 V_DDto indicate a logic HIGH while below the 3.6 V allowable maximum

voltage.

For the following operating conditions

VBUS_max= 5.25 V

V

_DD= 3.6 V,

the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.

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LPCxxxx

V

DD

R2

R3

R1

1.5 kꢁ

USB

USB_VBUS

D+

D-

USB-B

connector

R

= 33 ꢁ

S

USB_DP

USB_DM

V

SS

aaa-023996

Fig 32. USB interface on a self-powered device where USB_VBUS = 5 V

The internal pull-up (1.5 k) can be enabled by setting the DCON bit in the

DEVCMDSTAT register to prevent the USB from timing out when there is a significant

delay between power-up and handling USB traffic. External circuitry is not required.

LPCxxxx

V

DD

REGULATOR

(1)

(2)

USB_VBUS

USB

R1

1.5 kꢁ

VBUS

D+

USB-B

R

= 33 ꢁ

S

USB_DP

D-

connector

R

USB_DM

V

SS

aaa-023997

Two options exist for connecting VBUS to the USB_VBUS pin:

(1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered.

(2) Connect the VBUS signal directly from the connector to the USB_VBUS pin. In this case, 5 V are applied to the USB_VBUS pin

while the regulator is ramping up to supply V_DD. Since the USB_VBUS pin is only 5 V tolerant when V_DDis at operating level,

this connection can degrade the performance of the part over its lifetime. Simulation shows that lifetime is reduced to 15 years

at T_amb= 45 °C and 8 years at T_amb= 55 °C assuming that USB_VBUS = 5 V is applied continuously while V_DD= 0 V.

Fig 33. USB interface on a bus-powered device

Remark: When a self-powered circuit is used without connecting VBUS, configure the

USB_VBUS pin for GPIO (PIO1_6 or PIO1_11) and provide software that can detect the

host presence through some other mechanism before enabling USB_CONNECT and the

SoftConnect feature. Enabling the SoftConnect without host presence leads to USB

compliance failure.

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14. Package outline

LQFP48: plastic low pro le quad at package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v

M

D

A

e

w M

b

p

D

B

H

v

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 34. LQFP48 Package outline

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LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 35. LQFP64 Package outline

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15. Soldering

Footprint information for re ow soldering of LQFP48 package

SOT313-2

Hx

Gx

(0.125)

P2

P1

Hy

Gy

By

Ay

C

D2 (8)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650

sot313-2_fr

Fig 36. LQFP48 Soldering footprint

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Footprint information for re ow soldering of LQFP64 package

SOT314-2

Hx

Gx

(0.125)

P2

P1

Hy

Gy

By

Ay

C

D2 (8)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 13.300 13.300 10.300 10.300 1.500 0.280 0.400 10.500 10.500 13.550 13.550

sot314-2_fr

Fig 37. LQFP64 Soldering footprint

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16. Abbreviations

Table 41. Abbreviations

Acronym

AHB

Description

Advanced High-performance Bus

Advanced Peripheral Bus

Application Programming Interface

Communication Device Class

Direct Memory Access

APB

API

CDC

DMA

FRO oscillator

GPIO

FRO

Internal Free-Running Oscillator, tuned to the factory specified frequency

General Purpose Input/Output

Free Running Oscillator

HID

Human Interface Device

LSB

Least Significant Bit

MCU

MicroController Unit

MSC

Mass Storage Device

PLL

Phase-Locked Loop

SPI

Serial Peripheral Interface

TCP/IP

TTL

Transmission Control Protocol/Internet Protocol

Transistor-Transistor Logic

USART

Universal Asynchronous Receiver/Transmitter

17. References

[1] Technical note ADC design guidelines:

https://www.nxp.com/docs/en/supporting-information/TN00009.pdf

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18. Revision history

Table 42. Revision history

Document ID

Release date Data sheet status

20180517 Product data sheet

Change notice Supersedes

LPC51U68 v.1.3

-

LPC51U68 v.1.2

• Updated Section 2 “Features and benefits”. Added text: USB 2.0 full-speed host/device

controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in

device mode using software library. See Technical note TN00035 for more details.

• Updated VREFP, VREFN, V_DDAtext in Table 4 “Pin description”.

LPC51U68 v.1.2

LPC51U68 v.1.1

20180313

• Updated Section 1 “General description”. Removed text.

20180309 Product data sheet

• Updated Table 11 “Thermal resistance”.

• Updated top-side markings of LQFP48 and LQFP64 packages. See Section 4 “Marking”.

Product data sheet

-

LPC51U68 v.1.1

-

LPC51U68 v.1.0

20171213

Product data sheet

-

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

19.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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21. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.14.2

Flexcomm Interface serial communication. . . 32

7.14.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.14.3 USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.14.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.14.4 SPI serial I/O controller . . . . . . . . . . . . . . . . . 33

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

3.1

4

7.14.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . 33

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

I²S-bus interface . . . . . . . . . . . . . . . . . . . . . . 34

5

7.14.5

7.14.6

7.14.7

6

6.1

6.2

6.2.1

6.2.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

Termination of unused pins. . . . . . . . . . . . . . . 19

Pin states in different power modes . . . . . . . . 20

7.14.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.15

7.15.1

7.15.2

Standard counter/timers (CTimer 0, 1, 3). . . . 35

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SCTimer/PWM subsystem. . . . . . . . . . . . . . . 36

7

Functional description . . . . . . . . . . . . . . . . . . 20

ARM Cortex-M0+ co-processor . . . . . . . . . . . 20

Nested Vectored Interrupt Controller (NVIC) for

Cortex-M0+. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 20

System Tick timer (SysTick) . . . . . . . . . . . . . . 20

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 20

On-chip flash . . . . . . . . . . . . . . . . . . . . . . . . . 21

On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 21

Memory mapping . . . . . . . . . . . . . . . . . . . . . . 21

System control . . . . . . . . . . . . . . . . . . . . . . . . 23

Clock sources. . . . . . . . . . . . . . . . . . . . . . . . . 23

FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Watchdog oscillator (WDTOSC) . . . . . . . . . . . 23

Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

RTC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 24

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clock Generation . . . . . . . . . . . . . . . . . . . . . . 24

Brownout detection. . . . . . . . . . . . . . . . . . . . . 26

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Code security (Code Read Protection - CRP) 26

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 27

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 27

Deep power-down mode . . . . . . . . . . . . . . . . 27

General Purpose I/O (GPIO) . . . . . . . . . . . . . 30

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Pin interrupt/pattern engine . . . . . . . . . . . . . . 30

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 31

DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 31

7.15.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.15.3 Windowed WatchDog Timer (WWDT) . . . . . . 37

7.15.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.15.4 RTC timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.15.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.15.5 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 38

7.15.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.15.6 Micro-tick timer (UTICK) . . . . . . . . . . . . . . . . 39

7.15.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1

7.2

7.2.1

7.2.2

7.3

7.4

7.5

7.6

7.7

7.8

7.8.1

7.8.1.1

7.8.1.2

7.8.1.3

7.8.1.4

7.8.1.5

7.8.2

7.8.3

7.8.4

7.9

7.16

7.16.1

7.17

12-bit Analog-to-Digital Converter (ADC). . . . 39

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Temperature sensor. . . . . . . . . . . . . . . . . . . . 39

Emulation and debugging . . . . . . . . . . . . . . . 40

7.18

8

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 41

Thermal characteristics . . . . . . . . . . . . . . . . . 42

10

Static characteristics . . . . . . . . . . . . . . . . . . . 43

General operating conditions. . . . . . . . . . . . . 43

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 44

Power consumption . . . . . . . . . . . . . . . . . . . . 45

Pin characteristics . . . . . . . . . . . . . . . . . . . . . 50

Electrical pin characteristics. . . . . . . . . . . . . . 53

10.1

10.2

10.3

10.4

10.4.1

7.10

11

Dynamic characteristics. . . . . . . . . . . . . . . . . 56

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 56

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 57

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 57

FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 58

Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 59

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

I²S-bus interface . . . . . . . . . . . . . . . . . . . . . . 60

SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 64

USART interface . . . . . . . . . . . . . . . . . . . . . . 67

SCTimer/PWM output timing . . . . . . . . . . . . . 68

7.10.1

7.10.2

7.10.3

7.11

7.11.1

7.12

7.12.1

7.13

7.13.1

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

11.10

11.11

11.12

7.13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.14

7.14.1

Digital serial peripherals . . . . . . . . . . . . . . . . . 32

USB 2.0 device controller . . . . . . . . . . . . . . . . 32

7.14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

continued >>

LPC51U68

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 18 May 2018

92 of 93

LPC51U68

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.13

USB interface characteristics . . . . . . . . . . . . . 69

12

Analog characteristics . . . . . . . . . . . . . . . . . . 70

BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

12-bit ADC characteristics . . . . . . . . . . . . . . . 71

ADC input impedance. . . . . . . . . . . . . . . . . . . 74

Temperature sensor . . . . . . . . . . . . . . . . . . . . 75

12.1

12.2

12.2.1

12.3

13

Application information. . . . . . . . . . . . . . . . . . 77

Start-up behavior . . . . . . . . . . . . . . . . . . . . . . 77

Standard I/O pin configuration . . . . . . . . . . . . 77

Connecting power, clocks, and debug

13.1

13.2

13.3

functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

I/O power consumption. . . . . . . . . . . . . . . . . . 81

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 81

RTC Printed Circuit Board (PCB) design

13.4

13.5

13.5.1

guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Suggested USB interface solutions . . . . . . . . 82

13.6

14

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 84

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 88

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 89

15

16

17

18

19

Legal information. . . . . . . . . . . . . . . . . . . . . . . 90

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 90

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 91

19.1

19.2

19.3

19.4

20

21

Contact information. . . . . . . . . . . . . . . . . . . . . 91

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 May 2018

Document identifier: LPC51U68


型号：	LPC51U68JBD48E
厂家：	NXP
描述：	RISC Microcontroller 微控制器
文件：	总93页 (文件大小：2298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC51U68JBD48E [NXP]

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