LPC54018J2MET180E_技术文档

LPC54018JxM/LPC54S018JxM

32-bit ARM Cortex-M4 microcontroller; 4MB on-chip Quad SPI

Serial Flash; 360 kB SRAM; High-speed USB device/host +

PHY; Full-speed USB device/host; Ethernet AVB; LCD; EMC;

SPIFI; CAN FD, SDIO; 12-bit 5 Msamples/s ADC; DMIC

subsystem

Rev. 1.1 — 27 January 2019

Product data sheet

1. General description

The LPC54018JxM/LPC54S018JxM is a family of ARM Cortex-M4 based microcontrollers

for embedded applications featuring a rich peripheral set with very low power

consumption and enhanced debug features.

The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power

consumption, enhanced debug features, and a high level of support block integration. The

ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A

hardware floating-point processor is integrated into the core.

The LPC54018JxM/LPC54S018JxM family includes 4 MB of on-chip Quad SPI Serial

Flash (connected on SPIFI interface), 360 KB of on-chip SRAM, one high-speed and one

full-speed USB host and device controller, Ethernet AVB, LCD controller, Smart Card

Interfaces, SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem

with PDM microphone interface and I²S, five general-purpose timers, SCTimer/PWM,

RTC/alarm timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten

flexible serial communication peripherals (USART, SPI, I²S, I²C interface), Secure Hash

Algorithm (SHA), AES-256 engine, Physical Unclonable Function (PUF), secure boot

features, 12-bit 5.0 Msamples/sec ADC, and a temperature sensor.

2. Features and benefits

 ARM Cortex-M4 core (version r0p1):

 ARM Cortex-M4 processor, running at a frequency of up to 180 MHz.

 Floating Point Unit (FPU) and Memory Protection Unit (MPU).

 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input with a selection of sources.

 Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,

and four watch points. Includes Serial Wire Output and ETM Trace for enhanced

debug capabilities, and a debug timestamp counter.

 System tick timer.

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

 On-chip memory:

 Up to 4 MB of on-chip Quad SPI Serial Flash (connected on SPIFI interface).

 Up to 360 KB total SRAM consisting of 160 KB contiguous main SRAM and an

additional 192 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB

traffic.

 General-purpose One-Time Programmable (OTP) memory for user application

specific data and for AES keys.

 ROM API support:

 In-Application Programming (IAP) and In-System Programming (ISP).

 ROM-based USB drivers (HID, CDC, MSC, and DFU).

 Supports serial interface booting (UART, I2C, SPI) from an application processor,

automated booting from NOR flash (SPI, quad SPIFI, 8/16/32-bit external parallel

flash), and USB booting (full-speed, high-speed).

 FRO API for selecting FRO output frequency.

 OTP API for programming OTP memory.

 Random Number Generator (RNG) API.

 RSA API calls (LPC54S018Jx only).

 Execute in place (XIP) from internal serial flash (in quad, dual SPIFI mode or single-bit

SPI mode), and parallel NOR flash.

 Secure Boot features on LPC54S018Jx devices:

 Supports boot image authentication using RSASSA-PKCS1-v1_5 signature

verification with 2048-bit public keys (2048-bit modulus, 32-bit exponent).

 Supports Root of Trust (RoT) establishment by comparing the SHA-256 hash

digest of the RoT public key with OTP memory contents.

 Supports secure anti-rollback of images through revocation of image key

certificate. Supports up to 8 revocations through OTP fuses.

 Supports boot of AES-GCM encrypted images with a 128-bit symmetric key stored

in OTP memory or a 256-bit symmetric key stored using on-chip SRAM PUF.

 Secure Authentication Only Boot. Enforce booting of RSA-2048 signed images

only.

 Encrypted Image Boot. Enforce booting of AES-GCM encrypted images only.

 Enhanced Image Boot. Enforce booting of encrypted then signed images only.

 Security features:

 AES-256 encryption/decryption engine with keys stored in polyfuse OTP

(LPC54S018Jx only).

 Random number generator can be used to create keys with DMA support.

 Secure Hash Algorithm (SHA1/SHA2) module supports boot with dedicated DMA

controller.

 Physical Unclonable Function (PUF) root key using dedicated SRAM for silicon

fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits

(LPC54S018Jx only).

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

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NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

 Serial interfaces:

 Flexcomm Interface contains up to 11 serial peripherals. Each Flexcomm Interface

(except flexcomm 10, which is dedicated for SPI) can be selected by software to be

a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S

interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI,

and I2S if supported by that Flexcomm Interface. A variety of clocking options are

available to each Flexcomm Interface and include a shared fractional baud-rate

generator.

 I²C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to

1Mbit/s and with multiple address recognition and monitor mode. Two sets of true

I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.

 Two ISO 7816 Smart Card Interfaces with DMA support.

 USB 2.0 high-speed host/device controller with on-chip high-speed PHY.

 USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA

controller supporting crystal-less operation in device mode using software library.

See Technical note TN00033 for more details.

 SPIFI with XIP feature connected to on-chip Quad SPI Serial Flash.

 Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and

dedicated DMA controller.

 Two CAN FD modules with dedicated DMA controller.

 Digital peripherals:

 DMA controller with 30 channels and up to 24 programmable triggers, able to

access all memories and DMA-capable peripherals.

 LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film

Transistor (TFT) displays. It has a dedicated DMA controller, selectable display

resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.

 External Memory Controller (EMC) provides support for asynchronous static

memory devices such as RAM, ROM and flash, in addition to dynamic memories

such as single data rate SDRAM with an SDRAM clock of up to 100 MHz. EMC bus

width (bit) supports up to 8/16 data line wide static memory.

 Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.

 CRC engine block can calculate a CRC on supplied data using one of three

standard polynomials with DMA support.

 Up to 137 General-Purpose Input/Output (GPIO) pins.

 GPIO registers are located on the AHB for fast access. The DMA supports GPIO

ports.

 Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,

falling or both input edges.

 Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

 Analog peripherals:

 12-bit ADC with 12 input channels and with multiple internal and external trigger

inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two

independent conversion sequences.

 Integrated temperature sensor connected to the ADC.

 DMIC subsystem includes a dual-channel PDM microphone interface with decimators,

filtering, and hardware voice activity detection. The processed output data can be

routed directly to an I²S interface if needed.

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

3 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

 Timers:

 Five 32-bit general purpose timers/counters. All five timers support up to four

capture inputs and four compare outputs, PWM mode, and external count input.

Specific timer events can be selected to generate DMA requests.

 One SCTimer/PWM with eight input and ten output functions (including capture

and match). Inputs and outputs can be routed to or from external pins and internally

to or from selected peripherals. Internally, the SCTimer/PWM supports 16

match/captures, 16 events, and 16 states.

 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power

domain. A timer in the RTC can be used for wake-up from all low power modes

including deep power-down, with 1 ms resolution.

 Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

 Windowed Watchdog Timer (WWDT).

 Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose

use.

 Clock generation:

 12 MHz internal Free Running Oscillator (FRO). This oscillator provides a

selectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from the

selected higher frequency) that can be used as a system clock. The FRO is

trimmed to 1 % accuracy over the entire voltage and temperature range.

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz.

 32.768 kHz low-power RTC oscillator.

 System PLL allows CPU operation up to the maximum CPU rate and can run from

the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHz

RTC oscillator.

 Two additional PLLs for USB clock and audio subsystem.

 Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.

 Clock output function with divider.

 Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

 Power control:

 Programmable PMU (Power Management Unit) to minimize power consumption

and to match requirements at different performance levels.

 Reduced power modes: sleep, deep-sleep, and deep power-down.

 Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2C

peripherals when operating as slaves.

 Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be

used to wake up the device from low power modes.

 Power-On Reset (POR).

 Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.

 Single power supply 2.7 V to 3.6 V.

 Power-On Reset (POR).

 Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.

 JTAG boundary scan supported.

 128 bit unique device serial number for identification.

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

4 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

 Operating temperature range 40 °C to +105 °C.

 Available in TFBGA180 package.

LPC54018JxM/LPC54S018JxM

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Product data sheet

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32-bit ARM Cortex-M4 microcontroller

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC54018J2MET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54018J4MET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54S018J2MET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54S018J4MET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54018JxM/LPC54S018JxM

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Product data sheet

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

3.1 Ordering options

Table 2.

Ordering options

LPC54018Jx devices (HS/FS USB, Ethernet, CAN 2.0+CAN FD, LCD, SHA)

LPC54018J2MET180

LPC54018J4MET180

TFBGA180

2

4

360

yes yes yes yes yes yes 8/16 11 137 yes -

-

LPC54S018Jx devices (HS/FS USB, Ethernet, CAN 2.0+CAN FD, LCD, SHA, AES, PUF)

LPC54S018J2MET180

LPC54S018J4MET180

TFBGA180

2

4

360

yes yes yes yes yes yes 8/16 11 137 yes yes yes

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

7 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

4. Marking

Terminal 1 index area

aaa-025721

Fig 1. TFBGA180 marking

The LPC54018JxM/LPC54S018JxM TFBGA180 package have the following top-side

marking:

• First line: LPC54018JxM/LPC54S018JxM

• Second line: ET180

• Third line: xxxxxxxxxxxx

• Fourth line: xxxyywwx[R]x

– yyww: Date code with yy = year and ww = week.

– xR = boot code version and device revision.

Table 3.

Device revision table

Revision identifier (R)

Revision description

1B

Initial device revision with Boot ROM version 21.1

LPC54018JxM/LPC54S018JxM

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Product data sheet

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32-bit ARM Cortex-M4 microcontroller

5. Block diagram

Figure 2 shows the LPC54018JxM/LPC54S018JxM block diagram. In this figure, orange

shaded blocks support general purpose DMA and yellow shaded blocks include dedicated

DMA control.

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

JTAG test and

FS USB

bus

ISP access boundary scan

ethernet

PHY interface

LCD

panel

SDIO

interface

CAN

interface

port

interface

Xtalin Xtalout RST

CLOCK GENERATION,

POWER CONTROL,

AND OTHER

DEBUG INTERFACE

GENERAL

PURPOSE

DMA

ETHERNET

10/100

MAC

USB 2.0

HOST/

LCD

clocks

and

controls

CAN

FD

CAN

FD

CLK

OUT

SDIO

SHA

PANEL

ARM CORTEX-M4

WITH FPU/MPU

DEVICE

INTERFACE

SYSTEM FUNCTIONS

CONTROLLER

+AVB

H

D

internal

power

I-code D-code system

Vdd

VOLTAGE REGULATOR

bus

BOOT ROM

64 kB

HS USB

PHY

HS USB

bus

SRAM

192 kB

SPI FLASH

INTERFACE

Quad SPI FLASH

4 MB

SRAM

64 kB

SRAM

32 kB

MULTILAYER

AHB MATRIX

SRAM

32 kB

SRAM

32 kB

FS USB

HOST

HS USB

HOST

SHA SLAVE

INTERFACE

AES256 12b ADC

ADC

inputs

ENGINE

12-CH

REGISTERS REGISTERS

POLYFUSE OTP

256 b

TEMP

SENSOR

USB RAM

INTERFACE

SRAM

8 kB

D[31:0]

A[25:0]

control

GPIO

STATIC/DYNAMIC EXT

MEMORY CONTROLLER

HS GPIO

0-5

SPIFI

REGISTERS

EMC

REGISTERS

DMA

REGISTERS

LCD

REGISTERS

FS USB

DEVICE

REGISTERS

SCTimer/

PWM

FlexComms 0-4

-UARTs 0-4 - I2Cs 0-4

-SPI0s 0-4

CAN 0

CAN 1

ETHERNET

REGISTERS

HS USB

DEVICE

CRC

SDIO

FlexComms 5-9

-UARTs 5-9

REGISTERS REGISTERS

ENGINE

REGISTERS

-SPI0s 5-9

-I2Cs 5-9 - I2Ss 0,1

AUDIO SUBSYS

D-MIC,

AHB TO

APB slave group 0

DECIMATOR, ETC

APB BRIDGE

ASYNC AHB TO

APB BRIDGE

APB slave group 2

SYSTEM CONTROL

SYSTEM CONTROL (async regs)

I/O CONFIGURATION

AHB TO

APB BRIDGE

2 x 32-BIT TIMERS (T3, 4)

GPIO GLOBAL INTRPTS (0, 1)

GPIO INTERRUPT CONTROL

PERIPH INPUT MUX SELECTS

2 x 32-BIT TIMERS (T0, 1)

MULTI-RATE TIMER

APB slave group 1

PMU REGS (+BB, PVT)

32-BIT TIMERS (T2)

RIT

2 x SMARTCARDS

RANDOM NUMBER GEN

OTP CONTROLLER

RTC POWER

DOMAIN

RTC ALARM

WATCHDOG

OSC

WINDOWED WDT

REAL TIME

CLOCK

32 kHz

Osc

DIVIDER

MICRO TICK TIMER

PUF

Note:

- Orange shaded blocks support Gen. Purpose DMA.

- Yellow shaded blocks include dedicated DMA Ctrl.

aaa-030339-x

Fig 2. LPC54018JxM/LPC54S018JxM Block diagram

LPC54018JxM/LPC54S018JxM

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Product data sheet

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32-bit ARM Cortex-M4 microcontroller

6. Pinning information

6.1 Pinning

ball A1

index area

1

2

3

4

5

6

7

8

9 10 11 12 13 14

A

B

C

D

E

F

G

H

J

K

L

M

N

P

aaa-026026

Transparent top view

Fig 3. TFBGA 180 Pin configuration

LPC54018JxM/LPC54S018JxM

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Product data sheet

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32-bit ARM Cortex-M4 microcontroller

6.2 Pin description

On the LPC54018JxM/LPC54S018JxM, digital pins are grouped into several ports. Each

digital pin can support several different digital functions (including General Purpose I/O

(GPIO)) and an additional analog function.

Table 4.

Symbol

Pin description

Description

[2]

PIO0_0

D6

Z

I/O PIO0_0 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SCK

function.

I

CAN1_RD — Receiver input for CAN 1.

I/O FC3_SCK — Flexcomm 3: USART or SPI clock.

O

I

CTimer_MAT0 — Match output 0 from Timer 0.

SCT0_GPI0 — Pin input 0 to SCTimer/PWM.

O

PDM0_CLK — Clock for PDM interface 0, for digital microphone.

[2]

PIO0_1

A1

Z

I/O PIO0_1 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SSEL0

function.

O

CAN1_TD — Transmitter output for CAN 1.

I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

CT0_CAP0 — Capture input 0 to Timer 0.

SCT0_GPI1 — Pin input 1 to SCTimer/PWM.

PDM0_DATA — Data for PDM interface 0 (digital microphone).

[2]

PIO0_2/

TRST

E9

Z

I/O PIO0_2 — General-purpose digital input/output pin. In boundary scan

mode: TRST (Test Reset).

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MISO

function.

I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I

CT0_CAP1 — Capture input 1 to Timer 0.

SCT0_OUT0 — SCTimer/PWM output 0.

SCT0_GPI[2] — Pin input 2 to SCTimer/PWM.

O

I

I/O EMC_D[0] — External Memory interface data [0].

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Product data sheet

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_3/

TCK

A10

Z

I/O PIO0_3 — General-purpose digital input/output pin. In boundary scan

mode: TCK (Test Clock In).

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MOSI

function.

I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

I

CT0_MAT1 — Match output 1 from Timer 0.

SCT0_OUT1 — SCTimer/PWM output 1.

SCT0_GPI3 — Pin input 3 to SCTimer/PWM.

R — Reserved.

I/O EMC_D[1] — External Memory interface data [1].

[2]

PIO0_4/

TMS

C8

Z

I/O PIO0_4 — General-purpose digital input/output pin. In boundary scan

mode: TMS (Test Mode Select).

Remark: The state of this pin at Reset in conjunction with PIO0_5 and

PIO0_6 will determine the boot source for the part or if ISP handler is

invoked. See the Boot Process chapter in UM11060 for more details.

I

CAN0_RD — Receiver input for CAN 0.

I/O FC4_SCK — Flexcomm 4: USART or SPI clock.

I

CT3_CAP0 — Capture input 0 to Timer 3.

SCT0_GPI4 — Pin input 4 to SCTimer/PWM.

R — Reserved.

I/O EMC_D[2] — External Memory interface data [2].

ENET_MDC — Ethernet management data clock.

O

[2]

PIO0_5/

TDI

E7

Z

I/O PIO0_5 — General-purpose digital input/output pin.

In boundary scan mode: TDI (Test Data In).

Remark: The state of this pin at Reset in conjunction with PIO0_4 and

PIO0_6 will determine the boot source for the part or if ISP handler is

invoked. See the Boot Process chapter in UM11060 for more details.

O

CAN0_TD — Transmitter output for CAN 0.

I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

I

CT3_MAT0 — Match output 0 from Timer 3.

SCT0_GPI5 — Pin input 5 to SCTimer/PWM.

R — Reserved.

I/O EMC_D[3] — External Memory interface data [3].

I/O ENET_MDIO — Ethernet management data I/O.

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Product data sheet

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_6/

TDO

A5

Z

I/O PIO0_6 — General-purpose digital input/output pin. In boundary scan

mode: TDO (Test Data Out).

Remark: The state of this pin at Reset in conjunction with PIO0_4 and

PIO0_5 will determine the boot source for the part or if ISP handler is

invoked. See the Boot Process chapter in UM11060 for more details.

I/O FC3_SCK — Flexcomm 3: USART or SPI clock.

I

CT3_CAP1 — Capture input 1 to Timer 3.

CT4_MAT0 — Match output 0 from Timer 4.

SCT0_GPI6 — Pin input 6 to SCTimer/PWM.

R — Reserved.

O

I

I/O EMC_D[4] — External Memory interface data [4].

ENET_RX_DV — Ethernet receive data valid.

I

[2]

PIO0_7

H12

Z

I/O PIO0_7 — General-purpose digital input/output pin.

I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send,

I2C clock, SPI slave select 1.

O

SD_CLK — SD/MMC clock.

I/O FC5_SCK — Flexcomm 5: USART or SPI clock.

I/O FC1_SCK — Flexcomm 1: USART or SPI clock.

O

PDM1_CLK — Clock for PDM interface 1, for digital microphone.

I/O EMC_D[5] — External Memory interface data [5].

I

ENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet

Reference Clock (RMII interface).

[2]

PIO0_8

H10

Z

I/O PIO0_8 — General-purpose digital input/output pin.

I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.

I/O SD_CMD — SD/MMC card command I/O.

I/O FC5_RXD_SDA_MOSI — Flexcomm 5: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

I

SWO — Serial Wire Debug trace output.

PDM1_DATA — Data for PDM interface 1 (digital microphone).

I/O EMC_D[6] — External Memory interface data [6].

I/O PIO0_9 — General-purpose digital input/output pin.

I/O FC3_SSEL2 — Flexcomm 3: SPI slave select 2.

[2]

PIO0_9

G12

Z

O

SD_POW_EN — SD/MMC card power enable.

I/O FC5_TXD_SCL_MISO — Flexcomm 5: USART transmitter, I2C clock,

SPI master-in/slave-out data.

R — Reserved.

I/O SCI1_IO — SmartCard Interface 1 data I/O.

I/O EMC_D[7] — External Memory interface data [7].

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[4]

PIO0_10/

ADC0_0

P2

Z

I/O; PIO0_10/ADC0_0 — General-purpose digital input/output pin. ADC

AI

input channel 0 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.

I

CT2_CAP2 — Capture input 2 to Timer 2.

CT2_MAT0 — Match output 0 from Timer 2.

O

I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock,

SPI master-in/slave-out data.

R — Reserved.

O

SWO — Serial Wire Debug trace output.

[4]

PIO0_11/

ADC0_1

L3

Z

I/O; PIO0_11/ADC0_1 — General-purpose digital input/output pin. ADC

AI

input channel 1 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART receiver, I2C

data I/O, SPI master-out/slave-in data, I2S data I/O.

O

I

CT2_MAT2 — Match output 2 from Timer 2.

FREQME_GPIO_CLK_A — Frequency Measure pin clock input A.

R — Reserved.

I

SWCLK — Serial Wire Debug clock. This is the default function after

booting.

[4]

PIO0_12/

ADC0_2

M3

Z

I/O; PIO0_12/ADC0_2 — General-purpose digital input/output pin. ADC

AI

input channel 2 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock,

SPI master-in/slave-out data.

R — Reserved.

I

FREQME_GPIO_CLK_B — Frequency Measure pin clock input B.

SCT0_GPI7 — Pin input 7 to SCTimer/PWM.

R — Reserved.

I/O SWDIO — Serial Wire Debug I/O. This is the default function after

booting.

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[3]

[4]

PIO0_13

F11

E13

L4

Z

I/O PIO0_13 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SDA

function.

I/O FC1_CTS_SDA_SSEL0 — Flexcomm 1: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

UTICK_CAP0 — Micro-tick timer capture input 0.

CT0_CAP0 — Capture input 0 to Timer 0.

SCT0_GPI0 — Pin input 0 to SCTimer/PWM.

R — Reserved.

I

ENET_RXD0 — Ethernet receive data 0.

PIO0_14

I/O PIO0_14 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SCL

function.

I/O FC1_RTS_SCL_SSEL1 — Flexcomm 1: USART request-to-send,

I2C clock, SPI slave select 1.

I

UTICK_CAP1 — Micro-tick timer capture input 1.

CT0_CAP1 — Capture input 1 to Timer 0.

SCT0_GPI1 — Pin input 1 to SCTimer/PWM.

R — Reserved.

I

ENET_RXD1 — Ethernet receive data 1.

PIO0_15/

ADC0_3

I/O; PIO0_15/ADC0_3 — General-purpose digital input/output pin. ADC

AI

input channel 3 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC6_CTS_SDA_SSEL0 — Flexcomm 6: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

UTICK_CAP2 — Micro-tick timer capture input 2.

CT4_CAP0 — Capture input 4 to Timer 0.

I

O

SCT0_OUT2 — SCTimer/PWM output 2.

R — Reserved.

O

EMC_WEN — External memory interface Write Enable (active low).

ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[4]

PIO0_16/

ADC0_4

M4

Z

I/O; PIO0_16/ADC0_4 — General-purpose digital input/output pin. ADC

AI

input channel 4 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.ws

I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock,

SPI master-in/slave-out data.

O

I

CLKOUT — Output of the CLKOUT function.

CT1_CAP0 — Capture input 0 to Timer 1.

R — Reserved.

O

EMC_CSN[0] — External memory interface static chip select 0 (active

low).

ENET_TXD0 — Ethernet transmit data 0.

[2]

PIO0_17

E14

Z

I/O PIO0_17 — General-purpose digital input/output pin.

I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.

I

SD_CARD_DET_N — SD/MMC card detect (active low).

SCT0_GPI7 — Pin input 7 to SCTimer/PWM.

SCT0_OUT0 — SCTimer/PWM output 0.

R — Reserved.

I

O

EMC_OEN — External memory interface output enable (active low)

ENET_TXD1 — Ethernet transmit data 1.

[2]

PIO0_18

C14

Z

I/O PIO0_18 — General-purpose digital input/output pin.

I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

SD_WR_PRT — SD/MMC write protect.

O

CT1_MAT0 — Match output 0 from Timer 1.

SCT0_OUT1 — SCTimer/PWM output 1.

SCI1_SCLK — SmartCard Interface 1 clock.

EMC_A[0] — External memory interface address 0.

[2]

PIO0_19

C6

Z

I/O PIO0_19 — General-purpose digital input/output pin.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send,

I2C clock, SPI slave select 1.

I

UTICK_CAP0 — Micro-tick timer capture input 0.

CT0_MAT2 — Match output 2 from Timer 0.

SCT0_OUT2 — SCTimer/PWM output 2.

R — Reserved.

O

EMC_A[1] — External memory interface address 1.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART transmitter, I2C

clock, SPI master-in/slave-out data I/O, I2S word-select/frame.

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_20

D13

Z

I/O PIO0_20 — General-purpose digital input/output pin.

I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

I

CT1_MAT1 — Match output 1 from Timer 1.

CT3_CAP3 — Capture input 3 to Timer 3.

SCT0_GPI2 — Pin input 2 to SCTimer/PWM.

I

I/O SCI0_IO — SmartCard Interface 0 data I/O.

EMC_A[2] — External memory interface address 2.

O

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm 7: USART receiver, I2C

data I/O, SPI master-out/slave-in data, I2S data I/O.

[2]

PIO0_21

PIO0_22

PIO0_29

C13

B12

B13

Z

I/O PIO0_21 — General-purpose digital input/output pin.

I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send,

I2C clock, SPI slave select 1.

I

UTICK_CAP3 — Micro-tick timer capture input 3.

CT3_MAT3 — Match output 3 from Timer 3.

SCT0_GPI3 — Pin input 3 to SCTimer/PWM.

SCI0_SCLK — SmartCard Interface 0 clock.

EMC_A[3] — External memory interface address 3.

O

I

O

I/O FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock.

I/O PIO0_22 — General-purpose digital input/output pin.

[2][8]

I/O FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C

clock, SPI master-in/slave-out data I/O, I2S word-select/frame.

I

UTICK_CAP1 — Micro-tick timer capture input 1.

CT3_CAP3 — Capture input 3 to Timer 3.

SCT0_OUT3 — SCTimer/PWM output 3.

R — Reserved.

I

O

R — Reserved.

I

USB0_VBUS — Monitors the presence of USB0 bus power.

[2]

I/O PIO0_29 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 0 USART RXD

function.

I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

R — Reserved.

O

CT2_MAT3 — Match output 3 from Timer 2.

SCT0_OUT8 — SCTimer/PWM output 8.

TRACEDATA[2] — Trace data bit 2.

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_30

A2

Z

I/O PIO0_30 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 0 USART TXD

function.

I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock,

SPI master-in/slave-out data.

R — Reserved.

O

CT0_MAT0 — Match output 0 from Timer 0.

SCT0_OUT9 — SCTimer/PWM output 9.

TRACEDATA[1] — Trace data bit 1.

[4]

[2]

PIO0_31/

ADC0_5

M5

Z

I/O; PIO0_31/ADC0_5 — General-purpose digital input/output pin. ADC

AI

input channel 5 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I/O SD_D[2] — SD/MMC data 2.

O

CT0_MAT1 — Match output 1 from Timer 0.

SCT0_OUT3 — SCTimer/PWM output 3.

TRACEDATA[0] — Trace data bit 0.

PIO1_0/

ADC0_6

N3

I/O; PIO1_0/ADC0_6 — General-purpose digital input/output pin. ADC

AI

input channel 6 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC0_RTS_SCL_SSEL1 — Flexcomm 0: USART request-to-send,

I2C clock, SPI slave select 1.

I/O SD_D[3] — SD/MMC data 3.

I

CT0_CAP2 — Capture 2 input to Timer 0.

SCT0_GPI4 — Pin input 4 to SCTimer/PWM.

TRACECLK — Trace clock.

I

O

PIO1_1

K12

I/O PIO1_1/ — General-purpose digital input/output pin.

I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

R — Reserved.

I

CT0_CAP3 — Capture 3 input to Timer 0.

SCT0_GPI5 — Pin input 5 to SCTimer/PWM.

R — Reserved.

I/O FC10_MOSI — Flexcomm 10: SPI master-out/slave-in data.

I

USB1_OVERCURRENTN — USB1 bus overcurrent indicator (active

low).

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_2

L14

Z

I/O PIO1_2 — General-purpose digital input/output pin.

O

CAN0_TD — Transmitter output for CAN0.

R — Reserved.

O

I

CT0_MAT3 — Match output 3 from Timer0.

SCT0_GPI6 — Pin input 6 to SCTimer/PWM.

PDM1_CLK — Clock for PDM interface 1, for digital microphone.

O

I/O FC10_MISO — Flexcomm 10: SPI master-in/slave-out data.

O

USB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS

must be driven).

[2]

PIO1_3

J13

Z

I/O PIO1_3 — General-purpose digital input/output pin.

I

CAN0_RD — Receiver input for CAN0.

R — Reserved.

O

I

SCT0_OUT4 — SCTimer/PWM output 4.

PDM1_DATA — Data for PDM interface 1 (digital microphone).

O

USB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS

must be driven).

R — Reserved.

I/O FC10_SCK — Flexcomm 10: SPI clock.

I/O PIO1_4 — General-purpose digital input/output pin.

I/O FC0_SCK — Flexcomm 0: USART or SPI clock.

I/O SD_D[0] — SD/MMC data 0.

[2]

PIO1_4

D4

Z

O

I

CT2_MAT1 — Match output 1 from Timer 2.

SCT0_OUT0 — SCTimer/PWM output 0.

FREQME_GPIO_CLK_A — Frequency Measure pin clock input A.

I/O EMC_D[11]) — External Memory interface data [11].

I/O PIO1_5 — General-purpose digital input/output pin.

[2]

PIO1_5

E4

Z

I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

I/O SD_D[2] — SD/MMC data 2.

O

I

CT2_MAT0 — Match output 0 from Timer 2.

SCT0_GPI0 — Pin input 0 to SCTimer/PWM.

R — Reserved.

O

EMC_A[4] — External memory interface address 4.

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_6

PIO1_7

PIO1_8

PIO1_9

G4

N1

P8

K6

Z

I/O PIO1_6 — General-purpose digital input/output pin.

I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I/O SD_D[3] — SD/MMC data 3.

O

I

CT2_MAT1 — Match output 1 from Timer 2.

SCT0_GPI3 — Pin input 3 to SCTimer/PWM.

R — Reserved.

O

EMC_A[5] — External memory interface address 5.

Z

I/O PIO1_7 — General-purpose digital input/output pin.

I/O FC0_RTS_SCL_SSEL1 — Flexcomm 0: USART request-to-send,

I2C clock, SPI slave select 1.

I/O SD_D[1] — SD/MMC data 1.

O

I

CT2_MAT2 — Match output 2 from Timer 2.

SCT0_GPI4 — Pin input 4 to SCTimer/PWM.

R — Reserved.

O

EMC_A[6] — External memory interface address 6.

Z

I/O PIO1_8 — General-purpose digital input/output pin.

I/O FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

SD_CLK — SD/MMC clock.

R — Reserved.

SCT0_OUT1 — SCTimer/PWM output 1.

I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.

EMC_A[7] — External memory interface address 7.

I/O PIO1_9 — General-purpose digital input/output pin.

ENET_TXD0 — Ethernet transmit data 0.

I/O FC1_SCK — Flexcomm 1: USART or SPI clock.

O

ZZ

O

I

CT1_CAP0 — Capture 0 input to Timer 1.

SCT0_OUT2 — SCTimer/PWM output 2.

O

I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

EMC_CASN — External memory interface column access strobe

(active low).

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_10

N9

Z

I/O PIO1_10 — General-purpose digital input/output pin.

O

ENET_TXD1 — Ethernet transmit data 1.

I/O FC1_RXD_SDA_MOSI — Flexcomm 1: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

CT1_MAT0 — Match output 0 from Timer 1.

SCT0_OUT3 — SCTimer/PWM output 3.

R — Reserved.

O

EMC_RASN — External memory interface row address strobe (active

low).

[2][8]

PIO1_11

B4

Z

I/O PIO1_11 — General-purpose digital input/output pin.

ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

O

I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I

CT1_CAP1 — Capture 1 input to Timer 1.

USB0_VBUS — Monitors the presence of USB0 bus power.

R — Reserved.

O

EMC_CLK[0] — External memory interface clock 0.

[2]

PIO1_12

K9

Z

I/O PIO1_12 — General-purpose digital input/output pin.

ENET_RXD0 — Ethernet receive data 0.

I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.

I

O

CT1_MAT1 — Match output 1 from Timer 1.

USB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS

must be driven).

O

EMC_DYCSN[0] — External Memory interface SDRAM chip select 0

(active low).

[2]

PIO1_13

G10

Z

I/O PIO1_13 — General-purpose digital input/output pin.

ENET_RXD1 — Ethernet receive data 1.

I

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART receiver, I2C

data I/O, SPI master-out/slave-in data, I2S data I/O.

I

CT1_CAP2 — Capture 2 input to Timer 1.

USB0_OVERCURRENTN — USB0 bus overcurrent indicator (active

low).

O

USB0_FRAME — USB0 frame toggle signal.

EMC_DQM[0] — External memory interface data mask 0.

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_14

C12

Z

I/O PIO1_14 — General-purpose digital input/output pin.

I

ENET_RX_DV — Ethernet receive data valid.

UTICK_CAP2 — Micro-tick timer capture input 2.

CT1_MAT2 — Match output 2 from Timer 1.

I

O

I/O FC5_CTS_SDA_SSEL0 — Flexcomm 5: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

USB0_LEDN — USB0-configured LED indicator (active low).

EMC_DQM[1] — External memory interface data mask 0.

[2]

PIO1_15

A11

Z

I/O PIO1_15 — General-purpose digital input/output pin.

I

ENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet

Reference Clock (RMII interface).

I

UTICK_CAP3 — Micro-tick timer capture input 3.

CT1_CAP3 — Capture 3 input to Timer 1.

I/O FC5_RTS_SCL_SSEL1 — Flexcomm 5: USART request-to-send,

I2C clock, SPI slave select 1.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send,

I2C clock, SPI slave select 1.

O

EMC_CKE[0] — External memory interface SDRAM clock enable 0.

I/O PIO1_16 — General-purpose digital input/output pin.

ENET_MDC — Ethernet management data clock.

[2]

PIO1_16

B7

Z

O

I/O FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C

clock, SPI master-in/slave-out data I/O, I2S word-select/frame.

O

CT1_MAT3 — Match output 3 from Timer 1.

I/O SD_CMD — SD/MMC card command I/O.

R — Reserved.

O

EMC_A[10] — External memory interface address 10.

[2]

PIO1_17

N12

Z

I/O PIO1_17 — General-purpose digital input/output pin.

I/O ENET_MDIO — Ethernet management data I/O.

I/O FC8_RXD_SDA_MOSI — Flexcomm 8: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

R — Reserved.

O

SCT0_OUT4 — SCTimer/PWM output 4.

CAN1_TD — Transmitter output for CAN 1.

EMC_BLSN[0] — External memory interface byte lane select 0

(active low).

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Product data sheet

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_18

D1

Z

I/O PIO1_18 — General-purpose digital input/output pin.

R — Reserved.

I/O FC8_TXD_SCL_MISO — Flexcomm 8: USART transmitter, I2C clock,

SPI master-in/slave-out data.

R — Reserved.

O

I

SCT0_OUT5 — SCTimer/PWM output 5.

CAN1_RD — Receiver input for CAN 1.

O

EMC_BLSN[1] — External memory interface byte lane select 1

(active low).

[2]

PIO1_19

L1

Z

I/O PIO1_19 — General-purpose digital input/output pin.

I/O FC8_SCK — Flexcomm 8: USART or SPI clock.

O

I

SCT0_OUT7 — SCTimer/PWM output 7.

CT3_MAT1 — Match output 1 from Timer 3.

SCT0_GPI7 — Pin input 7 to SCTimer/PWM.

I/O FC4_SCK — Flexcomm 4: USART or SPI clock.

I/O EMC_D[8] — External Memory interface data [8].

I/O PIO1_20 — General-purpose digital input/output pin.

[2]

PIO1_20

M1

Z

I/O FC7_RTS_SCL_SSEL1 — Flexcomm 7: USART request-to-send,

I2C clock, SPI slave select 1.

R — Reserved.

I

CT3_CAP2 — Capture 2 input to Timer 3.

R — Reserved.

I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I/O EMC_D[9] — External Memory interface data [9].

I/O PIO1_21 — General-purpose digital input/output pin.

[2]

PIO1_21

N8

Z

I/O FC7_CTS_SDA_SSEL0 — Flexcomm 7: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

R — Reserved.

O

CT3_MAT2 — Match output 2 from Timer 3.

R — Reserved.

I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

I/O EMC_D[10] — External Memory interface data [10].

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

24 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_22

P11

Z

I/O PIO1_22 — General-purpose digital input/output pin.

I/O FC8_RTS_SCL_SSEL1 — Flexcomm 8: USART request-to-send,

I2C clock, SPI slave select 1.

I/O SD_CMD — SD/MMC card command I/O.

O

I

CT2_MAT3 — Match output 3 from Timer 2.

SCT0_GPI5 — Pin input 5 to SCTimer/PWM.

I/O FC4_SSEL3 — Flexcomm 4: SPI slave select 3.

EMC_CKE[1] — External memory interface SDRAM clock enable 1.

O

[2]

PIO1_23

M10

Z

I/O PIO1_23 — General-purpose digital input/output pin.

I/O FC2_SCK — Flexcomm 2: USART or SPI clock.

O

SCT0_OUT0 — SCTimer/PWM output 0.

R — Reserved.

I/O ENET_MDIO — Ethernet management data I/O.

I/O FC3_SSEL2 — Flexcomm 3: SPI slave select 2.

O

EMC_A[11] — External memory interface address 11.

[2]

PIO1_24

N14

Z

I/O PIO1_24 — General-purpose digital input/output pin.

I/O FC2_RXD_SDA_MOSI — Flexcomm 2: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

SCT0_OUT1 — SCTimer/PWM output 1.

R — Reserved.

I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.

EMC_A[12] — External memory interface address 12.

O

[2]

PIO1_25

M12

Z

I/O PIO1_25 — General-purpose digital input/output pin.

I/O FC2_TXD_SCL_MISO — Flexcomm 2: USART transmitter, I2C clock,

SPI master-in/slave-out data.

O

I

SCT0_OUT2 — SCTimer/PWM output 2.

R — Reserved.

UTICK_CAP0 — Micro-tick timer capture input 0.

R — Reserved.

O

EMC_A[13] — External memory interface address 13.

LPC54018JxM/LPC54S018JxM

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Product data sheet

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25 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_26

J10

Z

I/O PIO1_26 — General-purpose digital input/output pin.

I/O FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

I

SCT0_OUT3 — SCTimer/PWM output 3.

CT0_CAP3 — Capture 3 input to Timer 0.

UTICK_CAP1 — Micro-tick timer capture input 1.

R — Reserved.

I

O

EMC_A[8] — External memory interface address 8.

[2]

PIO1_27

F10

Z

I/O PIO1_27 — General-purpose digital input/output pin.

I/O FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send,

I2C clock, SPI slave select 1.

I/O SD_D[4] — SD/MMC data 4.

O

CT0_MAT3 — Match output 3 from Timer 0.

CLKOUT — Output of the CLKOUT function.

R — Reserved.

O

EMC_A[9] — External memory interface address 9.

[2]

PIO1_28

E12

Z

I/O PIO1_28 — General-purpose digital input/output pin.

I/O FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock.

I/O SD_D[5] — SD/MMC data 5.

I

CT0_CAP2 — Capture 2 input to Timer 0.

R — Reserved.

I/O EMC_D[12] — External Memory interface data [12].

I/O PIO1_29 — General-purpose digital input/output pin.

[2][8]

PIO1_29

C11

Z

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm 7: USART receiver, I2C

data I/O, SPI master-out/slave-in data, I2S data I/O.

I/O SD_D[6] — SD/MMC data 6.

I

SCT0_GPI6 — Pin input 6 to SCTimer/PWM.

O

USB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS

must be driven).

O

USB1_FRAME — USB1 frame toggle signal.

I/O EMC_D[13] — External Memory interface data [13].

LPC54018JxM/LPC54S018JxM

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Product data sheet

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26 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_30

A8

Z

I/O PIO1_30 — General-purpose digital input/output pin.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART transmitter, I2C

clock, SPI master-in/slave-out data I/O, I2S word-select/frame.

I/O SD_D[7] — SD/MMC data 7.

I

SCT0_GPI7 — Pin input 7 to SCTimer/PWM.

USB1_OVERCURRENTN — USB1 bus overcurrent indicator (active

low).

O

USB1_LEDN — USB1-configured LED indicator (active low).

I/O EMC_D[14] — External Memory interface data [14].

I/O PIO1_31 — General-purpose digital input/output pin.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

R — Reserved.

[2]

PIO1_31

C5

Z

O

CT0_MAT2 — Match output 2 from Timer 0.

SCT0_OUT6 — SCTimer/PWM output 6.

I/O FC8_CTS_SDA_SSEL0 — Flexcomm 8: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I/O EMC_D[15] — External Memory interface data [15].

[4]

[2]

PIO2_0/

ADC0_7

P3

P4

C3

Z

I/O; PIO2_0/ADC0_7 — General-purpose digital input/output pin. ADC

AI

input channel 7 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

R — Reserved.

I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

R — Reserved.

O

CT1_CAP0 — Capture input 0 to Timer 1.

PIO2_1/

ADC0_8

I/O; PIO2_1/ADC0_8 — General-purpose digital input/output pin. ADC

AI

input channel 8 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

R — Reserved.

I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock,

SPI master-in/slave-out data.

R — Reserved.

O

CT1_MAT0 — Match output 0 from Timer 1.

PIO2_2

I/O PIO2_2 — General-purpose digital input/output pin.

I

ENET_CRS — Ethernet Carrier Sense (MII interface) or Ethernet

Carrier Sense/Data Valid (RMII interface).

I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.

O

SCT0_OUT6 — SCTimer/PWM output 6.

CT1_MAT1 — Match output 1 from Timer 1.

LPC54018JxM/LPC54S018JxM

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Product data sheet

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27 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO2_3

PIO2_4

PIO2_5

PIO2_6

B1

D3

C1

F3

Z

I/O PIO2_3 — General-purpose digital input/output pin.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

SD_CLK — SD/MMC clock.

I/O FC1_RXD_SDA_MOSI — Flexcomm 1: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

CT2_MAT0 — Match output 0 from Timer 2.

I/O PIO2_4 — General-purpose digital input/output pin.

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

O

I/O SD_CMD — SD/MMC card command I/O.

I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock,

SPI master-in/slave-out data.

O

CT2_MAT1 — Match output 1 from Timer 2.

I/O PIO2_5 — General-purpose digital input/output pin.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

SD_POW_EN — SD/MMC card power enable

I/O FC1_CTS_SDA_SSEL0 — Flexcomm 1: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

CT1_MAT2 — Match output 2 from Timer 1.

I/O PIO2_6 — General-purpose digital input/output pin.

ENET_TX_CLK — Ethernet Transmit Clock (MII interface).

I

I/O SD_D[0] — SD/MMC data 0.

I/O FC1_RTS_SCL_SSEL1 — Flexcomm 1: USART request-to-send,

I2C clock, SPI slave select 1.

I

CT0_CAP0 — Capture input 0 to Timer 0.

I/O PIO2_7 — General-purpose digital input/output pin.

ENET_COL — Ethernet Collision detect (MII interface).

I/O SD_D(1) — SD/MMC data 1.

[2]

PIO2_7

PIO2_8

J2

Z

I

FREQME_GPIO_CLK_B — Frequency Measure pin clock input B.

CT0_CAP1 — Capture input 1 to Timer 0.

[2]

F4

I/O PIO2_8 — General-purpose digital input/output pin.

ENET_RXD2 — Ethernet Receive Data 2 (MII interface).

I

I/O SD_D[2] — SD/MMC data 2.

R — Reserved.

O

CT0_MAT0 — Match output 0 from Timer 0.

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Product data sheet

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28 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO2_9

K2

Z

I/O PIO2_9 — General-purpose digital input/output pin.

I

ENET_RXD3 — Ethernet Receive Data 3 (MII interface).

I/O SD_D[3] — SD/MMC data 3.

R — Reserved.

O

CT0_MAT1 — Match output 0 from Timer 1.

[2]

PIO2_10

PIO2_11

P1

K3

Z

I/O PIO2_10 — General-purpose digital input/output pin.

I

ENET_RX_ER — Ethernet receive error (RMII/MII interface).

SD_CARD_DET_N — SD/MMC card detect (active low).

I/O PIO2_11 — General-purpose digital input/output pin.

O

LCD_PWR — LCD panel power enable.

SD_VOLT[0] — SD/MMC card regulator voltage control [0].

R — Reserved.

I/O FC5_SCK — Flexcomm 5: USART or SPI clock.

I/O PIO2_12 — General-purpose digital input/output pin.

[2]

PIO2_12

M2

Z

O

I

LCD_LE — LCD line end signal.

SD_VOLT[1] — SD/MMC card regulator voltage control [1].

USB0_IDVALUE — Indicates to the transceiver whether connected

as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH).

R — Reserved.

I/O FC5_RXD_SDA_MOSI — Flexcomm 5: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

[2]

PIO2_13

P7

Z

I/O PIO2_13 — General-purpose digital input/output pin.

O

LCD_DCLK — LCD panel clock.

SD_VOLT[2] — SD/MMC card regulator voltage control [2].

R — Reserved.

I/O FC5_TXD_SCL_MISO — Flexcomm 5: USART transmitter, I2C clock,

SPI master-in/slave-out data.

[2][8]

PIO2_14

L7

Z

I/O PIO2_14 — General-purpose digital input/output pin.

O

LCD_FP — LCD frame pulse (STN). Vertical synchronization pulse

(TFT).

O

USB0_FRAME — USB0 frame toggle signal.

USB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS

must be driven).

O

CT0_MAT2 — Match output 2 from Timer 0.

I/O FC5_CTS_SDA_SSEL0 — Flexcomm 5: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

29 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO2_15

PIO2_16

PIO2_17

M8

Z

I/O PIO2_15 — General-purpose digital input/output pin.

O

I

LCD_AC — LCD STN AC bias drive or TFT data enable output.

USB0_LEDN — USB0-configured LED indicator (active low).

USB0_OVERCURRENTN — USB0 bus overcurrent indicator (active

low).

O

CT0_MAT3 — Match output 3 from Timer 0.

I/O FC5_RTS_SCL_SSEL1 — Flexcomm 5: USART request-to-send,

I2C clock, SPI slave select 1.

[2][8]

L8

I/O PIO2_16 — General-purpose digital input/output pin.

O

LCD_LP — LCD line synchronization pulse (STN). Horizontal

synchronization pulse (TFT).

O

USB1_FRAME — USB1 frame toggle signal.

USB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS

must be driven).

O

CT1_MAT3 — Match output 3 from Timer 1.

I/O FC8_SCK — Flexcomm 8: USART or SPI clock.

I/O PIO2_17 — General-purpose digital input/output pin.

[2]

P10

I

LCD_CLKIN — LCD clock input.

O

I

USB1_LEDN — USB1-configured LED indicator (active low).

USB1_OVERCURRENTN — USB1 bus overcurrent indicator (active

low).

I

CT1_CAP1 — Capture 1 input to Timer 1.

I/O FC8_RXD_SDA_MOSI — Flexcomm 8: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

[2]

PIO2_18

PIO2_19

N10

P12

Z

I/O PIO2_18 — General-purpose digital input/output pin.

O

LCD_VD[0] — LCD Data [0].

I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

I/O FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock.

O

CT3_MAT0 — Match output 0 from Timer 3.

I/O PIO2_19 — General-purpose digital input/output pin.

LCD_VD[1] — LCD Data [1].

[2]

O

I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm 7: USART receiver, I2C

data I/O, SPI master-out/slave-in data, I2S data I/O.

O

CT3_MAT1 — Match output 1 from Timer 3.

LPC54018JxM/LPC54S018JxM

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Product data sheet

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30 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO2_20

P13

Z

I/O PIO2_20 — General-purpose digital input/output pin.

O

LCD_VD[2] — LCD Data [2].

I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send,

I2C clock, SPI slave select 1.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART transmitter, I2C

clock, SPI master-in/slave-out data I/O, I2S word-select/frame.

O

I

CT3_MAT2 — Match output 2 from Timer 3.

CT4_CAP0 — Capture input 4 to Timer 0.

[2]

PIO2_21

PIO2_22

L10

K10

Z

I/O PIO2_21 — General-purpose digital input/output pin.

LCD_VD[3] — LCD Data [3].

O

I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

O

CT3_MAT3 — Match output 3 from Timer 3.

[2]

I/O PIO2_22 — General-purpose digital input/output pin.

O

LCD_VD[4] — LCD Data [4].

SCT0_OUT7 — SCTimer/PWM output 7.

R — Reserved.

I

CT2_CAP0 — Capture input 0 to Timer 2.

R — Reserved.

FC10_SSEL1 — Flexcomm 10: SPI Slave Select 1.

[2]

PIO2_23

PIO2_24

PIO2_25

M14

K14

J11

Z

I/O PIO2_23 — General-purpose digital input/output pin.

O

LCD_VD[5] — LCD Data [5].

SCT0_OUT8 — SCTimer/PWM output 8.

R — Reserved.

I/O FC10_SSEL2 — Flexcomm 10: SPI Slave Select 2.

I/O PIO2_24 — General-purpose digital input/output pin.

[2]

O

LCD_VD[6] — LCD Data [6].

SCT0_OUT9 — SCTimer/PWM output 9.

R — Reserved.

I/O FC10_SSEL3 — Flexcomm 10: SPI Slave Select 3.

I/O PIO2_25 — General-purpose digital input/output pin.

[2][8]

O

I

LCD_VD[7] — LCD Data [7].

USB0_VBUS — Monitors the presence of USB0 bus power.

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

31 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO2_26

H11

Z

I/O PIO2_26 — General-purpose digital input/output pin.

O

LCD_VD[8] — LCD Data [8].

R — Reserved.

I/O FC3_SCK — Flexcomm 3: USART or SPI clock.

CT2_CAP1 — Capture input 1 to Timer 2.

I/O PIO2_27 — General-purpose digital input/output pin.

LCD_VD[9] — LCD Data [9].

I

[2]

PIO2_27

PIO2_28

H14

G13

Z

O

I/O FC9_SCK — Flexcomm 9: USART or SPI clock.

I/O FC3_SSEL2 — Flexcomm 3: SPI slave select 2.

I/O PIO2_28 — General-purpose digital input/output pin.

O

LCD_VD[10]) — LCD Data [10].

I/O FC7_CTS_SDA_SSEL0 — Flexcomm 7: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

R — Reserved

I

CT2_CAP2 — Capture input 2 to Timer 2.

I/O PIO2_29 — General-purpose digital input/output pin.

LCD_VD[11] — LCD Data [11].

[2]

PIO2_29

G11

Z

O

I/O FC7_RTS_SCL_SSEL1 — Flexcomm 7: USART request-to-send,

I2C clock, SPI slave select 1.

I/O FC8_TXD_SCL_MISO — Flexcomm 8: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I

CT2_CAP3 — Capture 3 input to Timer 2.

CLKOUT — Output of the CLKOUT function.

O

[2]

PIO2_30

F12

Z

I/O PIO2_30 — General-purpose digital input/output pin.

O

LCD_VD[12] — LCD Data [12].

R — Reserved.

O

CT2_MAT2 — Match output 2 from Timer 2.

[2]

PIO2_31

PIO3_0

D14

D12

Z

I/O PIO2_31 — General-purpose digital input/output pin.

LCD_VD[13] — LCD Data [13].

I/O PIO3_0 — General-purpose digital input/output pin.

O

LCD_VD[14] — LCD Data [14].

PDM0_CLK — Clock for PDM interface 0, for digital microphone.

R — Reserved.

O

CT1_MAT0 — Match output 0 from Timer 1.

LPC54018JxM/LPC54S018JxM

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Product data sheet

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32 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO3_1

PIO3_2

D11

C10

Z

I/O PIO3_1 — General-purpose digital input/output pin.

O

I

LCD_VD[15] — LCD Data [15].

PDM0_DATA — Data for PDM interface 0 (digital microphone).

R — Reserved.

O

CT1_MAT1 — Match output 1 from Timer 1.

[2]

I/O PIO3_2 — General-purpose digital input/output pin.

LCD_VD[16] — LCD Data [16].

O

I/O FC9_RXD_SDA_MOSI — Flexcomm 9: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

R — Reserved.

O

CT1_MAT2 — Match output 2 from Timer 1.

I/O PIO3_3 — General-purpose digital input/output pin.

LCD_VD[17] — LCD Data [17].

[2]

PIO3_3

PIO3_4

A13

B11

Z

O

I/O FC9_TXD_SCL_MISO — Flexcomm 9: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I/O PIO3_4 — General-purpose digital input/output pin.

O

LCD_VD[18] — LCD Data [18].

R — Reserved.

I/O FC8_CTS_SDA_SSEL0 — Flexcomm 8: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

CT4_CAP1 — Capture input 4 to Timer 1.

[2]

PIO3_5

B10

Z

I/O PIO3_5 — General-purpose digital input/output pin.

O

LCD_VD[19] — LCD Data [19].

R — Reserved.

I/O FC8_RTS_SCL_SSEL1 — Flexcomm 8: USART request-to-send,

I2C clock, SPI slave select 1.

O

CT4_MAT1 — Match output 1 from Timer 4.

[2]

PIO3_6

PIO3_7

C9

B8

Z

I/O PIO3_6 — General-purpose digital input/output pin.

O

LCD_VD[20] — LCD Data [20].

LCD_VD[0] — LCD Data [0].

R — Reserved.

O

CT4_MAT2 — Match output 2 from Timer 4.

[2]

I/O PIO3_7 — General-purpose digital input/output pin.

O

LCD_VD[21] — LCD Data [21].

LCD_VD[1] — LCD Data [1].

R — Reserved.

I

CT4_CAP2 — Capture input 2 to Timer 4.

LPC54018JxM/LPC54S018JxM

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Product data sheet

Rev. 1.1 — 27 January 2019

33 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO3_8

PIO3_9

PIO3_10

A7

C7

A3

Z

I/O PIO3_8 — General-purpose digital input/output pin.

O

LCD_VD[22] — LCD Data [22].

LCD_VD[2] — LCD Data [2].

R — Reserved.

I

CT4_CAP3 — Capture input 3 to Timer 4.

I/O PIO3_9 — General-purpose digital input/output pin.

O

LCD_VD[23] — LCD Data [23].

LCD_VD[3] — LCD Data [3].

R — Reserved.

I

CT0_CAP2 — Capture input 2 to Timer 0.

I/O PIO3_10 — General-purpose digital input/output pin.

O

SCT0_OUT3 — SCTimer/PWM output 3.

R — Reserved.

CT3_MAT0 — Match output 0 from Timer 3.

R — Reserved.

O

EMC_DYCSN[1] — External Memory interface SDRAM chip select

1(active low).

TRACEDATA[0] — Trace data bit 0.

[2]

PIO3_11

B2

Z

I/O PIO3_11 — General-purpose digital input/output pin.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

I/O FC0_SCK — Flexcomm 0: USART or SPI clock.

I/O FC1_SCK — Flexcomm 1: USART or SPI clock.

R — Reserved.

O

TRACEDATA[3] — Trace data bit 3.

[2]

PIO3_12

L2

Z

I/O PIO3_12 — General-purpose digital input/output pin.

O

I

SCT0_OUT8 — SCTimer/PWM output 8.

R — Reserved.

CT3_CAP0 — Capture input 0 to Timer 3.

R — Reserved.

O

CLKOUT — Output of the CLKOUT function.

EMC_CLK[1] — External memory interface clock 1.

TRACECLK — Trace clock.

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO3_13

H4

Z

I/O PIO3_13 — General-purpose digital input/output pin.

O

SCT0_OUT9 — SCTimer/PWM output 9.

I/O FC9_CTS_SDA_SSEL0 — Flexcomm 9: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

CT3_CAP1 — Capture input 1 to Timer 3.

R — Reserved.

I

EMC_FBCK — External memory interface feedback clock.

TRACEDATA[1] — Trace data bit 1.

O

[2]

PIO3_14

E3

Z

I/O PIO3_14 — General-purpose digital input/output pin.

SCT0_OUT4 — SCTimer/PWM output 4.

O

I/O FC9_RTS_SCL_SSEL1 — Flexcomm 9: USART request-to-send,

I2C clock, SPI slave select 1.

O

CT3_MAT1 — Match output 1 from Timer 3.

R — Reserved.

TRACEDATA[2] — Trace data bit 2.

[2]

PIO3_15

PIO3_16

D2

E1

Z

I/O PIO3_15 — General-purpose digital input/output pin.

I/O FC8_SCK — Flexcomm 8: USART or SPI clock.

I

SD_WR_PRT — SD/MMC write protect.

I/O PIO3_16 — General-purpose digital input/output pin.

I/O FC8_RXD_SDA_MOSI — Flexcomm 8: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

I/O SD_D[4] — SD/MMC data 4.

[2]

PIO3_17

PIO3_18

K1

Z

I/O PIO3_17 — General-purpose digital input/output pin.

I/O FC8_TXD_SCL_MISO — Flexcomm 8: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I/O SD_D[5] — SD/MMC data 5.

M6

I/O PIO3_18 — General-purpose digital input/output pin.

I/O FC8_CTS_SDA_SSEL0 — Flexcomm 8: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I/O SD_D[6] — SD/MMC data 6.

O

CT4_MAT0 — Match output 0 from Timer 4.

CAN0_TD — Transmitter output for CAN 0.

SCT0_OUT5 — SCTimer/PWM output 5.

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Table 4.

Symbol

Pin description …continued

Description

[2]

PIO3_19

J3

Z

I/O PIO3_19 — General-purpose digital input/output pin.

I/O FC8_RTS_SCL_SSEL1 — Flexcomm 8: USART request-to-send,

I2C clock, SPI slave select 1.

I/O SD_D[7] — SD/MMC data 7.

O

I

CT4_MAT1 — Match output 1 from Timer 4.

CAN0_RD — Receiver input for CAN 0.

SCT0_OUT6 — SCTimer/PWM output 6.

O

[2]

PIO3_20

N2

Z

I/O PIO3_20 — General-purpose digital input/output pin.

I/O FC9_SCK — Flexcomm 9: USART or SPI clock.

I

SD_CARD_INT_N —

O

CLKOUT — Output of the CLKOUT function.

R — Reserved.

O

SCT0_OUT7 — SCTimer/PWM output 7.

[4]

PIO3_21/

ADC0_9

P5

I/O; PIO3_21/ADC0_9 — General-purpose digital input/output pin. ADC

AI

input channel 9 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC9_RXD_SDA_MOSI — Flexcomm 9: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

SD_BACKEND_PWR — SD/MMC back-end power supply for

embedded device.

O

I

CT4_MAT3 — Match output 3 from Timer 4.

UTICK_CAP2 — Micro-tick timer capture input 2.

[4]

[3]

PIO3_22/

ADC0_10

N5

C2

Z

I/O; PIO3_22/ADC0_10 — General-purpose digital input/output pin. ADC

AI

input channel 10 if the DIGIMODE bit is set to 0 in the IOCON register

for this pin.

I/O FC9_TXD_SCL_MISO — Flexcomm 9: USART transmitter, I2C clock,

SPI master-in/slave-out data.

PIO3_23

PIO3_24

I/O PIO3_23 — General-purpose digital input/output pin.

I/O FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

R — Reserved.

I

UTICK_CAP3 — Micro-tick timer capture input 3.

[3]

E2

Z

I/O PIO3_24 — General-purpose digital input/output pin.

I/O FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send,

I2C clock, SPI slave select 1.

I

CT4_CAP0 — Capture input 4 to Timer 0.

USB0_VBUS — Monitors the presence of USB0 bus power.

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO3_25

P9

Z

I/O PIO3_25 — General-purpose digital input/output pin.

R — Reserved.

I

CT4_CAP2 — Capture input 2 to Timer 4.

I/O FC4_SCK — Flexcomm 4: USART or SPI clock.

R — Reserved.

O

EMC_A[14] — External memory interface address 14.

[2]

PIO3_26

K5

Z

I/O PIO3_26 — General-purpose digital input/output pin.

R — Reserved.

O

SCT0_OUT0 — SCTimer/PWM output 0.

I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

R — Reserved.

O

EMC_A[15] — External memory interface address 15.

[2]

PIO3_27

P14

Z

I/O PIO3_27 — General-purpose digital input/output pin.

R — Reserved.

O

SCT0_OUT1 — SCTimer/PWM output 1.

I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock,

SPI master-in/slave-out data.

R — Reserved.

O

EMC_A[16] — External memory interface address 16.

[2]

PIO3_28

M11

Z

I/O PIO3_28 — General-purpose digital input/output pin.

R — Reserved.

O

SCT0_OUT2 — SCTimer/PWM output 2.

I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

R — Reserved.

O

EMC_A[17] — External memory interface address 17.

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO3_29

PIO3_30

PIO3_31

PIO4_0

L13

K13

J14

H13

Z

I/O PIO3_29 — General-purpose digital input/output pin.

R — Reserved.

O

SCT0_OUT3 — SCTimer/PWM output 3.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send,

I2C clock, SPI slave select 1.

R — Reserved.

O

EMC_A[18] — External memory interface address 18.

I/O PIO3_30 — General-purpose digital input/output pin.

I/O FC9_CTS_SDA_SSEL0 — Flexcomm 9: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

SCT0_OUT4 — SCTimer/PWM output 4.

I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.

R — Reserved.

O

EMC_A[19] — External memory interface address 19.

I/O PIO3_31 — General-purpose digital input/output pin.

I/O FC9_RTS_SCL_SSEL1 — Flexcomm 9: USART request-to-send,

I2C clock, SPI slave select 1.

O

SCT0_OUT5 — SCTimer/PWM output 5.

CT4_MAT2 — Match output 2 from Timer 4.

R — Reserved.

I

SCT0_GPI0 — Pin input 0 to SCTimer/PWM.

EMC_A[20] — External memory interface address 20.

O

I/O PIO4_0 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_CTS_SDA_SSEL0 — Flexcomm 6: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

CT4_CAP1 — Capture input 4 to Timer 1.

R — Reserved.

I

SCT0_GPI1 — Pin input 1 to SCTimer/PWM.

O

EMC_CSN[1] — External memory interface static chip select 1(active

low).

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO4_1

G14

Z

I/O PIO4_1 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.

R — Reserved.

I

SCT0_GPI2 — Pin input 2 to SCTimer/PWM.

O

EMC_CSN[2] — External memory interface static chip select 2 (active

low).

[2]

PIO4_2

F14

Z

I/O PIO4_2 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART receiver, I2C

data I/O, SPI master-out/slave-in data, I2S data I/O.

R — Reserved.

I

SCT0_GPI3 — Pin input 3 to SCTimer/PWM.

O

EMC_CSN[3] — External memory interface static chip select 3 (active

low).

[2]

PIO4_3

F13

Z

I/O PIO4_3 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C

clock, SPI master-in/slave-out data I/O, I2S word-select/frame.

I

CT0_CAP3 — Capture 3 input to Timer 0.

R — Reserved.

I

SCT0_GPI4 — Pin input 4 to SCTimer/PWM.

O

EMC_DYCSN[2] — External Memory interface SDRAM chip select 2

(active low).

[2]

PIO4_4

D9

Z

I/O PIO4_4 — General-purpose digital input/output pin.

R — Reserved.

I/O FC4_SSEL3 — Flexcomm 4: SPI slave select 3.

I/O FC0_RTS_SCL_SSEL1 — Flexcomm 0: USART request-to-send,

I2C clock, SPI slave select 1.

R — Reserved.

I

SCT0_GPI5 — Pin input 5 to SCTimer/PWM.

O

EMC_DYCSN[3] — External Memory interface SDRAM chip select 3

(active low).

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO4_5

E10

Z

I/O PIO4_5 — General-purpose digital input/output pin.

R — Reserved.

I/O FC9_CTS_SDA_SSEL0 — Flexcomm 9: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I/O FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

O

I

CT4_MAT3 — Match output 3 from Timer 4.

SCT0_GPI6 — Pin input 6 to SCTimer/PWM.

O

EMC_CKE[2] — External memory interface SDRAM clock enable 2.

[2]

PIO4_6

D10

Z

I/O PIO4_6 — General-purpose digital input/output pin.

R — Reserved.

I/O FC9_RTS_SCL_SSEL1 — Flexcomm 9: USART request-to-send,

I2C clock, SPI slave select 1.

R — Reserved.

I

SCT0_GPI7 — Pin input 7 to SCTimer/PWM.

O

EMC_CKE[3] — External memory interface SDRAM clock enable 3.

[2][8]

PIO4_7

PIO4_8

PIO4_9

A14

B14

A12

Z

I/O PIO4_7 — General-purpose digital input/output pin.

R — Reserved.

I

CT4_CAP3 — Capture input 3 to Timer 4.

O

USB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS

must be driven).

O

I

USB0_FRAME — USB0 frame toggle signal.

SCT0_GPI0 — Pin input 0 to SCTimer/PWM.

[2]

I/O PIO4_8 — General-purpose digital input/output pin.

ENET_TXD0 — Ethernet transmit data 0.

I/O FC2_SCK — Flexcomm 2: USART or SPI clock.

O

I

USB0_OVERCURRENTN — USB0 bus overcurrent indicator (active

low).

O

I

USB0_LEDN — USB0-configured LED indicator (active low).

SCT0_GPI1 — Pin input 1 to SCTimer/PWM.

[2][8]

I/O PIO4_9 — General-purpose digital input/output pin.

ENET_TXD1 — Ethernet transmit data 1.

O

I/O FC2_RXD_SDA_MOSI — Flexcomm 2: USART receiver, I2C data

I/O, SPI master-out/slave-in data.

O

USB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS

must be driven).

O

I

USB1_FRAME — USB1 frame toggle signal.

SCT0_GPI2 — Pin input 2 to SCTimer/PWM.

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO4_10

PIO4_11

PIO4_12

B9

A9

A6

Z

I/O PIO4_10 — General-purpose digital input/output pin.

I

ENET_RX_DV — Ethernet receive data valid.

I/O FC2_TXD_SCL_MISO — Flexcomm 2: USART transmitter, I2C clock,

SPI master-in/slave-out data.

I

USB1_OVERCURRENTN — USB1 bus overcurrent indicator (active

low).

O

USB1_LEDN — USB1-configured LED indicator (active low).

SCT0_GPI3 — Pin input 3 to SCTimer/PWM.

I/O PIO4_11 — General-purpose digital input/output pin.

ENET_RXD0 — Ethernet receive data 0.

I

I/O FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C

data I/O, SPI Slave Select 0.

I

USB0_IDVALUE — Indicates to the transceiver whether connected

as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH).

R — Reserved.

I

SCT0_GPI4 — Pin input 4 to SCTimer/PWM.

I/O PIO4_12 — General-purpose digital input/output pin.

ENET_RXD1 — Ethernet receive data 1.

I

I/O FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send,

I2C clock, SPI slave select 1.

R — Reserved.

I

SCT0_GPI5 — Pin input 5 to SCTimer/PWM.

[2]

PIO4_13

PIO4_14

B6

B5

Z

I/O PIO4_13 — General-purpose digital input/output pin.

O

ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

CT4_MAT0 — Match output 0 from Timer 4.

R — Reserved.

I

SCT0_GPI6 — Pin input 6 to SCTimer/PWM.

[2]

I/O PIO4_14 — General-purpose digital input/output pin.

I

ENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet

Reference Clock (RMII interface).

O

CT4_MAT1 — Match output 1 from Timer 4.

I/O FC9_SCK — Flexcomm 9: USART or SPI clock.

R — Reserved.

I

SCT0_GPI7 — Pin input 7 to SCTimer/PWM.

USB1 analog 3.3 V ground.

USB1_AVSSC

USB1_REXT

USB1_ID

F2

F1

G1

USB1 analog signal for reference resistor, 12.4 k +/-1%

Indicates to the transceiver whether connected as an A-device

(USB1_ID LOW) or B-device (USB1_ID HIGH).

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LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

[6][8]

USB1_VBUS

G2

I/O VBUS pin (power on USB cable). 5 V tolerant when USB1_AVDD3V3

and USB1_AVDDTX3V3 = 0 V.

USB1_AVDDC3V3

USB1_AVDDTX3V3

USB1_DP

G3

H1

H3

H2

J1

USB1 analog 3.3 V supply.

USB1 analog 3.3 V supply for line drivers.

I/O USB1 bidirectional D+ line.

I/O USB1 bidirectional D- line.

USB1 analog ground for line drivers.

I/O USB0 bidirectional D+ line.

I/O USB0 bidirectional D- line.

[6]

USB1_DM

USB1_AVSSTX3V3

USB0_DP

[6]

[5]

E5

D5

N13

USB0_DM

RESETN

External reset input: A LOW on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and the boot code

to execute. Wakes up the part from deep power-down mode.

VDD

A4

-

Single 2.7 V to 3.6 V power supply powers internal digital functions

and I/Os.

E6;

E8;

F5;

G5;

J12;

L6;

L11

VSS

B3;

D7;

D8;

E11;

H5;

J5;

-

Ground.

K7

VDDA

N6

N4

P6

L5

-

Analog supply voltage.

ADC negative reference voltage.

ADC positive reference voltage.

Analog ground.

VREFN

VREFP

VSSA

[7]

XTALIN

XTALOUT

VBAT

K4

J4

Main oscillator input.

Main oscillator output.

N11

Battery supply voltage. If no battery is used, tie VBAT to VDD or to

ground.

RTCXIN

L12

-

RTC oscillator input.

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32-bit ARM Cortex-M4 microcontroller

Table 4.

Symbol

Pin description …continued

Description

RTCXOUT

K11

-

I

RTC oscillator output.

Flash Enable

N7;

C4

PU

Flash Enable — Enables the internal serial flash memory. Pins C4

and N7 must be connected to each other.

N.C.

K8;

L9;

-

Not Connected pins — These pins must be left unconnected

(floating).

M7;

M9;

M13

[1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to V_DD). Z = high impedance; pull-up or pull-down disabled, AI = analog

input, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation. For pin states in the

different power modes, see Section 6.2.2 “Pin states in different power modes”. For termination on unused pins, see Section 6.2.1

“Termination of unused pins”.

[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if V_DDpresent; if V_DDnot present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength. See Figure 39. Pulse width of spikes or glitches suppressed by input

filter is from 3 ns to 16 ns (simulated value).

[3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode

Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not

disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

[4] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[5] Reset pad.5 V tolerant pad with glitch filter with hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to

20 ns (simulated value)

[6] 5 V tolerant transparent analog pad.

[7] The oscillator input pin (XTALIN) cannot be driven by an external clock. Must connect a crystal between XTALIN and XTALOUT.

[8] VBUS must be connected to supply voltage when using the USB peripheral.

[9] Z = high impedance; pull-up or pull-down disabled. GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3, PIO0_4, PIO0_5, and PIO0_6 have

the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will be floating by default. If unused, it is recommended to

externally terminate this pins to prevent leakage.

6.2.1 Termination of unused pins

Table 5 shows how to terminate pins that are not used in the application. In many cases,

unused pins should be connected externally or configured correctly by software to

minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with their

internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the

GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0

to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

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NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

Table 5.

Termination of unused pins

Default Recommended termination of unused pins

state^[1][2]

RESET

I; PU

The RESET pin can be left unconnected if the application does not use it.

all PIOn_m (not open-drain) I; Z

Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain)

IA

Can be left unconnected if driven LOW and configured as GPIO output by

software.

RTCXIN

RTCXOUT

XTALIN

XTALOUT

VREFP

VREFN

VDDA

-

F

Connect to ground. When grounded, the RTC oscillator is disabled.

Can be left unconnected.

Connect to ground. When grounded, the RTC oscillator is disabled.

Can be left unconnected.

Tie to VDD.

Tie to VSS.

Tie to VDD.

VSSA

Tie to VSS.

VBAT

Tie to VDD.

USBn_DP

Can be left unconnected. If USB interface is not used, pin can be left unconnected

except in deep power-down mode where it must be externally pulled low. When the

USB PHY is disabled, the pins are floating.

USBn_DM

F

Can be left unconnected. If USB interface is not used, pin can be left unconnected

except in deep power-down mode where it must be externally pulled low. When the

USB PHY is disabled, the pins are floating.

USB1_AVSCC

USB1_VBUS

F

Tie to VSS.

Tie to VDD.

USB1_AVDDC3V3

USB1_AVDDTX3V3

USB1_AVSSTX3V3

USB1_ID

Tie to VDD.

Tie to VSS.

Can be left unconnected. If USB interface is not used, pin can be left unconnected.

[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating

[2] Z = high impedance; pull-up or pull-down disabled. GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3, PIO0_4, PIO0_5, and PIO0_6 have

the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will be floating by default. If unused, it is recommended to

externally terminate this pins to prevent leakage.

6.2.2 Pin states in different power modes

Table 6.

Pin states in different power modes

Active

Sleep

Deep-sleep

Deep

power-down^[3]

PIOn_m pins (not I2C)

As configured in the IOCON^[1]. Default: internal pull-up enabled Floating

or high Z ^[2]

.

PIO0_13 to PIO0_14 (open-drain As configured in the IOCON^[1].

I2C-bus pins)

Floating

PIO3_23 to PIO3_24 (open-drain As configured in the IOCON^[1].

I2C-bus pins)

Floating

RESET

Reset function enabled. Default: input, internal pull-up enabled.

Reset function disabled.

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[1] Default and programmed pin states are retained in sleep and deep-sleep.

[2] Z = high impedance; pull-up or pull-down disabled. GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3, PIO0_4, PIO0_5, and PIO0_6 have

the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will be floating by default. If unused, it is recommended to

externally terminate this pins to prevent leakage.

[3] If VBAT> VDD, the external reset pin must be floating to prevent high VBAT leakage.

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7. Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses allow for concurrent code and data

accesses from different slave ports.

The LPC54018JxM/LPC54S018JxM uses a multi-layer AHB matrix to connect the ARM

Cortex-M4 buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slave ports of the matrix to be

accessed simultaneously by different bus masters.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M4 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and

divide, interruptable/continuable multiple load and store instructions, automatic state save

and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt

controller, and multiple core buses capable of simultaneous accesses.

A 3-stage pipeline is employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

7.3 ARM Cortex-M4 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and

accumulate, and square root operations. It also provides conversions between fixed-point

and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the

ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to

as the IEEE 754 standard.

7.4 Memory Protection Unit (MPU)

The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve

the reliability of an embedded system by protecting critical data within the user

application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to eight regions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

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7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4

The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

• Supports up to 54 vectored interrupts.

• Eight programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

7.6 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a

dedicated SYSTICK exception. The clock source for the SysTick can be the FRO or the

Cortex-M4 core clock.

7.7 On-chip serial flash

The LPC54018JxM/LPC54S018JxM supports up to 4 MB of on-chip Quad SPI Serial

Flash (connected on SPIFI interface).

7.8 On-chip static RAM

The LPC54018JxM/LPC54S018JxM support 360 kB SRAM with separate bus master

access for higher throughput and individual power control for low-power operation.

7.9 On-chip ROM

The 64 kB on-chip ROM contains the boot loader and the following Application

Programming Interfaces (API):

• In-Application Programming (IAP) and In-System Programming (ISP).

• ROM-based USB drivers (HID, CDC, MSC, and DFU).

• Supports serial interface booting (UART, I2C, SPI) from an application processor,

automated booting from NOR flash (SPI, quad SPIFI, 8/16/32-bit external parallel

flash), and USB booting (full-speed, high speed).

• Execute in place (XIP) from SPIFI NOR flash (in quad, dual SPIFI mode or single-bit

SPI mode), and parallel NOR flash.

• FRO API for selecting FRO output frequency.

• OTP API for programming OTP memory.

• Random Number Generator (RNG) API.

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• RSA API calls (LPC54S018Jx only).

• Secure Boot features on LPC54S018Jx devices:

– Supports boot image authentication using RSASSA-PKCS1-v1_5 signature

verification with 2048-bit public keys (2048-bit modulus, 32-bit exponent).

– Supports Root of Trust (RoT) establishment by comparing the SHA-256 hash

digest of the RoT public key with OTP memory contents.

– Supports secure anti-rollback of images through revocation of image key

certificate. Supports up to 8 revocations through OTP fuses.

– Supports boot of AES-GCM encrypted images with a 128-bit symmetric key stored

in OTP memory or a 256-bit symmetric key stored using on-chip SRAM PUF.

– Secure Authentication Only Boot. Enforce booting of RSA-2048 signed images

only.

– Encrypted Image Boot. Enforce booting of AES-GCM encrypted images only.

– Enhanced Image Boot. Enforce booting of encrypted then signed images only.

7.10 Memory mapping

The LPC54018JxM/LPC54S018JxM incorporates several distinct memory regions. The

APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.Each

peripheral is allocated 4 kB of space simplifying the address decoding. The registers

incorporated into the CPU, such as NVIC, SysTick, and sleep mode control, are located

on the private peripheral bus.

The ARM Cortex-M4 processor has a single 4 GB address space. The following table

shows how this space is used on the LPC54018JxM/LPC54S018JxM.

Table 7.

Memory usage and details

General Use

Address range

Address range details and description

0x0000 0000 to 0x1FFF FFFF SRAMX

Boot ROM

0x0000 0000 - 0x0002 FFFF I&D SRAM bank (192 kB).

0x0300 0000 - 0x0300 FFFF Boot ROM with API services in a 64 kB

space.

On-chip Serial

0x1000 0000 - 0x103F FFFF Serial flash memory mapped access

space (4 MB).

Flash Memory

(connected to

SPIFI interface)

0x2000 0000 to 0x3FFF FFFF Main SRAM

Banks

0x2000 0000 - 0x2002 7FFF SRAM0, SRAM1, SRAM2, SRAM3

banks (Total 160 kB).

SRAM bit band 0x2200 0000 - 0x23FF FFFF SRAM bit band alias addressing

alias addressing

(32 MB).

SRAM Bank

0x4010 0000 0x4010 2000

USB SRAM (8 kB).

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Table 7.

Memory usage and details …continued

Address range

General Use

Address range details and description

0x4000 0000 to 0x7FFF FFFF APB peripherals 0x4000 0000 - 0x4001 FFFF APB slave group 0 up to 32 peripheral

blocks of 4 kB each (128 kB).

0x4002 0000 - 0x4003 FFFF APB slave group 1 up to 32 peripheral

blocks of 4 kB each (128 kB).

0x4004 0000 - 0x4005 FFFF APB asynchronous slave group 2 up to

32 peripheral blocks of 4 kB each

(128 kB).

AHB peripherals 0x4008 0000 - 0x400B FFFF AHB peripherals (256 kB).

Peripheral bit

band alias

0x4200 0000 - 0x43FF FFFF Peripheral bit band alias addressing

(32 MB).

addressing

0x8000 0000 to 0xDFFF FFFF Off-chip Memory Four static memory chip selects:

via the External

0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64

Memory

Controller

MB)^[1]

0x8800 0000 - 0x8BFF FFFF Static memory chip select 1 (up to 64

MB)^[2]

0x9000 0000 – 0x93FF FFFF Static memory chip select 2 (up to 64

MB).

0x9800 0000 - 0x9BFF FFFF Static memory chip select 3 (up to 64

MB).

Four dynamic memory chip selects:

0xA000 0000 - 0xA7FF FFFF Dynamic memory chip select 0 (up to

256 MB).

0xA800 0000 - 0xAFFF FFFF Dynamic memory chip select 1 (up to

256 MB).

0xB000 0000 - 0xB7FF FFFF Dynamic memory chip select 2 (up to

256 MB).

0xB800 0000 - 0xBFFF FFFF Dynamic memory chip select 3 (up to

256 MB).

0xE000 0000 to 0xE00F FFFF Cortex-M4

Private

0xE000 0000 - 0xE00F FFFF Cortex-M4 related functions, includes

the NVIC and System Tick Timer.

Peripheral Bus

[1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See the

EMCSYSCTRL register bit 0 in the LPC54018JxM/LPC54S018JxM user manual.

[2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See the

EMCSYSCTRL register bit 0 in the LPC54018JxM/LPC54S018JxM user manual.

Figure 4 shows the overall map of the entire address space from the user program

viewpoint following reset.

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Memory space

AHB peripherals

0xFFFF FFFF

(reserved)

private peripheral bus

(EMC)

0x4010 BFFF

0x4010 2000

0x4010 0000

0xE010 0000

0xE000 0000

0x8000 0000

0x4400 0000

(reserved)

USB SRAM (8 kB)

(reserved)

0x400A 5000

0x400A 4000

0x400A 3000

0x400A 2000

0x400A 1000

0x400A 0000

0x4009 F000

0x4009 E000

0x4009 D000

0x4009 C000

0x4009 B000

0x4009 A000

0x4009 9000

0x4009 8000

0x4009 7000

0x4009 6000

0x4009 5000

0x4009 4000

0x4009 2000

0x4009 1000

SHA registers

peripheral

bit-band addressing

HS USB host registers

FS USB host registers

0x4200 0000

0x4010 C000

(reserved)

AES256

ADC

AHB

peripheral

0x4008 0000

0x4006 0000

Flexcomm 10

(reserved)

CAN 1

CAN 0

Asynchronous

APB peripherals

0x4004 0000

0x4002 0000

see APB

memory

map figure

(reserved)

SDIO

APB peripherals on

APB bridge 1

Flexcomm 9

Flexcomm 8

APB peripherals on

APB bridge 0

0x4000 0000

0x2400 0000

Flexcomm 7

Flexcomm 6

(reserved)

SRAM bit-band

addressing

Flexcomm 5

0x2200 0000

0x2002 8000

0x2002 0000

CRC engine

(reserved)

HS USB device

Ethernet

SRAM3

(up to 32 kB)

(reserved)

SRAM2

(up to 32 kB)

DMIC interface

High Speed GPIO

(reserved)

0x4009 0000

0x4008 C000

0x4008 B000

0x4008 A000

0x4008 9000

0x4008 8000

0x4008 7000

0x4008 6000

0x4008 5000

0x4008 4000

0x4008 3000

0x4008 2000

0x4008 1000

0x4008 0000

0x2001 8000

0x2001 0000

SRAM1

(up to 32 kB)

SRAM0

(up to 64 kB)

Flexcomm 4

Flexcomm 3

0x2000 0000

0x1040 0000

(reserved)

Flexcomm 2

On-chip Serial Flash

(up to 4 MB)

Flexcomm 1

Flexcomm 0

0x1000 0000

0x0301 0000

(reserved)

Boot ROM

SC Timer / PWM

FS USB device registers

0x0300 0000

0x0003 0000

LCD registers

DMA registers

(reserved)

SRAMX (192 kB)

EMC registers

SPIFI registers

0x0000 0000

0x0000 00C0

0x0000 0000

active interrupt vectors

aaa-030340-x

The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.

Fig 4. LPC54018JxM/LPC54S018JxM Memory mapping

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APB bridge 1

APB bridge 0

0x4003 FFFF

31-28

27

(reserved)

PUF

0x4003 C000

0x4003 B000

0x4003 A000

0x4003 8000

0x4003 7000

0x4003 6000

0x4002 E000

0x4002 D000

0x4001 FFFF

0x4001 6000

0x4001 5000

(reserved)

OTP controller

(reserved)

Micro-Tick

MRT

31-22

21

26

25-24

RNG

(reserved)

20-15

14

0x4001 F000

0x4000 E000

0x4000 D000

0x4000 C000

0x4000 A000

0x4000 9000

0x4000 8000

23

22

21-14

13

Smart card 1

Smart card 0

(reserved)

RIT

13

WDT

12

(reserved)

11-10

9

12

11-9

8

RTC

(reserved)

0x4002 C000

0x4002 9000

CTIMER1

CTIMER0

CTIMER2

(reserved)

8

0x4002 8000

0x4002 0000

7-0

(reserved)

Input muxes

7

6

5

4

3

2

1

0

0x4000 7000

0x4000 6000

0x4000 5000

Pin Interrupts (PINT)

0x4000 4000

Asynchronous APB bridge

GINT1

0x4000 3000

0x4000 2000

0x4000 1000

0x4000 0000

0x4005 FFFF

GINT0

IOCON

Syscon

(reserved)

CTIMER4

31-10

0x4004 A000

0x4004 9000

0x4004 8000

0x4004 1000

0x4004 0000

aaa-030341

9

8

CTIMER3

(reserved)

7-1

0

Asynch. Syscon

Fig 5. LPC54018JxM/LPC54S018JxM APB Memory map

7.11 One-Time Programmable (OTP) memory

The OTP memory contains four memory banks of 128 bits each. The first memory bank

(OTP Bank 0) is reserved. The other three OTP banks are programmable. In LPC54018Jx

devices, OTP banks 1 and 2 are available for storing general purpose data. In

LPC54S018Jx devices, OTP banks 1 and 2 are used for storing the AES keys. OTP bank

3 is used for customer programmable device configuration data.

7.11.1 Features

• The OTP memory stores user settings in bank 3, register 0 to configure:

– ISP and boot source modes

– Secure boot

– SPIFI boot delay

– Customer definable bits

• Root of Trust (RoT) hash digest for secure authenticated boot (OTP Banks 1, 2).

• Scrambled 128-bit AES key for secure encrypted boot (OTP Bank 2).

• USB Vendor and Product IDs (OTP Bank 2).

• Boot ROM API support for programming the OTP memory provided.

Remark: OTP programming requires a supply voltage of at least 3.3 V. To use the OTP

API, the main system clock must be running from the 12 MHz clock.

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7.12 System control

7.12.1 Clock sources

The LPC54018JxM/LPC54S018JxM supports one external and two internal clock

sources:

• Free Running Oscillator (FRO).

• Watchdog oscillator (WDOSC).

• Crystal oscillator.

7.12.1.1 Free Running Oscillator (FRO)

The FRO 12 MHz oscillator provides the default clock at reset and provides a clean

system clock shortly after the supply pins reach operating voltage.

• 12 MHz internal FRO oscillator, factory trimmed for accuracy, that can optionally be

used as a system clock as well as other purposes.

• Selectable 48 MHz or 96 MHz FRO oscillator, factory trimmed for accuracy, that can

optionally be used as a system clock as well as other purposes.

7.12.1.2 Watchdog oscillator (WDOSC)

The watchdog oscillator is a low-power internal oscillator. The WDOSC can be used to

provide a clock to the WWDT and to the entire chip. The low-power watchdog oscillator

provides a selectable frequency in the range of 6 kHz to 1.5 MHz. The accuracy of this

clock is limited to  40% over temperature, voltage, and silicon processing variations.

7.12.1.3 Crystal oscillator

The LPC54018JxM/LPC54S018JxM include four independent oscillators. These are the

main oscillator, the FRO, the watchdog oscillator, and the RTC oscillator.

Following reset, the LPC54018JxM/LPC54S018JxM will operate from the Internal FRO

until switched by software. This allows systems to operate without any external crystal

and the boot loader code to operate at a known frequency. See Figure 6 and Figure 7 for

an overview of the LPC54018JxM/LPC54S018JxM clock generation.

7.12.2 System PLL (PLL0)

The system PLL accepts an input clock frequency in the range of 32.768 kHz to 25 MHz.

The input frequency is multiplied up to a high frequency with a Current Controlled

Oscillator (CCO).

The PLL can be enabled or disabled by software.

7.12.3 USB PLL (PLL1)

The USB PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO).

The PLL can be enabled or disabled by software.

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7.12.4 Audio PLL (PLL2)

The audio PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO).

The PLL can be enabled or disabled by software.

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7.12.5 Clock Generation

00

01

10

to CPU, AHB bus,

Sync APB

“none”

CPU CLOCK

DIVIDER

pll_clk

fro_12m

00

32k_clk

(1)

main_clk

11

clk_in

01

to EMC

(function

clock)

EMC ClOCK

DIVIDER

AHBCLKDIV

wdt_clk

10

Main clock select B

MAINCLKSELB[1:0]

fro_hf

11

(1)

fro_hf

pll_clk

usb_pll_clk

audio_pll_clk

“none”

EMCCLKDIV

000

001

010

011

111

Main clock select A

MAINCLKSELA[1:0]

to ADC

ADC CLOCK

DIVIDER

fro_12m

clk_in

000

001

ADCCLKDIV

ADC clock select

ADCCLKSEL[2:0]

32k_clk

“none”

pll_clk

SYSTEM PLL

011

111

fro_hf

System PLL

settings

000

001

010

111

to USB0

(FS USB)

PLL clock select

SYSPLLCLKSEL[2:0]

pll_clk

usb_pll_clk

“none”

USB0 CLOCK

DIVIDER

xtalin

xtalout

USB0CLKDIV

clk_in

Crystal

oscillator

USB0 clock select

USB0CLKSEL[2:0]

Range select

SYSOSCCTRL[1:0]

main_clk

000

001

010

111

pll_clk

usb_pll_clk

“none”

to USB1 PHY

USB1 CLOCK

DIVIDER

fro_hf

fro_hf_div

FRO Clock

Divider

USB1CLKDIV

USB1 clock select

USB1CLKSEL[2:0]

FROHFCLKDIV

USB PLL

usb_pll_clk

clk_in

fro_12

to DMIC

000

001

010

011

100

101

fro_hf_div

audio_pll_clk

mclk_in

subsystem

DMIC CLOCK

DIVIDER

USB PLL

settings

main_clk

wdt_in

DMICCLKDIV

fro_12m

clk_in

000

001

111

“none”

audio_pll_clk

111

Audio PLL

“none”

DMIC clock select

DMICCLKSEL[2:0]

AUDIO PLL Settings

Audio clock select

AUDPLLCKSEL[2:0]

fro_hf_div

to MCLK pin

(output)

000

001

audio_pll_clk

“none”

MCLK

DIVIDER

main_clk

111

00

fro_12m

01

audio_pll_clk

10

to Async APB

MCLKDIV

MCLK clock select

MCLKCLKSEL[1:0]

fc6_fclk

(1)

11

main_clk

000

001

010

011

100

APB clock select B

ASYNCAPBCLKSELA[1:0]

pll_clk

usb_pll_clk

fro_hf

to SDIO

(function clock)

SDIO CLOCK

DIVIDER

audio_pll_clk

SDIOCLKDIV

“none”

111

(1): synchronized multiplexer,

see register descriptions for details.

SDIO clock select

SDIOCLKSEL[2:0]

aaa-029067

Fig 6. LPC54018JxM/LPC54S018JxM clock generation

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(1 per Flexcomm)

main_clk

000

fro_12m

000

001

010

011

100

111

pll_clk

001

fcn_fclk

fro_hf_div

audio_pll_clk

mclk_in

(function clock

of Flexcomm[0-9])

fro_12m

010

fro_hf

011

“none”

111

(up to 11 Flexcomm

Interfaces on these

devices)

FRG CLOCK

DIVIDER

frg_clk

“none”

to MCAN0

main_clk

function clock

MCAN0 clock

divider

FRGCTRL[15:0]

FRG clock select

FRGCLKSEL[2:0]

FCLKSEL[0-9]

to CLK32K of all Flexcomms (fc0-fc9)

32k_clk

CAN0CLKDIV

to MCAN1

function clock

MCAN1 clock

divider

main_clk

000

001

010

011

100

111

fcn_fclk

(function clock

of Flexcomm10)

pll_clk

usb_pll_clk

fro_hf

audio_pll_clk

“none”

CAN1CLKDIV

to Smartcard0

function clock

main_clk

Smartcard0

clock divider

FCLKSEL10

SC0CLKDIV

to Smartcard1

function clock

main_clk

pll_clk

000

001

010

011

111

to SCTimer/PWM

input clock 7

Smartcard1

clock divider

SCTimer/PWM

fro_hf

audio_pll_clk

“none”

Clock Divider

SC1CLKDIV

SCTCLKDIV

to ARM Trace

function clock

SCT clock select

SCTCLKSEL[2:0]

main_clk

ARM Trace

clock divider

ARMTRACECLKDIV

main_clk

lcdclkin

fro_hf

00

01

10

11

to LCD

(function clock)

LCD CLOCK

DIVIDER

“none”

main_clk

pll_clk

usb_pll_clk

000

001

010

011

100

111

LCDCLKDIV

to SPIFI

(function clock)

LCD clock select

LCDCLKSEL[1:0]

SPIFI CLOCK

DIVIDER

fro_hf

audio_pll_clk

“none”

SPIFI CLKDIV

main_clk

clk_in

wdt_clk

SPIFI clock select

SPIFICLKSEL[2:0]

000

001

010

011

100

101

fro_hf

pll_clk

usb_pll_clk

to Cortex-M4

System Tick

Timer

main_clk

CLKOUT

Systick Clock

Divider

CLKOUT

000

wdt_clk

001

DIVIDER

32k_clk

010

audio_pll_clk

32k_clk

CLKOUTDIV

SYSTICKCLKDIV

fro_12

110

111

011

“none”

111

CLKOUT select

CLKOUTSEL[2:0]

Systic clock select

SYSTICKCLKSEL[2:0]

aaa-029070

Fig 7. LPC54018JxM/LPC54S018JxM clock generation (continued)

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7.12.6 Brownout detection

The LPC54018JxM/LPC54S018JxM includes a monitor for the voltage level on the V_DD

pin. If this voltage falls below a fixed level, the BOD sets a flag that can be polled or cause

an interrupt. In addition, a separate threshold level can be selected to cause chip reset.

7.12.7 Safety

The LPC54018JxM/LPC54S018JxM includes a Windowed WatchDog Timer (WWDT),

which can be enabled by software after reset. Once enabled, the WWDT remains locked

and cannot be modified in any way until a reset occurs.

7.13 Power control

The LPC54018JxM/LPC54S018JxM support a variety of power control features. In Active

mode, when the chip is running, power and clocks to selected peripherals can be adjusted

for power consumption. In addition, there are three special modes of processor power

reduction with different peripherals running: sleep mode, deep-sleep mode, and deep

power-down mode that can be activated using the power API library from the SDK

software package.

7.13.1 Sleep mode

In sleep mode, the system clock to the CPU is stopped and execution of instructions is

suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be

clocked can continue operation during Sleep mode and may generate interrupts to cause

the processor to resume execution. Sleep mode eliminates dynamic power used by the

processor itself, memory systems and related controllers, internal buses, and unused

peripherals. The processor state and registers, peripheral registers, and internal SRAM

values are maintained, and the logic levels of the pins remain static.

7.13.2 Deep-sleep mode

In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All

analog blocks are powered down by default but can be selected to keep running through

the power API if needed as wake-up sources. The main clock and all peripheral clocks are

disabled by default. The FRO is disabled.

Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power

used by the processor itself, memory systems and related controllers, and internal buses.

The processor state and registers, peripheral registers, and internal SRAM values are

maintained, and the logic levels of the pins remain static.

GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB0,

USB1, DMIC, SPI, I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left

running in deep sleep mode The FRO, RTC oscillator, and the watchdog oscillator can be

left running.In some cases, DMA can operate in deep-sleep mode.

7.13.3 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the RTC power

domain and the RESET pin. The LPC54018JxM/LPC54S018JxM can wake up from deep

power-down mode via the RESET pin and the RTC alarm. The ALARM1HZ flag in RTC

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control register generates an RTC wake-up interrupt request, which can wake up the part.

During deep power-down mode, the contents of the SRAM and registers are not retained.

All functional pins are tri-stated in deep power-down mode.

Table 8 shows the peripheral configuration in reduced power modes.

Table 8.

Peripheral configuration in reduced power modes

Reduced power mode

Peripheral

Sleep

Deep-sleep

Deep power-down

FRO

BOD

PLL

Software configured Software configured

Software configured Off

Off

Watchdog osc and

WWDT

Software configured Software configured

Micro-tick Timer

DMA

Software configured Software configured

Off

Active

Configurable some for operations.

USART

Software configured Off; but can create a wake-up interrupt in synchronous Off

slave mode or 32 kHz clock mode

SPI

Software configured Off; but can create a wake-up interrupt in slave mode Off

I2C

USB0

USB1

Ethernet

DMIC

Software configured Software configured

Software configured Off

Off

Software configured Software configured

Off

Other digital peripherals Software configured Off

Off

RTC oscillator

Software configured Software configured

Software configured

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Table 9 shows wake-up sources for reduced power modes.

Table 9.

Wake-up sources for reduced power modes

Conditions

Power mode Wake-up source

Sleep

Any interrupt

HWWAKE

Enable interrupt in NVIC.

Certain Flexcomm Interface and DMIC subsystem activity.

Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers.

• Enable interrupt in NVIC and STARTER0 registers.

• Enable interrupt in BODCTRL register.

Deep-sleep

Pin interrupts

BOD interrupt

• Configure the BOD to keep running in this mode with the power API.

BOD reset

Enable reset in BODCTRL register.

Watchdog interrupt

• Enable the watchdog oscillator in the PDRUNCFG0 register.

• Enable the watchdog interrupt in NVIC and STARTER0 registers.

• Enable the watchdog in the WWDT MOD register and feed.

• Enable interrupt in WWDT MOD register.

• Configure the WDTOSC to keep running in this mode with the power API.

• Enable the watchdog oscillator in the PDRUNCFG0 register.

• Enable the watchdog and watchdog reset in the WWDT MOD register and feed.

Always available.

Watchdog reset

Reset pin

RTC 1 Hz alarm timer

• Enable the RTC 1 Hz oscillator in the RTCOSCCTRL register.

• Enable the RTC bus clock in the AHBCLKCTRL0 register.

• Start RTC alarm timer by writing a time-out value to the RTC COUNT register.

• Enable the RTCALARM interrupt in the STARTER0 register.

RTC 1 kHz timer

time-out and alarm

• Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL

register.

• Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.

• Enable the RTC wake-up interrupt in the STARTER0 register.

• Enable the watchdog oscillator in the PDRUNCFG0 register.

• Enable the Micro-tick timer clock by writing to the AHBCLKCTRL1 register.

• Start the Micro-tick timer by writing UTICK CTRL register.

• Enable the Micro-tick timer interrupt in the STARTER0 register.

Interrupt from I2C in slave mode.

Micro-tick timer

(intended for ultra-low

power wake-up from

deep-sleep mode

I2C interrupt

SPI interrupt

Interrupt from SPI in slave mode.

USART interrupt

Interrupt from USART in slave or 32 kHz mode.

USB0 need clock

interrupt

Interrupt from USB0 when activity is detected that requires a clock.

USB1 need clock

interrupt

Interrupt from USB1 when activity is detected that requires a clock.

Ethernet interrupt

DMA interrupt

HWWAKE

Interrupt from ethernet.

Interrupt from DMA.

Certain Flexcomm Interface and DMIC subsystem activity.

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Table 9.

Wake-up sources for reduced power modes

Power mode Wake-up source

Conditions

Deep

power-down

RTC 1 Hz alarm timer

• Enable the RTC 1 Hz oscillator in the RTC CTRL register.

• Start RTC alarm timer by writing a time-out value to the RTC COUNT register.

RTC 1 kHz timer

time-out and alarm

• Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTCOSCC-

TRL register.

• Enable the RTC bus clock in the AHBCLKCTRL0 register.

• Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.

Always available.

Reset pin

7.14 General Purpose I/O (GPIO)

The LPC54018JxM/LPC54S018JxM provides a total of 137 GPIO pins.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The current level

of a port pin can be read back no matter what peripheral is selected for that pin.

7.14.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt

request.

• One GPIO group interrupt can be triggered by a combination of any pin or pins.

7.15 Pin interrupt/pattern engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC. The pattern match engine can be used in

conjunction with software to create complex state machines based on pin inputs. Any

digital pin, independent of the function selected through the switch matrix can be

configured through the SYSCON block as an input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the I/O+ bus for fast single-cycle access.

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7.15.1 Features

• Pin interrupts:

– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as

edge-sensitive or level-sensitive interrupt requests. Each request creates a

separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH-active or LOW-active.

– Pin interrupts can wake up the device from sleep mode and deep-sleep mode.

• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute

to a boolean expression. The boolean expression consists of specified levels

and/or transitions on various combinations of these pins.

– Each bit slice minterm (product term) comprising of the specified boolean

expression can generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can also be programmed to generate an RXEV

notification to the CPU. The RXEV signal can be connected to a pin.

– Pattern match can be used in conjunction with software to create complex state

machines based on pin inputs.

– Pattern match engine facilities wake-up only from active and sleep modes.

7.16 Serial peripherals

7.16.1 Full-speed USB Host/Device interface (USB0)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

7.16.1.1 USB0 device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory. The serial

interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

Features

• Supports 10 physical (5 logical) endpoints including two control endpoints.

• Single and double-buffering supported.

• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

• Supports wake-up from reduced power mode on USB activity and remote wake-up.

• Supports SoftConnect.

• Link Power Management (LPM) supported.

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7.16.1.2 USB0 host controller

The host controller enables full- and low-speed data exchange with USB devices attached

to the bus. It consists of register interface, serial interface engine and DMA controller. The

register interface complies with the Open Host Controller Interface (OHCI) specification.

Features

• OHCI compliant.

• Two downstream ports.

7.16.2 High-speed USB Host/Device interface (USB1)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

7.16.2.1 USB1 device controller

The device controller enables 480 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory. The serial

interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

Features

• Fully compliant with USB 2.0 Specification (high speed).

• Supports 8 physical (16 logical) endpoints with up to 8 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• While USB is in the Suspend mode, the LPC54018JxM/LPC54S018JxM can enter

one of the reduced power modes and wake up on USB activity.

• Double buffer implementation for Bulk and Isochronous endpoints.

7.16.2.2 USB1 host controller

The host controller enables high speed data exchange with USB devices attached to the

bus. It consists of register interface and serial interface engine. The register interface

complies with the Enhanced Host Controller Interface (EHCI) specification.

Features

• EHCI compliant.

• Two downstream ports.

• Supports per-port power switching.

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7.16.3 Ethernet AVB

The Ethernet block enables a host to transmit and receive data over Ethernet in

compliance with the IEEE 802.3-2008 standard. The Ethernet interface contains a full

featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to

provide optimized performance through the use of DMA hardware acceleration.

7.16.3.1 Features

• 10/100 Mbit/s

• DMA support

• Power management remote wake-up frame and magic packet detection

• Supports both full-duplex and half-duplex operation

– Supports CSMA/CD Protocol for half-duplex operation.

– Supports IEEE 802.3x flow control for full-duplex operation.

– Optional forwarding of received pause control frames to the user application in

full-duplex operation.

– Supports IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic.

– Software support for AVB feature is available from NXP Professional Services. See

nxp.com for more details.

– Back-pressure support for half-duplex operation.

– Automatic transmission of zero-quanta pause frame on deassertion of flow control

input in full-duplex operation.

• Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE

1588-2008 v2).

7.16.4 SPI Flash Interface (SPIFI)

The SPI Flash Interface is connected to the on-chip serial flash in the

LPC54018JxM/LPC54S018JxM microcontroller with little performance penalty compared

to parallel flash devices with higher pin count.

After a few commands configure the interface at startup, the entire flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Simple sequences of commands handle erasure and

programming.

7.16.4.1 Features

• Connected to on-chip serial flash memory in the main memory map.

• Supports classic and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Quad SPI Flash Interface with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.

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• Supports DMA access.

• Provides XIP (execute in place) feature to execute code directly from on-chip serial

flash.

7.16.5 CAN Flexible Data (CAN FD) interface

The LPC54018JxM/LPC54S018JxM contains two CAN FD interfaces, CAN FD 1 and

CAN FD 2.

7.16.5.1 Features

• Conforms with CAN protocol version 2.0 part A, B and ISO 11898-1.

• CAN FD with up to 64 data bytes supported.

• CAN Error Logging.

• AUTOSAR support.

• SAE J1939 support.

• Improved acceptance filtering.

7.16.6 DMIC subsystem

7.16.6.1 Features

• Pulse-Density Modulation (PDM) data input for left and/or right channels on 1 or 2

buses.

• Flexible decimation.

• 16 entry FIFO for each channel.

• DC blocking or unaltered DC bias can be selected.

• Data can be transferred using DMA from deep-sleep mode without waking up the

CPU, then automatically returning to deep-sleep mode.

• Data can be streamed directly to I²S on Flexcomm Interface 7.

7.16.7 Smart card interface

7.16.7.1 Features

• Two DMA supported ISO 7816 Smart Card Interfaces.

• Both asynchronous protocols, T = 0 and T = 1 are supported.

7.16.8 Flexcomm Interface serial communication

7.16.8.1 Features

• USART with asynchronous operation or synchronous master or slave operation.

• SPI master or slave, with up to 4 slave selects.

• I²C, including separate master, slave, and monitor functions.

• Two I2S functions using Flexcomm Interface 6 and Flexcomm Interface 7.

• Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I²C

function does not use the FIFO.

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7.16.8.2 SPI serial I/O controller

Features

• Maximum data rates of 48 Mbit/s in master mode and 14 Mbit/s in slave mode for SPI

functions. (Flexcomm Interface 0-9).

• Maximum data rates of 50 Mbit/s in master mode and 50 Mbit/s in slave mode for SPI

functions (Flexcomm Interface10).

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or

DMA set-up.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• Four Slave Select input/outputs with selectable polarity and flexible usage.

• Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any

enabled interrupt.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

7.16.8.3 I²C-bus interface

The I²C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example, an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I²C is a multi-master bus and

can be controlled by more than one bus master connected to it.

Features

• All I2Cs support standard, Fast-mode, and Fast-mode Plus with data rates of up to

1 Mbit/s.

• All I2Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s.

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I²C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I²C-bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

• Activity on the I2C in slave mode allows wake-up from deep-sleep mode on any

enabled interrupt.

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7.16.8.4 USART

Features

• Maximum bit rates of 6.25 Mbit/s in asynchronous mode.

• The maximum supported bit rate for USART master synchronous mode is 24 Mbit/s,

and the maximum supported bit rate for USART slave synchronous mode is

12.5 Mbit/s.

• 7, 8, or 9 data bits and 1 or 2 stop bits.

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software address compare.

• RS-485 transceiver output enable.

• Autobaud mode for automatic baud rate detection

• Parity generation and checking: odd, even, or none.

• Software selectable oversampling from 5 to 16 clocks in asynchronous mode.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Loopback mode for testing of data and flow control.

• In synchronous slave mode, wakes up the part from deep-sleep mode.

• Special operating mode allows operation at up to 9600 baud using the 32.768 kHz

RTC oscillator as the UART clock. This mode can be used while the device is in

deep-sleep mode and can wake-up the device when a character is received.

• USART transmit and receive functions work with the system DMA controller.

7.16.8.5 I²S-bus interface

The I²S bus provides a standard communication interface for streaming data transfer

applications such as digital audio or data collection. The I²S bus specification defines a

3-wire serial bus, having one data, one clock, and one word select/frame trigger signal,

providing single or dual (mono or stereo) audio data transfer as well as other

configurations. In the LPC54018JxM/LPC54S018JxM, the I²S function is included in

Flexcomm Interface 6 and Flexcomm Interface 7. Each of the Flexcomm Interface

implements four I²S channel pairs.

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The I²S interface within one Flexcomm Interface provides at least one channel pair that

can be configured as a master or a slave. Other channel pairs, if present, always operate

as slaves. All of the channel pairs within one Flexcomm Interface share one set of I²S

signals, and are configured together for either transmit or receive operation, using the

same mode, same data configuration and frame configuration. All such channel pairs can

participate in a time division multiplexing (TDM) arrangement. For cases requiring an

MCLK input and/or output, this is handled outside of the I²S block in the system level

clocking scheme.

Features

• A Flexcomm Interface may implement one or more I²S channel pairs, the first of which

could be a master or a slave, and the rest of which would be slaves. All channel pairs

are configured together for either transmit or receive and other shared attributes. The

number of channel pairs is defined for each Flexcomm Interface, and may be from 0

to 4.

• Configurable data size for all channels within one Flexcomm Interface, from 4 bits to

32 bits. Each channel pair can also be configured independently to act as a single

channel (mono as opposed to stereo operation).

• All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and

word select/frame trigger (WS), and data line (SDA).

• Data for all I²S traffic within one Flexcomm Interface uses the Flexcomm Interface

FIFO. The FIFO depth is 8 entries.

• Left justified and right justified data modes.

• DMA support using FIFO level triggering.

• TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is

supported. Each channel pair can act as any data slot. Multiple channel pairs can

participate as different slots on one TDM data line.

• The bit clock and WS can be selectively inverted.

• Sampling frequencies supported depends on the specific device configuration and

applications constraints (for example, system clock frequency and PLL availability.)

but generally supports standard audio data rates.

Remark: The Flexcomm Interface function clock frequency should not be above 48 MHz.

7.17 Digital peripheral

7.17.1 LCD controller

The LCD controller provides all of the necessary control signals to interface directly to

various color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be operated. The display resolution is selectable and can be up to 1024  768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of

the displayed data) while still supporting many colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other system functions. A built-in FIFO acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time required to operate the display.

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7.17.1.1 Features

• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.

• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

• Supports single and dual-panel color STN displays.

• Supports Thin Film Transistor (TFT) color displays.

• Programmable display resolution including, but not limited to: 320  200, 320  240,

640  200, 640  240, 640  480, 800  600, and 1024  768.

• Hardware cursor support for single-panel displays.

• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

• 16 bpp true-color non-palettized for color STN and TFT.

• 24 bpp true-color non-palettized for color TFT.

• Programmable timing for different display panels.

• 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.

• Frame, line, and pixel clock signals.

• AC bias signal for STN, data enable signal for TFT panels.

• Supports little and big-endian, and Windows CE data formats.

• LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

7.17.2 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:

7.17.2.1 Features

• Secure Digital memory (SD version 1.1).

• Secure Digital I/O (SDIO version 2.0).

• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1).

• MultiMedia Cards (MMC version 4.1).

• Supports up to a maximum of 50 MHz of interface frequency.

7.17.3 External memory controller

The LPC54018JxM/LPC54S018JxM EMC is an ARM PrimeCell MultiPort Memory

Controller peripheral offering support for asynchronous static memory devices such as

RAM, ROM, and flash. In addition, it can be used as an interface with off-chip

memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus

Architecture (AMBA) compliant peripheral.

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7.17.3.1 Features

• Read and write buffers to reduce latency and to improve performance.

• Low transaction latency.

• Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode.

• 8/16 data and 16/20/26 address lines wide static memory support.

• Static memory features include:

– Asynchronous page mode read.

– Programmable Wait States.

– Bus turnaround delay.

– Output enable and write enable delays.

– Extended wait.

• Dynamic memory interface support including single data rate SDRAM.

• 16 bit and 32 bit wide chip select SDRAM memory support.

• EMC bus width (bit) on TFBGA180 package supports up to 8/16 data line wide static

memory.

• Four chip selects for synchronous memory and four chip selects for static memory

devices.

• Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to

SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB

parts, with 4, 8, 16, or 32 data bits per device.

• Separate reset domains allow the for auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

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7.17.4 DMA controller

The DMA controller allows peripheral-to memory, memory-to-peripheral, and

memory-to-memory transactions. Each DMA stream provides unidirectional DMA

transfers for a single source and destination.

7.17.4.1 Features

• One channel per on-chip peripheral direction: typically one for input and one for output

for most peripherals.

• DMA operations can optionally be triggered by on- or off-chip events.

• Priority is user selectable for each channel.

• Continuous priority arbitration.

• Address cache.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.

7.18 Counter/timers

7.18.1 General-purpose 32-bit timers/external event counter

The LPC54018JxM/LPC54S018JxM includes five general-purpose 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture inputs to trap the timer value when

an input signal transitions, optionally generating an interrupt.

7.18.1.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Up to four 32-bit captures can take a snapshot of the timer value when an input signal

transitions. A capture event may also optionally generate an interrupt. The number of

capture inputs for each timer that are actually available on device pins may vary by

device.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

– Shadow registers are added for glitch-free PWM output.

• For each timer, up to four external outputs corresponding to match registers with the

following capabilities (the number of match outputs for each timer that are actually

available on device pins may vary by device):

– Set LOW on match.

– Set HIGH on match.

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– Toggle on match.

– Do nothing on match.

• Up to two match registers can be used to generate timed DMA requests.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Up to four match registers can be configured for PWM operation, allowing up to three

single edged controlled PWM outputs. (The number of match outputs for each timer

that are actually available on device pins may vary by device.)

7.18.2 SCTimer/PWM

The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input

capture operations. The inputs and outputs of the SCTimer/PWM are shared with the

capture and match inputs/outputs of the 32-bit general-purpose counter/timers.

The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In

the two-counter case, in addition to the counter value the following operational elements

are independent for each half:

• State variable.

• Limit, halt, stop, and start conditions.

• Values of Match/Capture registers, plus reload or capture control values.

In the two-counter case, the following operational elements are global to the

SCTimer/PWM, but the last three can use match conditions from either counter:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

7.18.2.1 Features

• Two 16-bit counters or one 32-bit counter.

• Counter(s) clocked by bus clock or selected input.

• Up counter(s) or up-down counter(s).

• State variable allows sequencing across multiple counter cycles.

• Event combines input or output condition and/or counter match in a specified state.

• Events control outputs, interrupts, and the SCTimer/PWM states.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected event(s) can limit, halt, start, or stop a counter.

• Supports:

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– 8 inputs

– 10 outputs

– 16 match/capture registers

– 16 events

– 16 states

• PWM capabilities including dead time and emergency abort functions

7.18.3 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.18.3.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2²⁴ 4) in

multiples of T_cy(WDCLK) 4.

• The Watchdog Clock (WDCLK) uses the WDOSC as the clock source.

7.18.4 Real Time Clock (RTC) timer

The RTC timer is a 32-bit timer which counts down from a preset value to zero. At zero,

the preset value is reloaded and the counter continues. The RTC timer uses the 32.768

kHz clock input to create a 1 Hz or 1 kHz clock.

7.18.5 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

7.18.5.1 Features

• 24-bit interrupt timer.

• Four channels independently counting down from individually set values.

• Repeat and one-shot interrupt modes.

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7.18.6 Repetitive Interrupt Timer (RIT)

The repetitive interrupt timer provides a free-running 48-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.18.6.1 Features

• 48-bit counter running from the main clock. Counter can be free-running or can be

reset when an RIT interrupt is generated.

• 48-bit compare value.

• 48-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

• Can be used for ETM debug time stamping.

7.19 12-bit Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12-bit and fast conversion rates of up to 5 Msamples/s.

Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible

trigger sources are the SCTimer/PWM, external pins, and the ARM TXEV interrupt.

The ADC supports a variable clocking scheme with clocking synchronous to the system

clock or independent, asynchronous clocking for high-speed conversions

The ADC includes a hardware threshold compare function with zero-crossing detection.

The threshold crossing interrupt is connected internally to the SCTimer/PWM inputs for

tight timing control between the ADC and the SCTimer/PWM.

7.19.1 Features

• 12-bit successive approximation analog to digital converter.

• Input multiplexing among up to 12 pins.

• Two configurable conversion sequences with independent triggers.

• Optional automatic high/low threshold comparison and “zero crossing” detection.

• Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage

level).

• 12-bit conversion rate of 5.0 Msamples/s. Options for reduced resolution at higher

conversion rates.

• Burst conversion mode for single or multiple inputs.

• Synchronous or asynchronous operation. Asynchronous operation maximizes

flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger

latency and can eliminate uncertainty and jitter in response to a trigger.

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7.20 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings

supports several CRC standards commonly used. To save system power and bus

bandwidth, the CRC engine supports DMA transfers.

7.20.1 Features

• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

– CRC-CCITT: x¹⁶+ x¹²+ x⁵+ 1

– CRC-16: x¹⁶+ x¹⁵+ x²+ 1

– CRC-32: x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵+ x⁴+ x²+ x + 1

• Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

• Programmable seed number setting.

• Supports CPU PIO or DMA back-to-back transfer.

• Accept any size of data width per write: 8, 16 or 32-bit.

– 8-bit write: 1-cycle operation.

– 16-bit write: 2-cycle operation (8-bit x 2-cycle).

– 32-bit write: 4-cycle operation (8-bit x 4-cycle).

7.21 Temperature sensor

The temperature sensor transducer uses an intrinsic pn-junction diode reference and

outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage

varies inversely with device temperature with an absolute accuracy of better than ±5 C

over the full temperature range (40 C to +105 C). The temperature sensor is only

approximately linear with a slight curvature. The output voltage is measured over different

ranges of temperatures and fit with linear-least-square lines.

After power-up, the temperature sensor output must be allowed to settle to its stable value

before it can be used as an accurate ADC input.

7.22 Security features

The LPC54018JxM/LPC54S018JxM consists of an AES engine (LPC54S018Jx only), a

SHA engine, a random number generator, and a key storage block that supports keys

stored in OTP or keys from an SRAM based PUF (LPC54S018Jx only). Additionally, for

each device there is a 128-bit unique device serial number for identification.

7.22.1 SHA-1 and SHA-2

All LPC54018JxM/LPC54S018JxM devices provide on-chip hash support to perform

SHA-1 and SHA-2 with 256-bit digest (SHA-256). Hashing is a way to reduce arbitrarily

large messages or code images to a relatively small fixed size “unique” number called a

digest. The SHA-1 Hash produces a 160 bit digest (5 words), and the SHA-256 hash

produces a 256 bit digest (8 words).

7.22.1.1 Features

• Performs SHA-1 and SHA-2(256) based hashing.

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• Used with HMAC to support a challenge/response or to validate a message.

7.22.2 AES encryption/decryption

The LPC54S018Jx devices provide an on-chip hardware AES encryption and decryption

engine to protect the image content and to accelerate processing for data encryption or

decryption, data integrity, and proof of origin. Data can be encrypted or decrypted by the

AES engine using the scrambled key from the OTP or a software supplied key.

7.22.2.1 Features

• Encryption and Decryption of data.

• Secure storage of AES key that cannot be read.

• AES engine peak performance of 0.5 bytes/clock cycle.

• GF128 Hash Engine.

• AES engine supports 128, 192 or 256-bit key in:

– Electronic Codebook (ECB) mode.

– Cipher Block Chaining (CBC) mode.

– Cipher Feedback (CFB) mode.

– Output Feedback (OFB) mode.

– Counter (CTR) mode.

– Galois/Counter Mode (GCM).

• The AES engine is compliant with the FIPS (Federal Information Processing

Standard) Publication 197, Advanced Encryption Standard (AES).

• Data is processed in little endian mode. This means that the first byte read from

memory is integrated into the AES codeword as least significant byte. The 16th byte

read from memory is the most significant byte of the first AES codeword.

• DMA transfers supported through the DMA controller.

7.22.3 PUF

The PUF controller on the LPC54S018Jx provides a secure key storage without injecting

or provisioning device unique PUF root key.The PUF block can generate, store, and

reconstruct key sizes from 64 to 4096 bits.

7.22.3.1 PUF keys

The PUF controller provides secure key storage without storing the key. This is done by

using the digital fingerprint of a device derived from SRAM. Instead of storing the key, a

Key Code is generated, which in combination with the digital fingerprint is used to

reconstruct keys that are routed to the AES engine or for use by software. The PUF

controller provides generation and secure storage for keys.

7.22.3.2 PUF controller features

The PUF controller has the following features:

• Key strength of 256 bits.

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– The PUF constructs 256-bit strength device unique PUF root key using the digital

fingerprint of a device derived from SRAM and error correction data called

Activation Code (AC). The Activation Code is generated during enrollment

process. The Activation Code should be stored on external non-volatile memory

device in the system.

• Generation, storage, and reconstruction of keys.

• Key sizes from 64 to 4096 bits.

– PUF controller allows storage of keys, generated externally or on chip, of sizes 64

to 4096 bits.

– PUF Controller combines keys with digital fingerprint of device to generate key

codes. These key codes should be provided to the controller to reconstruct original

key. They can be stored on external non-volatile memory device in the system.

• Key output via dedicated hardware interface or through register interface.

– PUF controller allows to assign a 4-bit index value for each key while generating

key codes. Keys that are assigned index value zero are output through HW bus,

accessible to AES engine only. Keys with non-zero index are available through

APB register interface.

• 32-bit APB interface.

7.23 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and

trace functions are supported. The ARM Cortex-M4 is configured to support up to eight

breakpoints and four watch points.

The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,

execute the boot code, restart from address 0x0000 0000, and break at the user entry

point.

The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the

SWD functions by default.

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8. Limiting values

Table 10. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

Parameter

Conditions

Min

Max

Unit

[2]

V_DD

supply voltage (core and on pin VDD

external rail)

-0.5

+4.6

V

V_DDA

V_BAT

V_ref

V_I

analog supply voltage

battery supply voltage

reference voltage

input voltage

on pin VDDA

-0.5

+4.6

+5.0

V

on pin VBAT

on pin VREFP

-

[6][7]

[5]

only valid when the V_DD> 1.8 V;

5 V tolerant I/O pins

on I2C open-drain pins

-0.5

+5.0

V

USB_DM,

USB_DP pins

[8][9]

V_IA

analog input voltage

on digital pins configured for an

analog function

-0.5

VDD

V

[3]

I_DD

supply current

per supply pin,

-

300

100

mA

2.7 V  V_DD< 3.6 V

per ground pin,

I_SS

ground current

2.7 V  V_DD< 3.6 V

(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 C

I_latch

I/O latch-up current

[10]

T_stg

storage temperature

-65

-

+150

C

T_j(max)

maximum junction

temperature

[11]

[13]

[4]

P_tot(pack)

Based on package heat transfer,

not device power consumption

-

0.95

1.2

W

V

total power dissipation (per package)

Based on package heat transfer,

not device power consumption

V_ESD

electrostatic discharge

voltage

Human Body Model; all pins

2000

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 19.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 19) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[5] V_DDpresent or not present. Compliant with the I²C-bus standard. 5.5 V can be applied to this pin when V_DDis powered down.

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[6] Applies to all 5 V tolerant I/O pins except true open-drain pins.

[7] Including the voltage on outputs in 3-state mode.

[8] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 10⁶s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

[11] JEDEC (4.5 in  4 in); still air.

[12] Single layer (4.5 in  3 in); still air.

[13] 8-layer (4.5 in  3 in); still air.

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9. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T _j= T_amb+ P_D R_{th j – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 11. Thermal resistance

Symbol Parameter

TFBGA180 Package

Conditions

Max/Min

Unit

R_th(j-a)

thermal resistance from

junction to ambient

JEDEC (4.5 in  4 in); still air

8-layer (4.5 in  3 in); still air

41 15 % C/W

33 15 % C/W

14 15 % C/W

R_th(j-c)

thermal resistance from

junction to case

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10. Static characteristics

10.1 General operating conditions

Table 12. General operating conditions

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min Typ^[1]Max Unit

f_clk

CPU clock frequency

-

180

MHz

For USB high-speed device and host

operations

60

CPU clock frequency

For USB full-speed device and host

operations

12

-

180

MHz

V_DD

supply voltage (core and

external rail)

2.7

3.0

2.7

1.71

2.7

-

3.6

V_DDA

V

[2]

For OTP programming only

For USB Full-Speed operation only

For USB High-Speed operation only

V_DDA

V_BAT

V_refp

analog supply voltage

battery supply voltage

ADC positive reference

voltage

V_DDA2 V

V_DDA< 2 V

V_DDA

3.0

-

V_DDA

3.6

V

USB1_AVDD3V3,

USB1 analog supply

3.3

USB1_AVDDTX3V3

RTC oscillator pins

V_i(rtcx)

32.768 kHz oscillator input on pin RTCXIN

voltage

-0.5

-

+3.6

V

V_o(rtcx)

32.768 kHz oscillator

output voltage

on pin RTCXOUT

V_i(xtal)

crystal input voltage

crystal output voltage

on pin XTALIN

0.5

-

1.95

V

V_o(xtal)

on pin XTALOUT

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] Attempting to program below 2.7 V will result in unpredictable results and the part might enter an unrecoverable state.

10.2 CoreMark data

Table 13. CoreMark score

T_amb= 25C, V_DD= 3.3V

Parameter

ARM Cortex-M4 in active mode

CoreMark score CoreMark code executed from SRAMX;

Conditions

Typ

Unit

[1][3][4][5]

[2][3][4][5]

CCLK = 12 MHz

CCLK = 96 MHz

CCLK = 180 MHz

3.38

(Iterations/s) / MHz

[1] Clock source FRO. PLL disabled.

[2] Clock source 12 MHz FRO. PLL enabled.

[3] Characterized through bench measurements using typical samples.

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[4] Compiler settings: IAR C/C++ Compiler for Arm ver 8.22.2, optimization level 3, optimized for time on.

[5] SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered.

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Conditions: V_DD= 3.3 V; T_amb= 25 °C; active mode; all peripherals disabled; BOD disabled;

Measured with IAR ver 8.22.2. Optimization level 3, optimized for time ON.

12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.

36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,

and 180 MHz: FRO enabled; PLL enabled.

CoreMark score from SRAMX: SRAM0 is powered.

Fig 8. Typical CoreMark score ((iterations/s)/MHz) vs. Frequency (MHz) from SRAMX

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10.3 Power consumption

Power measurements in Active, sleep, and deep-sleep modes were performed under the

following conditions:

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

• Configure GPIO pins as outputs using the GPIO DIR register.

• Write 1 to the GPIO CLR register to drive the outputs LOW.

• All peripherals disabled.

Table 14. Static characteristics: Power consumption in active and sleep mode

T_amb= 40 C to +105 C, unless otherwise specified.2.7 V  V_DD 3.6 V.

Symbol

Active mode

I_DD

Parameter

Conditions

Min

Typ^[1]

Max

Unit

supply current

CoreMark code executed from

SRAMX:

[2][3][4]

[3][4][5]

CCLK = 12 MHz

CCLK = 96 MHz

CCLK = 180 MHz

-

3.0

-

mA

16.0

35.0

Sleep mode

[2][3][4]

[3][4][5]

I_DD

supply current

CCLK = 12 MHz

CCLK = 96 MHz

CCLK = 180 MHz

-

1.7

4.1

8.3

-

mA

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.

[2] Clock source FRO. PLL disabled.

[3] Characterized through bench measurements using typical samples.

[4] Compiler settings: Keil uVision v.5.23, optimization level 0, optimized for time off.

[5] Clock source FRO. PLL enabled.

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DDDꢀꢁꢂꢃꢄꢂꢅ

ꢂꢄꢉ

ꢋ$ꢍ0+]ꢌ

ꢁꢆꢉ

ꢁꢄꢉ

ꢀꢆꢉ

ꢀꢄꢉ

ꢆꢉ

0ꢄꢊ65$0ꢊꢋꢋ)52ꢎꢊꢊ33////ꢌꢌ

0ꢄꢊ65$0ꢊꢋꢋ)52ꢌ

ꢀꢁ

ꢄꢉ

ꢇꢈ

ꢆꢇ

ꢀꢁꢄ

ꢀꢃꢁ

ꢀꢈꢉ

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Conditions: V_DD= 3.3 V; T_amb= 25 °C; active mode; all peripherals disabled; BOD disabled;

Measured with Keil uVision v.5.23. Optimization level 0, optimized for time off.

12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.

36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,

and 180 MHz: FRO enabled; PLL enabled.

CoreMark A/MHz from SRAMX: SRAM0 is powered.

Fig 9. CoreMark power consumption: typical A/MHz vs. frequency (MHz) SRAMX

Table 15. Static characteristics: Power consumption in deep-sleep and deep power-down modes

T_amb= 40 C to +105 C, unless otherwise specified, 2.7 V  V_DD 3.6 V.

Symbol Parameter

I_DDsupply current Deep-sleep mode:

SRAMX (64 KB) powered

Conditions

Min Typ^[1][2]Max^[3]Unit

-

55

-

175

A

T_amb= 25 C

SRAMX (64 KB) powered

2020

T

_amb= 105 C

Deep power-down mode

RTC oscillator input grounded (RTC oscillator

disabled)

-

891

-

1.6

42

-

A

nA

T_amb= 25 C

RTC oscillator input grounded (RTC oscillator

disabled)

T

_amb= 105 C

RTC oscillator running with external crystal

VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V

660

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 3.3 V.

[2] Characterized through bench measurements using typical samples.

[3] Tested in production, VDD = 3.6 V.

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Table 16. Static characteristics: Power consumption in deep power-down mode

T_amb= 40 C to +105 C, unless otherwise specified, 2.7 V  V_DD 3.6 V.

Symbol Parameter

Conditions

Min Typ^[1][2]Max

Unit

I_BAT

battery supply deep power-down mode;

current

RTC oscillator running with external crystal

VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V

-

0

-

nA

VDD = VDDA= VREFP = 0 V or tied to ground, VBAT =

3.0 V

380^[3]

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).

[2] Characterized through bench measurements using typical samples.

[3] If VBAT> VDD, the external reset pin must be floating to prevent high VBAT leakage.

DDDꢀꢁꢂꢃꢄꢂꢆ

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,

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ꢋ$ꢌ

ꢀꢉꢉꢉ

ꢈꢉꢉ

ꢇꢉꢉ

ꢄꢉꢉ

ꢁꢉꢉ

ꢉ

ꢂꢐꢇꢊ99

ꢂꢐꢂꢊ99

ꢀꢐꢈꢊ99

ꢀꢐꢅꢀꢊ99

ꢏꢄꢉ

ꢏꢀꢉ

ꢁꢉ

ꢃꢉ

ꢈꢉ

7HPSHUDWXUHꢊꢋ&ꢌ

ꢀꢀꢉ

Conditions: BOD disabled; all oscillators and analog blocks disabled; all SRAM disabled except

64 KB SRAMX.

Remark: At hot temperature and below 2.0 V, the supply current increases slightly because of

reduction of available RBB (reverse body bias) voltage.

Fig 10. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

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DDDꢀꢁꢂꢃꢄꢂꢇ

ꢁꢃ

ꢁꢉ

ꢀꢃ

ꢀꢉ

ꢃ

,

''

ꢋ$ꢌ

ꢂꢐꢇꢊ99

ꢂꢐꢂꢊ99

ꢀꢐꢈꢊ99

ꢀꢐꢅꢀꢊ99

ꢉ

ꢏꢄꢉ

ꢏꢀꢉ

ꢁꢉ

ꢃꢉ

ꢈꢉ

ꢀꢀꢉ

7HPSHUDWXUHꢊꢋ&ꢌ

RTC disabled (RTC oscillator input grounded).

Fig 11. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD

Table 17 shows the typical peripheral power consumption measured on a typical sample

at Tamb = 25 °C and VDD = 3.3 V. The supply current per peripheral is measured as the

difference in supply current between the peripheral block enabled and the peripheral block

disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1/2, and PDRUNCFG0/1

registers. All other blocks are disabled and no code accessing the peripheral is executed.

The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, 96 MHz

and 180MHz.

Table 17. Typical peripheral power consumption^[1][2]

V_DD= 3.3 V; T_amb= 25 °C

Peripheral

FRO

I_DDin uA

100

WDT OSC

BOD

2.0

[1] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using PDRUNCFG0/1 registers. All other blocks are

disabled and no code accessing the peripheral is executed.

[2] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

Table 18. Typical AHB/APB peripheral power consumption ^[3][4][5]

T_amb= 25 °C, V_DD= 3.3 V;

Peripheral

I_DDin uA/MHz

AHB peripheral

CPU: 12 MHz, sync CPU: 48 MHz, sync CPU: 96 MHz, sync CPU: 180 MHz, sync

APB bus: 12 MHz

APB bus: 48 MHz

APB bus: 96 MHz

APB bus: 180 MHz

USB0 device

USB1 device

DMIC

0.3

4.4

0.2

0.9

0.3

4.4

0.2

0.9

0.3

4.4

0.2

0.9

0.4

5.0

0.2

1.0

[1]

GPIO0

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Table 18. Typical AHB/APB peripheral power consumption ^[3][4][5]

T_amb= 25 °C, V_DD= 3.3 V;

Peripheral

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

DMA

I_DDin uA/MHz

0.8

I_DDin uA/MHz

0.8

I_DDin uA/MHz

0.8

I_DDin uA/MHz

1.0

[1]

1.0

1.1

1.3

1.0

1.2

0.7

0.8

0.7

0.8

CRC

1.0

ADC0

1.6

1.9

SCTimer/PWM

Ethernet AVB

LCD

4.5

5.3

24.0

13.0

39.0

10.8

10.7

7.9

24.0

13.0

39.0

10.8

10.7

7.9

24.0

13.0

39.0

10.8

10.7

7.9

28.0

15.0

45.4

12.6

12.4

9.3

EMC

CAN0

CAN1

SD/MMC

Flexcomm Interface 0

(USART, SPI, I²C)

1.6

1.9

Flexcomm Interface1

(USART, SPI, I²C)

1.6

1.7

1.4

1.7

2.0

1.6

1.5

1.6

1.7

1.4

1.5

1.7

2.0

1.6

1.5

1.6

1.7

1.4

1.5

1.7

2.0

1.6

1.5

1.8

1.9

1.6

1.7

1.9

2.3

1.9

1.8

Flexcomm Interface 2

(USART, SPI, I²C)

Flexcomm Interface 3

(USART, SPI, I²C)

Flexcomm Interface 4

(USART, SPI, I²C)

Flexcomm Interface 5

(USART, SPI, I²C)

Flexcomm Interface 6

(USART, SPI, I²C, I²S)

Flexcomm Interface 7

(USART, SPI, I²C, I²S)

Flexcomm Interface 8

(USART, SPI, I²C)

Flexcomm Interface 9

(USART, SPI, I²C)

Flexcomm Interface 10

(SPI)

Sync APB peripheral

CPU: 12 MHz, sync CPU: 48 MHz, sync CPU: 96 MHz, sync CPU: 180 MHz, sync

APB bus: 12 MHz

APB bus: 48 MHz

APB bus: 96 MHz

APB bus: 180 MHz

[1]

INPUTMUX

IOCON

0.83

2.67

1.1

0.85

2.65

1.1

0.86

2.65

1.1

1.0

3.13

1.3

PINT

GINT0 and GINT1

1.33

1.35

1.34

1.52

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Table 18. Typical AHB/APB peripheral power consumption ^[3][4][5]

T_amb= 25 °C, V_DD= 3.3 V;

Peripheral

WWDT

RTC

I_DDin uA/MHz

0.42

0.3

I_DDin uA/MHz

0.42

0.3

I_DDin uA/MHz

0.42

0.3

I_DDin uA/MHz

0.46

0.3

MRT

0.3

RIT

0.1

UTICK

0.2

CTimer0

CTimer1

CTimer2

Smart card0

Smart card1

RNG

0.8

0.9

0.8

0.9

1.0

0.83

2.5

0.85

2.5

0.88

2.5

0.99

2.8

2.5

2.8

1.4

1.5

OTP controller

SHA

4.0

4.5

1.2

1.3

AES

<tbd>

PUF

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Table 18. Typical AHB/APB peripheral power consumption ^[3][4][5]

T_amb= 25 °C, V_DD= 3.3 V;

Peripheral

I_DDin uA/MHz

CPU: 12 MHz,

I_DDin uA/MHz

CPU: 180 MHz,

Async APB peripheral

CPU: 48 MHz, sync CPU: 96 MHz,

Async APB bus: 12 APB bus: 12 MHz^[2]Async APB bus: 12 Async APB bus:

MHz

MHz^[2]

12 MHz^[2]

Timer3

Timer4

0.9

[1] Turn off the peripheral when the configuration is done.

[2] For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a

higher frequency.

[3] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1, and

PDRUNCFG0/1 registers. All other blocks are disabled and no code accessing the peripheral is executed.

[4] The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, 96 MHz and 180 MHz.

[5] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

10.4 Pin characteristics

Table 19. Static characteristics: pin characteristics

T_amb= 40 C to +105 C, unless otherwise specified. 2.7 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

RESET pin

Conditions

Min

Typ^[1]Max

Unit

V_IH

V_IL

HIGH-level input voltage

0.8  V_DD

0.5

-

5.0

V

LOW-level input voltage

hysteresis voltage

0.3  V_DD

[14]

V_hys

0.05  V_DD

-

Standard I/O pins

Input characteristics

I_IL

I_IH

V_I

LOW-level input current

V_I= 0 V; on-chip pull-up resistor

disabled.

-

3.0

180

nA

HIGH-level input current V_I= V_DD; V_DD= 3.6 V; for RESETN

pin.

HIGH-level input current V_I= V_DD; on-chip pull-down resistor

disabled

[3]

input voltage

pin configured to provide a digital

function;

V_DD 1.8 V

0

-

5.0

3.6

5.0

+0.8

-

V

V_DD= 0 V

0

V_IH

V_IL

HIGH-level input voltage 2.7 V  V_DD 3.6 V

LOW-level input voltage 2.7 V  V_DD 3.6 V

hysteresis voltage

2.0

0.5

[14]

V_hys

0.1  V_DD

Output characteristics

V_O

I_OZ

output voltage

output active

0

-

V_DD

180

V

OFF-state output current V_O= 0 V; V_O= V_DD; on-chip

pull-up/pull-down resistors disabled

3

nA

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Table 19. Static characteristics: pin characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified. 2.7 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

V

V_OH

V_OL

I_OH

HIGH-level output voltage I_OH= 6 mA; 2.7 V  V_DD 3.6 V

LOW-level output voltage I_OL= 6 mA; 2.7 V  V_DD3.6 V

V_DD 0.4

-

0.4

-

V

HIGH-level output current V_OH= V_DD 0.4 V;

2.7 V  V_DD 3.6 V

6.0

mA

I_OL

LOW-level output current V_OL= 0.4 V; 2.7 V  V_DD 3.6 V

6.0

-

mA

[2][4]

I_OHS

HIGH-level short-circuit

output current. Drive

HIGH; connected to

ground;

2.7 V  V_DD< 2.7 V

87

I_OLS

LOW-level short-circuit

output current. Drive

2.7 V  V_DD< 2.7 V

-

77

mA

LOW; connected to V_DD

Weak input pull-up/pull-down characteristics

I_pd

pull-down current

V_I= V_DD

25

80

25

6

80

A

[2]

V_I= 5 V

100

80

30

I_pu

pull-up current

V_I= 0 V

[2][7]

V_DD< V_I< 5 V

Open-drain I²C pins

V_IH

V_IL

V_hys

I_LI

HIGH-level input voltage

2.7 V  V_DD< 2.7 V

0.7  V_DD

-

V

LOW-level input voltage

hysteresis voltage

0

-

0.3  V_DD

V

0.1  V_DD

-

V

[5]

input leakage current

V_I= V_DD

V_I= 5 V

-

2.5

5.5

-

3.5

10

-

A

mA

-

I_OL

LOW-level output

current

V_OL= 0.4 V; pin configured for

standard mode or fast mode

4.0

V_OL= 0.4V; pin configured for

Fast-mode Plus

20

-

mA

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Table 19. Static characteristics: pin characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified. 2.7 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

USB0_DM and USB0_DP pins

V_I

input voltage

0

-

V_DD

-

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

-

V

0.8

-

V

V_hys

Z_out

V_OH

V_OL

I_OH

0.4

33.0

2.8

-

V

[11]

[12]

output impedance

44

-

Ω

HIGH-level output voltage

LOW-level output voltage

V

[13]

0.3

74

9.0

74

9.0

100

V

[9][10]

[10][11]

[9][10]

[10][11]

[10]

HIGH-level output current V_OH= V_DD 0.3 V

V_OH= V_DD 0.3 V

38

6.0

38

6.0

-

mA

I_OL

LOW-level output current V_OL= 0.3 V

V_OL= 0.3 V

-

I_OLS

I_OHS

LOW-level short-circuit

output current

drive LOW; pad connected to

ground

-

[10]

HIGH-level short-circuit

output current

drive HIGH; pad connected to

ground

-

100

mA

Pin capacitance

C_io

input/output capacitance I²C-bus pins

[8]

[6]

-

6.0

2.0

7.0

pF

pins with digital functions only

Pins with digital and analog

functions

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.

[2] Based on characterization. Not tested in production.

[3] With respect to ground.

[4] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[5] To V_SS

.

[6] The values specified are simulated and absolute values, including package/bondwire capacitance.

[7] The weak pull-up resistor is connected to the V_DDrail and pulls up the I/O pin to the V_DDlevel.

[8] The value specified is a simulated value, excluding package/bondwire capacitance.

[9] Without 33 Ω  2 % series external resistor.

[10] The parameter values specified are simulated and absolute values.

[11] With 33 Ω  2 % series external resistor.

[12] With 15 KΩ  5 % resistor to V_SS

.

[13] With 1.5 KΩ  5% resistor to 3.6 V external pull-up.

[14] Guaranteed by design, not tested in production.

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V

DD

I

OL

pd

+

-

pin PIO0_n

A

I

OH

Ipu

-

+

A

aaa-010819

Fig 12. Pin input/output current measurement

10.4.1 Electrical pin characteristics

DDDꢀꢁꢅꢈꢆꢁꢄ

DDDꢀꢁꢅꢈꢆꢅꢁ

ꢇꢉ

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ꢄꢉ

ꢂꢉ

ꢁꢉ

ꢀꢉ

ꢉ

ꢇꢉ

ꢏꢄꢉ&

,

2/

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2/

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ꢀꢉꢃ&

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ꢁꢃ&

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ꢂꢉ

ꢀꢃ

ꢉ

ꢆꢉ&

ꢀꢉꢃ&

ꢉ

ꢉꢐꢀ

ꢉꢐꢁ

ꢉꢐꢂ

ꢉꢐꢄ

ꢉꢐꢃ

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ꢉꢐꢇ

ꢉ

ꢉꢐꢀ

ꢉꢐꢁ

ꢉꢐꢂ

ꢉꢐꢄ

ꢉꢐꢃ

ꢉꢐꢇ

9

ꢊꢋ9ꢌ

9

ꢊꢋ9ꢌ

2/

Conditions: V_DD= 1.8 V; on pins PIO0_13 to PIO0_14.

Conditions: V_DD= 3.3 V; on pins PIO0_13 to PIO0_16.

Fig 13. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus LOW-level output voltage

V_OL

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

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Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 14. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

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Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 15. Typical HIGH-level output voltage V_OHversus HIGH-level output source current I_OH

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Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 16. Typical pull-up current I_PUversus input voltage V_I

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Conditions: V_DD= 1.8V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 17. Typical pull-down current I_PDversus input voltage V_I

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11. Dynamic characteristics

11.1 I/O pins

Table 20. Dynamic characteristic: I/O pins^[1]

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Standard I/O pins - normal drive strength

[2][3]

t_r

t_f

t_r

t_f

rise time

fall time

rise time

fall time

pin configured as output; SLEW = 1

(Fast-mode);

2.7 V  V_DD<= 3.6 V

1.0

0.9

1.9

-

2.5

4.3

ns

pin configured as output; SLEW = 1

(Fast-mode);

2.7 V  V_DD<= 3.6 V

pin configured as output; SLEW = 0 (standard

mode);

2.7 V  V_DD3.6 V

pin configured as output; SLEW = 0 (standard

mode);

2.7 V  V_DD 3.6 V

pin configured as input

1.9

0.3

0.2

-

4.0

1.3

1.2

ns

[4]

t_r

t_f

rise time

fall time

[1] Simulated data, not tested in production.

[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between

80 % and 20 % of the full output signal level.

[3] The slew rate is configured in the IOCON block the SLEW bit.

[4] C_L= 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.

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11.2 Wake-up process

Table 21. Dynamic characteristic: Typical wake-up times from low power modes

V_DD= 3.3 V;T_amb= 25 C; using FRO as the system clock.

Symbol Parameter Conditions

Min Typ^[1]

Max Unit

[2][3]

[2][5]

t_wake

wake-up

time

from sleep mode

-

2.0

-

s

from deep-sleep mode; SRAMx

powered.

150

SRAM0, SRAM1, SRAM2,

SRAM3, and USB SRAM powered

down.

[4][5]

from deep power-down mode;

RTC disabled; using RESET pin.

-

1.2

-

ms

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler.

[3] FRO enabled, all peripherals off. PLL disabled.

[4] RTC disabled. Wake up from deep power-down causes the part to go through entire reset

process. The wake-up time measured is the time between when the RESET pin is triggered to wake the

device up and when a GPIO output pin is set in the reset handler.

[5] FRO disabled.

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11.3 External memory interface

Table 22. Dynamic characteristics: Static external memory interface

C_L= 10 pF balanced loading on all pins, T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external device and PCB; Values based on simulation.

Symbol Parameter^[1]

Conditions^[1]

Min

Typ

Max

Unit

Read cycle parameters

t_CSLAV

CS LOW to address

valid time

RD₁

RD₂

1.2

-

1.6

ns

[2]

[2][6]

[2]

t_CSLOEL

CS LOW to OE LOW

time

0.4+ T_cy(clk)

WAITOEN



0.8+ T_cy(clk)

WAITOEN



t_CSLBLSLCS LOW to BLS LOW RD₃; PB = 1

time

1.6

0

t_OELOEHOE LOW to OE HIGH RD₄

time

(WAITRD 

WAITOEN + 1) 

T_cy(clk)

0.3

+ (WAITRD 

WAITOEN + 1) 

T_cy(clk)

[2][3]

t_am

memory access time

RD₅

6.7

-

ns

+ (WAITRD 

WAITOEN +1) 

T_cy(clk)

[2][4]

[6]

t_h(D)

data input hold time

RD₆

4.8

-

ns

t_CSHBLSHCS HIGH to BLS HIGH PB = 1

time

0.8

1.5

[2]

t_CSHOEHCS HIGH to OE HIGH

time

0.5

-

0.9

0

ns

t_OEHANVOE HIGH to address

invalid time

0.4

0.5

t_deact

Write cycle parameters

t_CSLAVCS LOW to address

valid time

deactivation time

RD₇

0.9

WR₁

0.1

-

0.5

2.2

0

ns

t_CSLDV

CS LOW to data valid WR₂

time

1.0

[2][6]

t_CSLWELCS LOW to WE LOW

time

WR₃; PB =1

0.6

1.2

t_CSLBLSLCS LOW to BLS LOW WR₄; PB = 1

time

0

t_WELWEHWE LOW to WE HIGH WR₅; PB =1

time

(WAITWR 

WAITWEN + 1) 

T_cy(clk)

0.1

+ (WAITWR 

WAITWEN + 1) 

T_cy(clk)

[2][6]

t_BLSLBLSHBLS LOW to BLS

HIGH time

PB = 1

2.5

1.6

0.6

-

5.5

2.9

0.9

ns

t_WEHDNVWE HIGH to data

invalid time

WR₆; PB =1

WR₇; PB = 1

[2][5][6]

t_WEHEOWWE HIGH to end of

write time

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Product data sheet

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Table 22. Dynamic characteristics: Static external memory interface …continued

C_L= 10 pF balanced loading on all pins, T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external device and PCB; Values based on simulation.

Symbol Parameter^[1]

Conditions^[1]

Min

Typ

Max

Unit

[6]

t_BLSHDNVBLS HIGH to data

invalid time

PB = 1

0.8

-

0

ns

t_WEHANVWE HIGH to address

invalid time

PB = 1

0.6

-

0.9

0

ns

[2][6]

t_deact

deactivation time

WR₈; PB = 0;

PB = 1

0.8

1.2

t_CSLBLSLCS LOW to BLS LOW WR₉; PB = 0

(WAITWEN + 1) ns

 T_cy(clk)

+ (WAITWEN + 1)

 T_cy(clk)

[2][6]

t_BLSLBLSHBLS LOW to BLS

HIGH time

WR₁₀; PB = 0

2.5

-

5.5

ns

+ (WAITWR 

WAITWEN + 1) 

T_cy(clk)

+ (WAITWR 

WAITWEN + 1) 

T_cy(clk)

[2][5][6]

[2][6]

t_BLSHEOWBLS HIGH to end of

write time

WR₁₁; PB = 0

0.8

-

T_cy(clk)

ns

+ T_cy(clk)

0.2 + T_cy(clk)

t_BLSHDNVBLS HIGH to data

invalid time

WR12;

PB = 0

0.5 + T_cy(clk)

[1] Parameters are shown as RD_nor WD_nin Figure 18 as indicated in the Conditions column.

[2] T_cy(clk)= 1/EMC_CLK (see UM11060 LPC54018JxM/LPC54S018JxM manual).

[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).

[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.

[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).

[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM11060

LPC54018JxM/LPC54S018JxM manual).

Table 23. Dynamic characteristics: Static external memory interface

C_L= 20 pF balanced loading on all pins, T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external device and PCB; Values based on simulation.

Symbol Parameter^[1]

Conditions^[1]

Min

Typ

Max

Unit

Read cycle parameters

t_CSLAV

CS LOW to address

valid time

RD₁

RD₂

1.2

-

1.6

ns

[2]

[2][6]

[2]

t_CSLOEL

CS LOW to OE LOW

time

0.5+ T_cy(clk)

WAITOEN



0.8+ T_cy(clk) WAITOEN ns

t_CSLBLSLCS LOW to BLS LOW RD₃; PB = 1

time

2.3

0

ns

t_OELOEHOE LOW to OE HIGH RD₄

time

(WAITRD 

WAITOEN + 1) 

T_cy(clk)

0.3

+ (WAITRD 

WAITOEN + 1)  T_cy(clk)

[2][3]

t_am

memory access time

RD₅

7.9

-

ns

+ (WAITRD 

WAITOEN +1) 

T_cy(clk)

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Table 23. Dynamic characteristics: Static external memory interface …continued

C_L= 20 pF balanced loading on all pins, T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external device and PCB; Values based on simulation.

Symbol Parameter^[1]

Conditions^[1]

Min

5.5

0.7

Typ

Max

-

Unit

ns

[2][4]

[6]

t_h(D)data input hold time

RD₆

-

t_CSHBLSHCS HIGH to BLS HIGH PB = 1

time

1.5

ns

[2]

t_CSHOEHCS HIGH to OE HIGH

time

0.5

-

0.9

0

ns

t_OEHANVOE HIGH to address

invalid time

RD₈

RD₇

0.4

0.5

t_deact

deactivation time

0.9

Write cycle parameters^[2]

t_CSLAV

t_CSLDV

CS LOW to address

valid time

WR₁

0.1

1

-

0.5

2.2

ns

CS LOW to data valid WR₂

time

[2][6]

t_CSLWELCS LOW to WE LOW

time

WR₃; PB =1

0.5 +

(WAITWEN + 1) 

T_cy(clk)

(WAITWEN + 1)  T_cy(clk)ns

[2][6]

t_CSLBLSLCS LOW to BLS LOW WR₄; PB = 1

time

1.9

-

0

ns

t_WELWEHWE LOW to WE HIGH WR₅; PB =1

time

0.1 +

(WAITWEN + 1) 

T_cy(clk)

(WAITWEN + 1)  T_cy(clk)ns

[2][6]

[2][5][6]

[6]

t_BLSLBLSHBLS LOW to BLS

HIGH time

PB = 1

3.1

-

6.7

ns

t_WEHDNVWE HIGH to data

invalid time

WR₆; PB =1

WR₇; PB = 1

PB = 1

1.6 + T_cy(clk)

0.5+T_cy(clk)

0.8

2.8 + T_cy(clk)

t_WEHEOWWE HIGH to end of

write time

0.8 + T_cy(clk)

t_BLSHDNVBLS HIGH to data

invalid time

0

[6]

t_WEHANVWE HIGH to address

invalid time

PB = 1

0.5

0.8

0

[2][6]

t_deact

deactivation time

WR₈; PB = 0;

PB = 1

0.8

t_CSLBLSLCS LOW to BLS LOW WR₉; PB = 0

1.9

(WAITWEN + 1)  T_cy(clk)ns

+ (WAITWEN + 1)

 T_cy(clk)

[2][6]

t_BLSLBLSHBLS LOW to BLS

HIGH time

WR₁₀; PB = 0

WR₁₁; PB = 0

3.1+ (WAITWR 

WAITWEN + 1) 

T_cy(clk)

-

6.7+ (WAITWR 

WAITWEN + 1)  T_cy(clk)

ns

[2][5][6]

[2][6]

t_BLSHEOWBLS HIGH to end of

write time

0.8

-

T_cy(clk)

ns

+ T_cy(clk)

0.2 + T_cy(clk)

t_BLSHDNVBLS HIGH to data

invalid time

WR12;

PB = 0

0.5 + T_cy(clk)

[1] Parameters are shown as RD_nor WD_nin Figure 18 as indicated in the Conditions column.

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[2] T_cy(clk)= 1/EMC_CLK (see UM11060 LPC54018JxM/LPC54S018JxM manual).

[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).

[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.

[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).

[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM11060

LPC54018JxM/LPC54S018JxM manual).

EMC_Ax

RD

WR

1

EMC_CSx

EMC_OE

WR

8

RD

8

RD

2

RD

4

RD

7

WR

11

9

10

EMC_BLSx

EMC_WE

RD

5a

RD

5b

WR

2

WR

12

RD

5

6

EMC_Dx

EOW

EOR

aaa-026103

Fig 18. External static memory read/write access (PB = 0)

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EMC_Ax

RD

WR

1

EMC_CSx

EMC_OE

RD

WR

8

2

8

RD

4

RD

WR

4

RD

3

7

EMC_BLSx

EMC_WE

WR

8

WR

7

3

5

RD

5a

RD

5b

RD

5c

WR

6

2

RD

6

RD

5

EMC_Dx

EOR

EOW

aaa026104

Fig 19. External static memory read/write access (PB =1)

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

RD

5

EMC_Dx

002aag216

Fig 20. External static memory burst read cycle

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Table 24. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 ^[2]

C_L= 10 pF balanced loading on all pins, T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external device and PCB. Values based on simulation. t_cmddlyis programmable delay value for EMC

command outputs in command delayed mode; t_fbdlyis programmable delay value for the feedback clock that controls input

data sampling.

Symbol

Parameter

Min

Typ

Max

Unit

For RD = 1

Common to read and write cycles

[1]

T_cy(clk)

t_d(SV)

clock cycle time

10

-

ns

chip select valid delay time

chip select hold time

-

t_cmddly+ 3.7

-

t_h(S)

t_cmddly+ 1.7

-

t_d(RASV)

row address strobe valid

delay time

t_cmddly+ 4.1

t_h(RAS)

t_d(CASV)

t_h(CAS)

row address strobe hold

time

t_cmddly+ 1.8

-

ns

column address strobe valid

delay time

t_cmddly+ 4.4

-

column address strobe hold

time

t_cmddly+ 1.9

t_d(WV)

t_h(W)

t_d(AV)

t_h(A)

write valid delay time

write hold time

-

t_cmddly+ 5.1

ns

t_cmddly+ 2.4

-

address valid delay time

address hold time

t_cmddly+ 4.8

-

t_cmddly+ 1.7

Read cycle parameters

t_su(D)data input set-up time

t_h(D)data input hold time

Write cycle parameters

t_d(QV)data output valid delay time

t_h(Q)data output hold time

0.5

2.1

-

ns

-

8.1

-

ns

1.7

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] See Table 26 for internal programmable delay.

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Table 25. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 ^[2]

C_L= 20 pF balanced loading on all pins, T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external device and PCB. Values based on simulation. t_cmddlyis programmable delay value for EMC

command outputs in command delayed mode; t_fbdlyis programmable delay value for the feedback clock that controls input

data sampling.

Symbol

Parameter

Min

Typ

Max

Unit

For RD = 1

Common to read and write cycles

[1]

T_cy(clk)

t_d(SV)

clock cycle time

10

-

ns

chip select valid delay time

chip select hold time

-

t_cmddly+ 4.9

-

t_h(S)

t_cmddly+ 2.4

-

t_d(RASV)

row address strobe valid

delay time

t_cmddly+ 5.4

t_h(RAS)

t_d(CASV)

t_h(CAS)

row address strobe hold

time

t_cmddly+ 2.5

-

ns

column address strobe valid

delay time

t_cmddly+ 5.6

-

column address strobe hold

time

t_cmddly+ 2.6

t_d(WV)

t_h(W)

t_d(AV)

t_h(A)

write valid delay time

write hold time

-

t_cmddly+ 6.3

ns

t_cmddly+ 3.1

-

address valid delay time

address hold time

t_cmddly+ 6.1

-

t_cmddly+ 2.4

Read cycle parameters

t_su(D)data input set-up time

t_h(D)data input hold time

Write cycle parameters

t_d(QV)data output valid delay time

t_h(Q)data output hold time

0.5

2.1

-

ns

-

9.3

-

ns

2.4

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] See Table 26 for internal programmable delay.

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T

cy(clk)

EMC_CLKOUT0

EMC_CLKOUT1

EMC_DYCSn,

EMC_RAS,

t

h(x)

d(xV)

EMC_CAS,

EMC_WE,

EMC_CKEOUTn,

EMC_A[22:0],

EMC_DQMOUTn

t

d(QV)

t

h(Q)

EMC_D[31:0]

write

t

su(D)

h(D)

EMC_D[31:0]

read

aaa-024988

Fig 21. Dynamic external memory interface signal timing

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Table 26. Dynamic characteristics: Dynamic external memory interface programmable clock delays (CMDDLY,

FBCLKDLY)

T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V.Values guaranteed by design. t_cmddlyis programmable delay value for EMC

command outputs in command delayed mode; t_fbdlyis programmable delay value for the feedback clock that controls input

data sampling.

Symbols

Parameter Five bit value for each delay in EMCDLYCTL^[1]Min

Typ

Max

Unit

ns

t_cmddly, t_fbdly

delay time

b00000

b00001

b00010

b00011

b00100

b00101

b00110

b00111

b01000

b01001

b01010

b01011

b01100

b01101

b01110

b01111

b10000

b10001

b10010

b10011

b10100

b10101

b10110

b10111

b11000

b11001

b11010

b11011

b11100

b11101

b11110

b11111

0.41

0.52

0.69

0.8

0.66 0.77

0.85 1.03

1.11 1.3

1.3

1.56

0.95

1.06

1.23

1.34

1.45

1.56

1.73

1.84

1.99

2.1

1.53 1.77

1.72 2.03

1.98 2.3

2.17 2.56

2.3

2.67

2.49 2.93

2.75 3.2

2.94 3.46

3.17 3.67

3.36 3.93

3.62 4.2

3.81 4.46

3.86 4.46

4.05 4.72

4.31 4.99

2.27

2.38

2.45

2.56

2.73

2.84

2.99

3.1

4.5

5.25

4.73 5.46

4.92 5.72

5.18 5.99

5.37 6.25

3.27

3.38

3.49

3.6

5.5

6.36

5.69 6.62

5.95 6.89

6.14 7.15

6.37 7.36

6.56 7.62

6.82 7.89

7.01 8.15

3.77

3.88

4.03

4.14

4.31

4.42

[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All

delay times are incremental delays for each element starting from delay block 0.

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11.4 System PLL (PLL0)

Table 27. PLL lock times and current

T_amb= 40 C to +105 C, unless otherwise specified. V_DD= 2.7 V to 3.6 V

Symbol

Parameter

Conditions

Min Typ Max

Unit

PLL0 configuration: input frequency 12 MHz; output frequency 100 MHz

[1]

t_lock(PLL0)

I_DD(PLL0)

PLL0 lock time

PLL0 current

96

s

[1][2]

when locked

-

2.0

mA

PLL0 configuration: input frequency 32 kHz; output frequency 100 MHz

[1]

t_lock(PLL0)

I_DD(PLL0)

PLL0 lock time

PLL0 current

-

108

1.6

s

[1][2]

when locked

mA

[1] Data based on characterization results, not tested in production.

[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

Table 28. Dynamic characteristics of the PLL0^[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Reference clock input

F_in

input frequency

32.768 kHz -

25 MHz

Clock output

[2]

[3]

f_o

output frequency

output duty cycle

CCO frequency

for PLL0 clkout output

4.3

46

-

550

54

MHz

%

d_o

f_CCO

275

550

MHz

Lock detector output

_lock(PFD)PFD lock criterion

1

2

4

ns

Dynamic parameters at f_out= f_CCO= 540 MHz; standard bandwidth settings

[4][5]

J_rms-interval

J_pp-period

RMS interval jitter

f_ref= 10 MHz

-

15

40

30

80

ps

[4][5]

peak-to-peak, period jitter

[1] Data based on characterization results, not tested in production.

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.

[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion

means lock output is HIGH.

[4] Actual jitter dependent on amplitude and spectrum of substrate noise.

[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

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11.5 USB PLL (PLL1)

Table 29. PLL1 lock times and current

T_amb= 40 C to +105 C, unless otherwise specified. V_DD= 2.7 V to 3.6 V

Symbol Parameter Conditions

PLL1 configuration: input frequency 12 MHz; output frequency 48 MHz

Min

Typ Max

Unit

[1]

t_lock(PLL1)

I_DD(PLL1)

PLL1 lock time

PLL1 current

-

7.4

-

s

[1][2]

When locked

260

A

[1] Data based on characterization results, not tested in production.

[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

Table 30. Dynamic characteristics of the PLL1^[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Reference clock input

F_in

input frequency

1

-

25

MHz

Clock output

[2]

f_o

output frequency

for PLL1 clkout

output

9.75

45

-

160

55

MHz

%

d_o

output duty cycle

CCO frequency

for PLL1 clkout

output

f_CCO

156

320

MHz

Dynamic parameters at f_out= f_CCO= 320 MHz; standard bandwidth settings

[3][4]

J_pp-period

peak-to-peak, period f_ref= 4 MHz

jitter

-

300

ps

[1] Data based on simulation, not tested in production.

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.

[3] Actual jitter dependent on amplitude and spectrum of substrate noise.

[4] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

11.6 Audio PLL (PLL2)

Table 31. PLL2 lock times and current

T_amb= 40 C to +105 C, unless otherwise specified. V_DD= 2.7 V to 3.6 V

Symbol

Parameter

Conditions

Min Typ Max

Unit

PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz

[1]

t_lock(PLL2)

I_DD(PLL2)

PLL2 lock time

PLL2 current

-

96

s

[1][2]

when locked

2.0

mA

PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz

[1]

t_lock(PLL2)

I_DD(PLL2)

PLL2 lock time

PLL2 current

-

108

1.6

s

[1][2]

when locked

mA

[1] Data based on characterization results, not tested in production.

[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

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Table 32. Dynamic characteristics of the PLL2^[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Reference clock input

F_in

input frequency

1

-

25

MHz

Clock output

[2]

f_o

output frequency

for PLL2 clkout

output

4.3

46

-

550

54

MHz

%

d_o

output duty cycle

CCO frequency

for PLL2 clkout

output

f_CCO

275

550

MHz

Lock detector output

_lock(PFD)PFD lock criterion

[3]

1

2

4

ns

Dynamic parameters at f_out= f_CCO= 540 MHz; standard bandwidth settings

[4][5]

J_rms-intervalRMS interval jitter

f_ref= 10 MHz

-

15 30

40 80

ps

[4][5]

J_pp-period

peak-to-peak, period f_ref= 10 MHz

jitter

[1] Data based on characterization results, not tested in production.

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.

[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion

means lock output is HIGH.

[4] Actual jitter dependent on amplitude and spectrum of substrate noise.

[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

11.7 FRO

The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.

Table 33. Dynamic characteristic: FRO

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V.

Symbol

f_osc(RC)

Parameter

Conditions Min

Typ^[1]

12

Max

Unit

MHz

FRO clock frequency

-

11.88

12.12

48.48

96.96

47.52

95.04

48

96

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

11.8 Crystal oscillator

Table 34. Dynamic characteristic: oscillator

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V.^[1]

Symbol

Low-frequency mode (1-20 MHz)^[4]

t_jit(per)period jitter time

Parameter

Conditions

Min

Typ^[2]

Max

Unit

[3]

5 MHz crystal

10 MHz crystal

15 MHz crystal

-

13.2

6.6

-

ps

4.8

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Table 34. Dynamic characteristic: oscillator …continued

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V.^[1]

Symbol Parameter Conditions

High-frequency mode (20 - 25 MHz)^[5]

Min

Typ^[2]

Max

Unit

[3]

t_jit(per)

period jitter time

20 MHz crystal

25 MHz crystal

-

4.3

3.7

-

ps

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] Indicates RMS period jitter.

[4] Select Low Frequency range = 0 in the SYSOSCCTRL register.

[5] Select High Frequency = 1 in the SYSOSCCTRL register.

11.9 RTC oscillator

See Section 13.5 for connecting the RTC oscillator to an external clock source.

Table 35. Dynamic characteristic: RTC oscillator

T_amb= 40 C to +105 C; 2.7  V_DD 3.6^[1]

Symbol Parameter

f_iinput frequency

Conditions

Min

Typ^[1]

Max

Unit

-

32.768

-

kHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

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11.10 Watchdog oscillator

Table 36. Dynamic characteristics: Watchdog oscillator

T_amb= 40 C to +105 C; 2.7  V_DD 3.6^[1]

Symbol

f_osc(int)

D_clkout

J_PP-CC

t_start

Parameter

Conditions

Min

200

48

-

Typ^[1]

Max

1500

52

Unit

kHz

%

[2]

internal watchdog oscillator frequency

clkout duty cycle

-

[3][4]

[4]

peak-peak period jitter

start-up time

1

4

20

ns

-

s

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +105 C) is 40 %.

[3] Actual jitter dependent on amplitude and spectrum of substrate noise.

[4] Guaranteed by design. Not tested in production samples.

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11.11 I²C-bus

Table 37. Dynamic characteristic: I²C-bus pins^[1]

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V.^[2]

Symbol Parameter

Conditions

Min

Max

100

400

1

Unit

kHz

MHz

ns

f_SCL

SCL clock frequency

fall time

Standard-mode

Fast-mode

0

-

Fast-mode Plus

Both SDA and SCL signals

Standard-mode

Fast-mode

[4][5][6][7]

t_f

300

20 + 0.1 

300

ns

C_b

Fast-mode Plus

Standard-mode

Fast-mode

-

120

ns

s

ns

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

data hold time

4.7

1.3

0.5

4.0

0.6

0.26

0

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

Fast-mode Plus

Standard-mode

Fast-mode

[3][4][8]

[9][10]

t_HD;DAT

0

Fast-mode Plus

Standard-mode

Fast-mode

0

t_SU;DAT

data set-up time

250

100

50

Fast-mode Plus

[1] Guaranteed by design. Not tested in production.

[2] Parameters are valid over operating temperature range unless otherwise specified. See the I²C-bus specification UM10204 for details.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[8] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t_VD;DATor

t_VD;ACKby a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement t_SU;DAT= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

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t

SU;DAT

f

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 22. I²C-bus pins clock timing

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11.12 I²S-bus interface

Table 38. Dynamic characteristics: I²S-bus interface pins ^[1][4]

T_amb= 40 C to 105 C; V_DD= 2.7 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ^[3]Max

Unit

Common to master and slave

t_WH

pulse width HIGH

on pins I2Sx_TX_SCK and I2Sx_RX_SCK^[5]

CCLK  100 MHz

(T_cyc/2)-1 -

(T_cyc/2) +1 ns

CCLK > 100 MHz

(T_cyc/2) +1 ns

t_WL

pulse width LOW

on pins I2Sx_TX_SCK and I2Sx_RX_SCK^[5]

CCLK  100 MHz

(T_cyc/2)-1 -

(T_cyc/2) +1 ns

CCLK > 100 MHz

Master; 2.7 V  VDD  3.6 V

[2]

t_v(Q)

data output valid time on pin I2Sx_TX_SDA

CCLK  100 MHz

21.4

20.6

-

30.4

28.7

ns

CCLK > 100 MHz

on pin I2Sx_WS

CCLK  100 MHz

21.1

20.3

-

29

ns

CCLK > 100 MHz

28.3

[2]

t_su(D)

data input set-up time on pin I2Sx_RX_SDA

CCLK  100 MHz

1.3

1.0

-

ns

CCLK > 100 MHz

t_h(D)

data input hold time

on pin I2Sx_RX_SDA

CCLK  100 MHz

CCLK > 100 MHz

2.9

3.3

-

ns

Slave; 2.7 V  VDD  3.6 V

[2]

t_v(Q)

data output valid time on pin I2Sx_TX_SDA

CCLK  100 MHz

13.8

13

-

23.6

21.9

ns

CCLK > 100 MHz

t_su(D)

data input set-up time on pin I2Sx_RX_SDA

CCLK  100 MHz

4.7

4.2

-

ns

CCLK > 100 MHz

on pin I2Sx_WS

CCLK  100 MHz

0.9

0.7

-

ns

CCLK > 100 MHz

[2]

t_h(D)

data input hold time

on pin I2Sx_RX_SDA

CCLK  100 MHz

CCLK > 100 MHz

on pin I2Sx_WS

0

-

ns

CCLK  100 MHz

CCLK > 100 MHz

1.5

1.3

-

ns

[1] Based on characterization; not tested in production.

[2] Clock Divider register (DIV) = 0x0.

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[3] Typical ratings are not guaranteed.

[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section

in the I²S chapter (UM11060) to calculate clock and sample rates.

[5] Based on simulation. Not tested in production.

T

t

f

t

r

cy(clk)

I2Sx_SCK

t

WL

WH

I2Sx_TX_SDA

t

v(Q)

I2Sx_RX_SDA

I2Sx_WS

t

h(D)

su(D)

t

aaa-026799

v(Q)

Fig 23. I²S-bus timing (master)

T

t

f

t

r

cy(clk)

I2Sx_SCK

t

WL

WH

I2Sx_TX_SDA

t

v(Q)

I2Sx_RX_SDA

I2Sx_WS

t

su(D)

t

h(D)

t

h(D)

su(D)

aaa-026800

Fig 24. I²S-bus timing (slave)

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11.13 SPI interfaces (Flexcomm Interface 0-9)

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 14 Mbit/s.

Table 39. SPI dynamic characteristics^[1]

T_amb= 40 C to 105 C; 2.7 V  V_DD 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

SPI master 2.7 V  V_DD 3.6 V

t_DS

data set-up time

CCLK  100 MHz

CCLK > 100 MHz

CCLK  100 MHz

CCLK > 100 MHz

2.4

2.2

4.2

4.5

1.8

1.7

-

ns

-

t_DH

data hold time

-

t_v(Q)

data output valid time CCLK  100 MHz

4.6

4.0

CCLK > 100 MHz

SPI slave 2.7 V  V_DD 3.6 V

t_DS

data set-up time

CCLK  100 MHz

CCLK > 100 MHz

CCLK  100 MHz

CCLK > 100 MHz

1.2

1.0

0

-

ns

-

t_DH

data hold time

-

0

-

t_v(Q)

data output valid time CCLK  100 MHz

14

13.3

23.9

22.2

CCLK > 100 MHz

[1] Based on characterization; not tested in production.

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

MISO (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MOSI (CPHA = 1)

MISO (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

IDLE

DATA VALID (LSB)

DATA VALID

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014969

Fig 25. SPI master timing

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

MOSI (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MISO (CPHA = 1)

MOSI (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

IDLE

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014970

Fig 26. SPI slave timing

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11.14 SPI interfaces (Flexcomm Interface 10)

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode is 50 Mbit/s, and the maximum supported bit rate for SPI slave mode is 50 Mbit/s.

Table 40. SPI dynamic characteristics^[1]

T_amb= 40 C to 105 C; 2.7 V  V_DD 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew =

1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising

or falling edge.

Symbol Parameter

SPI master

Conditions Min

Typ

Max

Unit

t_DS

data set-up time

0

-

ns

t_DH

data hold time

10.0

0.8

-

t_v(Q)

SPI slave

t_DS

data output valid time

10.0

data set-up time

data hold time

1.2

-

ns

t_DH

10.0

4.28

-

t_v(Q)

data output valid time

10.0

[1] Based on characterization; not tested in production.

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

MISO (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MOSI (CPHA = 1)

MISO (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

IDLE

DATA VALID (LSB)

DATA VALID

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014969

Fig 27. SPI master timing

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

MOSI (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MISO (CPHA = 1)

MOSI (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

IDLE

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014970

Fig 28. SPI slave timing

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11.15 DMIC subsystem

Table 41. Dynamic characteristics^[1]

T_amb= 40 C to 105 C; V_DD= 2.7 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to

standard mode for all pins; Bypass bit = 0; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

14.3

0

Typ

Max

Unit

ns

t_DS

data set-up time CCLK  100 MHz

-

CCLK > 100 MHz

ns

t_DH

data hold time

CCLK  100 MHz

ns

CCLK > 100 MHz

0

ns

[1] Based on simulated values.

CLOCK

t

DH

t

SU

DATA

aaa-017025

Fig 29. DMIC timing diagram

11.16 Smart card interface

Table 42. Dynamic characteristics^[1]

T_amb= 40 C to 105 C; V_DD= 2.7 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

2.7 V  VDD  3.6 V

t_DS

data set-up time

CCLK  100 MHz

CCLK > 100 MHz

CCLK  100 MHz

CCLK > 100 MHz

2.1

0

-

ns

-

t_DH

data hold time

-

0

-

t_v(Q)

data output valid time CCLK  100 MHz

11.0

22.5

CCLK > 100 MHz

[1] Based on simulated values. V_DD= 2.7 V - 3.6 V.

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11.17 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master synchronous mode is 24 Mbit/s, and the maximum supported bit rate for USART

slave synchronous mode is 12.5 Mbit/s.

Table 43. USART dynamic characteristics^[1]

T_amb= 40 C to 105 C; V_DD= 2.7 V to 3.6 V; C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

USART master (in synchronous mode) 2.7 V  VDD  3.6 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time

data input hold time

data output valid time

CCLK  100 MHz

CCLK > 100 MHz

CCLK  100 MHz

CCLK > 100 MHz

CCLK  100 MHz

CCLK > 100 MHz

20.5

18.9

0

-

ns

-

0

-

1.5

1.3

3.6

3.2

USART slave (in synchronous mode) 2.7 V  VDD  3.6 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time

data input hold time

data output valid time

CCLK  100 MHz

CCLK > 100 MHz

CCLK  100 MHz

CCLK > 100 MHz

CCLK  100 MHz

CCLK > 100 MHz

1.2

1

-

ns

-

0

-

0

-

15.2

14.3

26.1

24.2

[1] Based on characterization; not tested in production.

T

cy(clk)

Un_SCLK (CLKPOL = 0)

Un_SCLK (CLKPOL = 1)

TXD

t

vQ)

v(Q)

START

BIT0

BIT1

t

su(D) h(D)

BIT1

START

BIT0

RXD

aaa-015074

Fig 30. USART timing

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11.18 SCTimer/PWM output timing

Table 44. SCTimer/PWM output dynamic characteristics

T_amb= 40 C to 105 C; 2.7 V  V_DD 3.6 V C_L= 30 pF. Simulated skew (over process, voltage, and temperature) of any two

SCT fixed-pin output signals; sampled at the 90 % and 10 % level of the rising or falling edge; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_sk(o)

output skew time

-

3.4

-

4.5

ns

11.19 USB interface characteristics

Table 45. Dynamic characteristics: USB0 pins (full-speed)

C_L= 50 pF; R_pu= 1.5 k on D+ to V_DD, unless otherwise specified; 3.0 V  V_DD 3.6 V.

Symbol

t_r

Parameter

rise time

fall time

Conditions

10 % to 90 %

Min

4.0

90

Typ

Max

20

Unit

ns

%

t_f

20

t_FRFM

V_CRS

t_FEOPT

t_FDEOP

differential rise and fall time matching t_r/ t_f

output signal crossover voltage

111.11

2.0

1.3

160

2

V

source SE0 interval of EOP

see Figure 31

175

+5

ns

source jitter for differential transition see Figure 31

to SE0 transition

t_JR1

receiver jitter to next transition

18.5

9

+18.5

+9

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

-

[1]

t_EOPR1

must reject as

EOP; see

Figure 31

40

t_EOPR2

EOP width at receiver

must accept as

EOP; see

82

-

ns

Figure 31

[1] Characterized but not implemented as production test. Guaranteed by design.

11.20

T

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × T

+ t

PERIOD

FDEOP

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 31. Differential data-to-EOP transition skew and EOP width

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11.21 Ethernet AVB

Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply

with the IEEE standard 802.3.

Table 46. Dynamic characteristics: Ethernet

T_amb= 40 C to 105 C, V_DD= 2.7 V to 3.6 V. C_L= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.

Symbol

RMII mode

f_clk

Parameter

Conditions

Min

Typ

Max

Unit

[1]

clock frequency

clock duty cycle

for ENET_RX_CLK

-

50.0

55.0

MHz

%

[1]

_clk

45.0

[1][2]

t_su

data input set-up

time

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

CCLK  100 MHz

4.4

-

ns

CCLK > 100 MHz

[1][2]

t_h

data input hold time for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

CCLK  100 MHz

1.3

-

0

ns

CCLK > 100 MHz

t_v(Q)

data output valid

time

for ENET_TXDn, ENET_TX_EN

CCLK  100 MHz

9.9

-

17.3

ns

CCLK > 100 MHz

MII mode

[1]

f_clk

_clk

f_clk

_clk

t_su

clock frequency

clock duty cycle

clock frequency

clock duty cycle

for ENET_TX_CLK

for ENET_RX_CLK

-

25.0

55.0

25.0

55.0

MHz

%

[1]

45.0

-

[1]

MHz

%

[1]

45.0

[1][2]

data input set-up

time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

CCLK  100 MHz

4.7

-

ns

CCLK > 100 MHz

[1][2]

t_h

data input hold time for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

CCLK  100 MHz

1.2

-

0

ns

CCLK > 100 MHz

t_v(Q)

data output valid

time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

CCLK  100 MHz

10.0

-

18.2

ns

CCLK > 100 MHz

[1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input

capacitance of the receiving device.

[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or

output level.

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ENET_RX_CLK

t

v(Q)

ENET_TX_EN

ENET_TXDn

t

su

t

h

ENET_RXDn

ENET_RX_DV

aaa-025108

Fig 32. Ethernet RMII timing

ENET_RX_CLK

t

su

t

h

ENET_RXDn

ENET_RX_DV

ENET_RX_ER

ENET_TX_CLK

t

v(Q)

ENET_TX_EN

ENET_TXDn

aaa-025109

Fig 33. Ethernet MII timing

11.22 SD/MMC and SDIO

Table 47. Dynamic characteristics: SD/MMC and SDIO

T_amb= 40 C to +105 C, V_DD= 2.7 V to 3.6 V; C_L= 20 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY

register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns

for SD_DATn and SD_CMD pins. Simulated values in high-speed mode.

Symbol

f_clk

Parameter

Conditions

Min

Typ

Max

Unit

clock frequency

data input set-up time

on pin SD_CLK; data transfer mode

on pins SD_DATn as inputs

CCLK  100 MHz

-

50

MHz

t_su(D)

14.4

-

ns

CCLK > 100 MHz

on pins SD_CMD as inputs

CCLK  100 MHz

14.4

-

ns

CCLK > 100 MHz

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Table 47. Dynamic characteristics: SD/MMC and SDIO …continued

T_amb= 40 C to +105 C, V_DD= 2.7 V to 3.6 V; C_L= 20 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY

register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns

for SD_DATn and SD_CMD pins. Simulated values in high-speed mode.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_h(D)

data input hold time

on pins SD_DATn as inputs

CCLK  100 MHz

1.5

-

ns

CCLK > 100 MHz

on pins SD_CMD as inputs

CCLK  100 MHz

1.5

-

ns

CCLK > 100 MHz

t_v(Q)

data output valid time

on pins SD_DATn as outputs

CCLK  100 MHz

1.9

-

3.5

ns

CCLK > 100 MHz

on pins SD_CMD as outputs

CCLK  100 MHz

1.9

-

3.5

ns

CCLK > 100 MHz

T

cy(clk)

SD_CLK

t

h(Q)

d(QV)

SD_CMD (O)

SD_DATn (O)

t

su(D)

h(D)

SD_CMD (I)

SD_DATn (I)

002aag204

Fig 34. SD/MMC and SDIO timing

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11.23 LCD

Table 48. Dynamic characteristics: LCD

T_amb= 40 C to 105 C; V_DD= 2.7 V to 3.6 V; C_L= 30 pF. Simulated values.

Symbol

f_clk

Parameter

Conditions

Min

-

Typ

Max

50

Unit

MHz

ns

clock frequency

on pin LCD_DCLK

-

t_v(Q)

data output valid time on all CCLK  100 MHz

LCD output pins

0.9

1.6

CCLK > 100 MHz

ns

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12. Analog characteristics

12.1 BOD

Table 49. BOD static characteristics

T_amb= 25 C; based on characterization; not tested in production.

Symbol

Parameter

Conditions

interrupt level 0

assertion

Min

Typ

Max

Unit

V_th

threshold voltage

1.5

-

1.63

1.69

V

de-assertion

reset level 0

assertion

1.55

1.5

-

1.62

1.69

V

de-assertion

interrupt level 1

assertion

1.55

V_th

threshold voltage

1.54

1.6

-

1.68

1.75

V

de-assertion

reset level 1

assertion

1.55

1.61

-

1.68

1.74

V

de-assertion

interrupt level 2

assertion

1.79

1.85

-

1.95

2.02

V

de-assertion

reset level 2

assertion

2.04

2.19

-

2.21

2.38

V

de-assertion

interrupt level 3

assertion

2.62

2.77

-

2.86

3.03

V

de-assertion

reset level 3

assertion

2.62

2.78

-

2.85

3.02

V

de-assertion

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12.2 12-bit ADC characteristics

Table 50. 12-bit ADC static characteristics

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V; V_SSA= VREFN = GND. ADC calibrated at T_amb= 25C.

Symbol

Parameter

Conditions

Min

Typ^[2]

Max

Unit

[3]

[4]

V_IA

analog input

voltage

0

-

V_DDA

V

C_ia

analog input

capacitance

5.0

-

pF

f_clk(ADC)

f_s

ADC clock

frequency

80

5.3

-

MHz

sampling

frequency

-

5.0

3.0

Msamples/s

LSB

[1][5]

[1][6]

E_D

differential linearity 2.7 V  V_DDA 3.6 V

error

2.7 V < VREFP  3.6 V

_clk(ADC)= 80 MHz

f

E_L(adj)

integral

2.7 V  V_DDA 3.6 V

-

4.0

-

LSB

non-linearity

2.7 V < VREFP  3.6 V

f_clk(ADC)= 80 MHz

[1][7]

[1][8]

E_O

offset error

calibration enabled

-

2.2

3.0

-

mV

V_err(FS)

full-scale error

voltage

2.7 V  V_DDA 3.6 V

2.7 V < VREFP  3.6 V

LSB

f_clk(ADC)= 80 MHz

[9][10]

Z_i

input impedance

f_s= 5.0 Msamples/s

17.0

-

k

[1] Based on characterization; not tested in production.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5.

[4] C_iarepresents the external capacitance on the analog input channel for sampling speeds of

5.0 Msamples/s. No parasitic capacitances included.

[5] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width.

See Figure 35.

[6] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 35.

[7] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 35.

[8] The full-scale error voltage or gain error (E_G) is the difference between the straight-line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 35.

[9] T_amb= 25 C; maximum sampling frequency f_s= 5.0 Msamples/s and analog input capacitance C_ia= 5 pF.

[10] Input impedance Z_iis inversely proportional to the sampling frequency and the total input capacity including

C_iaand C_io: Z_i 1 / (f_s C_i). See Table 19 for C_io. See Figure 36.

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offset

error

O

gain

error

E

G

4095

4094

4093

4092

4091

4090

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

VREFP - VREFN

1 LSB =

4096

aaa-016908

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 35. 12-bit ADC characteristics

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Table 51. ADC sampling times^[1]

-40 C  T_amb<= 85 C; 2.7 V  V_DDA 3.6 V; 2.7 V  V_DD 3.6 V

Symbol Parameter Conditions

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit

Min

Typ

Max

Unit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

20

23

26

31

47

75

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 10 bit

t_s

sampling time

Z_o< 0.05 kΩ

15

18

20

24

38

62

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 8 bit

t_s

sampling time

Z_o< 0.05 kΩ

12

13

15

19

30

48

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 6 bit

t_s

sampling time

Z_o< 0.05 kΩ

9

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

10

11

13

22

36

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit

t_s

sampling time

Z_o< 0.05 kΩ

43

46

50

56

74

105

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

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Table 51. ADC sampling times^[1]…continued

-40 C  T_amb<= 85 C; 2.7 V  V_DDA 3.6 V; 2.7 V  V_DD 3.6 V

Symbol Parameter Conditions

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit

Min

Typ

Max

Unit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

35

38

40

46

61

86

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit

t_s

sampling time

Z_o< 0.05 kΩ

27

29

32

36

48

69

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit

t_s

sampling time

Z_o< 0.05 kΩ

20

22

23

26

36

51

-

ns

0.05 kΩ <= Z_o< 0.1 kΩ

0.1 kΩ <= Z_o< 0.2 kΩ

0.2 kΩ <= Z_o< 0.5 kΩ

0.5 kΩ <= Z_o< 1 kΩ

1 kΩ <= Z_o< 5 kΩ

[1] Characterized through simulation. Not tested in production.

[2] The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output

impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum

sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.

[3] Z_o= analog source output impedance.

[4] For VDD  2.5 V, add one additional clock cycle to the values in Table 51.

12.2.1 ADC input impedance

Figure 36 shows the ADC input impedance. In this figure:

• ADCx represents slow ADC input channels 6 to 11.

• ADCy represents fast ADC input channels 0 to 5.

• R₁and R_sware the switch-on resistance on the ADC input channel.

• If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through

R_swto the sampling capacitor (C_ia).

• If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through

R₁+ R_swto the sampling capacitor (C_ia).

• Typical values, R₁= 487 , R_sw= 278 

• See Table 19 for C_io.

• See Table 50 for C_ia.

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ADC

R

1

ADCx

ADCy

C

io

C

ia

R

sw

DAC

C

io

aaa-017600

Fig 36. ADC input impedance

12.3 Temperature sensor

Table 52. Temperature sensor static and dynamic characteristics

V_DD= V_DDA= 2.7 V to 3.6 V

Symbol

Parameter

Conditions

_amb= 40 C to +105 C

Min

Typ

Max

Unit

[1]

[2]

DT_sen

sensor

temperature

accuracy

T

-

2.56

C

E_L

linearity error

T_amb= 40 C to +105 C

-

2.56

15.0

C

s

t_s(pu)

power-up

settling time

to 99% of temperature

sensor output value

10.0

[1] Absolute temperature accuracy.

[2] Based on simulation.

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Table 53. Temperature sensor Linear-Least-Square (LLS) fit parameters

V_DD= V_DDA= 2.7 V to 3.6 V

Fit parameter

LLS slope

Range

Min

Typ

2.04

584.0

-

Max

Unit

mV/C

mV

[1]

[2]

T_amb= 40 C to +105 C

-

LLS intercept at 0 C

Value at 30 C

-

520.3

532.7

mV

[1] Measured over typical samples.

[2] Measured for samples over process corners.

DDDꢀꢁꢂꢉꢊꢄꢆ

ꢈꢉꢉ

9

R

ꢋP9ꢌ

//6ꢊIILLWW

ꢇꢉꢉ

ꢄꢉꢉ

ꢁꢉꢉ

ꢉ

ꢏꢄꢉ

ꢏꢀꢉ

ꢁꢉ

ꢃꢉ

ꢈꢉ

ꢀꢀꢉ

7HPSHUDWXUHꢊꢋ&ꢌ

V_DD= V_DDA3.3 V; measured on matrix samples.

Fig 37. LLS fit of the temperature sensor output voltage

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13. Application information

13.1 Start-up behavior

Figure 38 shows the start-up timing after reset. The FRO 12 MHz oscillator provides the

default clock at Reset and provides a clean system clock shortly after the supply pins

reach operating voltage.

FRO

starts

FRO status

internal reset

V

DD

valid threshold

= 1.71 V

t

a

μs

t μs

b

GND

boot time

supply ramp-up

time

user code

t

c

μs

processor status

boot code

execution

finishes;

user code starts

aaa-024049

Fig 38. Start-up timing

Table 54. Typical start-up timing parameters

Parameter

Description

Value

t_a

t_b

FRO start time

 20 s

151 s

Internal reset de-asserted

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13.2 Standard I/O pin configuration

Figure 39 shows the possible pin modes for standard I/O pins:

• Digital output driver: enabled/disabled.

• Digital input: Pull-up enabled/disabled.

• Digital input: Pull-down enabled/disabled.

• Digital input: Repeater mode enabled/disabled.

• Z mode; High impedance (no cross-bar currents for floating inputs).

Default configuration for the standard I/O pins is Z mode (high impedance; pull-up or

pull-down disabled). The weak MOS devices provide a drive capability equivalent to

pull-up and pull-down resistors. GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3, PIO0_4,

PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled in

IOCON register) and will be floating by default. If unused, it is recommended to externally

terminate this pins to prevent leakage.

VDD

ESD

enable output driver

data output from core

slew rate bit SLEW

input buffer enable bit EZI

data input to core

GLITCH

FILTER

filter select bit ZIF

ESD

VSS

pull-up enable bit EPUN

pull-down enable bit EPD

analog I/O

aaa-015595

The glitch filter rejects pulses of typical 12 ns width.

Fig 39. Standard I/O and RESET pin configuration

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13.3 Connecting power, clocks, and debug functions

Figure 40 shows the basic board connections used to power the

LPC54018JxM/LPC54S018JxM devices, connect the external crystal and the 32 kHz

oscillator for the RTC, and provide debug capabilities via the serial wire port.

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3.3 V

SWD connector

(4)

(6)

SWDIO/PIO0_12

~10 kΩ - 100 kΩ

XTALIN

C1

(1)

1

2

C2

XTALOUT

DGND

~10 kΩ - 100 kΩ

SWCLK/PIO0_11

(6)

3

4

RTCXIN

n.c.

C3

(1)

6

8

5

7

9

C4

n.c.

RTCXOUT

DGND

RESETN

10

V

SS

(2)

3.3 V

V

DD

0.1 ꢀF

0.01 ꢀF

DGND

V

SSA

DGND

LPC

AGND

PIO0_4

(3)

V

DDA

3.3 V

0.1 ꢀF

10 ꢀF

PIO0_5

PIO0_6

ISP select pins

(5)

(3)

VREFP

ADCx

3.3 V

0.1 ꢀF

10 ꢀF

0.1 ꢀF

VREFN

AGND

(7)

VBAT

3.3 V

0.1 ꢀF

DGND

AGND

DGND

aaa-029082

(1) See Section 13.6 “XTAL oscillator” for the values of C1, C2, C3, and C4.

(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the V_DDpin. Add one set of decoupling

capacitors to each V_DDpin.

(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and V_DDApins. The 10 μF bypass capacitor

filters the power line. Tie V_DDAand VREFP to V_DDif the ADC is not used. Tie VREFN to V_SSif ADC is not used.

(4) Uses the ARM 10-pin interface for SWD.

(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 3.

(6) External pull-up resistors on SWDIO and SWCLK pins are needed since these pins are in high Z mode (internal pull-up and

pull-down disabled). GPIO pins SWDIO/PIO0_12, SWCLK/PIO0_11, PIO0_2, PIO0_3, PIO0_4, PIO0_5, and PIO0_6 have the

input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will be floating by default. If unused, it is

recommended to externally terminate this pins to prevent leakage.

(7) Position the decoupling capacitor of 0.1 F as close as possible to the V_BATpin. Tie V_BATto V_DDif not used.

Fig 40. Power, clock, and debug connections

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13.4 I/O power consumption

I/O pins are contributing to the overall dynamic and static power consumption of the part.

If pins are configured as digital inputs, a static current can flow depending on the voltage

level at the pin and the setting of the internal pull-up and pull-down resistors. This current

can be calculated using the parameters R_puand R_pdgiven in Table 19 for a given input

voltage V_I. For pins set to output, the current drive strength is given by parameters I_OHand

I_OLin Table 19, but for calculating the total static current, you also need to consider any

external loads connected to the pin.

I/O pins also contribute to the dynamic power consumption when the pins are switching

because the V_DDsupply provides the current to charge and discharge all internal and

external capacitive loads connected to the pin in addition to powering the I/O circuitry.

The contribution from the I/O switching current I_swcan be calculated as follows for any

given switching frequency f_swif the external capacitive load (C_ext) is known (see Table 19

for the internal I/O capacitance):

I

_sw= V_DDx f_swx (C_io+ C_ext)

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13.5 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances C_X1and C_X2

need to be connected externally on RTCXIN and RTCXOUT. See Figure 41.

LPC

L

RTCXIN

RTCXOUT

C

R

C

P

=

L

XTAL

S

C

X2

X1

aaa-029083

Fig 41. RTC oscillator components

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (CL), series resistance (RS), and drive level (DL) are important

parameters to consider while choosing the crystal. After selecting the proper crystal, the

external load capacitor C_X1and C_X2values can also be generally determined by the

following expression:

C_X1= C_X2= 2C_L (C_Pad+ C_Parasitic

)

Where:

C_L- Crystal load capacitance

C_Pad- Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF).

C_Parasitic– Parasitic or stray capacitance of external circuit.

Although C_Parasiticcan be ignored in general, the actual board layout and placement of

external components influences the optimal values of external load capacitors. Therefore,

it is recommended to fine tune the values of external load capacitors on actual hardware

board to get the accurate clock frequency. For fine tuning, output the RTC Clock to the

CLOCKOUT pin and optimize the values of external load capacitors for minimum

frequency deviation.

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13.5.1 RTC Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to

the oscillator input and output pins of the chip.

• The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal

usage, have a common ground plane.

• Loops must be made as small as possible to minimize the noise coupled in through

the PCB and to keep the parasitics as small as possible.

• Lay out the ground (GND) pattern under crystal unit.

• Do not lay out other signal lines under crystal unit for multi-layered PCB.

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13.6 XTAL oscillator

In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances C_X1and C_X2

need to be connected externally on XTALIN and XTALOUT. See Figure 42.

LPCxxxx

L

XTALIN

XTALOUT

C

R

C

P

=

L

XTAL

S

C

X2

X1

aaa-025725

Fig 42. XTAL oscillator components

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (CL), series resistance (RS), and drive level (DL) are important

parameters to consider while choosing the crystal. After selecting the proper crystal, the

external load capacitor C_X1and C_X2values can also be generally determined by the

following expression:

C_X1= C_X2= 2C_L (C_Pad+ C_Parasitic

)

Where:

C_L- Crystal load capacitance

C_Pad- Pad capacitance of the XTALIN and XTALOUT pins (~3 pF).

C_Parasitic– Parasitic or stray capacitance of external circuit.

Although C_Parasiticcan be ignored in general, the actual board layout and placement of

external components influences the optimal values of external load capacitors. Therefore,

it is recommended to fine tune the values of external load capacitors on actual hardware

board to get the accurate clock frequency. For fine tuning, measure the clock on the

XTALOUT pin and optimize the values of external load capacitors for minimum frequency

deviation.

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13.6.1 XTAL Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to

the oscillator input and output pins of the chip.

• The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal

usage, have a common ground plane.

• Loops must be made as small as possible to minimize the noise coupled in through

the PCB and to keep the parasitics as small as possible.

• Lay out the ground (GND) pattern under crystal unit.

• Do not lay out other signal lines under crystal unit for multi-layered PCB.

13.7 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 43) or

bus-powered device (see Figure 44).

On the LPC54018JxM/LPC54S018JxM, the USB_VBUS pin is 5 V tolerant only when V_DD

is applied and at operating voltage level. Therefore, if the USB_VBUS function is

connected to the USB connector and the device is self-powered, the USB_VBUS pin must

be protected for situations when V_DD= 0 V.

If V_DDis always at operating level while VBUS = 5 V, the USB_VBUS pin can be

connected directly to the VBUS pin on the USB connector.

For systems where V_DDcan be 0 V and VBUS is directly applied to the VBUS pin,

precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum

allowable voltage on the USB_VBUS pin in this case.

One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the

USB connector. The voltage divider ratio should be such that the USB_VBUS pin is

greater than 0.7 V_DDto indicate a logic HIGH while below the 3.6 V allowable maximum

voltage.

For the following operating conditions

VBUS_max= 5.25 V

V_DD= 3.6 V,

the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.

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LPCxxxx

V

DD

R2

R3

R1

1.5 kꢁ

USB

USB_VBUS

D+

D-

USB-B

connector

R

= 33 ꢁ

S

USB_DP

USB_DM

V

SS

aaa-023996

Fig 43. USB interface on a self-powered device where USB_VBUS = 5 V

The internal pull-up (1.5 k) can be enabled by setting the DCON bit in the

DEVCMDSTAT register to prevent the USB from timing out when there is a significant

delay between power-up and handling USB traffic. External circuitry is not required.

LPCxxxx

V

DD

REGULATOR

(1)

(2)

USB_VBUS

USB

R1

1.5 kꢁ

VBUS

D+

USB-B

R

= 33 ꢁ

S

USB_DP

D-

connector

R

USB_DM

V

SS

aaa-023997

Two options exist for connecting VBUS to the USB_VBUS pin:

(1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered.

(2) Connect the VBUS signal directly from the connector to the USB_VBUS pin. In this case, 5 V are applied to the USB_VBUS pin

while the regulator is ramping up to supply V_DD. Since the USB_VBUS pin is only 5 V tolerant when V_DDis at operating level,

this connection can degrade the performance of the part over its lifetime. Simulation shows that lifetime is reduced to 15 years

at T_amb= 45 °C and 8 years at T_amb= 55 °C assuming that USB_VBUS = 5 V is applied continuously while V_DD= 0 V.

Fig 44. USB interface on a bus-powered device

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142 of 150

LPC54018JxM/LPC54S018JxM

NXP Semiconductors

32-bit ARM Cortex-M4 microcontroller

14. Package outline

TFBGA180: thin fine-pitch ball grid array package; 180 balls

SOT570-3

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

C

M

∅ v

∅ w

C

A

B

e

1/2 e

b

y

C

1

P

N

M

K

H

L

J

e

2

G

E

F

1/2 e

D

C

A

B

ball A1

index area

1

3

5

7

9

11

13

2

4

6

8

10

12

14

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max 1.20 0.40 0.80 0.50 12.1 12.1

nom 1.06 0.35 0.71 0.45 12.0 12.0

mm

0.8

10.4 10.4 0.15 0.05 0.12

0.1

min

0.95 0.30 0.65 0.40 11.9 11.9

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

08-07-09

10-04-15

SOT570-3

Fig 45. TFBGA180 package

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Product data sheet

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LPC54018JxM/LPC54S018JxM

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32-bit ARM Cortex-M4 microcontroller

15. Soldering

Footprint information for reflow soldering of TFBGA180 package

SOT570-3

Hx

P

Hy

see detail X

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste deposit

solder land plus solder paste

SL

SP

SR

occupied area

solder resist

detail X

DIMENSIONS in mm

P

SL

SP

SR

Hx

Hy

0.80

0.400 0.400 0.550 12.575 12.575

sot570-3_fr

Fig 46. Reflow soldering of the TFBGA180 package

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32-bit ARM Cortex-M4 microcontroller

16. Abbreviations

Table 55. Abbreviations

Acronym

AHB

Description

Advanced High-performance Bus

Advanced Peripheral Bus

APB

API

Application Programming Interface

Direct Memory Access

DMA

FRO oscillator

GPIO

FRO

Internal Free-Running Oscillator, tuned to the factory specified frequency

General Purpose Input/Output

Free Running Oscillator

LSB

Least Significant Bit

MCU

MicroController Unit

PDM

Pulse Density Modulation

PLL

Phase-Locked Loop

SPI

Serial Peripheral Interface

TCP/IP

TTL

Transmission Control Protocol/Internet Protocol

Transistor-Transistor Logic

USART

Universal Asynchronous Receiver/Transmitter

17. References

[1] LPC54018JxM/LPC54S018JxM. User manual UM11155

[2] LPC54018JxM/LPC54S018JxM. Errata sheet.

[3] Technical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

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18. Revision history

Table 56. Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

- v.1.0

LPC54018JxM/LPC54S018JxM v1.1 20190127

Product data sheet

Modifications:

• Updated Table 4 “Pin description”: Added text to USB1_VBUS.

• Updated Table 12 “General operating conditions”: Added USB1 analog supply.

• Updated Section 7.13.2 “Deep-sleep mode”: Added text: In deep-sleep mode, the

system clock to the processor is disabled as in sleep mode. All analog blocks are

powered down by default but can be selected to keep running through the power

API if needed as wake-up sources. The main clock and all peripheral clocks are

disabled by default.

• Updated part number in ordering information

LPC54018JxM/LPC54S018JxM v1.0 20180918

Product data sheet

-

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

19.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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32-bit ARM Cortex-M4 microcontroller

21. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.16

Serial peripherals . . . . . . . . . . . . . . . . . . . . . . 60

7.16.1

Full-speed USB Host/Device interface (USB0) . .

60

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 6

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 7

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

3.1

4

7.16.1.1 USB0 device controller. . . . . . . . . . . . . . . . . . 60

7.16.1.2 USB0 host controller . . . . . . . . . . . . . . . . . . . 61

7.16.2

High-speed USB Host/Device interface (USB1) .

61

5

6

6.1

6.2

6.2.1

6.2.2

Pinning information. . . . . . . . . . . . . . . . . . . . . 11

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 12

Termination of unused pins. . . . . . . . . . . . . . . 43

Pin states in different power modes . . . . . . . . 44

7.16.2.1 USB1 device controller. . . . . . . . . . . . . . . . . . 61

7.16.2.2 USB1 host controller . . . . . . . . . . . . . . . . . . . 61

7.16.3

7.16.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.16.4 SPI Flash Interface (SPIFI) . . . . . . . . . . . . . . 62

7.16.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.16.5 CAN Flexible Data (CAN FD) interface . . . . . 63

7.16.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.16.6 DMIC subsystem . . . . . . . . . . . . . . . . . . . . . . 63

7.16.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.16.7 Smart card interface. . . . . . . . . . . . . . . . . . . . 63

7.16.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.16.8 Flexcomm Interface serial communication. . . 63

Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . . 62

7

Functional description . . . . . . . . . . . . . . . . . . 46

Architectural overview. . . . . . . . . . . . . . . . . . . 46

ARM Cortex-M4 processor . . . . . . . . . . . . . . . 46

ARM Cortex-M4 integrated Floating Point Unit

(FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Memory Protection Unit (MPU). . . . . . . . . . . . 46

Nested Vectored Interrupt Controller (NVIC) for

Cortex-M4. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 47

System Tick timer (SysTick) . . . . . . . . . . . . . . 47

On-chip serial flash. . . . . . . . . . . . . . . . . . . . . 47

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 47

On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 47

Memory mapping . . . . . . . . . . . . . . . . . . . . . . 48

One-Time Programmable (OTP) memory. . . . 51

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

System control . . . . . . . . . . . . . . . . . . . . . . . . 52

Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1

7.2

7.3

7.4

7.5

7.16.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.16.8.2 SPI serial I/O controller . . . . . . . . . . . . . . . . . 64

7.16.8.3 I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . 64

7.16.8.4 USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.16.8.5 I²S-bus interface. . . . . . . . . . . . . . . . . . . . . . . 65

7.5.1

7.5.2

7.6

7.7

7.8

7.17

7.17.1

Digital peripheral . . . . . . . . . . . . . . . . . . . . . . 66

LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 66

7.9

7.10

7.11

7.11.1

7.12

7.12.1

7.17.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.17.2 SD/MMC card interface . . . . . . . . . . . . . . . . . 67

7.17.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.17.3 External memory controller . . . . . . . . . . . . . . 67

7.17.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.17.4 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 69

7.17.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.12.1.1 Free Running Oscillator (FRO). . . . . . . . . . . . 52

7.12.1.2 Watchdog oscillator (WDOSC) . . . . . . . . . . . . 52

7.12.1.3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 52

7.12.2

7.12.3

7.12.4

7.12.5

7.12.6

7.12.7

7.13

7.13.1

7.13.2

7.13.3

7.14

7.14.1

7.15

7.18

7.18.1

Counter/timers . . . . . . . . . . . . . . . . . . . . . . . . 69

General-purpose 32-bit timers/external event

counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

System PLL (PLL0). . . . . . . . . . . . . . . . . . . . . 52

USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . . 52

Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . . 53

Clock Generation . . . . . . . . . . . . . . . . . . . . . . 54

Brownout detection. . . . . . . . . . . . . . . . . . . . . 56

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 56

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 56

Deep power-down mode. . . . . . . . . . . . . . . . . 56

General Purpose I/O (GPIO) . . . . . . . . . . . . . 59

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Pin interrupt/pattern engine . . . . . . . . . . . . . . 59

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.18.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.18.2 SCTimer/PWM . . . . . . . . . . . . . . . . . . . . . . . . 70

7.18.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.18.3 Windowed WatchDog Timer (WWDT) . . . . . . 71

7.18.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.18.4

7.18.5

Real Time Clock (RTC) timer . . . . . . . . . . . . . 71

Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 71

7.18.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.18.6 Repetitive Interrupt Timer (RIT) . . . . . . . . . . . 72

7.18.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.19

12-bit Analog-to-Digital Converter (ADC). . . . 72

7.15.1

continued >>

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Product data sheet

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32-bit ARM Cortex-M4 microcontroller

7.19.1

7.20

7.20.1

7.21

7.22

7.22.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

13

Application information . . . . . . . . . . . . . . . . 133

Start-up behavior . . . . . . . . . . . . . . . . . . . . . 133

Standard I/O pin configuration . . . . . . . . . . . 134

Connecting power, clocks, and debug functions .

135

I/O power consumption . . . . . . . . . . . . . . . . 137

RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . 138

RTC Printed Circuit Board (PCB) design

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 139

XTAL oscillator . . . . . . . . . . . . . . . . . . . . . . . 140

XTAL Printed Circuit Board (PCB) design

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Suggested USB interface solutions . . . . . . . 141

CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Temperature sensor . . . . . . . . . . . . . . . . . . . . 73

Security features. . . . . . . . . . . . . . . . . . . . . . . 73

SHA-1 and SHA-2. . . . . . . . . . . . . . . . . . . . . . 73

13.1

13.2

13.3

13.4

13.5

13.5.1

7.22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.22.2 AES encryption/decryption . . . . . . . . . . . . . . . 74

7.22.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.22.3 PUF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.22.3.1 PUF keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.22.3.2 PUF controller features. . . . . . . . . . . . . . . . . . 74

13.6

13.6.1

7.23

Emulation and debugging. . . . . . . . . . . . . . . . 75

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 76

Thermal characteristics. . . . . . . . . . . . . . . . . . 78

13.7

14

8

Package outline. . . . . . . . . . . . . . . . . . . . . . . 143

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 145

References. . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Revision history . . . . . . . . . . . . . . . . . . . . . . 146

9

15

10

Static characteristics. . . . . . . . . . . . . . . . . . . . 79

General operating conditions . . . . . . . . . . . . . 79

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 79

Power consumption . . . . . . . . . . . . . . . . . . . . 81

Pin characteristics. . . . . . . . . . . . . . . . . . . . . . 87

Electrical pin characteristics . . . . . . . . . . . . . . 90

16

10.1

10.2

10.3

10.4

10.4.1

17

18

19

Legal information . . . . . . . . . . . . . . . . . . . . . 147

Data sheet status . . . . . . . . . . . . . . . . . . . . . 147

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 147

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 148

19.1

19.2

19.3

19.4

11

11.1

11.2

11.3

11.4

11.5

11.6

11.7

Dynamic characteristics . . . . . . . . . . . . . . . . . 93

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 94

External memory interface . . . . . . . . . . . . . . . 95

System PLL (PLL0) . . . . . . . . . . . . . . . . . . . 104

USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . 105

Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . 105

FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 106

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107

Watchdog oscillator . . . . . . . . . . . . . . . . . . . 108

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

I²S-bus interface. . . . . . . . . . . . . . . . . . . . . . 111

SPI interfaces (Flexcomm Interface 0-9) . . . 113

SPI interfaces (Flexcomm Interface 10) . . . . 116

DMIC subsystem . . . . . . . . . . . . . . . . . . . . . 119

Smart card interface . . . . . . . . . . . . . . . . . . . 119

USART interface. . . . . . . . . . . . . . . . . . . . . . 120

SCTimer/PWM output timing . . . . . . . . . . . . 121

USB interface characteristics . . . . . . . . . . . . 121

Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . 122

SD/MMC and SDIO . . . . . . . . . . . . . . . . . . . 123

LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

20

21

Contact information . . . . . . . . . . . . . . . . . . . 148

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

11.8

11.9

11.10

11.11

11.12

11.13

11.14

11.15

11.16

11.17

11.18

11.19

11.21

11.22

11.23

12

Analog characteristics . . . . . . . . . . . . . . . . . 126

BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

12-bit ADC characteristics . . . . . . . . . . . . . . 127

ADC input impedance. . . . . . . . . . . . . . . . . . 130

Temperature sensor . . . . . . . . . . . . . . . . . . . 131

12.1

12.2

12.2.1

12.3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 January 2019

Document identifier: LPC54018JxM/LPC54S018JxM


型号：	LPC54018J2MET180E
厂家：	NXP
描述：	RISC Microcontroller 微控制器外围集成电路
文件：	总150页 (文件大小：5544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC54018J2MET180E [NXP]

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