LPC82X_技术文档

LPC82x

32-bit ARM^®Cortex^®-M0+ microcontroller; up to 32 kB flash

and 8 kB SRAM; 12-bit ADC; comparator

Rev. 1.4 — 19 March 2021

Product data sheet

1. General description

The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and

8 KB of SRAM.

The peripheral complement of the LPC82x includes a CRC engine, four I²C-bus

interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer,

self-wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a

DMA, one 12-bit ADC and one analog comparator, function-configurable I/O ports through

a switch matrix, an input pattern match engine, and up to 29 general-purpose I/O pins.

For additional documentation related to the LPC82x parts, see Section 18.

2. Features and benefits

 System:

 ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to

30 MHz with single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 AHB multilayer matrix.

 Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

 MTB

 Memory:

 Up to 32 KB on-chip flash programming memory with 64 Byte page write and

erase. Code Read Protection (CRP) supported.

 8 KB SRAM.

 ROM API support:

 Boot loader.

 On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power

profiles) and integer divide.

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

 Digital peripherals:

 High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 29

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and digital filter. GPIO direction

control supports independent set/clear/toggle of individual bits.

 High-current source output driver (20 mA) on four pins.

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

 High-current sink driver (20 mA) on two true open-drain pins.

 GPIO interrupt generation capability with boolean pattern-matching feature on

eight GPIO inputs.

 Switch matrix for flexible configuration of each I/O pin function.

 CRC engine.

 DMA with 18 channels and 9 trigger inputs.

 Timers:

 State Configurable Timer (SCTimer/PWM) with input and output functions

(including capture and match) for timing and PWM applications. Each

SCTimer/PWM input is multiplexed to allow selecting from several input sources

such as pins, ADC interrupt, or comparator output.

 Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

 Self-Wake-up Timer (WKT) clocked from either the IRC, a low-power,

low-frequency internal oscillator, or an external clock input in the always-on power

domain.

 Windowed Watchdog timer (WWDT).

 Analog peripherals:

 One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports

two independent conversion sequences.

 Comparator with four input pins and external or internal reference voltage.

 Serial peripherals:

 Three USART interfaces with pin functions assigned through the switch matrix and

one common fractional baud rate generator.

 Two SPI controllers with pin functions assigned through the switch matrix.

 Four I²C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates

on two true open-drain pins and listen mode. Three I2Cs support data rates up to

400 kbit/s on standard digital pins.

 Clock generation:

 12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be

used as a system clock.

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock

input, or the internal RC oscillator.

 Clock output function with divider that can reflect all internal clock sources.

 Power control:

 Power consumption in active mode as low as 90 uA/MHz in low-current mode

using the IRC as the clock source.

 Integrated PMU (Power Management Unit) to minimize power consumption.

 Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

 Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and

I2C peripherals.

 Timer-controlled self wake-up from Deep power-down mode.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

2 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

 Power-On Reset (POR).

 Brownout detect (BOD).

 Unique device serial number for identification.

 Single power supply (1.8 V to 3.6 V).

 Operating temperature range -40 °C to +105 °C.

 Available in a TSSOP20 and HVQFN33 (5x5) package.

3. Applications

 Sensor gateways

 Industrial

 Simple motor control

 Portables and wearables

 Lighting

 Gaming controllers

 8/16-bit applications

 Consumer

 Motor control

 Fire and security applications

 Climate control

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC824M201JHI33

LPC822M101JHI33

HVQFN33

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; n/a

33 terminals; body 5  5  0.85 mm

HVQFN33

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; n/a

33 terminals; body 5  5  0.85 mm

LPC824M201JDH20 TSSOP20

LPC822M101JDH20 TSSOP20

plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

4.1 Ordering options

Table 2.

Ordering options

Type number

Flash/ SRAM/ USART I²C

KB KB

SPI ADC

channels

Comparator GPIO

Package

LPC824M201JHI33

LPC822M101JHI33

LPC824M201JDH20

LPC822M101JDH20

32

8

3

4

2

12

Y

y

29

16

HVQFN33

TSSOP20

16

32

16

4

8

4

12

5

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

3 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

5. Marking

20

Terminal 1 index area

1

aaa-014766

aaa-014382

Fig 1. TSSOP20 package marking

Fig 2. HVQFN33 package marking

The HVQFN33 packages typically have the following top-side marking:

82xJ

xx xx

yywwxR

The TSSOP20 packages typically have the following top-side marking:

LPC82x

Mx01J

xxxxxxxx

zzywwxR

In the last line, field ‘y’ or ‘yy’ states the year the device was manufactured. Field ‘ww’

states the week the device was manufactured during that year. Field ‘R’ states the chip

revision.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

4 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

6. Block diagram

LPC82xM

SWCLK, SWD

TEST/DEBUG

INTERFACE

29 x

PIO0

HIGH-SPEED

GPIO

ARM

CORTEX-M0+

FLASH

16/32 KB

SRAM

4/8 KB

ROM

PIN INTERRUPTS/

PATTERN MATCH

slave

SCT_PIN[3:0]

SCT_OUT[6:0]

SCTIMER/

PWM

AHB-LITE BUS

slave master

slave

CRC

DMA

AHB TO APB

BRIDGE

TXD, RTS

RXD, CTS

SCLK

WWDT

IOCON

USART0/1/2

SPI0/1

SCK, SSEL

MISO, MOSI

29 x

SWITCH

MATRIX

MULTI-RATE TIMER

SCL

SDA

2

I C0/1/2/3

XTALOUT

XTALIN

PMU

XTAL

SYSCON

RESET, CLKIN

CLKOUT

SELF

WAKE-UP TIMER

ALWAYS-ON POWER DOMAIN

IRC

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

WDOsc

BOD

ADC_[11:0]

ADC

FUNCTIONS

POR

ACMP_I[4:1]

VDDCMP

ACMP_O

COMPARATOR

clocks and

controls

aaa-014399

Gray-shaded blocks show peripherals that can provide hardware triggers or fixed DMA requests for DMA transfers.

Fig 3. LPC82x block diagram

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

5 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

7. Pinning information

7.1 Pinning

1

2

20

19

18

17

16

15

14

13

12

11

PIO0_23/ADC_3/ACMP_I4

PIO0_14/ADC_2/ACMP_I3

PIO0_0/ACMP_I1/TDO

VREFP

PIO0_17/ADC_9

PIO0_13/ADC_10

3

4

PIO0_12

VREFN

5

RESET/PIO0_5

V

SS

V

DD

TSSOP20

6

PIO0_4/ADC_11/WAKEUP/TRST

SWCLK/PIO0_3/TCK

SWDIO/PIO0_2/TMS

PIO0_11/I2C0_SDA

PIO0_10/I2C0_SCL

7

PIO0_8/XTALIN

8

PIO0_9/XTALOUT

PIO0_1/ACMP_I2/CLKIN/TDI

PIO0_15

9

10

aaa-011391

Fig 4.

Pin configuration TSSOP20 package

terminal 1

index area

1

2

3

4

5

6

7

8

24

PIO0_13/ADC_10

PIO0_12

PIO0_0/ACMP_I1/TDO

PIO0_6/ADC_1/VDDCMP

PIO0_7/ADC_0

VREFP

23

22

21

20

19

18

17

PIO0_5/RESET

PIO0_4/ADC_11/TRST

PIO0_28/WKTCLKIN

SWCLK/PIO0_3/TCK

SWDIO/PIO0_2/TMS

PIO0_11/I2C0_SDA

VREFN

V

DD

PIO0_8/XTALIN

33 V

SS

PIO0_9/XTALOUT

aaa-011396

Transparent top view

Fig 5.

Pin configuration HVQFN33 package

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

6 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

7.2 Pin description

The pin description table Table 3 shows the pin functions that are fixed to specific pins on

each package. These fixed-pin functions are selectable through the switch matrix

between GPIO and the comparator, ADC, SWD, RESET, and the XTAL pins. By default,

the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG

functions are available in boundary scan mode only.

Movable function for the I2C, USART, SPI, and SCT pin functions can be assigned

through the switch matrix to any pin that is not power or ground in place of the pin’s fixed

functions.

The following exceptions apply:

Do not assign more than one output to any pin. However, more than one input can be

assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is

disabled.

Pin PIO0_4 triggers a wake-up from Deep power-down mode. If the part must wake up

from Deep power-down mode via an external pin, do not assign any movable function to

this pin.

The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to

PIO0_4 by hardware when the part is in boundary scan mode.

Table 3.

Symbol

Pin description

Reset

state^[1]

Type

Description

[2]

PIO0_0/ACMP_I1/

TDO

19 24

I; PU

IO

PIO0_0 — General-purpose port 0 input/output 0.

In ISP mode, this is the U0_RXD pin.

In boundary scan mode: TDO (Test Data Out).

ACMP_I1 — Analog comparator input 1.

PIO0_1 — General-purpose port 0 input/output 1.

In boundary scan mode: TDI (Test Data In).

ACMP_I2 — Analog comparator input 2.

CLKIN — External clock input.

A

PIO0_1/ACMP_I2/

CLKIN/TDI

12 16

IO

A

I

[4]

SWDIO/PIO0_2/

TMS

8

7

6

I; PU

IO

SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default

on this pin. In boundary scan mode: TMS (Test Mode Select).

I/O

I

PIO0_2 — General-purpose port 0 input/output 2.

SWCLK/PIO0_3/

TCK

SWCLK — Serial Wire Clock. SWCLK is enabled by default on

this pin.

In boundary scan mode: TCK (Test Clock).

IO

PIO0_3 — General-purpose port 0 input/output 3.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

7 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 3.

Symbol

Pin description

Reset

state^[1]

Type

Description

[3]

PIO0_4/ADC_11/

TRSTN/WAKEUP

6

4

I; PU

IO

PIO0_4 — General-purpose port 0 input/output 4.

In boundary scan mode: TRST (Test Reset).

In ISP mode, this pin is the U0_TXD pin.

This pin triggers a wake-up from Deep power-down mode. If the

part must wake up from Deep power-down mode via an external

pin, do not assign any movable function to this pin. This pin

should be pulled HIGH externally before entering Deep

power-down mode. A LOW-going pulse as short as 50 ns causes

the chip to exit Deep power-down mode and wakes up the part.

A

ADC_11 — ADC input 11.

[7]

RESET/PIO0_5

5

3

I; PU

IO

RESET — External reset input: A LOW-going pulse as short as

50 ns on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor

execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH

externally. The RESET pin can be left unconnected or be used as

a GPIO or for any movable function if an external RESET function

is not needed and the Deep power-down mode is not used.

I

PIO0_5 — General-purpose port 0 input/output 5.

PIO0_6 — General-purpose port 0 input/output 6.

ADC_1 — ADC input 1.

[10]

PIO0_6/ADC_1/

VDDCMP

-

23

22

I; PU

IO

A

VDDCMP — Alternate reference voltage for the analog

comparator.

[2]

[8]

PIO0_7/ADC_0

PIO0_8/XTALIN

I; PU

IO

A

PIO0_7 — General-purpose port 0 input/output 7.

ADC_0 — ADC input 0.

14 18

13 17

IO

A

PIO0_8 — General-purpose port 0 input/output 8.

XTALIN — Input to the oscillator circuit and internal clock

generator circuits. Input voltage must not exceed 1.95 V.

[8]

[6]

PIO0_9/XTALOUT

I; PU

IO

A

PIO0_9 — General-purpose port 0 input/output 9.

XTALOUT — Output from the oscillator circuit.

PIO0_10/I2C0_SCL 10

9

Inactive I; F

PIO0_10 — General-purpose port 0 input/output 10 (open-drain).

I2C0_SCL — Open-drain I²C-bus clock input/output. High-current

sink if I²C Fast-mode Plus is selected in the I/O configuration

register.

[6]

PIO0_11/I2C0_SDA

9

8

Inactive I; F

PIO0_11 — General-purpose port 0 input/output 11 (open-drain).

I2C0_SDA — Open-drain I²C-bus data input/output. High-current

sink if I²C Fast-mode Plus is selected in the I/O configuration

register.

[4]

[2]

PIO0_12

4

3

2

1

I; PU

IO

PIO0_12 — General-purpose port 0 input/output 12. ISP entry

pin. A LOW level on this pin during reset starts the ISP command

handler.

PIO0_13/ADC_10

IO

A

PIO0_13 — General-purpose port 0 input/output 13.

ADC_10 — ADC input 10.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

8 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 3.

Symbol

Pin description

Reset

state^[1]

Type

Description

[2]

PIO0_14/

ACMP_I3/ADC_2

20 25

11 15

I; PU

IO

A

PIO0_14 — General-purpose port 0 input/output 14.

ACMP_I3 — Analog comparator common input 3.

ADC_2 — ADC input 2.

A

[5]

[4]

[2]

PIO0_15

I; PU

IO

A

PIO0_15 — General-purpose port 0 input/output 15.

PIO0_16 — General-purpose port 0 input/output 16.

PIO0_17 — General-purpose port 0 input/output 17.

ADC_9 — ADC input 9.

PIO0_16

-

10

32

PIO0_17/ADC_9

2

[2]

PIO0_18/ADC_8

PIO0_19/ADC_7

PIO0_20/ADC_6

PIO0_21/ADC_5

PIO0_22/ADC_4

-

31

30

29

28

27

26

I; PU

IO

A

PIO0_18 — General-purpose port 0 input/output 18.

ADC_8 — ADC input 8.

-

IO

A

PIO0_19 — General-purpose port 0 input/output 19.

ADC_7 — ADC input 7.

-

IO

A

PIO0_20 — General-purpose port 0 input/output 20.

ADC_6 — ADC input 6.

-

IO

A

PIO0_21 — General-purpose port 0 input/output 21.

ADC_5 — ADC input 5.

-

IO

A

PIO0_22 — General-purpose port 0 input/output 22.

ADC_4 — ADC input 4.

PIO0_23/ADC_3/

ACMP_I4

1

IO

A

PIO0_23 — General-purpose port 0 input/output 23.

ADC_3 — ADC input 3.

A

ACMP_I4 — Analog comparator common input 4.

PIO0_24 — General-purpose port 0 input/output 24.

PIO0_25 — General-purpose port 0 input/output 25.

PIO0_26 — General-purpose port 0 input/output 26.

PIO0_27 — General-purpose port 0 input/output 27.

[5]

[3]

PIO0_24

PIO0_25

PIO0_26

PIO0_27

-

14

13

12

11

5

I; PU

IO

PIO0_28/

PIO0_28 — General-purpose port 0 input/output 28. This pin can

host an external clock for the self-wake-up timer. To use the pin

as a self-wake-up timer clock input, select the external clock in the

wake-up timer CTRL register. The external clock input is active in

all power modes, including deep power-down.

WKTCLKIN

V_DD

15 19

-

Supply voltage for the I/O pad ring, the core voltage regulator, and

the analog peripherals.

V_SS

16 33^[11]

17 20

-

Ground.

VREFN

VREFP

ADC negative reference voltage.

18 21

ADC positive reference voltage. Must be equal or lower than V_DD.

[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V_DD

level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 14.5 “Pin states in

different power modes”. For termination on unused pins, see Section 14.4 “Termination of unused pins”.

[2] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

9 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. This pin is

active in Deep power-down mode and includes a 20 ns glitch filter (active in all power modes). In Deep power-down mode, pulling the

WAKEUP pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other purposes, if the

WKT low-power oscillator is enabled for waking up the part from Deep power-down mode. See Table 17 “Dynamic characteristics:

WKTCLKIN pin” for the WKTCLKIN input.

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[6] True open-drain pin. I²C-bus pins compliant with the I²C-bus specification for I²C standard mode, I²C Fast-mode, and I²C Fast-mode

Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output

functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all

functions on this pin.

[7] See Figure 10 for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is

not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An

external pull-up resistor is required on this pin for the Deep power-down mode.

[8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system

oscillator. When configured for XTALIN and XTALOUT, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[9] The WKTCLKIN function is enabled in the DPDCTRL register in the PMU. See the LPC82x user manual.

[10] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with

configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is

disabled.

[11] Thermal pad for HVQFN33.

Table 4.

Movable functions (assign to pins PIO0_0 to PIO0_28 through switch matrix)

Function name

U0_TXD

Type

O

Description

Transmitter output for USART0.

Receiver input for USART0.

U0_RXD

I

U0_RTS

O

Request To Send output for USART0.

Clear To Send input for USART0.

Serial clock input/output for USART0 in synchronous mode.

Transmitter output for USART1.

Receiver input for USART1.

U0_CTS

I

U0_SCLK

U1_TXD

I/O

O

U1_RXD

I

U1_RTS

O

Request To Send output for USART1.

Clear To Send input for USART1.

Serial clock input/output for USART1 in synchronous mode.

Transmitter output for USART2.

Receiver input for USART2.

U1_CTS

I

U1_SCLK

U2_TXD

I/O

O

U2_RXD

I

U2_RTS

O

Request To Send output for USART1.

Clear To Send input for USART1.

Serial clock input/output for USART1 in synchronous mode.

Serial clock for SPI0.

U2_CTS

I

U2_SCLK

SPI0_SCK

SPI0_MOSI

SPI0_MISO

SPI0_SSEL0

SPI0_SSEL1

SPI0_SSEL2

SPI0_SSEL3

SPI1_SCK

I/O

Master Out Slave In for SPI0.

Master In Slave Out for SPI0.

Slave select 0 for SPI0.

Slave select 1 for SPI0.

Slave select 2 for SPI0.

Slave select 3 for SPI0.

Serial clock for SPI1.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

10 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 4.

Movable functions (assign to pins PIO0_0 to PIO0_28 through switch matrix)

Function name

SPI1_MOSI

SPI1_MISO

SPI1_SSEL0

SPI1_SSEL1

SCT_PIN0

Type

I/O

I

Description

Master Out Slave In for SPI1.

Master In Slave Out for SPI1.

Slave select 0 for SPI1.

Slave select 1 for SPI1.

Pin input 0 to the SCT input multiplexer.

Pin input 1 to the SCT input multiplexer.

Pin input 2 to the SCT input multiplexer.

Pin input 3 to the SCT input multiplexer.

SCT output 0.

SCT_PIN1

I

SCT_PIN2

I

SCT_PIN3

I

SCT_OUT0

SCT_OUT1

SCT_OUT2

SCT_OUT3

SCT_OUT4

SCT_OUT5

I2C1_SDA

O

SCT output 1.

O

SCT output 2.

O

SCT output 3.

O

SCT output 4.

O

SCT output 5.

I/O

I

I²C1-bus data input/output.

I²C1-bus clock input/output.

I²C2-bus data input/output.

I²C2-bus clock input/output.

I²C3-bus data input/output.

I²C3-bus clock input/output.

ADC external pin trigger input 0.

ADC external pin trigger input 1.

Analog comparator output.

Clock output.

I2C1_SCL

I2C2_SDA

I2C2_SCL

I2C3_SDA

I2C3_SCL

ADC_PINTRIG0

ADC_PINTRIG1

ACMP_O

I

O

CLKOUT

O

GPIO_INT_BMAT

O

Output of the pattern match engine.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

11 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8. Functional description

8.1 ARM Cortex-M0+ core

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a

two-stage pipeline. The core revision is r0p1.

Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two

watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast

GPIO access.

The core includes a single-cycle multiplier and a system tick timer.

8.2 On-chip flash program memory

The LPC82x contain up to 32 KB of on-chip flash program memory. The flash memory

supports a 64 Byte page size with page write and erase.

8.3 On-chip SRAM

The LPC82x contain a total of 8 KB on-chip static RAM data memory in two separate

SRAM blocks with one combined clock for both SRAM blocks.

8.4 On-chip ROM

The on-chip ROM contains the bootloader and the following Application Programming

Interfaces (APIs):

• In-System Programming (ISP) and In-Application Programming (IAP) support for flash

including IAP erase page command.

• Power profiles for configuring power consumption and PLL settings

• 32-bit integer division routines

• APIs to use the following peripherals:

– SPI

– USART

– I2C

– ADC

8.5 Memory map

The LPC82x incorporates several distinct memory regions. Figure 6 shows the overall

map of the entire address space from the user program viewpoint following reset. The

interrupt vector area supports address remapping.

The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,

the system tick timer (SysTick), and the reduced power modes.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

12 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

LPC82x

4 GB

0xFFFF FFFF

0xE010 0000

0xE000 0000

reserved

APB peripherals

0x4008 0000

private peripheral bus

reserved

30 - 31 reserved

0x4007 8000

0xA000 8000

I2C3

29

28

27

26

25

24

23

22

0x4007 4000

0x4007 0000

0x4006 C000

GPIO PINT

GPIO

0xA000 4000

0xA000 0000

I2C2

USART2

USART1

USART0

reserved

SPI1

0x4006 8000

0x4006 4000

reserved

0x4006 0000

0x4005 C000

0x5000 C000

0x5000 8000

0x5000 4000

0x5000 0000

DMA

SCTimer/PWM

CRC

SPI0

0x4005 8000

0x4005 4000

0x4005 0000

I2C1

I2C0

21

20

19

reserved

APB peripherals

reserved

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

system control (SYSCON)

IOCON

18

17

0x4008 0000

0x4000 0000

1 GB

flash controller

reserved

16

15

0x4003 C000

0x4003 8000

0x4003 4000

14

reserved

13

12

reserved

input mux

0x2000 0000

0x4003 0000

0x4002 C000

0x4002 8000

0.5 GB

11

10

9

reserved

DMA TRIGMUX

analog comparator

0x1FFF 3000

0x1FFF 0000

0x4002 4000

0x4002 0000

12 KB boot ROM

PMU

8

reserved

12-bit ADC

reserved

7

0x4001 C000

0x4001 8000

0x1400 1000

0x1400 0000

4 KB MTB registers

6

reserved

5

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

4

reserved

switch matrix

self wake-up timer

MRT

3

0x1001 2000

0x1000 1000

0x1000 0000

4 KB SRAM1

4 KB SRAM0

2

1

0

0x4000 4000

0x4000 0000

WWDT

reserved

0x0000 8000

0x0000 0000

0x0000 00C0

active interrupt vectors

32 KB on-chip flash

0x0000 0000

0 GB

aaa-015072

Fig 6. LPC82x Memory mapping

8.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight

coupling to the CPU allows for low interrupt latency and efficient processing of late arriving

interrupts.

8.6.1 Features

• Nested Vectored Interrupt Controller is a part of the ARM Cortex-M0+.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

13 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• Supports 32 vectored interrupts.

• In the LPC82x, the NVIC supports vectored interrupts for each of the peripherals and

the eight pin interrupts.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation using the ARM exceptions SVCall and PendSV.

• Supports NMI.

8.6.2 Interrupt sources

Each peripheral device has at least one interrupt line connected to the NVIC but can have

several interrupt flags. Individual interrupt flags can also represent more than one interrupt

source.

8.7 System tick timer

The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to

generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).

8.8 I/O configuration

The IOCON block controls the configuration of the I/O pins. Each digital or mixed

digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10

and PIO0_11) in Table 3 can be configured as follows:

• Enable or disable the weak internal pull-up and pull-down resistors.

• Select a pseudo open-drain mode. The input cannot be pulled up above V_DD. The

pins are not 5 V tolerant when V_DDis grounded.

• Program the input glitch filter with different filter constants using one of the IOCON

divided clock signals (IOCONCLKCDIV, see Figure 9 “LPC82x clock generation”).

You can also bypass the glitch filter.

• Invert the input signal.

• Hysteresis can be enabled or disabled.

• For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard

digital operation, for I2C standard and fast modes, or for I2C Fast mode+.

• The switch matrix setting enables the analog input mode on pins with analog and

digital functions. Enabling the analog mode disconnects the digital functionality.

Remark: The functionality of each I/O pin is flexible and is determined entirely through the

switch matrix. See Section 8.9 for details.

8.8.1 Standard I/O pad configuration

Figure 7 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver with configurable open-drain output.

• Digital input: Weak pull-up resistor (PMOS device) enabled/disabled.

• Digital input: Weak pull-down resistor (NMOS device) enabled/disabled.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

14 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• Digital input: Repeater mode enabled/disabled.

• Digital input: Programmable input digital filter selectable on all pins.

• Analog input: Selected through the switch matrix.

V

DD

open-drain enable

output enable

strong

pull-up

ESD

data output

pin configured

as digital output

driver

strong

pull-down

ESD

V

SS

V

DD

weak

pull-up

pull-up enable

weak

pull-down

repeater mode

enable

pull-down enable

data input

PROGRAMMABLE

DIGITAL FILTER

pin configured

as digital input

select data

inverter

SWM PINENABLE for

analog input

pin configured

as analog input

aaa-014392

Fig 7. Standard I/O pad configuration

8.9 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a

highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and

I2C functions to any pin that is not power or ground. These functions are called movable

functions and are listed in Table 4.

Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can

be enabled or disabled through the switch matrix. These functions are called fixed-pin

functions and cannot move to other pins. The fixed-pin functions are listed in Table 3. If a

fixed-pin function is disabled, any other movable function can be assigned to this pin.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

15 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.10 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC82x use accelerated GPIO functions:

• GPIO registers are on the ARM Cortex-M0+ IO bus for fastest possible single-cycle

I/O timing, allowing GPIO toggling with rates of up to 15 MHz.

• An entire port value can be written in one instruction.

• Mask, set, and clear operations are supported for the entire port.

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be

moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and

RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

8.10.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to GPIO inputs with internal pull-up resistors enabled after reset -

except for the I²C-bus true open-drain pins PIO0_10 and PIO0_11.

• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 7).

• Direction (input/output) can be set and cleared individually.

• Pin direction bits can be toggled.

8.11 Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC.

The pattern match engine can be used, with software, to create complex state machines

based on pin inputs.

Any digital pin, independently of the function selected through the switch matrix, can be

configured through the SYSCON block as input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are on the IO+

bus for fast single-cycle access.

8.11.1 Features

• Pin interrupts

– Up to eight pins can be selected from all digital pins as edge- or level-sensitive

interrupt requests. Each request creates a separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH- or LOW-active.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

16 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

– Pin interrupts can wake up the LPC82x from sleep mode, deep-sleep mode, and

power-down mode.

• Pin interrupt pattern match engine

– Up to eight pins can be selected from all digital pins to contribute to a boolean

expression. The boolean expression consists of specified levels and/or transitions

on various combinations of these pins.

– Each minterm (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can be also programmed to generate an RXEV

notification to the ARM CPU. The RXEV signal can be connected to a pin.

– The pattern match engine does not facilitate wake-up.

8.12 DMA controller

The DMA controller can access all memories and the USART, SPI, I2C, and ADC

peripherals using DMA requests or triggers. DMA transfers can also be triggered by

internal events like the ADC interrupts, the pin interrupts (PININT0 and PININT1), the

SCTimer DMA requests, and the DMA trigger outputs.

8.12.1 Features

• 18 channels with each channel connected to peripheral request inputs.

• DMA operations can be triggered by on-chip events or by two pin interrupts. Each

DMA channel can select one trigger input from 9 sources.

• Priority is user selectable for each channel.

• Continuous priority arbitration.

• Address cache with two entries.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.

8.12.2 DMA trigger input MUX (TRIGMUX)

Each DMA trigger is connected to a programmable multiplexer which connects the trigger

input to one of multiple trigger sources. Each multiplexer supports the same trigger

sources: the ADC sequence interrupts, the SCT DMA request lines, and pin interrupts

PININT0 and PININT1, and the outputs of the DMA triggers 0 and 1 for chaining DMA

triggers.

8.13 USART0/1/2

All USART functions are movable functions and are assigned to pins through the switch

matrix.

8.13.1 Features

• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode for USART functions connected to all digital pins except the

open-drain pins.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

17 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• 7, 8, or 9 data bits and 1 or 2 stop bits

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485

possible with software address detection and transceiver direction control.)

• Parity generation and checking: odd, even, or none.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator.

• A fractional rate divider is shared among all UARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Separate data and flow control loopback modes for testing.

• Baud rate clock can also be output in asynchronous mode.

• Supported by on-chip ROM API.

8.14 SPI0/1

All SPI functions are movable functions and are assigned to pins through the switch

matrix.

8.14.1 Features

• Maximum data rates of up to 30 Mbit/s in master mode and up to 18 Mbit/s in slave

mode for SPI functions connected to all digital pins except the open-drain pins.

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data, which can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data, which allows very

versatile operation, including “any length” frames.

• One Slave Select input/output with selectable polarity and flexible usage.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

8.15 I2C-bus interface (I2C0/1/2/3)

The I²C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

18 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master.

The I2C0-bus functions are fixed-pin functions. All other I2C-bus functions for I2C1/2/3

are movable functions and can be assigned through the switch matrix to any pin.

However, only the true open-drain pins provide the electrical characteristics to support the

full I2C-bus specification (see Ref. 3).

8.15.1 Features

• I2C0 supports Fast-mode Plus with data rates of up to 1 Mbit/s in addition to standard

and fast modes on two true open-drain pins.

• True open-drain pins provide fail-safe operation: When the power to an I²C-bus

device is switched off, the SDA and SCL pins connected to the I²C0-bus are floating

and do not disturb the bus.

• I2C1/2/3 support standard and fast mode with data rates of up to 400 kbit/s.

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I²C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I²C bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

8.16 SCTimer/PWM

The state configurable timer can perform basic 16-bit and 32-bit timer/counter functions

with match outputs and external and internal capture inputs. In addition, the

SCTimer/PWM can employ up to eight different programmable states, which can change

under the control of events, to provide complex timing patterns.

The inputs to the SCT are multiplexed between movable functions from the switch matrix

and internal connections such as the ADC threshold compare interrupt, the comparator

output, and the ARM core signals ARM_TXEV and DEBUG_HALTED. The signal on each

SCT input is selected through the INPUT MUX.

All outputs of the SCT are movable functions and are assigned to pins through the switch

matrix. One SCT output can also be selected as one of the ADC conversion triggers.

8.16.1 Features

• Each SCTimer/PWM supports:

– Eight match/capture registers.

– Eight events.

– Eight states.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

19 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

– Four inputs. Each input is configurable through an input multiplexer to use one of

four external pins (connected through the switch matrix) or one of four internal

sources. The maximum input signal frequency is 25 MHz.

– Six outputs. Connected to pins through the switch matrix.

• Counter/timer features:

– Each SCTimer is configurable as two 16-bit counters or one 32-bit counter.

– Counters can be clocked by the system clock or selected input.

– Configurable as up counters or up-down counters.

– Configurable number of match and capture registers. Up to eight match and

capture registers total.

– Upon match create the following events: interrupt; stop, limit, halt the timer or

change counting direction; toggle outputs.

– Counter value can be loaded into capture register triggered by a match or

input/output toggle.

• PWM features:

– Counters can be used with match registers to toggle outputs and create

time-proportioned PWM signals.

– Up to six single-edge or dual-edge PWM outputs with independent duty cycle and

common PWM cycle length.

• Event creation features:

– The following conditions define an event: a counter match condition, an input (or

output) condition such as a rising or falling edge or level, a combination of match

and/or input/output condition.

– Selected events can limit, halt, start, or stop a counter or change its direction.

– Events trigger state changes, output toggles, interrupts, and DMA transactions.

– Match register 0 can be used as an automatic limit.

– In bidirectional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• State control features:

– A state is defined by events that can happen in the state while the counter is

running.

– A state changes into another state as a result of an event.

– Each event can be assigned to one or more states.

– State variable allows sequencing across multiple counter cycles.

• One SCTimer match output can be selected as ADC hardware trigger input.

8.16.2 SCTimer/PWM input MUX (INPUT MUX)

Each input of the SCTimer/PWM is connected to a programmable multiplexer which

allows to connect one of multiple internal or external sources to the input. The available

sources are the same for each SCTimer/PWM input and can be selected from four pins

configured through the switch matrix, the ADC threshold compare interrupt, the

comparator output, and the ARM core signals ARM_TXEV and DEBUG_HALTED.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

20 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.17 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

8.17.1 Features

• 31-bit interrupt timer

• Four channels independently counting down from individually set values

• Bus stall, repeat and one-shot interrupt modes

8.18 Windowed WatchDog Timer (WWDT)

The watchdog timer resets the controller if software fails to service the watchdog timer

periodically within a programmable time window.

8.18.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2²⁴ 4) in

multiples of T_cy(WDCLK) 4.

• The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator

(WDOSC).

8.19 Self-Wake-up Timer (WKT)

The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to

this timer automatically enables the counter and launches a count-down sequence. When

the counter is used as a wake-up timer, this write can occur prior to entering a reduced

power mode.

8.19.1 Features

• 32-bit loadable down counter. Counter starts automatically when a count value is

loaded. Time-out generates an interrupt/wake up request.

• The WKT resides in a separate, always-on power domain.

• The WKT supports three clock sources: an external clock on the WKTCLKIN pin, the

low-power oscillator, and the IRC. The low-power oscillator is located in the always-on

power domain, so it can be used as the clock source in Deep power-down mode.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

21 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• The WKT can be used for waking up the part from any reduced power mode,

including Deep power-down mode, or for general-purpose timing.

8.20 Analog comparator (ACMP)

The analog comparator with selectable hysteresis can compare voltage levels on external

pins and internal voltages.

After power-up and after switching the input channels of the comparator, the output of the

voltage ladder must be allowed to settle to its stable value before it can be used as a

comparator reference input. Settling times are given in Table 25.

The analog comparator output is a movable function and is assigned to a pin through the

switch matrix. The comparator inputs and the voltage reference are enabled through the

switch matrix.

COMPARATOR ANALOG BLOCK

COMPARATOR DIGITAL BLOCK

V

DD

VDDCMP

4

32

comparator

level ACMP_O,

ADC trigger

sync

edge detect

comparator

edge NVIC

ADC_0

internal

voltage

reference

4

ACMP_I[4:1]

aaa-012135

Fig 8. Comparator block diagram

8.20.1 Features

• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input

hysteresis.

• Two selectable external voltages (V_DDor VDDCMP on pin PIO0_6); fully configurable

on either positive or negative input channel.

• Internal voltage reference from band gap selectable on either positive or negative

input channel.

• 32-stage voltage ladder with the internal reference voltage selectable on either the

positive or the negative input channel.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

22 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V

supply voltage rail.

• Voltage ladder can be separately powered down for applications only requiring the

comparator function.

• Interrupt output is connected to NVIC.

• Comparator level output is connected to output pin ACMP_O.

• One comparator output is internally collected to the ADC trigger input multiplexer.

8.21 Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12 bit and fast conversion rates of up to

1.2 MSamples/s. Sequences of analog-to-digital conversions can be triggered by multiple

sources. Possible trigger sources are the pin triggers, the SCT output SCT_OUT3, the

analog comparator output, and the ARM TXEV.

The ADC includes a hardware threshold compare function with zero-crossing detection.

Remark: For best performance, select VREFP and VREFN at the same voltage levels as

V

_DDand V_SS. When selecting VREFP and VREFN different from VDD and VSS, ensure

that the voltage midpoints are the same:

(VREFP-VREFN)/2 + VREFN = V_DD/2

8.21.1 Features

• 12-bit successive approximation analog to digital converter.

• 12-bit conversion rate of up to 1.2 MSamples/s.

• Two configurable conversion sequences with independent triggers.

• Optional automatic high/low threshold comparison and zero-crossing detection.

• Power-down mode and low-power operating mode.

• Measurement range VREFN to VREFP (not to exceed V_DDvoltage level).

• Burst conversion mode for single or multiple inputs.

• Hardware calibration mode.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

23 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.22 Clocking and power control

SYSCON

AHB clock 0

(core, system;

main clock

system clock

always-on)

CLOCK DIVIDER

SYSAHBCLKDIV

29

memories

and peripherals,

peripheral clocks

SYSAHBCLKCTRL[1:29]

(system clock enable)

USART0

USART1

USART2

FRACTIONAL RATE

GENERATOR

CLOCK DIVIDER

UARTCLKDIV

IRC oscillator

7

IOCON

glitch filter

CLOCK DIVIDER

IOCONCLKDIV

watchdog oscillator

MAINCLKSEL

(main clock select)

IRC oscillator

system oscillator

watchdog oscillator

CLOCK DIVIDER

CLKOUTDIV

CLKOUT pin

XTALIN

XTALOUT

SYSTEM

OSCILLATOR

SYSTEM PLL

CLKIN

CLKOUTSEL

(CLKOUT clock select)

SYSPLLCLKSEL

system PLL clock select

WWDT

WKT

watchdog oscillator

IRC oscillator

PMU

WKT

low-power oscillator

aaa-012136

Fig 9. LPC82x clock generation

8.22.1 Crystal and internal oscillators

The LPC82x include four independent oscillators:

1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz.

2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz.

3. The internal low-power, low-frequency Oscillator with a nominal frequency of 10 kHz

with 40% accuracy for use with the self-wake-up timer.

4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal

frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

24 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Each oscillator, except the low-frequency oscillator, can be used for more than one

purpose as required in a particular application.

Following reset, the LPC82x operates from the IRC until switched by software allowing the

part to run without any external crystal and the bootloader code to operate at a known

frequency.

See Figure 9 for an overview of the LPC82x clock generation.

8.22.1.1 Internal RC Oscillator (IRC)

The IRC may be used as the clock source for the WWDT, and/or as the clock that drives

the PLL and then the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to

1.5 % accuracy over the entire voltage and temperature range.

The IRC can be used as a clock source for the CPU with or without using the PLL. The

IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating

frequency, by the system PLL.

Upon power-up or any chip reset, the LPC82x use the IRC as the clock source. Software

may later switch to one of the other available clock sources.

8.22.1.2 Crystal Oscillator (SysOsc)

The crystal oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted

to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

8.22.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc)

The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz.

The frequency spread over silicon process variations is  40%.

The WDOsc is a dedicated oscillator for the windowed WWDT.

The internal low-power 10 kHz ( 40% accuracy) oscillator serves as the clock input to the

WKT. This oscillator can be configured to run in all low-power modes.

8.22.2 Clock input

An external clock source can be supplied on the selected CLKIN pin directly to the PLL

input. When selecting a clock signal for the CLKIN pin, follow the specifications for digital

I/O pins in Table 8 “Static characteristics, supply pins” and Table 16 “Dynamic

characteristics: I/O pins^[1]”.

An 1.8 V external clock source can be supplied on the XTALIN pins to the system

oscillator limiting the voltage of this signal (see Section 14.1).

The maximum frequency for both clock signals is 25 MHz.

8.22.3 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

25 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is nominally 100 s.

8.22.4 Clock output

The LPC82x features a clock output function that routes the IRC, the SysOsc, the

watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can

be connected to any digital pin through the switch matrix.

8.22.5 Wake-up process

The LPC82x begin operation at power-up by using the IRC as the clock source allowing

chip operation to resume quickly. If the SysOsc, the external clock source, or the PLL are

needed by the application, software must enable these features and wait for them to

stabilize before they are used as a clock source.

8.22.6 Power control

The LPC82x supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also be

controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering

the CPU clock divider value. This allows a trade-off of power versus processing speed

based on application requirements. In addition, a register is provided for shutting down the

clocks to individual on-chip peripherals, allowing to fine-tune power consumption by

eliminating all dynamic power use in any peripherals that are not required for the

application. Selected peripherals have their own clock divider which provides even better

power control.

8.22.6.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile API. The API is accessible through the on-chip

ROM.

The power configuration routine configures the LPC82x for one of the following power

modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

8.22.6.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

26 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

8.22.6.3 Deep-sleep mode

In Deep-sleep mode, the LPC82x core is in Sleep mode and all peripheral clocks and all

clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if

selected. The IRC output is disabled. In addition, all analog blocks are shut down and the

flash is in standby mode. In Deep-sleep mode, the application can keep the watchdog

oscillator and the BOD circuit running for self-timed wake-up and BOD protection.

The LPC82x can wake up from Deep-sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave mode).

Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Deep-sleep mode saves power and allows for short wake-up times.

8.22.6.4 Power-down mode

In Power-down mode, the LPC82x is in Sleep mode and all peripheral clocks and all clock

sources are off except for watchdog oscillator or low-power oscillator if selected. In

addition, all analog blocks and the flash are shut down. In Power-down mode, the

application can keep the watchdog oscillator and the BOD circuit running for self-timed

wake-up and BOD protection.

The LPC82x can wake up from Power-down mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave mode).

Any interrupt used for waking up from Power-down mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Power-down mode reduces power consumption compared to Deep-sleep mode at the

expense of longer wake-up times.

8.22.6.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

pin and the self-wake-up timer if enabled. Four general-purpose registers are available to

store information during Deep power-down mode. The LPC82x can wake up from Deep

power-down mode via the WAKEUP pin, or without an external signal by using the

time-out of the self-wake-up timer (see Section 8.19).

The LPC82x can be prevented from entering Deep power-down mode by setting a lock bit

in the PMU block. Locking out Deep power-down mode enables the application to keep

the watchdog timer or the BOD running at all times.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

27 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in

Deep power-down mode.

8.23 System control

8.23.1 Reset

Reset has four sources on the LPC82x: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

In Deep power-down mode, an external pull-up resistor is required on the RESET pin.

V

DD

V

DD

V

DD

R

pu

ESD

20 ns RC

GLITCH FILTER

reset

ESD

V

SS

aaa-004613

Fig 10. Reset pad configuration

8.23.2 Brownout detection

The LPC82x includes up to four levels for monitoring the voltage on the V_DDpin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a

dedicated status register. Four threshold levels can be selected to cause a forced reset of

the chip.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

28 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.23.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For

details, see the LPC82x user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using the

ISP entry pin as well. If necessary, the application must provide a flash update

mechanism using IAP calls or using a call to the reinvoke ISP command to enable

flash update via the USART.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can

be disabled. For details, see the LPC82x user manual.

8.23.4 APB interface

The APB peripherals are located on one APB bus.

8.23.5 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the

main static RAM, the CRC, the DMA, the ROM, and the APB peripherals.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

29 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.24 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is

configured to support up to four breakpoints and two watch points.

The Micro Trace Buffer is implemented on the LPC82x.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC82x is

in reset. The JTAG boundary scan pins are selected by hardware when the part is in

boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 3).

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

V

DD

3.3 V

LPC82x

~10 kΩ -

100 kΩ

VTREF

SWDIO

SWCLK

nRESET

GND

SWDIO

SWCLK

from SWD

connector

RESET

~10 kΩ -

100 kΩ

DGND

PIO0_12

ISP entry

aaa-015075

Fig 11. Connecting the SWD pins to a standard SWD connector

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

30 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

9. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol Parameter

Conditions

Min

Max

Unit

[2]

V_DD

supply voltage (core and external

0.5

+4.6

V

rail)

V_ref

V_I

reference voltage

input voltage

on pin VREFP

0.5

V_DD

V

[3][4]

[5]

5 V tolerant I/O pins; V_DD

1.8 V



+5.5

on I2C open-drain pins

PIO0_10, PIO0_11

0.5

+5.5

V

[6]

3 V tolerant I/O pin PIO0_6

0.5

+3.6

+4.6

V

[7][8]

[9]

V_IA

analog input voltage

[2]

V_i(xtal)

I_DD

crystal input voltage

supply current

0.5

+2.5

100

V

per supply pin

-

mA

I_SS

ground current

per ground pin

I_latch

I/O latch-up current

(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 C

[10]

[11]

T_stg

storage temperature

65

+150

150

1.5

C

W

T_j(max)

maximum junction temperature

-

P_tot(pack)total power dissipation (per

package)

based on package heat

transfer, not device power

consumption

V_esd

electrostatic discharge voltage

human body model; all pins

-

3500

1200

V

charged device model;

HVQFN33 package

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 7) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_10 and PIO0_11 and except the 3 V tolerant pin PIO0_6.

[4] Including the voltage on outputs in 3-state mode.

[5] V_DDpresent or not present. Compliant with the I²C-bus standard. 5.5 V can be applied to this pin when V_DDis powered down.

[6] V_DDpresent or not present.

[7] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 10⁶s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[8] If the comparator is configured with the common mode input V_IC= V_DD, the other comparator input can be up to 0.2 V above or below

V_DDwithout affecting the hysteresis range of the comparator function.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

31 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

10. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T _j= T_amb+ P_D R_{th j – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 6.

Symbol

Thermal resistance

Parameter

Conditions

Max/min

Unit

HVQFN33 package

R_th(j-a)thermal resistance from

JEDEC (4.5 in  4 in); still air 40 +/- 15 % C/W

junction-to-ambient

single-layer (4.5 in  3 in); still 114 +/- 15 % C/W

air

R_th(j-c)

thermal resistance from

junction-to-case

18 +/- 15 % C/W

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

32 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11. Static characteristics

11.1 General operating conditions

Table 7.

General operating conditions

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

f_clk

Parameter

Conditions

Min

-

Typ^[1]

-

Max

30

Unit

MHz

V

clock frequency

internal CPU/system clock

V_DD

supply voltage (core

and external rail)

1.8

3.3

3.6

V_ref

reference voltage

on pin VREFP

2.4

-

V_DD

V

Oscillator pins

V_i(xtal)

crystal input voltage

crystal output voltage

on pin XTALIN

0.5

1.8

1.95

V

V_o(xtal)

on pin XTALOUT

Pin capacitance

C_ioinput/output

capacitance

[2]

pins with analog and digital

functions

I²C-bus pins (PIO0_10 and

PIO0_11)

-

7.1

2.5

2.8

pF

pins with digital functions only

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] Including bonding pad capacitance. Based on simulation, not tested in production.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

33 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.2 Supply pins

Table 8.

Static characteristics, supply pins

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_DD

supply current

Active mode; code

while(1){}

executed from flash;

[2][3][4]

[6][7]

system clock = 12 MHz; default

mode; V_DD= 3.3 V

-

1.85

1.04

3.95

3.2

-

mA

[2][3][4]

[6][7]

system clock = 12 MHz;

low-current mode; V_DD= 3.3 V

[2][3][6]

[7][9]

system clock = 30 MHz; default

mode; V_DD= 3.3 V

[2][3][6]

[7][9]

system clock = 30 MHz;

low-current mode; V_DD= 3.3 V

Sleep mode

[2][3][4]

[6][7]

system clock = 12 MHz; default

mode; V_DD= 3.3 V

-

1.35

0.8

-

mA

[2][3][4]

[6][7]

system clock = 12 MHz;

low-current mode; V_DD= 3.3 V

[2][3][9]

[6][7]

system clock = 30 MHz; default

mode; V_DD= 3.3 V

2.55

2.1

[2][3][9]

[6][7]

system clock = 30 MHz;

low-current mode; V_DD= 3.3 V

[2][3][10]

[2][11]

I_DD

supply current

Deep-sleep mode;

_DD= 3.3 V;

V

T_amb= 25 C

T_amb= 105 C

158

-

300

400

A

-

Power-down mode;

_DD= 3.3 V

V

T_amb= 25 C

T_amb= 105 C

1.6

-

10

50

A

-

Deep power-down mode; V_DD

=

3.3 V; 10 kHz low-power oscillator

and self-wake-up timer (WKT)

disabled

T

_amb= 25 C

-

0.2

-

1

4

A

T_amb= 105 C

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

34 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 8.

Static characteristics, supply pins …continued

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_DD

supply current

Deep power-down mode; V_DD

=

-

1.1

-

A

3.3 V; 10 kHz low-power oscillator

and self-wake-up timer (WKT)

enabled

Deep power-down mode; V_DD

3.3 V; external clock input

WKTCLKIN @ 10 kHz with

self-wake-up timer enabled

=

-

0.4

0.7

-

A

Deep power-down mode; V_DD

3.3 V; external clock input

WKTCLKIN @ 32 kHz with

self-wake-up timer enabled

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] T_amb= 25 C.

[3] I_DDmeasurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; system oscillator disabled; system PLL disabled.

[5] System oscillator enabled; IRC disabled; system PLL disabled.

[6] BOD disabled.

[7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system

configuration block.

[8] IRC enabled; system oscillator disabled; system PLL enabled.

[9] IRC disabled; system oscillator enabled; system PLL enabled.

[10] All oscillators and analog blocks turned off.

[11] WAKEUP pin pulled HIGH externally.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

35 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.3 Electrical pin characteristics

Table 9.

Static characteristics, electrical pin characteristics

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol Parameter Conditions

Standard port pins configured as digital pins, RESET

Min

Typ^[1]

Max

Unit

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

-

0.5

-

10^[2]

5

nA

V

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD; on-chip pull-down resistor

disabled

-

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

-

[4]

[6]

input voltage

V_DD 1.8 V; 5 V tolerant pins

0

except PIO0_6

V_DD= 0 V

0

-

3.6

V_DD

-

V

V_O

output voltage

output active

0

V_IH

HIGH-level input

voltage

0.7V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

V_OH

0.4

-

V

HIGH-level output

voltage

I_OH= 4 mA; 2.5 V <= V_DD<= 3.6 V

I_OH= 3 mA; 1.8 V <= V_DD< 2.5 V

I_OL= 4 mA; 2.5 V <= V_DD<= 3.6 V

I_OL= 3 mA; 1.8 V <= V_DD< 2.5 V

V_OH= V_DD 0.4 V;

V_DD 0.4 -

-

V

-

V

V_OL

LOW-level output

voltage

-

0.4

-

V

-

V

I_OH

HIGH-level output

current

4

mA

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

4

-

mA

I_OL

LOW-level output

current

V_OL= 0.4 V

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

-

mA

[7]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

45

LOW-level short-circuit V_OL= V_DD

output current

-

50

mA

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

V_I= 0 V;

10

50

150

A

2.0 V  V_DD 3.6 V

15

10

0

50

0

85

0

A

1.8 V  V_DD< 2.0 V

V_DD< V_I< 5 V

High-drive output pin configured as digital pin (PIO0_2, PIO0_3, PIO0_12, PIO0_16)

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

-

0.5

10^[2]

nA

I_IH

I_OZ

HIGH-level input

current

V_I= V_DD; on-chip pull-down resistor

disabled

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

36 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 9.

Static characteristics, electrical pin characteristics …continued

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[4]

[6]

V_I

input voltage

V_DD 1.8 V

0

-

5.0

V

V_DD= 0 V

0

-

3.6

V_DD

-

V

V_O

output voltage

output active

0

V_IH

HIGH-level input

voltage

0.7V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

V_OH

0.4

-

HIGH-level output

voltage

I_OH= 20 mA; 2.5 V <= V_DD< 3.6 V

I_OH= 12 mA; 1.8 V <= V_DD< 2.5 V

I_OL= 4 mA

V_DD 0.4 -

-

V_OL

I_OH

LOW-level output

voltage

-

0.4

HIGH-level output

current

V_OH= V_DD 0.4 V;

2.5 V <= V_DD< 3.6 V

20

12

4

-

mA

V_OH= V_DD 0.4 V;

1.8 V <= V_DD< 2.5 V

I_OL

LOW-level output

current

V_OL= 0.4 V

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

-

mA

[7]

I_OLS

LOW-level short-circuit V_OL= V_DD

output current

50

[8]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

10

0

50

50

0

150

85

0

A

V_I= 0 V

V_DD< V_I< 5 V

I²C-bus pins (PIO0_10 and PIO0_11)

V_IH

HIGH-level input

voltage

0.7V_DD

-

V

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

-

V

V_hys

I_OL

0.05V_DD

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as standard mode pins

2.5 V <= V_DD< 3.6 V

3.5

3

-

mA

1.8 V <= V_DD< 2.5 V

I_OL

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as Fast-mode Plus pins;

2.5 V <= V_DD< 3.6 V

1.8 V <= V_DD< 2.5 V

V_I= V_DD

20

16

-

mA

A

-

[9]

I_LI

input leakage current

2

10

4

22

V_I= 5 V

-

A

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] Based on characterization. Not tested in production.

[3] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[4] Including voltage on outputs in 3-state mode.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

37 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

[5] V_DDsupply voltage must be present.

[6] 3-state outputs go into 3-state mode in Deep power-down mode.

[7] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[8] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 12.

[9] To V_SS

.

V

DD

I

OL

pd

+

-

pin PIO0_n

A

I

OH

Ipu

-

+

A

aaa-010819

Fig 12. Pin input/output current measurement

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

38 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.4 Power consumption

Power measurements in Active, Sleep, Deep-sleep, and Power-down modes were

performed under the following conditions:

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

• Configure GPIO pins as outputs using the GPIO DIR register.

• Write 1 to the GPIO CLR register to drive the outputs LOW.

aaa-013992

4

30 MHz

I

DD

24 MHz

12 MHz

6 MHz

4 MHz

3 MHz

2 MHz

1 MHz

(mA)

3

2

1

0

1.8

2.4

3

3.6

V

(V)

DD

Conditions: T_amb= 25 C; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: external clock; IRC, PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: system oscillator enabled; PLL enabled.

Fig 13. Active mode: Typical supply current I_DDversus supply voltage V_DD

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

39 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-013993

4

3

2

1

0

30 MHz

24 MHz

12 MHz

6 MHz

4 MHz

3 MHz

2 MHz

1 MHz

I

DD

(mA)

-40

-10

20

50

80

110

temperature (°C)

Conditions: V_DD= 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: external clock; IRC, PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: system oscillator enabled; PLL enabled.

Fig 14. Active mode: Typical supply current I_DDversus temperature

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

40 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-013994

2.5

30 MHz

24 MHz

12 MHz

6 MHz

4 MHz

3 MHz

2 MHz

1 MHz

I

DD

(mA)

2

1.5

1

0.5

0

-40

10

60

110

temperature (°C)

Conditions: V_DD= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: external clock; IRC, PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: system oscillator enabled; PLL enabled.

Fig 15. Sleep mode: Typical supply current I_DDversus temperature for different system

clock frequencies

aaa-013983

180

DD

(μuAA))

170

V3.6 V= 3.6 V

DD

I

3.3 VV

2.7 VV

2 V

1.8 VV

160

150

140

130

120

-40

-10

20

50

80

temperature (°C)

110

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 16. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

41 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-013984

25

20

15

10

5

I

DD

(μA)

VDD==33..66VV

DD

3.3 VV

1.8 VV

0

-40

-10

20

50

80

110

temperature (°C)

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 17. Power-down mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

aaa-013985

2

I

DD

(μuAA))

1.5

1

V

= 3.63.V6

3.33.V3

2.72.V7

1.81.V8

DD

0.5

0

-40

-10

20

50

80

110

temperature (°C)

WKT not running.

Fig 18. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

42 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-013991

3

2.5

2

I

DD

(μA)

V

= 3.6 V

3.6

DD

3.3 V

2.4 V

1.8 V

1.5

1

0.5

0

-40

-10

20

50

80

temperature (°C)

110

WKT running with internal 10 kHz low-power oscillator.

Fig 19. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD(internal clock)

aaa-014386

2

I

DD

(μA)

VDD==33..66VV

DD

1.5

1

3.3 VV

2.7 VV

1.8 VV

0.5

0

-40

-10

20

50

80

110

temperature (°C)

WKT running with external 10 kHz clock. Clock input waveform: square wave with rise time and fall

time of 5 ns.

Fig 20. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD(external 10 kHz input clock)

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

43 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-014388

3

2.5

2

I

DD

(μA)

VDD==33..66VV

DD

3.3 VV

2.7 VV

1.8 VV

1.5

1

0.5

0

-40

-10

20

50

80

110

temperature (°C)

WKT running with external 32 kHz clock. Clock input waveform: square wave with rise time and fall

time of 5 ns.

Fig 21. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD(external 32 kHz input clock)

aaa-014389

25

I

DD

(μA)

20

15

10

5

VDD = 33..66 VV

3.3 VV

2.7 VV

1.8 VV

20

0

-40

-10

50

80

110

temperature (°C)

WKT running with external 1 MHz clock. Clock input waveform: square wave with rise time and fall

time of 5 ns.

Fig 22. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD(external 1 MHz input clock)

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

44 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.5 CoreMark data

aaa-014006

2.5

coremark score

((iterations/s)/MHz)

CPU/epfeffiirccfoiieernnmccayynce/efficiency

2

1.5

1

default

low-current

0.5

0

6

12

18

24

30

system clock frequency (MHz)

Conditions: V_DD= 3.3 V; T_amb= 25 °C; active mode; all peripherals except one UART and the SCT

disabled in the SYSAHBCLKCTRL register; BOD disabled; internal pull-up resistors enabled.

Measured with Keil uVision 5.10.

1 MHz - 6 MHz: external clock; IRC, PLL disabled.12 MHz: IRC enabled; PLL disabled. 24 MHz:

IRC enabled; PLL enabled.30 MHz: system oscillator enabled; PLL enabled.

Fig 23. CoreMark score

aaa-014007

8

6

4

2

0

I

DD

(mA)

default

CPU//peefffiirccfoiieernnmccayynce/efficiency

low-current

0

6

12

18

24

30

system clock frequency (MHz)

Conditions: V_DD= 3.3 V; T_amb= 25 °C; active mode; all peripherals except one UART and the SCT

disabled in the SYSAHBCLKCTRL register; BOD disabled; internal pull-up resistors enabled.

Measured with Keil uVision 5.10.

1 MHz - 6 MHz: external clock; IRC, PLL disabled.12 MHz: IRC enabled; PLL disabled.24 MHz:

IRC enabled; PLL enabled.30 MHz: system oscillator enabled; PLL enabled.

Fig 24. Active mode: CoreMark power consumption I_DD

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

45 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.6 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG.

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code accessing the peripheral is executed. Measured on a typical

sample at T_amb= 25 C. Unless noted otherwise, the system oscillator and PLL are

running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz.

Table 10. Power consumption for individual analog and digital blocks

Peripheral

Typical supply current in μA

Notes

System clock frequency =

n/a

12 MHz

30 MHz

IRC

261

-

System oscillator running; PLL off;

independent of main clock frequency; IRC

output disabled.

System oscillator at 12 MHz

Watchdog oscillator

274

2

-

IRC running; PLL off; independent of main

clock frequency.

System oscillator running; PLL off;

independent of main clock frequency.

BOD

39

-

Independent of main clock frequency.

-

Main PLL

CLKOUT

301

67

-

150

Main clock divided by 4 in the CLKOUTDIV

register.

ROM

-

27

95

68

-

GPIO + pin interrupt/pattern

match

233

GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

register.

SWM

-

59

45

168

89

29

54

49

52

57

55

50

54

56

34

145

110

411

220

71

-

IOCON

SCTimer/PWM

MRT

WWDT

I2C0

132

122

127

142

136

124

134

138

82

I2C1

I2C2

I2C3

SPI0

SPI1

USART0

USART1

USART2

Comparator ACMP

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

46 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 10. Power consumption for individual analog and digital blocks …continued

Peripheral

Typical supply current in μA

Notes

System clock frequency =

n/a

12 MHz

30 MHz

ADC

-

57

141

Digital controller only. Analog portion of the

ADC disabled in the PDRUNCFG register.

-

57

141

Combined analog and digital logic. ADC

enabled in the PDRUNCFG register and

LPWRMODE bit set to 1 in the ADC CTRL

register (ADC in low-power mode).

1990

2070

Combined analog and digital logic. ADC

enabled in the PDRUNCFG register and

LPWRMODE bit set to 0 in the ADC CTRL

register (ADC powered).

DMA

CRC

-

324

34

793

85

-

11.7 Electrical pin characteristics

aaa-013973

aaa-013974

1.8

OLH

3.5

V

OHL

(V)

V

(V)

1.7

3.2

2.9

2.6

2.3

2

-40 CC°C

25 °CC

90 °CC

105 °CC

-40 °CC

25 °CC

90 °CC

105 °CC

1.6

1.5

1.4

1.3

1.2

0

4

8

12

16

20

24

0

20

40

60

OH

80

I

(mA)

I

(mA)

OH

Conditions: V_DD= 1.8 V; on pin PIO0_12.

Conditions: V_DD= 3.3 V; on pin PIO0_12.

Fig 25. High-drive output: Typical HIGH-level output voltage V_OHversus HIGH-level output current I_OH

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

47 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-013964

aaa-013972

40

60

45

30

15

0

I

OLL

(mA)

OLL

(mA)

-40 CC°C

25 °CC

90 °CC

105 °CC

-40 °CC

25 °CC

90 °CC

105 °CC

30

20

10

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

OL

Conditions: V_DD= 1.8 V; on pins PIO0_10 and PIO0_11.

Conditions: V_DD= 3.3 V; on pins PIO0_10 and PIO0_11.

Fig 26. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus LOW-level output voltage

V_OL

aaa-013975

aaa-013976

10

8

15

12

9

I

OLL

(mA)

OLL

(mA)

-40 CC°C

25 °CC

90 °CC

105 °CC

-40 °CC

25 °CC

90 °CC

105 °CC

6

4

6

2

3

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

OL

Conditions: V_DD= 1.8 V; standard port pins and

high-drive pin PIO0_12.

Conditions: V_DD= 3.3 V; standard port pins and

high-drive pin PIO0_12.

Fig 27. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

48 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-013977

aaa-013978

1.8

OHH

3.5

-40 CC°C

25 °CC

90 °CC

105 °CC

V

(V)

V

OHH

(V)

1.7

1.6

1.5

1.4

1.3

1.2

3.2

2.9

2.6

2.3

2

-40 °CC

25 °CC

90 °CC

105 °CC

0

1.5

3

4.5

OH

6

0

8

16

24

I

(mA)

I

(mA)

OH

Conditions: V_DD= 1.8 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 28. Typical HIGH-level output voltage V_OHversus HIGH-level output source current I_OH

aaa-013979

aaa-013980

0

-4

-8

0

I

pu

(μuAA))

pu

(uμAA))

-14

-28

-42

-56

-70

-40 CC°C

105 °CC

90 °CC

25 °CC

105 °CC

-40 °CC

90 °CC

25 °CC

-12

-16

0

0.7

1.4

2.1

2.8

V (V)

3.5

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 1.8 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 29. Typical pull-up current I_PUversus input voltage V_I

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

49 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

aaa-013981

aaa-013982

35

80

60

40

20

0

I

pd

(μuAA))

puud

(uμAA))

28

21

14

7

-40 CC°C

-40 °CC

25 °CC

90 °CC

105 °CC

25 °CC

90 °CC

105 °CC

0

0.7

1.4

2.1

2.8

3.5

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 1.8 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 30. Typical pull-down current I_PDversus input voltage V_I

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

50 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12. Dynamic characteristics

12.1 Power-up ramp conditions

Table 11. Power-up characteristics

T_amb= −40 °C to +105 °C; 1.8 V ≤ V_DD≤ 3.6 V

Symbol Parameter

Conditions

Min

0

Typ

Max

500

-

Unit

ms

s

[1][3]

[1][2][3]

[3]

t_r

rise time

V_I 200 mV

-

t_wait

V_I

wait time

12

0

input voltage

at t = t₁on pin V_DD

200

mV

[1] See Figure 31.

[2] The wait time specifies the time the power supply must be at levels below 200 mV before ramping up. See

the LPC82x errata sheet.

[3] Based on characterization, not tested in production.

t

r

V

DD

200 mV

0

t

wait

t = t

1

aaa-017426

Condition: 0 < V_I 200 mV at start of power-up (t = t₁)

Fig 31. Power-up ramp

12.2 Flash/EEPROM memory

Table 12. Flash characteristics

T_amb= −40 °C to +105 °C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

N_endu

endurance

10000

100000

-

cycles

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

51 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 12. Flash characteristics

T_amb= −40 °C to +105 °C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol

Parameter

Conditions

powered

Min

10

Typ

20

Max

Unit

years

ms

t_ret

retention time

-

not powered

20

40

-

t_er

erase time

page or multiple

consecutivepages,

sector or multiple

consecutive

95

100

105

sectors

[2]

t_prog

programming

time

0.95

1

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 64 bytes to the flash. T_amb<= +85 C. Flash programming with IAP

calls (see LPC82x user manual).

12.3 External clock for the oscillator in slave mode

Remark: The input voltage on the XTALIN and XTALOUT pins must be  1.95 V (see

Table 7). For connecting the oscillator to the XTAL pins, also see Section 12.3.

Table 13. Dynamic characteristic: external clock (XTALIN input)

T_amb= −40 °C to +105 °C; V_DDover specified ranges.^[1]

Symbol

f_osc

Parameter

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk) 0.4

-

ns

T_cy(clk) 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

t

CHCX

t

CLCH

CHCL

CLCX

T

cy(clk)

aaa-004648

Fig 32. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

52 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.4 Internal oscillators

Table 14. Dynamic characteristics: IRC

T_amb= −40 °C to +105 °C; 2.7 V ≤ V_DD≤ 3.6 V^[1].

Symbol Parameter

Conditions

Min

Typ^[2]Max

12 12.18

Unit

f_osc(RC)

internal RC

-

11.82

MHz

oscillator frequency

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

aaa-014008

12.2

V3.6 V= 3.6 V

DD

3.3 VV

3 V

f

(MHz)

2.7 VV

2.4 VV

2.1 VV

2 V

12.1

1.8 VV

12

11.9

11.8

-40

-10

20

50

80

110

temperature (°C)

Conditions: Frequency values are typical values. 12 MHz  1.5 % accuracy is guaranteed for

2.7 V  V_DD 3.6 V. Variations between parts may cause the IRC to fall outside the 12 MHz 

1.5 % accuracy specification for voltages below 2.7 V.

Fig 33. Typical Internal RC oscillator frequency versus temperature

Table 15. Dynamic characteristics: Watchdog oscillator

Symbol

Parameter

Conditions

Min Typ^[1Max Unit

]

[2][3]

f_osc(int)

internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1

-

9.4

-

kHz

frequency

in the WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register

2300

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +105 C) is 40 %.

[3] See the LPC82x user manual.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

53 of 82

LPC82x

NXP Semiconductors

12.4.1 I/O pins

32-bit ARM Cortex-M0+ microcontroller

Table 16. Dynamic characteristics: I/O pins^[1]

T_amb= −40 °C to +105 °C; 3.0 V ≤ V_DD≤ 3.6 V.

Symbol Parameter Conditions

Min

3.0

2.5

Typ

Max

5.0

Unit

ns

t_r

t_f

rise time

fall time

pin configured as output

-

5.0

ns

[1] Applies to standard port pins and RESET pin.

12.4.2 WKTCLKIN pin (wake-up clock input)

Table 17. Dynamic characteristics: WKTCLKIN pin

T_amb= −40 °C to +105 °C; 1.8 V ≤ V_DD≤ 3.6 V.

Symbol Parameter

Conditions

Min Max

Unit

[1]

f_clk

clock frequency

deep power-down mode and

power-down mode

-

1

MHz

[1]

deep-sleep, sleep, and active mode

-

10

-

MHz

ns

t_CHCX

t_CLCX

clock HIGH time

clock LOW time

-

50

-

ns

[1] Assuming a square-wave input clock.

12.4.3 SCTimer/PWM output timing

Table 18. SCTimer/PWM output dynamic characteristics

T_amb= −40 °C to 105 °C; 2.4 V <= V_DD<= 3.6 V; C_L= 10 pF. Simulated skew (over process, voltage,

and temperature) of any two SCT output signals routed to standard I/O pins; sampled at the 50 %

level of the falling or rising edge; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_sk(o)

output skew time

-

4

ns

12.4.4 I²C-bus

Table 19. Dynamic characteristic: I²C-bus pins^[1]

T_amb= −40 °C to +105 °C; values guaranteed by design.^[2]

Symbol

Parameter

Conditions

Standard-mode

Fast-mode

Min

Max

Unit

f_SCL

SCL clock

frequency

0

100

400

1

kHz

MHz

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

[4][5][6][7]

t_f

fall time

of both SDA and

SCL signals

-

300

ns

Standard-mode

Fast-mode

20 + 0.1  C_b300

120

ns

Fast-mode Plus;

on pins PIO0_10

and PIO0_11

-

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

54 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 19. Dynamic characteristic: I²C-bus pins^[1]

T_amb= −40 °C to +105 °C; values guaranteed by design.^[2]

Symbol

Parameter

Conditions

Standard-mode

Fast-mode

Min

4.7

1.3

Max

Unit

s

t_LOW

LOW period of

the SCL clock

-

s

Fast-mode Plus; on 0.5

pins PIO0_10 and

PIO0_11

s

t_HIGH

HIGH period of

the SCL clock

Standard-mode

Fast-mode

4.0

0.6

-

s

Fast-mode Plus; on 0.26

pins PIO0_10 and

PIO0_11

[3][4][8]

t_HD;DAT

data hold time

Standard-mode

Fast-mode

0

-

s

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

[9][10]

t_SU;DAT

data set-up

time

Standard-mode

Fast-mode

250

100

-

ns

Fast-mode Plus; on 50

pins PIO0_10 and

PIO0_11

[1] See the I²C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] t_HD;DATis the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

V_IH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF.

[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage t_fis specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of t_VD;DATor t_VD;ACKby a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (t_LOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] t_SU;DATis the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement

t_SU;DAT= 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

55 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

t

f

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

aaa-004643

Fig 34. I²C-bus pins clock timing

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

56 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.4.5 SPI interfaces

In master mode, the maximum supported bit rate is limited by the maximum system clock

to 30 Mbit/s. In slave mode, assuming a set-up time of 3 ns for the external device and

neglecting any PCB trace delays, the maximum supported bit rate is 1/(2 x (26 ns + 3 ns))

= 17 Mbit/s at 3.0 V <= VDD <= 3.6 V and 13 Mbit/s at 1.8 V <= VDD < 3.0 V. The actual

bit rate depends on the delays introduced by the external trace and the external device.

Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for

all digital pins except the open-drain pins PIO0_10 and PIO0_11.

Table 20. SPI dynamic characteristics

T_amb= −40 °C to 105 °C; C_L= 20 pF; input slew = 1 ns. Simulated parameters sampled at the 30 %

and 70 % level of the rising or falling edge; values guaranteed by design. Delays introduced by the

external trace or external device are not considered.

Symbol

SPI master

t_DS

Parameter

Conditions

Min

Max

Unit

data set-up time

data hold time

1.8 V <= V_DD<= 3.6 V

2

-

ns

t_DH

6

-

t_v(Q)

data output valid time 1.8 V <= V_DD<= 3.6 V

-3

4

SPI slave

t_DS

data set-up time

data hold time

1.8 V <= V_DD<= 3.6 V

2

4

0

-

ns

t_DH

-

t_v(Q)

data output valid time 3.0 V <= V_DD<= 3.6 V

1.8 V <= V_DD< 3.0 V

26

35

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

57 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

MISO (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MOSI (CPHA = 1)

MISO (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

IDLE

DATA VALID (LSB)

DATA VALID

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014969

T_cy(clk)= CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC82x User manual.

Fig 35. SPI master timing

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

58 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

MOSI (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MISO (CPHA = 1)

MOSI (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

IDLE

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014970

Fig 36. SPI slave timing

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

59 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.4.6 USART interface

The maximum USART bit rate is 10 Mbit/s in synchronous mode master mode and

10 Mbit/s in synchronous slave mode.

Remark: USART functions can be assigned to all digital pins. The characteristics are

valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11.

Table 21. USART dynamic characteristics

T_amb= −40 °C to 105 °C; 1.8 V <= V_DD<= 3.6 V unless noted otherwise; C_L= 10 pF; input slew =

10 ns. Simulated parameters sampled at the 30 %/70 % level of the falling or rising edge; values

guaranteed by design.

Symbol

Parameter

Conditions

Min

Max Unit

USART master (in synchronous mode)

t_su(D)

data input set-up time

3.0 V <= V_DD<= 3.6 V

1.8 V <= V_DD< 3.0 V

31

37

0

-

ns

t_h(D)

t_v(Q)

data input hold time

data output valid time

-

ns

0

5

USART slave (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

data input set-up time

data input hold time

data output valid time

6

2

0

-

ns

-

3.0 V <= V_DD<= 3.6 V

1.8 V <= V_DD< 3.0 V

28

37

T

cy(clk)

Un_SCLK (CLKPOL = 0)

Un_SCLK (CLKPOL = 1)

TXD

t

vQ)

v(Q)

START

BIT0

BIT1

t

su(D) h(D)

BIT1

START

BIT0

RXD

aaa-015074

In master mode, T_cy(clk)= U_PCLK/BRGVAL. See the LPC82x User manual.

Fig 37. USART timing

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

60 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

13. Characteristics of analog peripherals

13.1 BOD

Table 22. BOD static characteristics^[1]

T_amb= 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 1

assertion

-

2.25

2.40

-

V

de-assertion

interrupt level 2

assertion

-

2.54

2.68

-

V

de-assertion

interrupt level 3

assertion

-

2.85

2.95

-

V

de-assertion

reset level 1

assertion

-

2.05

2.20

-

V

de-assertion

reset level 2

assertion

-

2.34

2.49

-

V

de-assertion

reset level 3

assertion

-

2.63

2.78

-

V

de-assertion

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the

LPC82x user manual. Interrupt level 0 is reserved.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

61 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

13.2 ADC

Table 23. 12-bit ADC static characteristics

T_amb= −40 °C to +105 °C unless noted otherwise; V_DD= 2.4 V to 3.6 V; VREFP = V_DD; VREFN = V_SS

.

Symbol

V_IA

Parameter

Conditions

Min

0

Typ

Max

V_DD

0.32

Unit

V

analog input voltage

reference voltage

-

V_ref

on pin VREFP

2.4

-

V

C_ia

analog input

capacitance

pF

[2]

[3]

f_clk(ADC)

ADC clock frequency

2.7 V <= V_DD<= 3.6 V

2.4 V <= V_DD< 2.7 V

2.7 V <= V_DD<= 3.6 V

2.4 V <= V_DD< 2.7 V

T_amb= 105 °C

-

30

25

1.2

1

MHz

-

MHz

[2]

f_s

sampling frequency

-

Msamples/s

LSB

[3]

-

[5][4]

E_D

differential linearity

error

+/- 2.5

-

[6][4]

[7][4]

[8][4]

E_L(adj)

E_O

integral non-linearity

offset error

T_amb= 105 °C

-

+/- 2.5

+/- 4.5

+/- 0.5

-

LSB

%

-

V_err(fs)

Z_i

full-scale error voltage 1.2 Msamples/s; T_amb= 105 °C

input impedance f_s= 1.2 Msamples/s

-

[1][9]

[10]

0.1

M

[1] The input resistance of ADC channel 0 is higher than for all other channels. See Figure 38.

[2] In the ADC TRM register, set VRANGE = 0 (default).

[3] In the ADC TRM register, set VRANGE = 1 (default).

[4] Based on characterization. Not tested in production.

[5] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 39.

[6] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 39.

[7] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 39.

[8] The full-scale error voltage or gain error (E_G) is the difference between the straight line fitting the actual transfer curve after removing

offset error, and the straight line which fits the ideal transfer curve. See Figure 39.

[9] T_amb= 25 C; maximum sampling frequency f_s= 1.2 Msamples/s and analog input capacitance C_ia= 0.1 pF.

[10] Input impedance Z_iis inversely proportional to the sampling frequency and the total input capacity including C_iaand C_io: Z_i 1 / (f_s C_i).

See Table 7 for C_io.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

62 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

ADC

R

= 0.25 kΩ...2.5 kΩ

1

ADCn_0

C

io

R

= 5 Ω...25 Ω

sw

ADCn_[1:11]

DAC

C

DAC

C

io

C

ia

aaa-011748

Fig 38. ADC input impedance

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

63 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

offset

error

O

gain

error

E

G

4095

4094

4093

4092

4091

4090

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

VREFP - V

4096

SS

1 LSB =

002aaf436

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 39. 12-bit ADC characteristics

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

64 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

13.3 Comparator and internal voltage reference

Table 24. Internal voltage reference static and dynamic characteristics

T_amb= −40 °C to +105 °C; V_DD= 3.3 V; hysteresis disabled in the comparator CTRL register.

Symbol Parameter

Conditions

Min

Typ

-

Max

Unit

mV

V_O

output voltage T_amb= 25 C to 105C

T_amb= 25 C

860

940

904

aaa-014424

0.910

V

Oref

(m(VV))

0.905

0.900

0.895

0.890

-40

-10

20

50

80

110

temperature (°C)

V_DD= 3.3 V; characterized through bench measurements on typical samples.

Fig 40. Typical internal voltage reference output voltage

Table 25. Comparator characteristics

T_amb= −40 °C to +105 °C unless noted otherwise; V_DD= 1.8 V to 3.6 V.

Symbol Parameter

Static characteristics

Conditions

Min Typ

Max

Unit

V_ref(cmp)

comparator reference

voltage

pin PIO0_6/VDDCMP configured for

function VDDCMP

1.5

-

3.6

V

[2]

I_DD

supply current

VP > VM; T_amb= 25 °C; V_DD= 3.3 V

VM > VP; T_amb= 25 °C; V_DD= 3.3 V

-

90

-

A

V

-

60

-

V_IC

common-mode input voltage

output voltage variation

offset voltage

0

-

V_DD

DV_O

V_offset

-

V_DD

V

[2]

V_IC= 0.1 V; V_DD= 2.4 V; T_amb= 105 °C

V_IC= 1.5 V; V_DD= 2.4 V; T_amb= 105 °C

V_IC= 2.9 V; V_DD= 2.4 V; T_amb= 105 °C

+/- 4

+/- 2

+/- 4

-

mV

-

Dynamic characteristics

t_startup

start-up time

nominal process; V_DD= 3.3 V; T_amb

=

-

13

-

s

²⁵°C

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

65 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 25. Comparator characteristics …continued

T_amb= −40 °C to +105 °C unless noted otherwise; V_DD= 1.8 V to 3.6 V.

Symbol Parameter

t_PDpropagation delay

Conditions

Min Typ

Max

Unit

HIGH to LOW; V_DD= 3.0 V; T_amb

=

¹⁰⁵°C

[1][2][4]

[1][2]

V_IC= 0.1 V; 100 mV overdrive input

-

140

190

130

120

220

80

-

ns

V_IC= 0.1 V; rail-to-rail input

[1][2][4]

[1][2]

V_IC= 1.5 V; 100 mV overdrive input

V_IC= 1.5 V; rail-to-rail input

[1][2][4]

[1][2]

V_IC= 2.9 V; 100 mV overdrive input

V_IC= 2.9 V; rail-to-rail input

t_PD

propagation delay

LOW to HIGH; V_DD= 3.0 V; T_amb=

¹⁰⁵°C

[1][2][4]

[1][2]

V_IC= 0.1 V; 100 mV overdrive input

-

240

60

-

ns

V_IC= 0.1 V; rail-to-rail input

[1][2][4]

[1][2]

V_IC= 1.5 V; 100 mV overdrive input

V_IC= 1.5 V; rail-to-rail input

160

150

260

[1][2][4]

[1][2]

V_IC= 2.9 V; 100 mV overdrive input

V_IC= 2.9 V; rail-to-rail input

[3]

V_hys

R_lad

hysteresis voltage

ladder resistance

positive hysteresis; V_DD= 3.0 V;

V

_IC= 1.5 V; T_amb= 105 °C; settings:

5 mV

6

mV

10 mV

20 mV

-

11

23

-

[1][3]

negative hysteresis; V_DD= 3.0 V;

V

_IC= 1.5 V; T_amb= 105 °C; settings:

5 mV

-

10

15

27

1

-

mV

M

10 mV

20 mV

-

[1] C_L= 10 pF

[2] Characterized on typical samples, not tested in production.

[3] Input hysteresis is relative to the reference input channel and is software programmable.

[4] 100 mV overdrive corresponds to a square wave from 50 mV below the reference (V_IC) to 50 mV above the reference.

Table 26. Comparator voltage ladder dynamic characteristics

T_amb= −40 °C to +105 °C; V_DD= 1.8 V to 3.6 V.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[1]

t_s(pu)power-up settling

to 99% of voltage

ladder output value

-

17

-

s

time

t_s(sw)

switching settling

time

to 99% of voltage

ladder output value

-

18

-

s

[1] Characterized on typical samples, not tested in production.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

66 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 27. Comparator voltage ladder reference static characteristics

V_DD= 1.8 V to 3.6 V. T_amb= -40 °C to + 105°C; external or internal reference.

Symbol

Parameter

Conditions

Min

Typ^[1]Max

Unit

mV

%

[2]

E_V(O)

output voltage error

decimal code = 00

decimal code = 08

decimal code = 16

decimal code = 24

decimal code = 30

decimal code = 31

-

+/- 6

+/- 1

-

%

[1] Characterized though limited samples. Not tested in production.

[2] All peripherals except comparator, temperature sensor, and IRC turned off.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

67 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

14. Application information

14.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended to couple the input through a capacitor with C_i=

100 pF. To limit the input voltage to the specified range, choose an additional capacitor to

ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave mode, a

minimum of 200 mV(RMS) is needed.

LPC800

XTALIN

C

i

C

g

100 pF

aaa-004646

Fig 41. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled with a capacitor of 100 pF

(Figure 41), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 42 and in

Table 28 and Table 29. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C_X1and C_X2must be connected externally in case of fundamental

mode oscillation (the fundamental frequency is represented by L, C_Land R_S).

Capacitance C_Pin Figure 42 represents the parallel package capacitance and should not

be larger than 7 pF. Parameters F_OSC, C_L, R_Sand C_Pare supplied by the crystal

manufacturer (see Table 28).

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

68 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

LPC800

L

XTALIN

XTALOUT

C

R

C

P

=

L

XTAL

S

C

X2

X1

aaa-004647

Fig 42. Oscillator modes and models: oscillation mode of operation and external crystal

model used for C_X1/C_X2evaluation

Table 28. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

1 MHz to 5 MHz

10 pF

< 300 

< 200 

< 100 

< 160 

< 60 

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

20 pF

30 pF

5 MHz to 10 MHz

10 pF

20 pF

30 pF

10 MHz to 15 MHz

15 MHz to 20 MHz

10 pF

20 pF

10 pF

< 80 

Table 29. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

15 MHz to 20 MHz

10 pF

< 180 

< 100 

< 160 

< 80 

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

20 pF

20 MHz to 25 MHz

10 pF

20 pF

14.2 XTAL Printed-Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1,C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

69 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_x1and C_x2should be chosen smaller

according to the increase in parasitics of the PCB layout.

14.3 Connecting power, clocks, and debug functions

Figure 43 shows the basic board connections used to power the LPC82x, connect the

external crystal, and provide debug capabilities via the serial wire port.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

70 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

3.3 V

SWD connector

Note 4

3.3 V

~10 kΩ - 100 kΩ

SWDIO/PIO0_2

SWCLK/PIO0_3

1

2

4

3

5

7

PIO0_8/XTALIN

~10 kΩ - 100 kΩ

n.c.

6

8

C1

Note 1

n.c.

DGND

C2

PIO0_9/XTALOUT

RESET/PIO0_5

9

10

DGND

V

SS

DGND

Note 2

3.3 V

V

DD

LPC82x

0.1 μF

0.01 μF

PIO0_12

ADC_0

DGND

ISP select pin

Note 5 (ADC_1),

Note 3 (VDDCMP)

PIO0_6/ADC_1/VDDCMP

Note 5

Note 3

3.3 V

VREFP

0.1 μF

10 μF

VREFN

AGND

DGND

aaa-015073

(1) See Section 14.1 “XTAL input” for the values of C1 and C2.

(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the V_DDpin. Add one set of decoupling

capacitors to each V_DDpin.

(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and V_DDpins. The 10 μF bypass capacitor

filters the power line. Tie VREFP to V_DDif the ADC is not used. Tie VREFN to V_SSif ADC is not used.

(4) Uses the ARM 10-pin interface for SWD.

(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 4.

Fig 43. Power, clock, and debug connections

14.4 Termination of unused pins

Table 30 shows how to terminate pins that are not used in the application. In many cases,

unused pins may should be connected externally or configured correctly by software to

minimize the overall power consumption of the part.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

71 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Unused pins with GPIO function should be configured as outputs set to LOW with their

internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the

GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0

to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

Table 30. Termination of unused pins

Default Recommended termination of unused pins

state^[1]

RESET/PIO0_5

I; PU

In an application that does not use the RESET pin or its GPIO function, the

termination of this pin depends on whether Deep power-down mode is used:

• Deep power-down used: Connect an external pull-up resistor and keep pin in

default state (input, pull-up enabled) during all other power modes.

• Deep power-down not used and no external pull-up connected: can be left

unconnected if internal pull-up is disabled and pin is driven LOW and

configured as output by software.

all PIOn_m (not

open-drain)

I; PU

Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain)

VREFP

IA

-

Can be left unconnected if driven LOW and configured as GPIO output by software.

Tie to VDD.

Tie to VSS.

VREFN

-

[1] I = Input, O = Output, IA = Inactive (no pull-up/pull-down enabled), F = floating, PU = Pull-Up.

14.5 Pin states in different power modes

Table 31. Pin states in different power modes

Active

Sleep

Deep-sleep/Power- Deep power-down

down

PIOn_m pins (not As configured in the IOCON^[1]. Default: internal pull-up

I2C) enabled.

Floating.

PIO0_4, PIO0_5 As configured in the IOCON^[1].

Floating.

(open-drain

I2C-bus pins)

RESET

Reset function enabled. Default: input, internal pull-up

enabled.

Reset function disabled; floating; if the part

is in deep power-down mode, the RESET

pin needs an external pull-up to reduce

power consumption.

PIO0_16/

WAKEUP

As configured in the IOCON^[1]. WAKEUP function inactive. Wake-up function enabled; can be disabled

by software.

[1] Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes.

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

72 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

15. Package outline

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 44. Package outline SOT360-1 (TSSOP20)

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

73 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

D

B

A

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

v

w

C

A

B

C

1

e

1/2 e

b

9

16

L

17

8

e

E

h

2

1/2 e

24

1

terminal 1

index area

32

25

X

D

h

0

2.5

scale

5 mm

Dimensions (mm are the original dimensions)

(1)

Unit

A

b

c

D

E

e

L

v

w

y

1

h

1

2

max

0.05 0.30

5.1 3.75 5.1 3.75

0.5

mm nom 0.85

min

0.2

0.5 3.5 3.5

0.1 0.05 0.05 0.1

0.00 0.18

4.9 3.45 4.9 3.45

0.3

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

hvqfn33f_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

11-10-11

11-10-17

MO-220

Fig 45. Package outline (HVQFN33 5x5)

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

74 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

16. Soldering

Footprint information for reflow soldering of TSSOP20 package

SOT360-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450

sot360-1_fr

Fig 46. Reflow soldering of the TSSOP20 package

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

75 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Footprint information for reflow soldering of HVQFN33 package

Hx

Gx

see detail X

P

nSPx

Ay

By

SLy

Hy Gy

nSPy

C

D

SLx

Bx

Ax

0.60

0.30

solder land

solder paste

occupied area

detail X

Dimensions in mm

P

Ax

Ay

Bx

By

C

D

Gx

Gy

Hx

Hy

6.2

SLx

SLy

nSPx nSPy

0.5

5.95

4.25

0.85

0.27

5.25

6.2

3.75

3

11-11-15

11-11-20

Issue date

002aag766

Fig 47. Reflow soldering of the HVQFN33 package (5x5)

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

76 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

17. Abbreviations

Table 32. Abbreviations

Acronym

AHB

Description

Advanced High-performance Bus

Advanced Peripheral Bus

BrownOut Detection

APB

BOD

GPIO

PLL

General-Purpose Input/Output

Phase-Locked Loop

RC

Resistor-Capacitor

SPI

Serial Peripheral Interface

System Management Bus

Transverse ElectroMagnetic

SMBus

TEM

UART

Universal Asynchronous Receiver/Transmitter

18. References

[1] LPC82x User manual UM10800:

http://www.nxp.com/documents/user_manual/UM10800.pdf

[2] LPC82x Errata sheet:

http://www.nxp.com/documents/errata_sheet/ES_LPC82X.pdf

[3] I2C-bus specification UM10204.

[4] Technical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

77 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

19. Revision history

Table 33. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC82X v.1.4

20210319

Product data sheet

-

LPC82X v.1.3

Modifications:

Updated footnotes for Table 23.

Updated Table 9 , For Vi input voltage tolerant pin is changed to PIO0_6 instead of

PIO0_12.

Updated Table 11, Condition changed for rise time spec.

LPC82X v.1.3

Modifications:

LPC82X v.1.2

Modifications:

20180404

• Updated table note 2 of Section 12.1 “Power-up ramp conditions”.

20161003 Product data sheet LPC82X v.1.1

Product data sheet

201804004I

LPC82X v.1.2

-

• Added text to Table 4 “Movable functions (assign to pins PIO0_0 to PIO0_28 through

switch matrix)”:

–

SPI0_SSEL1 - Slave select 1 for SPI0.

SPI0_SSEL2 - Slave select 2 for SPI0.

SPI0_SSEL3 - Slave select 3 for SPI0.

• Changed the cross reference in the remark of Section 12.3 “External clock for the

oscillator in slave mode” to Table 7 “General operating conditions”.

• Updated table note section 2 in Table 5 “Limiting values” to make the reference to

Table 7 “General operating conditions”.

LPC82X v.1.1

Modifications:

20160602

Product data sheet

-

LPC82X v.1

• Updated Power, clock, and debug connections diagram. See Figure 43.

• Changed PIO0_13 to PIO0_16 in High-drive output pin configured as digital pin

(PIO0_2, PIO0_3, PIO0_12, PIO0_16). See Table 9 “Static characteristics, electrical

pin characteristics”.

• Changed the table header of Table 10 “Power consumption for individual analog and

digital blocks” from main clock to system clock.

• Added Section 12.1 “Power-up ramp conditions”.

• Removed BOD reset level 0 specifications in Table 22 “BOD static characteristics[1]”.

LPC82X v.1

20141001

Product data sheet

-

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

78 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

22. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.20.1

8.21

8.21.1

8.22

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Analog-to-Digital Converter (ADC). . . . . . . . . 23

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clocking and power control . . . . . . . . . . . . . . 24

Crystal and internal oscillators . . . . . . . . . . . . 24

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

4

4.1

5

8.22.1

8.22.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 25

8.22.1.2 Crystal Oscillator (SysOsc) . . . . . . . . . . . . . . 25

8.22.1.3 Internal Low-power Oscillator and Watchdog

Oscillator (WDOsc) . . . . . . . . . . . . . . . . . . . . 25

8.22.2

8.22.3

8.22.4

8.22.5

8.22.6

8.22.6.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 26

8.22.6.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.22.6.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27

8.22.6.4 Power-down mode . . . . . . . . . . . . . . . . . . . . . 27

8.22.6.5 Deep power-down mode . . . . . . . . . . . . . . . . 27

6

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 26

8

8.1

8.2

8.3

8.4

8.5

8.6

8.6.1

8.6.2

8.7

8.8

8.8.1

8.9

8.10

8.10.1

8.11

8.11.1

8.12

8.12.1

8.12.2

8.13

8.13.1

8.14

8.14.1

8.15

8.15.1

8.16

8.16.1

8.16.2

8.17

8.17.1

8.18

8.18.1

8.19

8.19.1

8.20

Functional description . . . . . . . . . . . . . . . . . . 12

ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . 12

On-chip flash program memory . . . . . . . . . . . 12

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 12

On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 12

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Nested Vectored Interrupt Controller (NVIC) . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 14

System tick timer . . . . . . . . . . . . . . . . . . . . . . 14

I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 14

Standard I/O pad configuration. . . . . . . . . . . . 14

Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 15

Fast General-Purpose parallel I/O (GPIO) . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pin interrupt/pattern match engine . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DMA trigger input MUX (TRIGMUX). . . . . . . . 17

USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

I2C-bus interface (I2C0/1/2/3) . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SCTimer/PWM . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SCTimer/PWM input MUX (INPUT MUX). . . . 20

Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Windowed WatchDog Timer (WWDT) . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Self-Wake-up Timer (WKT). . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Analog comparator (ACMP) . . . . . . . . . . . . . . 22

8.23

System control . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Brownout detection . . . . . . . . . . . . . . . . . . . . 28

Code security (Code Read Protection - CRP) 29

APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 29

AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Emulation and debugging . . . . . . . . . . . . . . . 30

8.23.1

8.23.2

8.23.3

8.23.4

8.23.5

8.24

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31

Thermal characteristics . . . . . . . . . . . . . . . . . 32

10

11

Static characteristics . . . . . . . . . . . . . . . . . . . 33

General operating conditions . . . . . . . . . . . . . 33

Supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electrical pin characteristics. . . . . . . . . . . . . . 36

Power consumption . . . . . . . . . . . . . . . . . . . . 39

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 45

Peripheral power consumption. . . . . . . . . . . . 46

Electrical pin characteristics. . . . . . . . . . . . . . 47

11.1

11.2

11.3

11.4

11.5

11.6

11.7

12

12.1

12.2

12.3

Dynamic characteristics. . . . . . . . . . . . . . . . . 51

Power-up ramp conditions . . . . . . . . . . . . . . . 51

Flash/EEPROM memory . . . . . . . . . . . . . . . . 51

External clock for the oscillator in slave mode 52

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 53

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

WKTCLKIN pin (wake-up clock input) . . . . . . 54

SCTimer/PWM output timing . . . . . . . . . . . . . 54

12.4

12.4.1

12.4.2

12.4.3

12.4.4

12.4.5

12.4.6

I²

C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 57

USART interface . . . . . . . . . . . . . . . . . . . . . . 60

continued >>

LPC82x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.4 — 19 March 2021

81 of 82

LPC82x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

13

Characteristics of analog peripherals . . . . . . 61

13.1

13.2

13.3

BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Comparator and internal voltage reference . . 65

14

14.1

14.2

Application information. . . . . . . . . . . . . . . . . . 68

XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

XTAL Printed-Circuit Board (PCB) layout

guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Connecting power, clocks, and debug

14.3

functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Termination of unused pins. . . . . . . . . . . . . . . 71

Pin states in different power modes . . . . . . . . 72

14.4

14.5

15

16

17

18

19

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 73

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 77

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 78

20

Legal information. . . . . . . . . . . . . . . . . . . . . . . 79

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 79

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 80

20.1

20.2

20.3

20.4

21

22

Contact information. . . . . . . . . . . . . . . . . . . . . 80

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81


型号：	LPC82X
厂家：	NXP
描述：	32-bit ARMÂ® CortexÂ®-M0 microcontroller; up to 32 kB flash and 8 kB SRAM; 12-bit ADC; comparator 静态存储器
文件：	总83页 (文件大小：2412K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC82X [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E