MC145507P [NXP]
A/MU-LAW, PCM CODEC, PDIP16, PLASTIC, DIP-16;
| 型号： | MC145507P |
| 厂家： | 
NXP |
| 描述： | A/MU-LAW, PCM CODEC, PDIP16, PLASTIC, DIP-16 PC 电信 光电二极管 电信集成电路 |
| 文件： | 总24页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145506/D
Advance Information
The MC145506, MC145507, and MC145508 are per channel codec–filter
PCM mono–circuits. These devices perform the voice digitization and
reconstruction, as well as the band limiting and smoothing required for PCM
systems. These devices have HCMOS compatible digital outputs and otherwise
supplement the MC145500 – MC145505 series of PCM codec–filters. The
MC145506, MC145507, and MC145508 are functionally similar to the
MC145502, MC145503, and MC145505, respectively. They are designed to
operate in both synchronous and asynchronous applications and contain an
on–chip precision reference voltage. The MC145506 is offered in a 22–pin
package and has the capability of selecting from three peak overload voltages
(2.5 V, 3.15 V, and 3.78 V). The MC145507 and MC145508 offer versatility and
low cost in 16–pin DIP and wide body SOIC packages. Most of the features of
these devices can be made available in a lower pin count package tailored to a
specific user’s application. Contact the factory for further details.
16
1
P SUFFIX
PLASTIC DIP
CASE 648
16
1
These devices maintain compatibility with Motorola’s family of MC3419/
MC33120 SLIC products.
The MC145500 family of PCM codec–filter mono–circuits utilize CMOS due
to its reliable low–power performance and proven capability for complex
analog/digital VLSI functions.
DW SUFFIX
SO PACKAGE
CASE 751G
MC145507/08
MC145506 (22–Pin Package, HCMOS Output Version of MC145502)
•
•
•
•
Selectable Peak Overload Voltages (2.5 V, 3.15 V, 3.78 V)
Push–Pull Analog Output with Gain Adjust
64 kHz to 4.1 MHz Transmit and/or Receive Data Clock Rate
All the Features of the MC145507 Listed Below
22
1
P SUFFIX
PLASTIC DIP
CASE 708
MC145507 (16–Pin Package, HCMOS Output Version of MC145503)
•
•
•
•
•
•
Transmit Bandpass and Receive Low–Pass Filters on Chip
Pin Selectable Mu/A Law Companding with Corresponding Data Format
On–Chip Precision Reference Voltage (3.15 V)
Power Dissipation of 50 mW, Power Down of 0.1 mW at ±5 V
Three Terminal Transmit Input Operational Amplifier
Automatic Prescaler Accepts 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz,
and 2.56 MHz for Internal Sequencing
MC145506
•
Separate Transmit and Receive Data Clocks
MC145508 (16–Pin Package, HCMOS Output Version of MC145505) Same
as MC145507 Except:
•
•
Common 64 kHz to 4.1 MHz Transmit/Receive Data Clock
Separate CCI Pin with Automatic Prescaler Accepts 128 kHz, 1.536 MHz,
1.544 MHz, 2.048 MHz, and 2.56 MHz for Internal Sequencing
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 0
2/00
Motorola, Inc. 2000
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145506/07/08 PCM CODEC–FILTER MONO–CIRCUIT BLOCK DIAGRAM
RDD
RCE
RDC
RECEIVE SHIFT
REGISTER
1
RxO
RxG
RxO
D/A
FREQUENCY
Rx
Rx
V
DD
SHARED
DAC
–
400 µA
÷ 1, 12, 16, 20
CCI
MSI
CCI PRESCALER
+
V
DD
V
SS
V
AG
2.5 V
REF
+
–
SEQUENCE
AND
V
LS
CONTROL
PDI
V
SS
V
RSI
ref
RSI
TxI
CIRCUITRY
TDD
–
–Tx
TRANSMIT SHIFT
REGISTER
A/D
TDE
TDC
+Tx
+
FREQUENCY
FREQUENCY
NOTES:
Controlled by V
.
LS
Rx ≈ 100 kΩ (internal resistors).
PIN ASSIGNMENTS
(Drawings Do Not Reflect Relative Size)
MC145506P
MC145507P
MC145508P
V
1
2
3
4
5
6
7
8
9
22 RSI
21
V
1
2
3
4
5
6
7
8
16
15
14
V
V
1
2
3
4
5
6
7
8
16
15
14
V
DD
ref
AG
DD
AG
RxO
+Tx
TxI
RxO
+Tx
TxI
RDD
RCE
RDD
RCE
V
AG
V
DD
RxO
20 RDD
19 RCE
18 RDC
17 TDC
16 CCI
15 TDD
14 TDE
13 MSI
RxG
RxO
+Tx
13 RDC
13 DC
12
11
10
9
12
11
10
9
–Tx
TDC
TDD
TDE
–Tx
CCI
Mu/A
PDI
Mu/A
PDI
TDD
TDE
TxI
–Tx
V
SS
V
SS
V
LS
V
LS
Mu/A
PDI 10
11
MC145507DW
MC145508DW
V
12
V
LS
SS
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
V
V
V
V
DD
AG
DD
AG
RxO
+Tx
TxI
15 RDD
14 RCE
13 RDC
12 TDC
11 TDD
10 TDE
RxO
+Tx
TxI
15 RDD
14 RCE
13 DC
–Tx
–Tx
12 CCI
11 TDD
10 TDE
Mu/A
PDI
Mu/A
PDI
9
9
V
LS
V
LS
V
SS
V
SS
MC145506•MC145507•MC145508
2
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to V
)
SS
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high–impedance circuit. For
Rating
DC Supply Voltage
Voltage, Any Pin to V
Symbol
Value
Unit
V
V
– V
–0.5 to 13
DD
SS
V
I
–0.5 to V
DD
+ 0.5
V
SS
DC Drain Per Pin (Excluding V , V
)
10
mA
°C
°C
DD SS
proper operation, it is recommended that V
in
≤
Operating Temperature Range
Storage Temperature Range
T
A
–40 to 85
and V
out
be constrained to the range V
SS
(V or V ) ≤ V
.
T
stg
–85 to 150
in out DD
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., V
,
SS
V , V , or V ).
DD LS AG
RECOMMENDED OPERATING CONDITIONS (T = –40° to 85°C)
A
Characteristic
Min
Typ
Max
Unit
DC Supply Voltage
V
Dual Supplies: V
Single Supply: V
= –V
(V
SS AG
= V = 0 V)
LS
4.75
5.0
6.3
DD
DD
to V
(V
is an Output, V = V
or V
)
SS
SS AG LS
DD
MC145506, MC145507, MC145508 Using Internal 3.15 V Reference
MC145506 Using Internal 2.5 V Reference
MC145506 Using Internal 3.78 V Reference
8.5
7.0
9.5
—
—
—
—
12.6
12.6
12.6
12.6
MC145506 Using External 1.5 V Reference, Referenced to V
AG
4.75
Power Dissipation
CMOS Logic Mode (V
HCMOS Logic Mode (V
mW
to V
= 10 V, V = V )
DD
SS
—
—
40
50
70
90
DD
SS
= 5 V, V
LS
= –5 V, V = V = 0 V)
LS AG
DD
Power Down Dissipation
—
0.1
8.0
1.0
8.5
mW
kHz
kHz
Frame Rate Transmit and Receive
7.5
CCI Clock Rate (TDC Clock Rate for MC145507)
MC145506, MC145508
—
—
—
—
—
128
—
—
—
—
—
1536
1544
2048
2560
Must Use One of These Frequencies ±2%, Relative to MSI Frequency of 8 kHz
Data Rate for MC145506, MC145508
64
—
4096
kHz
Full Scale Analog Input and Output Level
MC145507, MC145508
V
P
—
—
—
—
—
—
—
3.15
3.78
3.15
—
—
—
—
—
—
—
MC145506 (V = V
)
RSI = V
DD
ref
SS
RSI = V
SS
AG
DD
SS
AG
RSI = V
RSI = V
RSI = V
2.5
1.51 x V
1.26 x V
MC145506 Using an External Reference Voltage Applied at V Pin
ref
ref
ref
RSI = V
V
ref
DIGITAL LEVELS (V
SS
to V
= 4.75 V to 12.6 V, T = –40° to 85°C)
DD
A
Characteristic
Symbol
Min
Max
Unit
Input Voltage Levels (TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI, PDI)
V
CMOS Mode (V = V , V
is Digital Ground)
“0”
“1”
V
—
0.7 x V
—
0.3 x V
—
LS
DD SS
IL
DD
V
V
V
IH
IL
DD
V
LS
+ 0.8 V
—
HCMOS Mode (V ≤ V – 4.0 V, V is Digital Ground)
DD LS
“0”
“1”
LS
V
LS
+ 2.0 V
IH
Output Current for TDD (Transmit Digital Data)
mA
CMOS Mode (V = V , V
= 0 V and is Digital Ground)
(V
LS
DD SS
= 5 V, V
= 10 V, V
= 5 V, V
= 10 V, V
= 0.4 V)
= 0.5 V)
= 4.5 V)
= 9.5 V)
I
1.6
1.6
–1.6
–1.6
1.6
—
—
—
—
—
—
DD
out
out
out
out
OL
(V
DD
(V
DD
I
OH
(V
DD
I
HCMOS Mode (V ≤ V
– 4.75 V, V = 0 V and is Digital Ground) (V
= 0.4 V)
– 0.5 V)
OL
LS
DD
LS
OL
DD
I
–1.6
(V
OH
= V
OH
MOTOROLA
MC145506•MC145507•MC145508
For More Information On This Product,
Go to: www.freescale.com
3
Freescale Semiconductor, Inc.
ANALOG TRANSMISSION PERFORMANCE
(V
= 5 V ± 5%, V
= –5 V ± 5%, V = V
= 0 V, V = RSI = V
(Internal 3.15 V Reference),
SS
DD
SS
0 dBm0 = 1.546 Vrms = 6 dBm @ 600 Ω, T = –40° to 85°C, TDC = RDC = CCI, TDE = RCE = MSI, Unless Otherwise Noted)
LS AG
ref
A
End–to–End
A/D
D/A
Characteristic
Unit
dB
dB
dB
dB
dB
Min
—
Max
—
Min
–0.30
—
Max
0.30
Min
–0.30
—
Max
0.30
Absolute Gain (0 dBm0 @ 1.02 kHz, T = 25°C, V
= 5 V, V
= –5 V)
SS
A
DD
Absolute Gain Variation with Temperature 0° to 70°C
Absolute Gain Variation with Temperature –40° to 85°C
Absolute Gain Variation with Power Supply (V = 5 V, V
—
—
±0.03
±0.1
±0.03
±0.1
—
—
—
—
= –5 V, 5%)
SS
—
—
—
±0.02
—
±0.02
DD
Gain vs Level Tone (Relative to –10 dBm0, 1.02 kHz)
3 to –40 dBm0
–40 to –50 dBm0
–50 to –55 dBm0
–0.4
–0.8
–1.6
0.4
0.8
1.6
–0.2
–0.4
–0.8
0.2
0.4
0.8
–0.2
–0.4
–0.8
0.2
0.4
0.8
Gain vs Level Pseudo Noise (A–Law Relative to –10 dBm0)
dB
CCITT G.714
–10 to –40 dBm0
–40 to –50 dBm0
–50 to –55 dBm0
—
—
—
—
—
—
–0.25
–0.30
–0.45
0.25
0.30
0.45
–0.25
–0.30
–0.45
0.25
0.30
0.45
Total Distortion – 1.02 kHz Tone (C–Message)
0 to –30 dBm0
–40 dBm0
35
29
24
—
—
—
36
29
24
—
—
—
36
30
25
—
—
—
dBC
dB
–45 dBm0
Total Distortion With Pseudo Noise (A–Law)
CCITT G.714
–3 dBm0
–6 to –27 dBm0
–34 dBm0
27.5
35
33.1
28.2
13.2
—
—
—
—
—
28
—
—
—
—
—
28.5
36
34.2
30.0
15.0
—
—
—
—
—
35.5
33.5
28.5
13.5
–40 dBm0
–55 dBm0
Idle Channel Noise (For End–End and A/D, See Note 1)
(Mu–Law, C–Message Weighted)
(A–Law, Psophometric Weighted)
—
—
15
–69
—
—
15
–69
—
—
9
–78
dBrnC0
dBm0p
Frequency Response (Relative to 1.02 kHz @ 0 dBm0)
15 to 60 Hz
300 to 3000 Hz
3400 Hz
—
–0.3
–1.6
—
–23
0.3
0
–28
–60
—
–0.15
–0.8
—
–23
0.15
0
–14
–32
—
–0.15
–0.8
—
0.15
0.15
0
–14
–30
dB
4000 Hz
≥4600 Hz
—
—
—
Inband Spurious (1.02 kHz @ 0 dBm0, Transmit and RxO)
—
—
—
–43
—
–43
dBm0
dB
300 to 3000 Hz
Out–of–Band Spurious at RxO (300 – 3400 Hz @ 0 dBm0 In)
4600 to 7600 Hz
—
—
—
–30
–40
–30
—
—
—
—
—
—
—
—
—
–30
–40
–30
7600 to 8400 Hz
8400 to 100,000 Hz
Idle Channel Noise Selective @ 8 kHz, Input = V , 30 Hz Bandwidth
AG
—
–70
—
—
—
–70
dBm0
µs
Absolute Delay @ 1020 Hz (TDC = 2.048 MHz, TDE = 8 kHz)
Group Delay Referenced to 1600 Hz (TDC = 2048 kHz,
µs
TDE = 8 kHz)
500 to 600 Hz
600 to 800 Hz
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
Crosstalk of 1020 Hz @ 0 dBm0 From A/D or D/A (Note 2)
—
—
—
—
—
—
–75
–41
—
—
–80
–41
dB
dB
Intermodulation Distortion of Two Frequencies of Amplitudes –4 to
–21 dBm0 from the Range 300 to 3400 Hz
NOTES:
1. Extrapolated from a 1020 Hz @ –50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while the A/D is stimulated with 2667 Hz @ –50 dBm0.
MC145506•MC145507•MC145508
For More Information On This Product,
MOTOROLA
Go to: www.freescale.com
4
Freescale Semiconductor, Inc.
ANALOG ELECTRICAL CHARACTERISTICS (V
= –V
= 5 V to 6 V ±5%, T = –40° to 85°C)
SS A
DD
Characteristic
Symbol
Min
—
5
Typ
±0.01
10
Max
±0.2
—
Unit
µA
Input Current
+Tx, –Tx
+Tx, –Tx
+Tx, –Tx
I
in
AC Input Impedance to V
Input Capacitance
(1 kHz)
Z
in
MΩ
pF
AG
—
—
—
10
Input Offset Voltage of Txl Op Amp
Input Common Mode Voltage Range
Input Common Mode Rejection Ratio
Txl Unity Gain Bandwidth
< ±30
—
—
mV
V
+Tx, –Tx
+Tx, –Tx
V
V
+ 1.0
V
– 2.0
ICR
CMRR
BW
SS
DD
—
—
—
—
0
70
—
—
dB
R
R
≥ 10 kΩ
≥ 10 kΩ
1000
75
kHz
dB
L
p
Txl Open Loop Gain
A
VOL
—
L
Equivalent Input Noise (C–Message) Between +Tx and –Tx, at Txl
Output Load Capacitance for Txl Op Amp
–20
—
—
dBrnC0
pF
100
Output Voltage Range Txl Op Amp, RxO or RxO
V
out
V
R
R
= 10 kΩ to V
= 600 Ω to V
V
SS
V
SS
+ 0.8
+ 1.5
—
—
V
DD
V
DD
– 1.0
– 1.5
L
L
AG
AG
±5.5
—
—
mA
Output Current Txl, RxO, RxO
Output Impedance RxO, RxO*
V
+ 1.5 V ≤ V
out
≤ V – 1.5 V
DD
SS
0 to 3.4 kHz
Z
out
—
0
3
—
Ω
Output Load Capacitance for RxO and RxO*
Output dc Offset Voltage Referenced to V
—
200
pF
mV
Pin
RxO
RxO*
—
—
—
—
±100
±150
AG
Internal Gainsetting Resistors for RxG to RxO and RxO
62
0.5
—
100
—
225
kΩ
V
External Reference Voltage Applied to V (Referenced to V
)
V
– 1.0
ref AG
DD
V
ref
Input Current
—
20
—
µA
V
V
AG
Output Bias Voltage
—
0.53 V
0.47 V
+
DD
SS
V
Output Current
Source
Sink
I
0.4
10.0
—
—
0.8
—
mA
µA
AG
VAG
Output Leakage Current During Power Down for the Txl Op Amp, V
RxO, and RxO
,
—
—
±30
AG
Positive Power Supply Rejection Ratio,
0 – 100 kHz @ 250 mV, C–Message Weighting
Transmit
Receive
45
55
50
65
—
—
dBC
dBC
Negative Power Supply Rejection Ratio,
0 – 100 kHz @ 250 mV, C–Message Weighting
Transmit
Receive
50
50
55
60
—
—
* Assumes that RxG is not connected for gain modifications to RxO.
MOTOROLA
MC145506•MC145507•MC145508
For More Information On This Product,
Go to: www.freescale.com
5
Freescale Semiconductor, Inc.
MODE CONTROL LOGIC (V
SS
to V
= 4.75 V to 12.6 V, T = –40° to 85°C)
A
DD
Characteristic
Voltage for HCMOS Mode (HCMOS Logic Levels Referenced to V
Min
Typ
—
Max
V – 4.0
DD
Unit
V
V
V
)
LS
V
SS
LS
Voltage for CMOS Mode (CMOS Logic Levels of V
SS
to V
)
V
V
– 0.5
—
V
V
LS
DD
DD
DD
Mu/A Select Voltage
V
Mu–Law Mode
Sign Magnitude Mode
A–Law Mode
– 0.5
– 0.5
—
—
—
V
DD
DD
V
AG
V
+ 0.5
+ 0.5
AG
V
SS
V
SS
RSI Voltage for Reference Select Input (MC145506)
3.78 V Mode
2.5 V Mode
3.15 V Mode
V
– 0.5
– 0.5
—
—
—
V
V
V
DD
DD
V
AG
V
+ 0.5
+ 0.5
AG
V
SS
V
SS
V
ref
Voltage for Internal or External Reference (MC145506 Only)
Internal Reference Mode
External Reference Mode
V
—
—
V
V
+ 0.5
– 1.0
SS
+ 0.5
SS
DD
V
AG
Analog Test Mode Selection Frequency, MS = CCI (MC145506 Only)
See Pin Description; Test Modes
—
128
—
kHz
SWITCHING CHARACTERISTICS (V
SS
to V
= 9.5 V to 12.6 V, T = –40° to 85°C, C = 150 pF, CMOS or HCMOS Mode)
DD A L
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time
Output Fall Time
TDD
t
t
—
—
30
30
80
80
ns
TLH
THL
Input Rise Time
Input Fall Time
TDE, TDC, RCE, RDC, DC, MSI, CCI
t
t
—
—
—
—
4
4
µs
TLH
THL
Pulse Width
TDE Low, TDC, RCE, RDC, DC, MSI, CCI
TDC, RDC, DC
t
100
64
—
—
—
ns
w
Data Clock Pulse Frequency
f
4096
kHz
kHz
CL
CCI Clock Pulse Frequency (MSI = 8 kHz)
This Pin Will Accept One of These Discrete Clock Frequencies and
Will Compensate to Produce Internal Sequencing
f
f
f
f
f
—
—
—
—
—
128
—
—
—
—
—
CL1
CL2
CL3
CL4
CL5
1536
1544
2048
2560
Propagation Delay Time
ns
TDE Rising to TDD Low Impedance
HCMOS
t
t
t
t
—
—
—
—
—
—
—
—
90
90
—
—
90
90
90
90
180
150
55
P1
P2
P3
P4
CMOS
HCMOS
CMOS
HCMOS
CMOS
TDE Falling to TDD High Impedance
40
TDC Rising Edge to TDD Data, During TDE High
TDE Rising Edge to TDD Data, During TDC High
180
150
180
150
HCMOS
CMOS
TDC Falling Edge to TDE Rising Edge Setup Time
TDE Rising Edge to TDC Falling Edge Setup Time
t
20
100
20
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
µA
pF
µA
su1
su2
su8
su3
su4
su5
su6
su7
t
t
t
t
t
t
t
TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data
RDC Falling Edge to RCE Rising Edge Setup Time
RCE Rising Edge to RDC Falling Edge Setup Time
RDD Valid to RDC Falling Edge Setup Time
—
—
20
—
—
100
60
—
—
—
—
CCI Falling Edge to MSI Rising Edge Setup Time
MSI Rising Edge to CCI Falling Edge Setup Time
RDD Hold Time from RDC Falling Edge
20
—
—
100
100
—
—
—
t
h
—
—
TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance
TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current
TDD Capacitance During High Impedance (TDE Low)
TDD Input Current During High Impedance (TDE Low)
—
10
—
±0.01
12
±0.2
15
—
—
±0.1
±10.0
MC145506•MC145507•MC145508
6
MOTOROLA
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maximum flexibility. The MC145506 contains all the features
DEVICE DESCRIPTIONS
of the MC145507 and MC145508. The MC145506 is in-
tended for bit interleaved or byte interleaved applications with
data clock frequencies which are nonstandard or time vary-
ing. One of the five standard frequencies (listed below) is ap-
plied to the CCI input, and the data clock inputs can be any
A codec–filter is a device which is used for digitizing and
reconstructing the human voice. These devices were devel-
oped primarily for the telephone network to facilitate voice
switching and transmission. Once the voice is digitized, it
may be switched by digital switching methods or transmitted
long distance (T1, microwave, satellites, etc.) without degra-
dation. The name codec is an acronym from “coder” for the
A/D used to digitize voice, and “decoder” for the D/A used for
reconstructing voice. A codec is a single device that does
both the A/D and D/A conversions.
frequency between 64 kHz and 4.096 MHz. The V
pin
ref
allows for use of an external shared reference or selection of
the internal reference. The RxG pin accommodates gain ad-
justments for the inverted analog output. All three pins of the
input gainsetting operational amplifier are present which pro-
vide maximum flexibility for the analog interface.
To digitize intelligible voice requires a signal to distortion of
about 30 dB for a dynamic range of about 40 dB. This may be
accomplished with a linear 13–bit A/D and D/A, but will far ex-
ceed the required signal to distortion at amplitudes greater
than 40 dB below the peak amplitude. This excess perform-
ance is at the expense of data per sample. Two methods of
data reduction are implemented by compressing the 13–bit
linear scheme to companded 8–bit schemes. These com-
panding schemes follow a segmented or “piecewise–linear”
curve formatted as a sign bit, 3 chord bits, and 4 step bits. For
a given chord, all 16 of the steps have the same voltage
weighting. As the voltage of the analog input increases, the 4
step bits increment and carry to the 3 chord bits which incre-
ment. With the chord bits incremented, the step bits double
their voltage weighting. This results in an effective resolution
of 6 bits (sign + chord + 4 step bits) across a 42 dB dynamic
range (7 chords above 0, by 6 dB per chord). There are two
companding schemes used; Mu–255 Law specifically in
North America, and A–Law specifically in Europe. These
companding schemes are accepted world wide. The tables
show the linear quantization levels to PCM words for the two
companding schemes.
MC145507
The MC145507 PCM mono–circuit is intended for standard
byte interleaved synchronous or asynchronous applications.
TDC can be one of five discrete frequencies. These are
128 kHz (40% to 60% duty cycle), 1.536 MHz, 1.544 MHz,
2.048 MHz, or 2.56 MHz. (For other data clock frequencies,
see MC145506 or MC145508.) The internal reference is set
for 3.15 V peak full scale, and the full scale input level at TxI
and output level at RxO is 6.3 Vp–p. This is the 3 dBm0 level
of the PCM codec–filter. The +Tx and –Tx inputs provide
maximum flexibility for analog interface. All other functions
are described in the pin description.
MC145508
The MC145508 PCM mono–circuit is intended for byte in-
terleaved synchronous applications. The MC145508 has all
the features of the MC145507 but internally connects TDC
and RDC (see pin description) to the DC pin. One of the five
standard frequencies (listed above) should be applied to CCI.
The data clock input (DC) can be any frequency between
64 kHz and 4.069 MHz.
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a band-
width of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the inband signal. The telephone line is also subject to
50/60 Hz power line coupling which must be attenuated from
the signal by a high–pass filter before the A/D converter.
The D/A process reconstructs a staircase version of the
desired inband signal which has spectral images of the in-
band signal modulated about the sample frequency and its
harmonics. These spectral images are called aliasing compo-
nents which need to be attenuated to obtain the desired sig-
nal. The low–pass filter used to attenuate these aliasing
components is typically called a reconstruction or smoothing
filter.
PIN DESCRIPTIONS
DIGITAL
V
LS
Logic Level Select Input and HCMOS Digital Ground
V
controls the logic levels and digital ground reference
LS
for all digital inputs and the digital output. These devices can
operate with logic levels from full supply (V to V ) or
SS
DD
with TTL logic levels using V as digital ground. For V
=
LS
LS
swing) with CMOS
V
, all I/O is full supply (V to V
DD
switch points. For V
SS
LS
DD
< (V – 4 V), all inputs are
DD
< V
SS
TTL compatible with V being the digital ground while TDD
LS
outputs HCMOS levels from V to V . The pins controlled
LS
DD
by V
are inputs MSI, CCI, TDE, TDC, RCE, RDC, RDD,
LS
PDI, and output TDD.
MSI
Master Synchronization Input
MSI is used for determining the sample rate of the transmit
side and as a time base for selecting the internal prescale
divider for the convert clock input (CCI) pin. The MSI pin
should be tied to an 8 kHz clock which may be a frame sync
or system sync signal. MSI has no relation to transmit or
receive data timing, except for determining the internal trans-
mit strobe as described under the TDE pin description. MSI
should be derived from the transmit timing in asynchronous
applications. In many applications, MSI can be tied to TDE.
(MSI is tied internally to TDE in the MC145507/08.)
The MC145500 series PCM codec–filters have the codec,
both presampling and reconstruction filters, a precision volt-
age reference on chip, and require no external components.
There are three distinct versions of the Motorola MC145500
series with HCMOS compatible outputs.
MC145506
The MC145506 PCM codec–filter is the full–featured
22–pin device. It is intended for use in applications requiring
MOTOROLA
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CCI
RDC
Convert Clock Input
Receive Data Clock Input
RDC can be any frequency from 64 kHz to 4.096 MHz. This
pin is often tied to the TDC pin for applications that can use a
common clock for both transmit and receive data transfers.
The receive shift register is controlled by the receive clock
enable (RCE) pin to clock data into the receive digital data
(RDD) pin on falling RDC edges. These three signals can be
asynchronous with all other digital pins. The RDC input is in-
ternally tied to the TDC input on the MC145508 and called
DC.
CCI is designed to accept five discrete clock frequencies.
These are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
2.56 MHz. The frequency at this input is compared with MSI
and prescale divided to produce the internal sequencing
clock at 128 kHz (or 16 times the sampling rate). The duty
cycle of CCI is dictated by the minimum pulse width except for
128 kHz, which is used directly for internal sequencing and
must have a 40% to 60% duty cycle. In asynchronous appli-
cations, CCI should be derived from transmit timing. (CCI is
tied internally to TDC in the MC145507.)
RCE
Receive Clock Enable Input
TDC
The rising edge of RCE should identify the sign bit of a
receive PCM word on RDD. The next falling edge of RDC,
after a rising RCE, loads the first bit of the PCM word into the
receive register. The next seven falling edges enter the
remainder of the PCM word. On the ninth rising edge, the
receive PCM word is transferred to the receive buffer register
and the A/D sequence is interrupted to commence the
decode process. In asynchronous applications with an 8 kHz
transmit sample rate, the receive sample rate should be be-
tween 7.5 kHz and 8.5 kHz. Two receive PCM words may be
decoded and analog summed each transmit frame to allow
on–chip conferencing. The two PCM words should be
clocked in as two single PCM words, a minimum of 31.25 µs
apart, with a receive data clock of 512 kHz or faster.
Transmit Data Clock Input
TDC can be any frequency from 64 kHz to 4.096 MHz, and
is often tied to CCI if the data rate is equal to one of the five
discrete frequencies. This clock is the shift clock for the trans-
mit shift register and its rising edges produce successive data
bits at TDD. TDE should be derived from this clock. (TDC and
RDC are tied together internally in the MC145508 and are
called DC.)
TDE
Transmit Data Enable Input
TDE serves three major functions. The first TDE rising
edge following an MSI rising edge, generates the internal
transmit strobe which initiates an A/D conversion. The inter-
nal transmit strobe also transfers a new PCM data word into
the transmit shift register (sign bit first) ready to be output at
TDD. The TDE pin is the high–impedance control for the
transmit digital data (TDD) output. As long as this pin is high,
the TDD output stays low impedance. This pin also enables
the output shift register for clocking out the 8–bit serial PCM
word. The logical AND of the TDE pin with the TDC pin,
clocks out a new data bit at TDD. TDE should be held high for
eight consecutive TDC cycles to clock out a complete PCM
word for byte interleaved applications. The transmit shift reg-
ister feeds back on itself to allow multiple reads of the transmit
data. If the PCM word is clocked out once per frame in a byte
interleaved system, the MSI pin function is transparent and
may be connected to TDE.
RDD
Receive Digital Data Input
RDD is the receive digital data input. The timing for this pin
is controlled by RDC and RCE. The data format is determined
by the Mu/A pin.
Mu/A
Mu/A Select
This pin selects the companding law and the data format at
TDD and RDD.
Mu/A = V ; Mu–255 Companding D3 Data Format with
DD
Zero Code Suppress
Mu/A = V ; Mu–255 Companding with Sign Magnitude
AG
Data Format
Mu/A = V ; A–Law Companding with CCITT Data Format
SS
The TDE pin may be cycled during a PCM word for bit inter-
leaved applications. TDE controls both the high–impedance
state of the TDD output and the internal shift clock. TDE must
Bit Inversions
Sign/
A–Law
fall before TDC rises (t
) to ensure integrity of the next data
su8
Magnitude
(CCITT)
Code
Mu–Law
bit. There must be at least two TDC falling edges between the
last TDE rising edge of one frame and the first TDE rising
edge of the next frame. MSI must be available separate from
TDE for bit interleaved applications.
+ Full Scale
+ Zero
– Zero
1111 1111
1000 0000
0000 0000
0111 1111
1000 0000
1111 1111
0111 1111
0000 0010
1010 1010
1101 0101
0101 0101
0010 1010
– Full Scale
TDD
SIGN
BIT
Transmit Digital Data Output
CHORD BITS
STEP BITS
The output levels at this pin are controlled by the V pin.
LS
connected to V , the output levels are from V
For V
0
1
2
3
4
5
6
7
LS
DD
SS
to V . For a voltage of V between V
– 4 V and V , the
DD LS
DD
SS
output levels are HCMOS compatible with V
LS
being the
NOTE: Starting from sign magnitude, to change format:
To Mu–Law —
digital ground supply and V
DD
being the positive logic supply.
The TDD pin is a three–state output controlled by the TDE
pin. The timing of this pin is controlled by TDC and TDE. The
data format (Mu–Law, A–Law, or sign magnitude) is con-
trolled by the Mu/A pin.
MSB is unchanged (sign)
Invert remaining 7 bits
If code is 0000 0000, change to 0000 0010 (for zero
code suppression)
MC145506•MC145507•MC145508
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To A–Law —
reference voltage gain selection circuitry associated with RSI
must be considered to arrive at the desired codec–filter gain.
Internal Mode — In the internal reference mode (V
MSB is unchanged (sign)
Invert odd numbered bits
Ignore zero code suppression
=
ref
), an internal 2.5 V reference supplies the reference volt-
V
SS
age for the RSI circuitry. The V
pin is functionally con-
ref
for the MC145507 and MC145508 pinouts.
nected to V
PDI
SS
Power Down Input
RSI
The power down input disables the bias circuitry and gates
off all clock inputs. This puts the V , Txl, RxO, RxO, and
TDD outputs into a high–impedance state. The power dissi-
pation is reduced to 0.1 mW when PDI is a low logic level. The
circuit operates normally with PDI = V
Reference Select Input (MC145506 Only)
AG
The RSI input allows the selection of three different over-
load or full–scale A/D and D/A converter reference voltages
independent of the internal or external reference mode. The
RSI pin is a digital input that senses three different logic
states: V , V , and V
DD
voltage is used directly for the converters. The internal refer-
or with a logic high
DD
as defined by connection at V . TDD will not come out of
high impedance for two MSI cycles after PDI goes high.
LS
. For RSI = V , the reference
SS AG
AG
ence is 2.5 V. For RSI = V , the reference voltage is multi-
plied by the ratio of 1.26, which results in an internal converter
SS
DC
Data Clock Input
reference of 3.15 V. For RSI = V
multiplied by 1.51, which results in an internal converter refer-
ence of 3.78 V. The device requires a minimum of 1.0 V of
, the reference voltage is
DD
In the MC145508, TDC and RDC are internally connected
to DCLK.
headroom between the internal converter reference to V
.
DD
has this same absolute valued minimum, also measured
V
ANALOG
SS
from the V
pin. The various modes of operation are sum-
AG
marized in Table 2. The RSI pin is functionally connected to
for the MC145507 and MC145508 pinouts.
V
AG
Analog Ground Input/Output Pin
V
SS
V
is the analog ground power supply input/output. All
AG
RxO, RxO
Receive Analog Outputs
analog signals into and out of the device use this as their
ground reference. Each version of the MC145500 PCM
codec–filter family can provide its own analog ground supply
internally. The dc voltage of this internal supply is 6% positive
These two complimentary outputs are generated from the
output of the receive filter. They are equal in magnitude and
out of phase. The maximum signal output of each is equal to
the maximum peak–to–peak signal described with the refer-
of the midway between V
and V . This supply can sink
DD
SS
more than 8 mA but has a current source limited to 400 µA.
The output of this supply is internally connected to the analog
ground input of the part. The node where this supply and the
analog ground are connected is brought out to the V
symmetric dual supply systems (±5, ±6, etc.), V
AG
externally tied to the system analog ground supply. When
RxO or RxO drive low–impedance loads tied to V , a pull–
up resistor to V
capability if V
AG
signals for the part are referenced to V , including noise;
therefore, decoupling capacitors (0.1 µF) should be used
from V
ence. If a 3.15 V reference is used with RSI tied to V
and a
AG
3 dBm0 sine wave is decoded, the RxO output will be a 6.3 V
peak–to–peak signal. RxO will also have an inverted signal
output of 6.3 V peak–to–peak. External loads may be con-
nected from RxO to RxO for a 6 dB push–pull signal gain or
from either RxO or RxO to V . With a 3.15 V reference, each
output will drive 600 Ω to 9 dBm. With RSI tied to V , each
pin. In
may be
AG
AG
AG
will be required to boost the source current
is not tied to the supply ground. All analog
DD
DD
output will drive 900 Ω to 9 dBm.
AG
RxG
Receive Output Gain Adjust (MC145506 Only)
to V
and V
to V .
DD
AG
SS
AG
The purpose of the RxG pin is to allow external gain adjust-
ment for the RxO pin. If RxG is left open, then the output sig-
nal at RxO will be inverted and output at RxO. Thus, the
push–pull gain to a load from RxO to RxO is two times the out-
put level at RxO. If external resistors are applied from RxO to
RxG (RI) and from RxG to RxO (RG), the gain of RxO can be
set differently from inverting unity. These resistors should be
in the range of 10 kΩ. The RxO output level is unchanged by
the resistors and the RxO gain is approximately equal to
minus RG/RI. The actual gain is determined by taking into
account the internal resistors which will be in parallel to these
external resistors. The internal resistors have a large toler-
ance, but they match each other very closely. This matching
tends to minimize the effects of their tolerance on external
gain configurations. The circuit for RxG and RxO is shown in
the Block Diagram.
V
ref
Positive Voltage Reference Input (MC145506 Only)
The V
pin allows an external reference voltage to be
ref
used for the A/D and D/A conversions. If V is tied to V
the internal reference is selected. If V > V , then the ex-
ternal mode is selected and the voltage applied to V
ref
used for generating the internal converter reference voltage.
In either internal or external reference mode, the actual volt-
age used for conversion is multiplied by the ratio selected by
the RSI pin. The RSI pin circuitry is explained under its pin
description below. Both the internal and external references
are inverted within the PCM codec–filter for negative input
voltages such that only one reference is required.
,
ref
SS
ref
AG
is
External Mode — In the external reference mode (V
), a 2.5 V reference like the MC1403 may be connected
>
ref
V
AG
from V to V . A single external reference may be shared
Txl
ref
AG
Transmit Analog Input
by tying together a number of V pins and V
ref AG
different codec–filters. In special applications, the external
reference voltage may be between 0.5 and 5 V. However, the
pins from
TxI is the input to the transmit filter. It is also the output of
the transmit gain amplifier. The TxI input has an internal gain
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of 1.0, such that a 3 dBm0 signal at TxI corresponds to the
peak converter reference voltage as described in the V
and RSI pin descriptions. For a 3.15 V reference, the 3 dBm0
input should be 6.3 V peak–to–peak.
ground accommodating TTL logic levels), and V = 0 V
AG
being tied to system analog ground.
ref
For single–supply applications, typical power supply con-
figurations include:
V
V
V
= 10 V to 12 V
= 0 V
generates a mid supply voltage for referencing all ana-
DD
SS
+Tx / –Tx
Positive Tx Amplifier Input
Negative Tx Amplifier Input
AG
log signals.
controls the logic levels. This pin should be connected
V
LS
to V
The Txl pin is the input to the transmit band–pass filter. If
+Tx or –Tx is available, then there is an internal amplifier
preceding the filter whose pins are +Tx, –Tx, and TxI. These
pins allow access to the amplifier terminals to tailor the input
gain with external resistors. The resistors should be in the
range of 10 kΩ.
for CMOS logic levels from V
to V . This pin
DD
should be connected to digital ground for true TTL logic input
levelsreferencedtoV , withHCMOSoutputlevelsfromV
SS DD
LS
LS
to V
.
DD
TESTING CONSIDERATIONS (MC145506 ONLY)
POWER SUPPLIES
An analog test mode is activated by connecting MSI and
CCI to 128 kHz. In this mode, the input of the A/D (the output
of the Tx filter) is available at the PDI pin. This input is direct
coupled to the A/D side of the codec. The A/D is a differential
design. This results in the gain of this input being effectively
attenuated by half. If monitored with a high–impedance buff-
er, the output of the Tx low–pass filter can also be measured
at the PDI pin. This test mode allows independent evaluation
of the transmit low–pass filter and A/D side of the codec. The
transmit and receive channels of these devices are tested
with the codec–filter fully functional.
V
DD
Most Positive Power Supply
V
is typically 5 V to 12 V.
DD
V
SS
Most Negative Power Supply
V
is typically 10 V to 12 V negative of V
.
DD
SS
For a ±5 V dual–supply system, the typical power supply
configuration is V = 5 V, V = –5 V, V = 0 V (digital
DD
SS
LS
5 V
0.1 µF
MC145507
V
AG
Rx
Tx
51 kΩ*
1
16
V
V
DD
AG
600 Ω
2
3
4
5
6
7
8
15
14
13
12
11
10
9
RxO
+Tx
RDD
RCE
ENABLE
CLOCK
5 kΩ
10 kΩ
TxI
RDC
–Tx
TDC
TDD
TDE
681
Mu/A
PDI
V
V
LS
SS
0.1 µF
–5 V
* To define RDD when TDD is high Z.
Figure 1. Test Circuit
Table 1. MC145506 Options Available by Pin Selection
RSI*
Pin Level
V
*
Peak–to–Peak Overload Voltage
(Txl, RxO)
ref
Pin Level
V
V
V
7.56 Vp–p
DD
SS
V
+ V
(3.02 x V ) Vp–p
EXT
DD
AG
EXT
EXT
EXT
V
AG
V
SS
5 Vp–p
(2 x V ) Vp–p
V
AG
V
+ V
AG
EXT
6.3 Vp–p
(2.52 x V ) Vp–p
V
V
V
SS
SS
V
+ V
SS
AG
EXT
* On MC145507/08, RSI and V
ref
are tied internally to V
.
SS
MC145506•MC145507•MC145508
10
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Table 2. Summary of Operation Conditions User Programmed Through Pins V , V , and V
DD AG
SS
Pin
RSI
Programmed
Peak
Logic
Level
Overload
Voltage
Mu/A
V
LS
V
Mu–Law Companding Curve and D3/D4 Digital
Formats with Zero Code Suppress
3.78
2.50
3.15
CMOS
Logic Levels
DD
V
AG
Mu–Law Companding Curve and Sign Magnitude
Data Format
TTL Input Levels, V
HCMOS Output Levels, V
Up;
AG
to V
to V
AG
DD
V
A–Law Companding Curve and CCITT Digital
Format
TTL Levels, V
HCMOS Output Levels, V
Up;
SS
SS
SS
DD
TDE
t
P4
t
w
f
CL
t
su2
t
t
t
w
su8
su1
TDC
1
2
3
t
4
5
6
7
8
t
9
10
11
t
P2
t
P3
P3
P2
t
P1
MSB
LSB
*
TDD
PCM WORD REPEATED
* Data output during this time will vary depending on TDC rate and TDE timing.
Figure 2. Transmit Timing Diagram
t
w
RCE
t
su4
f
CL
t
w
t
su3
t
w
RDC
RDD
1
2
3
4
5
6
7
8
9
10
11
t
h
t
su5
DON’T
CARE
DON’T
CARE
MSB
LSB
Figure 3. Receive Timing Diagram
t
w
MSI
CCI
t
t
w
su7
t
t
w
su6
1
2
3
4
5
6
7
8
9
10
11
Figure 4. MSI/CCI Timing Diagram
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1.00
0.80
1.00
V
= 5 V
= –5 V
V
= 5 V
= –5 V
DD
DD
0.80
0.60
0.40
0.20
0
V
V
SS
SS
2048 kHz CLOCK
0.60
0.40
0.20
0
2048 kHz CLOCK
GUARANTEED
PERFORMANCE
GUARANTEED
PERFORMANCE
TYPICAL
PERFORMANCE
TYPICAL
PERFORMANCE
–0.20
–0.40
–0.60
–0.20
–0.40
–0.60
–0.80
–1.00
–0.80
–1.00
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL AT 1.02 kHz
INPUT LEVEL AT 1.02 kHz
Figure 5. MC145506 Gain vs Level Mu–Law Transmit
Figure 6. MC145506 Gain vs Level Mu–Law Receive
45.0
45.0
40.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
TYPICAL
PERFORMANCE
TYPICAL
PERFORMANCE
35.0
30.0
25.0
20.0
15.0
10.0
C–MESSAGE WEIGHTED
C–MESSAGE WEIGHTED
V
V
SS
= 5 V
= –5 V
V
V
SS
= 5 V
= –5 V
DD
DD
2048 kHz CLOCK
2048 kHz CLOCK
GUARANTEED
PERFORMANCE
GUARANTEED
PERFORMANCE
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL AT 1.02 kHz
INPUT LEVEL AT 1.02 kHz
Figure 7. MC145506 Quantization
Distortion Mu–Law Transmit
Figure 8. MC145506 Quantization
Distortion Mu–Law Receive
0.8
0.6
0.4
0.8
0.6
0.4
V
= 5 V
= –5 V
V
= 5 V
= –5 V
DD
DD
V
V
SS
SS
2048 kHz CLOCK
2048 kHz CLOCK
0.2
0
0.2
0
TYPICAL PERFORMANCE
TYPICAL PERFORMANCE
GUARANTEED
–0.2
–0.4
–0.2
–0.4
PERFORMANCE
GUARANTEED
PERFORMANCE
–0.6
–0.8
–0.6
–0.8
–60
–50
–40
–30
–20
–10
–60
–50
–40
–30
–20
–10
INPUT LEVEL PSEUDO NOISE (dBm0)
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 9. MC145506 Gain vs Level A–Law Transmit
Figure 10. MC145506 Gain vs Level A–Law Receive
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40.0
35.0
30.0
25.0
20.0
15.0
10.0
40.0
TYPICAL
PERFORMANCE
TYPICAL
PERFORMANCE
GUARANTEED
PERFORMANCE
35.0
GUARANTEED
PERFORMANCE
30.0
PSOPHOMETRIC
WEIGHTED
25.0
20.0
15.0
10.0
PSOPHOMETRIC
WEIGHTED
V
= 5 V
= –5 V
V
V
= 5 V
= –5 V
2048 kHz
DD
DD
SS
V
SS
2048 kHz
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL PSEUDO NOISE (dBm0)
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 11. MC145506 Quantization Distortion
A–Law Transmit
Figure 12. MC145506 Quantization Distortion
A–Law Receive
70
60
70
TYPICAL PERFORMANCE
TYPICAL PERFORMANCE
60
50
40
30
50
40
30
20
10
0
20
10
0
0
10
20
30
40 50
60 70 80
90 100
0
10 20
30 40
50 60
70
80
90 100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 13. MC145506 Power Supply Rejection
Ratio Positive Transmit VAC = 250 mVrms,
C–Message Weighted
Figure 14. MC145506 Power Supply Rejection
Ratio Negative Transmit VAC = 250 mVrms,
C–Message Weighted
70
70
TYPICAL PERFORMANCE
TYPICAL PERFORMANCE
60
60
50
40
30
20
10
0
50
40
30
20
10
0
0
10 20
30
40
50
60
70
80
90 100
0
10
20 30
40
50 60
70
80
90 100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 15. MC145506 Power Supply Rejection
Ratio Positive Receive VAC = 250 mVrms,
C–Message Weighted
Figure 16. MC145506 Power Supply Rejection
Ratio Negative Receive VAC = 250 mVrms,
C–Message Weighted
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0.2
0.1
2.0
0
0
–2.0
TYPICAL
PERFORMANCE
–4.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–6.0
–8.0
GUARANTEED
PERFORMANCE
TYPICAL
PERFORMANCE
–10.0
GUARANTEED
PERFORMANCE
–12.0
–14.0
–16.0
–18.0
GUARANTEED
PERFORMANCE
0
0.4
0.8
1.2
1.6
2.0 2.4
2.8
3.2
3.6
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 17. MC145506 Pass–Band
Filter Response Transmit
Figure 18. MC145506 Low–Pass Filter
Response Transmit
2.0
–2.0
0.2
0.1
TYPICAL
PERFORMANCE
0
–0.1
–0.2
–0.3
–0.4
–0.5
–6.0
TYPICAL
PERFORMANCE
–10.0
–14.0
–18.0
–22.0
–26.0
–30.0
GUARANTEED
PERFORMANCE
GUARANTEED
PERFORMANCE
–0.6
–0.7
–0.8
0
0.4
0.8
1.2
1.6
2.0 2.4
2.8
3.2
3.6
0
0.04
0.08
0.12
0.16
0.20
0.24
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 19. MC145506 High–Pass Filter
Response Transmit
Figure 20. MC145506 Pass–Band
Filter Response Receive
2.0
0
GUARANTEED
–2.0
PERFORMANCE
–4.0
–6.0
–8.0
TYPICAL
PERFORMANCE
–10.0
–12.0
GUARANTEED
PERFORMANCE
–14.0
–16.0
–18.0
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2
FREQUENCY (kHz)
Figure 21. MC145506 Low–Pass Filter Response Receive
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2.048 MHz
18 pF
18 pF
10 MΩ
300 Ω
2.048 MHz
5 V
(TDC, RDC, CCI)
V
CC
R
OSC
IN
OSC
OUT 1 OUT 2
OSC
8 kHz
(TDE, RCE, MSI)
0.1 µF
MC74HC4060
GND Q8
Q4
5 V
V
CC
J
Q
J
Q
Q
1/2
MC74HC73
1/2
MC74HC73
K
Q
K
GND
R
R
5 V
255
256
1
2
3
4
5
6
7
8
9
10
2.048 MHz
8 kHz
Figure 22. Simple Clock Circuit for Driving MC145506/07/08 Codec–Filters
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V
AG
V
DD
N = 1
R0
RxO
RDD
RCE
R0
N = 2
+Tx
TxI
–48 V
10 kΩ
N = 1
RDC
TDC
10 kΩ
–Tx
TDD
TDE
Mu/A
PDI
V
SS
V
LS
MC145507
(a) Simplified Transformer Hybrid Using MC145507
V
AG
V
DD
N = 1
R3
RxO
+Tx
TxI
RDD
RCE
R0
R5
R6
N = 2 R4
–48 V
R1
N = 1
RDC
TDC
R2
–Tx
TDD
TDE
Mu/A
PDI
R0 = R3 R4 (R2 + R1) R3 R4
R0 R4 (R2 + R1)
R0 R4
A
=
V
out
R3 + R0 R4 (R2 + R1)
R3 + R0 R4
V
SS
V
LS
– R1
A
=
V
MC145507
in
R2
NOTE: Hybrid balance by R5 and R6 to equate the RxO signal gain at Txl through the
inverting and non–inverting signal paths.
(b) Universal Transformer Hybrid Using MC145507
Figure 23. Hybrid Interfaces to the MC145507 PCM Codec–Filter Mono–Circuit
MC145506•MC145507•MC145508
16
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R0 = 600 Ω
R0 = 900 Ω
+V
ref
RSI
V
SS
V
V
AG
DD
RDD
RCE
RDC
TDC
N = 1
RxO
RxG
R5
R6
R4
R3
R0
N = 2
RxO
+Tx
–48 V
N = 1
R0
TxI
CCI
TDD
TDE
MSI
R2
R1
–Tx
NOTE: Balance by R5 and R6 to equate the Txl gains through the inverting
and non–inverting input signal paths, respectively, is given by:
Mu/A
PDI
R1
R3
R4
R1
R2
R6
R3
R5
1 –
=
1 +
–
2 × R2
R5 + R6
R4 R5 + R6
V
SS
V
LS
Tx Gain = R1/R2
Rx Gain = 1 + R3/R4
R5, R6 ≈ 10 kΩ
MC145506
Adjust Rx Gain with R3
Adjust Tx Gain with R1
(a) Universal Transformer Hybrid Using MC145506
R0 = 600 Ω
R0 = 900 Ω
T
+V
ref
RSI
N = 1
N = 1
V
SS
V
AG
10 kΩ
V
DD
N = 2
R0
R0
RxO
RxG
RDD
RCE
RDC
TDC
20 kΩ
–48 V
RxO
R
+Tx
TxI
CCI
TDD
TDE
MSI
20 kΩ
–Tx
10 kΩ
Mu/A
PDI
V
SS
V
LS
MC145506
(b) Single–Ended Hybrid Using MC145506
Figure 24. Hybrid Interfaces to the MC145506 PCM Codec–Filter Mono–Circuit
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Figure 25. A Complete Single Party Channel Unit Using
MC3419 SLIC and MC145507 PCM Mono–Circuit
MC145506•MC145507•MC145508
18
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MC145406
MC145428
MC145426
MC34119
MC145507
MC145412
Figure 26. Digital Telephone Schematic
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Table 3. Mu–Law Encode–Decode Characteristics
Normalized
Digital Code
Encode
Normalized
Decode
Levels
1
2
3
4
5
6
7
8
Chord
Number
Number
of Steps
Step
Size
Decision
Levels
Sign
Chord Chord Chord Step
Step Step
Step
8159
7903
4319
4063
2143
2015
1055
991
511
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
8031
4191
2079
1023
495
231
99
8
16
256
7
6
5
4
3
2
1
16
16
16
16
16
16
128
64
32
16
8
479
239
223
103
95
4
35
33
31
15
1
2
1
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
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Table 4. A–Law Encode–Decode Characteristics
Normalized
Digital Code
Encode
Normalized
Decode
Levels
1
2
3
4
5
6
7
8
Chord
Number
Number
of Steps
Step
Size
Decision
Levels
Sign
Chord Chord Chord Step
Step Step
Step
4096
3968
2176
2048
1088
1024
544
512
272
256
136
128
68
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032
2112
1056
528
264
132
66
7
16
128
6
5
4
3
2
16
16
16
16
16
32
64
32
16
8
4
64
1
2
2
1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes alternate bit inversion, as specified by CCITT.
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PACKAGE DIMENSIONS
DW SUFFIX
SOG PACKAGE
CASE 751–03
(MC145507/08)
A
D
16
9
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
8
MILLIMETERS
B
16X B
DIM MIN
MAX
2.65
0.25
0.49
0.32
10.45
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
10.15
7.40
M
S
S
0.25
T A
B
e
1.27 BSC
H
h
L
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
14X
e
C
T
P SUFFIX
PLASTIC DIP
CASE 648–08
(MC145507/08)
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
B
S
8
INCHES
DIM MIN MAX
0.770 18.80
MILLIMETERS
MIN
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
C
L
0.270
0.175
0.021
0.70
6.35
3.69
0.39
1.02
SEATING
–T–
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
MC145506•MC145507•MC145508
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P SUFFIX
PLASTIC DIP
CASE 708–04
(MC145506)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
22
1
12
11
B
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
1.115
0.360
0.200
0.022
0.070
A
B
C
D
F
27.56
8.64
3.94
0.36
1.27
28.32 1.085
9.14 0.340
5.08 0.155
0.56 0.014
1.78 0.050
L
A
N
G
H
J
K
L
2.54 BSC
0.100 BSC
C
K
1.02
0.20
2.92
1.52 0.040
0.38 0.008
3.43
0.060
0.015
0.135
0.115
10.16 BSC
0.400 BSC
M
N
0
0.51
15
0
15
0.040
SEATING
PLANE
J
H
G
F
D
M
1.02 0.020
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