MC14551BCL [ONSEMI]
IC,ANALOG SWITCH,QUAD,SPDT,CMOS,DIP,16PIN,CERAMIC;
| 型号： | MC14551BCL |
| 厂家： | 
ONSEMI |
| 描述： | IC,ANALOG SWITCH,QUAD,SPDT,CMOS,DIP,16PIN,CERAMIC 解复用器 |
| 文件： | 总12页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14551B
Quad 2-Channel Analog
Multiplexer/Demultiplexer
The MC14551B is a digitally–controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.
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• Triple Diode Protection on All Control Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V – V ) = 3.0 to 18 V
MARKING
DIAGRAMS
DD
EE
16
Note: V must be v V
EE
SS
PDIP–16
P SUFFIX
CASE 648
MC14551BCP
AWLYYWW
• Linearized Transfer Characteristics
• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical
1
• For Low R , Use The HC4051, HC4052, or HC4053 High–Speed
ON
CMOS Devices
16
• Switch Function is Break Before Make
SOIC–16
D SUFFIX
CASE 751B
14551B
AWLYWW
1
MAXIMUM RATINGS (2.)
16
SOEIAJ–16
F SUFFIX
CASE 966
Symbol
Parameter
Value
Unit
MC14551B
ALYW
V
DD
DC Supply Voltage Range
– 0.5 to + 18.0
V
(Referenced to V , V ≥ V )
EE
EE
SS
1
V , V
in out
Input or Output Voltage (DC or
Transient) (Referenced to V for
– 0.5 to V + 0.5
V
DD
SS
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
Control Input & V for Switch I/O)
EE
I
in
Input Current (DC or Transient),
per Control Pin
± 10
mA
WW, W = Work Week
I
Switch Through Current
± 25
500
mA
mW
_C
sw
(3.)
P
T
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
ORDERING INFORMATION
D
– 55 to + 125
– 65 to + 150
260
Device
Package
PDIP–16
Shipping
A
T
_C
stg
MC14551BCP
MC14551BD
MC14551BDR2
MC14551BF
2000/Box
48/Rail
T
Lead Temperature
(8–Second Soldering)
_C
L
SOIC–16
SOIC–16
SOEIAJ–16
2500/Tape & Reel
See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V for control inputs and V ≤ (V or V ) ≤
SS
in
out
DD
EE
in
out
V
DD
for Switch I/O.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V , V or V ). Unused outputs must be left open.
SS
EE
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 4
MC14551B/D
MC14551B
PIN ASSIGNMENT
W1
X0
X1
X
1
2
3
4
5
6
7
8
16
V
DD
15 W0
14
13
W
Z
Y
12 Z1
11 Z0
10 Y1
Y0
V
EE
SS
V
9
CONTROL
CONTROL
9
W
14
ă4
W0
W1
X0
X1
Y0
Y1
Z0
Z1
15
1
2
3
6
X
COMMONS
OUT/IN
SWITCHES
IN/OUT
Y
Z
ă5
13
10
11
12
Control
ON
V
V
V
= Pin 16
= Pin 8
= Pin 7
DD
SS
EE
0
1
W0 X0 Y0 Z0
W1 X1 Y1 Z1
NOTE: Control Input referenced to V , Analog Inputs and
SS
Outputs reference to V . V must be v V
.
EE
EE
SS
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2
MC14551B
ELECTRICAL CHARACTERISTICS
– 55_C
Min Max Min
25_C
125_C
(4.)
Typ
Max Min
Max
Characteristic
Symbol
V
DD
Test Conditions
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to V
)
EE
Power Supply Voltage
Range
V
DD
—
V
– 3.0 ≥ V
SS
≥
3.0
18
3.0
—
18
3.0
18
V
DD
V
EE
Quiescent Current Per
Package
I
5.0 Control Inputs: V
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µA
DD
in =
10
15
V
or V
,
SS
DD
Switch I/O: V v V
EE
I/O
v V , and ∆V
DD
switch
(5.)
v 500 mV
Total Supply Current
(Dynamic Plus
Quiescent, Per Package)
I
5.0 T = 25_C only (The
µA
D(AV)
A
(0.07 µA/kHz) f + I
DD
10
15
channel component,
(V – V )/R , is
in out on
Typical (0.20 µA/kHz) f + I
(0.36 µA/kHz) f + I
DD
DD
not included.)
CONTROL INPUT (Voltages Referenced to V
)
SS
Low–Level Input Voltage
V
5.0
10
15
R
= per spec,
on
= per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
V
IL
IH
in
I
off
High–Level Input Voltage
V
5.0
10
15
R
= per spec,
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
on
I
off
= per spec
Input Leakage Current
Input Capacitance
I
15
—
V
in
= 0 or V
—
—
±0.1
—
—
±0.00001 ±0.1
—
—
±1.0
µA
DD
C
—
5.0
7.5
—
pF
in
SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to V
)
EE
Recommended Peak–to–
Peak Voltage Into or Out
of the Switch
V
—
—
—
Channel On or Off
0
0
V
0
—
V
0
0
V
V
p–p
I/O
DD
DD
DD
Recommended Static or
∆V
Channel On
600
0
—
600
300
—
mV
switch
Dynamic Voltage Across
(5.)
the Switch
(Figure 3)
Output Offset Voltage
ON Resistance
V
OO
V
in
= 0 V, No Load
—
—
—
10
—
—
µV
(5.)
R
5.0 ∆V
10
15
v 500 mV
V = V or V
in IL IH
,
—
—
800
400
220
—
—
—
250
120
80
1050
500
280
—
—
—
1200
520
300
Ω
on
switch
(Control), and V
=
in
0 to V (Switch)
DD
∆ON Resistance Between
Any Two Channels
in the Same Package
∆R
5.0
10
15
—
—
—
70
50
45
—
—
—
25
10
10
70
50
45
—
—
—
135
95
65
Ω
on
Off–Channel Leakage
Current (Figure 8)
I
off
15
V
in
= V or V
IH
—
±100
—
±0.05
±100
—
±1000
nA
IL
(Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O
C
C
C
—
—
Switch Off
—
—
—
—
—
—
10
17
—
—
—
—
—
—
pF
pF
pF
I/O
O/I
I/O
Capacitance, Common O/I
Capacitance, Feedthrough
(Channel Off)
—
—
Pins Not Adjacent
Pins Adjacent
—
—
—
—
—
—
0.15
0.47
—
—
—
—
—
—
4. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
5. For voltage drops across the switch (∆V ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn; i.e. the
switch
DD
current out of the switch may contain both V
and switch input components. The reliability of the device will be unaffected unless the
DD
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
MC14551B
ELECTRICAL CHARACTERISTICS (C = 50 pF, T = 25_C, V v V
)
L
A
EE
SS
V
– V
EE
DD
(6.)
Vdc
Characteristic
Propagation Delay Times
Symbol
, t
Min
Typ
Max
Unit
t
ns
PLH PHL
Switch Input to Switch Output (R = 10 kΩ)
L
t
t
t
, t
= (0.17 ns/pF) C + 26.5 ns
5.0
10
15
—
—
—
35
15
12
90
40
30
PLH PHL
L
, t
= (0.08 ns/pF) C + 11 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 9.0 ns
L
PLH PHL
Control Input to Output (R = 10 kΩ)
t
, t
ns
L
PLH PHL
V
EE
= V (Figure 4)
5.0
10
15
—
—
—
350
140
100
875
350
250
SS
Second Harmonic Distortion
—
10
—
0.07
—
%
R = 10 kΩ, f = 1 kHz, V = 5 V
L
in
p–p
Bandwidth (Figure 5)
BW
10
—
17
—
MHz
R = 1 kΩ, V = 1/2 (V – V
)
,
L
in
DD
EE p–p
20 Log (V /V ) = – 3 dB, C = 50 pF
out in
L
Off Channel Feedthrough Attenuation, Figure 5
—
—
—
10
10
10
—
—
—
– 50
– 50
75
—
—
—
dB
dB
R = 1 kΩ, V = 1/2 (V – V )
EE p–p
,
L
in
DD
f
in
= 55 MHz
Channel Separation (Figure 6)
R = 1 kΩ, V = 1/2 (V – V )
EE p–p
,
L
in
DD
f
in
= 3 MHz
Crosstalk, Control Input to Common O/I, Figure 7
R1 = 1 kΩ, R = 10 kΩ,
mV
L
Control t = t = 20 ns
r
f
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14551B
V
DD
V
DD
V
DD
IN/OUT
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
V
EE
Figure 1. Switch Circuit Schematic
16
V
DD
CONTROLă9
LEVEL
CONVERTER
CONTROL
8
V
SS
7
V
EE
W0ă15
W1ăă1
14ăW
4ăăX
X0ăă2
X1ăă3
Y0ăă6
Y1ă10
5ăăY
13ăZ
Z0ă11
Z1ă12
Figure 2. MC14551B Functional Diagram
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5
MC14551B
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
PULSE
GENERATOR
CONTROL
V
out
LOAD
V
R
L
C
L
SOURCE
V V
DD EE
V V
EE DD
Figure 3. ∆V Across Switch
Figure 4. Propagation Delay Times,
Control to Output
Control input used to turn ON or OFF
the switch under test.
R
L
ON
CONTROL
V
out
CONTROL
OFF
R
L
C = 50 pF
L
V
out
R
L
C = 50 pF
L
V
in
V
in
V
DD
- V
2
V
DD
- V
2
EE
EE
Figure 5. Bandwidth and Off–Channel
Feedthrough Attenuation
Figure 6. Channel Separation
(Adjacent Channels Used for Setup)
OFF CHANNEL UNDER TEST
V
DD
EE
V
CONTROL
SECTION
OF IC
OTHER
CHANNEL(S)
CONTROL
V
out
V
V
EE
R
L
C = 50 pF
L
DD
R1
V
V
EE
DD
Figure 7. Crosstalk, Control Input
to Common O/I
Figure 8. Off Channel Leakage
V
DD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kΩ
RANGE
X/Y
PLOTTER
V
DD
V
EE
= V
SS
Figure 9. Channel Resistance (RON) Test Circuit
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6
MC14551B
TYPICAL RESISTANCE CHARACTERISTICS
350
300
350
300
250
200
150
100
250
200
150
T = 125°C
A
T = 125°C
A
100
25°C
-ā55°C
25°C
-ā55°C
50
0
50
0
-ā10 -ā8.0 -ā6.0 -ā4.0 -ā2.0
0
2.0 4.0
6.0 8.0
10
-ā10 -ā8.0 -ā6.0 -ā4.0 -ā2.0
0
2.0 4.0 6.0 8.0 10
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V
Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V
700
600
350
300
T = 25°C
A
V
DD
= 2.5 V
500
400
300
200
250
200
150
100
5.0 V
T = 125°C
A
7.5 V
25°C
100
0
-ā55°C
50
0
-ā10 -ā8.0 -ā6.0 -ā4.0 -ā2.0
0
2.0 4.0
6.0 8.0
10
-ā10 -ā8.0 -ā6.0 -ā4.0 -ā2.0
0
2.0 4.0 6.0 8.0 10
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V
Figure 13. Comparison at 25_C, VDD @ – VEE
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7
MC14551B
APPLICATIONS INFORMATION
Figure A illustrates use of the on–chip level converter
detailed in Figure 2. The 0–to–5 volt Digital Control signal
margin at each peak. If voltage transients above V and/or
DD
below V are anticipated on the analog channels, external
EE
is used to directly control a 9 V analog signal.
diodes (D ) are recommended as shown in Figure B. These
p–p
x
The digital control logic levels are determined by V
diodes should be small signal types able to absorb the
maximum anticipated current surges during clipping.
The absolute maximum potential difference between
DD
and V . The V voltage is the logic high voltage; the V
SS
DD
SS
voltage is logic low. For the example, V = + 5 V = logic
DD
high at the control inputs; V = GND = 0 V = logic low.
V
and V is 18.0 volts. Most parameters are specified
DD EE
SS
The maximum analog signal level is determined by V
up to 15 volts which is the recommended maximum
difference between V and V
DD
and V . The V
voltage determines the maximum
.
EE
EE
DD
DD
recommended peak above
V
.
SS
The
V
voltage
Balanced supplies are not required. However, V must
EE
SS
determines the maximum swing below V . For the
be greater than or equal to V . For example, V
=
DD
SS
EE
example, V – V = 5 volt maximum swing above V
;
SS
+ 10 volts, V = + 5 volts, and V = – 3 volts is acceptable.
DD
SS
SS EE
V
SS
– V = 5 volt maximum swing below V . The
See the table below.
EE
SS
example shows a ± 4.5 volt signal which allows a 1/2 volt
+5 V
-5 V
V
DD
V
SS
V
EE
+4.5 V
9 V
p-p
+5 V
SWITCH
I/O
ANALOG SIGNAL
9 V
p-p
COMMON
O/I
GND
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
MC14551B
CONTROL
0-TO-5 V DIGITAL
CONTROL SIGNAL
-4.5 V
CIRCUITRY
Figure A. Application Example
V
DD
V
DD
D
D
D
D
x
x
SWITCH
I/O
COMMON
O/I
x
x
V
EE
V
EE
Figure B. External Schottky or Germanium Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS
Control Inputs
Logic High/Logic Low
In Volts
V
V
V
EE
In Volts
Maximum Analog Signal Range
In Volts
DD
SS
In Volts
In Volts
+ 8
0
0
0
0
– 8
+ 8/0
+ 5/0
+ 8 to – 8 = 16 V
p–p
+ 5
– 12
0
+ 5 to – 12 = 17 V
p–p
+ 5
+ 5/0
+ 5 to 0 = 5 V
p–p
+ 5
– 5
+ 5/0
+ 5 to – 5 = 10 V
+ 10 to – 5 = 15 V
p–p
+ 10
– 5
+ 10/ + 5
p–p
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8
MC14551B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
–T–
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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9
MC14551B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
R X 45
K
_
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
C
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
7
0
_
_
_
_
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
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10
MC14551B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE O
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
16
9
L
E
Q
1
H
E
M
_
ąă4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
ąă5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
---
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
---
0.05
0.35
0.18
9.90
5.10
2.05
A
1
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
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http://onsemi.com
11
MC14551B
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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MC14551B/D
相关型号：
MC14551BFEL
Single-Ended Multiplexer, 4 Func, 2 Channel, CMOS, PDSO16, EIAJ, PLASTIC, SOIC-16
ROCHESTER
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