MC33389ADHR2 [NXP]
DATACOM, INTERFACE CIRCUIT, PDSO20, POWER, HSOP-20;
| 型号： | MC33389ADHR2 |
| 厂家： | 
NXP |
| 描述： | DATACOM, INTERFACE CIRCUIT, PDSO20, POWER, HSOP-20 电信 光电二极管 电信集成电路 |
| 文件： | 总35页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order Number: MC33389/D
Rev 3.5, March 17th, 03
MOTOROLAFreescale Semiconductor, Inc.
Semiconductor Technical Data
Advance Information
MC33389
System Basis Chip with Low
Speed Fault Tolerant CAN
AUTOMOTIVE SBC
SYSTEM BASIS CHIP
The MC33389 is a monolithic integrated circuit combining many functions
frequently used by automotive ECUs. It incorporates a low speed fault tolerant
CAN transceiver.
SILICON MONOLITHIC
INTEGRATED CIRCUIT
PIN CONNECTIONS
• Dual Low Drop Voltage Regulators, with Respectively 100mA and 200mA
Current Capabilities, Current Limitation and Over Temperature Detection with
Prewarning
DH SUFFIX
POWER PACKAGE
CASE 979C
• 5V Output Voltage for V1 Regulator
• Three Operational Modes (Normal, Standby and Sleep Mode) Separated
from the CAN Interface Operating Modes
HSOP-20
• Low Speed 125kBaud Fault Tolerant CAN Interface, Compatible with
MC33388 Standalone Physical Interface
TX
V1
1
2
20
V3
• V1 Regulator Monitoring and Reset Function
19
VBAT
18
RX
3
• Three External High Voltage Wake-up Inputs, Associated with V3 Vbat Switch
• 100mA Output Current Capability for V3 Vbat Switch Allowing Drive of
External Switches or Relays
RTL
V2
RSTB
INTB
MISO
MOSI
SCK
CSB
L2
4
17
16
5
CANH
GND
CANL
RTH
L0
6
5
1
• Low Standby and Sleep Current Consumption
• Vbat Monitoring and Vbat Failure Detection Capabilities
• DC Operating Voltage up to 27V
7
14
3
1
8
9
12
11
• 40V Maximum Transient Voltage
10
L1
• Programmable Software Window Watchog and Reset
• Wake up Capabilities (CAN Interface, Local Programmable Cyclic Wake up)
• Interface with MCU through SPI
DW SUFFIX
PLASTIC PACKAGE
CASE 751F
• Programmable Interupt Function
SO-28
1
2
3
4
5
6
7
8
9
V3
28
TX
27
26
25
24
VBAT
V1
RX
RTL
RSTB
V2
Simplified Block Diagram
CANH
INTB
GND
GND
GND
GND
3
2
GND
GND
2 2
21
20
19
Dual Voltage Regulator
VBAT
GND
GND
CANL
V2
(+12V)
Voltage control
5V
MISO 10
max 200mA
max 110mA
Bat fail detect
MOSI
SCK
CSB
L2
11
12
13
18 RTH
17 NC
VCC monitor
5V
VBAT switch supply
Mode control
V1
L0
16
L1
4
1
5
1
ORDERING INFORMATION
Operating
I3 max. 100mA
Interrupt control
Reset control
Device and version
Package
INT
Temperature Range
V3
(Switch supply)
Reset
MC33389ADW (1) T = -40 to 125°C SO-28
Watchdog & oscillator
A
T = -40 to 125°C
HSOP20
SO-28
MC33389ADH (1)
MC33389CDW (2)
MC33389CDH (2)
MC33389DDW (3)
A
MOSI
SCK
T = -40 to 125°C
A
SPI Interface
T = -40 to 125°C
A
MISO
HSOP20
SO-28
CSB
T = -40 to 125°C
A
L0
L1
L2
Programmable
wake-up inputs
(1) Version A: If device remains in reset greater than 100ms due
to V1 undervoltage, device switches to sleep mode to minimise
current consumption. Wake-up configuration active.
Wake-up
Gnd
inputs
(2) Version C: In V1 undervoltage condition, device remains in
permanent reset state until V1 returns to nominal conditions. V1
protected by overcurrent and over temperature functions.
CAN H
Fault tolerant
CAN
R1
Rth
TX
RX
Rtl
(3) Version D: In V1 undervoltage condition, device remains in
permanent reset state until V1 returns to nominal conditions. V1
protected by overcurrent and over temperature functions.
Change of undervoltage reset threshold. Refer to electrical pa-
rameter table, V1 PIn 5V.
R2
transceiver
CAN L
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right to change or discontinue this product without notice.
© Motorola, Inc., 2002. All rights reserved.
Freescale SMeCm33i3c89onductor, Inc.
MAXIMUM RATINGS
Description
Symbol
Min
Typ
Max
27
Unit
V
Test Conditions
DC Voltage at Pin Vbat
Transient Voltage at Pin Vbat
DC Voltage at Pins CANH CANL
Vbat
-0.3
40
V
t<500ms (Load Dump)
-20
-40
27
V
Transient Voltage at Pins
CANH CANL
0<V2<5.5, Vbat>0,
t<500ms
40
V
V
With 100Ω Termination
Resistors. Coupled
Through 1nF (note1)
Coupled Transient Voltage at Pins
CANH CANL
-100
100
DC Voltage at Pins V1 V2
-0.3
-20
6
V
DC Current at output pins: RX,
MISO, RSTB, INTB
20
mA
DC Voltage at input pins TX, MOSI,
SCLK, CSB, RSTB
-0.3
6
V
DC Voltage at Pins L0, L1, L2
Current at Pins L0, L1, L2
Transient Current at Pin V3
DC Voltage at Pins RTH, RTL
-0.3
-15
-30
-0.3
40
V
0<Vbat<40V
mA
mA
V
20
40
ESD Voltage on any Pin
(HBM 100pF, 1.5K)
-2
-2
2
2
kV
kV
V
ESD Voltage on
L0, L1, L2, CANH, CANL, Vbat
ESD Voltage on any Pin
-150
150
(MM 200pF, 0Ω).
Junction Temperature
Tj
Tjt
Ts
-40
-40
-65
500
150
160
150
16k
°C
°C
°C
Ω
Junction Temperature
Storage Temperature
RTH, RTL Termination Resistance
Junction to Heatsink Thermal
Resistance for HSOP20
33% Power on V1, 66% on
V2 (Including CAN), Note 2
3.1
17
K/W
K/W
Junction to Pin Thermal
Resistance for SO28WB
Note 2, Note 3
NOTE 1: Pulses 1, 2, 3a, 3b according to ISO7637.
NOTE 2: Refer to thermal management in device description section.
NOTE 3: pins 6,7,8,9,20,21,22,23 of SO28WB package
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ELECTRICAL PARAMETERS Vbat=5.5V to 18V, -40°< Tj < 150°C, unless otherwise specified
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Vbat PIN
Nominal Vbat Operating Range
Functional Vbat Operating Range
Vbat Threshold for BatFail Flag
5.5
5.5
2
18
27
4
V
V
V
BatFail
Tfail
0<V1<5,1V
V
bat<BatFail, measured
Delay for Signalling BatFail
150
400
µs
from Vbat low to INT active
Overvoltage Vbat Threshold
BAThigh
Thigh
18
4
20
18
22
50
V
Delay for Setting BAThigh Flag
µs
Vbat>BatHigh
Forced Wake-up and Cyclic
Sense Disabled
Supply Current in Sleep Mode
Supply Current in Sleep Mode
Supply current in sleep mode
Supply Current in Sleep Mode
Isleep1
Isleep2
Isleep3
Isleep4
75
125
210
155
250
µA
µA
µA
Vbat=12V,Tj = 25°C to150°C
Forced Wake-up and Cyclic
Sense Disabled
Vbat=12V, Tj = -40°C to 25°C
Forced Wake-up or Cyclic
Sense Enabled. Vbat=12V, Tj =
25°C to 150°C
105
Forced Wake-up or Cyclic
Sense Enabled
Vbat12V, Tj -40 to 25°C,
Forced Wake-up or Cyclic
Sense Enabled. Vbat 6V to 16V,
Tj -40 to 150°C
Supply Current in Sleep Mode
Supply Current in Standby Mode
Supply Current in Normal Mode
Isleep5
300
1
Istb2
0.5
3.5
mA
mA
Normal Mode with
I(V1)=I(V2)=0
Inrec
7
Bus in Recessive State
V1 PIN 5V
0mA<Iout<100mA
5.5V<Vbat<27V
Output Voltage
V1nom
V1
4.85
4.8
5
5
5.15
5.2
V
V
I
out=<100mA
Output Voltage
27V<Vbat<40V
Iout=100mA (Note 4)
V1nom-100mV
Drop Voltage
V1drop
I1max
TV1h
0.35
170
0.5
200
190
160
40
V
mA
°C
°C
°C
Output Current Limitation
V1 Overtemp Shut-off Threshold
V1 Pre-warning Temp Threshold
Temperature Threholds Difference
130
160
130
20
Junction Temperature
Junction Temperature
TV1l
TV1 -TV1
h
l
Reset Threshold on V1 (A and C
versions)
Vr1
4.1
4.3
4.8
V
5.5V<Vbat<27V
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Parameter
Reset Threshold on V1 (D version)
Reset Active V1 Range
Reset Delay Time
Symbol
Min
V1-0.4
1
Typ
V1-0.28
Vr1
Max
Unit
Test Conditions
Vr1
V1-0.1
V
5.5V<Vbat<27V
V1r
V
td
2
20
µs
Line Regulation
-15
-50
-50
2
+15
+50
+50
mV
mV
mV
9V<Vbat<16.5,Iload=10mA
5.5V<Vbat<27V,Iload=10mA
1mA<Iload<100mA
Line Regulation
10
Load Regulation
100Hz, 1Vpp on Vbat=12V,
Iload=100mA, guaranteed by
design
Line Ripple Rejection
30
55
27
dB
mV
mV
Vbat from 12V to 40V in
Line Transient Response
Load Transient Response
1µs,(10µF, ESR=3Ω)
I
load from 10µA to 100mA in
1µs (Cload=10µF esr=3Ω)
(Note 5)
400
16
Iload from 10µA to 100mA in
1µs (Cload=10µF esr=0.1Ω)
Load Transient Response
mV
mA
Reverse Current From V1 to Vbat and Gnd
IRev
1
V1=4.9V, 0<Vbat<4.9 V
NOTE 4: Measured when V1 has dropped 100mV below its nominal value.
NOTE 5: This condition does not produce reset.
V2 PIN
0mA<Iout<200mA
5.5V<Vbat<40V
Output Voltage
V2nom
4.75
5
5.25
V
Drop Voltage
V2drop
V2drop
I1max
Vr2
0.2
0.05
280
4.55
0.5
0.15
350
4.75
70
V
V
Iout=200mA (Note 6)
Iout=20mA (Note 6)
V2nom-100mV
Drop Voltage
Output Current Limitation
Threshold on V2 to Report V2 off
220
4.1
20
mA
V
V2 Nominal
Vr2 Delay Time
µs
°C
°C
mV
mV
V2 Overtemp Pre-warning Threshold
V2 Overtemp Switch-off Threshold
Line Regulation
TV2l
130
155
-15
-75
160
185
+15
+75
V2 Junction Temperature
V2 Junction Temperature
9V<Vbat<16.5
TV2h
Load Regulation
4mA<Iload<200mA
100Hz, 1Vpp on Vbat, guar-
anteed by design
Line Ripple Rejection
30
-3
55
dB
%
Percentage Difference V2-V1
3
V
bat>9V, IV1=20mA,
IV2=40mA
NOTE 6: Measured when V2 has dropped 100mV below its nominal value.
V3 PIN
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Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
High Level Voltage Drop
V3drop
0.4
1
V
IV3=-50mA, 9V<Vbat<40V
High Level Voltage Drop
V3 Output Current Limitation
V3 Leakage Current
V3drop
I3lim
1.5
250
15
V
mA
µA
°C
V
IV3=50mA, 6V<Vbat<9V
5.5V<Vbat<27V
100
15
I3leak
TV3
V3=0 (V3 off)
V3 Overtemp Detection
155
0.3
185
0.5
Junction Temperature
V3 voltage with -30mA (negative
current for Relay Switch off)
VV3
For t≤100ms, no
Functional Error Allowed
CAN TRANSCEIVER
V2 for Forced BusStandby Mode
(Fail Safe)
Vrc2
3
3.9
4.7
V
CANH, CANL Pins
Differential Receiver, Threshold Voltage
-3.2
-3.2
-2.5
-2.5
0.2
V
V
Differential Receiver, Dominant to
Recessive Threshold
(Bus failures 1, 2, 5)
CANH Recessive Output Voltage
CANL Recessive Output Voltage
Vcanh
Vcanl
V
V
TX=high, R(RTH)<4k
TX=high, R(RTL)<4k
V2-0.2
V2-1.4
TX=0V ; BusNormal Mode,
Icanh= -40mA
CANH Output Voltage, Dominant
CANL Output Voltage, Dominant
Vcanh
V
V
TX=0V ; BusNormal Mode,
Vcanl
1.4
I
canl=40mA
CANH Output Current Limit
CANL Output Current Limit
Icanh
Icanl
50
50
75
95
100
130
mA
mA
(Vcanh=0, TX=0)
(Vcanl=14V, TX=0)
Detection Threshold
VcanhVcanl
7.3
7.9
8.9
V
BusNormal Mode
BusStandby Mode
for Short-circuit to Battery Voltage
Detection Threshold
Vcanh
Vbat/2+3
Vbat/2+5
V
for Short-circuit to Battery Voltage
CANH Output Current, Failure3
CANL Output Current, Failure4
5
0
10
2
µA
µA
BusStandby Mode Vcanh=12V
BusStandby Mode,
Vcanl=0V, Vbat=12V
CANL Wake up Voltage Threshold
CANH Wake up Voltage Threshold
Wake up Threshold Difference
VwakeL
VwakeH
2.5
1.2
0.2
3.3
2
3.9
2.7
V
V
V
BusStandby Mode
BusStandby Mode
V
-V
wakeL wakeH
CANH Single Ended
Receiver Threshold
Vcanh
1.5
1.85
2.15
V
Failures 4,6,7
CANL Single Ended
Receiver Threshold
Vcanl
2.8
45
3.05
75
3.4
90
V
Failures 3,8
CANL Pull up Current
Icanlpu
µA
BusNormal Mode
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Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
CANH Pull Down Current
Icanlpd
45
75
90
µA
BusNormal Mode
Receiver Differential Input
Impedance CANH / CANL
Rdiff
100
-8
180
8
kΩ
Differential Receiver Common
Mode Voltage Range
Vcom
V
RTH, RTL Pins
I
out<-10mA, BusNormal
RTL to V2 Switch on Resistance
Rrtl
10
8
25
70
Ω
Operating Mode
RTL to BAT Switch Series Resistance
RTH to Ground Switch on Resistance
THERMAL SHUTDOWN
Rrtl
12.5
25
20
70
kΩ
BusStandby Mode
Rrth
Ω
Iout<10mA, All Mode
Shutdown Temperature
Tsd
165
°C
AC CHARACTERISTICS
CANL and CANH Slew Rates, Ris-
ing or Falling Edges, Tx from
Recessive to Dominant State
C
load=10nF, 133Ω
3.5
2
5
10
10
V/µs
V/µs
Termination Resistors
CANL and CANH Slew Rates, Ris-
ing or Falling Edges, Tx from Domi-
nant to Recessive State
Cload=10nF, 133Ω
3.5
Termination Resistors
Cload=10nF, 133Ω
Propagation Delay TX to RX Low
Propagation Delay TX to RX High
Tdh
Tdl
1.2
2
2
3
µs
µs
µs
Termination Resistors
C
load=10nF, 133Ω
Termination Resistors
Min. Dominant Time for Wake-up
on CANL or CANH
BusStandby Mode,
Vbat=12V
Twake
4
40
Failure 3 Detection Time
10
10
60
60
µs
µs
BusNormal Mode
BusNormal Mode
BusNormal Mode
BusNormal Mode
BusNormal Mode
BusNormal Mode
Failure 3 Recovery Time
Failure 6 Detection Time
50
400
1000
4
µs
Failure 6 Recovery Time
150
0.75
10
µs
Failure 4, 7, 8 Detection Time
Failure 4, 7, 8 Recovery Time
Failure 3, 4, 7 Detection Time
Failure 3, 4, 7 Recovery Time
ms
µs
60
0.8
8
ms
ms
BusStandby Mode, Vbat=12V
BusStandby Mode,Vbat=12V
2.5
3
Edge Count Difference Between
CANH and CANL for
BusNormal Mode
BusNormal Mode
Failures 1, 2, 5 Detection
Edge Count Difference Between
CANH and CANL for
3
Failures 1, 2, 5 Recovery
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Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
TX Permanent Dominant
Timer Disable Time
BusNormal Mode and
Failure Mode
Ttxd
0.75
4
ms
TX, MOSI, SCK, CSB
High Level Input Voltage
0.7V1
V1+0.3V
SBC in Sleep Mode,
V1<1.5V
CSB Threshold for SPI Wake-up
2.2
V
CSB Filter Time for SPI Wake-up
Low Level Input Voltage
High Level Input Current on CSB
Low Level Input Current (CSB)
TX High Level Input Current
TX Low Level Input Current
SI, SCK Input Current
3
0.3 V1
-20
µs
V
SBC in Sleep Mode, V1<1V
-0.3
-100
-100
-200
-800
-10
µA
µA
µA
µA
µA
Vi=4V
Vi=1V
-20
ITX
ITX
-80
-25
Vi=4V
-320
-100
10
Vi=1V
0<VIN<V1
RX, INTB, MISO
High Level Output Voltage
Low Level Output Voltage
Tristated SO Output Current
RSTB Pin
Voh
Vol
Iz
V1-0.9
V1
0.9
+2
V
V
I0=-250µA
I0=1.5mA
0
-2
µA
0V<Vso<V1
High Level Input Voltage
Low Level Input Voltage
High Level Output current 1
High Level Output current 2
Low Level Output Voltage (I0=1.5mA)
Reset Duration after V1High
L0, L1, L2 WAKE-UP INPUTS
Positive Switching Threshold
Negative Switching Threshold
Hysteresis
Vih
Vil
0.7V1
-0.3
V1+0.3V
0.3V1
-10
V
-50
-30
µA
µA
V
0<Vout<0.5V1
0.5<Vout<V1
1v<Vbat<27V
-300
0
0.9
tres
1
ms
Vwup
Vwun
Vhyst
3
3.7
3
4.5
3.8
V
V
6V<Vbat<16V
6V<Vbat<16V
6V<Vbat<16V
2.5
700
mV
µA
µs
µA
Leakage Current 0<Vwu<Vbat
Wake up Filter Time
-5
8
+5
38
20
Lx input current @ 40V
Vin
350
600
DIGITAL INTERFACE TIMING
SCLK Clock Period
tpSCLK
500
ns
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Parameter
SCLK Clock High Time
SCLK Clock Low Time
Symbol
twSCLKH
twSCLKL
Min
175
175
Typ
Max
Unit
Test Conditions
ns
ns
Falling Edge of CSB to Rising
Edge of SCLK
tlead
250
250
50
50
ns
ns
Falling Edge of SCLK to Rising
Edge of CSB
tlead
SI to Falling Edge of SCLK
Falling Edge of SCLK to SI
SO Rise Time (CL = 220pF)
SO Fall Time (CL = 220pF)
tSISU
tSI(hold)
trSO
125
125
25
25
25
25
ns
ns
ns
ns
75
75
tfSO
SI, CSB, SCLK Incoming
Signal Rise Time
trSI
200
200
ns
SI, CSB, SCLK Incoming
Signal Fall Time
tfSI
Time from Falling Edge of CSB to SO
Low Impedance
tSO(en)
tSO(dis)
200
200
ns
High Impedance
Time from Rising Edge of
SCLK to SO Data Valid
0.2 V1 or V2≤SO≥ 0.8V1 or
tvalid
50
125
V2, CL=200pF
SOFTWARE WATCHDOG TIMINGS
(note 1: software watchdog timing accuracy are based on the running mode oscillator tolerance)
normal request, normal and
standby modes. (Note 1)
Running mode oscillator tolerance
-12
+12
%
Software Watchdog Timing 1
Software Watchdog Timing 2
Software Watchdog Timing 3
Software Watchdog Timing 4
Software Watchdog Timing 5
Software Watchdog Timing 6
Software Watchdog Timing 7
Software Watchdog Timing 8
SWt1
SWt2
SWt3
SWt4
SWt5
SWt6
SWt7
SWt8
4.4
8.8
17.6
28
5
5.6
11.2
22.4
36
ms
ms
ms
ms
ms
ms
ms
ms
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
10
20
32
44.8
65
51
58
74
83
88
100
202
112
226
178
FORCED WAKE-UP AND CYCLIC SENSE TIMINGS
(note 2: cyclic sense and forced wake up timing accuracy are based on the sleep mode oscillator tolerance)
Sleep mode oscillator tolerance
Cyclic Sense / FWU timing 1
Cyclic Sense / FWU timing 2
Cyclic Sense / FWU timing 3
-30
+30
41.6
83.2
166.4
%
sleep mode (Note 2)
sleep mode (Note 2)
sleep mode (Note 2)
sleep mode (Note 2)
CYt1
CYt2
CYt3
22.4
44.8
89.6
32
64
ms
ms
ms
128
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Parameter
Symbol
Min
Typ
Max
Unit
ms
ms
ms
ms
ms
Test Conditions
sleep mode (Note 2)
sleep mode (Note 2)
sleep mode (Note 2)
sleep mode (Note 2)
sleep mode (Note 2)
Cyclic Sense / FWU timing 4
Cyclic Sense / FWU timing 5
Cyclic Sense / FWU timing 6
Cyclic Sense / FWU timing 7
Cyclic Sense / FWU timing 8
GND SHIFT DETECTION
CYt4
179
256
333
CYt5
358
512
665
CYt6
717
1024
2048
8192
1331
2662
10650
CYt7
1434
5734
CYt8
(note 3: no over lap between two adjacent thresholds).
CAN Transceiver Active In
Two-wire Operation
Ground Shift Threshold 1 (Note 3)
Ground Shift Threshold 2 (Note 3)
Ground Shift Threshold 3 (Note 3)
Ground Shift Threshold 4 (Note 3)
GS1
-1
-1.5
-2
-0.7
-1.2
-1.7
-2.2
-0.3
-0.8
-1.3
-1.7
V
V
V
V
CAN Transceiver Active In
Two-wire Operation
GS2
GS3
GS4
CAN Transceiver Active In
Two-wire Operation
CAN Transceiver Active In
Two-wire Operation
-2.6
Figure 1. Input Timing Switch Characteristics
CSB
t
t
t
t
t
lag
lead
wSCLKH
r
f
SCLK
t
wSCLKL
t
SISU
t
SI(hold)
SI
Don’t Care
Valid
Don’t Care
Valid
Don’t Care
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DEVICE DESCRIPTION
Thermal Management
SO28WB Package
The MC33389 is proposed in two different packages.
HSOP20 for high power applications and SO28WB with 8 pins
to the leadframe for medium power applications.
The case(pin) to junction Rth is here represented by only
one thermal resistance for the total power since the 3 power
sources strongly interact on the silicon for such a package.
HSOP20 Package
Figure 3. SO28WB Simplified Thermal Model
For such a package, the heat flow is mainly vertical and
each heat source (dissipating element) can be seen as an
independent thermal resistance to the Heatsink. The thermal
network can be roughly depicted as:
Total power
Tj (max 155°C)
Rthj/c=20°C/W
Figure 2. HSOP20 Simplified Thermal Model
V2 power
Can power
V1 power
Tj (max 155°C)
Rthj/c=18°C/W
Tcase(pin)
9°C/W
6.5°C/W
Rthc/a
Tcase(heatsink)
Rthc/a (ECU supplier dependent)
Tambient
Tambient
Example
Assuming IV1=45mA at Vbat=16V,
IV2=45mA at Vbat=16V (Excluding CAN consumption).
ICAN=50mA at Vbat=16V, we have :
PV1=0.5W, PV2=0.5W, Pcan=0.55W thus Ptotal=1.55W
Example
Assuming IV1=100mA at Vbat=16V,
IV2=150mA at Vbat=16V (Excluding CAN consumption).
ICAN=50mA at Vbat=16V, we have :
System assumptions:
PV1=1.1W, PV2=1.65W, Pcan=0.55W
If Tamb=85°C and Rthc/a=25°C/W, this gives:
Tcase=Tamb+Rthc/a x 1.55W=85+25x1.55 =124°C
and TjV1=124 + 20 x 1.55= 155°C.
System assumptions:
If Tamb=85°C and Rthc/a=18°C/W, this gives:
Tcase=Tamb+Rth c/a x 3.3W = 85+18 x 3.3=145°C
and TjV1=TjV2=Tjcan=155°C.
This example represents the limit for the maximum power
dissipations with a SO28WB.
This example represents the limit for the maximum power
dissipations with a HSOP20.
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MC33389
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DEVICE DESCRIPTION
Introduction
against short to ground (current limitation) and overtemperature.
The System Basis Chip is an integrated circuit dedicated
V2 is active in Normal mode.
to car body applications. It includes three main blocks :
- A dual voltage regulator
Undervoltage Detection
V2 is monitored for undervoltage and a flag is set in the
VSSR register.
- Reset, watchdog, wake up inputs, cyclic wake up
- CAN low speed fault tolerant physical interface
Overtemperature Protection
V2 internal ballast transistor is monitored for
overtemperature. Two detection thresholds are provided. A
pre-warning threshold at 140°C and a shut-off threshold at
165°C. Once the first threshold is reached, a flag is set in the
OTSR register which is readable. A maskable interrupt can be
sent to microcontroller.
Supplies
Two low drop regulators and one switch to Vbat are
provided to supply the ECU microcontroller or peripherals,
with independent control and monitoring through SPI.
Once the second threshold is reached, a flag is set in the
OTSR register, V2 is switched off. It can only be switched on
again via the SPI.
Voltage Regulator V1
V1 is a 5V, 3% low drop voltage regulator dedicated to the
microcontroller supply. It can deliver up to 100mA and is
totally protected against short to ground (current limitation)
and overtemperature. V1 is active in Normal request, Normal
and standby modes.
Table 5. V2 Control
Conditions For V2 On
Conditions For V2 Off
No forward parasitic diode exists from V1 to Vbat. This
Normal mode (via SPI) AND
Sleep mode, or standby
mode or NormalRequest or
emergency mode (via SPI)
means that, if Vbat voltage drops below V1, no high current
flowing from V1 to Vbat will discharge the capacitor connected
V2 below shut off
temperature threshold
to V1. Its stored energy will only be used to supply the
Shut-off temp.
microcontroller and gives time to save all relevant data.
threshold reached
V1 disabled
Undervoltage Reset
(for any reason)
V1 is monitored for undervoltage (power up, power down)
and a reset is provided at RSTB output for 1ms. This ensures
proper initialization of the microcontroller at power-on or after
supply is lost. On top of that, a flag is set in RSR register
readable via the SPI.
Switch V3
V3 is a 10Ω switch to Vbat, it can be used to supply
external contacts or relays. A great flexibility is given for the
different possible ways for its control. It is protected against
short to ground (current limitation).
Overtemperature Protection
Overtemperature Protection
V1 internal ballast transistor is monitored for
overtemperature. Two detection thresholds are provided. A
pre-warning threshold at 145°C and a shut-off threshold at
175°C. Once the first threshold is reached, a flag is set in the
OTSR register. A maskable interrupt can be sent to the
microcontroller. Once the second threshold is reached, a flag
is set in the OTSR register, a maskable interrupt is sent to the
microcontroller and V1 is switched off.
V3 output transistor is monitored for overtemperature.
Once the threshold is reached, a flag is set in the VSSR
register, V3 is switched off. It will be automatically switched on
once the junction temperature is back to the pre-warning
threshold.
Table 6. V3 Control
Conditions For V3 On
Conditions For V3 Off
Once the junction temperature is back to the pre-warning
threshold, V1 regulator it will be automatically switched on.
Permanently in Normal
Permanently in Normal
mode if configured via SPI
mode if configured
Permanently in Standby
NormalRequest mode
Table 4. V1 Control
mode if configured via SPI
In sleep mode, during
enable time of cyclic
sense if configured
Permanently in Standby
mode if configured
Conditions For V1 On
Conditions For V1 Off
NormalRequest mode
Sleep mode (via SPI)
(at V1 power on)
Permanently in sleep
mode if configured
In sleep mode, during
disable time of cyclic
sense if configured
Shut-off temperature
threshold reached
Normal mode (via SPI)
Standby mode
(via SPI)
No Vbat power supply
(cold start)
V1 below pre-warning
Emergency mode
Overtemp threshold reached
V1 disabled (for any reason)
V2 over temperature shutdown
temperature threshold
During Reset
Note: current capability of V1, V2 and V3 depends upon
the thermal management. Over temperature shutdown might
be reached and lead to turn off of V1, V2 and V3 for output
current below their max current capability.
Supply and Vbat Block
Vbat Monitoring
Voltage Regulator V2
Vbat is the main power supply coming from the Battery
voltage after an external protection diode (for reverse battery).
V2 is a 5V low drop voltage regulator dedicated to
peripherals supply. It can deliver up to 200mA and is protected
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DEVICE DESCRIPTION
Vbat is monitored for undervoltage and overvoltage. provides differential transmission capability, but will switch in
V
bat Undervoltage
error condition to single wire transmitter and/or receiver.
The rise and fall slopes are limited to reduce RFI. This
allows use of an unshielded twisted pair or a parallel pair of
wires for the bus. It supports transmission capability on either
bus wire if one of the bus wire is corrupted. The logic failure
detection automatically selects a suitable transmission mode.
In normal operation (no wiring failures), the differential bus
state is output to RX. The differential receiver inputs are
connected to CANH and CANL through integrated filters. The
filtered inputs signals are also used for the single wire
receivers. The CANH and CANL receivers have threshold
voltages that assure maximum noise margin in single wire
modes. In the RXOnly mode, the transmitter is disabled but
the receive part of the transceiver remains active. In this
mode, RX reports bus and TX activity (RX = TX or Bus
dominant). Failure detection and management is the same as
BusNormal mode.
Vbat is monitored for undervoltage, if it is below 4V the
BatFail flag is set in the VSSR register and a maskable
interrupt is sent to the microcontroller.
V
bat Overvoltage
When Vbat is > 20V, the BatHigh flag is set in the VSSR
register. A maskable interrupt is sent to the microcontroller.
No specific action is taken to reduce current consumption (to
limit power dissipation). This is to let the entire flexibility at the
microcontroller for decision.
CAN Transceiver
The device incorporates a low speed 125kBaud CAN
physical interface. Its electrical parameters for the CANL,
CANH, Rtl,Rth,RX and TX pins are identical to the MC33388,
standalone CAN physical interface.
The mode control for the CAN transceiver (normal, Vbat
standby, sleep, etc...) are selectable through the MC33389
SPI interface.
Failure Detector
The failure detector is active in RXTX and RXOnly
operation mode and detects the following single bus failures
and switches to an appropriate mode.
1- CANH wire interrupted
• Baud Rate up to 125kBit/s
• Supports unshielded bus wires
• Short-circuit proof to Battery and Ground in 12V powered
systems
2- CANL wire interrupted or shorted to 5V
3- CANH short-circuited to battery
• Supports single-wire transmission modes with Ground offset
voltages up to 1.5V
4- CANL short-circuited to ground
5- CANH short-circuited to ground
• Automatic switching to single wire mode in case of Bus failures
• Automatic reset to differential mode if bus failure is removed
• Low EMI due to built in slope control and signal symmetry.
• Fully integrated receiver filters
6- CANL short-circuited to battery
7- CANL mutually shorted to CANH
8- CANH to V2 (5V)
Note : Shorts-circuit failures are detected for 0 to 50Ω shorts.
• Thermally protected
• Bus lines protected against Automotive transients.
• Low Current BusStandby mode with wake-up capability
via the Bus.
The differential receiver (CANH-CANL) threshold is set at -
2.8V, this assures a proper reception in the normal operating
modes. In case of failures 1, 2 and 5 the on-going message is not
destroyed due to noise margin
• An unpowered node does not disturb the bus lines.
Figure 7. CAN Simplified Block Diagram
Failures 3 and 6 are detected by comparators respectively
connected to CANH and CANL. If the comparator threshold is
exceeded for a certain time, the reception is switched to single
wire mode. This time is needed to avoid false triggering by
external RF fields. Recovery from these failures is detected
automatically after a certain time-out (filtering).
VDD2
VDD2
VBAT
CAN
CAN
TX
RX
Protection
Transmitter
Drivers
Failures 4 and 7 initially result in a permanent dominant
level at RX. After a time out, the CANL driver and the RTL pin
are switched off, only a weak pull up at CANL remains.
Reception continues by switching to single wire mode through
CANH. When the failures 4 or 7 are removed, the recessive
bus levels are restored. If the differential voltage remains
below the recessive threshold for a certain time, reception and
transmission switch back to the differential mode.
Receiver
- Fail detect
- Receive mode
RTL
RTH
Termination
CAN Transceiver Register
SPI
If any of the 8 wiring failure occurs, a flag is set in the
TESRH and TESRL status registers. 8 different types of errors
are distinguished out of these 8 errors and are separately
stored in these register (See SPI Register Description Section
on page 21). A maskable interrupt is sent to the microcontroller. On
error recovery, the corresponding flag is reset after read-out
operation.
CAN transceiver simplified block diagramm
During all single wire transmissions, the EMC
performance (both immunity and emission) is worse than in
differential mode. Integrated receiver filters suppress any HF
noise induced into the bus wires. The cut-off frequency of
these filters is a compromise between propagation delay and
HF suppression. In single wire mode, low frequency noise can
not be distinguished from the wanted signal.
CAN Transceiver Description
The CAN transceiver is an interface between CAN
protocol controller and the physical bus. It is intended for low
speed applications up to 125kBit/s in passenger cars. It
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DEVICE DESCRIPTION
In the event of a permanent dominant TX state (for more
Full transmitting and receiving capabilities are enabled.
than 2ms) the output drivers are disabled. That assures the
operation of the complete system in case of a permanent
dominant TX state of one control unit. A defect control unit
autonomous go to RXOnly or TermVCC mode.
Full failure detection is enabled.
Note: Standard/RXTX and Extended/RXTX are equivalent.
RXOnly mode
The transmitter is disabled but the receive part of the
transceiver remains active. In this mode, RX reports bus and
TX activity (RX = TX or Bus dominant).
Low Power Modes
The transceiver provides a low power modes which can be
entered and exit by a SPI command. This is the BusStandby
mode with the lowest power consumption (for the
transceiver). CANL is biassed to the battery voltage via the
RTL output and the pull-up current source on CANL and pull-
down current source on CANH are disabled. Wake-up
requests are recognized by the transceiver, when a dominant
state is detected on either bus lines (Bus wake-up). On a Bus
wake-up request the SBC will activate the INTB output or, if it
is in sleep mode, switch to NormalRequest mode. This event
is stored in the WUISR status register.
Note: Standard/RXOnly and Extended/RXOnly are equivalent.
BusStandby Mode
This is the low power mode for the CAN transceiver. The
driver and receivers are disabled. Wake-up capability on both
bus lines as well as failure 3, 4, 7, 8 detection are enabled. In
bus standby mode RTL termination is set to Vbat
.
Global Power Save Concept
The SBC allows to minimize power consumption of the
ECU. Several operating modes are available to go to low
power consumption when the full activity is not required.
Several possibilities are provided to wake-up the ECU. This
allows to have peripherals or the microcontroller switched off
when no activity on the ECU is required.
To prevent false wake-up due to transients or RF fields,
wake-up threshold levels have to be maintained for a certain
time. In the transceiver low power mode, failure detection
circuit remains partly active to prevent increased power
consumption in cases of error 3, 4,7 and 8.
Two switchable independent supply voltages (V1 and V2)
are provided for optimum ECU power management.
Power On
After the Vbat supply is switched on, the SBC is in
NormalRequest mode. The corresponding mode for the CAN
transceiver is BusStandby.
Generalities
The SBC can be operated in four modes: Sleep, Standby,
Normal and Emergency mode. After reset, the MC33389 is
automatically initialised to a temporally mode, NormalRequest,
Waiting for microcontroller configuration.
The CAN transceiver is supplied by V2. As long as V2 is
below its undervoltage threshold, the transceiver is forced to
BusStandby mode (fail safe property).
Reset Mode
Protection
This mode is entered after SBC power up, or if an incorrect
Software W/D trigger occurs. The minimum duration for reset
mode is 1ms typical, and unless a V1 failure condition, the
SBC enters the NormalRequest mode after reset.
In case of V1 failure condition leading to V1 low (ex: short
to gnd), the SBC goes in reset mode. If V1 is still below reset
threshold after 100ms, the behavior depends upon the device
version A, C or D:
A current limiting circuit protects the transmitter output
stages against short-circuit to positive and negative battery
voltage. If the junction temperature exceeds a maximum
value, the transmitter output stages are disabled. Because the
transmitter is responsible for a part of the power dissipation,
this will result in a reduced power dissipation and hence a
lower chip temperature. All other parts of the transceiver will
remain operating. The CANH and CANL inputs are protected
against electrical transients which may occur in an automotive
environment.
- A version : will enter sleep mode.
- C and D versions: will stay in reset mode.
NormalRequest Mode
Consequence Of Failure Detections
S1 is the switch from RTH to Ground
S2 is the switch from RTL to V2 and
S3 is the switch from RTL to Vbat
This is the default mode after MC33389 reset. V1 is active,
V2 and V3 are passive. The SBC is not configured. The
default values are set in the registers. The SBC is waiting for
configuration data via the SPI.
For each failure type is given which switch is open and
which driver is disabled.
If no SPI data is received 75ms after the Reset is released,
then the SBC switches itself to sleep mode.
Failure 1 : nothing done
The data the SBC must receive to consider that the
microcontroller starts the configuration sequence is the SW
timing word (in SWCR register). Once received this SW timing
word, the watchdog timer becomes active. Then any other
control data can be sent from the microcontroller to SBC.
The watchdog is not active in NormalRequest mode
before the SW timing word is programmed into the SBC. In
this mode, neither V2 nor the CAN transmitter are active.
Failure 2 : nothing done
Failure3 : S1 open. Driver CANH is disabled
Failure4 : S2 and S3 open. Driver CANL is disabled
Failure5 : Nothing done
Failure6 : S2 and S3 open. Driver CANL disabled
Failure7: S2 and S3 open. Driver CANL disabled
Failure8: S1 open. CANH driver disabled
CAN Transceiver Modes
The CAN transceiver has its own functioning modes:
RXTX mode, TermVBAT/TermVCC mode, and RXOnly mode.
They are controlled by TCR register.
RXTX mode
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DEVICE DESCRIPTION
SBC MODES
Table 8. NormalRequest: V1 active, V2&V3 passive
Entering NormalRequest Leaving NormalRequest
When firstly receiving the
SBC reset just released
SW timing word, SBC
goes to Normal
SBC Sleep Mode
If time-out without receiving
SPI commands (75ms),
SBC goes to sleep
This is a low power consumption mode. V1 and V2 are
disabled. V3 can be permanently disabled or cyclically active.
Table 11. SBC Sleep Mode: V1 And V2 Are Passive, V3
Passive Or Cyclic.
SBC Normal Mode
In this mode, V1 and V2 are active, V3 can be set active or
passive via the SPI. Therefore, the whole ECU can be
operated. Normal mode is entered by a SWCR register
configuration in NormalRequest mode.
Entering Sleep Mode
Leaving Sleep Mode
If SW timing not configured
75ms after entering
CAN wake-up, going to
NormalRequest
NormalRequest mode
Table 9. SBC Normal Mode: V1 And V2 Are Active. V3 Is
Active Or Passive
If a wake-up is detected with
cyclic sense
By SPI command
Entering Normal Mode
Leaving Normal Mode
For MC33389ADW only: If
V1 is below V1 reset for
more than 100ms
If a wake-up is detected with
wake-up not connected to V3
(permanent sense)
By SPI command, going to
any other mode
By SPI command
Forced wake-up (See Forced
Wake up Section)
After SWCR register
configuration in
Watchdog time out, going
to NormalRequest after
activating Reset
NormalRequest mode
SPI wake-up (See Wake up
by SPI Section)
V1 undervoltage detection,
going to NormalRequest
mode after activating Reset
Emergency Mode
In case the microcontroller detects the ECU or the system
is not under control any more, it may decide to switch the SBC
to the Emergency mode. V1, V2, V3 will be passive and wake-
up are not detected. The only way to leave this mode is to
disconnect the ECU from the Battery voltage (BatFail
detection).
SBC Standby Mode
In this mode V1 is active, V2 is passive. V3 can be either
permanently active or permanently passive. This is a low
power mode with V1 active in order to have a fast reaction
time in case of any wake-up.
Table 12. SBC Emergency Mode: V1 And V2 V3 Are
Passive
For standby mode, the SBC monitors the SW. It means the
microcontroller runs and is monitored and must serve a
watchdog trigger.
Entering Emergency Mode Leaving Emergency Mode
SBC BatFail detection (Dis-
Table 10. Standby: V1 Active V2 Passive, V3 Active Or
Passive, Watchdog Is Active
By SPI command
connection of the Battery
voltage)
Entering Standby
Leaving Standby
Figure 13. Typical Behaviour At Power On
If SW time-out going to
NormalRequest after
microcontroller Reset
SPI SW
timing configuration
Normal
at t<75ms
By SPI command going to
any other mode
By SPI command
SPI go to Emergency
at t<75ms
V1 low
Reset
V1 on
ECU
connected
to battery
NormalRequest
Emergency
Sleep
V1 undervoltage detection,
going to NormalRequest
mode after activating Reset
(reset
released)
No SPI SW
External activation of the
RSTB pin
timing configuration
at t=75ms
Vbat > 4V and V1 low for t>100ms for MC33389ADW only (A version)
Note: In Normalrequest, if an SPI command is received
before the SW timing configuration (SWCR register), it will not
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DEVICE DESCRIPTION
SBC MODES
be taken into account by the SBC (except for the go to
In normal mode the SBC get the watchdog word from the
microcontroller via SPI. In case of a trigger time failure (no
trigger or trigger outside the enable window) the SBC-reset is
switched to active.
Emergency mode).
Correspondence between SBC and CAN Transceiver Modes
The table here below gives the different possible CAN
transceiver modes versus SBC modes.
NormalRequest, Sleep And Emergency Mode
Watchdog is not active in this modes.
Table 14. CAN Modes Versus SBC Modes
When SBC Is In The
Following Mode
CAN Transceiver
Can Be In
Reset condition
NormalRequest
Normal
Bus Standby mode
Bus Standby mode
RXTX or RXOnly or BusStandby
Bus Standby
Standby
Sleep
Bus Standby
Emergency
Bus Standby
Normal & V2 off (over load)
(note)
Bus standby
Note: In case V2 is turned off either by SPI command
(standby mode) or by the SBC itself due to V2 over load
condition (V2 short to gnd or V2 over temperature) the CAN is
automatically set into the Bus standby mode and does not
return to TXRX mode automatically when V2 is back to 5V.
The CAN must be re configured to TXRX or RXonly mode
after a V2 turn off.
Watchdog
General
The software window watchdog function is used to
monitors the microcontroller operation in Normal and in
Standby modes. The window watchdog timing is derived from
the SBC-clock. The desired watchdog timing must be first
transmitted during the SBC configuration, in NormalRequest
mode, via SPI to SWCR register. It can also be changed later
on. Selectable watchdog timings are 5ms, 10ms, 20ms,
33ms, 50ms, 75ms, 100ms and 200ms. These timings
correspond to the full disable window plus full enable window.
Figure 15. Window Watchdog Timing
earliest trigger time
watchdog trigger
50%
50%
latest
trigger
time
SBC watchdog window
enable window
disabled window
nom. trigger period
latest
reset
time
Watchdog Timing
SBC-Reset OUT
time out
As soon as the watchdog trigger is received in the enable
window, the internal counter is reset and start a new disable
window. The SBC triggers the watchdog word at CSB low to
high transition. Any watchdog trigger outside the enable
window leads to SBC reset.
In Normal and Standby Modes
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DEVICE DESCRIPTION
WAKE-UP CAPABILITIES
Several wake up capabilities are available.
register. Once activated, V3 remains ‘on’ during 400µs. The
wake-up inputs states are sampled at 300µs.
Forced Wake-up
Figure 16. V3 Timing
The forced wake-up is enabled and disabled by SPI in
V3R register. It is used in sleep mode to automatically wake-
up the system by supplying V1 with proper reset. This
correspond to jump into NormalRequest mode. If then, the
SBC is not properly configured within 75ms, it switches back
to sleep mode till the next wake-up. If both Cyclic sense and
forced wake-up are enabled by the SPI in sleep mode, only
Cyclic sense will be active.
wake-up inputs sample point
active
V3
passive
300us
400us
cyclic sense programmable period
The period of forced wake-up are 32ms, 64ms, 128ms,
256ms, 512ms, 1024ms, 2048ms, 8192ms, chosen by SPI in
CYTCR register.
Note: In sleep mode, the Cyclic Sense feature
‘EXCLUSIVE OR’ the forced Wake-up is chosen (not both).
Wake-up Inputs (Local Wake-up) / Cyclic Sense
Figure 17. Cyclic Sense Timing
SBC provides 3 wake-up inputs to monitor external events
such as closing/opening of switches. The wake-up feature is
available in Normal, Standby and sleep modes. The switches
can be directly connected to Vbat or to V3. The SBC must be
properly configured by setting bit WI2V3 in register V3R. In
this case, wake-ups are only detected when V3 is On. It can
take advantage of V3 cyclic sense feature. If both Cyclic
sense and forced wake-up are enabled by the SPI in sleep
mode, only Cyclic sense will be active.
Cyclic sense connected to wake-up inputs. Example with wake-up input L1
sensitivity to Low state and timing=80ms
V3
wake-up
OPEN
CLOSED
switch status
sample point (80%)
setup
V(L1)
Read L1
INTB
Options For Wake Input
300µs
Different conditions for wake-up can be chosen for wake-
up input pins (via SPI in WUICR register).
read
400
µ
s
No wake-up: No wake-up is detected, whatever occurs on
wake-up inputs.
0
80ms
(t1)
160ms
(t0)
High state: if the input pin voltage is above the detection
threshold during more than a 20µs filter time, a wake-up is
detected. A flag is set in the WUISR register.
Low state: if the input pin voltage is below the detection
threshold during more than a 20µs filter time, a wake-up is
detected. A flag is set in the WUISR register.
Change of state: each change of the wake-up input pin is
considered as a wake-up, if it lasts more than a 20µs filter
time. The first reference state (no wake-up) is the wake-up
input state when the SBC is programmed to this option. A flag
is set in the WUISR register.
1
1
1
0
1
1
0
0
0
actual state (read)
memory state
INTB (wake-up active=0)
Wake Up Inputs With Permanent Sense
Wake up detection can also be done on a permanent way
in Normal and Standby mode. If the contacts are connected to
V3, wake ups are only detected if V3 is on.
Wake ups are also detected on a permanent way in sleep
mode if the contacts are directly connected to Vbat (if they are
connected to V3, only cyclic sense is available in sleep mode).
Multiple sampling events: when wake-up inputs are used
with V3 in cyclic sense in sleep mode.
Local Wake-up Consequences
For positive edge sensitivity, 2 samples Low followed by 2
samples High are necessary to validate the wake-up
condition.
In normal or standby modes, the real time state of each
wake-up input pin is stored in the readable register WUIRTI.
Wake-ups are detected according to the option chosen. A flag
is set in the WUISR register. A maskable interrupt is sent via
INTB output.
For negative edge sensitivity, 2 samples High followed by
2 samples Low are necessary to validate the wake-up
condition.
In sleep mode, a local wake-up leads to a jump to
NormalRequest mode (via proper reset of the microcontroller). A
flag is set in the WUISR register.
For both edge sensitivity, 2 samples at a given state
followed by 2 samples in the opposite state are necessary to
validate the wake-up condition.
Table 18. SBC Mode Versus Local Wake-up Behaviour
Wake-up Inputs With Cyclic Sense
Connecting the external switches to V3 allows power
saving since V3 can be programmed to be active, passive or
cyclic (cyclic sense). This gives a great flexibility to reduce
total power consumption while allowing full wake-up
capabilities. Cyclic sense is available only in sleep mode.
The period of the Cyclic sense can be chosen out of 8
different timings: 32ms, 64ms, 128ms, 256ms, 512ms,
1024ms, 2048ms, 8192ms programmable via SPI in CYTCR
SBC Modes
Local Wake-up Behaviour
NormalRequest
No detection
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DEVICE DESCRIPTION
WAKE-UP CAPABILITIES
SBC Modes
Local Wake-up Behaviour
Detection Principle
Detection active according to the option.
The event is stored in WUISR register.The
SBC may activate INTB output.
The gnd shift to detect is selected via the SPI out of 4
different values (-0.7V, -1.2V, -1.7V, -2.2V). At each TX falling
edge (end of recessive state) CANH voltage is sensed. If it is
detected to be below the selected gnd shift threshold, the bit
SHIFT is set at 1 in GSLR register. No filter is implemented.
Required filtering for reliable detection should be done by
software (e.g. several trials).
Normal and
Standby
Real time state of each wake-up input
pin available in WUIRTI register
Detection active according to the option.
The event is stored in WUISR register. The
SBC switches to NormalRequest mode
Sleep
Emergency
No detection
DEVICE DIFFERENT VERSIONS
Wake-up By SPI
In some applications, the microcontroller might be
supplied by an external VDD and remains powered in SBC
Sleep mode. In this case, a feature is provided which makes
possible to wake-up the SBC by SPI activity.
The MC33389 is proposed in several package versions,
and also offers slight differences in term of functionalities.
The device version is identified in the device part number
by the first letter after the 389 number.
After V1 is totally switched off in sleep mode (V1<1.5V), if
a falling edge occurs on CSB (crossing 2.5V threshold), a
wake-up by SPI is detected, the SBC switches to
NormalRequest mode. A flag is set in ISR2.
The package identification is done by the last two letters of
the part number (DW for SO28 wide body, DH for power
SO20).
Interrupt Output
The INTB output may be activated in the following cases:
• Vbat overvoltage (BatHigh)
Differences between A, C and D versions:
• Vbat undervoltage (BatFail)
Behavior for V1 low:
• High temperature on V1 or V2
• Pre-warning temperature on V1 or V2
• CAN bus failure
A version:
If V1 is below reset threshold, device enters reset mode,
and if V1 stays below reset threshold for more than 100ms,
then the SBC automatically enters sleep mode. This could be
the case if V1 is shorted or permanently over loaded, and
going to sleep mode would then avoid system over current
consumption.
• SPI error
• Local wake-up (can be used for low battery detection)
• Bus wake-up
All these interrupts are maskable (See Register
Description Section).
This concerns the device reference: MC33389ADW and
MC33389ADH.
RSTB Input/Output
C and D versions:
The RSTB (reset) pin is an input/output pin. The typical
reset duration from SBC to microcontroller is 1ms. If longer
times are required, an external capacitor can be used. SBC
provides two RSTB output pull-up currents.
If V1 is below reset threshold, the SBC enters and stays in
reset mode (reset low) permanently.
This concerns the device reference: MC33389CDW and
MC33389CDH and MC33389DDW
A typical 30µA pull up when Vreset is below 2.5V and a
300uA pull up when reset voltage is higher than 2.5V.
RSTB is also an input for the SBC. It means the MC33389
is forced to NormalRequest mode after RSTB is released by
the microcontroller
Reset threshold specification:
A and C versions:
The reset threshold is defined per table “electrical
parameter, V1 pin 5V.
This concerns device MC33389ADW, ADH, CDW and
CDH
GND SHIFT DETECTION
D version : The reset threshold for the D version is slightly
higher than the A and C versions. Refer to device electrical
parameter table, V1 pin 5V
General
This concerns device reference MC33389DDW.
When normally working in two-wire operating mode, the
CAN transmission can afford some ground shift between
different nodes without trouble. Nevertheless, in case of bus
failure, the transceiver switches to single-wire operation,
therefore working with less noise margin. The affordable
ground shift is decreased in this case.
The SBC is provided with a ground shift detection for
diagnosis purpose. Four ground shift levels are selectable
and the detection is stored in the GSLR register which is
accessible via the SPI.
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DEVICE DESCRIPTION
Table 19. SBC Operation Mode
Wake up
V1 & V2 regula-
tors, V3 switch
Software
mode
capabilities
(if enabled)
Reset pin
INT
CAN cell
Watchdog
V1: ON (unless
failure condition
V2: OFF
Reset
state
Low
TermVbat
(duration 1ms)
V3: OFF
High.
V1: ON (75ms
time out)
(Active low -go to
reset state- if V1
under voltage
occurs)
Normal
Term Vbat
Request
V2: OFF
V3: OFF
High.
If enabled,
signal failure
condition or L0/
L1/L2 inputs
state change.
V1: ON
V2: ON
(Active low -go to
reset state- if W/
D or V1 under
voltage occurs)
Tx/Rx, or
Rx Only,
Normal
Standby
Sleep
Running
Running
V3: ON or OFF
or TermVbat
V1: ON
V2: OFF
same as Normal
Mode
same as Normal
Mode
TermVbat
V3: ON or OFF
- CAN
- SPI
V1: OFF
V2: OFF
V3 OFF or
cyclic
TermVbat
+ Wake up
capability
Not
- L0,L1,L2
Low
Low
Not active
Not active
Running
- Cyclic sense
- Forced Wake up
V1: OFF
V2: OFF
V3 OFF
Emerge
ncy
Not
none
TermVbat
Running
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DEVICE DESCRIPTION
Figure 20. State Machine
PowerDown
Reset
Emergency
W/D: timeout (4) OR V1 low (1)
Reset counter (1ms)
expired AND V1 high (2)
V1 low (1)
Standby
Normal Request
MC33389 C
version (9b)
SPI:Sleep (5)
Sleep
Normal
(MC33389 A version only: V1 low > 100ms) (9) (9a)
W/D: timeout (4) OR V1 low (1)
Legend:
1: “V1 low” means V1 below reset threshold
2: “V1 high” means V1 above reset threshold
3: “W/D: Trigger” means SCWR register write operation during Normal Request mode.
4: “W/D: time out” means SWCR register not written before W/D time out period expired, or W/D written in
incorrect time window. In normal request mode time out is 75ms.
5: “SPI: Sleep” means SPI write command to MCR and MCVR registers, data sleep
6: “SPI: Normal” means SPI write command to MCR and MCVR registers, data normal
7: “SPI: Standby” means SPI write command to MCR and MCVR registers, data standby
8: “Wake up” means one of the following event occur: CAN wake up, Forced wake, Cyclic sense wake up,
Direct Lx wake up or SPI CSB wake up.
9: “V1 low > 100ms” means V1 below reset threshold for more than 100ms.
9a: This condition leads to SBC in sleep mode only for the MC33389ADW (SO28 package).
9b: V1 low for > 100ms does not lead to sleep mode for the MC33389CDW (SO28WB package) and for
the MC33389CDH (HSOP20 package).
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SPI FUNCTIONNAL DESCRIPTION
General Description
Data Transfer
The SPI system is flexible enough to communicate directly
with numerous standard peripherals and MCUs available from
Motorola and other semiconductor manufacturers. SPI
reduces the number of pins necessary for input/output on the
MC33389. The SPI system of communication consists of the
MCU transmitting, and in return, receiving one databit of
information per clock cycle. Databits of information are
simultaneously transmitted by one pin, Microcontroller Out
Serial In (MOSI), and received by another pin, Microcontroller
In Serial Out (MISO), of the MCU. Figure 21 below shows the
basic SPI configuration between an MCU and one MC33389.
The SPI serial operation is guaranteed to 2.0 MHz.
The data to and from the MC33389 are transferred in form
of two bytes.The structure of the transferred information is the
same for control the MC33389 and status reporting. The
address field A5 to A0 (Bit15 to Bit10) contains the address of
a control or status register in the MC33389. RW (Bit9 and Bit8)
contains the read/write flag for the data field. The parity field is
located at P3 to P0 (Bit7 to Bit4). The data field D3 to D0 (Bit3
to Bit0) is attached to the 2 byte data word, see figure below.
Figure 22.
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MOSI
MISO
A5 A4 A3 A2 A1 A0 RW RW P3 P2 P1 P0 D3 D2 D1 D0
Figure 21. SPI Interface With Microcontroller
address + R/W
parity
data
MOSI
MISO
MOSI
MISO
MC68HCXX
MC33389
The SBC is accessible via the SPI interface in
NormalRequest mode, Normal mode and Standby mode. In
all other modes (Sleep mode, Emergency mode), the voltage
supply for the microcontroller in permanently switched off and
the SBC input logic for MISO, MOSI, CSB and SCLK isn’t
working (except SPI wake-up function in Sleep mode).
SCLK
CSB
Writing Data
To write data in a SPI register, two one-byte transmissions
have to performed. The first byte contains the address of the
register (MSB first) and the read/write bits which have to be
set to 1. The second byte contains the new data addressed by
the previous byte (MSB first) and the parity information. The
calculation of the parity field P3-P0 has to follow the equations
below:
Control and Status Reporting of the MC33389
The MCU is responsible for the control data transfer to the
MC33389, while the MC33389 reports its status to the MCU.
Summarized below are the major data for control and status
reporting.
- SPI initialization during start up
P3 = D3 ⊕ D0
P2 = D3 ⊕ D2
P1 = D2 ⊕ D1
P0 = D1 ⊕ D0
(EX-OR)
- MC33389 control during operation
- Watchdog triggering
- Reading status registers of the MC33389
Control Data
Note, that during the transmission of the two bytes the
CSB pin remains 0. See figure23 hereafter.
The control data are transferred from the MCU to the
MC33389. A control word includes an address of a certain
control register and the appropriate data. Basically the
following data will be transferred (See the SPI Register
Description section on page 21).
- MC33389 mode control
Figure 23.
HC08/12 SPI Data Register
SBC SPI Data Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A5 A4 A3 A2 A1 A0 RW RW P3 P2 P1 P0 D3 D2 D1 D0
A5 A4 A3 A2 A1 A0
1
1
- Supply control
- Forced wake-up timing
new address + R/W (1st byte)
old address + R/W
old parity
old data
- Cyclic sense control
- Watchdog control
P3 P2 P1 P0 D3 D2 D1 D0
- Transceiver control
new data + parity (2nd byte)
Status Data
The status data are transmitted from the MC33389 to the
MCU. After receiving a valid register address from the MCU,
the MC33389 returns the appropriate status. Some of the
major status data are listed below:
- Current operation mode status
- Wake-up sources
The SBC sends back the old address, R/W, parity, and
data information from a previous transmission. This data
contains no useful information (e.g. status).It shouldn’t be used.
In case of a wrong address field or parity mismatch, an
interrupt will be issued and the SBC retains the old state.
- Reset status
Reading Data
- Error status
To read data from a dedicated register two one-byte
transmissions have to be performed. The first byte contains
the address of the register (MSB first) and the read/write flag
setting to 0. The second byte needn’t to contain valid data,
- Overtemperature status
- Transceiver status
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SPI FUNCTIONNAL DESCRIPTION
nevertheless the parity calculation has to performed to avoid
Address coding, based on increasing the Hamming
an interrupt caused by a parity mismatch.
distance, parity check and generation for data.
During a read operation the SBC sends back the old
address and R/W bits and the new data addressed by the first
transmitted byte starting with P3 after the last valid read/write
bit has been received.
For the address and the read/write bits only codes with a
Hamming distance < 2 will be used. So, any single bit failure
caused by disturbances will be recognized and handled.
When one bit toggles in the address field during the
transmission, no misbehaviour occurs.
Note, that during the transmission of the two bytes the
CSB pin remains 0.
Additionally, validation registers are implemented to
validate safety critical settings in the MC33389, e.g. the mode
control register MCR and its validation register MCVR. To
change the appropriate settings, both registers must have the
same content to switch to another mode.
Figure below shows the content of the HC08/12 SPI
DataRegister and the SBC SPI Data Register before the
transmission. The new address and R/W bits are already in
the SPI Data Register while the new data and parity bits are
still in an appropriate microcontroller register or memory. This
2nd byte has to be loaded into the HC08/12 SPI Data Register
after the first byte has been transmitted to the SBC.
To increase data integrity a parity check is used. A parity
module in the MC33389 ascertains the parity of the data field
and compares the result with the received parity. When the
parity check is successfully passed, data will be written into
the addressed registers. The parity bits P3 to P0 results from
the logic equations below:
Figure 24.
HC08/12 SPI Data Register
SBC SPI Data Register
P3 = D3 ⊕ D0
P2 = D3 ⊕ D2
(EX-OR)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A5 A4 A3 A2 A1 A0 RW RW P3 P2 P1 P0 D3 D2 D1 D0
A5 A4 A3 A2 A1 A0
0
0
new address + R/W (1st byte)
old address + R/W
old parity
old data
P1 = D2 ⊕ D1
P0 = D1 ⊕ D0
0
0
0
0
0
0
0
0
new data + parity (2nd byte)
In case of error detection, the incoming data is not taken in
the SBC and an error flag is set in an SPI register.CSB Pin
The system MCU selects the MC33389 to be
communicated with, through the use of the CSB pin.
Whenever the pin is in logic low state, data can be transferred
from the MCU to the MC33389 and vice versa. Clocked-in
data from the MCU is transferred from the MC33389 shift
register and latched into the addressed registers on the rising
edge of the CSB signal if the read/write bit is set and the parity
check was successful.
After transmission of the 1st byte the HC08/12 SPI read
buffer contains the old address and R/W bits received from the
SBC. An appropriate operation in the microcontroller loads
the new data and parity into the HC08/12 SPI Data Register
(2nd byte). In the SBC the internal logic loads P3-P0 and D3-
D0 to the location of Bit15 to Bit8 in the SBC SPI Data Register
and will shift this data within the remaining eight clock cycles
(Figure below 25).
Figure 25.
The CSB pin controls the output driver of the serial output
pin. Whenever the CSB pin goes to a logic low state, the MISO
pin output driver is enabled allowing information to be
transferred from the MC33389 to the MCU. To avoid any
spurious data, it is essential that the high-to-low transition of
the CSB signal occur only when SCLK is in a logic low state.
HC08/12 SPI Data Register
SBC SPI Data Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0
0
0
0
0
0
0
0
P3 P2 P1 P0 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0
0
0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A5 A4 A3 A2 A1 A0 RW RW
new parity
new data
new address + R/W
SCLK Pin
old address + R/W in
HC08/12 SPI read buffer
addressed by the new address
The system clock pin (SCLK) clocks the internal shift
registers of the MC33389. The serial input pin (MOSI) accepts
data into the input shift register on the falling edge of the SCLK
signal while the serial output pin (MISO) shifts data
information out of the shift register on the rising edge of the
SCLK signal. False clocking of the shift register must be
avoided to guarantee validity of data. It is essential that the
SCLK pin be in a logic low state whenever chip select bar pin
(CSB) makes any transition. For this reason, it is
recommended though not necessary, that the SCLK pin be
kept in a low logic state as long as the device is not accessed
(CSB in logic high state). When CSB is in a logic high state,
any signal at the SCLK and MOSI pin is ignored and MISO is
tristated (high impedance).
After sixteen clock cycles the microcontrollers read buffer
contains the new parity and data and is now ready for the next
transmission (See figure hereafter 26)
Figure 26. .
HC08/12 SPI Data Register
SBC SPI Data Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A5 A4 A3 A2 A1 A0
0
0
A5 A4 A3 A2 A1 A0 RW RW
old address + R/W
0
0
0
0
0
0
0
0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P3 P2 P1 P0 D3 D2 D1 D0
old parity
old data
new parity + new data in
HC08/12 SPI read buffer
MOSI Pin
This pin is for the input of serial instruction data. MOSI
information is read in on the falling edge of SCLK. To program
the MC33389 by setting appropriate programming registers,
an sixteen bit serial stream of data is required to be entered
Safety Concept
Due the fact the SPI interface is an on-board interface
without any data fault detection capabilities, the SPI interface
of the MC33389 provides built-in fail save functions.
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SPI REGISTER DESCRIPTION
the MOSI pin starting with Bit15, followed by Bit14, Bit13, etc.,
Table 27. Module Address Map
to Bit0. For each fall of the SCLK signal, with CSB held in a
logic low state, a databit is loaded into the shift register per the
databit MOSI state.The shift register is full after sixteen bits of
information have been entered.
Register
Name
Address
$000
$003
$005
$006
$009
$00A
$00C
$00F
$011
$012
$014
$017
$018
$01B
$01D
$01E
$021
$022
$024
Register
Mode Control Register
MCR
MCVR
V3R
MISO Pin
Mode Control Validation
RegisterMCVR
The serial output (MISO) pin is the tri-stateable output
from the shift register. The MISO pin remains in a high
impedance state until the CSB pin goes to a logic low state.
The MISO pin changes state on the rising edge of SCLK and
reads out on the falling edge of SCLK. The MOSI/MISO
shifting of data follows a first-in-first-out protocol with both
input and output words transferring the MSB first.
Module Address Map, the module address map is shown
in table below.
V3 control register
Cyclic timing control register
CYTCR
SWCR
GSLR
WUICR
WUISR
WUIRTI
OTSR
TESRH
TESRL
RSR
Software watchdog
control register
Ground shift level register
Wake-up input control register
Wake-up input status register
Wake up input real time information
Overtemperature status register
Transceiver error status
register for CANH
Transceiver error status
register for CANL
Reset source register
Voltage supply status register
Interrupt mask control register 1
Interrupt mask control register 2
Interrupt source register 1
Interrupt source register 2
Transceiver control register
VSSR
IMR1
IMR2
ISR1
ISR2
TCR
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Table 28. MCR —Mode Control Register
MCR and MCVR registers are used to control the mode of the SBC. To change the operating mode of the SBC, both
registers must have the same content. The order of writing the registers has to be taken into account. To set the SBC mode
properly, MCR has to be written first then followed by MCVR write. A write operation sets the MCR and MCVR registers, a read
operation perform a read out of the current status (MSR - mode status register).
The Emergency mode is a regular mode.
A reset of both MCR and MCVR registers occurs when RSTB = low and the SBC is set to NormalRequest mode.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
MSR2
MCR2
0
BIT 1
MSR1
MCR1
0
BIT 0
MSR0
MCR0
0
R
MCR
$000
W
RESET
Table 29. MCVR — Mode Control Validating Register
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
MSVR2
MCR2
0
BIT 1
MSVR1
MCR1
0
BIT 0
MSVR0
MCR0
0
R
MCVR
$003
W
RESET
Table 30.
MC(V)R2
MC(V)R1
MC(V)R0
MSR2
MSR1
MSR0
Automatically entered after reset
NormalRequest
Normal
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
1
0
0
1
Standby
Sleep
Emergency
Table 31. V3R — V3R Control Register
This register is used to configure the state of V3 high side switch in normal and standby modes, and the V3 operation and the
Forced wake up or the cyclic sense option for the sleep mode operation.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
WI2V3
1
BIT 2
FWU
0
BIT 1
CYS
0
BIT 0
V3R0
0
R
V3R
$005
W
RESET
Table 32.
WI2V3
FWU
CYS
V3R0
Comments
X
X
X
0
0
X
0
0
1
0
1
V3 off
V3 on
Only In Normal And Standby
Mode Available
X
Cyclic Sense On
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WI2V3
FWU
CYS
V3R0
Comments
Only In Sleep Mode Available
X
1
1
0
X
X
Forced Wake-up On
X
X
wake-up inputs linked to V3
Note: In low power modes cyclic sense has priority. A reset of the register occurs when RSTB = low.
Table 33. CYTCR — Cyclic Timing Control Register
This register is used to select the cyclic sense or force wake up timing.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
CYTCR2
0
BIT 1
CYTCR1
0
BIT 0
CYTCR0
0
R
CYTCR
$006
W
RESET
Table 34.
CYTCR2
CYTCR1
CYTCR0
Comments
t(ms) typical
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Timer on, t1 (default)
Timer on, t2
Timer on, t3
Timer on, t4
Timer on, t5
Timer on, t6
Timer on, t7
Timer on, t8
32
64
128
256
512
1024
2048
8192
A reset of the register occurs when RSTB = low
Table 35. SWCR — Software Watchdog Control Register
This register is used to select the window watchdog time period. Open window of the selected period is only the second half
of the selected period.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
SWCR2
0
BIT 1
SWCR1
0
BIT 0
SWCR0
0
R
SWCR
$009
W
RESET
Table 36.
SWCR2
SWCR1
SWCR0
Comments
Timer on, t1 (default)
t(ms) typical
0
0
0
5
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SWCR2
SWCR1
SWCR0
Comments
Timer on, t2
Timer on, t3
Timer on, t4
Timer on, t5
Timer on, t6
Timer on, t7
Timer on, t8
t(ms) typical
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
10
20
33
50
75
100
200
The SW watchdog is only running in Normal and Standby mode. A reset of this register occurs when RSTB = low
Table 37. GSLR — Ground Shift Level Register
This register is used to monitor the ground shift of the vehicle network.
r
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
GSLR1
0
BIT 0
GSLR0
0
R
TXDOM
SHIFT
GSLR
$00A
W
RESET
0
Table 38.
GSLR1
GSLR0
Typ GND Shift Level
0
0
1
1
0
1
0
1
0.7V
-1.2V
-1.7V
-2.2V
SHIFT
1=ground shift above the threshold selected by GSLR1 and GSLR2. 0=no ground shift
The SHIFT information is latched until a read operation of the GSLR register occurs. The GSLR register is set to 0 after
power on reset. A reset of GSLR1 and GSLR0 occurs when RSTB = low.
TXDOM
0 = no failure on TX
1 = TX permanent dominant
Table 39. WUICR — Wake-up Input Control Register/SPI And Bus Wake-up Status
This register is used to configure the wake up level for the L0, L1 and L2 inputs. in read operation it reports the CAN wake up
and SPI (csb) wake up events
.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
WUICR1
0
BIT 0
WUICR0
0
R
SPIWU
BUSWU
WUICR
$00C
W
RESET
0
0
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Table 40.
WUICR1
WUICR0
Description
Comments
Comments
0
0
1
1
0
1
0
1
Wake-up inputs disabled
Positive edge sensitive
Negative edge sensitive
Positive and negative sensitive
Table 41.
SPIWU
BUSWU
Description
0
X
1
0
1
No wake-up events
Wake-up event on CAN bus
Wake-up event on SPI bus
X
The information in SPIWU and BUSWU is latched. Bits SPIWU and BUSWU will be reseted by a read operation of the
WUICR register and are set to 0 after a power on reset. A reset of WUICR1 and WUICR0 occurs when RSTB = low.
Table 42. WUISR — Wake-up Input Status Register
This register is used to read back the wake input (L0, L1 or L2) which has cause the SBC to wake up.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
WUISR2
WUISR1
WUISR0
WUISR
$00F
W
RESET
0
0
0
Table 43.
WUISR2
WUISR1
WUISR0
Comments
0
X
X
1
0
X
1
0
1
No Event on Wake-up Inputs
Event on L0
X
X
Event on L1
X
Event on L2
In case of a wake-up event, the appropriate bit is set to 1. The bits will be reseted by a read operation of the register. After
power on reset all bits are set to 0.
Table 44. WUIRTI — Wake-up Input Real-time Information
This register reports the real time information on the state (high or low) of the L0, L1 and L2 inputs.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
WUIRTI2
WUIRTI1
WUIRTI0
WUIRTI
$011
W
RESET
The bits WUIRTI2-0 contain the real time logic value coming from the wake-up inputs (0 mean input below threshold, 1 mean
input above threshold. Typical threshold is 3.5V).
Table 45. OTSR — Overtemperature Status Register
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This register is used to read back the overtemperature status for the V1 and V2 regulators. In write mode, it is used to turn V2
on after a V2 over temperature shutdown has occurred.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
OTV2
OTV2C
0
BIT 0
OTV1
R
OPWV2
OPWV1
OTSR
$012
W
RESET
0
0
0
OTV1: 1=V1 overtemperature shutdown, 0=V1 no overtemperature
OTV2: 1=V2 overtemperature shutdown, 0=V2 no overtemperature
OPWV1: 1=V1 overtemperature pre-warning, 0=V1 normal temperature
OPWV2: 1=V2 overtemperature pre-warning, 0=V2 normal temperature
In case of V1 or V2 overtemperature the appropriate voltage regulators are switched off automatically and the
overtemperature flags are set (latched). The flags can be reseted by a read operation of the register OTSR.
Once V2 has been switched off because of overtemp (OTV2=1) it can only be switched on again by forcing OTV2C=0 by a
write operation.
The V1 and V2 pre-warning flags are set as long as the first overtemperature exists. The flags disappear, when the
temperature is below the threshold. An overtemperature of the V2 power supply will also switch off V3. After a power on reset all
bits of the register are set to 0.
Table 46. TESRH — Transceiver Error Status Register For CANH
Register used to report the CAN H failure status
.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
TESRH3
TESRH2
TESRH1
TESRH0
TESRH
$014
W
RESET
0
0
0
0
Table 47.
TESRH3
TESRH2
TESRH1
TESRH0
0
0
X
0
1
0
X
X
1
0
0
1
0
0
0
1
No failure on CANH
CANH wire interruption
CANH short circuited to Vbat
CANH short circuited to ground
CANH short circuited to VCC
X
X
X
X
In case of CANH line failures, the appropriate bit(s) are set according to table 46. This information is latched. The register
can be reseted by a read operation. After power on reset, all bits are set to 0.
Table 48. TESRL — Transceiver Error Status Register For CANL And Tx
Register used to report the CANL and Tx permanent dominant failure status
.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
TESRL3
TESRL2
TESRL1
TESRL0
TESRL
$017
W
RESET
0
0
0
0
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Table 49.
TESRL3
TESRL2
TESRL1
TESRL0
0
0
0
0
0
0
1
No failure
X
CANL wire interruption
CANL short circuited to ground/
CANH mutually shorted to CANL
0
1
0
X
X
1
X
X
1
0
X
X
CANL short circuited to Vbat
CANL short circuited to Vdd
In case of CANL line failures, the appropriate bit(s) are set according to table 48. This information is latched and the register
can be reseted by a read operation. After power on reset, all bits are set to 0.
Table 50. RSR — Reset Source Register
This register reports the source of a reset that has occurred
.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
RSR2
RSR1
RSR0
RSR
$018
W
RESET
1
0
1
RSR0: 1 => VDD1 undervoltage occurred (RSR2=1 in this case), 0=> no undervoltage on VDD1 occurred
RSR1: 1 =>SW watchdog reset occurred (RSR2=1 in this case), 0=>no SW watchdog reset occurred
RSR2: 1 =>external reset occurred (RSR0=RSR1=0 in this case), 0=>no external reset occurred
Events related to the bits in register RSR are latched. All bits can be reseted by a read operation of the register. After a power
on reset, RSR2 and RSR0 are set to 1. Therefore the first read out of the register after power on delivers RSR[2:0] = [101].
Table 51. VSSR — Voltage Supply Status Register
Register used to monitor the status of the V2, V3 and Vbat voltage level.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
V3SR
BIT 2
V2SR
BIT 1
BIT 0
R
VBSR1
VBSR0
VSSR
$01B
W
RESET
POR
0
0
0
0
0
1
Table 52.
VBSR1
VBSR0
0
X
1
0
1
No failure on Vbat
Undervoltage (BatFail)
Overvoltage (BatHigh)
X
V2SR: 1=V2 on, 0=V2 off
V3SR: 1=V3 overtemperature, 0=V3 no overtemperature
VBSR1 is a real time information and cannot be reseted. Bits V3SR, V2SR and VBSR0 are latched and can be reseted by a read
operation of the register.
Table 53. IMR1 — Interrupt Mask Control Regis
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The next two registers (IMR1 and IMR2) are used to mask the interrupt function.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
HV
0
BIT 2
HTPW
0
BIT 1
MTPW
0
BIT 0
BATU
0
R
IMR1
$01D
W
RESET
Table 54. IMR2 — Interrupt Mask Control Register 2
BIT 6 BIT 5 BIT 4 BIT 3
BIT 7
BIT 2
BUSF
0
BIT 1
SPIE
0
BIT 0
WU
0
R
IMR2
$01E
W
RESET
To enable the appropriate interrupt, the mask bit has to be set to 1. For disabling the interrupt the bit must be cleared to 0.
After a power on reset or RSTB = low, the bits are cleared to 0. All interrupts are disabled. Explanation for the abbreviations:
HV : Vbat high voltage
HT : High temperature on V1 or V2
MTPW : Medium temperature pre-warning on V1 or V2
BATU: Battery undervoltage (BatFail)
BUSF : CAN bus failure
SPIE : SPI error
WU : Wake-up
Table 55. ISR1 — Interrupt Source Register
The next two registers (ISR1 and ISR2) are used to read the interrupt source.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
HV
BIT 2
BIT 1
BIT 0
R
HTPW
MTPW
BATU
ISR
$021
W
RESET
0
0
0
0
Table 56. ISR2 — Interrupt Source Register 2
BIT 6 BIT 5 BIT 4 BIT 3
BIT 7
BIT 2
BIT 1
SPIE
BIT 0
WU
R
BUSF
ISR
$022
W
RESET
0
0
0
All bits in registers ISR1 and ISR2 are copies of the appropriate bits in different SPI registers. For a faster read out, these bits
are merged in ISR1 and ISR2. A reset cannot be done for registers ISR1 and ISR2.
Table 57. TCR—Transceiver Control/Status Register
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This register is used to control the state of the CAN transceiver (CAN transceiver state is also dependant upon the SBC
mode). When it is read, this register reports the CAN transceiver state and a CAN overtemperature condition
.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
TSR2
TCR2
0
BIT 1
TSR1
TCR1
0
BIT 0
TSR0
TCR0
0
R
TOT
TCR
$024
W
RESET
0
Table 58.
TCR2
TCR1
TCR0
TSR2
TSR1
TSR0
0
1
1
0
0
1
Standard/TermVbat
Standard/RXOnly
Standard/RXTX
0
0
0
0
1
1
0
0
1
0
TOT
1 => Transceiver overtemperature
0 => normal temperature
The MODE bit selects between the standard and extended physical layer mode.
Any conditions forcing the transceiver to TermVbat lead to reset of TCR0 TCR1 bits.
After power on reset all bits of the register are set to 0. The information TOT is latched.
To reset TOT a read operation of TCR has to be performed. In case of RSTB = low the register content remains unchanged.
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APPLICATION
Sleep Mode Activation
The SBC then enters sleep mode. It will wake up after the
Once in sleep mode, the SBC turns off V1 and V2
regulator. Thus the micro controller can not run any mode.
in order to have it run again, the SBC should enable and
turn on V1, and this is achieve by an SBC wake up event.
Several options are available to wake up the SBC and the
application and have the micro controller in run mode.
Some wake up are selectable, some are always active in
sleep mode.
time period selected in the CYTCR register.
Sleep Mode Enter With Cyclic Sense
To enter sleep mode and activate the cyclic sense wake
up the following register must be written:
- Write to V3R register, data 1010, this set the VI2V3 and
CYS bits to 1.
- Write to CYTCR register the desired cyclic sense period.
(This sets the time the SBC will wait in sleep mode to turn on
V3 and sense the Lx inputs).
- Wake up from CAN interface and wake up from SPI
(CSB) are always active.
- Wake up from L0/L1/L2 inputs, with and without cyclic
sense and the FWU (Forced Wake Up) are selectable. The
selection must be done while the SBC is in Normal or Standby
mode, and prior to enter sleep mode.
- Write to WUICR bits 0 and 1 to select the edge sensitivity
for the Lx inputs.
- Write to MCR register: data SLEEP (100)
- Write to MCVR register: data SLEEP (100)
The SBC then enters sleep mode. It will periodically turn
on V3 and while V3 is on, sample the level of the Ls inputs.
If any of the 3 Lx inputs is in the correct state for two
consecutive samples, SBC will wake up. If not, it will stay in
sleep mode. (refer to device description for detail).
General Condition To Enter Sleep Mode
In order to make sure the SBC enters the sleep mode, and
in addition to the write into MCR and MCVR register, all
previous wake up conditions must have been cleared. To
clear a wake up condition requires that the appropriate
register is read.
Sleep Mode Enter With Direct Lx Input Wake Up
To enter sleep mode and activate the direct wake up from
the Lx inputs, the following register must be written:
- Write to V3R register, data 0000), this clear VI2V3 bit.
- Write to WUICR bits 0 and 1 to select the edge sensitivity
for the Lx inputs.
After an SBC power up from “zero” (battery power up or
cold start), the following registers must be read:
- WUICR: possible wake up event report from CAN bus
- RSR: report a V1 undervoltage
- VSSR: reports a Vbat fail flag
Once these read operation are done, the wake up
conditions or flag are reset.
- Write to MCR register: data SLEEP (100)
- Write to MCVR register: data SLEEP (100)
The SBC then enters sleep mode. It will wake up as soon
as any of the Lx input read the correct state.
The VSSR register bit VBSR0 can be used to determined
if the SBC has experience a loss of battery voltage.
After an SBC wake up from “sleep mode” the following
registers indicate the wake up source and must be cleared in
order to allow the SBC to enter sleep mode again:
- WUICR: wake up event report for CAN or SPI buses.
- WUISR: Wake up event report for the L0/L1/L2 inputs.
- RSR: report a V1 undervoltage
Figure 59. Typical Sleep Current vs Temp and Batt
180
160
140
120
100
- VSSR: reports a Vbat fail flag
- etc
The paragraphs below describe the write operation to be
done for the several sleep mode and wake up control options.
In addition to FWU, cyclic sense and direct wake up, the
CAN and SPI wake will always be activated.
Sleep Mode With CAN And SPI Wake Up
The enter sleep mode and activate the only the CAN or
SPI wake up, no dedicated wake up condition must be done.
In sleep mode the SBC has CAN and SPI wake up always
active. To enter sleep mode in this case, while the SBC is in
normal or standby mode:
80
16V
60
12V
6V
40
-50
- Write to V3R register: data 0000 (this clear the bit WI2V3
which is set to1 after reset).
-25
0
25
50
75
100
125 150
- Write to MCR register: data SLEEP (100)
TEMPERATURE (°C)
- Write to MCVR register: data SLEEP (100)
The SBC then enters sleep mode.
Voltage
Sleep Mode Enter With Forced Wake Up
To enter sleep mode and activate the forced wake up the
following register must be written:
- Write to V3R register, data 0100), this set the FWU bit to 1.
- Write to CYTCR register the desired wake up time. (This
sets the time the SBC will stay in sleep mode).
- Write to MCR register: data SLEEP (100)
- Write to MCVR register: data SLEEP (100)
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APPLICATION
Figure 60. Typical Application Schematic 1
Auxillary 5V
Vdd
C5
C6
V2
V1
Vbat
V3
C1
C2
Ignition
Auxillary 12V
C3
C4
Reset
INT
reset
int
Rp0
Rs0
CL0
L0
L1
L2
S0
S1
CSB
MISO
MOSI
SCK
SPI
Rtl
CANH
CANL
Rp1
Rp2
RH
Rs1
CL1
Tx
Rx
RL
CAN
Rth
Gnd
Gnd
Rs2
CL2
C1: 22uF
RH> 500 ohms
RL> 500 ohms
S2
C2: 100nF
C3: 22uF esr <10 ohms
C4: 100nF
Rp0,1,2: 22k
Rs0,1,2: 22 k
CL0,1,2: 10nF
CAN bus
C5: 22uF esr < 10 ohms
C6: 100nF
(V3 supplies switch pull up resistors. Sleep mode with cyclic sense).
Figure 61. Typical Application: V3 used as auxilaary ECU supply - Reset Duration Extension
Vbat
C1
C2
Ignition
switch
V3
Rp0
Rp1
Rs0
CL0
L0
L1
L2
V1
Vdd
S0
S1
Micro
C3
C4
MC33389
Gnd
Reset
reset
Rs1
CL1
Cr
Auxillary local 12V
(V3 supplies local switch 12V.
Switch pull up resistors supplied
from Switch battery line.
Reset duration extension
Rp2
Rs2
CL2
Sleep mode without cyclic sense).
S2
Figure 62. Typical Application Schematic
Auxillary 5V
Vdd
C5
C6
V2
Vbat
C1
C2
V1
Ignition
S0
V3
Auxillary 12V
Reset
INT
reset
int
Rp0
Rs0
CL0
L0
L1
L2
CSB
MISO
MOSI
SCK
SPI bus
SPI
Rtl
CANH
CANL
RH
RL
CAN bus # 1
Tx
Rx
CAN 1
CAN 2
SCI
Rth
Gnd
(Wake up input linked to pe-
ripheral circuits: (ex: low speed
CAN or LIN transceivers).
Inh
Vbat
Rtl
Vdd
RH
CAN bus # 2
CANH
CANL
Tx/Rx
MC33388
RL
Gnd
Rth
Gnd
+12V
1k
Inh
Vsup
Tx/Rx
MC33399
Gnd
LIN bus
LIN
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APPLICATION
The SBC offers several capabilities to help user debug its
When the SBC has had it W/D reactivated it is not possible
application.
to deactivated it again by software. The only way to do this is
to remove battery supply voltage (Vbat < 3V for more than
200us) and then power up the SBC.
- External bias of V1 and reset pin.
- Turn off of the software watchdog in standby mode.
- Special debug samples with software watchdog disable
at power up (contact local Motorola representative).
Debug And Program Download Into Flash Memory
While the SBC is powered it enters normal request and
expect within the 75ms time period of the NR mode an SPI
tigger word (to enter normal mode and select the W/D time
period). If this does not occurs, the SBC enter sleep mode and
turn off V1.
When the software is been debug, and when using
development tools, it is not always easy to make sure these
events properly. It is thus possible to externally power the V1
line with an external 5V supply, and to force the Reset pin to
V1 or to and external 5V. These can be done at nominal
voltage and temperature. By doing this, 5V is provided to the
MCU Vdd and reset lines.
Under this condition the SBC is not operational. However
the reset pin is pulled low and is sinking 5mA to ground. This
means that the external circuitry which drive reset must have
a current capability higher than 5mA in order to drive the reset
in high state.
Disable Of Software Watchdog In Standby Mode
The software watchdog can be disable in standby mode
only. In order to disable it the following operation must be done:
- Write to MCR register: data 011 (bit 2, bit 1, bit 0)
- Write to MCVR register: data 011 (bit 2, bit 1, bit 0)
Then the SBC enters the standby mode without software
watchdog. However the V2 can not be turn on, and the CAN
cell can not be used.
Special Device
Special components are available to make the debug
even easier. These device has a special behaviour which at
power up disable the watchdog. These device can be
available through marketing only. Contact local Motorola
representative for more detail.
The behaviour of such special parts is as follow:
- At power up (from Vbat =0V), the SBC enters "normal request
mode" and stays in this mode permanently. V1 is on, V2 and V3
off, CAN in Term Vbat. For reference, with MC33389ADW and
MC33389CDH units it stays there 75ms only and go to sleep if no
SPI.
- To get the SBC out on NormalRequest mode, write to
SWCR register any valid data. This will enable the SBC to
enter Normal mode, with V1 and V2 on. Once this is done, the
SBC is controllable through SPI, in the same way as the
normal versions. It can be turned in sleep. After wake up it
enters NR mode (same as after power up described above).
Only difference is that there is no need to refresh the
software watchdog. Internally, the watchdog is running but
when time out elapsed a reset is not generated.
When application debug is advanced enough, it is
possible to enable the W/D-reset function.
To re activated the W/D effect, the VSSR register, bit
VBSR0 (bat fail) must be read (cleared). When this is done,
the W/D and 75ms timer of the NR mode effects are activated.
However, due to re synchronisation, it is likely that at some
point a reset is generated and that the SBC enter reset state
then Normalrequest mode.
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PIN ONE ID
NOTES:
h X 45
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
E2
E3
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.150 PER SIDE. DIMENSIONS D AND E1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
20
1
D1
D
A
10
11
6. DATUMS –A– AND –B– TO BE DETERMINED AT
DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE TIEBAR
PROTRUSIONS. ALLOWABLE TIEBAR
PROTRUSIONS ARE 0.150 PER SIDE.
EXPOSED
HEATSINK AREA
B
E1
10X
E
E4
MILLIMETERS
BOTTOM VIEW
DIM
A
A1
A2
A3
D
MIN
3.000
0.100
2.900
0.00
MAX
3.400
0.300
3.100
0.100
M
bbb
C
B
DATUM
Y
H
PLANE
b1
15.800 16.000
A2
A
D1 11.700 12.600
D2
E
0.900
13.950 14.450
1.100
c1
c
E1 10.900 11.100
SEATING
PLANE
C
E2
E3
E4
L
2.500
6.400
2.700
0.840
2.700
7.200
2.900
1.100
b
M
aaa
C A
L1
b
b1
c
c1
e
0.350 BSC
0.400
0.400
0.230
0.230
0.520
0.482
0.320
0.280
SECTION W–W
GAUGE
PLANE
L1
W
1.270 BSC
h
–––
0
1.100
8
W
L
bbb
C
aaa
bbb
0.200
0.100
(1.600)
DETAIL Y
CASE 979C–02
ISSUE A
For More Information On This Product,
MC33389
MOTOROLA
34
Go to: www.freescale.com
Freescale SMeCm33i3c89onductor, Inc.
D
NOTES:
A
1. DIMENSIONS ARE IN MILLIMETERS.
28
15
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
14
MILLIMETERS
B
PIN 1 IDENT
DIM
A
A1
B
C
D
MIN
2.35
0.13
0.35
0.23
17.80
7.40
MAX
2.65
0.29
0.49
0.32
18.05
7.60
L
E
e
0.10
1.27 BSC
H
L
10.05
0.41
0
10.55
0.90
8
e
C
SEATING
PLANE
B
C
M
S
S
0.025
C
A
B
CASE 751F–05
ISSUE F
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do
vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer
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Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its
officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2002
How to reach us:
: Motorola Literature Distribution;
: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1,
USA / EUROPE / Locations Not Listed
JAPAN
P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447
Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-344-3569
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Technical Information Center: 1-800-521-6274
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852-26668334
: http://www.motorola.com/semiconductors
HOME PAGE
For More Information On This Product,
Go to: www.freescale.com
MC33389/D
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