MC33394DWB [NXP]
1.2A SWITCHING CONTROLLER, 220kHz SWITCHING FREQ-MAX, PDSO54, PLASTIC, SOICW-54;型号: | MC33394DWB |
厂家: | NXP |
描述: | 1.2A SWITCHING CONTROLLER, 220kHz SWITCHING FREQ-MAX, PDSO54, PLASTIC, SOICW-54 开关 光电二极管 |
文件: | 总44页 (文件大小:640K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor,OIrdnercth.is document from Analog Marketing
Rev. 2.5, 11/2002
MULTI–OUTPUT
POWER SUPPLY
The 33394 is a multi–output power supply integrated circuit with high
speed CAN transceiver. The IC incorporates a switching pre–regulator
operating over a wide input voltage range from +4.0V to +26.5V (with
transients up to 45V).
SEMICONDUCTOR
TECHNICAL DATA
The switching regulator has an internal 3.0A current limit and runs in both
buck mode or boost mode to always supply a pre–regulated output followed
by Low Drop Out (LDO) regulators: VDDH / 5.0V @ 400mA; VDD3_3 / 3.3V
@ 120mA; VDDL / 2.6V (User scalable between 3.3V – 1.25V) @ 400mA
typically, using an external NPN pass transistor. The Keep Alive regulator
VKAM (scalable) @ 50mA; FLASH memory programming voltage VPP /
5.0V or 3.3V @ 150mA; three sensor supply outputs VREF(1,2,3) / 5.0V
(tracking VDDH) @ 100mA each; and a switched battery output (VSEN) to
supply 125mA clamped to 17V.
44–Lead HSOP
DH SUFFIX
CASE 1291
Additional features include Active Reset circuitry watching VDDH,
VDD3_3, VDDL and VKAM, user selectable Hardware Reset Timer (HRT),
Power Sequencing circuitry guarantees the core supply voltages never
exceed their limits or polarities during system power up and power down.
A high speed CAN transceiver physical layer interfaces between the
microcontroller CMOS outputs and differential bus lines. The CAN driver is
short circuit protected and tolerant of loss of battery or ground conditions.
33394 is designed specifically to meet the needs of modules, which use
the MPC565 microcontroller, though it will also support others from the
MPC5XX family of Motorola microcontrollers.
44–Lead QFN
FC SUFFIX
CASE 1310
(BOTTOM VIEW)
Features:
• Wide operating input voltage range: +4.0V to +26.5V (+45V transient).
• Provides all regulated voltages for MPC5XX MCUs and other ECU’s
logic and analog functions.
• Accurate power up/down sequencing.
• Provides necessary MCU support monitoring and fail–safe support.
54–Lead SOICW–EP
DWB SUFFIX
• Provides three 5.0 V buffer supplies for internal & external (short–circuit
CASE 1377
protected) sensors.
• Includes step–down/step–up switching regulator to provide supply
voltages during different battery conditions.
PIN CONNECTIONS
• Interfaces Directly to Standard 5.0V I/O for CMOS Microprocessors by
means of Serial Peripheral Interface.
1
GND
CANL
CANH
HRT
CANTXD
CANRXD
/PORESET
/HRESET
/PRERESET
N/C
VDDL_FB
VDDL_B
VDDL_X
VDD3_3FB
VDD3_3
VPP
VPP_EN
VREF1
WAKEUP
REGON
VSEN
VKAM_FB
VKAM
VIGN
N/C
KA_VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
PIN CONNECTIONS
/SLEEP
N/C
CS
DI
SCLK
DO
1
VBAT
VBAT
KA_VBAT
VIGN
VKAM
VKAM_FB
VSEN
REGON
WAKEUP
VREF1
VPP_EN
VPP
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
SW1
SW1
SW1
BOOT
SW2G
GND
INV
GND
1
/SLEEP
HRT
CANH
CANL
GND
CANTXD
CANRXD
/PORESET
/HRESET
/PRERESET
VDDL_FB
N/C
SW2G
BOOT
SW1
VREF3
VREF2
VDDH
VPRE_S
VPRE
VCOMP
INV
VCOMP
VPRE
VPRE_S
VDDH
VREF2
VREF3
DO
SCLK
DI
CS
/SLEEP
HRT
CANH
CANL
GND
SOICW
SW1
SW1
QFN
HSOP
VBAT
VBAT
KA_VBAT
VIGN
VKAM
GND
SW2G
BOOT
N/C
SW1
SW1
SW1
SW1
SW1
TOP VIEW
This document contains information on a new product. Specifications
and information herein are subject to change without notice.
For More Information On This Product,
Go to: www.freescale.com
Motorola, Inc. 2002
Freescale Semiconductor, Inc.
33394
To Q3
Figure 1. 33394DH – Simplified Block Diagram and Typical Application
L1
47
Lf1
6.8
VPRE
5.6 V
H
H
Dp1
Dp2
D2
VBAT
SW1
1, 2
Cf2
42–44
Cf1
10
+
–
C1
100
Oscillator
Cb
100 nF
F
100
F
F
Feed
Forward
Ramp
D1
BOOT
41
KA_VBAT
3
High–Side
Drive
Buck
Generator
Control
Logic
ON
SW2G
40
4.7 k
Q1
VIGN
4
Low–Side
Drive
Control
Boost
GND
MTD20N03HDL
Cc3
OFF
10 nF
39
+
–
VKAM
5
2.6 V
VKAM
Keep–Alive
Adj. Volt.
60 mA
22 k
40 k
3.3 nF
INV
38
VKAM_FB
6
–
+
10 nF
22
F
+
–
I–Lim
Rc3
430R
Rc2
100 k
11.7 k
20 k
100 pF
VCOMP
37
Cc1
Vbg
Cc2
1.0 nF
VSEN
VBAT Volt.
125 mA
VSEN
7
VPRE
36
35
VPRE_S
T–Lim, I–Lim
REGON
8
Enable
CANRXD
WAKEUP
Sleep
9
VREF1
5.0 V
100 mA
LDO
VDDH
5.0 V
400 mA
LDO
CAN
Wakeup
Logic
VDDH
34
5.0 V
VREF1
10
5.0 V
10 nF
T–Lim, I–Lim
T–Lim, I–Lim
10 nF
47
F
1.0
F
V
bg
VPP
5.0 V/3.3 V
150 mA
LDO
T–Lim, I–Lim
VREF2
5.0 V
100 mA
LDO
VPP_EN
11
VREF2
33
5.0 V
10 nF
Band Gap
Reference
5.0 V/3.3 V VPP
12
T–Lim, I–Lim
1.0
F
10 nF
47
F
VDD3_3
VDD3_3
3.3 V
120 mA
LDO, Pass
T–Lim, I–Lim
VREF3
5.0 V
100 mA
LDO
VREF3
32
5.0 V
10 nF
13
VDD3_FB
Standby
Control
3.3 V
T–Lim, I–Lim
14
1.0
F
V
Q3
VPRE
Q2
10 nF 47
F
VDDL_B
VDDL Drive
Adj. Volt.
40 mA
Dual Pass
T–Lim
DO
16 Bit
SPI
Control
Fault Rep.
31
15
16
17
SCLK
DI
VDDL_X
Q3
MJD31C
30
29
28
MJD31C
VDDL_FB
VDDL
2.6 V
CS
110R
VDDH
5.0 V
Sleep
/PRERESET
18
19
Reset
Detection
VDDH,
VDD3_3,
VDDL
/SLEEP
10 nF
47
F
/HRESET
27
100R
/PORESET
20
High–Speed CAN
Transceiver
47 k
1.0
HRT
26
POR Timer
F
10 k 10 k
10 k
21
CANRXD
22
23 24
25
VKAM
2.6 V
CANL CANH
CANTXD
GND
120 R
Notes: 1. In this configuration the device can operate with a minimum input voltage VBAT of 4.0 V (voltage at 33394 VBAT pins).
Notes: 2.VDDL and VKAM are adjustable to support current microprocessor technology (1.25 V to 3.3 V) by means of an external resistor divider.
Notes: 3. When the 33394 CAN transceiver is not used, CANL and CANH pins can be shorted together.
Notes: 4. Dp1 = reverse battery protection diode. Dp2 = load dump protection diode. Dp1, Dp2 can be ommitted in those applications which do not require such protection.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
PIN FUNCTION DESCRIPTION (44–HSOP Package)
PIN NO.
1
NAME
VBAT
DESCRIPTION
Battery supply to IC (external reverse battery protection needed in some applications)
Battery supply to IC (external reverse battery protection needed in some applications)
Keep alive supply (with internal protection diode)
Turn–On control through ignition switch (with internal protection diode)
VDDL tracking Keep Alive Memory (Standby) supply
VKAM output feedback
2
VBAT
3
KA_VBAT
VIGN
4
5
VKAM
6
VKAM_FB
VSEN
7
Switched battery output
8
REGON
WAKEUP
VREF1
VPP_EN
VPP
Regulator “Hold On” input
9
CAN wake up event output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VDDH tracking linear regulator 1
VPP enable
5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3
3.3 V regulated supply output, base drive for optional external pass transistor
VDD3_3 output feedback
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
GND
VDDL optional external pass transistor base drive, operating in Boost Mode only
VDDL external pass transistor base drive
VDDL output feedback
Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset)
Open drain / HRESET (Hardware Reset) output
Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.
CAN receive data (DOUT)
CAN transmit data (DIN)
Ground
CANL
CAN differential bus drive low line
CANH
CAN differential bus drive high line
HRT
Hardware Reset Timer pin (programmed with external capacitor and resistor)
Sleep Mode & Power Down control
/SLEEP
CS
SPI chip select
DI
SPI serial data in
SCLK
SPI clock input
DO
SPI serial data out
VREF3
VREF2
VDDH
VDDH tracking linear regulator 3
VDDH tracking linear regulator 2
5.0 V regulated supply output
VPRE_S
VPRE
Switching pre–regulator output sense
Switching pre–regulator output
VCOMP
INV
Switching pre–regulator compensation (error amplifier output)
Switching pre–regulator error amplifier inverting input
Ground
GND
SW2G
BOOT
External power switch (MOSFET) gate drive — Boost regulator
Bootstrap capacitor
SW1
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
SW1
SW1
NOTE: The exposed pad of the 44 HSOP package is electrically and thermally connected with the IC ground.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
PIN FUNCTION DESCRIPTION (44–QFN Package)
DESCRIPTION
PIN NO.
NAME
1
GND
SW2G
BOOT
Ground
2
External power switch (MOSFET) gate drive — Boost Reg.
Bootstrap capacitor
3
4
SW1
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
Battery supply to IC (external reverse battery protection needed in some applications)
Battery supply to IC (external reverse battery protection needed in some applications)
Keep alive battery supply (with internal protection diode)
Turn on control through ignition switch (with internal protection diode)
VDDL tracking Keep Alive Memory (Standby) supply
VKAM output feedback
5
SW1
6
SW1
7
VBAT
8
VBAT
9
KA_VBAT
VIGN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VKAM
VKAM_FB
VSEN
Switched battery output
REGON
WAKEUP
VREF1
VPP_EN
VPP
Regulator “Hold On” input
CAN wake up event output
VDDH tracking linear regulator 1
VPP enable
5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3
3.3 V regulated supply output, base drive for optional external pass transistor
VDD3_3 output feedback
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
GND
VDDL optional external pass transistor base drive, operating in Boost Mode only
VDDL external pass transistor base drive
VDDL output feedback
Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset)
Open drain / HRESET (Hardware Reset) output
Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.
CAN receive data (DOUT)
CAN transmit data (DIN)
Ground
CANL
CAN differential bus drive low line
CANH
CAN differential bus drive high line
HRT
Hardware Reset Timer pin (programmed with external capacitor and resistor)
Sleep Mode & Power Down control
/SLEEP
CS
SPI chip select
DI
SPI serial data in
SCLK
SPI clock input
DO
SPI serial data out
VREF3
VREF2
VDDH
VDDH tracking linear regulator 3
VDDH tracking linear regulator 2
5.0 V regulated supply output
VPRE_S
VPRE
Switching pre–regulator output sense
Switching pre–regulator output
VCOMP
INV
Switching pre–regulator compensation (error amplifier output)
Switching pre–regulator error amplifier inverting input
NOTE: The exposed pad of the 44 QFN package is electrically and thermally connected with the IC ground.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
PIN FUNCTION DESCRIPTION (54 SOICW–EP Package)
PIN NO.
1
NAME
GND
DESCRIPTION
Ground
2
CANL
CAN differential bus drive low line
3
CANH
HRT
CAN differential bus drive high line
4
Hardware Reset Timer pin (programmed with external capacitor and resistor)
Sleep Mode & Power Down control
5
/SLEEP
N/C
6
No Connect
7
CS
SPI chip select
8
DI
SPI serial data in
9
SCLK
SPI clock input
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
DO
SPI serial data out
N/C
No Connect
VREF3
VREF2
VDDH
VPRE_S
VPRE
VDDH tracking linear regulator 3
VDDH tracking linear regulator 2
5.0 V regulated supply output
Switching pre–regulator output sense
Switching pre–regulator output
VCOMP
INV
Switching pre–regulator compensation (error amplifier output)
Switching pre–regulator error amplifier inverting input
Ground
GND
SW2G
BOOT
SW1
External power switch (MOSFET) gate drive — Boost regulator
Bootstrap capacitor
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
Source of the internal power switch (n–channel MOSFET)
Battery supply to IC (external reverse battery protection needed in some applications)
Battery supply to IC (external reverse battery protection needed in some applications)
Battery supply to IC (external reverse battery protection needed in some applications)
Battery supply to IC (external reverse battery protection needed in some applications)
Battery supply to IC (external reverse battery protection needed in some applications)
Keep alive supply (with internal protection diode)
No Connect
SW1
SW1
SW1
SW1
VBAT
VBAT
VBAT
VBAT
VBAT
KA_VBAT
N/C
VIGN
Turn–On control through ignition switch (with internal protection diode)
VDDL tracking Keep Alive Memory (Standby) supply
VKAM output feedback
VKAM
VKAM_FB
VSEN
Switched battery output
REGON
WAKEUP
VREF1
VPP_EN
VPP
Regulator “Hold On” input
CAN wake up event output
VDDH tracking linear regulator 1
VPP enable
5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3
3.3 V regulated supply output, base drive for optional external pass transistor
VDD3_3 output feedback
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
N/C
VDDL optional external pass transistor base drive, operating in Boost Mode only
VDDL external pass transistor base drive
VDDL output feedback
No Connect
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset)
Open drain / HRESET (Hardware Reset) output
Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.
CAN receive data (DOUT)
CAN transmit data (DIN)
NOTE: The exposed pad of the 54 SOICW–EP package is electrically and thermally connected with the IC ground.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
1. MAXIMUM RATINGS (Maximum Ratings indicate sustained limits beyond which damage to the device may occur.
Voltage parameters are absolute voltages referenced to ground.)
Parameter
Min.
–0.3
–18
Max.
+45
Unit
V
Supply Voltage (VBAT), Load Dump
Supply Voltage (KA_VBAT, VIGN), Load Dump
Supply Voltages (VDDH, VPP, VDD3_3, VDDL, VKAM)
Supply Voltages (VREF1, VREF2, VREF3, VSEN)
CANL, CANH (0<VBAT<18 VDC no time limit)
+45
V
–0.3
–2.0
–18
+5.8
+18
V
V
+26.5
V
ESD Voltage
Human Body Model all pins
Machine Model all pins
(Note 1)
(Note 2)
–2.0
–200
+2.0
+200
kV
V
CANLesd, CANHesd
(Note 1)
(Note 2)
(Note 3)
–4.0
–200
–200
–18
+4.0
+200
+200
+45
kV
V
CANLesd, CANHesd
CANLtransient, CANHtransient
V
/SLEEP
V
REGON, VPP_EN, /HRESET, /PORESET, /PRERESET, HRT, DO, DI, CS, SCLK
CANTXD, CANRXD
–0.3
–0.3
–40
+7.0
+7.0
+125
+150
V
V
Operational Package Temperature [Ambient Temperature]
Storage Temperature
°C
°C
–65
Power Dissipation (T = 125 C)
A
8.3
5.0
5.0
W
W
W
44 HSOP
(Note 4)
(Note 4)
(Note 4)
44 QFN
54 SOICW–EP
Lead Soldering Temperature
(Note 5)
260
+150
41
C
Maximum Junction Temperature
°C
R
R
R
R
R
R
R
R
R
, Thermal Resistance, Junction to Ambient (44 HSOP)
, Thermal Resistance, Junction to Case (44 HSOP)
, Thermal Resistance, Junction to Base (44 HSOP)
, Thermal Resistance, Junction to Ambient (44 QFN)
, Thermal Resistance, Junction to Case (44 QFN)
, Thermal Resistance, Junction to Base (44 QFN)
, Thermal Resistance, Junction to Ambient (54 SOICW–EP)
, Thermal Resistance, Junction to Case (54 SOICW–EP)
, Thermal Resistance, Junction to Base (54 SOICW–EP)
(Note 6)
(Note 7)
(Note 8)
(Note 6)
(Note 7)
(Note 8)
(Note 6)
(Note 7)
(Note 8)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
θJC
θJB
θJA
θJC
θJB
θJA
θJC
θJB
0.2
3
77
1.7
5.0
52
1.2
8.1
1. Human body model: C = 100 pF, R = 1.5 kΩ.
2. Machine model: C = 200 pF, R = 10 Ω and L = 0.75 µH. In case of a discharge from pin CANL to pin GND: – 100 V < CANL transient < +100
V; in case of a discharge from pin CANH to Vcc: –150 V < CANH transient < +150 V.
3. The waveforms of the applied transients is in accordance with ”ISO 7637 part 1” test pulses 1, 2, 3a and 3b.
4. Maximum power dissipation at indicated junction temperature.
5. Lead soldering temperature limit is for 10 seconds maximum duration; contact Motorola Sales Office for device immersion soldering
time/temperature limits.
6. Thermal resistance measured in accordance with EIA/JESD51–2.
7. Theoretical thermal resistance from the die junction to the exposed pad.
8. Thermal resistance measured in accordance with JESD51–8.
2. RECOMMENDED OPERATING CONDITIONS (All voltages are with respect to ground unless otherwise noted)
Parameter
Value
4.0 to 26.5
0 to 1.2
0 to 400
0 to 120
0 to 40
Unit
V
Supply Voltages (VBAT, KA_VBAT)
Switching Regulator Output Current (I
VDDH Output Current
)
(Note 1)
A
VPRE
mA
mA
mA
mA
mA
mA
mA
mA
VDD3_3 Output Current
VDDL_B Pass Transistor Base Drive Current
VPP Output Current
0 to 150
0 to 100
0 to 125
0 to 60
VREF Output Current
VSEN Output Current
VKAM Standby Output Current (normal mode of operation)
VKAM Standby Output Current (standby mode of operation)
1. See Typical Application Diagram in Figure 1.
0 to 12
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
GENERAL
Start Up Voltage
VBAT
start
6.2
V
W
V
Power Dissipation, VBAT = 13.3 V (Buck Mode)
Undervoltage Shut Down
1.8
VBAT
UV
3.4
3.9
Battery Input Current, Power Down Mode, VIGN = 0 V; REGON = 0 V;
I
750
1000
µA
VBAT(sleep)
I
= 0 mA, VBAT = 13.3 V; Battery Voltage = 14 V
VKAM
Battery Input Current, Keep Alive Mode
VIGN = 0; I = –10 mA
12
27
mA
mA
VKAM
Power On Current, Regulator ON with no load on VDDH, VDD3_3,
VDDL, VKAM, VREF, VPP, VSEN; VBAT = 13.3 V
I
VBAT(no load)
Battery Input Current, VPRE = –1.0 A, VBAT = 4.5 V
Battery Input Current, VPRE = –1.0 A, VBAT = 9 V
Battery Input Current, VPRE = –1.0 A, VBAT = 13.3 V
Battery Input Current, VPRE = –1.0 A, VBAT = 18 V
MODE CONTROL
I
2.2
3.0
1.5
1.2
1.1
A
A
A
A
VBAT(4.5)
I
VBAT(9)
I
VBAT(13.3)
I
VBAT(18)
VIGN Input Voltage Threshold, REGON = 0 V
VBAT = 13.3 V; Battery Voltage = 14 V
V
V
2.8
1.7
3.15
2.0
3.4
2.3
V
IH
IL
VIGN Hysteresis
0.7
40
1.0
1.5
V
VIGN Pull–Down Current, REGON = 0V
VBAT = 13.3 V, Battery Voltage = 14 V, VIGN = 14 V
R
100
150
µA
PD
REGON Input High Voltage Threshold
REGON Input Low Voltage Threshold
REGON Input Voltage Threshold Hysteresis
V
1.3
0.8
0.2
10
1.65
1.35
0.3
20
2.1
1.5
0.4
50
V
V
IH
V
IL
V
Ihys
V
REGON Pull–Down Current, REGON = VDDH to V
/SLEEP Input High Voltage Threshold
R
µA
V
IL(min)
PD
V
IH
1.7
1.4
0.2
10
2.2
1.9
0.3
20
2.6
2.2
0.4
50
/SLEEP Input Low Voltage Threshold
V
V
IL
/SLEEP Input Voltage Threshold Hysteresis
V
Ihys
V
/SLEEP Pull–Down Current, /SLEEP = VDDH to V
VPP_EN Input High Voltage Threshold
VPP_EN Input Voltage Low Threshold
R
µA
V
IL(min)
PD
V
IH
1.3
0.8
10
1.65
1.35
20
2.1
1.5
50
V
V
IL
VPP_EN Pull–Down Current, VPP_EN = VDDH to V
IL(min)
R
µA
PD
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7
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
BUCK CONVERTER
Buck Converter Output Voltage, VBAT = 7.5V to 18V; I
Buck to Boost Mode Threshold Voltage
Boost to Buck Mode Threshold Voltage
N–channel power MOSFET SW1
SW1 Drain–Source Breakdown Voltage
SW1 Continuous Drain Current
=500mA
VPRE
5.4
5.6
6.7
7.2
5.8
V
V
V
LOAD
(Note 1)
(Note 1)
VBAT
VBAT
thd
thu
(Note 1)
BV
50
V
A
DSS
ID
Isc
–2.75
–2.5
SW1
SW1 Drain–Source Current Limit
–3.0
–3.5
300
A
SW1
SW1 Drain–Source On–Resistance; I = 1.0 A, VBAT = 9.0 V
D
R
mΩ
DS(on)
Error Amplifier (Design Information Only)
Input Offset Voltage
(Note 1)
V
20
80
mV
dB
MHz
V
OS
DC Open Loop Gain
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
A
VOL
BW
Unity Gain Bandwidth
1.5
4.2
0.4
1.0
200
Output Voltage Swing — High Level
Output Voltage Swing — Low Level
Output Source Current
V
OH
V
V
OL
OUT
OUT
I
I
mA
µA
Output Sink Current
Ramp Generator
Sawtooth Peak Voltage
(Note 1)
(Note 1)
V
3.5
3.0
V
V
OSC
Sawtooth Peak–to–Peak Voltage
BOOST CONVERTER
V
OSCp–p
External Power MOSFET Gate Drive SW2G
Boost Converter Output Voltage, VBAT = 4.5 V to 6.0 V
SW2G Output Voltage, Power MOSFET On
SW2G Source Continuous Current
SW2G Sink Continuous Current
(Note 1)
(Note 1)
(Note 1)
VPRE
5.9
200
180
6.0
VPRE
TBD
300
6.6
400
220
V
V
V
g
I
mA
mA
source
I
sink
AC CHARACTERISTICS:
BUCK CONVERTER
Oscillator Frequency
Freq
200
TBD
TBD
TBD
TBD
1.25
75
kHz
ns
ns
ns
ns
µs
%
SW1 Switch Turn–ON Time
SW1 Switch Turn–OFF Time
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
t
T–ON
t
T–OFF
SW2G Switch Turn–ON Time, C
gate
= pF
= pF
t
T–ON
SW2G Switch Turn–OFF Time, C
t
T–OFF
gate
OFF Time
Duty cycle
NOTE:
t
OFF
d
1. Guaranteed by design but not production tested.
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8
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
VDDH
VDDH Output Voltage, I
= –400 mA;
VDDH
4.9
–40
–20
5.0
5.1
40
V
VDDH
VDDH Load Regulation, VBAT = 13.3 V; I
VDDH
= 0 to –400 mA;
LoadRg
mV
mV
mV
VDDH
VDDH Line Regulation, VBAT = 4.0 V to 26.5 V; I
= –400 mA;
LineRg
20
VDDH
VDDH
VDDH Drop Out Voltage, VPRE – VDDH, I
Decrease VBAT until Resets asserted
= –400 mA;
V
DOV
450
VDDH
VDDH Output Current, VBAT = 4.0 V to 26.5 V
VDDH Short Circuit Current, VDDH = 0 V
I
–400
mA
mA
µA
VDDH
I
–750
0.5
–440
135
SC
VDDH Maximum Allowed Feedback Current
(Power Up Sequence Guaranteed)
(Note 1)
(Note 2)
VDDH Reset Voltage, Range of VDDH where Resets must remain
asserted
V
4.8
V
VDDH_HRST
Thermal Shutdown Junction Temperature
Thermal Shutdown Hysteresis
VDD3_3
(Note 1)
(Note 1)
TS
150
5.0
190
20
°C
°C
DIS
TS
HYS
VDD3_3 Output Voltage, I
= –120 mA;
VDD3_3
3.21
–40
–20
3.3
3.36
40
V
mV
mV
V
VDD3_3
VDD3_3 Load Regulation, VBAT = 13.3 V; I
= 0 to –120 mA
LoadRg
VDD3_3
VDD3
VDD3_3 Line Regulation, VBAT = 4.0V to 26.5V; I
= –120mA
LineRg
20
VDD3_3
VDD3
VDD3_3 Drop Out Voltage, VPRE – VDD3_3
V
DOV
2.04
I
= –120 mA; Decrease VBAT until Resets asserted
VDD3_3
VDD3_3 Output Current, VBAT = 4.0 V to 26.5 V
VDD3_3 Short Circuit Current, VDD3_3 = 0 V
I
–120
mA
mA
µA
VDD3_3
I
–320
0.5
–130
135
SC
VDD3_3 Maximum Allowed Feedback Current
(Power Up Sequence Guaranteed)
(Note 1)
(Note 2)
VDD3_3 Reset Voltage
Range of VDD3_3 where Resets must remain asserted
V
3.1
V
VDD3_HRST
Thermal Shutdown Junction Temperature
Thermal Shutdown Hysteresis
VDDL
(Note 1)
(Note 1)
TS
150
5.0
190
20
°C
°C
DIS
TS
HYS
VDDL Feedback Reference Voltage, pin VDDL_FB
VDDL
1.242
1.267
1.292
V
REF
I
= 0 to –40 mA
VDDL_B
VDDL Load Regulation, VBAT = 13.3 V; I
= 0 to –40 mA
LoadRg
–1.6
–0.8
0
%
%
VDDL_B
VDDL
VDDL Line Regulation
LineRg
0.8
VDDL
VBAT = 4.0 V to 26.5 V; I
VDDL_B
= –40 mA
VDDL Drop Out Voltage, VPRE – VDDL
= –400 mA; VBAT decreases until Resets asserted
V
1.3
V
V
V
DOV
I
VDDL
VDDL Reset Voltage,
Range of VDDL where Resets must remain asserted
(Note 1)
(Note 3)
V
0.5
VDDL
–5%
VDDL_HRST
VDDL Susceptibility to Feeding Back
(Power Up Sequence Guaranteed)
VDDL
0.187
REF
VDDL_B Drive Output Current, VBAT = 7.5V to 26.5V
I
–40
–40
mA
mA
VDDL_B
VDDL_B Drive Short Circuit Current
VDDL_B = 0V, VBAT = 7.5V to 26.5V
Isc
–100
–45
VDDL_B
VDDL_X Drive Output Current, VBAT = 4.0 V to 6 V
I
mA
mA
µA
VDDL_B
VDDL_X Drive Short Circuit Current, VDDL_X = 0V, VBAT = 4.0V to 6V
VDDL Feedback VDDL_FB Input Current, VDDL_FB = 5.0 V
Isc
–100
0
–45
2.0
VDDL_X
I
VDDL_FB
NOTE:
1. Guaranteed by design but not production tested.
2. Maximum allowed current flowing back into the regulator output.
3. Voltage fed back into the VDDL output, which still guaranties proper Power Up sequencing.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
VKAM
VKAM Feedback Reference Voltage, pin VKAM_FB
VKAM
1.242
1.267
1.292
V
REF
Normal Mode (switcher running), I
= 0 to –50mA
VKAM
VKAM Load Regulation, VBAT = 13.3 V; I = –0 to –50 mA
LoadRg
–1.6
–0.8
–1.6
0
%
%
%
VKAM
VKAM
VKAM Line Regulation, VBAT = 4.0 V to 26.5 V; I
= –50 mA
LineRg
VT
0.8
0.8
VKAM
VKAM
VKAM Tracking to VDDL Voltage, VDDL – VKAM
VKAM
VBAT = 4.0 V to 26.5 V; I
VKAM
= 0 to –50 mA, I = 0 to –400mA
VDDL
VKAM Feedback Voltage — Power Down Mode
3.0 V ≤ Battery Voltage ≤ 26.5 V, I = –12 mA
VKAM
0.675
0.5
V
V
VKAM
VKAM Reset Voltage (/PORESET)
Range of VKAM where Resets must remain asserted
V
VKAM
–5%
VKAM_HRST
VKAM Output Current (Normal Mode), VBAT = 4.0 V to 26.5 V
VKAM Output Current (Sleep Mode and when VBAT ≤ 4.0 V)
VKAM Short Circuit Current, VKAM = 0 V
I
–50
–12
mA
mA
mA
µA
VKAM
I
VKAM(sleep)
I
–140
0
–50
2.0
SC
I
VKAM_FB
VKAM Feedback VKAM_FB Input Current, VKAM_FB = 5.0 V
VKAM Output Capacitance Required, Capacitor Initial Tolerance 10%
VPP
22
100
µF
VPP 5.0V Output Voltage (Default), I
= –150 mA
VPP
VPP
4.86
3.22
5.0
3.3
5.12
3.38
V
V
VPP
VPP 3.3 V Output Voltage (Programmed by SPI)
= –150 mA
5
3
I
VPP
VPP Load Regulation, VBAT = 13.3 V; I
= 0 to –150 mA
LoadRg
–0.8
–0.4
–0.8
0.8
0.4
0.8
%
%
%
VPP
VPP
VPP Line Regulation, VBAT = 4.0 V to 26.5 V; I
= –150 mA
LineRg
VT
VPP
VPP
VPP Tracking to VDDH Voltage, VDDH – VPP,
VPP
VBAT = 4.0 V to 26.5 V; I
VPP
= 0 to –150 mA;
I
= 0 to –400 mA
VDDH
VPP Drop Out Voltage, VPRE — VPP (VPP set to default 5.0V)
= –150 mA; Decrease VBAT until VPP is out of specification
V
DOV
0.4
V
I
VPP
(less than 4.86 V)
VPP Output Current, VBAT = 4.0 V to 26.5 V
VPP Short Circuit Current, VPP = 0 V
Thermal Shutdown Junction Temperature
Thermal Shutdown Hysteresis
I
–150
mA
mA
°C
VPP
I
–360
150
5.0
–165
190
20
SC
(Note 1)
(Note 1)
TS
DIS
TS
°C
HYS
NOTE:
1. Guaranteed by design but not production tested.
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10
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
VREF1, 2, 3
VREF Output Voltage, I
= –100 mA
VREF
4.86
–40
–20
–40
5.0
5.12
40
V
VREF
VREF Load Regulation, VBAT = 13.3 V; I
VREF
= 0 to –100 mA
= –100 mA
LoadRg
mV
mV
mV
VREF
VREF Line Regulation, VBAT = 4.0 V to 26.5 V; I
VREF
LineRg
20
VREF
VREF Tracking to VDDH Voltage, VDDH – VREF,
VBAT = 4.0 V to 26.5 V, I = 0 to –100 mA;
VT
20
VREF
VREF
I
= 0 to –400 mA
VDDH
VREF Drop Out Voltage, VPRE–VREF
= –100 mA; Decrease VBAT until VREF is out of specification
V
DOV
0.4
V
I
VREF
(less than 4.86 V)
VREF Output Current, VBAT = 4.0 V to 26.5 V
VREF Short Circuit Current, VREF = –2.0 V
VREF Short to Battery Load Current, VBAT = 18 V, VREF = 18 V
VREF Leakage Current, VREF disabled, VREF = –2.0 V
I
–100
mA
mA
mA
mA
°C
VREF
I
–260
–110
40
SC
Istb
VREF
I
–2.0
150
5.0
LKVREF
Thermal Shutdown Junction Temperature
Thermal Shutdown Hysteresis
VSEN
(Note 1)
(Note 1)
TS
190
20
DIS
TS
°C
HYS
VSEN Saturation Voltage, I
= 0 to –125 mA, VBAT= 8 to 16 V
VSEN
0.2
21
V
V
VSEN
VSEN Output Voltage Limit, I
sat
= 0 to –125mA, VBAT= 16 to 26.5V
VSEN
16
17
VSEN
limit
VSEN Short Circuit Current, VSEN = –2.0 V
Isc
–290
–140
40
mA
mA
µA
°C
°C
VSEN
VSEN Short to Battery Load Current, VBAT = 18 V, VSEN = 18 V
VSEN Leakage Current, VSEN disabled, VSEN = –2.0 V
Istb
VSEN
I
200
190
20
LKVSEN
Thermal Shutdown Junction Temperature
Thermal Shutdown Hysteresis
(Note 1)
(Note 1)
TS
150
5.0
DIS
TS
HYS
NOTE:
1. Guaranteed by design but not production tested.
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11
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
SUPERVISORY OUTPUTS
Reset Voltage Thresholds
/HRESET to follow /PRERESET by 0.7 µs
VDDH Reset Upper Threshold Voltage
VDDH Reset Lower Threshold Voltage
VDD3_3 Reset Upper Threshold Voltage
VDD3_3 Reset Lower Threshold Voltage
VDDL Reset Upper Threshold Voltage
VDDL Reset Lower Threshold Voltage
/PORESET Voltage Threshold
(Note 1)
(Note 1)
5.2
V
V
V
V
V
V
4.8
3.17
1.2
(Note 1)
3.43
1.35
(Note 1)
(Notes 1, 4)
(Notes 1, 4)
VKAM Reset Upper Threshold Voltage
VKAM Reset Lower Threshold Voltage
(Notes 2, 5)
(Notes 2, 5)
1.35
V
V
V
1.2
/PRERESET, /HRESET, /PORESET Open Drain Maximum Voltage
(Note 3)
7.0
1.0
0.5
15
/PRERESET, /HRESET, /PORESET Open Drain Pull–Down Current,
mA
V
V < 0.4 V
reset
/PRERESET, /HRESET, /PORESET Low–Level Output Voltage,
IOL = 1.0 mA
/PRERESET /HRESET /PORESET Leakage Current
WAKEUP High–Level Output Voltage, IOH = –800µA
WAKEUP Low–Level Output Voltage, IOL = 1.6 mA
HRT Voltage Threshold
µA
V
VDDH–0.8
2.49
0.4
2.57
1.0
V
2.53
V
HRT Sink Current
mA
µA
V
HRT Leakage Current
5.0
HRT Saturation Voltage, HRT Current = 1 mA
0.4
AC CHARACTERISTICS:
SUPERVISORY OUTPUTS
/PORESET Delay
Delay time from VKAM in regulation and stable to the release of
/PORESET
7.0
10
10
20
15
50
ms
Reset Delay Time
µs
Time from fault on VDDH, VDD3_3, VDDL or VKAM to Reset
(/PORESET, /PRERESET)
/HRESET Delay Time
Time From /PRERESET low to /HRESET low
0.5
0.7
1.0
µs
µs
VDDH, VDDL, VREF Power Up Sequence
800
Max Power Up Sequence Time Dependent on Output Load
Characteristics.
(Note 3)
NOTE:
1. VDDH, VDD3_3, VDDL regulator outputs supervised by /PRERESET and /HRESET.
2. VKAM regulator output supervised by /PORESET.
3. Guaranteed by design but not production tested.
4. Measured at the VDDL_FB pin.
5. Measured at the VKAM_FB pin.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
CAN Transceiver (Bus Load CANH to CANL R = 60 Ω; Vdiff = V
CANH
– V
)
CANL
L
CAN Transceiver Supply Current (dominant), V
CAN Transceiver Supply Current (recessive), V
Transmitter Data Input CANTXD
= 0V
I
30
50
5
70
10
mA
mA
CANTXD
CANTXD
DD(CAN)
DD(CAN)
= VDDH
I
2.5
High–Level Input Voltage Threshold (recessive), Vdiff<0.5V
Low–Level Input Voltage Threshold (dominant), Vdiff>1.0V
High–Level Input Current, VCANTXD = VDDH
V
1.4
0.8
–5
2.0
1.4
+5
V
IH
V
V
IL
I
IH
0
µA
µA
µA
pF
Low–Level Input Current, V
CANTXD
= 0V
I
IL
–10
–10
–15
–30
–60
10
CANTXD Pull–up Current, V
= 0V to V
I
PU
CANTXD
IH(max)
CANTXD Input Capacitance
(Note 1)
C
5
I(TXD)
Receiver Data Output CANRXD
High–Level Output Voltage
V
VDDH
–0.8
VDDH
V
OH
V
= VDDH, I
CANRXD
= –0.8 mA
= 0, I
CANTXD
Low–Level Output Voltage, V
CANTXD
= 1.6 mA
V
0.4
–800
1.6
V
CANRXD
OL
High–Level Output Current, V
= 0.7VDDH
= 0.4V
I
µA
mA
CANRXD
CANRXD
OH
Low–Level Output Current, V
I
OL
BUS Lines CANH, CANL
Output Voltage CANH (recessive)
= VDDH; R = open
V
2.0
2.0
2.5
2.5
3.0
3.0
V
V
CANH(r)
V
CANTXD
Output Voltage CANL (recessive)
= VDDH; R = open
L
V
CANL(r)
O(CANH)(r)
V
CANTXD
Output Current CANH (recessive)
= VDDH; V , V
L
I
100
µA
µA
V
= 2.5V
= 2.5V
CANTXD
CANH CANL
Output Current CANL (recessive)
= VDDH; V , V
I
–100
O(CANL)(r)
V
CANTXD
CANH CANL
Output Voltage CANH (dominant), V
= 0V
= 0V
V
2.75
0.5
3.5
1.5
2.0
4.5
2.25
3.0
V
V
V
CANTXD
CANTXD
CANH(d)
Output Voltage CANL (dominant), V
V
CANL(d)
Differential Output Voltage (dominant) V
– V
V
Odiff(d)
1.5
CANH(d)
CANL(d)
V
= 0V
CANTXD
Differential Output Voltage (recessive) V
= VDDH
– V
V
0
0.5
V
CANH(r)
CANL(r)
Odiff(r)
V
CANTXD
Differential Input Common Mode Voltage Range
Differential Receiver Threshold Voltage (recessive)
= VDDH, V < 0.4V, – 2.0V < V < 7.0V
CM
V
CM
–2.0
0.5
7.0
1.0
V
V
V
0.75
0.2
RXDdiff(th)
V
CANTXD
CANRXD
Differential Receiver Input Voltage Hysteresis
V
0.10
–70
0.30
V
Idiff(hys)
Short Circuit Output Current CANH
I
–200
mA
SC(CANH)
V
= – 8.0V, V = 0V
CANTXD
CANH
Short Circuit Output Current CANL
= VBAT = 18V, V
I
70
200
mA
SC(CANL)
V
= 0V
CANL
CANTXD
Loss of Ground — see Figure 11. Refer to Figure 10 for loading considerations.
Output Leakage Current CANH, V
CANH
= –18V
= –18V
I
–2.0
–2.0
2.0
2.0
mA
mA
OLKG(CANH)
Output Leakage Current CANHL, V
CANL
I
OLKG(CANL)
Loss of Battery — see Figure 12. Refer to Figure 10 for loading considerations.
Input Leakage Current CANH, V
= 6.0V
= 6.0V
I
–800
–800
800
800
µA
µA
CANH
ILKG(CANH)
Input Leakage Current CANHL, V
I
ILKG(CANL)
CANL
NOTE:
1. Guaranteed by design but not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
CAN Transceiver (Continued) (Bus Load CANH to CANL R = 60 Ω; Vdiff = V
– V
)
CANL
L
CANH
CANH,CANL impedance
CANH Common Mode Input Resistance
R
5.0
5.0
25
25
50
50
kΩ
kΩ
%
i(CM)CANH
CANL Common Mode Input Resistance
R
i(CM)CANL
i(CM)MCAN
CANH, CANL Common Mode Input Resistance Mismatch
R
–3.0
3.0
100(R
iCANH
– R
)/[ (R
+ R
)/2]
i(CM)CANL
i(CM)CANL
iCANH
Differential Input Resistance
CANH Input Capacitance, V
R
25
50
7.5
75
20
20
10
kΩ
pF
pF
pF
I(dif)
= VDDH
= VDDH
(Note 1)
C
I(CANH)
CANTXD
CANTXD
CANL Input Capacitance, V
(Note 1)
C
7.5
I(CANL)
Differential Input Capacitance, C
INCANH
– C
,
C
3.75
INCANL
I(CANdif)
V
= VDDH
(Note 1)
CANTXD
Thermal Shutdown
Thermal Shutdown Junction Temperature
Thermal Shutdown Hysteresis
(Note 1)
(Note 1)
TS
150
5.0
190
20
°C
°C
DIS
TS
HYS
AC CHARACTERISTICS:
CAN Transceiver
Timing Characteristics
See Figure 2, CANTXD = 250 kHz square wave; CANH & CANL Load R = 60 Ω differential.
L
Delay CANTXD to Bus Active, C = 3nF
t
50
80
ns
ns
ns
ns
L
onTXD
offTXD
onRXD
offRXD
Delay CANTXD to Bus Inactive, C = 10pF
t
L
Delay CANTXD to CANRXD, Bus Active, C = 3nF
t
t
120
190
L
Delay CANTXD to CANRXD, Bus Inactive, C = 10pF
L
NOTE:
1. Guaranteed by design but not production tested.
VDDH (5V)
0 V
CANTxD
CANH = 3.5V (Dominant bit)
CANH (Recessive bit)
CANL (Recessive bit)
Vdiff
2.5 V
CANL = 1.5V (Dominant bit)
0.9 V
Vdiff
0.5 V
VDDH (5V)
0 V
CANRxD
0.7VDDH
0.3VDDH
tonTxD
tonRxD
toffTxD
toffRxD
Figure 2. CAN Delay Timing Waveform
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
A
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
SPI
DO Output High Voltage, I
= –100 µA
V
4.2
V
V
OH
= 1.6 mA
OH
DO Output Low Voltage, I
V
0.4
10
OL
OL
DOLkg
DO Tri–state Leakage Current, CS = 0
CS, SCLK, DI Input High Voltage
I
–10
2.7
1.7
0.8
10
µA
V
V
3.1
2.1
1.0
20
3.5
2.5
1.2
50
IH
CS, SCLK, DI Input Low Voltage
V
V
IL
CS, SCLK, DI Input Voltage Threshold Hysteresis
V
V
Ihys
SPI_PD
CS, SCLK, DI Pull–Down Current,
CS, SCLK, DI = VDDH to V
IL(min)
I
µA
AC CHARACTERISTICS:
SPI
NOTES: MPC565 QSMCM/ SPI set for CPHA = 0 & CPOL = 0. *Assumes MPC565 SCLK rise and fall times of 30 ns, DO load = 200pF
–
Transfer Frequency
SCLK Period
fop
tsck
tlead
tlag
tsckhs
tsckls
tsus
ths
dc
200
105
50
70
70
16
20
–
5.00
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
Enable Lead Time
–
3
Enable Lag Time
–
4
SCLK High Time*
–
5
SCLK Low Time*
–
6
7
SDI Input Setup Time
SDI Input Hold Time
SDO Access Time
–
–
8
ta
75
100
75
–
9
SDO Disable Time
SDO Output Valid Time
SDO Output Hold Time
Rise Time (Design Information)
Fall Time (Design Information)
CS Negated Time
tdis
tvs
–
10
–
11
tho
0
12
(Note 1)
(Note 1)
(Note 1)
tro
–
30
30
–
13
tfo
–
14
tcsn
500
NOTE:
1. Guaranteed by design but not production tested.
3
14
20% and 70% of Vdd typ.
CS
2
8
4
1
SCLK
5
10
9
11
DON’T
CARE
DO
DI
LSB OUT
DATA
MSB OUT
1213
6
7
LSB IN
DATA
MSB IN
Figure 3. SPI Timing Diagram
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
4. FUNCTIONAL DESCRIPTION
The 33394 is an integrated buck regulator/linear supply
output are brought out to enable the control loop to be
externally compensated. The compensation technique is
described in paragraph 5.2.3. Buck Converter Feedback
Compensation in the Application Information section. In
order to improve line rejection, feed forward is implemented in
the ramp generator. The feed forward modifies the ramp slope
in proportion to the VBAT voltage in a manner to keep the loop
gain constant, thus simplifying loop compensation. At startup,
a soft start circuit lowers the current limit value to prevent
potentially destructive in–rush current.
specifically designed to supply power to the Motorola
MPC55x/MPC56x microprocessors. A detailed functional
description of the Buck Regulator, Linear Regulators, Power
Up/Down Sequences, Thermal Shutdown Protection, Can
Transceiver Reset Functions and Reverse Battery Function
are given below. Block diagram of the 33394 is given in Figure
1. The 33394 is packaged in a 44 pin HSOP, 54 pin SOICW
and the 44 pin QFN.
4.1. Input Power Source (VBAT, KA_VBAT & VIGN)
The VBAT and KA_VBAT pins are the input power source
for the 33394. The VBAT pins must be externally protected
from vehicle level transients greater than +45 V and reverse
battery. See typical application diagram in Figure 1. The VBAT
pins directly supply the pre–regulator switching power supply.
All power to the linear regulators (except VKAM in the power
down mode) is supplied from VBAT through the switching
regulator. VKAM power is supplied through VBAT input pins
and switching regulator when the 33394 is awake. When the
microprocessor is in a power down mode (no VDDH or VDDL
supply), the current requirement on VKAM falls to less than 12
mA. During this period the VKAM current is supplied from the
reverse battery protected KA_VBAT input.
The KA_VBAT supply pin is the power source to the Keep
Alive Memory regulator (VKAM) in power down mode. Power
is continuously supplied regardless of the state of the ignition
switch (VIGN input). The KA_VBAT input is reverse battery
protected but requires external load dump protection (refer to
Figure 1).
In Boost mode, pulse–frequency modulation (PFM) control
is utilized. The duty cycle is set to 75% and the switching
action is stopped either by the Boost Comparator, sensing the
switcher output voltage VPRE, or by the Current Limit circuit
when the switching current reaches its predetermined limit
value. This control method requires no external components.
The selection of the control method is determined by the
control logic based on the VBAT input voltage.
4.2.1. Switching Transistor (SW1)
The internal switching transistor is an n–channel power
MOSFET. The R
of this internal power FET is
DS(on)
approximately 0.25 ohm at +125 C. The 33394 has a nominal
instantaneous current limit of 3.0 A (well below the saturation
current of the MOSFET and external surface mounted
inductor) in order to supply 1.2 A of current for the linear
regulators that are connected to the VPRE pin (see Figure 1).
The input to the drain of the internal N—channel MOSFET
must be protected by an external series blocking diode, for
reverse battery protection (see Figure 1).
The VIGN pin is used as a control input to the 33394. The
regulation circuits will function and draw current from VBAT
when VIGN is high (active) or REGON is high (active) or on
CAN bus activity (WAKEUP active). To keep the VIGN input
from floating, a 10k pull–down resistor to GND should be
used. The VIGN pin has a 3.0 V threshold and 1.0 volt of
hysteresis. VIGN is designed to operate up to +26.5 volt
battery while providing reverse battery and +45voltloaddump
protection. The input requires ESD, and transient protection.
See Figure 1 for external component required.
4.2.2. Bootstrap Pin (BOOT)
An external bootstrap 0.1 µF capacitor connected between
SW1 and the BOOT pin is used to generate a high voltage
supply for the high side driver circuit of the buck controller. The
capacitor is pre charged to approximately 10V while the
internal FET is off. On switching, the SW1 pin is pulled up to
VBAT, causing the BOOT pin to rise to approximately
VBAT+10V — the highest voltage stress on the 33394.
4.2.3. External MOSFET Gate Drive (SW2G)
This is an output for driving an external FET for boost mode
operation. Due to the fact that the gate drive supply voltage is
VPRE the external power MOSFET should be a logic level
4.2. Switching Regulator Functional Description
A block diagram of the internal switching regulator is shown
in Figure 4. The switching regulator incorporates circuitry to
implement a Buck or a Buck/Boost regulator with additional
device. It also has to have a low R
for acceptable
DS(on)
efficiency. During buck mode, this gate output is held low.
external components. A high voltage, low R
power
DS(on)
MOSFET is included on chip to minimize the external
components required to implement a Buck regulator. The
power MOSFET is a sense FET to implement current limit. For
low voltage operation, a low side driver is provided that is
capable of driving external logic level MOSFETs. This allows
a switching regulator utilizing Buck/Boost topology to be
implemented. Two independent control schemes are utilized
in the switching regulator.
In Buck mode, voltage mode pulse–width modulation
(PWM) control is used. The switcher output voltage divided by
an internal resistor divider is sensed by an Error Amplifier and
compared with the bandgap reference voltage. The PWM
Comparator uses the output signal from the Error Amplifier as
the threshold level. The PWM Comparator compares the
sawtooth voltage from the Ramp Generator with the output
signal from the Error Amplifier thus creating a PWM signal to
the control logic block. The Error Amplifier inverting input and
4.2.4. Compensation (INV, VCOMP)
The PWM error amplifier inverting input and output are
brought out to allow the loop to be compensated. The
recommended compensation network is shown in Figure 18
and its Bode plot is in Figure 19. The use of external
compensation components allows optimization of the buck
converter control loop for the maximum bandwidth. Refer to
the paragraph 5.2.3. Buck Converter Feedback
Compensation in the Application Information section for
further details of the buck controller compensation.
4.2.5. Switching Regulator Output Voltage (VPRE)
The output of the switching regulator is brought into the chip
at the VPRE pin. This voltage is required for both the switching
regulator control and as the supply voltage for all the linear
regulators.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
resistor divider and compared with the bandgap reference
voltage (see Figure 4).
Refer to Section 5 Application Information for detailed
description of the switching regulator operation.
4.2.6. Switching Regulator Output Voltage Sense
(VPRE_S)
This is the switching regulator output voltage sense input.
The switcher output voltage VPRE is divided by an internal
BOOT
SW1
VBAT
VPRE
BOOTSTRAP
SOFT
START
CURRENT
LIMIT
HS
DRIVER
VPRE
SWITCHER
MODE
ENABLE
LS
DRIVER
VPRE
SW2G
VPRE_S
BUCK &
BOOST
CONTROL
LOGIC
V
bg
40 k
PWM
COMP
E/A
–
INV
THERMAL
LIMIT
+
–
+
11.7 k
V
bg
1.25 V
FEED
FORWARD
RAMP
VCOMP
V
bg
GENERATOR
SWITCHER
OSCILLATOR
200 kHz
V
bg
+
–
VPRE
COMP
V
1.25 V
bg
+
–
BOOST
COMP
V
bg
1.25 V
Figure 4. Switching Regulator Block Diagram
output, and incorporates current limit short circuit protection
and over temperature shut down protection. This output is
intended for FLASH memory programming and includes a
dedicated enable pin (VPP_EN). The regulator enable can
also be controlled through the SPI interface but requires both
the VPP_EN pin and the SPI bit (EN_VPP bit) to be high to
enable. The selection of tracking VDDH or VDD3_3 is
controlled by the VPP_V bit in the SPI. Logic “1” selects VDDH
(default), logic “0” selects VDD3_3. The voltage output is
stable under all load/line conditions. However, the designer
must consider ripple and high frequency filtering as well as
regulator response when choosing external components. See
Table 1 for recommended output capacitor parameters.
The VPP tracking regulator should not be used in parallel
with the VDDH regulator, because this arrangement can
corrupt the proper power sequencing of the IC.
4.3. Voltage Regulator (VDDH)
The VDDH output is a linearly regulated +5.0 +/– 0.10V
voltage supply capable of sourcing a maximum of 400 mA
steady state current from VPRE (+5.6 V) for VBAT voltages
from +4.0 V to +26.5 V (+45V transient). This regulator
incorporates current limit short circuit protection and thermal
shut down protection. The voltage output is stable under all
load/line conditions. However, the designer must consider
ripple and high frequency filtering as well as regulator
response, when choosing external components. See Table 1
in the Applications Information section for recommended
output capacitor parameters.
NOTE :
Backfeeding into the VDDH output can cause problems
during the power up sequence. Refer to the Electrical
Characteristics VDDH Regulator Section for the maximum
allowed backfed current into the VDDH output.
4.5. Tracking Voltage Regulator (VREFn)
TheoutputsoftheVREF1, VREF2, VREF3linearregulators
are 100 mA at +5.0 V. They track the VDDH output. The power
supplies are designed to supply power to sensors that are
located external to the module. These regulators may be
enabled or disabled via the SPI, which also provides fault
reporting for these regulators. They are protected for short to
4.4. Tracking Voltage Regulator (VPP)
This linearly regulated +5.0 V/+3.3 V (SPI selectable)
voltage supply is capable of sourcing 150 mA of steady state
current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to
+26.5 V (up to +45V transient). It tracks the VDDH or VDD3_3
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
battery (+18 V) and short to –2.0 V. Precautions must be taken
Applications Information section for recommended output
to protect the VREF pins from exposure to transients. See
Table 1 for recommended output capacitor parameters.
capacitor parameters.
NOTES:
4.5.1. VREF Over Temperature Latch Off Feature
If either the VREF1, VREF2 or VREF3 outputs is shorted to
ground for any duration of time, an over temperature shut
down circuit disables the output source transistor once the
local die temperature exceeds +150°C to +190°C. The output
transistor remains off until the locally sensed temperature is
5°C to 20°C. below the trip off temperature. The output(s) will
periodically turn on and off until either the die temperature
decreases or until the fault condition is removed. If one of
these outputs goes into over—temperature shutdown, it will
not impact the operation of any of the other outputs (assuming
that no other package thermal or VPRE current limit
specifications are violated). Fault information is reported
through the SPI communication interface (see Figure 8).
1. The use of an EXTERNAL pass device allows the power
dissipation of the 33394 to be reduced by approximately 50%
and thereby allows the use of a thermally efficient package
such as an HSOP 44 or QFN 44. The base drive control
signal (VDDL_B) is provided by on chip circuitry. The
regulated output voltage sense signal is fed back into the on
chip differential amplifier through pin VDDL_FB. The
collector of this external pass device should be connected to
VPRE to minimize power dissipation and adequately supply
400 mA. Proper thermal mounting considerations must be
accounted for in the PCB design.
2. Backfeeding into the VDDL output can cause problems
during the power up sequence. Refer to the Electrical
Characteristics VDDL Regulator Section for the maximum
allowed backfed current into the VDDL output.
4.6. Voltage Regulator (VDD3_3)
This linearly regulated +3.3 V +/–0.06 V voltage supply is
capable of sourcing 120 mA of steady state current from
VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (+45V
transient). This regulator incorporates current limit short
circuit protection and thermal protection. When no external
pass transistor is used the VDD3_3 and the VDD3_3FB pins
must be shorted together — see Figure 22. The current
capability of the VDD3_3 output can be increased by means
of an external pass transistor — see Figure 1. When the
external pass transistor is used the VDD3_3 internal short
circuit current limit does not provide the short circuit
protection. The voltage output is stable under all load/line
conditions. However, the designer must consider ripple and
high frequency filtering as well as regulator response when
4.8. Keep–Alive/Standby Supply (VKAM)
This linearly regulated Keep Alive Memory voltage supply
tracks the VDDL (+1.25 V to +3.3 V) core voltage, and is
capable of sourcing 50 mA of steady state current from VPRE
during normal microprocessor operation and 12 mA through
KA_VBAT pin during stand–by/sleep mode. The VKAM
regulator output incorporates a current limit short circuit
protection. The output requires a specific range of capacitor
values to be stable under all load/line conditions. See Table 1
in the Applications Information section for recommended
output capacitor parameters.
NOTE :
choosing external components. See Table
1 in the
The source current for the VKAM supply output depends on
Applications Information section for recommended output
capacitor parameters.
the sleep/wake state of the 33394.
4.9. Switched Battery Output (VSEN)
NOTE :
Thisisasaturatedswitchoutput, whichtrackstheVBATand
is capable of sourcing 125 mA of steady state current from
VBAT. This regulator will track the voltage VBAT to less than
200 mV, and its output voltage is clamped at +17 V. The gate
voltage of the internal N—channel MOSFET is provided by a
charge pump from VBAT. There is an internal gate–to–source
voltage clamp. This regulator is short circuit protected and has
independent over—temperature protection. If this output is
shortedandgoesintothermalshutdown, thenormaloperation
of all other voltage outputs is not impacted. This output is
controlled by the SPI VSEN bit.
Backfeeding into the VDD3_3 output can cause problems
during the power up sequence. Refer to the Electrical
Characteristics VDD3_3 Regulator Section for the maximum
allowed backfed current into the VDD3_3 output.
4.7. Voltage Regulator (VDDL)
The output voltage of the VDDL linear regulator is
adjustable by means of an external resistor divider.
This linearly regulated +/–2% core voltage supply uses an
external pass transistor and is capable of sourcing 40 mA
base drive current typically (see application circuit, Figure 1)
of steady state current. The collector of the external NPN pass
transistor is connected to VPRE (+5.6 V) for a VBAT voltage
from +7.5 V to +26.5 V (+45V transient). The voltage output is
stable under all load/line conditions. However, the designer
must consider ripple and high frequency filtering as well as
regulator response when choosing external components.
Also, the dynamic load characteristics of the microprocessor,
relative to CPU clock frequency changes must be considered.
An additional external pass transistor, for VDDL regulation in
the Boost mode, can be added between protected battery
voltage (see Figure 1) and VDDL, with its base driven by
VDDL_X. Inthatarrangementthe33394’scorevoltagesupply
operates over the whole input voltage range VBAT = +4.0 V
to +26.5 V (up to +45V transient). See Table 1 in the
NOTE:
A short to VBAT on VREF1, VREF2, VREF3 or VSEN will
not result in additional current being drawn from the battery
under normal (+8 V to +18 V) voltage levels. Under jumpstart
condition (VBAT = +26.5 V) and during load dump condition,
the device will survive this condition, but additional current
may be drawn from the battery.
4.9.1. VSEN Over Temperature Latch Off Feature
If the VSEN output is shorted to ground for any duration of
time, an over temperature shut down circuit disables the
output source transistor once the local die temperature
exceeds +150°C to +190°C. The output transistor remains off
until the locally sensed temperature drops 5°C to 20°C below
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
the trip–off temperature. The output will periodically turn on
capacitor is used to program the timer. To minimize quiescent
current during power down modes, the RC timer current
should be drawn from one of the VDD supplies (see Figure 1).
ThethresholdontheHRTpinhaszerotemperaturecoefficient
and is set at 2.5 V.
and off until either the die temperature decreases or until the
fault condition is removed. If the VSEN output goes into
over—temperatureshutdown, itdoesnotimpacttheoperation
of any of the other outputs (assuming that no other package
thermal or VPRE current limit specifications are violated).
Fault information is reported through the SPI communication
interface (see Figure 8).
4.12. Power Up/Down Sequencing
The 33394 power up sequence is specifically designed to
meet the power up and power down requirements of the
MPC565 microprocessor. The MPC565 processor requires
that VDDH remain within 3.1 volts of VDDL during power up
and can not lag VDDL by more than 0.5 volts. This condition
is met by the 33394 regardless of load impedance. It is critical
to note that the 33394 under normal conditions is designed to
supply VKAM prior to the power up sequence on VDDH,
VDD3_3 and VDDL. During power up and power down
sequencing /PRERESET and /HRESET are held low. Power
up and power down sequencing is implemented in six steps.
During this process the reference voltage for VDDH, VDD3_3
and VDDL is ramped up in six steps. Minimum power up/down
time is dependent on the internal clock and is 800 µs.
Maximum power up/down time is also dependent on load
impedance. During the power up/down cycle, voltage level
requirements for each step of VDDH, VDD3_3 and VDDL
must be met before the supply may advance to the next
voltage level. Hence VDDH and VDDL will remain within the
3.1/0.5 V window. Figure 6 illustrates a typical power up and
down sequence.
4.10. Resets To Microprocessor
/PORESET – Power On Reset, /PRERESET — Pre Reset,
/HRESET– Hardware Reset. All the Reset pins are open drain
‘active low’ outputs, capable of sinking 1.0 mA current and
able to withstand +7.0 V. See Figure 1 and Figure 20 for
recommended pull–up resistor values and their connection.
The /PORESET pin is pulled up to the VKAM voltage by a
pull up resistor. It is connected to the microprocessor Power
OnReset(POR)pin, andisnormallyhigh. Duringinitialbattery
connect the /PORESET is held to ground by the 33394. After
the VKAM supply is in regulation and an internal 10 ms timer
has expired, the /PORESET is released. If VKAM goes out of
regulation the device will first pull the /PORESET and
/PRERESET followed by a 0.7 µs delay then /HRESET. By
/HRESET low VDDH, VDD3_3 and VDDL will start a power
down sequence. When the fault is removed a standard power
up sequence is initiated. The VKAM linear regulator output
must be out of regulation for greater than 20 µs before
/PORERSET and /PRERESET (with /HRESET 0.7 µs
delayed) are pulled low. If a fault occurs on VKAM in the
Key–Off Mode (when the VIGN is off) and the fault is then
removed the VKAM will regulate but /PORESET will not be
released until Key–On (asserting VIGN pin) allows the 10 ms
timer to run.
4.13. Regulator Enable Function (REGON)
This feature allows the microcontroller to select the delayed
shut down of the 33394 device. It holds off the activation of the
Reset signals, to the microcontroller, after the VIGN signal has
transitioned and signals the request to shutdown the VDDH,
VDD3_3, VDDL, VSEN and the VREFn supplies. This allows
the microcontroller to delay a variable amount of time, after
sensingthattheVIGNsignalhastransitionedandsignaledthe
request to shutdown the regulated supplies. This time can be
used to store data to EPROM memory, schedule an orderly
shutdown of peripherals, etc. The microcontroller can then
drive the REGON signal, to the 33394, to the low logic state,
to turn off the regulators (except for the VKAM supply).
The Reset signals (/PRERESET, /HRESET) are not
asserted when the 33394 enters Sleep Mode by asserting the
/SLEEP pin. When exiting out of Sleep Mode the 33394
asserts theResets(/PRERESET, /HRESET)duringthepower
up sequence.
The /PRERESET and /HRESET pins are pulled up to the
VKAM (see Figure 1) or to VDDL (see Figure 20). Refer to
section 5. Application Information, paragraph 5.3.
Selecting Pull–Up Resistors for detailed description of
thesetwoconnectionscenarios. The33394monitorsthemain
supply voltages VDDH, VDD3_3 and VDDL. If any of these
voltages falls out of regulation limits the /PRERESET will be
pulled down followed by the /HRESET after 0.7 µs delay, and
the power down sequence will be initiated. There are several
different scenarios how to connect the /PRERESET and
/HRESET pins to the microprocessor. Typically the
/PRERESET pin will be connected to the IRQ0 pin of the
microprocessor, and the /HRESET to the microprocessor
/HRESET pin (see Figure 5). The VDDH, VDD3_3 and VDDL
linear regulator outputs must be out of regulation for greater
than 20 µs before /PRERESET (with /HRESET 0.7 µs
delayed) are pulled low.
4.14. Regulator Shutdown Function (/SLEEP)
This feature allows for an external control element (e.g.
microprocessor) to shut down the 33394 regulators, even if
the VIGN signal (or REGON) is active, by asserting the
/SLEEP pin from high to low (falling edge transition). In this
case the 33394 initiates the power down sequence, but the
Reset signals (/PRERESET, /HRESET) arenotasserted. This
allows the microprocessor to continue to execute code when
it is supplied only from the Keep Alive supply VKAM. Whenthe
microprocessor exits sleep state by pulling /SLEEP pin high
the Resets (/PRERESET, /HRESET) are asserted during the
power up sequence.
The /SLEEP pin has an internal pull down, therefore when
its functionality is not used this pin can be either pulled up to
VKAM, VBAT, pulled down to ground or left open.
4.11. Hardware Reset Timer (HRT)
The HRT pin is used to set the delay between VDDH,
VDD3_3 and VDDL active and stable and the release of the
/HRESET and /PRERESET outputs. An external resistor and
The /SLEEP pin should not be pulled up to VDDH.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
33394
MPC56X
* VDD3_3 = 3.3V (not used by MPC56x)
Output
Supply Input
VDDH = 5.0V
VDDH, VDDA,
VFLASH5
5.0V
2.6V
VDD3_3 = 3.3V*
VDDH
VDD3_3
VDDL
NVDDL, QVDDL,
VDD, VDDSYN,
VDDF
VDDL = 2.6V
2
6
8
VIGN
4
9
10
VKAM = 2.6V
2.6V
KAPWR,
VDDSRAM1,2,3
VDDRTC
3
1
VKAM
7
11
PORESET
IRQ0
/PORESET
2.6V
2.6V
10ms
/PRERESET
/HRESET
5
HRESET
0.7 s
0.7 s
HRT DELAY
0.7 s
HRT DELAY
HRT DELAY
Figure 5. 33394 Timing Diagram
1 Module connected to the battery, VKAM starts to regulate, /PORESET is released after VKAM is in regulation for 10 ms.
2 VIGN is applied, 33394 starts power up sequence.
3 VDDH, VDD3_3, VDDL are stable and in regulation before /PRERESET and /HRESET are released (with a HRT delay
programmable by an external capacitor and resistor, HRT pin).
4 Any of VDDH, VDD3_3, VDDL voltages out of regulation initiate /PRERESET asserted. Power down sequence initiated.
5 /HRESET is asserted 0.7 s after /PRERESET
6 When fault is removed and VDDH, VDD3_3, VDDL are in regulation, the /PRERESET and /HRESET outputs are released
(with an HRT delay).
7 When VKAM goes out of regulation limits (4% below its nominal value), /PORESET, /PRERESET and /HRESET (/HRESET
with 0.7 s delay) are asserted – see Note 1.
8 33394 initiates power down sequence.
9 Fault on VKAM removed, the 33394 initiates the start up sequence.
10 When VDDH, VDD3_3, VDDL are in regulation again, the /PRERESET and /HRESET outputs are released (with an HRT
delay).
11 /PORESET is released with a 10 ms delay after the fault on VKAM was removed.
VDDH = 5.0 V
VDD3_3 = 3.3 V
LESS THAN 3.1 V
VDDL = 2.6 V*
0 V
POWER UP SEQUENCE
POWER DOWN SEQUENCE
*NOTE: VDDL = 2.6 V for MPC565
Figure 6. 33394 Power Up/Down Sequence
* VKAM voltage level for MPC55x devices is 3.3 V and for MPC56x devices is 2.6 V.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
pin be in a logic low state whenever the chip select pin (CS)
4.15. SPI Interface to Microcontroller (Serial
Peripheral Interface)
makes any transition. For this reason, it is recommended
though not necessary, that the SCLK pin is commanded to a
low logic state as long as the device is not accessed (CS in
logic low state). When CS is in a logic low state, any signal at
the SCLK and DI pin is ignored and the DO is tri—stated (high
impedance).
The pins specified for this function are: DI (Data Input), DO
(Data Output), CS (Chip Select) and SCLK. Refer to Figure 3
for the 33394 SPI timing information. The delay, which is
needed from CS leading edge active to the first SCLK leading
edge transition (0 to 1) is approximately 125 ns. The SCLK
rate is a maximum of 5.0 MHz. The SPI function will provide
control of such 33394 features as VREFn regulator turn on/off,
VREFn fault reporting and CAN wake up feature activation.
Refer to Figure 7 & Figure 8 for the data and status bit
assignments for the 16 bit SPI data word exchange.
4.15.3. DI (Data Input) Pin
The DI pin is used for serial data input. This information is
latched into the input register on the rising edge of SCLK. A
logic high state present on DI will program a specific function
(see Figure 7 for the data bits assignments for the 16 bit SPI
data word exchange.). The change will happen with the falling
edge of the CS signal. To program the specific function of the
33394 a 16 bit serial stream of data is required to be entered
into the DI pin starting with LSB. For each rising edge of the
SCLKwhileCSislogichigh, adatabitinstructionisloadedinto
the shift register per the data bit DI state. The shift register is
full after 16 bits of information have been entered. To preserve
data integrity, care should be taken to not transition DI as
SCLK transitions from a low to high logic state.
4.15.1. CS (Chip Select) Pin
The system MCU selects the 33394 to be communicated
with through the use of the CS pin. Whenever the pin is in a
logic high state, data can be transferred from the MCU to the
33394 and vice versa. Clocked—in data from the MCU is
transferred to the 33394 shift register and latched in on the
falling edge of the CS signal. On the rising edge of the CS
signal, output status information is transferred from the output
status register into the device’s shift register. Whenever the
CS pin goes to a logic high state, the DO pin output is enabled
allowing information to be transferred from the 33394 to the
MCU. To avoid any spurious data, it is essential that the
transition of the CS signal occur only when SCLK is in a logic
low state.
4.15.4. DO (Data Output) Pin
The serial output (DO) pin is the output from the shift
register. The DO pin remains tri—state until the CS pin goes
to a logic high state. See Figure 8 for the status bits
assignments for the 16–bit SPI data word exchange. The CS
positive transition will make LSB status available on DO pin.
Each successive positive SCLK will make the next bit status
4.15.2. SCLK (System Clock) Pin
The shift clock pin (SCLK) clocks the internal shift registers
of the 33394. The serial input (DI) data is latched into the input
shift register on the rising edge of the SCLK. The serial output
pin (DO) shifts data information out of the shift register also on
therisingedgeoftheSCLKsignal. ItisessentialthattheSCLK
available. The DI/DO shifting of data follows
a
first—in—first—out protocol with both input and output words
transferring the Least Significant Bit (LSB) first.
33394 SPI Registers:
Serial Input Data/Control
Default Value
Bit
0
0
0
0
0
0
0
9
0
8
15
14
13
12
11
10
Name
Bit Definitions:
Bit 15 to 8 = 0
Default Value
Bit
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 (LSB)
VREF1
Name
WKUP
CAN_EN
VPP_V
EN_VPP
VSEN
VREF3
VREF2
Bit Definitions:
Bit 7 — WKUP: WAKEUP activation. WKUP = 1: WAKEUP pin will signal CAN bus activity
Bit 6 — CAN_EN: Enables CAN receiver, will draw small current during power off
Bit 5 — VPP_V: Set VPP reference to 5V (1) or 3.3V (0), default is 5V
Bit 4 — EN_VPP: – Used to turn the VPP regulator off and on from the MCU
Bit 3 — VSEN: – Used to turn the VSEN regulator off and on from the MCU
Bit 2 — VREF3: – Used to turn the VREF3 regulator off and on from the MCU
Bit 1 — VREF2: – Used to turn the VREF2 regulator off and on from the MCU
Bit 0 — VREF1: – Used to turn the VREF1 regulator off and on from the MCU
Figure 7. SPI Input Data/ Control Register
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
33394 SPI Registers:
Serial Output Data/Status
Default Value
Bit
0
0
0
0
0
0
0
9
0
8
15
14
13
12
11
10
Name
Bit Definitions:
Bit 15 to 8 = 0
Default Value
Bit
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0 (LSB)
VREF1–I
Name
VSEN–T
VREF3–T
VREF2–T
VREF1–T
VSEN–I
VREF3–I
VREF2–I
Bit Definitions:
Bit 7 — VSEN–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 6 — VREF3–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 5 — VREF2–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 4 — VREF1–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 3 — VSEN–I: – Will be set (1), if a current limit condition exists
Bit 2 — VREF3–I: – Will be set (1), if a current limit condition exists
Bit 1 — VREF2–I: – Will be set (1), if a current limit condition exists
Bit 0 — VREF1–I: – Will be set (1), if a current limit condition exists
NOTES: # individual thermal limit latch will clear on the trailing edge of the SPI CS signal
Figure 8. SPI Output Data/ Status Register
controller will contain one of the terminations. The other
termination should be as close to the other ”end” of the CAN
Bus as possible. The termination provides a total of 60 Ω
differential resistive impedance for generation of the voltage
difference between CANH and CANL. Current flows out of
CANH, through the termination, and then through CANL and
back to ground. The CAN bus is not defined in terms of the bus
capacitance. A filter capacitor of 220 pF to 470 pF may be
required. The maximum capacitive load on the CAN bus is
then 15 nF (not a lumped capacitance but distributed through
the network cabling). Refer to Figure 9.
4.16. CAN Transceiver
The CAN protocol is defined in terms of ’dominant’ and
’recessive’ bits. When the digital input (CANTXD) is a logic ”0”
(negated level, dominant bit), CANH goes to +3.5 V (nominal)
and CANL goes to +1.5 V (nominal). The digital output will also
be negated. When the digital input is logic ”1” (asserted level,
recessive bit), CANH and CANL are set to +2.5 V (nominal).
The corresponding digital output is also asserted.
4.16.1. CAN Network Topology
There are two 120 Ω (only two), terminations between the
CANHandCANLoutputs. Themajorityofthetime, themodule
Common Mode Choke
Max : 31 Remotes
Vehicle Term.
PCM
2.2 mH
CANH
CANL
470 pF*
470 pF*
470 pF*
120
120
470 pF*
*Optional
Figure 9. CAN Load Characteristics
sensed on the CAN bus pins, the 33394 will perform a power
up sequence and will provide the microprocessor with
indication (WAKEUP pin high) that wake up occurred from a
CAN message. The 33394 may be placed back in low
quiescent mode by pulling the /SLEEP pin from high to low.
4.16.2. CAN Transceiver Functional Description
A block diagram of the CAN transceiver is shown in Figure
10. A summary of the network topology is shown in Figure 9.
The transceiver has wake up capability controlled by the state
of the SPI bit WKUP. This allows 33394 to enter a low power
mode and be awakened by CAN bus activity. When activity is
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
The Wake–up function can be disabled through SPI by setting
the WKUP bit to 0.
input drives the outputs to a differential (dominant) voltage,
where the CANH output is +3.5 V and the CANL output is +1.5
V. A logic ‘1’ input drives the outputs to their idle (recessive)
state, where the CANH and CANL outputs are +2.5 V. An
internal pull–up to VDDH shall guarantee a logic ”1” input level
if this input is left open. On power–up, or in the event of a
thermal shutdown, this input must be toggled high and then
low to clear the thermal fault latch. The faulted CAN bus
output(s) will remain disabled until the thermal fault latch is
cleared. The CAN bus data rate is determined by the data rate
of CANTXD.
The CAN transceiver of the 33394 is designed for
communications speeds up to 1.0 Mbps. The use of a
common mode choke may be required in some applications.
When the 33394 CAN transceiver physical interface is not
used in the system design, the CAN bus driver pins CANH and
CANL should be shorted together.
4.16.3. CANH
CANH is an output driver stage that sources current on the
CANH output. It’s output follows CANL, but in the opposite
polarity. The output is short circuit protected. In the event that
battery or ground is lost to the module, the CANH transmitter’s
output stage is disabled.
4.16.6. CANRXD
This is a CMOS compatible output used to send data from
the CAN bus pins, CANH and CANL, to the microprocessor.
When the voltage differential between CANH and CANL is
under the differential input voltage threshold (recessive state),
CANRXD is logic ‘1’. When the voltage differential between
CANH and CANL is over the voltage threshold (dominant
state), CANRXD is logic ‘0’. In standby mode, input voltage
threshold remains the same. There is a minimum of 0.1 V of
hysteresis between the high and low (and vice versa)
transition points.
4.16.4. CANL
CANL is an output driver stage that sinks current on the
CANL output. The sink type output is short circuit protected.
In the event that battery or ground is lost to the module, the
CANL transmitter’s output stage is disabled.
4.16.5. CANTXD
CANTXD input comes from the microcontroller and drives
that state of the CAN bus pins, CANH and CANL. A logic ‘0’
OverTemp
Sense &
Hysteresis
VDDH
VDDH
CANH
CANL
Complimentary
High/Low Side
Drivers w/
CAN_EN
10 µA
0.8 – 2.0 V
CANTXD
CANRXD
Current Limit
25 k
5 k
0.5 – 1.0 V
2.5 V
+
+
–
–
AWAKE
CAN_EN
5 k
CANRXD
25 k
Figure 10. CAN Transceiver Block Diagram
on the module level in Figure 11. The nomenclature is suited
to a test environment. In the application, a loss of ground
condition results in all I/O pins floating to battery voltage. In
this condition, the CAN bus must not source enough current
to corrupt the bus.
4.16.7. CAN Over Temperature Latch Off Feature
If the CANH or CANL output is shorted to ground or battery
for any duration of time, an over temperature shut down circuit
disables the output stage. The output stage remains latched
off until the CANTXD input is toggled from a logic ’1’ to a logic
’0’ to clear the over temperature shutdown latch. Thermal
shutdown does not impact the remaining functionality of the
IC.
4.16.9. CAN Loss of Assembly Battery
The loss of battery condition at the IC level is that the power
inputpinsoftheICseeinfiniteimpedancetothebatterysupply
voltage (depending upon the application) but there is some
undefined impedance looking from these pins to ground. In
this condition, the CAN bus must not sink enough current to
corrupt the bus. Refer to Figure 12.
4.16.8. CAN Loss of Assembly Ground
The definition of a loss of ground condition at the device
levelisthatallpinsoftheIC(excludingtransmitteroutputs)will
see very low impedance to VBAT. The loss of ground is shown
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
ICANH
ICANH
ICANL
Battery
16 V
Battery
CANH
CANL
CANH
CANL
VBAT
VIGN
VBAT
ICANL
VIGN
51
51
POWER
OAK
POWER
OAK
+
+
–
–2V
+6V
–
VDDH
VDDH
68
43
43
68
43
43
+
–
+
–
–2V
+6V
VDD3_3
VDDL
GND
VDD3_3
VDDL
GND
Figure 11. CAN Loss of Ground Test Circuit
Figure 12. CAN Loss of Battery Test Circuit
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
5. APPLICATION INFORMATION
This section provides information on external components
reasonable for most of practical applications. Then the ESR
of the output capacitor has to satisfy the following condition:
that are required by the 33394. The IC is designed to operate
in an automotive environment. Conducted immunity and
radiated emissions requirements have been addressed
during the design. However, the IC requires some external
protection.
V
o
ESR
I
o
Where:
Protection is required for all pins connected directly to
battery. The module designer should use an MOV or another
transient voltage suppressor in all cases, when the load
dump transition exceeds + 45 volts with respect to ground.
Protection should also include a reverse battery protection
diode (or relay) and input filter. This is required to protect the
33394 from ESD and +/– 300V ignition transients. Typical
configurations are shown in Figure 1. Outputs and inputs
connected directly to connector pins require module level
ESD protection.
∆Vo is the maximum allowed linear regulator voltage drop
caused by the load current transient.
∆Io is the maximum current transient, which can occur due to
the abrupt step in the linear regulator load current.
In this example the VDDH output with the 400 mA load step
is considered with the maximum voltage drop of 100mV. This
gives the output capacitor’s maximum ESR value of:
100 mV
400 mA
ESR
250 m
5.1. Selecting Components for Linear Regulators
The output capacitor of the linear regulator serves two
different purposes. It maintains the linear regulator loop
stability, and it provides an energy reservoir to supply current
during very fast load transients. This is especially true when
supplying highly modulated loads like microcontrollers and
other high–speed digital circuits. Due to the limited
bandwidth of the linear regulators, the output capacitor is
selected to limit the ripple voltage caused by these abrupt
changes in the load current. During the fast load current
transients, the linear regulator output capacitor alone
controls the initial output voltage deviation. Hence, the output
capacitor’s equivalent series resistance (ESR) is the most
critical parameter.
The outputs, which do not experience such severe
conditions (the VREF e.g.), use the output capacitor mainly
for stability purpose, and therefore its capacitance value can
be significantly smaller. The typical output capacitor
parameters are: C = 1.0 µF; ESR = 2.0 ohms. When a
ceramic 1 µF capacitor is used, the ESR can be provided by
a discrete serial resistor (see Figure 20).
This level of ESR requires a relatively large capacitance. In
order to maintain the linear regulator stability and to satisfy
large load current steps requirements the solid tantalum
capacitor 100µF/10V with ESR = 200 mΩ. One device that
meets these requirements is the TPSC107K010S020
tantalum capacitor from the AVX Corporation.
V
ESR
I
o
200 m
400 mA
80 mV
ESR
In the next step, the voltage drop associated with the
capacitance can be calculated:
I
o
t
0.4 A
100
5
F
s
V
20 mV
C
C
Where:
C is the output capacitance.
t is the linear regulator response time.
∆I is the maximum current transient, which can occur due to
o
the abrupt step in the linear regulator load current.
Assuming that the capacitor ESL is negligible, the total
voltage drop in the voltage regulator output caused by the
current fast transient can be calculated as:
The following example shows how to determine the output
capacitance for a heavily loaded output supplying digital
circuits.
V
V
V
C
80 mV 20 mV
100 mV
total
ESR
A ceramic capacitor with capacitance value 10nF should
be placed in parallel to provide filtering for the high frequency
transients caused by the switching regulator.
Properly sized decoupling ceramic capacitor close to the
microprocessor supply pin should be used as well. Table 1
shows the suggested output capacitors for the 33394 IC
linear regulator outputs.
5.1.1. Selecting the Output Capacitor Example:
The output capacitance must be selected to provide
sufficiently low ESR. The selected capacitor must have an
adequate voltage, temperature and ripple current rating for
the particular application.
In order to calculate the proper output capacitor
parameters, several assumptions will be made.
Other factors to consider when selecting output capacitors
include key off timing for memory retention. Though the
VKAM is not a heavily loaded output, the VKAM output
capacitor has to have a sufficiently large capacitance value to
supply current to the microcontroller for a certain time after
battery voltage is disconnected.
1) During the very fast load current transients, the linear
regulator can not supply the required current fast enough,
and therefore for a certain time the entire load current is
supplied by the output capacitor. 2) The capacitor’s
equivalent series inductance (ESL) is neglected. These
assumptions can greatly simplify the calculations, and are
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
Table 1. Linear Regulator Output Capacitor Examples
Output
SMD tantalum
Value/Rating
Part n. (AVX Corp.)
VDDH
VPP
100uF/10V
33uF/10V
68uF/6.3V
100uF/6.3V
10uF/16V
100uF/6.3V
TPSC107K010S0200
TPSB336K010S0650
TPSC686K006S0200
TPSC107K006S0150
THJB106K016S
VDD3_3
VDDL
VREFx
VKAM*
TPSC107K006S0150
inductor input voltage is clamped one forward diode drop
below ground. The inductor current during the off time is:
5.2. Switching Regulator Operation
The 33394 switching regulator circuit consists of two basic
switching converter topologies. One is the typical voltage
mode PWM step–down or buck regulator, which provides
pre–regulated VPRE voltage (+5.6 V) during normal
operating conditions.
(V
V
)
t
off
o
fwd
L
i
L(off)
Where:
During cold start–up, when the car battery is weak, the
input voltage for the 33394 can fall below the lower operating
limit of the step–down converter. Under such conditions, the
step–up or boost converter provides the required value of the
VPRE voltage. The following paragraphs describe the basic
principles of the two converters operation.
t
is the off–time of the power switch.
off
i
is the inductor current during the off time.
is forward voltage drop across the rectifier.
L(off)
V
fwrd
During the steady state operation i
= i = ∆I , and
L(on) L(off) L
V /V = d
in
Buck Mode
o
One switching cycle of the step–down converter operation
has two distinct parts: the power switch on state and the off
state. When the power switch is on, one inductor terminal is
connected to the input voltage Vin, and the other inductor
Where:
d is the duty cycle, and d = t /T.
on
T is switching period, T = 1/f.
f is the frequency of operation.
terminal is the output voltage V . During this part of the
o
switching period the rectifier (catch diode) is back biased,
and the current ramps up through the inductor to the output:
Two relations give the ripple voltage in the output capacitor
C . The first describes ripple voltage caused by current
(V
V )
o
L
t
on
o
in
i
L(on)
variation upon the output capacitance C :
o
I
L
Where:
Vpp
Co
8Co
f
t
is the on–time of the power switch.
is the input voltage.
The other is caused by current variations over the output
capacitor equivalent series resistance ESR:
on
V
in
V is the output voltage.
o
Vpp
ESR
I
L
R
ESR
Practically, the ESR contributes predominantly to the buck
converter ripple voltage:
i
is the inductor current during the on–time.
L(on)
L is the inductance of the inductor L.
V
>>V
ppCo
ppESR
During the on time, current ramping through the inductor
stores energy in the inductor core.
During the off time of the power switch, the input voltage
source Vin is disconnected from the circuit. The energy
stored in the core forces current to continue to flow in the
same direction, the rectifier is forward biased and the
The inductor peak current can be calculated as follows:
1
2
Ipk
I
o
I
L
L
Where:
I is the average output current.
o
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
I
L
I
I
L
Q
+
I
O
I
L
L
Q
+
V
O
R
LOAD
I
D
C
O
D
V
in
–
I
Q
I
LO
L
+
–I
D
I
+
LOAD
R
LOAD
C
O
V
in
V
out
–
POWER SWITCH ON
V
D
V
fwd
I
LO
+
I
+
LOAD
R
LOAD
V
Co
C
O
V
D(fwd)
V
out
t
t
–
on off
t
POWER SWITCH OFF
T
Figure 13. Basic Buck Converter Operation and its Waveforms
(V
Boost Mode
V )
in
L
t
off
o
i
L(off)
The operation of the boost converter also consists of two
parts, when the power switch is on and off. When the power
switch turns on, the input voltage source is placed directly
across the inductor, and the current ramps up linearly
through the inductor as described by:
Where:
is the off–time of the power switch.
t
off
V is the output voltage.
o
V
t
on
in
i
L(on)
During the steady state operation i
= i = ∆I , and
L(on) L(off) L
L
Where:
V
V
in
o
d
V
o
t
on
is the on–time of the power switch.
is the input voltage.
Where:
V
in
d is the duty cycle, and d = t /T.
on
i
is the inductor current during the on–time.
L(on)
T is switching period, T = 1/f.
f is the frequency of operation.
L is the inductance of the inductor L.
The current ramping across the inductor stores energy
within the core material. In order to maintain steady–state
operation, the amount of energy stored during each switching
cycle, times the frequency of operation must be higher (to
cover the losses) than the power demands of the load:
The ripple voltage of the boost converter can be described
as:
(V
V )
in
f
I
C
o
o
o
Vpp
Co
V
o
1
2
P
LI2
f
P
out
sto
pk
Where:
When the power switch turns off again, the inductor voltage
flies back above the input voltage and is clamped by the
forward biased rectifier at the output voltage.
The current ramps down through the inductor to the output
until the new on time begins or, in case of discontinuous
mode of operation, until the energy stored in the inductor core
drops to zero.
V
is the ripple caused by output current.
ppCo
The portion of the output ripple voltage caused by the ESR
of the output capacitor is:
V
o
1
2
Vpp
ESR
(I
o
I )
L
R
ESR
V
in
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
Where I is the average output current.
V
V
o
o
in
1
2
Ipk
I
o
I
L
L
The inductor peak current is given by the following
equation:
I
L
I
L
I
D
+
–
I
L
L
D
+
V
O
R
LOAD
I
Q
Q
C
O
V
in
I
D
I
O
+
I
Q
I
+
LOAD
R
LOAD
L
I
ON
C
O
V
in
V
out
–
POWER SWITCH ON
V
Q
I
L
+
I
+
I
OFF
LOAD
R
LOAD
V
Co
C
O
V
IN
V
out
t
t
–
t
on off
POWER SWITCH OFF
T
Figure 14. Basic Boost Converter Operation and its Waveforms
5.6 V and the linear regulators require a minimum of 0.4 V
dropout voltage. This leaves a ±0.2 V window for the
peak—to–peak output voltage ripple. Assuming the following
conditions:
5.2.1. Switching Regulator Component Selection
The selection of the external inductor L2 and capacitor C2
values (see Figure 15) is a compromise between the two
modes of operation of the switching regulator, the pre
regulated voltage VPRE and the dropout voltage of the linear
regulators. Ideal equations describing the peak—peak
inductor current ripple, peak—peak output voltage ripple and
peak inductor current are shown below. Since the switching
regulator will work mostly in the buck mode, the inductor and
the switcher input and output capacitor were selected for
optimum buck controller performance, but also taking into
account the restriction placed by adopting the boost
converter as well.
V (typ) = 13.5 V
in
I = 1.2
o
VPRE = 5.6 V (+6 V in the boost mode)
f = 200 kHz
V
= V
= 0.5 V
fwd2
fwd1
Maximum allowed output voltage ripple in the buck mode
= 0.2 V/2 = 0.1 V (to allow for process and
V
pp(max)
temperature variations).
I
Q
V
V
RL
I
L
V
fwd2
RDS(on)
+
5.2.1.1. Selecting the Inductor
In order to select the proper inductance value, the inductor
L
Q
1
R
DS(on)
R
L
D
2
R
LOAD
ripple current ∆I has to be determined. The usual ratio of ∆I
to output current I is:
o
ESR
L
L
V
O
D
1
V
fwd1
Q
2
+
∆I = 0.3 I
L
o
V
in
C
O
As described in the previous section, and taking into
account the 33394 switcher topology (see Figure 15), the
inductor ripple current can be estimated as:
–
Figure 15. 33394 Switcher Topology
(V
V
V
)
fwd2
in
o
L
V
V
o
V
fwd2
f
The following example shows a procedure for determining
the component values. The VPRE output is set to regulate to
I
L
in
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
After substitution, the calculated inductance value is L = 45
µH, which gives 47 µH standard component value.
V
= ∆I x R
= 0.345 x 0.08 = 28 [mV]
ppESR
L
ESR
One device that meets both, the low ESR, and the
The peak–to peak ripple current value is: ∆I = 0.345 A.
temperature stability requirements is, for example, the
TPSV107K020R0085 tantalum capacitor from AVX Corp.
L
The peak inductor current is given by:
Boost Converter Power Capability
The boost converter with selected components has to be
able to deliver the required power.
I
= 0.5∆I + I = 0.5x0.345 + 1.2 = 1.37[A]
L o
Lpk
The inductor saturation current is given by the upper value
of the 33394 internal switch current limit I = 3.0 A.
lim(max)
Due to the nature of this non–compensated PFM control
technique, the Boost converter output ripple voltage is higher
than if it utilized a typical PWM control method. Therefore the
switcher output voltage level is set higher than in the Buck
mode (in the Boost mode VPRE = +6 V), in order to maintain
a sufficient dropout voltage for the 5–volt linear regulators
(VDDH, VREFs) and to avoid unwanted Resets to the
microcontroller.
Considering also the inductor serial resistance, these
requirements are met, for example by the PO250.473T
inductor from Pulse Engineering, Inc.
5.2.1.2. Selecting the Catch Diode D
1
The rectifier D current capability has to be greater than
1
calculated average current value.
The maximum reverse voltage stress placed upon this
The most stringent conditions for the 33394 boost
converter occur with the lowest input voltage:
rectifier D is given by maximum input voltage (maximum
1
transient battery voltage). These requirements are met, for
example by the HSM350 (3 A, 50 V) schottky diode from
Microsemi, Inc.
V
= 3.5 V
in(min)
I = 0.8 A
o
5.2.1.3. Selecting the Output Capacitor
Vpre = +6 V
f = 200 kHz
The output capacitor C should be a low ESR part,
o
therefore the 100 µF tantalum capacitor with 80 mΩ ESR was
chosen.
V
= V
= 0.5 V
fwd2
fwd1
From the formula for calculating the ripple voltage:
d = 0.75, duty cycle is fixed at 75% in boost mode
V
RES
I
L
V
fwd2
I
L
+
I
LIM
L
I
R
D
01
D
2
I
L1
I
02
ESR
I
Q
V
O
R
LOAD
I
L2
Q
2
+
L1 > L2
V
in
I
<
I
L1
> I
L2
C
O
I
O1 O2
–
T
t
Figure 16. 33394 Switcher Topology – Boost Mode
The input voltage drop associated with the resistance of
the internal switch Q1 and inductor series resistance can be
estimated as:
Then the maximum average input current can be
calculated as:
0.125
2
1
2
I
I
I
L
2.5
2.43[A]
inAve
pk(min)
V
I
R
D
2.5 A 0.35
0.875 V
D
pk(min)
Finally, the boost converter power capability has to be
higher than the required output power or:
Where:
is the voltage dissipated on the major parasitic
V
D
P
P
in(max)
out
is the boost converter maximum input power:
in(max)
resistances, R
series resistance R
L.
For the worst case conditions:
of the internal power switch and inductor
DSon
Where P
h is the boost converter efficiency, in our case h is
estimated to be h = 85%, and includes switching losses of the
external power switch Q2 (MOSFET) inductor and capacitors
AC losses, and output rectifier D2 (schottky) switching
losses.
R
= R + R = 0.25 + 0.1 = 0.35[Ω]
D
DSon(max)
L
I
is the minimum internal power switch current limit
pk(min)
value.
P
is the boost converter output power, which includes
out
power loss of the output rectifier D2:
Then the equation for calculating ∆I can be modified as
follows:
L
P
P
(V
V
)
I
I
o
(6 0.5) 0.8
5.2[W]
out
in
o
fwd2
V )
(V
[
V
)
(V
V )
D
f
]
V
V
o
fwd2
(V
in
)
d
in
D
I
L
L
V
(V
o
fwd2
in
D
inAve
[
]
(6 0.5) (3.5 0.875)
0.75
3.5 0.875
47 10
(3.5 0.875) 2.43 0.85
As can be seen, the boost converter input power capability
meets the required criteria.
5.42[W]
(6 0.5) 0.2 106
6
125[mA]
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
5.2.1.4. Selecting the Power MOSFET Q2
5.2.2. Input Filter Selection
The boost converter maximum output voltage plus the
voltage drop across the output schottky rectifier D2 gives the
MOSFET’s maximum drain–source voltage stress:
Since the switcher will work in the Boost mode only during
cold crank condition, the 33394 EMC (electromagnetic
compatibility) performance is not of concern during this mode
of operation. Therefore, only the Buck mode of operation is
important for selecting the appropriate input filter. For the
Buck converter topology (see Figure 13) the low impedance
3rd order filter (C3, L2, C4 and C26 in the Application
Schematic Diagram Figure 20) offers a good solution. It can
be seen from the Buck converter current waveforms that
comparatively high current pulses are drawn from the
converter’s input source. The filter inductance must be kept
minimal and the capacitor, which is placed right next to the
power switch, must be sized large enough to provide
sufficient energy reservoir for proper switcher operation.
The ESR of this input capacitor combination C4, C26 has
to be sufficiently low to reduce the switching ripple of the
switcher input node VBAT. There are three main reasons to
keep the voltage ripple of the VBAT pin at its minimum. First,
it is the EMC (electromagnetic compatibility) performance of
the switcher in the normal operating mode (buck mode).
Second, it allows a smooth transition between the boost and
buck mode of operation. Third, it helps to avoid entering an
undervoltage condition too early. A practical way to achieve
sufficiently low ESR of the switcher input capacitor, even at
low temperature extremes, is to use several high value
ceramic capacitors in parallel with a large electrolytic
capacitor. These capacitors should be physically placed as
close to the VBAT pins as possible.
BV
>V +V
= 6 V+0.5 V, as can be seen, the
dsQ2
o
fwd2
breakdown voltage parameter is not critical.
The more important in our case is the Q2 current handling
capability. The external power MOSFET has to withstand
higher currents than the upper current limit of the 33394:
I >3A
DQ2
In order to keep the power dissipation of the 33394 boost
converter to its minimum, a very low R power MOSFET
DSon
has to be selected. Moreover, due to the fact that the 33394
external MOSFET gate driver is supplied from VPRE, in
order to assure proper switching of Q2 a logic level device
has to be selected.
Last but not least, the Q2 package has to suitable for the
harsh automotive environment with low thermal resistance.
These requirements are met, for example by the
MTD20N03HDL power MOSFET from ON Semiconductor.
5.2.1.5. Selecting the Boost Converter Output
Rectifier D2
Criteria similar to that of selecting the power MOSFET was
used to select the boost converter output rectifier. Its reverse
breakdown voltage is not a critical parameter:
V
rD2
>V =6 V
o
The D2 rectifier has to withstand higher peak current than
is the 33394 internal switch upper current limit I
.
lim(max)
5.2.3. Buck Converter Feedback Compensation
A typical control loop of the buck regulator is shown in
Figure 17. The loop consists of a power processing block —
the modulator in series with an error–detecting block — the
Error (Feedback) Amplifier. In principle, a portion of the
output voltage (VPRE of the 33394 switcher) is compared to
The most important parameter is its forward voltage drop,
which has to be minimal. This parameter is also crucial for the
proper 33394 switcher functionality, and especially for proper
transition between the buck and boost modes.
Finally, its switching speed, forward and reverse recovery
parameters play a significant role when selecting the output
rectifier D2.
a reference voltage (V ) in the Error Amplifier and the
bg
difference is amplified and inverted and used as a control
input for the modulator to keep the controlled variable (output
voltage VPRE) constant.
These requirements are met, for example by the HSM350
schottky rectifier from Microsemi, Inc.
V
in
V
out
To Load
Gain Block
(Modulator)
PWM
Signal
Ramp
+
G
V
in
V
out
–
+
–
MODULATOR
H
Z
f
Feedback
Block
Z
in
–
+
V
/V = G/(1 + GH)
out in
Reference
Voltage
ERROR FEEDBACK AMPLIFIER
Figure 17. The Buck Converter Control Loop
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
C2
80
60
40
20
0
R2
CLOSED LOOP (overall)
C3
R3
R1
f
p(LC)
C1
ERROR
AMPLIFIER
f
p2
VPRE_S
f
p1
E/A
VCOMP
U1
–
+
A
2
R
f
Z2
f
Z1
MODULATOR
A
1
Ref
If
xo
–20
Figure 18. Error Amplifier Two–Pole–Two–Zero
Compensation Network
f
–40
–60
Z(ESR)
The process of determining the right compensation
components starts with analysis of the open loop (modulator)
transfer function, which has to be determined and plotted into
the Bode plot (see Figure 19). The modulator DC gain can be
determined as follows:
1
10
100
1000
f (Hz)
10 k
100 k
1 M
90
0
V
V
in
e
MODULATOR
A
DC
Where V is the maximum change of the Error Amplifier
e
voltage to change the duty cycle from 0 to 100 percent (V =
e
–90
–180
2.6 V at Vbat =14 V).
ERROR AMPLIFIER
As can be seen from Figure 19, the buck converter
modulator transfer function has a double complex pole
caused by the output L–C filter. Its corner frequency can be
calculated as:
–270
–360
1
f
p(LC)
2
LC
o
CLOSED LOOP (overall)
This double pole exhibits a —40dB per decade rolloff and
a —180 degree phase shift.
1
10
100
1000
f (Hz)
10 k
100 k
1 M
Another point of interest in the modulator’s transfer
function is the zero caused by the ESR of the output
Figure 19. Bode Plot of the Buck Regulator
capacitor C and the capacitance of the output capacitor
itself:
The frequency of the compensating poles and zeros can
be calculated from the following expressions:
o
1
1
f
f
z1
z(ESR)
2 R
C
2 R C
ESR o
2 2
The ESR zero causes +20dB per decade gain increase,
and +90 degree phase shift.
1
1
f
z2
2 (R
R )C
3
2 R C
1
3
1 3
Once the open loop transfer function is determined, the
appropriate compensation can be applied in order to obtain
the required closed loop cross over frequency and phase
margin (~60 degree) — refer to Figure 18 and Figure 19.
Figure 19 shows the 33394 Switching Regulator modulator
gain–phase plot, E/A gain–phase plot, closed loop
gain–phase plot, and the E/A compensation circuit. The
1
f
p1
2 R C
3 3
C
C
2
1
1
f
p2
2 R C C
2 R C
2 1 2
2 1
and the required absolute gain is:
frequency f
is the required cross–over frequency of the
xo
buck regulator.
R
R
2
1
A
1
In order to achieve the best performance (the highest
bandwidth) and stability of the voltage–mode controlled buck
PWM regulator the two–pole–two–zero type of compensation
was selected — see Figure 19 for the compensated Error
Amplifier Bode plot, and Figure 18 for the compensation
network. The two compensating zeros and their positive
phase shift (2 x +90 degree) associated with this type of
compensation can counteract the negative phase shift
caused by the double pole of the modulator’s output filter.
R (R
2
R )
3
1
R
R
2
3
A
2
R R
1 3
Refer to Application Schematic Diagram (Figure 20) and
Table 2 for the 33394 switcher component values.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
Where R is the HRT timer pull–up resistor,
C is the HRT timer capacitor
Table 2.
Part number
(Figure 18)
Application diagram
part number (Figure 1)
Component value
V
V
is the pull–up voltage,
is the HRT timer threshold voltage (V = 2.5V
B
th
th
R1
R2
R3
C1
C2
C3
33394 internal resistor
39.6kΩ
100kΩ
430Ω
nominal value),
R2
R1
C6
C7
C5
V
is the saturation voltage of the internal pull–down
SAT
transistor.
100pF
1.0nF
3.3nF
If the HRT timer pull–up resistor is connected to VDDH
(see Figure 1) and the resistor value is ≥ 47 k , therefore the
V
can be neglected, the formula for calculating the time
SAT
delay can be simplified to:
5.3. Selecting Pull–Up Resistors
t
0.7 RC
D
All the Resets (/PORESET, /PRERESET and /HRESET)
are open drain outputs, which can sink a maximum of 1 mA
drain current. This determines the pull–up resistor minimum
value. VKAM should be used as the pull–up source for the
/PORESET output. /PORESET is pulled low only during
initial battery connect or when VKAM is below 2.5 volts (for
VDDL = 2.6 V).
To select the /PRERESET and /HRESET pull–up resistor
connections, consider current draw during sleep modes. For
example, the pull up resistor on /PRERESET and /HRESET
should receive its source from VDDL, if the sleep mode or low
power mode of the module is initiated primarily by the state of
the VIGN pin. Refer to Figure 20 for recommended pull–up
resistor values.
5.5. Selecting the VKAM Resistor Divider
The VKAM linear regulator output voltage is divided by an
external resistor divider and compared with the bandgap
reference voltage (V ) in the input of the VKAM error
bg
amplifier. The resistor divider can be designed according to
the following formula:
R
upper
V
V
1
KAM
KAMref
R
lower
V
= 1.267 V
KAMref
Where V
is the bandgap reference voltage.
KAMref
Since the VKAM feedback pin (VKAM_FB) input current is
only a few nA, the resistor value can be selected sufficiently
high in order to minimize the quiescent current of the module.
See Figure 20 for the VKAM resistor divider recommended
values.
Another way to connect the /PRERESET and /HRESET
pull–up resistors is to connect them to the VKAM output
together with the /PORESET pull–up resistor (see Figure 1).
This is the preferable solution when the sleep or low power
mode is initiated primarily by the microprocessor. In that
case, when the 33394 is shut down by pulling the /SLEEP pin
down, all three Resets (/PORESET, /PRERESET and
/HRESET) stay high. Since they are pulled–up to the supply
voltage (VKAM) they draw no current from the VKAM and the
module quiescent current is minimized.
5.6. Selecting the VDDL Resistor Divider
The VDDL regulator resistor divider is designed according
to the same formula as described in the paragraph above
(see Figure 20).
R
upper
V
V
1
5.4. Selecting Hardware Reset Timer Components
The HRT input sets the delay time from VDDH, VDD3_3
and VDDL stable to the release of /PRERESET and
/HRESET. When sizing the delay time the module design
engineer must consider capacitor leakage, printed board
leakage and HRT pin leakage. Resistor selection should be
low enough to make the leakage currents negligible. The
Hardware Reset (/HRESET) delay can be calculated as
follows:
DDL
DDLref
R
lower
Where V
= 1.267 V
DDLref
Nonetheless, the actual resistor values should be chosen
several decades lower than in the previous example. This is
due to the fact that the VDDL linear regulator needs to be
pre–loaded by a minimum of 10 mA current in order to
guarantee stable operation. See Figure 20 for the VDDL
resistor divider recommended values.
Delay time:
(
)
V
V
V
th
)
B
(
SAT
V
t
D
RC ln[
]
V
B
SAT
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
*
D2
L2
6.8uH
D1
20BQ030
L1
47uH
JP1
MURS320T3 Q3
+Battery
Vbat
1
2
1
2
1
2
VDDH
+
C3
1.0uF/50V
C4
100uF/35V
+
C2
D3
SS25
C5 100uF/16V
3.3nF
SW1
DIP–2
Q1
R13
18R
MMSF3300R2
R1
430R
C29
1.0uF/50V
R14
4.7k
VPP_EN
C1
100nF
U1
IGN
VIGN
1.0uF/50V
C26
R3
4.7k
C28
C6
100pF
28
29
30
31
27
26
25
24
C7
1.0nF
VBAT
SW1
SW1
VKAM
VBAT
10nF
VBAT
SW1
R4
VBAT
VBAT
KA_VBAT
N/C
VIGN
VKAM
VKAM_FB
VSEN
REGON
WAKEUP
VREF1
SW1
22k
R22
100k
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SW1
+
N/C
C23
10nF
BOOT
SW2G
GND
VPRE
C24
22uF
R6
20k
C30
INV
VDDH
+
VSEN
REGON
WAKEUP
VCOMP
VPRE
VPRE_S
VDDH
VREF2
VREF3
N/C
10nF
VPRE_S
VREF1
C10
C11
10nF
VPP_EN
47uF
VPP_EN
VPP
C8
10nF
C9
1.0uF
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
N/C
37
36
35
34
DO
VREF2
VDDL_X
VDDL_B
VDDL_FB
SCLK
DI
R19
2.0R
C14
1.0uF
C15
10nF
CS
N/C
/SLEEP
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
/SLEEP
HRT
CANH
CANL
GND
R20
2.0R
CANRXD
CANTXD
VPP
+
C12
10nF
C13
10uF
VREF3
C16
1.0uF
R15
47k
C17
10nF
R8
120R
+3.3V
VDDH
+
C21
10nF
C18
1.0uF
R21
2.0R
C22
10uF
*
*
C25
C27
R9 4.7k
R10 4.7k
R11 4.7k
R12 4.7k
37
36
35
34
DO
R16 R17 R18
10k
10k
10k
SCLK
DI
VKAM
CS
Q3
VPRE
VDDL_B
Q2
MJD31C
Q3
MJD31C
VDDL_X
VDDL = 2.6V
VDDL
+
R5
110R
VDDL_FB
C15
10nF
C20
47uF
J1
R7
100R
CON/34
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted.
Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Figure 20. 33394 Application Circuit Schematic Diagram
Table 3. 33394 Evaluation Board Performance
Value
(T = 25 C, Vin = 14V)
Line Regulation
(Vin = 5.2V to 26.5V)
Load Regulation
(Vin = 14 V)
Parameter
A
V
Load
[mA]
Load
V
Load
[mA]
[mV]
5.028
5.026
5.023
5.022
5.021
3.307
2.667
2.638
[mV]
[mA]
400
150
100
100
100
120
400
60
[mV]
18
5
VDDH
400
150
100
100
100
120
400
60
10
10
8
0 to 400
0 to 150
0 to 100
0 to 100
0 to 100
0 to 120
0 to 400
0 to 60
VPP
VREF1
VREF2
VREF3
VDD3_3
VDDL
8
8
10
11
7
6
5
5
10
14
VKAM
2
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33
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
Table 4. 33394DWB Evaluation Board Bill of Material
Item
1
Qty.
1
1
3
1
1
1
1
10
4
2
1
1
1
2
1
1
1
1
1
1
1
1
2
1
1
6
1
1
1
1
1
1
1
3
3
1
1
1
Part Designator
Value/ Rating
100nF/16V, Ceramic X7R
100µF/20V
Part Number/ Manufacturer
Any manufacturer
C1
2
C2
TPSV107K020R0085, AVX Corp.
C1812C105K5RACTR, Kemet
UUB1V101MNR1GS, Nichicon
Any manufacturer
3
C3,C26,C29
1.0µF/50V
4
C4
C5
C6
C7
100µF/35V
5
3.3nF, Ceramic X7R
100pF, Ceramic X7R
1.0nF, Ceramic X7R
10nF, Ceramic X7R
1.0µF, Ceramic X7R
47µF/10V, Tantalum
10µF/16V, Tantalum
10µF/6.3V, Tantalum
22µF/6.3V, Tantalum
470pF, Ceramic X7R
30V/2A Schottky
6
Any manufacturer
7
Any manufacturer
8
C8,C11,C12,C15,C17,C19,C21,C23,C28,C30
Any manufacturer
9
C9,C14,C16,C18
Any manufacturer
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
C20,C10
TPSC476K010R0350, AVX Corp.
TPSB106K016R0800, AVX Corp.
TPSA106K006R1500, AVX Corp.
TPSA226K006R0900, AVX Corp.
Any manufacturer
C13
C22
C24
C25,C27
D1
20BQ030, International Rectifier
MURS320T3, ON Semiconductor
SS25, General Semiconductor
Terminal Block
D2
200V/3A Diode
D3
50V/2A Schottky
JP1
2–pin, 0.2 (5.1mm)
34–pin, 0.1 x 0.1
J1
PCB Header Connector
P0250.473T, Pulse Engineering
P0751.682T, Pulse Engineering
MMSF3300R2, ON Semiconductor
MJD31C, ON Semiconductor
Any manufacturer
L1
47µH
L2
6.8µH
Q1
30V/11.5A, Mosfet
100V/3A, BJT
Q2,Q3
R1
430R, Resistor 0805
100k, Resistor 0805
4.7k, Resistor 0805
22k, Resistor 0805, 1%
110R, Resistor 0805, 1%
20k, Resistor 0805, 1%
100R, Resistor 0805, 1%
120R, Resistor 0805
18R, Resistor 0805
47k, Resistor 0805
10k, Resistor 0805
2.0R, Resistor 0805
2–Position DIP Switch
Test Point, 0.038
Integrated Circuit
R2
Any manufacturer
R3,R9,R10,R11,R12,R14
Any manufacturer
R4
Any manufacturer
R5
Any manufacturer
R6
Any manufacturer
R7
Any manufacturer
R8
Any manufacturer
R13
Any manufacturer
R15
Any manufacturer
R16,R17,R18
R19,R20,R21
SW1
Any manufacturer
Any manufacturer
BD02, C&K Components
240–333, Farnell
TP1
U1
33394DWB/ Motorola
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34
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
OPTIONAL
OUTPUT
FILTER
Q4
*
D1
20BQ030
D2
L2
6.8
JP1
VPRE_S
+BATTERY
VDDH
1
2
VBAT
L1
47
D3
SS25
L3
1
2
1
2
1 2
H
MURS320T3
1.0 F/50 V
H
1.0 F/
50 V
1.0 F/
50 V
C5
3.3 nF
100 F/
35 V
C4
C26
C3
C2
100 F/
20 V
C30
33 F/16 V
Q1
SW1
DIP–2
C29
MTD20N03HDL
C1
100 nF
VPP_EN
R13
18R
R14
4.7k
VIGN
2.6V VKAM
R1
430R
R3
4.7 k
R4
22 k
U1
C23
C24
100
10 nF
F
C6
C7
1.0 nF
C28
12
44
43
42
41
40
39
38
37
36
35
34
100 pF
R6
20 k
VKAM_FB
VSEN
REGON
WAKEUP
VREF1
VPP_EN
VPP
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
INV
10 nF
R2 100 k
13
14
15
16
17
18
19
20
21
22
VCOMP
VPRE
VPRE_S
VDDH
VREF2
VREF3
DO
VPRE
5.0V @ 100mA VREF1
5.0V @ 400 mA
VDDH
PC33394FC
C8
C11
10 nF
C9
1.0
C10
47
10 nF
F
F
SCLK
DI
CS
5.0V @ 150mA VPP
5.0V @ 100 mA
VREF2
C12
10 nF
C15
10 nF
C13
33
C14
1.0
F
F
VPRE
R15
47 k
VDDH
Q2
C18
1.0
120R
MJD31C
+3.3V
R19
10R
F
R16 R17 R18
10 k 10 k 10 k
5.0V @ 100 mA
VREF3
C16
VKAM
*
*
C25
C27
R9
4.7 k
4.7 k
4.7 k
4.7 k
DO
SCLK
DI
C21
10 nF
C22
47
C17
10 nF
37
36
35
34
F
1.0
F
R10
R11
R12
VPRE
Q4
CS
VDDL_B
VDDL_X
Q3
MJD31C
Q4
MJD31C
2.6V @ 400 mA
VDDL
VDDL
R5
C19
10 nF
C20
100
110R
F
VDDL_FB
R7
J1
100R
CON/34
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted.
Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Figure 21. 33394 Application Circuit with Increased 3.3V Output Current Capability
For More Information On This Product,
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
Table 5. 33394FC Evaluation Board Bill of Material
Item
1
Qty.
1
1
3
1
1
1
1
9
1
3
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
3
1
1
6
1
1
1
1
1
1
1
3
1
1
1
1
Part Designator
Value/ Rating
100nF/16V, Ceramic X7R
100µF/20V
Part Number/ Manufacturer
Any manufacturer
C1
2
C2
TPSV107K020R0085, AVX Corp.
C1812C105K5RACTR, Kemet
UUB1V101MNR1GS, Nichicon
Any manufacturer
3
C3,C26,C29
1.0µF/50V
4
C4
C5
C6
C7
100µF/35V
5
1.5nF, Ceramic X7R
100pF, Ceramic X7R
1.0nF, Ceramic X7R
10nF, Ceramic X7R
1.0µF, Ceramic X7R
1.0µF/35V Tantalum
47µF/10V Tantalum
33µF/10V Tantalum
100µF/6.3V Tantalum
22µF/6.3V, Tantalum
470pF, Ceramic X7R
33µF/16V
6
Any manufacturer
7
Any manufacturer
8
C8,C11,C12,C15,C17,C19,C21,C23,C28
Any manufacturer
9
C18
Any manufacturer
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
C9,C14,C16
TPSA105K035R3000, AVX Corp.
TPSC476K010R0350, AVX Corp.
TPSB336K010R0500, AVX Corp.
TPSC107K006R0150, AVX Corp.
TPSA226K006R0900, AVX Corp.
Any manufacturer
C10,C22
C13
C20
C24
C27,C25
C30
TPSC336K016R0300, AVX Corp.
20BQ030, International Rectifier
MURS320T3, ON Semiconductor
SS25, General Semiconductor
Terminal Block
D1
30V/ 2A Schottky
200V/3A Diode
D2
D3
SS25
JP1
2–pin, 0.2 (5.1mm)
34–pin, 0.1 x 0.1
47µH
J1
PCB Header Connector
P0250.473T, Pulse Engineering
P0751.682T, Pulse Engineering
HF30ACC575032/ TDK
MTD20N03HDL, ON Semiconductor
MJD31C, ON Semiconductor
Any manufacturer
L1
L2
6.8µH
L3
Ferrite Bead
Q1
30V/20A Mosfet
Q2,Q3,Q4
100V/3A BJT
R1
680R, Resistor 0805
100k, Resistor 0805
4.7k, Resistor 0805
22k, Resistor 0805, 1%
110R, Resistor 0805, 1%
20k, Resistor 0805, 1%
100R, Resistor 0805, 1%
120R, Resistor 0805
18R, Resistor 0805
47k, Resistor 0805
10k, Resistor 0805
10R, Resistor 0805
2–Position DIP Switch
Test Point
R2
Any manufacturer
R3,R9,R10,R11,R12,R14
Any manufacturer
R4
Any manufacturer
R5
Any manufacturer
R6
Any manufacturer
R7
Any manufacturer
R8
Any manufacturer
R13
Any manufacturer
R15
Any manufacturer
R16,R17,R18
R19
Any manufacturer
Any manufacturer
SW1
TP1
BD02, C&K Components
240–333, Farnell
U1
Integrated Circuit
MC33394DWB/ Motorola
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36
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
L1
47µF
VPRE = 5.6V
+
C2
100µF
Input voltage +7V to +26.5V
1
2
44
SW1
SW1
VBAT
VBAT
C1
100µF
+
43
42
41
S1
ON
D1
Cb
100nF
MBRS340T
OFF
3
4
5
R5
KA_VBAT
VIGN
SW1
C5
10nF
4.7k
BAV99
BOOT
SW2G
GND
INV
330nF
40
VKAM = 2.6V @ 60mA
VKAM
Rf3
430R
Cf3
3.3nF
+
Rf2
100k
C6
10nF
39
C7
47µF
6
VKAM_FB
VSEN
R2
22k
38
37
7
8
Cf1
100pF
R1
20k
Cf2
1nF
REGON
WAKEUP
VREF1
VCOMP
VPRE
36
35
34
33
9
VREF1 = 5V @ 100mA
10
VPRE_S
+
VDDH = 5V @ 400mA
C8
10nF
C9
11
12
13
14
VPP_EN
VPP
VDDH
VDDH
VREF2
1.0µF
VPP = 5V @ 150mA
+
VREF2 = 5V @ 100mA
+
C18
C14
100µF
C15
10nF
+
3.3V @ 120mA
+
VREF3 = 5V @ 100mA
C19
10nF
32
31
30
29
C17
47µF
C16
10nF
VREF3
DO
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
/PRERESET
/HRESET
1.0µF
+
C21
10nF
C10
10nF
C11
C20
1.0µF
47µF
15
16
VPRE
SCLK
Q1
MJD44H11
DI
CS
VDDL = 2.6V @ 600mA
17
18
19
20
21
22
28
27
+
R4
/PRERESET
/HRESET
/PORESET
C12
10nF
22R
C13
/SLEEP
R3
20R
Rt
47k
100µF
26
25
HRT
CANH
CANL
GND
VDDH
Ct
1.0 µF
/PORESET
CANRXD
60R
R6 10k
R7 10k
R8 10k
24
23
VKAM
CANTXD
Figure 22. 33394 Buck–Only Application
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37
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
+12V @ 100mA
+
D3
+
C23
47µF
C22
47µF
D3
Input voltage +10V to +26.5V
1
2
44
43
42
41
–12V @ 100mA
SW1
SW1
VBAT
VBAT
C1
100µF
VPRE = 5.6V
+
S1
ON
T1
OFF
3
4
5
+
R5
KA_VBAT
VIGN
SW1
C5
10nF
D1
MBRS340T
C2
100µF
4.7k
Cb
100nF
BOOT
SW2G
GND
INV
VKAM = 2.6V @ 60mA
Rf3
430R
40
39
VKAM
+
C6
10nF
C7
6
VKAM_FB
VSEN
47µF
Cf3
3.3nF
R2
Rf2
100k
38
37
7
8
22k
R1
20k
Cf1
100pF
REGON
WAKEUP
VREF1
VCOMP
VPRE
Cf2
1nF
36
35
34
33
9
VREF1 = 5V @ 100mA
10
VPRE_S
+
VDDH = 5V @ 400mA
+
C8
10nF
C9
11
12
13
14
VPP_EN
VPP
VDDH
VDDH
VREF2
1.0µF
VPP = 5V @ 150mA
VREF2 = 5V @ 100mA
+
C18
C14
100µF
C15
10nF
+
3.3V @ 120mA
+
VREF3 = 5V @ 100mA
C19
10nF
32
31
30
29
C17
47µF
C16
10nF
VREF3
DO
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
/PRERESET
/HRESET
1.0µF
+
C21
10nF
C10
10nF
C11
C20
1.0µF
47µF
15
16
VPRE
SCLK
Q1
MJD31C
DI
CS
VDDL = 2.6V @ 400mA
17
18
19
20
21
22
28
27
26
25
+
R4
/PRERESET
/HRESET
/PORESET
C12
10nF
22R
C13
/SLEEP
R3
20R
Rt
47k
100µF
HRT
CANH
CANL
GND
VDDH
Ct
1.0 µF
/PORESET
CANRXD
R6 10k
R7 10k
R8 10k
60R
24
23
VKAM
CANTXD
Figure 23. 33394 Flyback Converter Provides Symmetrical Voltages
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38
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
PACKAGE DIMENSIONS
DH SUFFIX
44–LEAD HSOP
PLASTIC PACKAGE
CASE 1291–01
ISSUE O
PIN ONE ID
h X 45
NOTES:
E3
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
E2
E5
4X
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.150 PER SIDE. DIMENSIONS D AND E1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
44
1
D
A
22
23
EXPOSED
6. DATUMS –A– AND –B– TO BE DETERMINED AT
DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE TIEBAR
PROTRUSIONS. ALLOWABLE TIEBAR
PROTRUSIONS ARE 0.150 PER SIDE.
HEATSINK AREA
B
E1
22X
E
E4
BOTTOM VIEW
M
bbb
C B
MILLIMETERS
DIM MIN
3.000
A1 0.025
A2 2.900
MAX
3.400
0.125
3.100
A
DATUM
PLANE
Y
H
b1
A2
A
D
15.800 16.000
D1 11.700 12.600
c1
D2 0.900
1.100
1.000
c
D3
E
–––
SEATING
PLANE
13.950 14.450
C
E1 10.900 11.100
b
E2 2.500
E3 6.400
E4 2.700
2.700
7.300
2.900
1.000
1.100
M
aaa
C A
E5
L
–––
0.840
SECTION W–W
GAUGE
PLANE
L1
b
0.350 BSC
L1
0.220
0.350
0.320
0.320
0.280
W
b1 0.220
0.230
c1 0.230
c
W
L
bbb C
e
h
0.650 BSC
–––
0
0.800
8
(1.600)
aaa
bbb
0.200
0.100
DETAIL Y
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39
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
PACKAGE DIMENSIONS
FC SUFFIX
44–LEAD QFN
PLASTIC PACKAGE
CASE 1310–01
ISSUE D
PIN 1
INDEX AREA
0.1
C
9
A
2X
M
0.1
C
G
0.1
C
2X
1.00
0.75
1.0
0.8
0.05
C
5
9
(0.325)
(0.65)
0.05
0.00
SEATING PLANE
C
DETAIL G
VIEW ROTATED 90 ° CLOCKWISE
M
B
0.1 C A B
6.85
6.55
DETAIL M
PIN 1 IDENTIFIER
34
44
EXPOSED DIE
ATTACH PAD
NOTES:
1
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
33
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF–PQFP–N.
4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
REFERENCE ONLY.
6.85
6.55
0.1 C A B
5. COPLANARITY APPLIES TO LEADS, CORNER
LEADS AND DIE ATTACH PAD.
6. FOR ANVIL SINGULATED QFN PACKAGES,
40X
0.65
23
11
MAXIMUM DRAFT ANGLE IS 12°.
N
22
12
0.75
0.50
44X
0.37
0.23
44X
M
M
0.1
C A B
C
VIEW M–M
0.05
°
(45 )
(3.53)
0.60
0.24
0.60
0.24
0.065
0.015
44X
(0.25)
DETAIL N
DETAIL N
CORNER CONFIGURATION OPTION
PREFERRED CORNER CONFIGURATION
4
4
3.4
3.3
BACKSIDE
PIN 1 INDEX
(90 )
DETAIL T
0.475
0.425
0.39
2X
0.31
0.25
R
0.1
0.0
2X
0.15
DETAIL T
DETAIL M
DETAIL M
PREFERRED BACKSIDE PIN 1 INDEX
BACKSIDE PIN 1 INDEX OPTION
PREFERRED BACKSIDE PIN 1 INDEX
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40
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
PACKAGE DIMENSIONS
DWB SUFFIX
54–LEAD SOICW–EP
PLASTIC PACKAGE
CASE 1377–01
ISSUE B
10.3
5
9
7.6
7.4
C
NOTES:
2.65
2.35
B
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
52X
1
54
0.65
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
PIN 1 INDEX
5. THIS DIMENSION DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH AND PROTRUSIONS SHALL
NOT EXCEED 0.25 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4
9
18.0
17.8
C
L
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD SHALL NOT LESS THAN
0.07 MM.
B
B
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1 MM AND
0.3 MM FROM THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES
OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTER–LEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
27
28
SEATING
A
PLANE
5.15
2X 27 TIPS
54X
0.10
A
0.3
A B C
A
R0.08 MIN
0.25
°
MIN
0
C
C
GAUGE PLANE
(1.43)
A
0.1
0.0
0.9
0.5
SECTION B–B
°
°
8
0
6.6
5.9
0.30 A B C
(0.29)
BASE METAL
0.30
0.25
(0.25)
4.8
4.3
0.38
0.22
0.30 A B C
PLATING
6
M
0.13
A
B C
8
SECTION A–A
ROTATED 90 CLOCKWISE
VIEW C–C
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41
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
NOTES
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Go to: www.freescale.com
42
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
NOTES
For More Information On This Product,
43
Go to: www.freescale.com
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
33394
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
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MOTOROLA and the
logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
Motorola, Inc. 2001.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334
Technical Information Center: 1–800–521–6274
HOME PAGE: http://www.motorola.com/semiconductors/
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◊
MC33394/D
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