MC33772BSA2AE_技术文档

MC33772B

Battery cell controller IC

Rev. 6.0 — 2 April 2020

Short data sheet: technical data

1 General description

The 33772 is a SMARTMOS lithium-ion battery cell controller IC designed for automotive

applications, such as hybrid electric (HEV) and electric vehicles (EV) along with industrial

applications, such as energy storage systems (ESS) and uninterruptible power supply

(UPS) systems.

The device performs ADC conversions of the differential cell voltages and current, as well

as battery coulomb counting and battery temperature measurements. The information is

digitally transmitted through the Serial Peripheral Interface (SPI) or Transformer Isolation

(TPL) to a microcontroller for processing.

2 Features

• 5.0 V ≤ V_PWR≤ 30 V operation, 40 V transient

• 3 to 6 cells management

• 0.8 mV total cell voltage measurement error

• Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI

• Addressable on initialization

• Synchronized cell voltage/current measurement with coulomb count

• Total stack voltage measurement

• Seven GPIO/temperature sensor inputs

• 5.0 V reference supply output with 5 mA capability

• Automatic over/undervoltage and temperature detection routable to fault pin

• Integrated sleep mode over/undervoltage and temperature monitoring

• Onboard 300 mA passive cell balancing with diagnostics

• Hot plug capable

• Detection of internal and external faults, as open lines, shorts, and leakages

• Designed to support ISO 26262 up to ASIL D safety system

• Fully compatible with the MC33771 for a maximum of 14 cells

• Qualified in compliance with AEC-Q100

NXP Semiconductors

MC33772B

Battery cell controller IC

3 Simplified application diagram

RDTX_OUT+

RDTX_OUT-

VCOM

V

PWR1

PWR2

CT6

CB6

CGND

battery

reference

VPRE

VANA

AGND

DGND

+

CB6:5_C

CT5

battery

reference

CTn

CBn

SDA

6 cell

voltage

measure

EEPROM

(OPTIONAL)

SCL

SPI_COM_EN

VCP

VPRE

CT1

CB2:1_C

CB1

battery

GNDCP

FAULT

MC33772

reference

+

GPIOy

GPIOx

CSB

RESET

CSB

CTREF

MCU

MISO

SO

GNDSUB

GNDFLG

MOSI

SCLK

SI/RDTX_IN+

SCLK/RDTX_IN-

battery

reference

VCOM

ISENSE+

ISENSE-

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

current

measure

battery

reference

aaa-029758

Figure 1.ꢀSimplified application diagram, SPI use case

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Short data sheet: technical data

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MC33772B

Battery cell controller IC

RDTX_OUT+

RDTX_OUT-

VCOM

VPWR1

VPWR2

CT6

VCOM cluster # 2

CB6

CB6:5_C

CT5

+

CGND

cluster # 2

reference

VPRE

VANA

AGND

DGND

FAULT

SDA

cluster # 2

reference

CTn

CBn

6 cell

voltage

measure

EEPROM

(OPTIONAL)

SCL

SO

MC33772

CSB

CT1

CB2:1_C

CB1

SPI_COM_EN

cluster # 2

reference

RESET

+

T1

SI/RDTX_IN+

SCLK/RDTX_IN-

VCP

CTREF

GNDSUB

GNDFLG

cluster # 2

reference

GNDCP

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

VCOM cluster # 2

cluster # 2

reference

ISENSE+

ISENSE-

cluster # 2

reference

RDTX_OUT+

RDTX_OUT-

VCOM

VPWR1

VPWR2

CT6

VCOM cluster # 1

CB6

CB6:5_C

CT5

+

CGND

cluster # 1

reference

VPRE

VANA

AGND

DGND

FAULT

SDA

cluster # 1

reference

CTn

CBn

6 cell

voltage

measure

BATTERY PACK

CONTROLLER

EEPROM

(OPTIONAL)

SCL

SO

MC33772

CSB

CT1

SPI_COM_EN

cluster # 1

CB2:1_C

reference

RESET

+

MCU

T1

SI/RDTX_IN+

CB1

T1

SPI1

MC33664

SCLK/RDTX_IN-

VCP

CTREF

SPI2

GNDSUB

GNDFLG

cluster # 1

reference

GNDCP

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

VCOM cluster # 1

cluster # 1

reference

ISENSE+

ISENSE-

current

measure

cluster # 1

reference

aaa-029759

Figure 2.ꢀSimplified application diagram, TPL use case

MC33772B_SDS

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Short data sheet: technical data

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MC33772B

Battery cell controller IC

4 Applications

• Automotive: 12 V to high-voltage battery packs

• E-bikes, e-scooters

• Energy Storage Systems (ESS)

• Uninterruptible Power Supply (UPS)

• Battery junction box

5 Ordering information

5.1 Part numbers definition

MC33772B xꢁyꢁzꢁAE/R2

Table 1.ꢀPart number breakdown

Code

Option

Description

S

T

x = S (SPI communication type)

x = T (TPL communication type)

y = A (Advanced)

x

A

B

y = B (Basic)

y

z

C

P

y = C (Current)

y = P (Premium)

0

z = 0 (0 channels)

1

z = 1 (3 to 6 channels)

z = 2 (3 to 4 channels)

Package suffix

2

AE

R2

Tape and reel indicator

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MC33772B

Battery cell controller IC

5.2 Part numbers list

This section describes the part numbers available to be purchased along with their

differences. Valid orderable part numbers are provided at http://www.nxp.com.

Table 2.ꢀOrderable part variations

Part Number^[1]

Precise differential Number of Cell

Precision

Functional Current

Communication

cell voltage monitored balancing GPIO as

verification measurement

cells

temperature

measurement diagnostics coulomb

and

channel and

CTx

Cell OV/UV

SPI

TPL

channel and

OT/UT

counter

MC33772BSA1AE Yes

MC33772BSA2AE Yes

MC33772BSP1AE Yes

MC33772BSP2AE Yes

MC33772BTA1AE Yes

MC33772BTA2AE Yes

MC33772BTB1AE Yes

MC33772BTC0AE No

MC33772BTP1AE Yes

MC33772BTP2AE Yes

Yes

No

3 to 6

3 to 4

3 to 6

3 to 4

3 to 6

3 to 4

3 to 6

0

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

3 to 6

3 to 4

Yes

[1] To order parts in tape and reel, add an R2 suffix to the part number.

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MC33772B

Battery cell controller IC

6 Pinning information

6.1 Pinout diagram

terminal 1

index area

1

2

36

VPWR2

VPWR1

FAULT

VPRE

AN0/GPIO0

RDTX_OUT+

SI/RDTX_IN+

SCLK/RDTX_IN-

RDTX_OUT-

CGND

35

34

33

32

31

30

29

28

27

26

25

3

4

5

VCP

6

GNDCP

CT_6

48 LQFP-EP

GNDFLAG

7

VCOM

8

CB_6

CSB

9

CB_6:5_C

CB_5

VDDIO

10

11

12

SO

CT_5

SCL

CT_4

SDA

aaa-029761

Transparent top view

Figure 3.ꢀPinout diagram

6.2 Pin definitions

Table 3.ꢀPin definitions

Pin number Pin name

Pin function

Input

Definition

1

2

3

VPWR2

VPWR1

FAULT

Power supply input to the 33772

Input

Output

Fault output dependent on user defined internal or external faults. If not used, it must

be left open.

4

VPRE

VCP

Output

Ground

Input

Pre-regulator voltage. Connect to 470 nF capacitor.

Charge pump capacitor ground, decouple with 10 nF.

Charge pump capacitor ground

5

6

GNDCP

CT_6

7

Cell terminal pin 6 input. Terminate to LPF resistor.

Cell balance driver. Terminate to cell 6 cell balance load resistor.

Cell balance 6:5 common. Terminate to cell 6 and 5 common pin.

Cell balance driver. Terminate to cell 5 cell balance load resistor.

Cell terminal pin 5 input. Terminate to LPF resistor.

Cell terminal pin 4 input. Terminate to LPF resistor.

Cell balance driver. Terminate to cell 4 cell balance load resistor.

8

CB_6

Output

Input

9

CB_6:5_C

CB_5

10

11

12

13

CT_5

CT_4

Input

CB_4

Output

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MC33772B

Battery cell controller IC

Pin number Pin name

Pin function

Output

Input

Definition

14

15

16

17

18

19

20

21

22

23

CB_4:3_C

CB_3

Cell balance 4:3 common. Terminate to cell 4 and 3 common pin.

Cell balance driver. Terminate to cell 3 cell balance load resistor.

Cell terminal pin 3 input. Terminate to LPF resistor.

CT_3

CT_2

Input

Cell pin 2 input. Terminate to LPF resistor.

CB_2

Output

Input

Cell balance driver. Terminate to cell 2 cell balance load resistor.

Cell balance 2:1 common. Terminate to cell 2 and 1 common pin.

Cell balance driver. Terminate to cell 1 cell balance load resistor.

Cell pin 1 input. Terminate to LPF resistor.

CB_2:1_C

CB_1

CT_1

CT_REF

SPI_COM_EN

Input

Cell terminal REF input. Terminate to LPF resistor.

Input

SPI communication enable input. Wire to VPRE to use SPI communication, else wire

to ground to use TPL communication.

24

RESET

Input

RESET is an active high input. RESET has an internal pull down. If not used, it can be

shorted to GND.

25

26

27

28

SDA

SCL

I/O

I²C data

I/O

I²C clock

SO

Output

Input

SPI serial output

VDDIO

IO voltage for I²C and SPI interfaces. Voltage level corresponding to Logic 1 will be

the same as VDDIO.

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

CSB

Input

Output

Ground

I/O

SPI active low chip select. If not used, it must be shorted to ground.

Communication regulator output, decouple with 2.2 µF to CGND.

Communication decoupling ground, terminate to GNDSUB.

TPL receive/transmit output negative

VCOM

CGND

RDTX_OUT−

SCLK/RDTX_IN-

SI/RDTX_IN+

RDTX_OUT+

AN0 GPIO0

AN1 GPIO1

AN2 GPIO2

AN3 GPIO3

AN4 GPIO4

AN5 GPIO5

AN6 GPIO6

ISENSE+

ISENSE−

AGND

I/O

SPI clock or TPL receive/transmit input negative

SPI serial input or TPL receive/transmit input positive

TPL receive/transmit output positive

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

Input

I/O

Current measurement input +

Current measurement input −

Analog ground, terminate to GNDSUB

DGND

I/O

Digital ground, terminate to GNDSUB

VANA

Output

Ground

Precision ADC analog supply. Decouple with 47 nF capacitor to AGND.

Ground reference for device, terminate to reference of battery cluster.

GNDSUB

GNDFLAG

Exposed pad, terminate to lowest potential of the battery cluster and to heat

dissipation area of PCB.

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Battery cell controller IC

7 General product characteristics

7.1 Ratings and operating requirements relationship

The operating voltage range pertains to the VPWR pins referenced to the AGND pins.

Table 4.ꢀRatings vs. operating requirements

Fatal range

Lower limited operating range Normal operating range

Upper limited

Fatal range

operating range

Permanent

failure may

occur

No permanent failure, but IC

functionality is not guaranteed

100 % functional

Permanent

failure may

occur

V_PWR< −0.3 V

5.0 V ≤ V_PWR≤ 6.0 V (SPI)

6.4 V ≤ V_PWR≤ 7.0 V (TPL)

Reset range:

6.0 V ≤ V_PWR≤ 30 V (SPI)

7.0 V ≤ V_PWR≤ 30 V (TPL)

30 V < V_PWR≤ 40 V 40 V < V_PWR

IC parameters

might be out of

specification.

Detection of V_PWR

overvoltage is

functional

–0.3 V ≤ V_PWR≤ 5.0 V (SPI)

–0.3 V ≤ V_PWR≤ 6.4 V (TPL)

POR with V_PWRfalling:

4.8 V ≤ V_PWR< 5.0 V (SPI)

6.1 V ≤ V_PWR< 6.4 V (TPL)

POR with V_PWRrising:

5.6 V ≤ V_PWR< 6.0 V (SPI)

6.6 V ≤ V_PWR< 7.0 V (TPL)

Handling range - No permanent failure

In both upper and lower limited operating range, no information can be provided about IC

performance. Only the detection of V_PWRovervoltage is guaranteed in the upper limited

operating range.

Performance in normal operating range is guaranteed only if there is a minimum of three

battery cells in the stack.

7.2 Maximum ratings

Table 5.ꢀMaximum ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction or

permanent damage to the device.

Symbol

Description (rating)

Min

Max

Unit

Electrical ratings

VPWR1, VPWR2

CT6

Supply input voltage

–0.3

−0.3

−10

−0.3

—

40

V

Cell terminal voltage

VPWR to CT6

CT_Nto CT_N-1

CT_N(CURRENT)

Voltage across VPWR1,2 pins pair and CT6 pin

Cell terminal differential voltage

Cell terminal input current

10

V

[1]

6.7

±500

10

V

µA

V

CB_Nto CB_{N:N-1_C}

CB_{N:N-1_C}to CB_N-1

Cell balance differential voltage

—

CB_N-1to CT_N-1

VISENSE

VCOM

Cell balance input to cell terminal input

−10

−0.5

—

+10

2.5

5.8

3.1

V

ISENSE+ and ISENSE– pin voltage

Maximum voltage may be applied to VCOM pin from external source

Maximum voltage may be applied to VANA pin

VANA

—

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MC33772B

Battery cell controller IC

Symbol

Description (rating)

Min

Max

Unit

VPRE

Maximum voltage which may be applied to VPRE pin from external

source

—

7.0

V

VCP

Maximum voltage which may be applied to VCP pin from external

source

—

14

V

VDDIO

Maximum voltage which may be applied to VDDIO pin from external

source

5.8

V_GPIO0

V_GPIOx

V_DIG

GPIO0 pin voltage

–0.3

6.5

V

GPIOx pins (x = 1 to 6) voltage

–0.3

VCOM + 0.5

Voltage I²C pins (SDA, SCL)

VDDIO + 0.5

V_RESET

V_CSB

V_{SPI_COMM_EN}

V_SO

RESET pin

6.5

7.0

CSB pin

SPI_COMM_EN

SO pin

–0.3

VDDIO + 0.5

V

V_GPIO5,6

FAULT

V_COMM

Maximum voltage for GPIO5 and GPIO6 pins used as current input

Maximum applied voltage to pin

−0.3

−10

2.5

7.0

10

Maximum voltage to pins RDTX_OUT+, RDTX_OUT–, SI/RDTX_IN+,

CLK/RDTX_IN–

f_SPI

SPI frequency (SPI mode)

—

4.2

2.1

4.2

MHz

Mbps

MHz

V

BR_TPL

f_TPL

Transformer communication bit rate (TPL mode)

Transformer signal frequency (TPL mode)

1.9

3.8

V_ESD

ESD voltage

Human body model (HBM)

Charge device model (CDM)

Charge device model corner pins (CDM)

—

±2000

±500

±750

[2]

V_ESD

ESD voltage (CTx, CBx, GPIOx, ISENSE+, ISENSE–, RDTX_OUT+,

RDTX_OUT–, SI/RDTX_IN+, SCLK/ RDTX_IN–)

V

Human body model (HBM)

—

±4000

V_ESD

ESD voltage (CTREF, CTx,, GPIOx, ISENSE+, ISENSE−, RDTX_

OUT+, RDTX_OUT−, SI/RDTX_IN+, SCLK/ RDTX_IN−)

IEC 61000-4-2, Unpowered (Gun configuration: 330 Ω / 150 pF)

HMM, Unpowered (Gun configuration: 330 Ω / 150 pF)

—

±8000

ISO 10605:2009, Unpowered (Gun configuration: 2 kΩ / 150 pF)

ISO 10605:2009, Powered (Gun configuration: 2 kΩ / 150 pF)

[1] Adjacent CT pins may experience an overvoltage that exceeds their maximum rating during OV/UV functional verification test or during open line

diagnostic test. Nevertheless, the IC is completely tolerant to this special situation.

[2] ESD testing is performed in accordance with the human body model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω).

7.3 Thermal characteristics

Table 6.ꢀThermal ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction or

permanent damage to the device.

Symbol

Description (rating)

Min

Max

Unit

Thermal ratings

Operating temperature

Ambient (SPI application)

Ambient (TPL application)

Junction

°C

T_A

T_J

–40

+125

+105

+150

T_STG

Storage temperature

−55

—

+150

260

°C

[1] [2]

T_PPRT

Peak package reflow temperature

Thermal resistance and package dissipation ratings

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MC33772B

Battery cell controller IC

Symbol

Description (rating)

Min

Max

Unit

[3]

[4] [5]

[6]

R_ΘJB

Junction-to-board (bottom exposed pad

soldered to board) 48 LQFP EP

—

11

°C/W

R_ΘJA

Junction-to-ambient, natural convection, single-

layer board (1s) 48 LQFP EP

—

72

30

24

0.98

4

°C/W

R_ΘJA

Junction-to-ambient, natural convection, four-

layer board (2s2p) 48 LQFP EP

R_ΘJCTOP

R_ΘJCBOTTOM

ΨJT

Junction-to-case top (exposed pad) 48 LQFP

EP

[7]

Junction-to-case bottom (exposed pad) 48

LQFP EP

[8]

Junction to package top, natural convection

[1] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a

malfunction or permanent damage to the device.

[2] NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture

Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts

(MC33xxxD enter 33xxx), and review parametrics.

[3] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board

near the package.

[4] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

[5] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

[6] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1), with the cold plate

temperature used for the case temperature.

[7] Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.

[8] Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2.

When Greek letter (Ψ) is not available, the thermal characterization parameter is written as Psi-JT.

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Battery cell controller IC

7.4 Electrical characteristics

Table 7.ꢀStatic and dynamic electrical characteristics

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤

125 °C (SPI mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR

= 24 V, T_A= 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

Power management

V_PWR(FO)

Supply voltage

V

Full parameter specification (SPI application)

Full parameter specification (TPL application)

6.0

7.0

—

30

I_VPWR

Supply current (base value)

mA

Normal mode, cell balance OFF, ADC inactive,

SPI communication inactive, IVCOM = 0 mA

—

6.0

8.0

—

Normal mode, cell balance OFF, ADC inactive,

TPL communication inactive, IVCOM = 0 mA

I_{VPWR(TPL_TX)}

I_VPWR(CBON)

Supply current adder when TPL communication active

—

50

—

mA

Supply current adder to set

2.0

all 6 cell balance switches ON

I_VPWR(ADC)

Delta supply current to perform

ADC conversions (addend)

mA

ADC1-A,B continuously converting

ADC2 continuously converting

—

4.7

1.0

—

I_VPWR(SS)

Supply current in sleep and idle modes,

communication inactive, cell balance off,

oscillator monitor on, cyclic measurement off

SPI mode (TA = 25 °C)

SPI mode (−40 °C ≤ TA ≤ 85 °C)

SPI mode (TA = 125 °C)

—

32

—

42

75

—

60

µA

—

TPL mode (TA = 25 °C)

—

TPL mode (−40 °C ≤ TA ≤ 85 °C)

TPL mode (TA = 125 °C)

100

130

Except for 20 V < VPWR ≤ 30 V and within 1200 ms

since entering into sleep mode from normal mode

SPI mode (TA = 25 °C)

SPI mode (−40 °C ≤ TA ≤ 85 °C)

SPI mode (TA = 125 °C)

—

40

—

75

—

µA

42

80

—

TPL mode (TA = 25 °C)

—

TPL mode (−40 °C ≤ TA ≤ 85 °C)

TPL mode (TA = 125 °C)

120

130

—

I_VPWR(CKMON)

V_{PWR(OV_FLAG)}

V_{PWR(LV_FLAG)}

V_{PWR(UV_POR)}

Clock monitor current consumption

V_PWRovervoltage fault threshold (flag)

V_PWRlow-voltage warning threshold (flag)

—

5

µA

V

33.5

7.8

—

V

V_PWRundervoltage shutdown

threshold (POR), falling VPWR

V

SPI mode

TPL mode

—

4.9

—

6.25

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Battery cell controller IC

Symbol

Parameter

Min

Typ

Max

Unit

V_{PWR(UV_RIS)}

V_PWRundervoltage shutdown

threshold (POR), rising VPWR

V

SPI mode

TPL mode

—

5.8

6.8

—

t_VPWR(FILTER)

V_PWROV, LV filter

—

50

—

µs

V

VPRE power supply

VPRE

Pre-regulator voltage range - decouple with 470 nF

SPI mode, ILoad = 15 mA

—

4.9

—

5.75

—

SPI mode, ILoad = 15 mA, 5.0 ≤ VPWR < 6.0 V

TPL mode, ILoad = 70 mA

6.5

V_{PRE(UV_TH)}

VCP power supply

VCP

PRE undervoltage threshold leading to a reset

—

4.25

—

V

Charge pump voltage range

2 × V_PRE– 2

—

2 × V_PRE

—

V

V_{CP(UV_TH)}

VDDIO power supply

V_DDIO

Undervoltage threshold for VCP minus VPRE

1.5

IO supply for I²C and SPI interfaces - voltage range

—

4.15

—

V

VCOM power supply

V_COM

VCOM output voltage

VCOM output current allocated for external use

VCOM undervoltage fault threshold

VCOM undervoltage hysteresis

VCOM undervoltage fault timer

VCOM fault retry timer

—

5.4

5.0

—

5.0

—

V

mA

V

I_VCOM

V_COM(UV)

4.4

100

10

V_{COM_HYS}

—

mV

µs

ms

V

t_{VCOM(FLT_TIMER)}

t_VCOM(RETRY)

V_COM(OV)

—

10

—

VCOM overvoltage fault threshold

—

5.9

I_LIM(OC)

VCOM current limit in TPL mode

VCOM current limit SPI mode

65

35

—

140

mA

R_VCOM(SS)

t_VCOM

VCOM sleep mode pulldown resistor

—

2.0

—

kΩ

µs

VCOM rise time (CL = 2.2 µF ceramic X7R only)

400

VANA power supply

V_ANA

VANA output voltage (not used by external circuits)

Decouple with 47 nF X7R 0603 or 0402

V

—

5

2.65

2.4

50

—

V_ANA(UV)

VANA undervoltage fault threshold

VANA undervoltage hysteresis

VANA undervoltage fault timer

VANA overvoltage fault threshold

VANA fault retry timer

V

mV

µs

V_{ANA_HYS}

V_{ANA(FLT_TIMER)}

V_ANA(OV)

—

11

—

2.8

10

—

V

t_VANA(RETRY)

I_LIM(OC)

R_{VANA_RPD}

t_VANA

—

ms

mA

kΩ

µs

VANA current limit

—

10

—

VANA sleep mode pull-down resistor

VANA rise time (CL = 47 nF ceramic X7R only)

—

1.0

—

100

ADC1-A, ADC1-B

CTn_(LEAKAGE)

CT_N

Cell terminal input leakage current

Cell terminal input current during conversion

Cell terminal open load detection pulldown resistor

—

10

50

—

nA

Ω

R_PD

950

MC33772B_SDS

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MC33772B

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Symbol

Parameter

VPWR terminal measurement resolution

Min

Typ

2.44148

Max

Unit

mV/LSB

V

V_{VPWR_RES}

V_{VPWR_RNG}

—

VPWR terminal measurement range

SPI application

5.0

7.0

—

36

TPL application

VPWR_{TERM_ERR}

V_{CT_RNG}

VPWR terminal measurement accuracy

−0.5

0.0

—

0.5

4.85

—

%

V

ADC differential input voltage range for CTn to CTn-1

V_{CT_ANx_RES}

Cell voltage and ANx resolution

in 15-bit MEAS_xxxx registers

152.58789

µV/LSB

V_ERR33RT

Cell voltage measurement error

V_CELL= 3.3 V, TA = 25 °C

mV

—

±0.4

±0.7

±0.4

—

V_ERR

Cell voltage measurement error

0.1 V ≤ V_CELL≤ 4.85 V

V_{ERR_1}

Cell voltage measurement error

0 V ≤ V_CELL≤ 1.5 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

—

V_{ERR_2}

V_{ERR_3}

V_{ERR_4}

Cell voltage measurement error

1.5 V ≤ V_CELL≤ 2.7 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

mV

±0.4

±0.5

±0.7

—

Cell voltage measurement error

2.7 V ≤ V_CELL≤ 3.7 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

Cell voltage measurement error

3.7 V ≤ V_CELL≤ 4.3 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

V_{ERR_5}

Cell voltage measurement error

1.5 V ≤ V_CELL≤ 4.5 V

mV

V_{ANx_ERR}

Magnitude of ANx error in the

entire measurement range:

Ratiometric measurement

—

16

10

Absolute measurement,

input in the range [1.0, 4.5] V

Absolute measurement,

input in the range [0, 4.85] V

—

15

t_VCONV

Single channel net conversion time

13-bit resolution

µs

—

6.77

9.43

—

14-bit resolution

15-bit resolution

14.75

25.36

16-bit resolution

V_{V_NOISE}

Conversion noise

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

µVrms

—

1800

1000

600

—

400

ADC2/current sense module

V_INC

ISENSE+/ISENSE− input voltage (reference to AGND)

−300

−150

—

300

150

0.5

—

mV

µV

%

V_IND

ISENSE+/ISENSE− differential input voltage range

ISENSE+/ISENSE− input voltage offset error

ISENSE error including nonlinearities

V_{ISENSEX(OFFSET)}

I_GAINERR

I_{ISENSE_OL}

—

−0.5

—

ISENSE open load injected current

130

µA

MC33772B_SDS

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NXP Semiconductors

MC33772B

Battery cell controller IC

Symbol

V_{ISENSE_OL}

V_2RES

Parameter

ISENSE open load detection threshold

Min

Typ

Max

Unit

mV

—

460

0.6

—

Current sense user register resolution

µV/LSB

mV

V_{PGA_SAT}

PGA saturation half-range

Gain = 256

—

4.9

19.5

78.1

150

—

Gain = 64

Gain = 16

Gain = 4

V_{PGA_ITH}

Voltage threshold for PGA gain increase

mV

Gain = 256

Gain = 64

Gain = 16

Gain = 4

—

2.344

9.375

37.50

V_{PGA_DTH}

Voltage threshold for PGA gain decrease

Gain = 256

Gain = 64

Gain = 16

Gain = 4

—

4.298

17.188

68.750

—

t_{AZC_SETTLE}

t_ICONV

Time to perform auto-zero procedure

after enabling the current channel

—

200

—

µs

ADC conversion time including PGA settling time

13-bit resolution

—

19.00

21.67

27.00

37.67

—

14-bit resolution

15-bit resolution

16-bit resolution

V_{I_NOISE}

Noise at 16-bit conversion

Noise error at 13-bit conversion

—

3.01

8.33

6.0

—

µVrms

MHz

V_{I_NOISE}

ADC_CLK

ADC2 and ADC1-A,B clocking frequency

Cell balance drivers

V_DS(CLAMP)

V_{OUT(FLT_TH)}

Cell balance driver VDS active clamp voltage

—

11

—

V

Output fault detection voltage threshold

Balance off (open load)

0.55

Balance on (shorted load)

R_{PD_CB}

Output OFF open load detection pull-down resistor

Balance off, open load detect disabled

kΩ

µA

—

2.0

—

I_OUT(LKG)

Output leakage current

Balance off, open load detect

disabled at V_DS= 4.0 V

1.0

I_{OUT(LKG_DIAG)}

Output leakage current in diagnostic mode

µA

Ω

CB_x pins, with balance OFF, open

load detect disabled, VDS = 4.0 V

—

15

49

CB_X:X-1_C pins, with balance OFF,

open load detect disabled, VDS = 4.0 V

R_DS(on)

Drain-to-source on resistance

I_OUT= 300 mA, T_J= 125 °C

I_OUT= 300 mA, T_J= 25 °C

I_OUT= 300 mA, T_J= −40 °C

—

0.80

—

0.5

0.4

—

I_{LIM_CB}

t_ON

Driver current limitation (shorted resistor)

310

—

950

mA

µs

Cell balance driver turn on

R_L= 15 Ω

—

350

—

MC33772B_SDS

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MC33772B

Battery cell controller IC

Symbol

Parameter

Min

Typ

Max

Unit

µs

t_OFF

Cell balance driver turn off

R_L= 15 Ω

—

200

20

—

t_{BAL_DEGLICTH}

Short/open detect filter time

µs

Internal temperature measurement

IC_TEMP1_ERR

IC_TEMP1_RES

TSD_TH

IC temperature measurement error

−3.0

—

3.0

—

K

K/LSB

°C

IC temperature resolution

Thermal shutdown

0.032

170

10

—

TSD_HYS

Thermal shutdown hysteresis

—

°C

Default operational parameters

V_CTOV(TH)

Cell overvoltage threshold (8 bits)

Cell overvoltage threshold resolution

Cell undervoltage threshold (8 bits)

Cell undervoltage threshold resolution

0.0

—

4.2

19.53125

2.5

5.0

—

V

mV/LSB

V

V_CTOV(RES)

V_CTUV(TH)

V_CTUV(RES)

V_{GPIO_OT(TH)}

0.0

—

5.0

—

19.53125

1.16

mV/LSB

V

GPIOx configured as ANx input

—

overtemperature threshold from POR

V_{GPIO_OT(RES)}

V_{GPIO_UT(TH)}

Overtemperature voltage threshold resolution

—

4.8828125

3.82

—

mV/LSB

V

GPIOx configured as ANx input

undertemperature threshold from POR

V_{GPIO_UT(RES)}

Undertemperature voltage threshold resolution

—

4.8828125

—

mV/LSB

General purpose input/output GPIOx

V_IH

V_IL

Input high-voltage (3.3 V compatible)

2.0

—

1.0

—

V

Input low-voltage (3.3 V compatible)

Input hysteresis

V_HYS

I_IL

—

100

mV

nA

Input leakage current

Pins tri-state, V_IN= V_COMor AGND

−100

−30

—

100

30

I_IDL

Differential input leakage current GPIO 5,6

nA

GPIO 5,6 configured as digital

inputs for current measurement

V_OH

V_OL

Output high-voltage I_OH= −0.5 mA

Output low-voltage I_OL= +0.5 mA

V_COM− 0.8

—

V

0.8

V_ADC

Analog ADC input voltage range

for ratiometric measurements

AGND

V_COM

V_OL(TH)

Analog input open pin detect threshold

Internal open detection pull-down resistor

GPIO0 WU de-glitch filter

—

3.8

—

0.15

5.0

50

—

5.6

V

R_OPENPD

t_{GPIO0_WU}

t_{GPIO0_FLT}

t_{GPIO2_SOC}

t_{GPIOx_DIN}

Reset input

V_{IH_RST}

kΩ

µs

GPIO0 daisy chain de-glitch filter both edges

GPIO2 convert trigger de-glitch filter

GPIOx configured as digital input de-glitch filter

—

20

—

2.0

—

2.5

Input high-voltage (3.3 V compatible)

Input low-voltage (3.3 V compatible)

Input hysteresis

2.0

—

1.0

—

V

V_{IL_RST}

V_HYS

0.6

100

V

t_RESETFLT

RESET de-glitch filter

—

µs

MC33772B_SDS

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MC33772B

Battery cell controller IC

Symbol

Parameter

Min

Typ

Max

Unit

kΩ

R_{RESET_PD}

Input logic pull down (RESET)

—

100

—

SPI_COM_EN input

V_IH

Input high-voltage (3.3 V compatible)

Input low-voltage (3.3 V compatible)

Input hysteresis

2.0

—

1.0

—

V

V_IL

V_HYS

—

450

mV

Bus switch for TPL communication

RX_TERMBus termination resistor (open

—

150

—

Ω

resistor when bus switch is closed)

Remark: If the bus switch is closed, then the termination resistor is open, else the termination resistor is connected. At the end of the daisy

chain, the switch must be open, so that the transmission line is properly terminated.

Digital interface

V_{FAULT_HA}

FAULT output (high active, IOH = 1.0 mA)

3.9

2.9

4.9

—

6.0

V

FAULT output (High Active, IOH = 1.0

mA), SPI mode, 5.0 ≤ VPWR < 6.0 V

I_{FAULT_CL}

R_{FAULT_PD}

V_{IH_COMM}

FAULT output current limit

FAULT output pulldown resistance

Voltage threshold to detect the input as high

3.0

—

25

—

mA

kΩ

V

100

SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA,

SCL (NOTE: needs to be 3.3 V compatible)

—

2.0

V_{IL_COMM}

Voltage threshold to detect the input as low

V

SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL

0.8

—

V_HYS

Input hysteresis

mV

nA

kΩ

SI/RDTX_IN+, SCLK/RDTX_IN−, CSB, SDA, SCL

100

I_{LOGIC_SS}

Sleep state input logic current

CSB

−100

—

100

—

R_{SCLK_PD}

Input logic pulldown resistance

(SCLK/RDTX_IN–, SI/RDTX+)

20

R_{I_PU}

Input logic pullup resistance to V_COM(CSB, SDA, SCL)

Tri-state SO input current 0 V to V_COM

—

−2.0

100

—

2.0

—

kΩ

µA

V

I_{SO_TRI}

V_{SO_HIGH}

V_{SO_LOW}

SO high-state output voltage with I_SO(HIGH)= −2.0 mA

V_DDIO− 0.4

—

SO, SDA, SLK low-state output

voltage with I_SO(HIGH)= −2.0 mA

—

0.4

V

CSB_{WU_FLT}

System timing

t_{CELL_CONV}

CSB wake-up de-glitch filter, low to high transition

—

50

—

µs

Time needed to acquire all 6 cell voltages and

the current after an on demand conversion

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

—

41

57

—

89

152

t_SYNC

V/I synchronization time

µs

ADC1-A,B at 13 bit, ADC2 at 13 bit

ADC1-A,B at 14 bit, ADC2 at 13 bit

ADC1-A,B at 15 bit, ADC2 at 13 bit

ADC1-A,B at 16 bit, ADC2 at 13 bit

—

41.39

42.71

47.37

95.14

—

MC33772B_SDS

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MC33772B

Battery cell controller IC

Symbol

Parameter

Min

Typ

Max

Unit

µs

t_SYNC

V/I synchronization time

ADC1-A,B at 13 bit, ADC2 at 14 bit

ADC1-A,B at 14 bit, ADC2 at 14 bit

ADC1-A,B at 15 bit, ADC2 at 14 bit

ADC1-A,B at 16 bit, ADC2 at 14 bit

—

46.73

—

48.05

50.71

92.47

t_SYNC

V/I synchronization time

µs

ADC1-A,B at 13 bit, ADC2 at 15 bit

ADC1-A,B at 14 bit, ADC2 at 15 bit

ADC1-A,B at 15 bit, ADC2 at 15 bit

ADC1-A,B at 16 bit, ADC2 at 15 bit

—

57.39

58.71

61.37

87.14

—

t_SYNC

V/I synchronization time

ADC1-A,B at 13 bit, ADC2 at 16 bit

ADC1-A,B at 14 bit, ADC2 at 16 bit

ADC1-A,B at 15 bit, ADC2 at 16 bit

ADC1-A,B at 16 bit, ADC2 at 16 bit

—

78.73

80.05

82.71

88.02

—

t_VPWR(READY)

t_WAKE-UP

Time after VPWR connection for

the IC to be ready for initialization

—

5.0

ms

µs

Sleep mode to normal mode device ready

Wake-up from fault

—

400

Wake-up from GPIO

Wake-up from network

Wake-up from CSB

Sleep mode to normal mode time after TPL bus wake-up

Time between wake pulses

—

600

60

1.0

—

ms

µs

s

t_{WAKE_DELAY}

t_IDLE

Idle timeout after POR

—

t_{WAKE_INIT}

t_BALANCE

t_CYCLE

Wake-up signaling timeout after POR

Cell balance timer range

—

0.65

—

s

0.5

0.0

511

8.5

min

s

Cyclic acquisition timer range

—

t_FAULT

Fault detection to activation of fault pin

Normal mode

µs

—

56

t_EOC

SOC to data ready (includes post processing of data)

13-bit resolution

µs

—

148

201

307

520

—

14-bit resolution

15-bit resolution

16-bit resolution

t_SETTLE

Time after SOC to begin converting with ADC1-A,B

—

12.28

—

µs

t_{CLST_TPL}

Time needed to send an SOC command and read

back 6 cell voltages, 7 temperatures, 1 current, and

1 coulomb counter with TPL communication working

at 2.0 Mbps and ADC1-A,B configured as follows:

ms

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

—

0.79

0.85

0.95

1.16

—

MC33772B_SDS

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MC33772B

Battery cell controller IC

Symbol

Parameter

Time needed to send an SOC command and read

Min

Typ

Max

Unit

ms

t_{CLST_SPI}

back 6 cell voltages, 7 temperatures, 1 current, and

1 coulomb counter with SPI communication working

at 4.0 Mbps and ADC1-A,B configured as follows:

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

—

0.48

0.54

0.64

0.86

—

t_{I2C_DOWNLOAD}

t_{I2C_ACCESS}

Time to download EEPROM calibration after POR

—

1.0

—

ms

EEPROM access time, EEPROM

write (depends on device selection)

5.0

t_{WAVE_DC_BITx}

Daisy chain duty cycle off time

t_{WAVE_DC_BITx = 00}

µs

ms

—

500

1.0

10

—

Daisy chain duty cycle off time

t_{WAVE_DC_BITx = 01}

Daisy chain duty cycle off time

t_{WAVE_DC_BITx = 10}

Daisy chain duty cycle off time

t_{WAVE_DC_BITx = 11}

—

100

500

—

550

—

t_{WAVE_DC_ON}

t_{COM_LOSS}

Daisy chain duty cycle on time

µs

Time out to reset the IC in the

absence of communication

1024

ms

SPI interface

F_SCK

CLK/RDTX_IN– frequency

SCLK/RDTX_IN– high time (A)

SCLK/RDTX_IN– high time (B)

SCLK/RDTX_IN− period (A+B)

SCLK/RDTX_IN− falling time

SCLK/RDTX_IN− rising time

SCLK/RDTX_IN− setup time (O)

SCLK/RDTX_IN– hold time (P)

SI/RDTX_IN+ setup time (F)

SI/RDTX_IN+ hold time (G)

—

125

250

—

4.0

—

15

—

40

MHz

ns

[1]

t_{SCK _H}

t_{SCK _L}

t_SCK

t_FALL

t_RISE

—

[1]

t_SET

20

t_HOLD

20

t_{SI_SETUP}

t_{SI_HOLD}

t_{SO_VALID}

40

SO data valid, rising edge of SCLK/

RDTX_IN− to SO data valid (I)

—

[1]

t_{SO_EN}

SO enable time (H)

SO disable time (K)

—

40

—

ns

µs

t_{SO_DISABLE}

t_{CSB_LEAD}

t_{CSB_LAG}

t_TD

CSB lead time (L)

100

1.0

CSB lag time (M)

Sequential data transfer delay (N)

TPL interface ^[2]

[1] See Figure 4

[2] Detailed application information about how to build a TPL daisy chain can be found in the AN12605 application note dedicated to communication.

MC33772B_SDS

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Battery cell controller IC

7.5 Timing diagrams

CSB

N

M

P

K

O

L

A

B

Don't care level

SCLK

Don't care level

H

I

SO

SI

Tri-state

MSB

LSB

F

G

MSB

aaa-027848

Figure 4.ꢀLow-voltage SPI interface timing

Start of

Bit 39

Bit 38

Bit 37

Bit 36

Bit 2

Bit 1

Bit 0

End of

message

Logic 1 Logic 1 Logic 0

Logic 0

Logic 1 Logic 0 Logic 0 message

3.75 V

RDTX_IN+

2.5 V

RDTX_IN-

1.25 V

two pulse

positive

sine

two pulse

negative

sine

aaa-027849

Figure 5.ꢀTransformer communication signaling

8 Packaging

8.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current

package outline drawing, go to www.nxp.com and perform a keyword search for the

drawing’s document number.

Table 8.ꢀPackage Outline

Package

Suffix

AE

Package outline drawing number

48-pin LQFP-EP

SOT1571-1

MC33772B_SDS

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MC33772B

Battery cell controller IC

MC33772B_SDS

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Short data sheet: technical data

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20 / 27

NXP Semiconductors

MC33772B

Battery cell controller IC

MC33772B_SDS

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Short data sheet: technical data

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NXP Semiconductors

MC33772B

Battery cell controller IC

Figure 6.ꢀPackage outline

MC33772B_SDS

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Short data sheet: technical data

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MC33772B

Battery cell controller IC

9 Revision history

Table 9.ꢀRevision history

Document ID

Release date

Data sheet status

Change notice Supersedes

MC33772B_SDS v.6.0

Modifications

20200402

Technical data

202003032I

MC33772B_SDS v.5.0

• Revision updated to match full data sheet

MC33772B_SDS v.5.0

MC33772B_SDS v.4.0

MC33772B_SDS v.3.0

20181108

20180731

20180608

Technical data

201806036I

MC33772B_SDS v.4.0

MC33772B_SDS v.3.0

—

MC33772B_SDS

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10 Legal information

10.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

[short] Data sheet: product preview

Development

This document contains certain information on a product under development.

NXP reserves the right to change or discontinue this product without notice.

[short] Data sheet: advance information

[short] Data sheet: technical data

Qualification

Production

This document contains information on a new product. Specifications and

information herein are subject to change without notice.

This document contains the product specification. NXP Semiconductors

reserves the right to change the detail specifications as may be required to

permit improvements in the design of its products.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

10.2 Definitions

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a

technical data data sheet shall define the specification of the product as

agreed between NXP Semiconductors and its customer, unless NXP

Semiconductors and customer have explicitly agreed otherwise in writing.

In no event however, shall an agreement be valid in which the NXP

Semiconductors product is deemed to offer functions and qualities beyond

those described in the technical data data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

10.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

MC33772B_SDS

All information provided in this document is subject to legal disclaimers.

Short data sheet: technical data

Rev. 6.0 — 2 April 2020

24 / 27

NXP Semiconductors

MC33772B

Battery cell controller IC

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

10.4 Trademarks

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

SMARTMOS — is a trademark of NXP B.V.

MC33772B_SDS

All information provided in this document is subject to legal disclaimers.

Short data sheet: technical data

Rev. 6.0 — 2 April 2020

25 / 27

NXP Semiconductors

MC33772B

Battery cell controller IC

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Part number breakdown ....................................4

Tab. 6.

Tab. 7.

Tab. 8.

Tab. 9.

Thermal ratings ................................................. 9

Static and dynamic electrical characteristics ... 11

Package Outline ..............................................19

Revision history ...............................................23

Orderable part variations ...................................5

Pin definitions ....................................................6

Ratings vs. operating requirements ...................8

Maximum ratings ...............................................8

Figures

Fig. 1.

Fig. 2.

Simplified application diagram, SPI use case ....2

Fig. 4.

Fig. 5.

Fig. 6.

Low-voltage SPI interface timing .....................19

Transformer communication signaling .............19

Package outline ...............................................20

Simplified application diagram, TPL use

case ...................................................................3

Pinout diagram ..................................................6

Fig. 3.

MC33772B_SDS

All information provided in this document is subject to legal disclaimers.

Short data sheet: technical data

Rev. 6.0 — 2 April 2020

26 / 27

NXP Semiconductors

MC33772B

Battery cell controller IC

Contents

1

General description ............................................ 1

2

3

4

5

5.1

5.2

6

6.1

6.2

7

Features ............................................................... 1

Simplified application diagram ..........................2

Applications .........................................................4

Ordering information .......................................... 4

Part numbers definition ......................................4

Part numbers list ............................................... 5

Pinning information ............................................ 6

Pinout diagram .................................................. 6

Pin definitions .................................................... 6

General product characteristics ........................ 8

Ratings and operating requirements

7.1

relationship .........................................................8

Maximum ratings ............................................... 8

Thermal characteristics ......................................9

Electrical characteristics .................................. 11

Timing diagrams .............................................. 19

Packaging .......................................................... 19

Package mechanical dimensions .................... 19

Revision history ................................................ 23

Legal information ..............................................24

7.2

7.3

7.4

7.5

8

8.1

9

10

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 April 2020

Document identifier: MC33772B_SDS


型号：	MC33772BSA2AE
厂家：	NXP
描述：	Battery cell controller IC 电池
文件：	总27页 (文件大小：407K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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