MC33772CTA2AE_技术文档

MC33772C

Battery cell controller IC

Rev. 3 — 4 June 2021

Product brief

1 General description

The MC33772C is a SMARTMOS lithium-ion battery cell controller IC designed for

automotive applications, such as hybrid electric (HEV) and electric vehicles (EV) along

with industrial applications, such as energy storage systems (ESS) and uninterruptible

power supply (UPS) systems.

The device performs ADC conversions of the differential cell voltages and current, as well

as battery coulomb counting and battery temperature measurements. The information is

transmitted to MCU using one of the microcontroller interfaces: serial peripheral interface

(SPI) or isolated daisy chain communication interface [also referred as transformer

physical layer (TPL)] which supports both capacitive and inductive isolation between

nodes of the IC. The product is AEC-Q100 qualified and operates up to 125 °C ambient

temperature.

2 Features

• 5.0 V ≤ V_PWR≤ 30 V operation, 40 V transient

• 3 to 6 cells management

• Isolated 2.0 Mbit/s differential communication or 4.0 Mbit/s SPI

• Addressable on initialization

• Bi-directional transceiver to support up to 63 nodes in daisy chain

• 0.8 mV total voltage measurement error

• Synchronized cell voltage/current measurement with coulomb count

• Averaging of cell voltage measurements

• Total stack voltage measurement

• Seven GPIO/temperature sensor inputs

• 5.0 V at 5.0 mA reference supply output

• Automatic over/undervoltage and temperature detection routable to fault pin

• Integrated sleep mode over/undervoltage and temperature monitoring

• Onboard 300 mA passive cell balancing with diagnostics

• Hot plug capable

• Detection of internal and external faults, as open lines, shorts, and leakage

• Designed to support ISO 26262, up to ASIL D safety system

• Fully compatible with the MC33771C and the MC33664

• Qualified in compliance with AEC-Q100

NXP Semiconductors

MC33772C

Battery cell controller IC

3 Simplified application diagram

Figure 1.ꢀSimplified application diagram, SPI use case

MC33772C

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MC33772C

Battery cell controller IC

RDTX_OUT+

RDTX_OUT-

VCOM

VPWR1

VPWR2

CT6

VDDIO

VCOM cluster # 2

VCOM

CGND

VPRE

CB6

CB6:5_C

CT5

+

cluster # 2

reference

VANA

AGND

DGND

FAULT

SDA

cluster # 2

reference

CTn

CBn

6 cell

voltage

measure

EEPROM

(OPTIONAL)

SCL

SO

MC33772C

CSB

CT1

CB2:1_C

CB1

SPI_COM_EN

cluster # 2

reference

RESET

+

T1

SI/RDTX_IN+

SCLK/RDTX_IN-

VCP

CTREF

GNDSUB

GNDFLG

cluster # 2

reference

GNDCP

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

VCOM cluster # 2

cluster # 2

reference

ISENSE+

ISENSE-

cluster # 2

reference

RDTX_OUT+

RDTX_OUT-

VCOM

VPWR1

VPWR2

CT6

VDDIO

VCOM cluster # 1

VCOM

CGND

VPRE

CB6

CB6:5_C

CT5

+

cluster # 1

reference

VANA

AGND

DGND

FAULT

SDA

cluster # 1

reference

CTn

CBn

6 cell

voltage

measure

BATTERY PACK

CONTROLLER

EEPROM

(OPTIONAL)

SCL

MC33772C

SO

CSB

CT1

SPI_COM_EN

cluster # 1

CB2:1_C

reference

RESET

+

MCU

T1

SI/RDTX_IN+

CB1

T1

SPI1

MC33664

SCLK/RDTX_IN-

VCP

CTREF

SPI2

GNDSUB

GNDFLG

cluster # 1

reference

GNDCP

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

VCOM cluster # 1

cluster # 1

reference

ISENSE+

ISENSE-

current

measure

cluster # 1

reference

aaa-037592

Figure 2.ꢀSimplified application diagram, TPL use case

MC33772C

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MC33772C

Battery cell controller IC

4 Applications

• Automotive: 12 V and high-voltage battery packs

• E-bikes, e-scooters, drones

• Energy storage systems

• Uninterruptible power supply (UPS)

• Battery junction box

5 Ordering information

5.1 Part numbers definition

MC33772C xꢁyꢁzꢁAE/R2

Table 1.ꢀPart number breakdown

Code

Option

Description

x

T

A

x = T (TPL communication type)

y = A (Advanced)

y

z

C

y = C (Current)

P

y = P (Premium)

0

z = 0 (0 channels)

z = 1 (3 to 6 channels)

z = 2 (3 to 4 channels)

Package suffix

1

2

AE

R2

Tape and reel indicator

MC33772C

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MC33772C

Battery cell controller IC

5.2 Part numbers list

This section describes the part numbers available to be purchased along with their

differences. Valid orderable part numbers are provided on the web. To determine the

orderable part numbers for this device, go to http://www.nxp.com.

Table 2.ꢀAdvanced orderable part table

Package type is 48-pin LQFP-EP

Orderable part

Number of

channels

OV/UV

Precision GPIO as temperature

channels and OT/UT

Current channel or

coulomb count

TPL differential communication protocol

MC33772CTA1AE

MC33772CTA2AE

3 to 6

3 to 4

Yes

No

Table 3.ꢀPremium orderable part table

Package type is 48-pin LQFP-EP

Orderable part

Number of

channels

OV/UV

Precision GPIO as temperature

channels and OT/UT

Current channel or

coulomb count

TPL differential communication protocol with current measurement option

MC33772CTP1AE

MC33772CTP2AE

3 to 6

3 to 4

Yes

Table 4.ꢀCurrent orderable part table

Package type is 48-pin LQFP-EP

Orderable part

Number of

channels

OV/UV

Precision GPIO as temperature

channels and OT/UT

Current channel or

coulomb count

TPL differential communication protocol

MC33772CTC0AE

MC33772CTC1AE

0

1

No

Yes

Note: To order parts in tape and reel, add an R2 suffix to the part number.

MC33772C

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MC33772C

Battery cell controller IC

6 Pinning information

6.1 Pinout diagram

terminal 1

index area

1

2

36

VPWR2

VPWR1

FAULT

VPRE

AN0/GPIO0

RDTX_OUT+

SI/RDTX_IN+

SCLK/RDTX_IN-

RDTX_OUT-

CGND

35

34

33

32

31

30

29

28

27

26

25

3

4

5

VCP

6

GNDCP

CT_6

48 LQFP-EP

GNDFLAG

7

VCOM

8

CB_6

CSB

9

CB_6:5_C

CB_5

VDDIO

10

11

12

SO

CT_5

SCL

CT_4

SDA

aaa-029761

Transparent top view

Figure 3.ꢀPinout diagram

6.2 Pin definitions

Table 5.ꢀPin definitions

Pin number Pin name

Pin function

Input

Definition

1

2

3

VPWR2

VPWR1

FAULT

Power supply input to the MC33772C

Input

Output

Fault output dependent on user defined internal or external faults. If not used, it must

be left open

4

VPRE

VCP

Output

Ground

Input

Pre-regulator voltage. Connect to a 470 nF capacitor

Charge pump. Decouple with a 10 nF capacitor

5

6

GNDCP

CT_6

Charge pump capacitor ground

7

Cell terminal pin 6 input. Terminate to LPF resistor

Cell balance driver. Terminate to cell 6 cell balance load resistor

Cell balance 6:5 common. Terminate to cell 6 and 5 common pin

Cell balance driver. Terminate to cell 5 cell balance load resistor

Cell terminal pin 5 input. Terminate to LPF resistor

Cell terminal pin 4 input. Terminate to LPF resistor

Cell balance driver. Terminate to cell 4 cell balance load resistor

8

CB_6

Output

Input

9

CB_6:5_C

CB_5

10

11

12

13

CT_5

CT_4

Input

CB_4

Output

MC33772C

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MC33772C

Battery cell controller IC

Table 5.ꢀPin definitions...continued

Pin number Pin name

Pin function

Definition

14

15

16

17

18

19

20

21

22

23

CB_4:3_C

CB_3

Output

Input

Cell balance 4:3 common. Terminate to cell 4 and 3 common pin

Cell balance driver. Terminate to cell 3 cell balance load resistor

Cell terminal pin 3 input. Terminate to LPF resistor

CT_3

CT_2

Input

Cell pin 2 input. Terminate to LPF resistor

CB_2

Output

Input

Cell balance driver. Terminate to cell 2 cell balance load resistor

Cell balance 2:1 common. Terminate to cell 2 and 1 common pin

Cell balance driver. Terminate to cell 1 cell balance load resistor

Cell pin 1 input. Terminate to LPF resistor

CB_2:1_C

CB_1

CT_1

CT_REF

SPI_COM_EN

Input

Cell terminal REF input. Terminate to LPF resistor

Input

SPI communication enable input. Wire to VPRE to use SPI communication, else wire

to ground to use TPL communication

24

RESET

Input

RESET is an active high input. RESET has an internal pull down. If not used, it can be

shorted to GND

25

26

27

28

SDA

SCL

I/O

I²C data

I/O

I²C clock

SO

Output

Input

SPI serial output

VDDIO

IO voltage for I²C and SPI interfaces. Voltage level corresponding to logic 1 will be the

same as VDDIO

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

CSB

Input

Output

Ground

I/O

SPI active low chip select. If not used, it must be shorted to ground

Communication regulator output. Decouple with 2.2 μF to CGND

Communication decoupling ground, terminate to GNDSUB

TPL receive/transmit output negative

VCOM

CGND

RDTX_OUT−

SCLK/RDTX_IN-

SI/RDTX_IN+

RDTX_OUT+

AN0 GPIO0

AN1 GPIO1

AN2 GPIO2

AN3 GPIO3

AN4 GPIO4

AN5 GPIO5

AN6 GPIO6

ISENSE+

ISENSE−

AGND

I/O

SPI clock or TPL receive/transmit input negative

SPI serial input or TPL receive/transmit input positive

TPL receive/transmit output positive

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

I/O

General purpose input/output

Input

I/O

Current measurement input +

Current measurement input −

Analog ground, terminate to GNDSUB

DGND

I/O

Digital ground, terminate to GNDSUB

VANA

Output

Ground

Precision ADC analog supply. Decouple with 47 nF capacitor to AGND

Ground reference for device, terminate to reference of battery cluster

GNDSUB

GNDFLAG

Exposed pad, terminate to lowest potential of the battery cluster and to heat

dissipation area of PCB

MC33772C

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MC33772C

Battery cell controller IC

7 General product characteristics

7.1 Ratings and operating requirements relationship

The operating voltage range pertains to the VPWR pins referenced to the AGND pins.

Table 6.ꢀRatings vs. operating requirements

Fatal range

Lower limited operating range Normal operating range

Upper limited

Fatal range

operating range

Permanent

failure may

occur

No permanent failure, but IC

functionality is not guaranteed

100 % functional

Permanent

failure may

occur

V_PWR< −0.3 V

5.0 V ≤ V_PWR≤ 6.0 V (SPI)

6.4 V ≤ V_PWR≤ 7.0 V (TPL)

Reset range:

6.0 V ≤ V_PWR≤ 30 V (SPI)

7.0 V ≤ V_PWR≤ 30 V (TPL)

30 V < V_PWR≤ 40 V 40 V < V_PWR

IC parameters

might be out of

specification.

Detection of V_PWR

overvoltage is

functional

–0.3 V ≤ V_PWR≤ 5.0 V (SPI)

–0.3 V ≤ V_PWR≤ 6.4 V (TPL)

POR with V_PWRfalling:

4.8 V ≤ V_PWR< 5.0 V (SPI)

6.1 V ≤ V_PWR< 6.4 V (TPL)

POR with V_PWRrising:

5.6 V ≤ V_PWR< 6.0 V (SPI)

6.6 V ≤ V_PWR< 7.0 V (TPL)

Handling range - No permanent failure

In both upper and lower limited operating range, no information can be provided about IC

performance. Only the detection of V_PWRovervoltage is guaranteed in the upper limited

operating range.

Performance in normal operating range is guaranteed only if there is a minimum of three

battery cells in the stack.

7.2 Maximum ratings

Table 7.ꢀMaximum ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction or permanent damage to

the device.

Symbol

Description (rating)

Min

Max

Unit

Electrical ratings

VPWR1, VPWR2

CT6

Supply input voltage

–0.3

−0.3

−10

−0.3

—

40

V

Cell terminal voltage

VPWR to CT6

CT_Nto CT_N-1

CT_N(CURRENT)

Voltage across VPWR1,2 pins pair and CT6 pin

Cell terminal differential voltage

Cell terminal input current

10

V

[1]

6.7

±500

10

V

µA

V

CB_Nto CB_{N:N-1_C}

CB_{N:N-1_C}to CB_N-1

Cell balance differential voltage

—

CB_N-1to CT_N-1

VISENSE

VCOM

Cell balance input to cell terminal input

−10

−0.5

—

+10

2.5

5.8

V

ISENSE+ and ISENSE– pin voltage

Maximum voltage may be applied to VCOM pin from external source

MC33772C

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MC33772C

Battery cell controller IC

Table 7.ꢀMaximum ratings...continued

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction or permanent damage to

the device.

Symbol

VANA

Description (rating)

Min

—

Max

3.1

Unit

V

Maximum voltage may be applied to VANA pin

VPRE

Maximum voltage which may be applied to VPRE pin from external

source

—

7.0

V

VCP

Maximum voltage which may be applied to VCP pin from external

source

—

14

V

VDDIO

Maximum voltage which may be applied to VDDIO pin from external

source

5.8

V_GPIO0

GPIO0 pin voltage

–0.3

−0.3

−2

6.5

V

V_GPIOx

GPIOx pins (x = 1 to 6) voltage

VCOM + 0.5

V_DIG

Voltage I²C pins (SDA, SCL)

VDDIO + 0.5

V

V_RESET

V_CSB

V_{SPI_COMM_EN}

V_SO

RESET pin

6.5

V

CSB pin

6.5

V

SPI_COMM_EN

7.0

V

SO pin

VDDIO + 0.5

V

V_GPIO5,6

FAULT

I_{pin_unpowered}

V_COMM

Maximum voltage for GPIO5 and GPIO6 pins used as current input

Maximum applied voltage to pin

Input current in a pin when the device is unpowered

2.5

7.0

2

V

mA

V

Maximum voltage to pins RDTX_OUT+, RDTX_OUT–, SI/RDTX_IN+,

CLK/RDTX_IN–

−10

10

V_ESD1

ESD voltage

V

Human body model (HBM)

Charge device model (CDM)

Charge device model corner pins (CDM)

—

±2000

±500

±750

[2]

[3]

V_ESD2

ESD voltage (VPWR1, VPWR2, CTx, CBx, GPIOx, ISENSE+,

ISENSE–, RDTX_OUT+, RDTX_OUT–, SI/RDTX_IN+, SCLK/ RDTX_

IN–)

V

—

±4000

Human body model (HBM)

V_ESD3

ESD voltage (CTREF, CTx, CBx, GPIOx, ISENSE+, ISENSE−, RDTX_

OUT+, RDTX_OUT−, SI/RDTX_IN+, SCLK/ RDTX_IN−)

IEC 61000-4-2, Unpowered (Gun configuration: 330 Ω / 150 pF)

HMM, Unpowered (Gun configuration: 330 Ω / 150 pF)

—

±8000

ISO 10605:2009, Unpowered (Gun configuration: 2 kΩ / 150 pF)

ISO 10605:2009, Powered (Gun configuration: 2 kΩ / 330 pF)

[1] Adjacent CT pins may experience an overvoltage that exceeds their maximum rating during OV/UV functional verification test or during open line

diagnostic test. Nevertheless, the IC is completely tolerant to this special situation.

[2] ESD testing is performed in accordance with the human body model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω).

[3] These voltage values can be sustained only if ESD caps are used as described in MC33772C External Components.

MC33772C

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MC33772C

Battery cell controller IC

7.3 Thermal characteristics

Table 8.ꢀThermal ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction or permanent damage to

the device.

Symbol

Thermal ratings

Operating temperature

Description (rating)

Min

Max

Unit

°C

T_A

T_J

Ambient (SPI application)

Ambient (TPL application)

Junction^[1]

–40

+125

+105

+150

T_STG

Storage temperature

−55

—

+150

260

°C

[2] [3]

T_PPRT

Peak package reflow temperature

Thermal resistance and package dissipation ratings

[4]

[5] [6]

[7]

R_ΘJB

Junction-to-board (bottom exposed pad soldered to board) 48 LQFP EP

—

11

72

30

24

0.98

4

°C/W

R_ΘJA

Junction-to-ambient, natural convection, single-layer board (1s) 48 LQFP EP

Junction-to-ambient, natural convection, four-layer board (2s2p) 48 LQFP EP

Junction-to-case top (exposed pad) 48 LQFP EP

R_ΘJA

R_ΘJCTOP

[8]

R_ΘJCBOTTOMJunction-to-case bottom (exposed pad) 48 LQFP EP

ΨJT Junction to package top, natural convection

[9]

[1] The user must ensure that the average maximum operating junction temperature (Tj) is not exceeded.

[2] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a

malfunction or permanent damage to the device.

[3] NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture

Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and

review parametrics.

[4] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board

near the package.

[5] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

[6] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

[7] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1), with the cold plate

temperature used for the case temperature.

[8] Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.

[9] Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2.

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MC33772C

Battery cell controller IC

7.4 Electrical characteristics

Table 9.ꢀStatic and dynamic electrical characteristics

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

Power management

V_PWR(FO)Supply voltage

Parameter

Min

Typ

Max

Unit

V

Full parameter specification (SPI application)

Full parameter specification (TPL application)

6.0

7.0

—

30

I_VPWR

Supply current (base value)

mA

Normal mode, cell balance OFF, ADC inactive, SPI

communication inactive, IVCOM = 0 mA

—

6.0

8.0

—

Normal mode, cell balance OFF, ADC inactive, TPL

communication inactive, IVCOM = 0 mA

I_{VPWR(TPL_TX1)}

Supply current adder when TPL communication active

with only one device in daisy chain

8.3

mA

I_{VPWR(TPL_TX1/}

Supply current adder when TPL communication active

with multiple devices in daisy chain

—

10

—

TX2)

I_VPWR(CBON)

I_VPWR(ADC)

Supply current adder to set all 6 cell balance switches

ON

2.0

Delta supply current to perform ADC conversions

(addend)

ADC1-A,B continuously converting

ADC2 continuously converting

—

4.7

1.0

—

I_VPWR(SS)

Supply current in sleep and idle modes, communication

inactive, cell balance off, oscillator monitor on, cyclic

measurement off

SPI mode (T_A= 25 °C)

—

32

—

60

—

µA

SPI mode (−40 °C ≤ T_A≤ 85 °C)

SPI mode (T_A= 125 °C)

42

75

—

TPL mode (T_A= 25 °C)

—

TPL mode (−40 °C ≤ T_A≤ 85 °C)

TPL mode (T_A= 125 °C)

100

138

—

I_VPWR(CKMON)

V_{PWR(OV_FLAG)}

V_{PWR(LV_FLAG)}

V_{PWR(UV_POR)}

Clock monitor current consumption

V_PWRovervoltage fault threshold (flag)

V_PWRlow-voltage warning threshold (flag)

5

µA

V

33.5

7.8

—

V

V_PWRundervoltage shutdown threshold (POR), falling

VPWR

V

SPI mode

TPL mode

—

4.9

—

6.25

V_{PWR(UV_RIS)}

V_PWRundervoltage shutdown threshold (POR), rising

VPWR

V

SPI mode

TPL mode

—

5.8

6.8

—

t_VPWR(FILTER)

V_PWROV, LV filter

—

50

—

µs

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Battery cell controller IC

Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

VPRE power supply

VPRE

Pre-regulator voltage range - decouple with 470 nF

V

SPI mode, ILoad = 15 mA

—

4.9

—

5.75

—

SPI mode, ILoad = 15 mA, 5.0 V ≤ VPWR < 6.0 V

TPL mode, ILoad = 70 mA

6.5

V_{PRE(UV_TH)}

VCP power supply

VCP

PRE undervoltage threshold leading to a reset

—

4.25

—

V

Charge pump voltage range

2 × V_PRE– 2

—

2 × V_PRE

—

V

V_{CP(UV_TH)}

Undervoltage threshold for VCP minus VPRE

1.5

VDDIO power supply

V_DDIO

IO supply for I²C and SPI interfaces - voltage range

—

4.15

—

V

VCOM power supply

V_COM

VCOM output voltage

—

5.4

5.0

—

5.0

—

V

I_VCOM

VCOM output current allocated for external use

VCOM undervoltage fault threshold

VCOM undervoltage hysteresis

mA

V

V_COM(UV)

V_{COM_HYS}

4.4

100

10

—

mV

µs

ms

V

t_{VCOM(FLT_TIMER)}VCOM undervoltage fault timer

—

t_VCOM(RETRY)

V_COM(OV)

I_LIM(OC)

VCOM fault retry timer

10

—

VCOM overvoltage fault threshold

—

5.9

VCOM current limit in TPL mode

VCOM current limit SPI mode

65

35

—

140

mA

R_VCOM(SS)

t_VCOM

VCOM sleep mode pulldown resistor

—

2.0

—

kΩ

µs

VCOM rise time (CL = 2.2 µF ceramic X7R only)

400

VANA power supply

V_ANA

VANA output voltage (not used by external circuits)

V

Decouple with 47 nF X7R 0603 or 0402

VANA undervoltage fault threshold

VANA undervoltage hysteresis

VANA undervoltage fault timer

VANA overvoltage fault threshold

VANA fault retry timer

—

5

2.65

2.4

50

—

V_ANA(UV)

V

V_{ANA_HYS}

V_{ANA(FLT_TIMER)}

V_ANA(OV)

—

mV

µs

V

11

—

2.8

10

—

t_VANA(RETRY)

I_LIM(OC)

R_{VANA_RPD}

t_VANA

—

ms

mA

kΩ

µs

VANA current limit

—

10

—

VANA sleep mode pull-down resistor

VANA rise time (CL = 47 nF ceramic X7R only)

—

1.0

—

100

ADC1-A, ADC1-B

CTn_(LEAKAGE)

CT_N

Cell terminal input leakage current

—

10

50

—

nA

Cell terminal input current during conversion

Cell terminal open load detection pulldown resistor

VPWR terminal measurement resolution

nA

R_PD

950

Ω

V_{VPWR_RES}

2.44148

mV/LSB

MC33772C

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MC33772C

Battery cell controller IC

Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

V_{VPWR_RNG}

VPWR terminal measurement range

SPI application

V

6.0

7.0

—

36

TPL application

VPWR_{TERM_ERR}VPWR terminal measurement accuracy

−0.5

0.0

—

0.5

%

V_{CT_RNG}

ADC differential input voltage range for CTn to CTn-1

4.85

V

V_{CT_ANx_RES}

Cell voltage and ANx resolution in 15-bit MEAS_xxxx

registers

µV/LSB

—

152.58789

—

V_{ANx_RATIO_RES}

V_ERR

ANx resolution in 15-bit MEAS_xxxx registers in

ratiometric mode

VCOM ×

30.51758

Cell voltage measurement error

0.1 V ≤ V_CELL≤ 4.85 V, –40 °C ≤ T_A≤ 105 °C

(or –40 °C ≤ T_J≤ 125 °C)

mV

—

±0.7

±0.4

±0.5

±0.7

—

V_{ERR_1}

V_{ERR_2}

V_{ERR_3}

V_{ERR_4}

V_{ERR_5}

V_{ANx_ERR}

Cell voltage measurement error

0 V ≤ V_CELL≤ 1.5 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

Cell voltage measurement error

1.5 V ≤ V_CELL≤ 2.7 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

Cell voltage measurement error

2.7 V ≤ V_CELL≤ 3.7 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

Cell voltage measurement error

3.7 V ≤ V_CELL≤ 4.3 V, –40 °C ≤ T_A≤ 60 °C

(or –40 °C ≤ T_J≤ 85 °C)

Cell voltage measurement error

1.5 V ≤ V_CELL≤ 4.5 V, –40 °C ≤ T_A≤ 105 °C

(or –40 °C ≤ T_J≤ 125 °C)

Magnitude of ANx error in the entire measurement

range:

Ratiometric measurement

−16

−10

—

16

10

Absolute measurement, input in the range

[1.0, 4.5] V

Absolute measurement, input in the range

[0, 4.85] V for −40 °C < T_A< 60 °C

−8.0

−11

—

8.0

11

Absolute measurement after soldering

and aging, input in the range [0, 4.85] V

for −40 °C < T_A< 105 °C

t_VCONV

Single channel net conversion time

13-bit resolution

µs

—

6.77

9.43

—

14-bit resolution

15-bit resolution

14.75

25.36

16-bit resolution

V_{V_NOISE}

Conversion noise

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

µVrms

—

1800

1000

600

—

400

MC33772C

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Battery cell controller IC

Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

ADC2/current sense module

V_INC

V_IND

ISENSE+/ISENSE− input voltage (reference to AGND)

ISENSE+/ISENSE− differential input voltage range

−300

−150

—

300

150

0.5

100

5.0

0.5

—

mV

µV

V_{ISENSEX(OFFSET)}ISENSE+/ISENSE− input voltage offset error

—

I_SENSEX(BIAS)

I_SENSE(DIF)

I_GAINERR

ISENSE+/ISENSE− input bias current

ISENSE+/ISENSE− differential input bias current

ISENSE error including nonlinearities

ISENSE open load injected current

−100

−5.0

−0.5

—

nA

—

nA

—

%

I_{ISENSE_OL}

V_{ISENSE_OL}

V_2RES

130

460

0.6

µA

ISENSE open load detection threshold

Current sense user register resolution

—

mV

µV/LSB

mV

—

V_{PGA_SAT}

PGA saturation half-range

Gain = 256

—

4.9

19.5

78.1

150

—

Gain = 64

Gain = 16

Gain = 4

V_{PGA_ITH}

Voltage threshold for PGA gain increase

mV

Gain = 256

Gain = 64

Gain = 16

Gain = 4

—

2.344

9.375

37.50

V_{PGA_DTH}

Voltage threshold for PGA gain decrease

Gain = 256

Gain = 64

Gain = 16

Gain = 4

—

4.298

17.188

68.750

—

t_{AZC_SETTLE}

t_ICONV

Time to perform auto-zero procedure after enabling the

current channel

—

200

—

µs

ADC conversion time including PGA settling time

13-bit resolution

—

19.00

21.67

27.00

37.67

—

14-bit resolution

15-bit resolution

16-bit resolution

V_{I_NOISE}

ADC_CLK

Noise at 16-bit conversion

—

3.01

8.33

6.0

—

µVrms

MHz

Noise error at 13-bit conversion

ADC2 and ADC1-A,B clocking frequency

Cell balance drivers

V_DS(CLAMP)

Cell balance driver VDS active clamp voltage

—

11

—

V

V_{OUT(FLT_TH)}

Output fault detection voltage threshold

Balance off (open load)

0.55

Balance on (shorted load)

R_{PD_CB}

Output OFF open load detection pull-down resistor

Balance off, open load detect disabled

kΩ

—

2.0

—

MC33772C

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MC33772C

Battery cell controller IC

Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

I_OUT(LKG)

Output leakage current

µA

Balance off, open load detect disabled at

V_DS= 4.0 V

—

1.0

R_DS(on)

Drain-to-source on resistance

I_OUT= 300 mA, T_J= 125 °C

I_OUT= 300 mA, T_J= 25 °C

I_OUT= 300 mA, T_J= −40 °C

Ω

—

0.80

—

0.5

0.4

—

I_{LIM_CB}

t_ON

Driver current limitation (shorted resistor)

310

—

950

mA

µs

Cell balance driver turn on

R_L= 15 Ω

—

350

—

t_OFF

Cell balance driver turn off

R_L= 15 Ω

µs

—

200

20

—

t_{BAL_DEGLICTH}

Short/open detect filter time

Internal temperature measurement

IC_TEMP1_ERR IC temperature measurement error

IC_TEMP1_RES IC temperature resolution

−3.0

—

0.032

170

10

3.0

—

K

K/LSB

°C

TSD_TH

Thermal shutdown

—

TSD_HYS

Thermal shutdown hysteresis

—

°C

Default operational parameters

V_CTOV(TH)

Cell overvoltage threshold (8 bits)

0.0

—

4.2

19.53125

2.5

5.0

—

V

V_CTOV(RES)

V_CTUV(TH)

V_CTUV(RES)

V_{GPIO_OT(TH)}

Cell overvoltage threshold resolution

Cell undervoltage threshold (8 bits)

Cell undervoltage threshold resolution

mV/LSB

0.0

—

5.0

—

V

19.53125

1.16

mV/LSB

V

GPIOx configured as ANx input overtemperature

threshold from POR

—

V_{GPIO_OT(RES)}

V_{GPIO_UT(TH)}

Overtemperature voltage threshold resolution

—

4.8828125

3.82

—

mV/LSB

V

GPIOx configured as ANx input undertemperature

threshold from POR

V_{GPIO_UT(RES)}

Undertemperature voltage threshold resolution

—

4.8828125

—

mV/LSB

General purpose input/output GPIOx

V_IH

V_IL

Input high-voltage (3.3 V compatible)

2.0

—

1.0

—

V

Input low-voltage (3.3 V compatible)

Input hysteresis

V

V_HYS

I_IL

—

100

mV

nA

Input leakage current

Pins 3-state, V_IN= V_COMor AGND

−100

−30

—

100

30

I_IDL

Differential input leakage current GPIO 5,6

nA

GPIO 5,6 configured as digital inputs for current

measurement

V_OH

V_OL

Output high-voltage I_OH= −0.5 mA

Output low-voltage I_OL= +0.5 mA

V_COM− 0.8

—

0.8

V

V_ADC

Analog ADC input voltage range for ratiometric

measurements

AGND

V_COM

MC33772C

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Battery cell controller IC

Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

V_OL(TH)

Parameter

Min

—

Typ

0.15

5.0

50

Max

—

Unit

V

Analog input open pin detect threshold

Internal open detection pull-down resistor

GPIO0 WU de-glitch filter

R_OPENPD

t_{GPIO0_WU}

t_{GPIO0_FLT}

t_{GPIO2_SOC}

t_{GPIOx_DIN}

Reset input

V_{IH_RST}

—

kΩ

µs

—

GPIO0 daisy chain de-glitch filter both edges

GPIO2 convert trigger de-glitch filter

GPIOx configured as digital input de-glitch filter

—

20

—

2.0

—

2.5

5.6

Input high-voltage (3.3 V compatible)

Input low-voltage (3.3 V compatible)

Input hysteresis

2.0

—

1.0

—

V

V_{IL_RST}

V

V_HYS

0.6

100

V

t_RESETFLT

R_{RESET_PD}

RESET de-glitch filter

—

µs

kΩ

Input logic pull down (RESET)

—

SPI_COM_EN input

V_IH

Input high-voltage (3.3 V compatible)

2.0

—

1.0

—

V

V_IL

Input low-voltage (3.3 V compatible)

Input hysteresis

V

V_HYS

—

450

mV

Digital interface

V_{FAULT_HA}

I_{FAULT_CL}

R_{FAULT_PD}

V_{IH_COMM}

FAULT output (high active, I_OH= 1.0 mA)

FAULT output current limit

—

3.0

—

4.9

—

25

—

V

mA

kΩ

V

FAULT output pulldown resistance

Voltage threshold to detect the input as high

100

SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL

(NOTE: needs to be 3.3 V compatible)

—

2.0

V_{IL_COMM}

Voltage threshold to detect the input as low

V

SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL

0.8

—

V_HYS

Input hysteresis

mV

nA

kΩ

SI/RDTX_IN+, SCLK/RDTX_IN−, CSB, SDA, SCL

100

I_{LOGIC_SS}

Sleep state input logic current

CSB

−100

—

100

—

R_{SCLK_PD}

Input logic pulldown resistance (SCLK/RDTX_IN–, SI/

RDTX+)

20

R_{I_PU}

Input logic pullup resistance to V_COM(CSB, SDA, SCL)

3-state SO input current 0 V to V_COM

—

−2.0

100

—

2.0

—

kΩ

µA

V

I_{SO_TRI}

V_{SO_HIGH}

V_{SO_LOW}

SO high-state output voltage with I_SO(HIGH)= −2.0 mA

V_DDIO− 0.4

—

SO, SDA, SLK low-state output voltage with

I_SO(HIGH)= −2.0 mA

—

0.4

V

CSB_{WU_FLT}

CSB wake-up de-glitch filter, low to high transition

—

50

—

µs

MC33772C

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Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

System timing

t_{CELL_CONV}

Time needed to acquire all 6 cell voltages and the

current after an on demand conversion

µs

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

—

41

57

—

89

152

t_SYNC

V/I synchronization time

µs

ms

ADC1-A,B at 13 bit, ADC2 at 13 bit

ADC1-A,B at 14 bit, ADC2 at 13 bit

ADC1-A,B at 15 bit, ADC2 at 13 bit

ADC1-A,B at 16 bit, ADC2 at 13 bit

—

41.39

42.71

47.37

95.14

—

t_SYNC

V/I synchronization time

ADC1-A,B at 13 bit, ADC2 at 14 bit

ADC1-A,B at 14 bit, ADC2 at 14 bit

ADC1-A,B at 15 bit, ADC2 at 14 bit

ADC1-A,B at 16 bit, ADC2 at 14 bit

—

46.73

48.05

50.71

92.47

—

t_SYNC

V/I synchronization time

ADC1-A,B at 13 bit, ADC2 at 15 bit

ADC1-A,B at 14 bit, ADC2 at 15 bit

ADC1-A,B at 15 bit, ADC2 at 15 bit

ADC1-A,B at 16 bit, ADC2 at 15 bit

—

57.39

58.71

61.37

87.14

—

t_SYNC

V/I synchronization time

ADC1-A,B at 13 bit, ADC2 at 16 bit

ADC1-A,B at 14 bit, ADC2 at 16 bit

ADC1-A,B at 15 bit, ADC2 at 16 bit

ADC1-A,B at 16 bit, ADC2 at 16 bit

—

78.73

80.05

82.71

88.02

—

t_VPWR(READY)

Time after VPWR connection for the IC to be ready for

initialization

—

5.0

t_WAKE-UP

t_{WAKE_DELAY}

t_NOWUP

Power up duration

—

600

—

440

—

µs

ms

Time between wake pulses

Time, starting from the first SOM received, to go back to

Sleep/Idle mode time after receiving incomplete TPL bus

wake-up sequence

1.3

t_IDLE

Idle timeout after POR

—

60

—

s

t_BALANCE

t_CYCLE

t_FAULT

Cell balance timer range

Cyclic acquisition timer range

0.5

0.0

511

8.5

min

s

Fault detection to activation of fault pin

Normal mode

µs

—

56

t_DIAG

t_EOC

Diagnostic mode timeout

0.047

1.0

8.5

s

SOC to data ready (includes post processing of data)

13-bit resolution

µs

—

148

201

307

520

—

14-bit resolution

15-bit resolution

16-bit resolution

t_SETTLE

Time after SOC to begin converting with ADC1-A,B

—

12.28

—

µs

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Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

t_{CLST_TPL}

Time needed to send an SOC command and read

back 6 cell voltages, 7 temperatures, 1 current, and

1 coulomb counter with TPL communication working at

2.0 Mbit/s and ADC1-A,B configured as follows (with

ADC_CFG[AVG] = 0):

ms

—

0.79

0.85

0.95

1.16

—

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

t_{CLST_SPI}

Time needed to send an SOC command and read

back 6 cell voltages, 7 temperatures, 1 current, and

1 coulomb counter with SPI communication working at

4.0 Mbit/s and ADC1-A,B configured as follows (with

ADC_CFG[AVG] = 0):

ms

—

0.48

0.54

0.64

0.86

—

13-bit resolution

14-bit resolution

15-bit resolution

16-bit resolution

t_{I2C_DOWNLOAD}

t_{I2C_ACCESS}

Time to download EEPROM calibration after POR

—

1.0

—

ms

EEPROM access time, EEPROM write (depends on

device selection)

5.0

t_{WAVE_DC_BITx}

Daisy chain duty cycle off time

t_{WAVE_DC_BITx}= 00

µs

—

500

1.0

10

—

Daisy chain duty cycle off time

t_{WAVE_DC_BITx}= 01

ms

Daisy chain duty cycle off time

t_{WAVE_DC_BITx}= 10

Daisy chain duty cycle off time

t_{WAVE_DC_BITx}= 11

—

100

500

—

t_{WAVE_DC_ON}

t_{COM_LOSS}

Daisy chain duty cycle on time

µs

Time out to reset the IC in the absence of

communication

1024

ms

SPI interface

t_TD

Sequential data transfer delay in SPI mode (N)

SCLK frequency

1.0

—

4.0

—

15

—

40

µs

MHz

ns

F_SCK

t_{SCK _H}

t_{SCK _L}

t_SCK

SCLK high time (A)

125

250

—

SCLK high time (B)

SCLK period (A+B)

t_FALL

SCLK falling time

t_RISE

SCLK rising time

—

t_SET

SCLK setup time (O)

20

t_HOLD

SCLK hold time (P)

20

t_{SI_SETUP}

t_{SI_HOLD}

t_{SO_VALID}

SI setup time (F)

40

SI hold time (G)

40

SO data valid, rising edge of SCLK to SO data valid (I)

—

MC33772C

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Table 9.ꢀStatic and dynamic electrical characteristics...continued

Characteristics noted under conditions: 6.0 V ≤ V_PWR≤ 30 V (SPI mode) or 7.0 V ≤ V_PWR≤ 30 V (TPL mode), −40 °C ≤ T_A≤ 125 °C (SPI

mode) or –40 °C ≤ T_A≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to V_PWR= 24 V, T_A= 25 °C, unless

otherwise noted.

Symbol

t_{SO_EN}

Parameter

Min

—

Typ

—

Max

40

Unit

ns

SO enable time (H)

SO disable time (K)

CSB lead time (L)

CSB lag time (M)

t_{SO_DISABLE}

t_{CSB_LEAD}

t_{CSB_LAG}

—

40

ns

100

—

ns

—

ns

TPL interface (MCU)

t_{MCU_RES}Time between two consecutive message request

4.0

—

µs

transmitted by MCU

t_{WU_Wait}

Time the MCU shall wait after sending first wake-up

message per MC33772C IC

0.75

ms

TPL interface (MC33772C)

t_{TPL_TD}Sequential data transfer delay in TPL mode

t_TPL

t_{port_delay}

t_RES

V_{RDTX INTH}

t_EOM

—

4.0

208

—

µs

ns

µs

mV

µs

Transmit pulse duration

Port delay introduced by each repeater in MC33772C

Slave response after read command

Differential receiver threshold

0.95

—

5.0

580

250

—

Message timeout duration

—

7.5 Timing diagrams

CSB

N

M

P

K

O

L

A

B

don't care level

SCLK

don't care level

H

I

SO

SI

3-state

MSB

LSB

F

G

MSB

aaa-042372

Figure 4.ꢀLow-voltage SPI interface timing

Start of

Bit 47

Bit 46

Bit 2

Bit 1

Bit 0

End of

message

Logic 1 Logic 1 Logic 1 Logic 0 Logic 0 message

3.2 V

RDTX_IN+

RDTX_OUT+

2.5 V

1.8 V

RDTX_IN-

RDTX_OUT-

aaa-032610

Figure 5.ꢀTransformer communication signaling

MC33772C

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8 Packaging

8.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package

outline drawing, go to www.nxp.com and perform a keyword search for the document

number of the drawings.

Table 10.ꢀPackage Outline

Package

Suffix

AE

Package outline drawing number

48-pin LQFP-EP

SOT1571-1

MC33772C

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MC33772C

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MC33772C

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MC33772C

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Figure 6.ꢀPackage outline

MC33772C

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9 Revision history

Revision history

Revision

v.3

Date

Description

20210604

20210310

20200324

update to align with data sheet MC33772C v.3

update to align with preliminary data sheet

initial version

v.2

v.1

MC33772C

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10 Legal information

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

10.1 Definitions

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

10.2 Disclaimers

Suitability for use in automotive applications — This NXP product has

been qualified for use in automotive applications. If this product is used

by customer in the development of, or for incorporation into, products or

services (a) used in safety critical applications or (b) in which failure could

lead to death, personal injury, or severe physical or environmental damage

(such products and services hereinafter referred to as “Critical Applications”),

then customer makes the ultimate design decisions regarding its products

and is solely responsible for compliance with all legal, regulatory, safety,

and security related requirements concerning its products, regardless of

any information or support that may be provided by NXP. As such, customer

assumes all risk related to use of any products in Critical Applications and

NXP and its suppliers shall not be liable for any such use by customer.

Accordingly, customer will indemnify and hold NXP harmless from any

claims, liabilities, damages and associated costs and expenses (including

attorneys’ fees) that NXP may incur related to customer’s incorporation of

any product in a Critical Application.

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Security — Customer understands that all NXP products may be subject

to unidentified or documented vulnerabilities. Customer is responsible

for the design and operation of its applications and products throughout

their lifecycles to reduce the effect of these vulnerabilities on customer’s

applications and products. Customer’s responsibility also extends to other

open and/or proprietary technologies supported by NXP products for use

in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up

appropriately. Customer shall select products with security features that best

meet rules, regulations, and standards of the intended application and make

the ultimate design decisions regarding its products and is solely responsible

for compliance with all legal, regulatory, and security related requirements

concerning its products, regardless of any information or support that may

be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,

reporting, and solution release to security vulnerabilities of NXP products.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

10.3 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

NXP — wordmark and logo are trademarks of NXP B.V.

MC33772C

All information provided in this document is subject to legal disclaimers.

Product brief

Rev. 3 — 4 June 2021

25 / 27

NXP Semiconductors

MC33772C

Battery cell controller IC

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Part number breakdown ....................................4

Tab. 7.

Tab. 8.

Tab. 9.

Maximum ratings ...............................................8

Thermal ratings ............................................... 10

Static and dynamic electrical

Advanced orderable part table ..........................5

Premium orderable part table ............................5

Current orderable part table ..............................5

Pin definitions ....................................................6

Ratings vs. operating requirements ...................8

characteristics ..................................................11

Tab. 10. Package Outline ..............................................20

Figures

Fig. 1.

Fig. 2.

Simplified application diagram, SPI use

case ...................................................................2

Simplified application diagram, TPL use

Fig. 3.

Fig. 4.

Fig. 5.

Fig. 6.

Pinout diagram ..................................................6

Low-voltage SPI interface timing .....................19

Transformer communication signaling .............19

Package outline ...............................................21

case ...................................................................3

MC33772C

All information provided in this document is subject to legal disclaimers.

Product brief

Rev. 3 — 4 June 2021

26 / 27

NXP Semiconductors

MC33772C

Battery cell controller IC

Contents

1

General description ............................................ 1

2

3

4

5

5.1

5.2

6

6.1

6.2

7

Features ............................................................... 1

Simplified application diagram ..........................2

Applications .........................................................4

Ordering information .......................................... 4

Part numbers definition ......................................4

Part numbers list ............................................... 5

Pinning information ............................................ 6

Pinout diagram .................................................. 6

Pin definitions .................................................... 6

General product characteristics ........................ 8

Ratings and operating requirements

7.1

relationship .........................................................8

Maximum ratings ............................................... 8

Thermal characteristics ....................................10

Electrical characteristics .................................. 11

Timing diagrams .............................................. 19

Packaging .......................................................... 20

Package mechanical dimensions .................... 20

Revision history ................................................ 24

Legal information ..............................................25

7.2

7.3

7.4

7.5

8

8.1

9

10

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 June 2021

Document identifier: MC33772C


型号：	MC33772CTA2AE
厂家：	NXP
描述：	Battery cell controller IC 电池
文件：	总27页 (文件大小：520K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33772CTA2AE [NXP]

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