MC33879APEK [NXP]
Switch, Congifurable 8 Channels, SOIC 32, Rail;
| 型号： | MC33879APEK |
| 厂家： | 
NXP |
| 描述： | Switch, Congifurable 8 Channels, SOIC 32, Rail PC 驱动 CD 光电二极管 接口集成电路 驱动器 |
| 文件： | 总26页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33879
Rev. 11.0, 7/2016
NXP Semiconductors
Technical Data
Configurable octal serial switch with
open load detect current disable
33879
33879A
The 33879 device is an 8-output hardware configurable, high-side/low-side
switch with 16-bit serial input control using the serial peripheral interface (SPI).
Two of the outputs may be controlled directly via a microcontroller for pulse-
width modulation (PWM) applications. The 33879 incorporates SMARTMOS
technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power
MOSFETs. The 33879 controls various inductive, incandescent, or LED loads by
directly interfacing with a microcontroller. The circuit’s innovative monitoring and
protection features include very low standby currents, cascade fault reporting,
internal +45 V clamp voltage for low-side configuration, -20 V high-side
configuration, output specific diagnostics, and independent overtemperature
protection.
HIGH-SIDE/ LOW-SIDE SWITCH
Features
• Designed to operate 5.5 V < VPWR < 27.5 V
EK SUFFIX (PB-FREE)
98ARL10543D
• 16-bit SPI for control and fault reporting, 3.3 V/5.0 V compatible
• Outputs are current limited (0.6 to 1.2 A) to drive incandescent lamps
• Output voltage clamp, +45 V (low-side) and -20 V (high-side) during
inductive switching
32-PIN SOICW
• On/Off control of open load detect current (LED application)
• Internal reverse battery protection on VPWR
• Loss of ground or supply will not energize loads or damage IC
• Maximum 5.0 μA IPWR standby current at 13 V VPWR
• RDS(ON) of 0.75 Ω at 25 °C typical
Applications
• Solenoids
• Relays
• Actuators
• Stepper motors
• Brush DC motors
• Incandescent lamps
• Short-circuit detect and current limit with automatic retry
• Independent overtemperature protection
V
V
PWR
BAT
5.0 V
33879
VPWR
D1
D2
D3
D4
S1
S2
VDD
High-side Drive
MCU
A0
EN
DI
S3
S4
MOSI
SCLK
CS
H-Bridge Configuration
M
SCLK
CS
V
V
D5
BAT
BAT
D6
D7
D8
S5
S6
S7
S8
MISO
PWM1
PWM2
D0
IN5
Low-side Drive
IN6
GND
Figure 1. 33879 simplified application diagram
© 2016 NXP B.V.
1
Orderable parts
Table 1. Orderable part variations
Part number (1)
Temperature (T )
Package
A
MC33879APEK
MC33879TEK
-40 to 125 °C
32 SOICW-EP
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
Table 2. Device variations
Symbol
Characteristic
Min.
Typ.
Max.
Unit
VPWR Supply Voltage
• 33879
• 33879A
VPWR
-16
-16
–
–
40
45
V
Output Fault Detection Current @ Threshold, High-side Configuration
Outputs Programmed OFF
• 33879
• 33879A
I
μA
μA
OUT(FLT-TH)
35
35
55
55
90
150
Output OFF Open Load Detection Current, High-side Configuration
VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
I
VPWR = 16 V
• 33879
• 33879A
OCO
65
60
100
100
160
190
Output OFF Open Load Detection Current, Low-side Configuration
VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
I
μA
VPWR =16 V
• 333879
• 338979A
OCO
40
40
75
75
135
150
EN Pull-down Current
EN = 5.0 V
• 333879
• 33879A
I
μA
V
EN
20
20
45
45
100
110
Output Fault Detection Voltage Threshold
Outputs Programmed OFF
• 33879
• 33879A
V
I
OUT(FLT-TH)
2.5
2.5
4.0
4.0
4.5
5.0
Output Fault Detection Current @ Threshold, Low-side Configuration
Outputs Programmed OFF
• 33879
• 33879A
μA
OUT(FLT-TH)
20
20
30
30
60
115
33879
2
NXP Semiconductors
2
Internal block diagram
VDD
VPWR
~50 μA
__
Overvoltage
Shutdown/POR
Sleep State
CS
Internal
Bias
Power Supply
Charge
Pump
SCLK
DI
GND
D1
DO
OV, POR, SLEEP
SPI and
Interface
Logic
EN
IN5
IN6
Typical of all 8 output drivers
TLIM
~110 kΩ
~50 μA
D2
D3
Drain
Open
Load
SPI Bit 0
D4 Outputs
D7
D8
Gate
Drive
Control
Detect
Enable
Current
~80 μA
Current
SPI Bit 4
IN5
Limit
+
‚
S1
S2
S3
~50 μA
+
‚
+
‚
Source
S4
S7
S8
Outputs
Open/Short
Comparator
~4.0 V Open/Short
Threshold
D5
D6
Drain
Outputs
Open
TLIM
Load
Detect
Current
~80 μA
Gate
Drive
Control
EP
Exposed Pad
Current
Limit
+
‚
S5
S6
Source
Outputs
+
‚
‚
+
~4.0 V Open/Short
Threshold
Open/Short
Comparator
Figure 2. 33879 simplified internal block diagram
33879
NXP Semiconductors
3
3
Pin connections
3.1
Pinout diagram
GND
VDD
S8
NC
D8
S2
D2
NC
NC
S1
D1
D6
S6
IN6
EN
DO
VPWR
NC
S7
D7
S4
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
D4
GND
8
NC
NC
S3
D3
D5
S5
IN5
CS
9
10
11
12
13
14
15
16
SCLK
DI
Figure 3. 33879 pin connections
3.2
Pin definitions
A functional description of each pin can be found in 5.1, Functional pin description, page 15.
Table 3. 33879 pin definitions
Pin number Pin name Pin function
Formal name
Definition
1
2
3
GND
Ground
Input
Ground
Digital ground.
V
Logic Supply Voltage Logic supply for SPI interface. With V
low the device is in Sleep mode.
DD
DD
Output
Source Output 8
Not Connected
Output 8 MOSFET source pin.
No internal connection to this pin.
S8
4, 8, 9, 24,
25, 30
No
Connection
NC
5
D8
S2
Output
Output
Output
Output
Output
Output
Output
Input
Drain Output 8
Source Output 2
Drain Output 2
Source Output 1
Drain Output 1
Drain Output 6
Source Output 6
Command Input 6
Enable Input
Output 8 MOSFET drain pin.
Output 2 MOSFET source pin.
Output 2 MOSFET drain pin.
Output 1 MOSFET source pin.
Output 1 MOSFET drain pin.
Output 6 MOSFET drain pin.
Output 6 MOSFET source pin.
6
7
D2
10
11
12
13
14
15
16
17
S1
D1
D6
S6
IN6
EN
SCLK
DI
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
IC Enable. Active high. With EN low, the device is in Sleep mode.
SPI control clock input pin.
Input
Clock
Input
SPI Clock
Serial Data Input
SPI control data input pin from MCU to the 33879. Logic [1] activates output.
SPI control chip select input pin from MCU to the 33879. Logic [0] allows data to be
transferred in.
18
CS
Input
SPI Chip Select
19
20
IN5
S5
Input
Command Input 5
Source Output 5
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output 5 MOSFET source pin.
Output
33879
4
NXP Semiconductors
Table 3. 33879 pin definitions (continued)
Pin number Pin name Pin function
Formal name
Definition
21
22
23
26
27
28
29
31
D5
D3
S3
D4
S4
D7
S7
Output
Output
Output
Output
Output
Output
Output
Input
Drain Output 5
Drain Output 3
Source Output 3
Drain Output 4
Source Output 4
Drain Output 7
Source Output 7
Battery Input
Output 5 MOSFET drain pin.
Output 3 MOSFET drain pin.
Output 3 MOSFET source pin.
Output 4 MOSFET drain pin.
Output 4 MOSFET source pin.
Output 7 MOSFET drain pin.
Output 7 MOSFET source pin.
Power supply pin to the 33879. V
V
has internal reverse battery protection.
PWR
PWR
SPI control data output pin from the 33879 to the MCU. DO=0 no fault, DO=1 specific
output has fault.
32
33
DO
EP
Output
Serial Data Output
Exposed Pad
Device performs as specified with the Exposed Pad un-terminated (floating) however,
it is recommended the exposed pad be terminated to pin 1 (GND) and system ground.
Ground
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NXP Semiconductors
5
4
Electrical characteristics
4.1
Maximum ratings
Table 4. 33879 maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
Electrical ratings
(1)
(1)
V
V
Supply Voltage
-0.3 to 7.0
-0.3 to 7.0
V
V
DD
DD
DC
DC
–
CS, DI, DO, SCLK, IN5, IN6, and EN
V
Supply Voltage
PWR
(1)
(2)
V
-16 to 40
-16 to 45
V
• 33879
• 33879A
PWR
DC
E
Output Clamp Energy
50
mJ
V
CLAMP
ESD Voltage
V
V
V
V
±450
±100
±2000
±200
• Human Body Model 33879
• Machine Model 33879
• Human Body Model 33879A
• Machine Model 33879A
ESD1
ESD2
ESD1
ESD2
(3)
Thermal ratings
Operating Temperature
• Ambient
• Junction
TA
TJ
TC
-40 to 125
-40 to 150
-40 to 125
°C
• Case
T
Storage Temperature
Power Dissipation
-55 to 150
1.7
°C
STG
(4)
P
W
D
Thermal Resistance
R
R
71
1.2
°C/W
• Junction to Ambient
• Between the Die and the Exposed Die Pad
θJA
θJC
(5), (6)
°C
TPPRT
Peak Package Reflow Temperature During Reflow
Note 6
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method with I = 350 mA.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance
with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4. Maximum power dissipation at T = 25 °C with no heatsink used.
A
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
6. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), Go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all
orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33879
6
NXP Semiconductors
4.2
Static electrical characteristics
Table 5. Static electrical characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power input
Supply Voltage Range
• Fully Operational 33879
• 33879A
V
5.5
5.5
–
–
26.5
27.5
V
PWR(FO)
I
Supply Current
–
–
14
24
mA
PWR(ON)
Sleep State Supply Current
• V or EN ≤ 0.8 V, VPWR = 13 V
I
2.0
5.0
μA
PWR(SS)
DD
Sleep State Supply Current
I
–
2.0
5.0
μA
VDD(SS)
• EN ≤ 0.8 V, VDD = 5.5 V
V
Overvoltage Shutdown Threshold Voltage
PWR
VPWR(OV)
27
28
28.5
30
32
33
V
• 33879
• 33879A
V
V
Overvoltage Shutdown Hysteresis Voltage
0.2
3.0
300
3.1
250
0.8
1.5
4.0
500
–
2.5
5.0
700
5.5
700
3.0
V
V
PWR(OV-HYS)
VPWR(UV)
PWR
PWR
PWR
V
V
Undervoltage Shutdown Threshold Voltage
Undervoltage Shutdown Hysteresis Voltage
VPWR(UV-HYS)
mV
V
V
I
Logic Supply Voltage
DD
Logic Supply Current
400
2.5
μA
V
DD
V
Logic Supply Sleep State Threshold Voltage
DD(SS)
Power output
Drain-to-Source ON Resistance (I
= 0.350 A, V
= 13 V)
OUT
PWR
• T = 125°C
–
–
–
–
0.75
–
1.4
–
–
J
R
Ω
DS(on)
T = 25°C
J
T = -40°C
J
I
Output Self Limiting Current High-side and Low-side Configurations
0.6
–
1.2
A
V
OUT(LIM)
Output Fault Detection Voltage Threshold Outputs Programmed OFF
(7)
V
I
2.5
2.5
4.0
4.0
4.5
5.0
• 33879
• 33879A
OUT(FLT-TH)
Output Fault Detection Current @ Threshold, High-side Configuration
Outputs Programmed OFF
μA
μA
OUT(FLT-TH)
OUT(FLT-TH)
35
35
55
55
90
150
• 33879
• 33879A
Output Fault Detection Current @ Threshold, Low-side Configuration
Outputs Programmed OFF
I
20
20
30
30
60
115
• 33879
• 33879A
Output OFF Open Load Detection Current, High-side Configuration
• V
= 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
DRAIN
VPWR = 16 V
33879
33879A
I
μA
OCO
65
60
100
100
160
190
Notes
7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.
33879
NXP Semiconductors
7
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power output (continued)
Output OFF Open Load Detection Current, Low-side Configuration
V
V
= 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
PWR =16 V
DRAIN
I
μA
OCO
40
40
75
75
135
150
• 33879
• 33879A
Output Clamp Voltage Low-side Drive
V
40
-15
–
45
-20
–
55
-25
5.0
V
V
OC(LSD)
• I = 10 mA
D
Output Clamp Voltage High-side Drive
V
I
OC(HSD)
• I = -10 mA
S
Output Leakage Current High-side and Low-side Configurations
μA
OUT(LKG)
• V
= 0 V, V
= 16 V, V
= 0 V
SOURCE
DD
DRAIN
Output Leakage Current Low-side Configuration
• V = 5.0 V, V = 16 V, V = 0 V, Open Load Detection
I
I
μA
μA
OUT(LKG)
DD
DRAIN
SOURCE
–
–
–
–
5.0
20
Current Disabled
Output Leakage Current High-side Configuration
• V = 5.0 V, V = 16 V, V = 0 V, Open Load Detection
OUT(LKG)
DD
DRAIN
SOURCE
Current Disabled
(8)
(8)
T
Overtemperature Shutdown
155
5.0
–
185
15
°C
°C
LIM
T
Overtemperature Shutdown Hysteresis
10
LIM(HYS)
Digital interface
(9)
(9)
V
Input Logic High-voltage Thresholds
Input Logic Low-voltage Thresholds
0.7 VDD
–
–
VDD + 0.3
0.2 VDD
V
V
IH
V
GND -0.3
IL
IN5, IN6, EN Input Logic Current
• IN5, IN6, EN = 0 V
I
I
I
-10
30
–
10
μA
μA
IN5, IN6, EN
IN5, IN6 Pull-down Current
I
I
45
100
IN5, IN6,
• 0.8 to
5.0 V
EN Pull-down Current, EN = 5.0 V
I
20
20
45
45
100
110
μA
• 33879
• 33879A
EN
SCLK, DI Input, Tri-state DO Output
• 0 to 5.0 V
I
I
I
-10
-10
-30
–
–
–
–
–
–
10
10
μA
μA
μA
μA
V
SCK, DI, TRI-DO
CS Input Current
• CS = VDD
I
CS
CS Pull-up Current
• CS = 0 V
I
-100
10
CS
CS Leakage Current to VDD
I
CS(LKG)
• CS = 5.0 V, V
= 0 V
DD
DO High State Output Voltage
• I = -1.6 mA
V
V
-0.4
VDD
DOHIGH
DD
DO-HIGH
Notes
8. This parameter is guaranteed by design; however, it is not production tested.
9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
33879
8
NXP Semiconductors
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
digital interface (continued)
DO Low State Output Voltage
• I = 1.6 mA
V
–
–
–
–
0.4
20
V
DOLOW
DO-LOW
(10)
C
Input Capacitance on SCLK, DI, Tri-state DO, IN5, IN6, EN
pF
IN
Notes
10. This parameter is guaranteed by design; however, it is not production tested.
33879
NXP Semiconductors
9
4.3
Dynamic electrical characteristics
Table 6. Dynamic electrical characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power output timing
Output Slew Rate Low-side Configuration
• R = 620Ω, CL = 200pF
(11)
(11)
(11)
(11)
tSR(RISE)
tSR(FALL)
tSR(RISE)
tSR(FALL)
0.1
0.1
0.1
0.1
0.5
0.5
0.3
0.3
1.0
1.0
1.0
1.0
V/μs
V/μs
V/μs
V/μs
LOAD
Output Slew Rate Low-side Configuration
• R = 620 Ω, CL = 200 pF
LOAD
Output Rise Time High-side Configuration
• R = 620 Ω, CL = 200 pF
LOAD
Output Fall Time High-side Configuration
• R = 620 Ω, CL = 200 pF
LOAD
(12)
(12)
(13)
tDLY(ON)
tDLY(OFF)
tFAULT
Output Turn ON Delay Time, High-side and Low-side Configuration
Output Turn OFF Delay Time, High-side and Low-side Configuration
Output Fault Delay Time
1.0
1.0
15
30
–
50
μs
μs
μs
100
300
100
Power-ON Reset Delay
t
100
100
–
–
–
–
μs
POR
• Delay Time Required from Rising Edge of EN and V
to SPI Active
DD
Low-State Duration on V
or EN for Reset
DD
t
µs
RESET
• V
or EN ≤ 0.2 V
DD
Digital interface timing(14)
(14)
fSPI
Recommended Frequency of SPI Operation
–
100
50
16
20
–
4.0
–
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
DI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time
LEAD
t
–
–
LAG
t
–
–
DI(SU)
t
–
–
DI(HOLD)
(15)
(15)
(16)
(17)
(18)
t
t
5.0
5.0
–
–
R(DI)
F(DI)
DI, CS, SCLK Signal Fall Time
–
–
t
Time from Falling Edge of CS to DO Low-impedance
Time from Rising Edge of CS to DO High-impedance
Time from Rising Edge of SCLK to DO Data Valid
–
55
55
55
DO(EN)
t
–
–
DO(DIS)
t
–
25
VALID
Notes
11. Output slew rate respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
CL capacitor is connected from Drain or Source output to Ground.
12. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points.
13. Duration of fault before fault bit is set. Duration between access times must be greater than 300 μs to read faults.
14. This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output status data to be available for use at DO pin.
17. Time required for output status data to be terminated at DO pin.
18. Time required to obtain valid data out from DO following the rise of SCLK.
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10
NXP Semiconductors
4.4
Timing diagrams
CS
0.2 V
DD
t
t
LAG
LEAD
0.7 V
0.2 V
DD
DD
SCLK
t
t
DI(SU) DI(HOLD)
0.7 V
0.2 V
DD
DD
DI
MSB in
t
t
DO(DIS)
DO(EN)
t
VALID
0.7 V
0.2 V
DD
DD
DO
MSB out
LSB out
Figure 4. SPI timing diagram
V
= 5.0 V
DD
33879
Under
Test
DO
C = 200 pF
SCLK
L
NOTE: C represents the total capacitance of the test
L
fixture and probe.
Figure 5. Valid data delay time and valid time test circuit
t
< 50 ns
50%
< 50 ns
3.3/5.0 V
t
F(DI
R(DI)
0.7 V
DD
0.2 V
SCLK
DD
0 V
V
OH
0.7 V
DD
DO
0.2 V
0.7 V
DD
V
V
OL
t
(Low-to-High)
DO
R(DO
t
VALID
0.2
OH
(High-to-Low)
DD
V
OL
Figure 6. Valid data delay time and valid time waveforms
33879
NXP Semiconductors
11
t
t
F(CS)
R(CS)
<50 ns
90%
<50 ns
0.7 V
3.3/5.0 V
0 V
CS
DO
DD
0.2 V
10%
DD
t
t
DO(EN)
DO(DIS)
V
Tri-State
90%
(Tri-StatetoLow)
10%
V
OL
t
t
DO(EN)
DO(DIS)
V
V
OH
90%
Tri-State
DO
10%
(Tri-State to High)
Figure 7. Enable and disable time waveforms
4.5
Typical electrical characteristics
20
19
18
17
16
15
14
V
@ 18 V
PWR
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-40 -25
0
25
50
75
100 125
TA, Ambient Temperature (ℜ°C
Figure 8. IPWR vs. temperature
7
V
@ 13 V
PWR
6
5
4
3
2
1
-40 -25
0
25
A, Ambient Temperature (ℜ°C
Figure 9. Sleep state IPWR vs. temperature
50
75
100 125
T
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140
120
100
80
T
= 25ℜ°
A
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60
40
20
33879A
0
5
10
VPWR
15
20
25
Figure 10. Sleep state IPWR vs. VPWR
1.4
1.2
1.0
0.8
0.6
0.4
V
@ 13 V
PWR
High-side Drive
-40 -25
0
25
50
75
100 125
T
A, Ambient Temperature (ℜ°C
Figure 11. RDS(ON) vs. temperature at 350 mA
1.4
1.2
1.0
0.8
0.6
0.4
0.2
T
= 25ℜ°
A
High-side Drive
0
5
10
VPWR (V)
Figure 12. RDS(ON) vs. VPWR at 350 mA
15
20
25
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13
140
120
100
80
V
@ 13 V
PWR
60
High-side
Low-side
40
20
-40 -25
0
25
50
75
100 125
TA, Ambient Temperature (ℜ°C
Figure 13. Open load detection current at threshold
5.5
V
@ 13 V
PWR
High-side and Low-side
5.0
4.5
4.0
3.5
3.0
2.5
-40 -25
0
25
A, Ambient Temperature (ℜ°C
Figure 14. Open load detection threshold vs. temperature
50
75
100 125
T
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5
Functional description
5.1
Functional pin description
5.1.1 CS pin
The system MCU selects the 33879 with which to communicate through the use of the chip select CS pin. Logic low on CS enables the
data output (DO) driver and allows data to be transferred from the MCU to the 33879 and vice versa. Data clocked into the 33879 is acted
upon on the rising edge of CS. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when the
SPI clock (SCLK) is in a logic low state.
5.1.2 SCLK pin
The SCLK pin clocks the internal shift registers of the 33879. The serial data input (DI) pin is latched into the input shift register on the
falling edge of the SCLK. The serial data output (DO) pin shifts data out of the shift register on the rising edge of the SCLK signal. False
clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK pin be in a logic low state when the CS pin
makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed
(CS in logic high state). With CS in a logic high state, signals present on SCLK and DI are ignored and the DO output is in tri-state.
5.1.3 DI pin
The DI pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high
state present on DI programs a specific output on. The specific output turns on with the rising edge of the CS signal. Conversely, a logic
low state present on the DI pin programs the output off. The specific output turns off with the rising edge of the CS signal. To program the
eight outputs and open load detection current on or off, send the DI data beginning with the open load detection current bits, followed by
output eight, output seven, and so on to output one. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or
off) is loaded into the shift register per the data bit DI state. Sixteen bits of entered information is required to fill the input shift register.
5.1.4 DO pin
The DO pin is the output from the shift register. The DO pin remains tri-state until the CS pin is in a logic low state. All faults on the 33879
device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are
reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. Outputs programmed with
open load detection current disabled report logic [0] in the off state. The first eight positive transitions of SCLK report logic [0] followed by
the status of the eight output drivers. The DI/DO shifting of data follows a first-in, first-out protocol with both input and output words
transferring the most significant bit (MSB) first.
5.1.5 EN pin
The EN pin on the 33879 enables the device. With the EN pin high, output drivers may be activated and open/short fault detection
performed and reported. With the EN pin low, all outputs become inactive, open load detection current is disabled, and the device enters
Sleep mode. The 33879 performs Power-ON Reset on the rising edge of the enable signal.
5.1.6 IN5 and IN6 pins
The IN5 and IN6 command inputs allow outputs five and six to be used in PWM applications. The IN5 and IN6 pins are OR-ed with the
serial peripheral interface (SPI) command input bits. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or
held low by the microprocessor. When using IN5 or IN6 to PWM the output, the control SPI bit must be logic [0]. Maximum PWM frequency
for each output is 2.0 kHz.
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5.1.7 VDD pin
The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive the DO
output and the pull-up current for CS. VDD must be applied for normal mode operation. The 33879 device performs Power-ON Reset with
the application of VDD.
5.1.8 VPWR pin
The VPWR pin is the battery input and Power-ON Reset to the 33879 IC. The VPWR pin has internal reverse battery protection. All internal
logic current is provided from the VPWR pin. The 33879 performs Power-ON Reset with the application of VPWR.
5.1.9 D1–D8 pins
The D1 to D8 pins are the open-drain outputs of the 33879. For high-side drive configurations, the drain pins are connected to battery
supply. In low-side drive configurations, the drain pins are connected to the low-side of the load. All outputs may be configured individually
as desired. When configured as low-side drive, the 33879 limits the positive inductive transient to 45 V.
5.1.10 S1–S8 pins
The S1 to S8 pins are the source outputs of the 33879. The source pins are connected directly to the load for high-side drive
configurations. In low-side drive configurations, the source is connected to ground. All outputs may be configured individually as desired.
When high-side drive is used, the 33879 will limit the negative inductive transient to negative 20 V.
5.1.11 Exposed Pad pin
Device performs as specified with the Exposed Pad un-terminated (floating) however, it is recommended the Exposed Pad be terminated
to pin 1 (GND) and system ground.
5.2
MCU interface description
5.2.1 Introduction
The 33879 is an eight output hardware-configurable power switch with 16-bit serial control. A simplified internal block diagram of the 33879
is shown in Figure 2. The 33879 device uses high-efficiency up-drain power DMOS output transistors exhibiting low drain-to-source ON
resistance (RDS(on) = 0.75 Ω at 25 °C typical) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast
inductive turn-off and transient protection.
In operation, the 33879 functions as an eight output serial switch, serving as an MCU bus expander and buffer with fault management
and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. This device directly
interfaces to an MCU using a SPI for control and diagnostic readout. Figure 15 illustrates the basic SPI configuration between an MCU
and one 33879.
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MC68HCxx
Microcontroller
33879
DI
MOSI
MISO
Shift Register
16 Bits
Shift Register
16 Bits
DO
SCLK
CS
Receive
Buffer
To
Logic
Parallel
Ports
Figure 15. SPI interface with microcontroller
All inputs are compatible with 5.0 V and 3.3 V CMOS logic levels and incorporate positive logic. When a SPI bit is programmed to a
logic [0], the corresponding output is OFF. Conversely, when a SPI bit is programmed to logic [1] the output being controlled is ON.
Diagnostics are treated in a similar manner. Outputs with a fault feed back (via DO) a logic [1] to the microcontroller, while normal
operating outputs provide a logic [0].
Figure 16 illustrates the daisy chain configuration using the 33879. Data from the MCU is clocked daisy chain through each device while
the CS bit is commanded low by the MCU. During each clock cycle, output status from the daisy chain is transferred to the MCU via the
Master In Slave Out (MISO) line. On rising edge of CS, command data stored in the input register is then transferred to the output driver.
SCLK
Parallel Port
33879
CS
33879
33879
CS SCLK
CS SCLK
MC68HCxx
Microcontroller
with
MISO
DO
DI
DO
DI
DO
DI
SPI Interface
8 Outputs
8 Outputs
8 Outputs
MOSI
Figure 16. 33879 SPI system daisy chain
Multiple 33879 devices can be controlled in a parallel input fashion using the SPI. Figure 17 illustrates the control of 24 loads using three
dedicated parallel MCU ports for chip select.
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33879
MOSI
SCLK
DI
SCLK
DO
MISO
8 Outputs
CS
MC68HCxx
Microcontroller
with
33879
SPI Interface
DI
SCLK
DO
8 Outputs
8 Outputs
CS
33879
DI
A
Parallel
Ports
SCLK
DO
B
C
CS
Figure 17. Parallel input SPI control
5.3
SPI definition
A 16-bit command word is sent to the 33879 on each SPI communication and a 16-bit status word is received from the 33879. The MSB
is sent and received first. As Table 7 shows, the Command Register defines the position and operation the 33879 performs on the rising
edge of CS. The Fault Register, shown in Table 8, defines the previous state status of the output driver. Table 9 identifies the type of fault
and the method by which the fault is communicated to the microprocessor
Table 7. Command register definition
MSB
LSB
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ON/
OFF
Open
Load
ON/
OFF
Open
Load
ON/
OFF
Open
Load
ON/
OFF
Open
Load
ON/
OFF
Open
Load
ON/
OFF
Open
Load
ON/
OFF
Open
Load
ON/
OFF
Open
Load
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
Detect Detect Detect Detect Detect Detect Detect Detect
8
7
6
5
4
3
2
1
0 = Bits 0 to 7, Output commanded OFF.
0 = Bits 8 to 15, Open Load Detection Current OFF.
1 = Bits 0 to 7, Output commanded ON.
1 = Bits 8 to 15 Open Load Detection Current ON.
Table 8. Fault register definition
MSB
LSB
Bit 15 Bit 14 Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
Status Status Status Status Status Status Status Status
0
0
0
0
0
0
0
0
0 = Bits 0 to 7, No Fault at Output.
1 = Bits 0 to 7, Output Short-to-Battery, Short-to-GND, Open Load, or TLIM
.
Bits 8 to 15 will always return “0”.
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Table 9. Fault operation
Serial output (DO) pin reports
Overtemperature
Fault reported by serial output (DO) pin.
DO pin reports short to battery/supply or overcurrent condition.
Not reported.
Overcurrent
Output ON Open Load Fault
DO pin reports output OFF open load condition only with Open Load Detection Current enabled.
DO pin will report “0” for Output OFF Open Load Fault with Open Load Detection Current disabled.
Output OFF Open Load Fault
Device shutdowns
Total device shutdown at V
the previous state upon recovery from overvoltage.
= VPWR(OV) V. Resumes normal operation with proper voltage. All outputs assuming
PWR
Overvoltage
Only the output experiencing an overtemperature shuts down. Output assumes previous state upon recovery from
overtemperature.
Overtemperature
5.4
Device operation
5.4.1 Power supply
The 33879 device has been designed with ultra-low Sleep mode currents. The device may enter Sleep mode via the EN pin or the VDD
pin. In the Sleep mode (EN or VDD ≤ 0.8 V), the current consumed by the VPWR pin is less than 5.0 μA. Placing the 33879 in Sleep mode
resets the internal registers to the Power-ON Reset state. The reset state is defined as all outputs off and open load detection current
disabled. To place the 33879 in the Sleep mode, either command all outputs off and apply logic low to the EN input pin or remove power
from the VDD supply pin. Prior to removing VDD from the device, it is recommended that all control inputs from the MCU be low.
5.4.2 Paralleling of outputs
Using MOSFETs as an output switch conveniently allows the paralleling of outputs for increased current capability. RDS(on) of MOSFETs
have an inherent positive temperature coefficient providing balanced current sharing between outputs without destructive operation. This
mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching
higher currents. Performance of parallel operation results in a corresponding decrease in RDS(on), while the output OFF open load
detection currents and the output current limits increase correspondingly. Paralleling outputs from two or more different IC devices is
possible, but not recommended.
5.4.3 Fault logic operation
Fault logic of the 33879 device has been greatly simplified over other devices using SPI communications. As command word one is being
written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the
configuration, with no outputs faulted and open load detection current enabled, all status bits being received by the MCU are zero. When
outputs are faulted (off state open circuit or on state short-circuit/overtemperature), the status bits being received by the MCU are one.
The distinction between open circuit fault and short/overtemperature is completed via the command word. For example, when a zero
command bit is sent and a one fault is received in the following word, the fault is open/short-to-battery for high-side drive or open/short-
to-ground for low-side drive. In the same manner, when a one command bit is sent and a one fault is received in the following word, the
fault is a short-to-ground/overtemperature for high-side drive or short-to-battery/overtemperature for low-side drive. The timing between
two write words must be greater than 300 μs to allow adequate time to sense and report the proper fault status.
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5.4.4 SPI integrity check
Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system
start-up or reset, the MCU writes one 32-bit pattern to the 33879. The first 16 bits read by the MCU are 8 logic [0]s followed by the fault
status of the outputs. The second 16 bits are the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent,
bus integrity is confirmed. Note the second 16-bit pattern the MCU sends to the device is the command word and is transferred to the
outputs with rising edge of CS. Important: A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications.
SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter are acknowledged. SPI messages consisting of
other than 16 + multiples of 8 SCLK pulses are ignored by the device.
5.4.5 Overtemperature fault
Overtemperature detection and shutdown circuits are specifically incorporated for each individual output. The shutdown following an
overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155 °C
to 185 °C. When an output shuts down owing to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault
by a one in the fault status register. After the 33879 device has cooled below the switch point temperature and 15 °C hysteresis, the output
activates unless otherwise told to shut down by the MCU via the SPI.
5.4.6 Overvoltage fault
An overvoltage condition on the VPWR pin causes the device to shut down all outputs until the overvoltage condition is removed. When
the overvoltage condition is removed, the outputs resume their previous state. This device does not detect an overvoltage on the VDD
pin. The overvoltage threshold on the VPWR pin is specified as VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR overvoltage detection
is global, causing all outputs to be turned OFF.
5.4.7 Output off open load fault
An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit
programmed to a logic low state). The Output OFF Open Load fault is detected by comparing the drain-to-source voltage of the specific
MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. An output OFF open
load fault is indicated when the drain-to-source voltage is less than the output threshold voltage (VOUT(FLT-TH)) of 2.5 V to 4.0 V. Hence,
the 33879 declares the load open in the OFF state when the output drain-to-source voltage is less than VOUT(FLT-TH)
.
This device has an internal 80 μA current source connected from drain to source of the output MOSFET. The current source may be
programmed on or off via the SPI. The Power-ON Reset state for the current source is “off” and must be enabled via the SPI. To achieve
low Sleep mode quiescent currents, the open load detection current source of each driver is switched off when VDD or EN is removed.
During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault
from being reported, an internal fault filter of 100 μs to 300 μs is incorporated. A false fault reporting is a function of the load impedance,
RDS(on), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer
times out before the fault comparator is enabled and the fault is detected. Once the condition causing the open load fault is removed, the
device resumes normal operation. The open load fault, however, is latched in the output DO register for the MCU to read.
5.4.8 Shorted load fault
A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater
than the current limit. There are two safety circuits progressively in operation during load short conditions providing system protection:
1. The device’s output current is monitored in an analog fashion using SENSEFET approach and current limited.
2. The device’s output thermal limit is sensed and when attained causes only the specific faulted output to shutdown. The output
remains off until cooled. The device then reasserts the output automatically. The cycle continues until fault is removed or the
command bit instructs the output off. Shorted load faults are reported properly through the SPI regardless of open load detection
current enable bits.
5.4.9 Undervoltage shutdown
An undervoltage condition on VDD or VPWR results in the shutdown of all outputs. The VDD undervoltage threshold is between 0.8 and
3.0 V. VPWR undervoltage threshold is between 3.0 V and 5.0 V. When the supplies fall below their respective thresholds, all outputs are
turned OFF. As both supplies returns to normal levels, internal logic is reset and the device resumes normal operation.
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5.4.10 Output voltage clamp
Each output of the 33879 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. Each
clamp independently limits the drain-to-source voltage to 45 V for low-side drive configurations and -20 V for high-side drive
configurations. The total energy clamped (EJ) can be calculated by multiplying the current area under the current curve (IA) times the
clamp voltage (VCL) (see Figure 18). Characterization of the output clamps, using a single pulse non-repetitive method at 0.35 A, indicates
the maximum energy per output to be 50 mJ at 150°C junction temperature.
Drain-to-Source Clamp
Voltage (VCL = 45 V)
Drain Voltage
Drain Current
(ID = 0.3 A)
Clamp Energy
(E = I x V
)
CL
J
A
Drain-to-Source ON
Voltage (VDS(ON))
Current
Area (I
)
A
GND
Time
BAT
Time
Drain-to-Source ON
Voltage (VDS(ON))
VS
GND
Current
Area (I )
A
Clamp Energy
(E = I x V )
CL
J
A
Source Current
(IS = 0.3 A)
Source Clamp Voltage
Source Voltage
(V
= -15 V)
CL
Figure 18. Output Voltage Clamping
5.4.11 SPI configurations
The SPI configuration on the 33879 device is consistent with other devices in the Octal Serial Switch (OSS) family. This device may be
used in serial SPI or parallel SPI with the 33298 and 33291. Different SPI configurations may be provided. For more information, contact
NXP Analog Products Division or the local NXP representative.
5.4.12 Reverse battery
The 33879 has been designed with reverse battery protection on the VPWR pin. All outputs consist of a power MOSFET with an integral
substrate diode. During the reverse battery condition, current flows through the load via the substrate diode. Under this circumstance,
relays may energize and lamps turn on. Where load reverse battery protection is desired, a reverse battery blocking diode must be placed
in series with the load.
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21
6
Package dimensions
Important: For the most current revision of the package, visit www.nxp.com and perform a keyword search using the “98ARL10543D”
drawing number listed below. Dimensions shown are provided for reference ONLY.
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7
Revision history
Revision
Date
Description of changes
• Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the internal block diagram.
• Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin definition.
• Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed. The VDD Supply contains
no hysteresis.
• Page 7, Table 3; Output Fault Detection Current @ Threshold, High-Side Configuration Max parameter has been
increased from 70uA to 90uA.
• Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration has been updated to reflect
the voltage of the VPWR pin during the parameter test.
5.0
2/2006
• Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has been updated to reflect the
voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max parameter has been
decreased from 7uA to 5uA.
• Page 15, Functional Pin Description; A description has been added for the Exposed Pad pin.
• Page 1, Device isometric; Corrected orientation of IC pin 1 from top left to bottom right.
• ALL Pages; Updated Data Sheet to reflect Freescale formatting.
• Added 33879A version
• Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information
• Added Device variations on page 2
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Rations on
page 6. Added note with instructions from www.freescale.com.
6.0
6/2007
• Changed Output Fault Detection Voltage Threshold Outputs Programmed OFF on page 7
• Renumbered X axis on Figure 14 - Open load detection threshold vs. temperature on page 14
• Changed Overvoltage on page 19 and Overvoltage fault on page 20
7.0
8.0
8/2008
• Updated package drawing.
• Updated data sheet status from Advance Information to Technical Data
• Updated to the current Freescale form and style
10/2009
• Removed MC33879EK from the ordering information
• Removed MCZ33879AEK and added MC33879APEK to the ordering information
• Removed MCZ33879EK and added MC33879TEK to the ordering information
• Updated Output Fault Detection Current @ Threshold, High-side Configuration Outputs Programmed OFF on page 7
• Updated Output OFF Open Load Detection Current, High-side Configuration on page 7
• Updated Output OFF Open Load Detection Current, Low-side Configuration on page 8
• Updated EN Pull-down Current, EN = 5.0 V on page 8
9.0
5/2012
• Updated the Freescale form and style
• Updated Output Fault Detection Voltage Threshold Outputs Programmed OFF on page 7
• Updated Output Fault Detection Current @ Threshold, Low-side Configuration Outputs Programmed OFF on page 7
• Updated the max limit for Output Fault Detection Current @ Threshold, High-side Configuration Outputs
Programmed OFF on page 7
6/2012
10.0
11.0
4/2013
11/2015
7/2016
• No technical changes. Revised back page. Updated document properties.
• Changed feature on page 1 to Designed to operate 5.5 V < VPWR < 27.5 V
• Updated Freescale form and style.
•
Updated to NXP document form and style
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NXP Semiconductors
25
Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to any
products herein.
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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,
and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
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NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or
service names are the property of their respective owners. All rights reserved.
© 2016 NXP B.V.
Document Number: MC33879
Rev. 11.0
7/2016
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