MC33879TEK-R2 [NXP]
BUF OR INV BASED PRPHL DRVR;
| 型号： | MC33879TEK-R2 |
| 厂家： | 
NXP |
| 描述： | BUF OR INV BASED PRPHL DRVR 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总23页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33879
Rev. 9.0, 5/2012
Freescale Semiconductor
Technical Data
Configurable Octal Serial Switch
with Open Load Detect Current
Disable
33879
33879A
The 33879 device is an 8-output hardware configurable, high side/
low side switch with 16-bit serial input control using the serial peripheral
interface (SPI). Two of the outputs may be controlled directly via a
microcontroller for pulse-width modulation (PWM) applications. The
33879 incorporates SMARTMOS technology, with CMOS logic,
bipolar/MOS analog circuitry, and DMOS power MOSFETs. The 33879
controls various inductive, incandescent, or LED loads by directly
interfacing with a microcontroller. The circuit’s innovative monitoring
and protection features include very low standby currents, cascade
fault reporting, internal +45 V clamp voltage for low side configuration,
-20 V high side configuration, output specific diagnostics, and
independent over-temperature protection.
HIGH SIDE/ LOW SIDE SWITCH
EK SUFFIX (PB-FREE)
98ARL10543D
Features
32-PIN SOICW
• Designed to operate 5.5 V < VPWR < 26.5 V
• 16-bit SPI for control and fault reporting, 3.3 V/5.0 V compatible
• Outputs are current limited (0.6 A to 1.2 A) to drive incandescent
lamps
• Output voltage clamp, +45 V (low side) and -20 V (high side)
during inductive switching
• On/Off control of open load detect current (LED application)
• Internal reverse battery protection on VPWR
• Loss of ground or supply will not energize loads or damage IC
• Maximum 5.0 μA IPWR standby current at 13 V VPWR
• RDS(ON) of 0.75 Ω at 25 °C typical
ORDERING INFORMATION
Temperature
Device
(For Tape and Reel,
add an R2 Suffix)
Package
Range (T )
A
MC33879APEK
MC33879TEK
-40°C to 125°C
32 SOICW-EP
• Short-circuit detect and current limit with automatic retry
• Independent over-temperature protection
V
V
PWR
BAT
5.0 V
33879
VPWR
D1
D2
D3
D4
S1
S2
VDD
High Side Drive
MCU
A0
EN
S3
S4
MOSI
SCLK
CS
DI
H-Bridge Configuration
M
SCLK
V
V
D5
BAT
BAT
CS
D0
D6
D7
D8
S5
S6
S7
S8
MISO
PWM1
PWM2
IN5
Low Side Drive
IN6
GND
Figure 1. 33879 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Characteristic
VPWR Supply Voltage
Symbol
Min
Typ
Max
Unit
VPWR
V
33879
-16
-16
–
40
45
33879A
Output Fault Detection Current @ Threshold, High Side
Configuration
I
μA
μA
OUT(FLT-TH)
Outputs Programmed OFF
33879
35
35
55
55
90
33879A
100
Output OFF Open Load Detection Current, High Side
Configuration
I
OCO
VDRAIN = 16 V, VSOURCE = 0 V, Outputs
Programmed OFF,
VPWR = 16 V
65
60
100
100
160
190
33879
33879A
Output OFF Open Load Detection Current, Low Side
Configuration
I
μA
OCO
VDRAIN = 16 V, VSOURCE = 0 V, Outputs
Programmed OFF,
VPWR =16 V
40
40
75
75
135
150
333879
338979A
EN Pull-down Current
EN = 5.0 V
333879
I
μA
EN
20
20
45
45
100
110
33879A
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
~50 μA
__
Over-voltage
Shutdown/POR
Sleep State
CS
Internal
Charge
Bias
Pump
SCLK
DI
Power Supply
GND
D1
DO
OV, POR, SLEEP
SPI and
Interface
Logic
EN
IN5
IN6
Typical of all 8 output drivers
TLIM
~110 kΩ
~50 μA
D2
D3
Drain
Open
Load
SPI Bit 0
D4 Outputs
D7
D8
Gate
Drive
Control
Detect
Enable
Current
~80 μA
Current
SPI Bit 4
IN5
Limit
+
‚
S1
S2
S3
S4
S7
S8
~50 μA
+
‚
+
‚
Source
Outputs
Open/Short
Comparator
~4.0 V Open/Short
Threshold
D5
D6
Drain
Outputs
Open
TLIM
Load
Detect
Current
~80 μA
Gate
Drive
Control
EP
Exposed Pad
Current
Limit
+
‚
S5
S6
Source
Outputs
+
‚
‚
+
~4.0 V Open/Short
Threshold
Open/Short
Comparator
Figure 2. 33879 Simplified Internal Block Diagram
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
GND
VDD
S8
NC
D8
S2
D2
NC
NC
S1
D1
D6
S6
IN6
EN
DO
VPWR
NC
S7
D7
S4
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
D4
GND
8
NC
NC
S3
D3
D5
S5
IN5
CS
9
10
11
12
13
14
15
16
SCLK
DI
Figure 3. 33879 Pin Connections
Table 2. 33879 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.
Pin
Pin Number Pin Name
Formal Name
Definition
Function
Ground
Input
Digital ground.
1
2
GND
VDD
Ground
Logic supply for SPI interface. With V
mode.
low the device will be in Sleep
Logic Supply
Voltage
DD
Output 8 MOSFET source pin.
No internal connection to this pin.
3
S8
Output
Source Output 8
Not Connected
4, 8, 9,
NC
No
24, 25, 30
Connection
Output 8 MOSFET drain pin.
Output 2 MOSFET source pin.
Output 2 MOSFET drain pin.
Output 1 MOSFET source pin.
Output 1 MOSFET drain pin.
Output 6 MOSFET drain pin.
Output 6 MOSFET source pin.
5
D8
S2
Output
Output
Output
Output
Output
Output
Output
Input
Drain Output 8
Source Output 2
Drain Output 2
Source Output 1
Drain Output 1
Drain Output 6
Source Output 6
Command Input 6
Enable Input
6
7
D2
10
11
12
13
14
15
16
17
18
S1
D1
D6
S6
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
IC Enable. Active high. With EN low, the device is in Sleep mode.
SPI control clock input pin.
IN6
EN
SCLK
DI
Input
Clock
Input
SPI Clock
SPI control data input pin from MCU to the 33879. Logic [1] activates output.
Serial Data Input
SPI Chip Select
SPI control chip select input pin from MCU to the 33879. Logic [0] allows
data to be transferred in.
CS
Input
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output 5 MOSFET source pin.
19
20
IN5
S5
Input
Command Input 5
Source Output 5
Output
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
PIN CONNECTIONS
Table 2. 33879 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.
Pin
Pin Number Pin Name
Formal Name
Definition
Function
Output
Output
Output
Output
Output
Output
Output
Input
Output 5 MOSFET drain pin.
Output 3 MOSFET drain pin.
Output 3 MOSFET source pin.
Output 4 MOSFET drain pin.
Output 4 MOSFET source pin.
Output 7 MOSFET drain pin.
Output 7 MOSFET source pin.
21
22
23
26
27
28
29
31
D5
D3
Drain Output 5
Drain Output 3
Source Output 3
Drain Output 4
Source Output 4
Drain Output 7
Source Output 7
Battery Input
S3
D4
S4
D7
S7
Power supply pin to the 33879. VPWR has internal reverse battery
protection.
VPWR
SPI control data output pin from the 33879 to the MCU. DO=0 no fault,
DO=1 specific output has fault.
32
33
DO
EP
Output
Serial Data Output
Exposed Pad
Device will perform as specified with the Exposed Pad un-terminated
(floating) however, it is recommended that the Exposed Pad be terminated
to pin 1 (GND) and system ground.
Ground
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. 33879 Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage(1)
V
V
-0.3 to 7.0
-0.3 to 7.0
V
DD
DD
DC
CS, DI, DO, SCLK, IN5, IN6, and EN(1)
Supply Voltage(1)
–
V
V
DC
DC
V
V
PWR
PWR
33879
-16 to 40
-16 to 45
33879A
Output Clamp Energy(2)
ESD Voltage(3)
E
50
mJ
V
CLAMP
Human Body Model 33879
Machine Model 33879
V
±450
±100
±2000
±200
ESD1
ESD2
ESD1
ESD2
V
Human Body Model 33879A
Machine Model 33879A
V
V
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
-40 to 125
Junction
TC
Case
Storage Temperature
Power Dissipation(4)
T
-55 to 150
1.7
°C
W
STG
P
D
Thermal Resistance
°C/W
R
71
Junction to Ambient
θJA
R
1.2
Between the Die and the Exposed Die Pad
θJC
Peak Package Reflow Temperature During Reflow (5), (6)
°C
TPPRT
Note 6
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method with I = 350 mA.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4. Maximum power dissipation at T = 25°C with no heatsink used.
A
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage Range
V
V
PWR(FO)
Fully Operational 33879
33879A
5.5
5.5
–
–
26.5
27.5
Supply Current
I
–
14
24
mA
PWR(ON)
Sleep State Supply Current
I
μA
PWR(SS)
V
or EN ≤ 0.8 V, VPWR = 13 V
–
2.0
5.0
DD
Sleep State Supply Current
I
μA
VDD(SS)
EN ≤ 0.8 V, VDD = 5.5 V
–
2.0
5.0
V
Over-voltage Shutdown Threshold Voltage
VPWR(OV)
V
PWR
33879
27
28
28.5
30
32
33
33879A
V
V
V
Over-voltage Shutdown Hysteresis Voltage
Under-voltage Shutdown Threshold Voltage
Under-voltage Shutdown Hysteresis Voltage
V
0.2
3.0
300
3.1
250
0.8
1.5
4.0
500
–
2.5
5.0
700
5.5
700
3.0
V
V
PWR
PWR
PWR
PWR(OV-HYS)
VPWR(UV)
VPWR(UV-HYS)
mV
V
Logic Supply Voltage
V
DD
DD
Logic Supply Current
I
400
2.5
μA
V
Logic Supply Sleep State Threshold Voltage
V
DD(SS)
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT
Drain-to-Source ON Resistance (I
= 0.350 A, V
= 13 V)
PWR
R
Ω
OUT
DS(ON)
–
–
–
–
0.75
–
1.4
–
T = 125°C
J
T = 25°C
J
T = -40°C
–
J
Output Self Limiting Current High Side and Low Side Configurations
I
0.6
2.5
–
1.2
4.5
A
V
OUT(LIM)
Output Fault Detection Voltage Threshold(7)
Outputs Programmed OFF
V
OUT(FLT-TH)
4.0
Output Fault Detection Current @ Threshold, High Side Configuration
Outputs Programmed OFF
I
μA
OUT(FLT-TH)
33879
33879A
35
35
55
55
90
100
Output Fault Detection Current @ Threshold, Low Side Configuration
I
μA
μA
OUT(FLT-TH)
Outputs Programmed OFF
20
30
60
Output OFF Open Load Detection Current, High Side Configuration
I
I
OCO
V
= 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
DRAIN
VPWR = 16 V
33879
65
60
100
100
160
190
33879A
Output OFF Open Load Detection Current, Low Side Configuration
= 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
μA
OCO
V
DRAIN
VPWR =16 V
33879
40
40
75
75
135
150
33879A
Output Clamp Voltage Low Side Drive
V
V
V
OC(LSD)
OC(HSD)
OUT(LKG)
OUT(LKG)
I
= 10 mA
40
-15
–
45
-20
–
55
-25
5.0
D
Output Clamp Voltage High Side Drive
= -10 mA
V
I
S
Output Leakage Current High Side and Low Side Configurations
= 0 V, V = 16 V, V = 0 V
I
I
μA
μA
V
DD
DRAIN
SOURCE
Output Leakage Current Low Side Configuration
= 5.0 V, V = 16 V, V = 0 V,
V
DD
DRAIN
SOURCE
Open Load Detection Current Disabled
–
–
5.0
Output Leakage Current High Side Configuration
= 5.0 V, V = 16 V, V = 0 V,
I
μA
OUT(LKG)
V
DD
DRAIN
SOURCE
Open Load Detection Current Disabled
Over-temperature Shutdown(8)
Over-temperature Shutdown Hysteresis(8)
Notes
–
–
–
20
185
15
T
155
5.0
°C
°C
LIM
T
10
LIM(HYS)
7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.
8. This parameter is guaranteed by design; however, it is not production tested.
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic High-voltage Thresholds(9)
Input Logic Low-voltage Thresholds(9)
V
0.7 VDD
–
–
VDD + 0.3
0.2 VDD
V
V
IH
V
GND -0.3
IL
IN5, IN6, EN Input Logic Current
IN5, IN6, EN = 0 V
I
I
I
μA
IN5, IN6, EN
-10
30
–
10
IN5, IN6 Pull-down Current
0.8 to 5.0 V
I
I
μA
μA
IN5, IN6,
45
100
EN Pull-down Current
EN = 5.0 V
I
EN
33879
20
20
45
45
100
110
33879A
SCLK, DI Input, Tri-state DO Output
0 to 5.0 V
I
I
I
μA
μA
SCK, DI, TRI-
DO
-10
-10
–
–
10
10
CS Input Current
CS = VDD
I
I
CS
CS
CS Pull-up Current
CS = 0 V
μA
μA
-30
–
–
–
-100
10
CS Leakage Current to VDD
I
CS(LKG)
CS = 5.0 V, V
= 0 V
DD
DO High State Output Voltage
= -1.6 mA
V
V
V
DOHIGH
I
V
-0.4
–
VDD
DO-HIGH
DD
DO Low State Output Voltage
= 1.6 mA
V
DOLOW
I
–
–
–
0.4
20
DO-LOW
Input Capacitance on SCLK, DI, Tri-state DO, IN5, IN6, EN(10)
C
–
pF
IN
Notes
9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
10. This parameter is guaranteed by design; however, it is not production tested.
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate Low Side Configuration(11)
= 620Ω, CL = 200pF
tSR(RISE)
tSR(FALL)
tSR(RISE)
tSR(FALL)
V/μs
V/μs
V/μs
V/μs
R
0.1
0.1
0.1
0.1
1.0
0.5
0.5
0.3
0.3
15
1.0
1.0
1.0
1.0
50
LOAD
Output Slew Rate Low Side Configuration(11)
= 620 Ω, CL = 200 pF
R
LOAD
Output Rise Time High Side Configuration(11)
= 620 Ω, CL = 200 pF
R
LOAD
Output Fall Time High Side Configuration(11)
= 620 Ω, CL = 200 pF
R
LOAD
Output Turn ON Delay Time, High Side and Low Side Configuration(12)
tDLY(ON)
tDLY(OFF)
tFAULT
μs
μs
Output Turn OFF Delay Time, High Side and Low Side Configuration(12)
1.0
30
–
100
300
Output Fault Delay Time(13)
Power-ON Reset Delay
100
μs
μs
t
POR
Delay Time Required from Rising Edge of EN and V
to SPI Active
100
100
–
–
–
–
DD
Low-State Duration on V
or EN for Reset
t
µs
DD
RESET
V
or EN ≤ 0.2 V
DD
Notes
11. Output slew rate respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
CL capacitor is connected from Drain or Source output to Ground.
12. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition
points.
13. Duration of fault before fault bit is set. Duration between access times must be greater than 300 μs to read faults.
33879
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING(14)
Recommended Frequency of SPI Operation(14)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
DI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time(15)
fSPI
–
100
50
16
20
–
4.0
–
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
LEAD
t
–
–
LAG
t
–
–
DI(SU)
t
–
–
DI(HOLD)
t
t
5.0
5.0
–
–
R(DI)
F(DI)
DI, CS, SCLK Signal Fall Time(15)
–
–
Time from Falling Edge of CS to DO Low-impedance(16)
Time from Rising Edge of CS to DO High-impedance(17)
Time from Rising Edge of SCLK to DO Data Valid(18)
Notes
t
–
55
55
55
DO(EN)
t
–
–
DO(DIS)
t
–
25
VALID
14. This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output status data to be available for use at DO pin.
17. Time required for output status data to be terminated at DO pin.
18. Time required to obtain valid data out from DO following the rise of SCLK.
TIMING DIAGRAMS
CS
0.2 V
DD
t
t
LAG
LEAD
0.7 V
0.2 V
DD
SCLK
DD
t
t
DI(SU) DI(HOLD)
0.7 V
0.2 V
DD
DI
MSB in
DD
t
t
DO(DIS)
DO(EN)
t
VALID
0.7 V
0.2 V
DD
DO
MSB out
LSB out
DD
Figure 4. SPI Timing Diagram
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
t
< 50 ns
50%
< 50 ns
3.3/5.0 V
t
R(DI)
F(DI
V
= 5.0 V
DD
0.7 V
DD
0.2 V
SCLK
DD
0 V
33879
Under
Test
DO
C = 200 pF
SCLK
V
OH
0.7 V
DD
L
DO
0.2 V
0.7 V
DD
V
V
OL
t
(Low-to-High)
DO
R(DO
t
VALID
0.2
OH
(High-to-Low)
DD
NOTE: C represents the total capacitance of the test
L
V
fixture and probe.
OL
Figure 5. Valid Data Delay Time
and Valid Time Test Circuit
Figure 6. Valid Data Delay Time
and Valid Time Waveforms
t
t
F(CS)
R(CS)
<50 ns
<50 ns
0.7 V
3.3/5.0 V
0 V
90%
10%
CS
DO
DD
0.2 V
DD
t
t
DO(EN)
DO(DIS)
V
Tri-State
90%
(Tri-StatetoLow)
10%
V
OL
t
t
DO(EN)
DO(DIS)
V
V
OH
90%
Tri-State
DO
10%
(Tri-State to High)
Figure 7. Enable and Disable Time Waveforms
TYPICAL ELECTRICAL CHARACTERISTICS
7
20
19
18
17
16
15
14
V
@ 13 V
PWR
V
@ 18 V
PWR
6
5
4
3
2
1
33879
33879A
-40 -25
0
25
50
75
100 125
-40 -25
0
25
A, Ambient Temperature (ℜ°C
Figure 8. IPWR vs. Temperature
50
75
100 125
TA, Ambient Temperature (ℜ°C
T
Figure 9. Sleep State IPWR vs. Temperature
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
140
120
100
80
140
120
100
80
V
@ 13 V
T
= 25ℜ°
PWR
A
33879
60
60
High Side
Low Side
40
40
20
20
33879A
0
-40 -25
0
25
50
75
100 125
5
10
VPWR
Figure 10. Sleep State IPWR vs. VPWR
15
20
25
T
A, Ambient Temperature (ℜ°C
Figure 13. Open Load Detection Current at Threshold
1.4
1.2
1.0
0.8
0.6
0.4
V
@ 13 V
5.5
PWR
V
@ 13 V
PWR
High Side Drive
High Side and Low Side
5.0
4.5
4.0
3.5
3.0
2.5
-40 -25
0
25
50
75
100 125
-40 -25
0
25
50
75
100 125
T
A, Ambient Temperature (ℜ°C
TA, Ambient Temperature (ℜ°C
Figure 11. RDS(ON) vs. Temperature at 350 mA
Figure 14. Open Load Detection
Threshold vs. Temperature
1.4
T
= 25ℜ°
A
High Side Drive
1.2
1.0
0.8
0.6
0.4
0.2
0
5
10
15
20
25
VPWR (V)
Figure 12. RDS(ON) vs. VPWR at 350 mA
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
logic [0] followed by the status of the eight output drivers. The
CS PIN
DI/DO shifting of data follows a first-in, first-out protocol with
both input and output words transferring the most significant
bit (MSB) first.
The system MCU selects the 33879 with which to
communicate through the use of the chip select CS pin. Logic
low on CS enables the data output (DO) driver and allows
data to be transferred from the MCU to the 33879 and vice
versa. Data clocked into the 33879 is acted upon on the rising
edge of CS.
EN PIN
The EN pin on the 33879 enables the device. With the EN
pin high, output drivers may be activated and open/short fault
detection performed and reported. With the EN pin low, all
outputs become inactive, Open Load Detection Current is
disabled, and the device enters Sleep mode. The 33879 will
perform Power-ON Reset on rising edge of the enable signal.
To avoid any spurious data, it is essential the high-to-low
transition of the CS signal occur only when SPI clock (SCLK)
is in a logic low state.
SCLK PIN
The SCLK pin clocks the internal shift registers of the
33879. The serial data input (DI) pin is latched into the input
shift register on the falling edge of the SCLK. The serial data
output (DO) pin shifts data out of the shift register on the
rising edge of the SCLK signal. False clocking of the shift
register must be avoided to ensure validity of data. It is
essential that the SCLK pin be in a logic low state when the
CS pin makes any transition. For this reason, it is
recommended the SCLK pin is commanded to a logic low
state when the device is not accessed (CS in logic high state).
With CS in a logic high state, signals present on SCLK and DI
are ignored and the DO output is tri-state.
IN5 AND IN6 PINS
The IN5 and IN6 command inputs allow outputs five and
six to be used in PWM applications. The IN5 and IN6 pins are
OR-ed with the Serial Peripheral Interface (SPI) command
input bits. For SPI control of outputs five and six, the IN5 and
IN6 pins should be grounded or held low by the
microprocessor. When using IN5 or IN6 to PWM the output,
the control SPI bit must be logic [0]. Maximum PWM
frequency for each output is 2.0 kHz.
VDD PIN
The VDD input pin is used to determine logic levels on the
microprocessor interface (SPI) pins. Current from VDD is
used to drive DO output and the pullup current for CS. VDD
must be applied for normal mode operation. The 33879
device will perform Power-ON Reset with the application of
VDD.
DI PIN
The DI pin is used for serial instruction data input. DI
information is latched into the input register on the falling
edge of SCLK. A logic high state present on DI will program
a specific output on. The specific output will turn on with the
rising edge of the CS signal. Conversely, a logic low state
present on the DI pin will program the output off. The specific
output will turn off with the rising edge of the CS signal. To
program the eight outputs and Open Load Detection Current
on or off, send the DI data beginning with the Open Load
Detection Current bits, followed by output eight, output
seven, and so on to output one. For each falling edge of the
SCLK while CS is logic low, a data bit instruction (on or off) is
loaded into the shift register per the data bit DI state. Sixteen
bits of entered information is required to fill the input shift
register.
VPWR PIN
The VPWR pin is battery input and Power-ON Reset to the
33879 IC. The VPWR pin has internal reverse battery
protection. All internal logic current is provided from the
VPWR pin. The 33879 will perform Power-ON Reset with the
application of VPWR.
D1–D8 PINS
The D1 to D8 pins are the open-drain outputs of the 33879.
For high side drive configurations, the drain pins are
connected to battery supply. In low side drive configurations,
the drain pins are connected to the low side of the load. All
outputs may be configured individually as desired. When
configured as low side drive, the 33879 limits the positive
inductive transient to 45 V.
DO PIN
The DO pin is the output from the shift register. The DO pin
remains tri-state until the CS pin is in a logic low state. All
faults on the 33879 device are reported as logic [1] through
the DO data pin. Regardless of the configuration of the driver,
open loads and shorted loads are reported as logic [1].
Conversely, normal operating outputs with non-faulted loads
are reported as logic [0]. Outputs programmed with Open
Load Detection Current disabled will report logic [0] in the off
state. The first eight positive transitions of SCLK will report
S1–S8 PINS
The S1 to S8 pins are the source outputs of the 33879. For
high side drive configurations, the source pins are connected
directly to the load. In low side drive configurations, the
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DESCRIPTION
MCU INTERFACE DESCRIPTION
source is connected to ground. All outputs may be configured
individually as desired. When high side drive is used, the
33879 will limit the negative inductive transient to negative
20 V.
EXPOSED PAD PIN
Device will perform as specified with the Exposed Pad un-
terminated (floating) however, it is recommended that the
Exposed Pad be terminated to pin 1 (GND) and system
ground.
MCU INTERFACE DESCRIPTION
each device while the CS bit is commanded low by the MCU.
During each clock cycle, output status from the daisy chain is
transferred to the MCU via the Master In Slave Out (MISO)
line. On rising edge of CS, command data stored in the input
register is then transferred to the output driver.
INTRODUCTION
The 33879 is an 8-output hardware-configurable power
switch with 16-bit serial control. A simplified internal block
diagram of the 33879 is shown in Figure 2 on page 3.
The 33879 device uses high-efficiency up-drain power
DMOS output transistors exhibiting low drain-to-source ON
resistance (RDS(ON) = 0.75 Ω at 25°C typical) and dense
CMOS control logic. All outputs have independent voltage
clamps to provide fast inductive turn-off and transient
protection.
SCLK
Parallel Port
33879
CS
33879
33879
In operation, the 33879 functions as an 8-output serial
switch serving as a MCU bus expander and buffer with fault
management and fault reporting features. In doing so, the
device directly relieves the MCU of the fault management
functions. This device directly interfaces to an MCU using a
SPI for control and diagnostic readout. Figure 15 illustrates
the basic SPI configuration between an MCU and one 33879.
CS SCLK
CS SCLK
MC68HCxx
Microcontroller
with
MISO
DO
DI
DO
DI
DO
DI
SPI Interface
8 Outputs
8 Outputs
8 Outputs
MOSI
MC68HCxx
Microcontroller
33879
Figure 16. 33879 SPI System Daisy Chain
Multiple 33879 devices can be controlled in a parallel input
fashion using the SPI. Figure 17 illustrates the control of
24 loads using three dedicated parallel MCU ports for chip
select.
DI
MOSI
MISO
Shift Register
16 Bits
Shift Register
16 Bits
DO
33879
MOSI
DI
SCLK
CS
SCLK
SCLK
Receive
Buffer
To
Logic
MISO
8 Outputs
DO
CS
Parallel
Ports
MC68HCxx
Microcontroller
with
33879
SPI Interface
DI
Figure 15. SPI Interface with Microcontroller
SCLK
DO
All inputs are compatible with 5.0 V and 3.3 V CMOS logic
levels and incorporate positive logic. When a SPI bit is
programmed to a logic [0], the corresponding output will be
OFF. Conversely, when a SPI bit is programmed to logic [1]
the output being controlled will be ON. Diagnostics are
treated in a similar manner. Outputs with a fault will feed back
(via DO) a logic [1] to the microcontroller, while normal
operating outputs will provide a logic [0].
8 Outputs
8 Outputs
CS
33879
DI
A
Parallel
Ports
SCLK
DO
B
C
CS
Figure 16 illustrates the daisy chain configuration using
the 33879. Data from the MCU is clocked daisy chain through
Figure 17. Parallel Input SPI Control
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
SPI DEFINITION
SPI DEFINITION
On each SPI communication, a 16-bit command word is
sent to the 33879 and a 16-bit status word is received from
the 33879. The MSB is sent and received first. As Table
shows, the Command Register defines the position and
operation the 33879 will perform on rising edge of CS. The
Fault Register, shown in Table 6, defines the previous state
status of the output driver. Table identifies the type of fault
and the method by which the fault is communicated to the
microprocessor
Table 6. Command Register Definition
MSB
LSB
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
Open Open Open Open Open Open Open
Load Load Load Load Load Load Load
Detect Detect Detect Detect Detect Detect Detect Detect
Open OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
Load
8
7
6
5
4
3
2
1
0 = Bits 0 to 7, Output commanded OFF.
1 = Bits 0 to 7, Output commanded ON.
0 = Bits 8 to 15, Open Load Detection Current OFF.
1 = Bits 8 to 15 Open Load Detection Current ON.
Table 7. Fault Register Definition
MSB
LSB
Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
0
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
Status Status Status Status Status Status Status Status
0 = Bits 0 to 7, No Fault at Output.
1 = Bits 0 to 7, Output Short-to-Battery, Short-to-GND,
Open Load, or TLIM
Bits 8 to 15 will always return “0”.
.
Table 8. Fault Operation
Serial Output (DO) Pin Reports
Over-temperature
Fault reported by serial output (DO) pin.
DO pin reports short to battery/supply or over-current condition.
Not reported.
Over-current
Output ON Open Load Fault
Output OFF Open Load Fault
DO pin reports output OFF open load condition only with Open Load Detection Current enabled.
DO pin will report “0” for Output OFF Open Load Fault with Open Load Detection Current disabled.
Device Shutdowns
Over-voltage
Total device shutdown at V
= VPWR(OV) V. Resumes normal operation with proper voltage. All
PWR
outputs assuming the previous state upon recovery from over-voltage.
Over-temperature
Only the output experiencing an over-temperature shuts down. Output assumes previous state upon
recovery from over-temperature.
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DESCRIPTION
DEVICE OPERATION
DEVICE OPERATION
SPI INTEGRITY CHECK
POWER SUPPLY
The 33879 device has been designed with ultra-low Sleep
mode currents. The device may enter Sleep mode via the EN
pin or the VDD pin. In the Sleep mode (EN or VDD ≤ 0.8 V),
the current consumed by the VPWR pin is less than 5.0 μA.
Checking the integrity of the SPI communication with the
initial power-up of the VDD and EN pins is recommended.
After initial system start-up or reset, the MCU will write one
32-bit pattern to the 33879. The first 16 bits read by the MCU
will be 8 logic [0]s followed by the fault status of the outputs.
The second 16 bits will be the same bit pattern sent by the
MCU. By the MCU receiving the same bit pattern it sent, bus
integrity is confirmed. Please note the second 16-bit pattern
the MCU sends to the device is the command word and will
be transferred to the outputs with rising edge of CS.
Placing the 33879 in Sleep mode resets the internal
registers to the Power-ON Reset state. The reset state is
defined as all outputs off and Open Load Detection Current
disabled.
To place the 33879 in the Sleep mode, either command all
outputs off and apply logic low to the EN input pin or remove
power from the VDD supply pin. Prior to removing VDD from
the device, it is recommended that all control inputs from the
MCU be low.
Important A SCLK pulse count strategy has been
implemented to ensure integrity of SPI communications. SPI
messages consisting of 16 SCLK pulses and multiples of
8 clock pulses thereafter will be acknowledged. SPI
messages consisting of other than 16 + multiples of 8 SCLK
pulses will be ignored by the device.
PARALLELING OF OUTPUTS
Using MOSFETs as an output switch conveniently allows
the paralleling of outputs for increased current capability.
RDS(ON) of MOSFETs have an inherent positive temperature
coefficient that provides balanced current sharing between
outputs without destructive operation. This mode of operation
may be desirable in the event the application requires lower
power dissipation or the added capability of switching higher
currents. Performance of parallel operation results in a
corresponding decrease in RDS(ON) while the output OFF
Open Load Detection Currents and the output current limits
increase correspondingly. Paralleling outputs from two or
more different IC devices is possible but not recommended.
OVER-TEMPERATURE FAULT
Over-temperature detection and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an over-temperature condition is
independent of the system clock or any other logic signal.
Each independent output shuts down at 155°C to 185°C.
When an output shuts down owing to an over-temperature
fault, no other outputs are affected. The MCU recognizes the
fault by a one in the fault status register. After the 33879
device has cooled below the switch point temperature and
15°C hysteresis, the output will activate unless told otherwise
by the MCU via SPI to shut down.
FAULT LOGIC OPERATION
Fault logic of the 33879 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs
faulted and Open Load Detection Current enabled, all status
bits being received by the MCU will be zero. When outputs
are faulted (off state open circuit or on state short-circuit/
over-temperature), the status bits being received by the MCU
will be one. The distinction between open circuit fault and
short/over-temperature is completed via the command word.
For example, when a zero command bit is sent and a one
fault is received in the following word, the fault is open/short-
to-battery for high side drive or open/short-to-ground for low
side drive. In the same manner, when a one command bit is
sent and a one fault is received in the following word, the fault
is a short-to-ground/over-temperature for high side drive or
short-to-battery/over-temperature for low side drive. The
timing between two write words must be greater than 300 μs
to allow adequate time to sense and report the proper fault
status.
OVER-VOLTAGE FAULT
An over-voltage condition on the VPWR pin will cause the
device to shut down all outputs until the over-voltage
condition is removed. When the over-voltage condition is
removed, the outputs will resume their previous state. This
device does not detect an over-voltage on the VDD pin. The
over-voltage threshold on the VPWR pin is specified as
VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR over-
voltage detection is global, causing all outputs to be turned
OFF.
OUTPUT OFF OPEN LOAD FAULT
An output OFF open load fault is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The
Output OFF Open Load fault is detected by comparing the
drain-to-source voltage of the specific MOSFET output to an
internally generated reference. Each output has one
dedicated comparator for this purpose.
An output OFF open load fault is indicated when the drain-
to-source voltage is less than the output threshold voltage
(VOUT(FLT-TH)) of 2.5 V to 4.0 V. Hence, the 33879 will
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
DEVICE OPERATION
declare the load open in the OFF state when the output drain-
output. Each clamp independently limits the drain-to-source
voltage to 45 V for low side drive configurations and -20 V for
high side drive configurations. The total energy clamped (EJ)
can be calculated by multiplying the current area under the
current curve (IA) times the clamp voltage (VCL) (see
Figure 18).
to-source voltage is less than VOUT(FLT-TH)
.
This device has an internal 80 μA current source
connected from drain to source of the output MOSFET. The
current source may be programmed on or off via SPI. The
Power-ON Reset state for the current source is “off” and must
be enabled via SPI. To achieve low Sleep mode quiescent
currents, the Open Load Detection Current source of each
driver is switched off when VDD or EN is removed.
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.35 A, indicates the maximum
energy per output to be 50 mJ at 150°C junction temperature.
During output switching, especially with capacitive loads,
a false output OFF open load fault may be triggered. To
prevent this false fault from being reported, an internal fault
filter of 100 μs to 300 μs is incorporated. A false fault
reporting is a function of the load impedance, RDS(ON), COUT
of the MOSFET, as well as the supply voltage, VPWR. The
rising edge of CS triggers the built-in fault delay timer. The
timer will time out before the fault comparator is enabled and
the fault is detected. Once the condition causing the open
load fault is removed, the device will resume normal
operation. The open load fault, however, will be latched in the
output DO register for the MCU to read.
Drain-to-Source Clamp
Voltage (VCL = 45 V)
Drain Voltage
Clamp Energy
Drain Current
(ID = 0.3 A)
(E = I x V )
J
A
CL
Drain-to-Source ON
Voltage (V
)
Current
Area (I
DS(ON)
)
A
GND
Drain-to-Source ON
Voltage (V
Time
BAT
Time
SHORTED LOAD FAULT
)
DS(ON)
VS
A shorted load (over-current) fault can be caused by any
output being shorted directly to supply, or an output
experiencing a current greater than the current limit.
GND
Current
Area (I )
A
There are two safety circuits progressively in operation
during load short conditions that provide system protection:
Clamp Energy
(E = I x V )
CL
J
A
1. The device’s output current is monitored in an analog
fashion using SENSEFET approach and current
limited.
Source Current
(I = 0.3 A)
S
Source Clamp Voltage
Source Voltage
2. The device’s output thermal limit is sensed and when
attained causes only the specific faulted output to shut
down. The output will remain off until cooled. The
device will then reassert the output automatically. The
cycle will continue until fault is removed or the
command bit instructs the output off. Shorted load
faults will be reported properly through the SPI
regardless of Open Load Detection Current enable
bits.
(V
= -15 V)
CL
Figure 18. Output Voltage Clamping
SPI CONFIGURATIONS
The SPI configuration on the 33879 device is consistent
with other devices in the Octal Serial Switch (OSS) family.
This device may be used in serial SPI or parallel SPI with the
33298 and 33291. Different SPI configurations may be
provided. For more information, contact Freescale Analog
Products Division or the local Freescale representative.
UNDER-VOLTAGE SHUTDOWN
An under-voltage condition on VDD or VPWR will result in
the shutdown of all outputs. The VDD under-voltage threshold
is between 0.8 and 3.0 V. VPWR under-voltage threshold is
between 3.0 and 5.0 V. When the supplies fall below their
respective thresholds, all outputs are turned OFF. As both
supplies returns to normal levels, internal logic is reset and
the device resumes normal operation.
REVERSE BATTERY
The 33879 has been designed with reverse battery
protection on the VPWR pin.
All outputs consist of a power MOSFET with an integral
substrate diode. During the reverse battery condition, current
will flow through the load via the substrate diode. Under this
circumstance, relays may energize and lamps will turn on.
Where load reverse battery protection is desired, a reverse
battery blocking diode must be placed in series with the load.
OUTPUT VOLTAGE CLAMP
Each output of the 33879 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of each
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search using the
“98ARL10543D” drawing number listed below. Dimensions shown are provided for reference ONLY.
EK (Pb-FREE) SUFFIX
32-LEAD SOICW EXPOSED PAD
98ARL10543D
ISSUE C
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
EK (Pb-FREE) SUFFIX
32-LEAD SOICW EXPOSED PAD
98ARL10543D
ISSUE C
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
PACKAGING
PACKAGE DIMENSIONS
EK (Pb-FREE) SUFFIX
32-LEAD SOICW EXPOSED PAD
98ARL10543D
ISSUE C
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the
internal block diagram.
2/2006
5.0
• Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin
definition.
• Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed.
The VDD Supply contains no hysteresis.
• Page 7, Table 3; Output Fault Detection Current @ Threshold, High-Side Configuration
Max parameter has been increased from 70uA to 90uA.
• Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration
has been updated to reflect the voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has
been updated to reflect the voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max
parameter has been decreased from 7uA to 5uA.
• Page 15, Functional Pin Description; A description has been added for the Exposed Pad
pin.
• Page 1, Device isometric; Corrected orientation of IC pin 1 from top left to bottom right.
• ALL Pages; Updated Data Sheet to reflect Freescale formatting.
• Added 33879A version
6/2007
6.0
• Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information
• Added Device Variations on page 2
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter
from Maximum Rations on page 6. Added note with instructions from
www.freescale.com.
• Changed Output Fault Detection Voltage Threshold(7) on page 8
• Renumbered X axis on Figure 14 - Open Load Detection Threshold vs. Temperature on
page 13
• Changed Over-voltage on page 16 and Over-voltage Fault on page 17
8/2008
• Updated package drawing.
7.0
8.0
• Updated data sheet status from Advance Information to Technical Data
• Updated to the current Freescale form and style
10/2009
• Removed MC33879EK from the ordering information
5/2012
9.0
• Removed MCZ33879AEK and added MC33879APEK to the ordering information
• Removed MCZ33879EK and added MC33879TEK to the ordering information
• Updated Output Fault Detection Current @ Threshold, High Side Configuration on page
8
• Updated Output OFF Open Load Detection Current, High Side Configuration on page 8
• Updated Output OFF Open Load Detection Current, Low Side Configuration on page 8
• Updated EN Pull-down Current on page 9
• Updated the Freescale form and style
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
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Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a
Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play,
SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2012 Freescale Semiconductor, Inc.
Document Number: MC33879
Rev. 9.0
5/2012
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