MC33897CEF [NXP]

DATACOM, INTERFACE CIRCUIT, PDSO14, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-012AB, SOIC-14;


型号：	MC33897CEF
厂家：	NXP
描述：	DATACOM, INTERFACE CIRCUIT, PDSO14, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-012AB, SOIC-14 电信光电二极管电信集成电路
文件：	总23页 (文件大小：701K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Document Number: MC33897

Rev. 14.0, 8/2006

Freescale Semiconductor

Advance Information

Single Wire CAN Transceiver

33897/A/B/C/D

The 33897 Series provides a physical layer for digital

communications purposes using a Carrier Sense Multiple Access/

Collision Resolution (CSMA/CR) data link operating over a single

wire medium. This is more commonly referred to as Single Wire

Controller Area Network (CAN).

SINGLE WIRE CAN

TRANSCEIVER

The 33897 Series operates directly from a vehicle's 12 V battery

system or a broad range of DC-power sources. It can operate at

either low or high (33.33 kbps or 83.33 kbps) data rates. A high-

voltage wake-up feature allows the device to control the regulator

used in support of the MCU and other logic. The device includes a

control terminal that can be used to put the module regulator into

Sleep mode. The presence of a defined wake-up voltage level on the

bus will reactivate the control line to turn the regulator and the system

back on.

EF (PB-FREE) SUFFIX

98ASB42564B

8-TERMINAL SOICN

D SUFFIX

EF (PB-FREE) SUFFIX

98ASB42565B

The device complies with the GMW3089v2.4 General Motors

Corporation specification.

14-TERMINAL SOICN

Features

• Waveshaping for Low Electromagnetic Interference (EMI)

• Detects and Automatically Handles Loss of Ground

• Worst-Case Sleep Mode Current of Only 60 µA

• Current Limit Prevents Damage Due to Bus Shorts

• Built-In Thermal Shutdown on Bus Output

• Protected Against Vehicular Electrical Transients

• Undervoltage Lockout Prevents False Data with Low Battery

• Pb-Free Packaging Designated by Suffix Code EF

ORDERING INFORMATION

Temperature

Device

Package

Range (T )

MC33897D/R2

MC33897TD/R2

MC33897EF/R2

MC33897TEF/R2

14 SOICN

MC33897AD/R2

MC33897AEF/R2

-40°C to 125°C

*MC33897CEF/R2

PC33897CLEF/R2

MC33897BEF/R2

8 SOICN

*MC33897DEF/R2

PC33897DLEF/R2

*Recommended device for all new designs

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Power

Source

VCC

Voltage

Regulator

Battery

VBATT

VCC

CNTL

TXD

RXD

BUS

SWC BUS

MCU

LOAD

MODE0

MODE1

GND

33897/A/C

Figure 1. 33897/A/C Simplified Application Diagram

VCC

Battery

VBATT

VCC

TXD

RXD

BUS

SWC BUS

MCU

LOAD

MODE0

MODE1

GND

33897B/D

Figure 2. 33897B/D Simplified Application Diagram

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

DEVICE VARIATIONS

Table 1. Device Variations

Load Voltage Sleep

Mode

Part No.

33897

Other Significant Differences

See Page

1.0 V Max

•

14-Pin Package

•

14-Pin Package

33897T

33897A

33897B

1.0 V Max

0.1 V Max

Electrical parameter changes noted in Errata MC33897TER, Revision 3.0

ESD is rated lower - Human Body Model - 1500 V, Machine Model - 100 V

14-Pin Package

Removes diode drop during Sleep Mode

May not detect Loss of Ground under certain module characteristics.

8-Pin Package

2, 3, 4, 6, 8 10,12, 14

Removes diode drop during Sleep Mode

Does not include the CNTL terminal

May not detect Loss of Ground under certain module characteristics.

14-Pin Package

*33897C

*33897D

0.1 V Max

Removes diode drop during Sleep Mode

Effectively detects Loss of Ground

8-Pin Package

2, 3, 4, 6, 8 10,12, 14

Removes diode drop during Sleep Mode

Effectively detects Loss of Ground

Does not include the CNTL terminal

*Recommended device for all new designs

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

INTERNAL BLOCK DIAGRAM

TXD BUS DRVR

TX Bus DRVR

HVWU En

MODE0

MODE1

HVWU Enable

BUS

Wave Shaping En

Waveshaping Enable

Mode

Control

TX Data

TXD Data

Control

Disable

Bus RCVR

BUS RCVR

WU D

tect

RX Data

RXD Data

Disable

TXD

RXD

Undervoltage

Detect

VBBAATTT

Timer

OSC

Timers

Load Switch

LOAD

GND

CNTL

CNTL*

*CNTL terminal is present on 33897/A/C only.

Figure 3. 33897/A/B/C/D Simplified Internal Block Diagram

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

PIN CONNECTIONS

33897/A/C

GND

TXD

GND

33897B/D

GND

BUS

TXD

MODE0

MODE1

RXD

BUS

MODE0

MODE1

RXD

LOAD

VBATT

CNTL

GND

LOAD

VBATT

GND

Figure 4. 33897/A/B/C/D Pin Connections

Table 2. Pin Definitions

A functional description of each terminal can be found in the Functional Pin Description section, beginning on page 14.

33897/A/C

Terminal

33897B/D

Terminal

Pin Name

Formal Name

Definition

Electrical Common Ground and Heat removal. A good thermal path will

also reduce the die temperature.

1, 7, 8, 14

GND

Ground

Data input here will appear on the BUS terminal. A logic [0] will assert

the bus, a logic [1] will make the bus go to the recessive state.

3, 4

TXD

Transmit Data

Mode Control

Receive Data

No Connect

These Pins control Sleep Mode, Transmit Level, and Speed. They have

weak pulldowns.

2, 3

MODE0,

MODE1

Open drain output of the data on BUS. A recessive bus = a logic [1], a

dominant bus = logic [0]. An external pullup is required.

RXD

No internal connection to these Pins. Pin 13 can be connected to GND

to allow the use of the 14-terminal or 8-terminal device. ⁽¹⁾

6, 13

–

Provides a battery-level logic signal.

–

CNTL

VBATT

LOAD

Control

Battery

Load

Power input. An external diode is needed for reverse battery protection.

The external bus load resistor connects here to prevent bus pullup in the

event of loss of module ground.

This terminal connects to the bus through external components.

BUS

Bus

Notes

1. Module boards can be planned for the 14-terminal package and still use the 8-terminal package.

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted.

Rating

Symbol

Value

Unit

Electrical Ratings

Supply Voltage

V_BATT

V_IN

V_RXD

V_CNTL

-0.3 to 40

-0.3 to 7.0

-0.3 to 40

Input Logic Voltage

RXD Pin Voltage

CNTL Pin Voltage (33897/A/C only)

ESD Voltage⁽²⁾

Human Body Model

All Pins Except BUS

BUS Terminal

ESD

±2000

±4000

±200

Machine Model

Thermal Ratings

Ambient Operating Temperature⁽³⁾

Junction Operating Temperature

Storage Temperature

-40 to 125

-40 to 150

-55 to 150

150

°C

T_STG

R_θJA

°C

Junction-to-Ambient Thermal Resistance

°C/W

°C

Peak Package Reflow Temperature During Solder Mounting ⁽⁴⁾

SOLDER

D Suffix

245

260

EF (Pb-Free) Suffix

Notes

2. ESD testing is performed in accordance with the Human Body Model (C

= 100 pF, R

= 1500 Ω),

ZAP

Machine Model (C

= 200 pF, R

= 0 Ω). Refer to Table 1, Device Variations for Part Number 33897T

ZAP

3. When using the 8-terminal device, consider the power dissipation at a high operating voltage and maximum network loading at ambient

temperatures exceeding 85°C.

4. Pin soldering temperature limit is for 10 second maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions of -40°C ≤ T_A≤ 125°C, unless otherwise stated. Voltages are relative to GND unless

otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Characteristic

Symbol

Min

Typ

Max

Unit

GENERAL

Quiescent Current

Sleep

I_QSLP

I_QATDIS

I_QATEN

5.0 V ≤ V_BATT≤ 13 V ⁽⁵⁾

–

4.0

9.0

µA

Awake with Transmitter Disabled

5.0 V ≤ V_BATT≤ 26.5 V

Awake with Transmitter Enabled

–

5.0 V ≤ V_BATT≤ 26.5 V

Undervoltage Shutdown

V_BATTUV

T_SD

4.0

–

5.0

Thermal Shutdown ⁽⁶⁾

190

°C

5.0 V ≤ V_BATT≤ 26.5 V

150

Thermal Shutdown Hysteresis ⁽⁶⁾

T_SDHYS

°C

5.0 V ≤ V_BATT≤ 26.5 V

–

LOGIC I/O, MODE0, MODE1, TXD, RXD

Logic Input Low Level (MODE0, MODE1, and TXD)

V_IL

V_IH

I_PD

5.0 V ≤ V_BATT≤ 26.5 V

–

2.0

–

0.8

–

Logic Input High Level (MODE0, MODE1, and TXD)

5.0 V ≤ V_BATT≤ 26.5 V

Mode Pin Pulldown Current (MODE0 and MODE1)

µA

Pin Voltage = 0.8 V, 5.0 V ≤ V_BATT≤ 26.5 V

Receiver Output Low (RXD)

V_OL

I_IN= 2.0 mA, 5.0 V ≤ V_BATT≤ 26.5 V

0.45

CNTL (33897/A/C ONLY)

CNTL Output Low

V_OLCNTL

I_IN= 5.0 µA, 5.0 V ≤ V_BATT≤ 26.5 V

–

0.8

CNTL Output High

V_OHCNTL

I_OUT= 180 µA, 5.0 V ≤ V_BATT≤ 26.5 V

V_BATT- 0.8

V_BATT

Notes

5. After t

CNTLFDLY

6. Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization.

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions of -40°C ≤ T_A≤ 125°C, unless otherwise stated. Voltages are relative to GND unless

otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Characteristic

Symbol

Min

Typ

Max

Unit

LOAD

LOAD Voltage Rise ⁽⁷⁾

V_LDRISE

Normal Speed and Voltage Mode, Transmit High-

Voltage Mode, Transmit High-Speed Mode

–

0.1

I_IN= 1.0 mA, 5.0 V ≤ V_BATT≤ 26.5 V

Sleep Mode

–

1.0

0.1

33897, I_IN= 7.0 mA

33897A/B/C/D I_IN= 7.0 mA ⁽⁸⁾

Loss of Battery

I_IN= 7.0 mA

–

1.0

LOAD Leakage During Loss of Module Ground ⁽⁹⁾

0.0 V ≤ V_BATT≤ 18 V33897/A/B

I_LDLEAK

µA

0.0

-10

–

-90

0.0 V ≤ V_BATT≤ 18 V33897C/D

BUS

Passive Out BUS Leakage

Passive In

I_LEAK

I_LKAI

-5.0

–

5.0

0.0 V ≤ V_BATT≤ 26.5 V, -1.5 V ≤ V_BUS< 0 V

Active In

0.0 V ≤ V_BATT≤ 26.5 V, 0 V < V_BUS≤ 12.5 V

BUS Leakage During Loss of Module Ground ⁽¹⁰⁾

I_BLKLOG

0.0 V ≤ V_BATT≤ 18 V33897/A/B

-10

0.0

–

0.0 V ≤ V_BATT≤ 18 V33897C/D

-90

High-Voltage Wake-up Mode Output High Voltage

12 V ≤ V_BATT≤ 26.5 V, 200 Ω ≤ R_L≤ 3332 Ω

33897

9.7

9.9

–

12.5

HVWUOHF

33897A/B/C/D

HVWUOHO

5.0 V ≤ V_BATT< 12 V, 200 Ω ≤ R_L≤ 3332 Ω

Lesser of V

- 1.5 or 9.7

V_BATT

BAT

High-Speed Mode Output High Voltage

V_OHHS

8.0 V ≤ V_BATT≤ 16 V, 75 Ω ≤ R_L≤ 135 Ω

4.2

–

5.1

Normal Mode Output High Voltage

6.0 V ≤ V_BATT≤ 26.5 V, 200 Ω ≤ R_L≤ 3332 Ω

5.0 V ≤ V_BATT< 6.0 V, 200 Ω ≤ R_L≤ 3332 Ω

V_NOHF

V_NOHO

4.4

–

5.1

Lesser of V_BATT- 1.6 or

4.4

Lesser of V_BATT

or 5.1

BUS Low Voltage

V_OL

5.0 V ≤ V_BATT≤ 26.5 V, 200 Ω ≤ R_L≤ 3332 Ω

-0.2

–

0.2

Short Circuit BUS Output Current

I_BSC

Dominant State, 5.0 V ≤ V_BATT≤ 26.5 V

-350

-150

Notes

7. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode.

The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4.

8. 33897A/B/C/D remove diode drop during Sleep mode.

9. LOAD terminal is at system ground voltage.

10. BUS terminal is at system ground voltage

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions of -40°C ≤ T_A≤ 125°C, unless otherwise stated. Voltages are relative to GND unless

otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Characteristic

Symbol

Min

Typ

Max

Unit

BUS (CONTINUED)

Input Threshold

Awake

2.0

–

2.2

5.0 V ≤ V_BATT≤ 26.5 V

V_BIA

V_BISF

V_BISO

Sleep

6.6

–

7.9

12 V ≤ V_BATT≤ 26.5 V

Sleep

Lesser of 6.6 V or

Lesser of 7.9 V or

5.0 V ≤ V_BATT< 12 V

- 4.3

- 3.25

BATT

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions of -40°C ≤ T_A≤ 125°C, unless otherwise stated. Voltages are relative to GND unless

otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Characteristic

Symbol

Min

Typ

Max

Unit

BUS

Normal Speed Rising Output Delay

t_DLYNORMRO

µs

200 Ω ≤ R_L≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs

Measured from TXD = V_ILto V_BUSas follows:

2.0

–

6.3

Max Time to V_BUSMOD= 3.7 V, 6.0 V ≤ V_BATT≤ 26.5 V ⁽¹¹⁾

Min Time to V_BUSMOD= 1.0 V, 6.0 V ≤ V_BATT≤ 26.5 V ⁽¹¹⁾

Max Time to V_BUSMOD= 2.7 V, V_BATT= 5.0 V ⁽¹¹⁾

Min Time to V_BUSMOD= 1.0 V, V_BATT= 5.0 V ⁽¹¹⁾

Normal Speed Falling Output Delay

t_DLYNORMFO

µs

200 Ω ≤ R_L≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs

Measured from TXD = V_IHto V_BUSas follows:

1.8

–

8.5

Max Time to V_BUSMOD= 1.0 V, 6.0 V ≤ V_BATT≤ 26.5 V ⁽¹¹⁾

Min Time to V_BUSMOD= 3.7 V, 6.0 V ≤ V_BATT≤ 26.5 V ⁽¹¹⁾

Max Time to V_BUSMOD= 1.0 V, V_BATT= 5.0 V ⁽¹¹⁾

Min Time to V_BUSMOD= 2.7 V, V_BATT= 5.0 V ⁽¹¹⁾

High-Speed Rising Output Delay

t_DLYHSRO

µs

75 Ω ≤ R_L≤ 135 Ω, 0.0 µs ≤ Load Time Constants ≤ 1.5 µs,

0.1

–

1.7

8.0 V ≤ V

≤ 16 V

BATT

Measured from TXD = V_ILto V_BUSas follows:

Max Time to V_BUS= 3.7 V ⁽¹²⁾

Min Time to V_BUS= 1.0 V ⁽¹²⁾

High-Speed Falling Output Delay

t_DLYHSFO

µs

75 Ω ≤ R_L≤ 135 Ω, 0.0 µs ≤ Load Time Constants ≤ 1.5 µs,

0.04

–

3.0

8.0 V ≤ V

≤ 16 V

BATT

Measured from TXD = V_IHto V_BUSas follows:

Max Time to V_BUS= 1.0 V ⁽¹²⁾

Min Time to V_BUS= 3.7 V ⁽¹²⁾

Notes

11.

12.

is the voltage at the BUSMOD node in Figure 7, page 16.

BUSMOD

is the voltage at the BUS terminal in Figure 8, page 16.

BUS

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions of -40°C ≤ T_A≤ 125°C, unless otherwise stated. Voltages are relative to GND unless

otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Characteristic

Symbol

Min

Typ

Max

Unit

BUS (CONTINUED)

High-Voltage Rising Output Delay

t_DLYHVRO

µs

200 Ω ≤ R_L≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs

Measured from TXD=V_ILto V_BUSas follows:

Max Time to V_BUSMOD= 3.7 V, 6.0 V ≤ V_BATT≤ 26.5 V ⁽¹³⁾

Min Time to V_BUSMOD= 1.0 V, 6.0 V ≤ V_BATT≤ 26.5 V ⁽¹³⁾

Max Time to V_BUSMOD= 9.4 V, 12.0 V ≤ V_BATT≤ 26.5 V ⁽¹³⁾

2.0

–

6.3

High-Voltage Falling Output Delay

t_DLYHVFO

µs

200 Ω ≤ R_L≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs,

12.0 V ≤ V_BATT≤ 26.5 V

Measured from TXD=V_IHto V_BUSas follows:

Max Time to V_BUSMOD= 1.0 V ⁽¹³⁾

Min Time to V_BUSMOD= 3.7 V ⁽¹³⁾

1.8

–

RECEIVER RXD

Receive Delay Time (5.0 V ≤ V_BATT≤ 26.5 V)

µs

RDLY

Awake

0.2

–

1.0

Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ V_BATT≤ 26.5 V)

RDLYSL

Sleep

CNTL

CNTL Falling Delay Time (5.0 V ≤ V_BATT≤ 26.5 V) (33897/A/C only)

300

–

1000

CNTLFDLY

Notes

13.

is the voltage at the BUSMOD node in Figure 7, page 16.

BUSMOD

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

TIMING DIAGRAMS

DYNAMIC ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

t_DLYNORMFO

t_DLYNORMRO

V_IH

TXD

V_IL

V_NOHF

V_BUSMOD

Bus

V_BIA

V_BUSMOD

V_IH

RXD

V_IL

t_RDLY

is the voltage at the BUSMOD node in Figure 7.

* V

BUSMOD

Figure 5. TXD, Bus and RXD Waveforms in Normal Mode

DLYHSRO

DLYHSFO

TXD

NOHF

BUS *

Bus

BIA

BUS *

RXD

RDLY

* V

is the voltage at the BUS terminal in Figure 8.

BUS

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

TIMING DIAGRAMS

DYNAMIC ELECTRICAL CHARACTERISTICS

Figure 6. TXD, Bus and RXD Waveforms in High Speed Mode

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33897 Series is intended for use as a physical layer

device in a Single Wire CAN communications bus.

actual system communications where the radiated EMI of the

higher rate could be an issue.

Communications takes place from a single terminal over a

single wire using a common ground for a current return path.

Two data rates are available, with the high rate used for

factory or assembly line communications and the lower for

Two Pins control the mode of operation (sleep, low-speed,

high-speed, and high-voltage wake-up).

FUNCTIONAL PIN DESCRIPTION

The 33897 Series is intended to be used with an MCU to

control its operation and to process and generate the data for

the bus.

RXD Data

The data received on the bus is translated to logic levels

on this terminal. This terminal is a logic high when the bus is

in the recessive state (near zero volts) and is logic low when

the bus is in either the normal or high-voltage dominant state.

GROUND PINS (33897/A/C)

The four ground PINS are not only for electrical

conduction, their number and locations at each of the four

corners serve also to remove heat from the IC. The biggest

benefit of this is obtained by putting a lot of copper on the

PCB in this area and, if ground is an internal layer, by adding

numerous plated-through connections to it with the largest

diameter holes the layout can use.

This is an open-drain type of output that requires an

external resistor to pull it up. When the device is in sleep

mode, the output will be off unless a high-voltage wake-up

level is detected on the bus. If the wake-up level is detected,

the output will be driven by the data on the bus. If the level of

the data returns to normal level, the output will return to off

after a short delay unless a non-sleep mode condition is set

by the MCU.

TXD DATA

LOAD Switch

The data driven onto the SWCAN bus is inverted from the

TXD terminal. A “1” driven on TXD will result in an undriven

(recessive) state (bus at near zero volts). When the TXD

terminal is low, the output goes to a driven state. The voltage

and waveshaping in the driven state is determined by the

levels on the MODE0 and MODE1 Pins (refer to Table 6).

Table 6. Mode Control Logic Levels

This switch is on in all operating modes unless a loss of

ground is detected. If this happens, the switch is opened and

the resistor normally attached to its terminal will no longer

pass current to or from the bus.

CNTL Output (33897/A/C ONLY)

This logic level signal is used to control a V_CCregulator.

When the output is low, the V_CCregulator is expected to

shutdown. This is normally used to shut down the MCU and

all the devices powered by V_CCwhen the IC is in sleep mode.

This is done to save power. When the part is taken out of the

sleep mode by the higher-than-normal bus voltage, this

terminal is asserted high and the V_CCregulator brings its

output up to the regulated level. This starts the MCU, which

controls the mode of the IC. The MCU must change the mode

signals to non-sleep mode levels in order to keep this

terminal from going low. There is a delay to allow the MCU to

fully wake up and take control after the high-voltage signaling

is removed before the level on this output returns low. After a

delay time, even if the bus is at high voltage, the IC will return

to sleep mode if both MODE Pins are low.

Logic Level

Operation

MODE0

MODE1

Sleep Mode

High Voltage Wake-Up Mode

High Speed Mode

Normal Mode

MODE CONTROL

The MODE Pins control the transmitter filtering and BUS

voltage and the IC sleep mode operation. Table 6 shows the

mode versus the logic levels on MODE0 and MODE1.

VBATT Input

The MODE0 and MODE1 Pins have a weak pulldown in

the IC so that in case the Pins are not driven, the device will

enter the sleep mode. This is usually the situation as the

MCU comes out of reset, before the driving signals have

been configured as outputs.

This power input is not reverse battery protected and

should use an external diode to protect it from damage owing

to reverse battery if this protection is desired. The voltage

drop of the diode must be taken into consideration when the

operating range of the system is being determined. This

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

FUNCTIONAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM COMPONENTS

diode is generally used to protect the entire module from

reverse battery and should be selected accordingly.

shown in the simplified application diagrams on page 17 of

this datasheet. The value of the capacitor should be adjusted

downward in direct proportion to the added capacitance of

the ESD or EMI circuits. The series resistance of the inductor

should be kept below 3.5 Ω to prevent its voltage drop from

significantly degrading system noise margins.

BUS I/O

This input/output may require electrostatic discharge

(ESD) and/or EMI external circuitry. A set of components is

FUNCTIONAL BLOCK DIAGRAM COMPONENTS

Timer OSC

TXD BUS DRVR

This circuit generates a 500 kHz signal to be used for

internal logic. It is the reference for some of the required

delays.

This circuit drives the BUS. It can drive it with the higher

voltage wake-up signals when enabled by the Mode Control

circuit. It can also provide waveshaping for reduced EMI or

not provide it for the higher data rate mode. The actual data

is received on TXD at CMOS logic levels, then translated by

this circuit to the necessary operating voltages.

Timers

This circuit contains the timing logic used to hold the CNTL

active for the required time after the conditions for sleep

mode have been met. It is also used to keep the TXD driver

active for a period of time after it has generated a passive

level on the bus.

Undervoltage Detect

This circuit monitors internal operating voltage to assure

proper operation of the part. If a low-voltage condition is

detected, it sends a signal to disable the BUS RCVR and

TXD BUS DRVR circuits. This prevents incorrect data from

being put on the bus or sent to the MCU.

Mode Control

This circuit contains the control logic for the various

operating modes and conditions required for the IC.

Load Switch

The LOAD switch provides a path for an external resistor

connected to the BUS to be connected to ground. When a

loss of ground is detected, this switch is opened to prevent

the current that would normally be flowing to the ground from

the module from going back through the load resistor and

raising the bus level. The circuit is opened when the voltage

between GND and VBATT becomes too low as would be the

case if module ground were lost.

BUS RCVR

This circuit translates the levels on the BUS terminal to a

CMOS level indicating the presence of a logic [0] or a

logic [1]. It also determines the presence of a high-voltage

wake-up (HVWU) signal that is passed to Mode Control and

Timers circuits. An analog filter is used to “de-glitch” the high-

voltage wake-up signal and prevent false exits from the sleep

mode.

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

BUS LOADING PARAMETERS

FUNCTIONAL BLOCK DIAGRAM COMPONENTS

BUS LOADING PARAMETERS

V_BATT

100 pF

1.0 kΩ

47 µH

33897

BUSMOD

BUS

6.49 kΩ

(n -1)

6.49 kΩ

= 100 pF + (n -1) 220 pF

NOM

LOAD

GND

Note: The letter “n” represents the number of nodes in the system.

Figure 7. Transmitter Delays in Normal and Transmit High-Voltage Wake-Up Modes

33897

BUS

6.49 kΩ

130 Ω

= (n) 220 pF

NOM

(n-1)

LOAD

GND

Note: The letter “n” represents the number of nodes in the system.

Figure 8. Transmitter Delays in Transmit High-Speed Mode

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

TYPICAL APPLICATIONS

The 33897/A/C can be used in applications where the

module includes a regulator that has the capability of going

into Sleep mode by having an Enable terminal. See Figure 9.

When the module’s regulator is in sleep mode, the module is

turned off. The module waits for a defined wake-up voltage

level on the bus. This wake-up voltage will activate the control

line, which enables the regulator and turns the module back

on. This 33897/A/C feature allows the module to be more

energy efficient since the current consumption is significantly

lowered when it goes into sleep mode.

Power

Source

Battery

100 nF

4.7 µF

Voltage

Regulator

100 pF

VBATT

CNTL

1.0 kΩ

47 µH

2.7 kΩ

10 kΩ

BUS

SWC BUS

TXD

47 pF

RXD

MODE0

LOAD

MCU

6.49 kΩ

MODE1

GND

33897/A/C

Figure 9. 33897/A/C Typical Application Schematic

The 33897B/D do not have a control terminal to enable the

module’s regulator. See Figure 10. The 33897B/D can be

used in applications where board space is limited and there

is no need for the module to have control over its regulator via

the transceiver.

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

TYPICAL APPLICATIONS

Battery

100 nF

100 pF

4.7 µF

VBATT

1.0 kΩ

47 µH

2.7 kΩ

10 kΩ

BUS

SWC BUS

TXD

47 pF

RXD

MODE0

LOAD

MCU

6.49 kΩ

MODE1

GND

33897B/D

Figure 10. 33897B/D Typical Application Schematic

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

Important: For the most current Package revision, visit

www.freescale.com and perform a Keyword Search on the

“98A” drawing number below.

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

PACKAGING

PACKAGE DIMENSIONS

D SUFFIX

EF (Pb-FREE) SUFFIX

14-TERMINAL SOIC NARROW BODY

PLASTIC PACKAGE

98ASB42565B

ISSUE H

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EF (Pb-FREE) SUFFIX

8-TERMINAL SOIC NARROW BODY

PLASTIC PACKAGE

98ASB42564B

ISSUE U

33897/A/B/C/D

Analog Integrated Circuit Device Data

Freescale Semiconductor

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

• Converted to Freescale format

5/2005

9.0

• Added A & B Versions

• Updated Device Variation Table, and Note “* Recommended device for all new designs”

• Added EF (Pb-Free) Devices, and higher soldering temperature

• Implemented Revision History page

8/2005

10.0

• Updated Simplified Application Diagrams

• Updated Typical Application Schematic

12/2005

1/2006

• Added 33897C and D versions and Timing Diagrams

11.0

12.0

• Updated Table 4, Static Electrical Characteristics - LOAD and BUS parameters

• Updated Ordering Information.

• Removed “Unless otherwise noted” from Static Electrical Characteristics & Dynamic

Electrical Characteristics table introductions

6/2006

8/2006

13.0

14.0

• Added Part Numbers MC33897TD and MC33897TEF to Ordering Information on Page 1.

• Added 33897T to Table 1, Device Variations on Page 3, Referencing Electrical Changes

per Errata MC33897TER, Revision 3 and specifying ESD variations

33897/A/

Analog Integrated Circuit Device Data

Freescale Semiconductor

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality

and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free

counterparts. For further information, see http://www.freescale.com or contact your

Freescale sales representative.

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Information in this document is provided solely to enable system and software

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MC33897

Rev. 14.0

8/2006

MC33897CEF [NXP]

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