MC33PF8100ERES_技术文档

PF8100; PF8200

12-channel power management integrated circuit for high

performance applications

Rev. 9.0 — 19 November 2019

Product data sheet

1 Overview

The PF8100/PF8200 is a power management integrated circuit (PMIC) designed for

high performance i.MX 8 and S32x based applications. It features seven high efficiency

buck converters and four linear regulators for powering the processor, memory and

miscellaneous peripherals.

Built-in one time programmable memory stores key startup configurations, drastically

reducing external components typically used to set output voltage and sequence of

external regulators. Regulator parameters are adjustable through high-speed I²C after

start up offering flexibility for different system states.

2 Features

• Up to seven high efficiency buck converters

• Four linear regulators with load switch options

• RTC supply and coin cell charger

• Watchdog timer/monitor

• Monitoring circuit to fit ASIL B safety level

• One time programmable device configuration

• 3.4 MHz I²C communication interface

• 56-pin 8 x 8 QFN package

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

3 Simplified application diagram

PF8x00

VSNVS

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

PF8x00

VSNVS

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

BUCK7

PF8x00

VSNVS

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

BUCK7

IMX8QXP

VDD_SNVS

IMX8QM

VDD_SNVS

VDD_MAIN

VDD_MEMC

GPU0

VIN:

2.7 V to

5.5 V

VIN:

2.7 V to

5.5 V

VIN:

2.7 V to

5.5 V

VDD_GPU

VDD_CPU (A35)

VDD_DDRIO

CPU1

(A72)

GPU1

CPU0 (A53)

VDD_DDRIO0

1.8 V I/O

VDD_MEMC

VDD_DDRIO1

3.3 V I/O

1.8 V I/O

(LV GPIO)

BUCK6

BUCK7

3.3 V I/O

(HV GPIO)

LDO1

LDO2

LDO3

LDO4

VDD_SCU

SDCARD0

2.5 V I/O

MISC

LDO1

LDO2

LDO3

LDO4

VDD_SCU

SDCARD0

3.3 V I/O

MISC

VDD_SIM

SDCARD1

2.5 V I/O

MISC

LDO1

LDO2

LDO3

LDO4

CONTROL

SIGNALS

CONTROL

SIGNALS

CONTROL

SIGNALS

INTERFACING AND

I C COMMUNICATIONS

INTERFACING AND

2

C COMMUNICATIONS

2

I

2

I

C

I

C

I C

SIMCARD

Ethernet

SIMCARD

SD Card

eMMC Supply

Ethernet

SD Card

eMMC Supply

SD Card

DRAM

LPDDR

Memory

LPDDR_0

Memory

LPDDR_1

Memory

MISCELLANEOUS

PERIPHERALS

MISCELLANEOUS

PERIPHERALS

aaa-028047

Figure 1.ꢀSimplified application diagram

4 Ordering information

Table 1.ꢀDevice options

Type

Package

Name

Description

Version

PF8100 (automotive)

PF8200 (automotive)

PF8100 (industrial)

HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package,

wettable flanks; 56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body

SOT684-21

(DD/SC)

HVQFN56

HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package,

56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body

SOT684-21

Table 2.ꢀOrdering information

Part number ^[1]

Target market

Automotive

NXP processor System comments

Safety grade

OTP ID

MC33PF8100A0ES

MC33PF8100CCES ^[2]

MC33PF8100CFES

MC33PF8100CHES

MC33PF8100EAES

n/a

Not programmed

LPDDR4 memory

DDR3L memory

QM

n/a

i.MX8QXP

i.MX8QM

LS1046A

http://www.nxp.com/MC33PF8100CCES-OTP-Report

http://www.nxp.com/MC33PF8100CFES-OTP-Report

http://www.nxp.com/MC33PF8100CHES-OTP-Report

http://www.nxp.com/MC33PF8100EAES-OTP-Report

DDR4 memory PMIC2

DDR4 Memory (VDDQ +

VTT)

MC33PF8100EPES

MC33PF8100EQES

MC33PF8100ERES

MC33PF8100FJES

MC33PF8100F3ES

MC34PF8100A0EP

MC34PF8100CCEP ^[2]

Automotive

Industrial

i.MX8QM

i.MX8QXP

LA1575

LPDDR4 memory PMIC1

LPDDR4 memory PMIC2

DDR4 memory PMIC1

LPDDR4 memory

QM

http://www.nxp.com/MC33PF8100EPES-OTP-Report

http://www.nxp.com/MC33PF8100EQES-OTP-Report

http://www.nxp.com/MC33PF8100ERES-OTP-Report

http://www.nxp.com/MC33PF8100FJES-OTP-Report

http://www.nxp.com/MC33PF8100F3ES-OTP-Report

n/a

LDDR4 memory

n/a

Not programmed

Industrial

i.MX8QXP

LPDDR4 memory

http://www.nxp.com/MC34PF8100CCEP-OTP-Report

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

2 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Part number ^[1]

Target market

Industrial

NXP processor System comments

Safety grade

QM

OTP ID

MC34PF8100CFEP

MC34PF8100CHEP

MC34PF8100EPEP

MC34PF8100EQEP

MC34PF8100EREP

MC34PF8100FJEP

MC34PF8100F3EP

MC33PF8200A0ES

MC33PF8200CXES

MC33PF8200D2ES

MC33PF8200DBES

MC33PF8200DEES

MC33PF8200DFES

MC33PF8200DHES

MC33PF8200EMES

MC33PF8200ESES

MC33PF8200ETES

i.MX8QXP

i.MX8QM

i.MX8QXP

LA1575

DDR3L memory

http://www.nxp.com/MC34PF8100CFEP-OTP-Report

http://www.nxp.com/MC34PF8100CHEP-OTP-Report

http://www.nxp.com/MC34PF8100EPEP-OTP-Report

http://www.nxp.com/MC34PF8100EQEP-OTP-Report

http://www.nxp.com/MC34PF8100EREP-OTP-Report

http://www.nxp.com/MC34PF8100FJEP-OTP-Report

http://www.nxp.com/MC34PF8100F3EP-OTP-Report

n/a

Industrial

DDR4 memory PMIC2

LPDDR4 memory PMIC1

LPDDR4 memory PMIC2

DDR4 memory PMIC1

LPDDR4 memory

QM

Industrial

QM

Industrial

QM

Industrial

QM

Industrial

QM

Industrial

LDDR4 memory

QM

Automotive

n/a

Not programmed

ASIL B

LS1043A

S32V234

i.MX8QM

i.MX8QXP

i.MX8QM

LS1043

LPDDR4 memory

http://www.nxp.com/MC33PF8200CXES-OTP-Report

http://www.nxp.com/MC33PF8200D2ES-OTP-Report

http://www.nxp.com/MC33PF8200DBES-OTP-Report

http://www.nxp.com/MC33PF8200DEES-OTP-Report

http://www.nxp.com/MC33PF8200DFES-OTP-Report

http://www.nxp.com/MC33PF8200DHES-OTP-Report

http://www.nxp.com/MC33PF8200EMES-OTP-Report

http://www.nxp.com/MC33PF8200ESES-OTP-Report

http://www.nxp.com/MC33PF8200ETES-OTP-Report

DDR3L memory 10 A core

LPDDR4 memory PMIC2

LPDDR4 memory

DDR3L memory

DDR4 memory PMIC2

Triple phase (VDD)

LPDDR4 memory PMIC1

DDR4 memory PMIC1

i.MX8QM

[1] To order parts in tape and reel, add the R2 suffix to the part number.

[2] Not recommended for new designs

5 Applications

• Automotive Infotainment

• High-end consumer and industrial

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

3 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

6 Internal block diagram

VDDIO SCL SDA

VDDOTP

RESETBMCU

WDI

PWRON

STANDBY TBBEN XINT INTB EWARNB PGOOD

FSOB

FAIL SAFE

CONTROL

XFAILB

SW1FB

SW1

VMON

MONITORING

BANDGAP

V

BG2

REF

SELEC.

WATCHDOG

TIMER

SW1IN

SW1LX

BANDGAP

COMPARATOR

V

BG2

EA

AND

DRIVER

SW1 DVS

AND MISC

REFERENCE

WD monitoring

V

BG1

REGULATION

BANDGAP

V1P5A

V1P5D

V1P5A

LDO

EPAD

DIGITAL CORE

AND

STATE MACHINE

SW2FB

SW2

VMON

V1P5D

LDO

REF

SELEC.

OTP MEMORY

SW2IN

SW2LX

COIN CELL

CHARGER

V

BG2

THERMAL MONITORING

/ SHUTDOWN

EA

AND

DRIVER

SW2 DVS

AND MISC

REFERENCE

LICELL

VSNVS

SW1VMON

PMIC

INTERNAL

MONITORS

10 x DIE

TEMPERATURE

MONITORS

EXTERNAL

CHANNEL

INPUT

VIN

OVLO

SW3FB

SW3

VMON

SW2VMON

SW3VMON

SW4VMON

SW5VMON

SW6VMON

SW7VMON

LDO1VMON

LDO2VMON

LDO3VMON

LDO4VMON

DGND

AGND

24 CHANNEL

ANALOG MUX

REF

SELEC.

SW3IN

SW3LX

PGOOD

MONITORS

AMUX

V

BG2

SYNCOUT

SYNCIN

EA

AND

DRIVER

SW3 DVS

AND MISC

REFERENCE

CLOCK MANAGEMENT

(100 kHz / 20 MHz / PLL /

DIGITAL MODULE)

MANUAL TUNING

SPREAD SPECTRUM

EXTERNAL CLOCK

SYNC

LDO1 VMON

LDO1

V

BG2

LDO1OUT

SW4FB

SW4

VMON

LDO12IN

REF

SELEC.

SW4IN

SW4LX

LDO2

V

BG2

LDO2OUT

SW6 DVS

AND MISC

REFERENCE

EA

AND

DRIVER

SW4 DVS

AND MISC

REFERENCE

LDO2 VMON

V

BG2

VSELECT

LDO2EN

÷ 2

REF

SELEC.

EPAD

V

BG2

VTT

REFERENCE

SELECTOR

SW5FB

SW5

VMON

LDO3 VMON

LDO3

SW6

VMON

SW7

VMON

SW7 MISC

REFERENCE

V

BG2

LDO30UT

LDO3IN

REF

SELEC.

V

BG2

EA

AND

DRIVER

EA

AND

DRIVER

SW5IN

SW5LX

LDO4IN

V

BG2

LDO4

EA

AND

DRIVER

SW5 DVS

LDO4OUT

AND MISC

REFERENCE

EPAD

LDO4 VMON

V

BG2

EPAD

SW6FB

SW6IN SW6LX

SW7FB

SW7IN SW7LX

Digital Signal(s)

Analog Reference(s)

20 MHz Clock/Derivative

100 kHz Clock/Derivative

aaa-028048

Figure 2.ꢀInternal block diagram

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

4 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

7 Pinning information

7.1 Pinning

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

DNC1

SW2FB

SW1FB

SW1IN

SW1LX

SW2LX

SW2IN

SW3IN

SW3LX

SW4LX

SW4IN

SW4FB

SW3FB

TBBEN

PGOOD

V1P5A

V1P5D

XINTB

3

4

5

SW7FB

SW7IN

SW7LX

SW6IN

SW6LX

SW5LX

SW5IN

SW5FB

SW6FB

FSOB

6

7

EPAD

8

9

10

11

12

13

14

aaa-028049

Figure 3.ꢀPin configuration for HVQFN56

7.2 Pin description

Table 3.ꢀHVQFN56 pin description

Pin number Symbol

Application description

Pin type

Min

—

Max

—

Units

1

DNC1

Do not connect

—

I

V

2

SW2FB

SW1FB

SW1IN

SW1LX

SW2LX

SW2IN

SW3IN

SW3LX

SW4LX

SW4IN

Buck 2 output voltage feedback

Buck 1 output voltage feedback

Buck 1 input supply

−0.3

6.0

3

I

4

I

5

Buck 1 switching node

Buck 2 switching node

Buck 2 input supply

O

I

6

7

8

Buck 3 input supply

I

9

Buck 3 switching node

Buck 4 switching node

Buck 4 input supply

O

I

10

11

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

5 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Pin number Symbol

Application description

Buck 4 output voltage feedback

Buck 3 output voltage feedback

Try Before Buy enable pin

LDO1 output

Pin type

Min

Max

6.0

2.0

6.0

0.3

5.5

6.0

Units

V

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SW4FB

SW3FB

TBBEN

LDO1OUT

VSELECT

LDO12IN

LDO2OUT

WDI

I

−0.3

-0.3

I

O

LDO2 voltage select input

LDO1 and LDO2 input supply

LDO2 output

I

O

Watchdog Input from MCU

Early warning to MCU

RESETBMCU open-drain output

PWRON input

I

EWARN

RESETBMCU

PWRON

STANDBY

INTB

O

I

STANDBY input

I

INTB open-drain output

LDO3 output

O

LDO3OUT

LDO3IN

LDO4IN

LDO4OUT

FSOB

O

LDO3 input supply

I

LDO4 input supply

I

LDO4 output

O

Safety output pin

O

SW6FB

SW5FB

SW5IN

Buck 6 output voltage feedback

Buck 5 output voltage feedback

Buck 5 input supply

I

SW5LX

SW6LX

SW6IN

Buck 5 switching node

Buck 6 switching node

Buck 6 input supply

O

I

SW7LX

SW7IN

Buck 7 switching node

Buck 7 input supply

O

−0.3

-0.3

I

SW7FB

XINTB

Buck 7 output voltage feedback

External interrupt input

1.6 V digital core supply

1.6 V analog core supply

PGOOD open-drain output

LDO2 enable pin

I

V1P5D

O

V1P5A

O

PGOOD

LDO2EN

XFAILB

DGND

O

I

External Synchronization pin

Digital ground

I/O

GND

−0.3

LICELL

VSNVS

SYNCIN

Coin cell input

I

VSNVS regulator output

O

I

External clock input pin for

synchronization

49

SYNCOUT

Clock out pin for external part

synchronization

O

−0.3

6.0

V

50

51

VIN

Main input voltage to PMIC

Analog ground

I

−0.3

6.0

0.3

V

AGND

GND

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

6 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Pin number Symbol

Application description

Analog multiplexer output

OTP selection input

Pin type

Min

Max

6.0

10

Units

52

53

54

AMUX

O

I

−0.3

V

VDDOTP

VDDIO

I/O supply voltage. Connect to

I

6.0

voltage rail between 1.6 V and 3.3 V

55

56

57

SCL

I²C clock signal

I²C data signal

I

−0.3

6.0

0.3

V

SDA

EPAD

I/O

GND

Exposed pad

Connect to ground

8 Absolute maximum ratings

Table 4.ꢀAbsolute maximum ratings

Symbol

Parameter

Min

−0.3

Typ

—

Max

Unit

[1]

VIN

Main input supply voltage

Regulator input supply voltage

6.0

V

SWxVIN,

LDOxVIN

—

VDDOTP

VLICELL

OTP programming input supply voltage

Coin cell voltage

−0.3

—

10

V

5.5

[1] Pin reliability may be affected if system voltages are above the maximum operating range of 5.5 V for extended periods of time. To minimize system

reliability impact, system must not operate above 5.5 V for more than 1800 sec over the lifetime of the device.

9 ESD ratings

Table 5.ꢀESD ratings

All ESD specifications are compliant with AEC-Q100 specification.

Symbol

V_ESD

Parameter

Min

Typ

Max

Unit

V

[1]

Human Body Model

—

2000

V_ESD

Charge Device Model

QFN package - all pins

V

—

500

100

I_LATCHUP

Latch-up current

mA

[1] ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),

robotic (CZAP = 4.0 pF)

10 Thermal characteristics

Table 6.ꢀThermal characteristics

Symbol

Parameter

Min

−40

—

Typ

—

Max

105

150

260

Unit

°C

[1]

T_A

Ambient operating temperature

Junction temperature

T_J

—

°C

T_ST

Storage temperature range

Peak package reflow temperature

—

°C

T_PPRT

—

°C

[1] All parameters are specified up to a junction temperature of 150 °C. All parameters are tested at T_Afrom −40°C to 105 °C to allow headroom for self

heating during operation. If higher T_Aoperation is required, proper thermal and loading consideration must be made to ensure device operation below the

maximum T_J= 150 °C.

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

7 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Table 7.ꢀQFN56 thermal resistance and package dissipation ratings

Symbol

Parameter

Min

Max

Unit

[1] [2]

R_θJA

Junction to Ambient Natural Convection

Single Layer Board (1s)

—

81

°C/W

R_θJA

Junction to Ambient Natural Convection

Four Layer Board (2s2p)

—

27

22

66

22

°C/W

R_θJA

Junction to Ambient Natural Convection

Eight Layer Board (2s6p)

[1] [3]

R_θJMA

Junction to Ambient (@200ft/min)

Single Layer Board (1s)

R_θJMA

Junction to Ambient (@200ft/min)

Four Layer Board (2s2p)

[4]

[5]

[6]

R_θJB

R_θJC

ΨJT

Junction to Board

—

11

0.6

1

°C/W

Junction to Case (bottom)

Junction to package (top)

[1] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

[2] Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.

[3] Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.

[4] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board

near the package.

[5] Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

[6] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

11 Operating conditions

Table 8.ꢀOperating conditions

Symbol

Parameter

Min

Typ

—

Max

5.5

Unit

V

V_IN

Main input supply voltage

LICELL input voltage range

UVDET

—

V_LICELL

—

4.2

V

12 General description

12.1 Features

The PF8100/PF8200 is a power management integrated circuit (PMIC) designed to be

the primary power management building block for NXP high-end multimedia application

processors from the i.MX 8 and S32x series. It is also capable of providing power

solution to the high end i.MX 6 series as well as several non-NXP processors.

• Buck regulators

– SW1, SW2, SW3, SW4, SW5, SW6: 0.4 V to 1.8 V; 2500 mA; 2 % accuracy

– SW7; 1.0 V to 4.1 V; 2500 mA; 2 % accuracy

– Dynamic voltage scaling on SW1, SW2, SW3, SW4, SW5, and SW6

– SW1, SW2 configurable as a dual phase regulator

– SW3, SW4 configurable as a dual phase regulator

– SW5, SW6 configurable as a dual phase regulator

– SW1, SW2 and SW3 configurable as a triple phase regulator with up to 7.5 A current

capability

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

8 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

– SW1, SW2, SW3 and SW4 configurable as a quad phase regulator with up to 10 A

current capability

– VTT termination mode on SW6

– Programmable current limit

– Spread-spectrum and manual tuning of switching frequency

• LDO regulators

– LDO1, 1.5 V to 5.0 V, 400 mA: 3 % accuracy with optional load switch mode

– LDO2, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode and

selectable hardware/software control

– LDO3, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode

– LDO4, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode

• RTC LDO/Switch supply from system supply or coin cell

– RTC supply VSNVS 1.8 V/3.0 V/3.3 V, 10 mA

– Battery backed memory including coin cell charger with programmable charge

current and voltage

• System features

– Fast PMIC startup

– Advanced state machine for seamless processor interface

– High speed I²C interface support (up to 3.4 MHz)

– PGOOD monitor

– User programmable standby and off modes

– Programmable soft start sequence and power down sequence

– Programmable regulator configuration

– 24 channel analog multiplexer for smart system monitoring/diagnostic

• OTP (One time programmable) memory for device configuration

• Monitoring circuit to fit ASIL B Safety level

– Independent voltage monitoring with programmable fault protection

– Advance thermal monitoring and protection

– External watchdog monitoring and programmable internal watchdog counter

– I²C CRC and write protection mechanism

– Analog built-in self-test (ABIST)

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

9 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

12.2 Functional block diagram

PF8x00

FUNCTIONAL BLOCK DIAGRAM

LDO1

BUCK1 (MASTER/SLAVE)

(1.5 V TO 5 V, 400 mA)

(0.4 V TO 1.8 V, 2.5 A)

LDO2

BUCK2 (MASTER/SLAVE)

(1.5 V TO 5 V, 400 mA)

(0.4 V TO 1.8 V, 2.5 A)

LDO3

BUCK3 (MASTER/SLAVE)

(1.5 V TO 5 V, 400 mA)

(0.4 V TO 1.8 V, 2.5 A)

LOGIC AND CONTROL

2

I C

WATCHDOG

MCU INTERFACE

REGULATOR CONTROL

FAULT DETECTION

FUNCTIONAL SAFETY

(ABIST)

LDO4

(1.5 V TO 5 V, 400 mA)

BUCK4 (MASTER/SLAVE)

(0.4 V TO 1.8 V, 2.5 A)

VSNVS (RTC SUPPLY)

BUCK5 (MASTER/SLAVE)

(1.8 V/3.0 V/3.3 V, 10 mA)

(0.4 V TO 1.8 V, 2.5 A)

24 CHANNEL AMUX

BUCK6 (MASTER/SLAVE)

(DIAGNOSTICS)

(VTT/0.4 V TO 1.8 V, 2.5 A)

OTP

BUCK7 (INDEPENDENT)

(FLEXIBLE CONFIGURATION)

(1.0 V TO 4.1 V, 2.5 A)

aaa-028050

Figure 4.ꢀFunctional block diagram

12.3 Power tree summary

The following table shows a summary of the voltage regulators in the PF8100/PF8200.

Table 9.ꢀVoltage supply summary

Regulator

Type

Input supply

Regulated output

range (V)

VOUT

programmable step

(mV)

IRATED (mA)

SW1

SW2

SW3

SW4

SW5

SW6

SW7

LDO1

Buck

SW1IN ^[1]

SW2IN ^[1]

SW3IN ^[1]

SW4IN ^[1]

SW5IN ^[1]

SW6IN ^[1]

SW7IN ^[1]

LDO12IN

0.4 V to 1.8 V

VTT/0.4 V to 1.8 V

1.0 V to 4.1 V

1.5 V to 5.0 V

6.25

—

2500

400

Buck

Linear (P-type)

—

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12-channel power management integrated circuit for high performance applications

Regulator

Type

Input supply

Regulated output

range (V)

VOUT

programmable step

(mV)

IRATED (mA)

LDO2

LDO3

LDO4

VSNVS

Linear (P-type)

LDO/Switch

LDO12IN

LDO3IN

1.5 V to 5.0 V

1.8 V/3.0 V/3.3 V

—

400

10

LDO4IN

VIN/LICELL

[1] Input supply for switching regulators must be capable to sink current to avoid overvoltage condition during the power down sequence of the device.

12.4 Device differences

Table 10.ꢀDevice differences

Description

PF8200

PF8100

Bits not available on PF8100

During the self-test, the device checks:

Available

Not available

AB_SWx_OV

• The high speed oscillator circuit is operating within

AB_SWx_UV

a maximum of 15 % tolerance

AB_LDOx_OVAB_LDOx_UV

STEST_NOK

• A CRC is performed on the mirror registers during

the self-test routine to ensure the integrity of the

registers before powering up

• ABIST test on all voltage monitors and toggling

signals

Fail-safe state: to lock down the system in case of

critical failures cycling the PMIC on/off

Available

Not available

FS_CNT[3:0]

OTP_FS_BYPASS

OTP_FS_MAX_CNT[3:0]

OTP_FS_OK_TIMER[2:0]

ABIST on demand

Not available

AB_RUN

Active safe state: allow the FSOB to remain asserted Available

as long as any of the non-safe conditions are present.

Allow the system to be set in safe state via the FSOB

pin.

FSOB_ASS_NOK

OTP_FSOB_ASS_EN (always 0)

Secure I²C write: I²C write procedure to modify

registers dedicated to safety features (I²C CRC is still

available)

Available

Not available

I2C_SECURE_EN

OTP_I2C_SECURE _EN (always 0)

RANDOM_GEN[7:0]

RANDOM_CHK[7:0]

13 State machine

The PF8100/PF8200 features a state of the art state machine for seamless processor

interface. The state machine handles the IC start up, provides fault monitoring and

reporting, and protects the IC and the system during fault conditions.

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12-channel power management integrated circuit for high performance applications

NO

VIN < UVDET

POWER

CRITICAL FAILURE

VIN > UVDET

V1P5D_POR

V1P5A_POR

Regulators off

FSOB = LOW*

VSNVS = On*

Fail-Safe

State

PF8200 only

PF8100 only

FS_CNT = FS_MAX_CNT

&& OTP_FS_BYPASS = 0

P

1. FS_CNT < FS_MAX_CNT

OR

OTP &

Trim Load

2. OTP_FS_BYPASS = 1

Fail-Safe

Transition

U

VSNVS On*

FS_CNT++

Regulators off

VSNVS = On*

FSOB = LOW*

R

LP_Off

J

BG_OK

OTP_OK

20 MHz_OK

Self-

Test

F

K

Fail self-test

(ST_COUNT < 3)

QPU_Off

2 ms

delay

L

Off Modes

TRIM_NOK = 0

&& OTP_NOK = 0

&& STEST_NOK = 0

System ON

O

Power up regulators

per OTP sequence

RESETBMCU = HIGH

Sys ON

Sequence

Power Up

Sequence

M

D

WD_Reset

E

PU_FAIL = True

Hard WD Reset

B

A

Power up

failure

Event

C

WD_FAIL_CNT++

RUN

Standby

Q

Turn-Off

POWER DOWN

Z

Fault

1. PWRON = 0

OR

Fault

POWER DOWN

S

2. PWRON H to L &&

PWRON = 0 > TRESET

OR

3. PMIC_OFF = 1 &&

500us_Shutdown_timer_expired

OR

1. WD_FAIL_CNT = WD_MAX_CNT

N

Turn-off

OR

2. PU_FAIL = True

OR

Power Down

3. FAULT_CNT = FAULT_MAX_CNT

4. VIN_OVLO_SDWN = 1 &&

VIN_OVLO detected

OR

4. Fault_Timer_Expired

OR

5. Tj > TSD

* Output is enabled/asserted if it is programmed to do

so by the OTP configuration

aaa-028051

Figure 5.ꢀState diagram

Table 11 lists the conditions for the different state machine transitions.

Table 11.ꢀState machine transition definition

Symbol

Description

Conditions

1. STANDBY = 0 && STANDBYINV bit = 0

2. STANDBY = 1 && STANDBYINV bit = 1

1. (STANDBY = 1 && STANDBYINV bit = 0

2. STANDBY = 0 && STANDBYINV bit = 1

1. Hard WD Reset event

Transition A

Standby to run

Transition B

Transition C

Run to standby

System on to WD reset

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12-channel power management integrated circuit for high performance applications

Symbol

Description

Conditions

Transition D

WD reset to system on

1. 30 µs delay passed && WD_EVENT_CNT < WD_MAX_

CNT

Transition E

WD reset to power down (fault)

1. WD_EVENT_CNT = WD_MAX_CNT

Transitory off state: device pass through LP_Off to Self-Test

to QPU_Off (no power up event present)

1. LPM_OFF = 1 && TBBEN = Low

Power up event from LP_Off state

2. LPM_OFF = 0

&& TBBEN = Low

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET< VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0

Transition J

LP_Off to self-test (PF8200 only)

Power up event from LP_Off state

3. LPM_OFF = 0

&& TBBEN = Low

&& (PWRON H to L && OTP_PWRON_MODE = 1

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0

Conditions: Transitory Off state to go into TBB Mode. Device

pass through LP_Off to Self-Test to QPU_Off (no power up

event present)

4. TBBEN = high (V1P5D)

1. Pass Self-Tests

Transition K

Self-test to QPU_Off (PF8200 only)

2. TBBEN = high (V1P5D)

Transitory Off state: device pass through LP_Off to QPU_Off

(no power up event present)

1. LPM_OFF = 1

&& TBBEN = Low

Power up event from LP_Off state

2. LPM_OFF = 0

&& TBBEN = Low

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET< VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

Transition F

LP_Off to QPU_Off (PF8100 only)

&& TRIM_NOK = 0 && OTP_NOK = 0

Power up event from LP_Off state

3. LPM_OFF =0

&& TBBEN = Low

&& (PWRON H to L && OTP_PWRON_MODE = 1)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD&& TRIM_NOK = 0 && OTP_NOK = 0

Transitory Off state: device pass through LP_Off to QPU_Off

(no power up event present)

4. TBBEN = High (V1P5D)

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12-channel power management integrated circuit for high performance applications

Symbol

Description

Conditions

Transitory QPU_Off state, power on event occurs from LP_

Off state, after self-test is passed, QPU_Off is just a transitory

state until power up sequence starts.

1. LPM_OFF = 0

&& TBBEN = Low

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

2. LPM_OFF = 1

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

3. LPM_OFF = 1

&& (PWRON H to L && OTP_PWRON_MODE = 1)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

Transition L

QPU_Off to power up

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

4. TBBEN = High

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

5. TBBEN = High

&& (PWRON H to L && OTP_PWRON_MODE = 1)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Transition M

Power up sequence to system on

1. RESETBMCU is released as part of the power up

sequence

Requested turn off event

1. OTP_PWRON_MODE = 0 && PWRON = 0

Requested turn off event

2. OTP_PWRON_MODE = 1 && (PWRON H to L &&

PWRON = low for t > TRESET)

Transition N

System on to power down (turn off)

Requested turn off event

3. PMIC_OFF = 1 && 500µs_Shutdown_Timer_Expired

Protective turn off event (no PMIC fault)

4. VIN_OVLO_SDWN=1 && VIN_OVLO detected for longer

than VIN_OVLO_DBNC time

Turn off event due to PMIC fault

1. Fault Timer expired

Turn off event due to PMIC fault

Transition Z

Transition O

System on to power down (fault)

Power down (turn off) to LP_Off

2. FAULT_CNT = FAULT_MAX_CNT

Turn off event due to PMIC fault

3. Thermal shutdown Tj > TSD

Requested turn off event moves directly to LP_Off

1. Power down sequences finished

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PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Symbol

Description

Conditions

Transition Q

Power up to power down (fault)

Power up failure

1. Failure during power up sequence

Transition R

Transition S

Self-test to fail-safe transition

1. Self-tests fail 3 times

&& TBBEN = low

Power down (fault) to fail-safe

transition

Turn off event due to a fault condition moves to fail-safe

transition

1. Power down sequence is finished

1. FS_CNT < FS_MAX_CNT

2. OTP_FS_BYPASS = 1

Transition U

Transition P

Fail-safe transition to LP_Off

Fail-safe transition to fail-safe state 1. FS_CNT = FS_MAX_CNT

(PF8200 only)

&& OTP_FS_BYPASS = 0

13.1 States description

13.1.1 OTP/TRIM load

Upon VIN application V1P5D and V1P5A regulators are turned on automatically. Once

the V1P5D and V1P5A cross their respective POR thresholds, the fuses (for trim and

OTP) are loaded into the mirror registers and into the functional I²C registers if configured

by the voltage on the VDDOTP pin.

The fuse circuits have a CRC error check routine which reports and protects against

register loading errors on the mirror registers. If a register loading error is detected, the

corresponding TRIM_NOK or OTP_NOK flag is asserted. See Section 17 "OTP/TBB and

default configurations" for details on handling fuse load errors.

If no fuse load errors are present, VSNVS is configured as indicated in the OTP

configuration bits, and the state machine moves to the LP_OFF state.

13.1.2 LP_Off state

The LP_Off state is a low power off mode selectable by the LPM_OFF bit during

the system on modes. By default, the LPM_OFF = 0 when VIN crosses the UVDET

threshold, therefore the state machine stops at the LP_Off state until a valid power up

event is present. When LPM_OFF= 1, the state machine transitions automatically to the

QPU_Off state if no power up event has been present and waits in the QPU_Off until a

valid power up event is present.

The selection of the LPM_OFF bit is based on whether prioritizing low quiescent current

(stay in LP_Off) or quick power up (move to QPU_Off state).

If a power up event is started in LP_Off state with LPM_OFF = 0 and a fuse loading error

is detected, the PF8100/PF8200 ignores the power up event and remains in the LP_Off

state to avoid any potential damage to the system.

To be in LP_Off state, it is necessary to have VIN present. If a valid LICELL is present,

but VIN is below the UVDET, the PF8100/PF8200 enters the coin cell state.

13.1.3 Self-test routine (PF8200 only)

When device transitions from the LP_Off state, it turns on all necessary internal circuits

as it moves into the self-test routine and performs a self-check routine to verify the

integrity of the internal circuits.

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12-channel power management integrated circuit for high performance applications

During the self-test routine the following blocks are verified:

• The high speed clock circuit is operating within a maximum of 15 % tolerance

• The output of the voltage generation bandgap and the monitoring bandgap are not

more than 4 % to 12 % apart from each other

• A CRC is performed on the mirror registers during the self-test routine, to ensure the

integrity of the registers before powering up

• ABIST test on all voltage monitors.

To allow for varying settling times for the internal bandgap and clocks, the self-test block

is executed up to 3 times (with 2.0 ms between each test) if a failure is encountered, the

state machine proceeds to the fail-safe transition.

A failure in the ABIST test is not interpreted as a self-test failure and it only sets the

corresponding ABIST flag for system information. The MCU is responsible for reading the

information and deciding whether it can continue with a safe operation. See Section 18.1

"System safety strategy" for more information about the functional safety strategy of

PF8200.

Upon a successful self-test, the state machine proceeds to the QPU_Off state.

13.1.4 QPU_Off state

The QPU_Off state is a higher power consumption off mode, in which all internal circuitry

required for a power on is biased and ready to start a power up sequence.

If LPM_OFF = 1 and no turn on event is present, the device stops at the QPU_Off state,

and waits until a valid turn on event is present.

In this state, if VDDIO supply is provided externally, the device is able to communicate

through I²C to access and modify the mirror registers in order to operate the device in

TBB mode or to program the OTP registers as described in Section 17 "OTP/TBB and

default configurations".

By default, the coin cell charger is disabled during the QPU_Off state when VIN crosses

the UVDET threshold, but it may be turned on or off in this state once it is programmed

by COINCHG_OFF during the system-on states.

If a power up event is started and any of the TRIM_NOK, OTP_NOK or STEST_NOK

flags are asserted, the device ignores the power up event and remains in the QPU_Off

state. See Section 17 "OTP/TBB and default configurations" for more details on

debugging a fuse loading failure.

Upon a power up event, the default configuration from OTP or hardwire is loaded into

their corresponding I²C functional register in the transition from QPU_Off to power up

state.

13.1.5 Power up sequence

During the power up sequence, the external regulators are turned on in a predefined

order as programmed by the default (OTP or hardwire) sequence.

If PGOOD is used as a GPO, it can also be set high as part of the power up sequence in

order to allow sequencing of any external supply/device controlled by the PGOOD pin.

The RESETBMCU is also programmed as part of the power up sequence, and it is used

as the condition to enter system-on states. The RESETBMCU may be released in the

middle of the power up sequence, in this case, the remaining supplies in the power up

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12-channel power management integrated circuit for high performance applications

continues to power up as the device is in the run state. See Section 14.5.2 "Power up

sequencing" for details.

13.1.6 System-on states

During the system-on states, the MCU is powered and out of reset and the system is fully

operational.

The system on is a virtual state composed by two modes of operations:

• Run state

• Standby state

Register to control the regulators output voltage, regulator enable, interrupt masks, and

other miscellaneous functions can be written to or read from the functional I²C register

map during the system-on states.

13.1.6.1 Run state

If the power up state is successfully completed, the state machine transitions to the run

state. In this state, RESETBMCU is released high, and the MCU is expected to boot up

and set up specific registers on the PMIC as required during the system boot up process.

The run mode is intended to be used as the normal mode of operation for the system.

Each regulator has specific registers to control its output voltage, operation mode and/or

enable/disable state during the run state.

By default, the VSWx_RUN[7:0] / VLDOx_RUN[3:0] registers are loaded with the data

stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively.

SW7 uses only one global register to configure the output voltage during run or

standby mode. Upon power up the VSW7[4:0] bits are loaded with the values of the

OTP_VSW7[4:0].

Upon power up, if the switching regulator is part of the power up sequence, the

SWx_RUN_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNCIN_EN = 1, default SWx_RUN_MODE at power up is always set to

PWM (0b01)

• When OTP_SYNCOUT_EN = 1, default SWx_RUN_MODE at power up is always set

to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_RUN_MODE at power up shall always set to

PWM (0b01)

• If none of the above conditions are met, the default value of the SWx_RUN_MODE bits

at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_RUN_MODE bits are set to

0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_RUN_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_RUN_MODE[1:0] bits are loaded with 0b00 (OFF mode).

Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to

1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the

LDOx_RUN_EN bit is set to 0 (disabled) by default.

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12-channel power management integrated circuit for high performance applications

In a typical system, each time the processor boots up (PMIC transitions from off mode

to run state), all output voltage configurations are reset to the default OTP configuration,

and the MCU should configure the PMIC to its desired usage in the application.

13.1.6.2 Standby state

The standby state is intended to be used as a low power (state retention) mode of

operation. In this state, the voltage regulators can be preset to a specific low power

configuration in order to reduce the power consumption during system’s sleep or state

retention modes of operations.

The standby state is entered when the STANDBY pin is pulled high or low as defined

by the STANBYINV bit. The STANDBY pin is pulled high/low by the MCU to enter/exit

system low power mode. See Section 14.9.2 "STANDBY" for detailed configuration of the

STANDBY pin.

Each regulator has specific registers to control its output voltage, operation mode and/or

enable/disable state during the standby state.

By default, the VSWx_STBY[7:0] / VLDOx_STBY[3:0] registers are loaded with the data

stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively.

Upon power up, if the switching regulator is part of the power up sequence, the

SWx_STBY_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNCIN_EN = 1, default SWx_STBY_MODE at power up is always set to

PWM (0b01)

• When OTP_SYNCOUT_EN = 1, default SWx_STBY_MODE at power up is always set

to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_STBY_MODE at power up shall always set to

PWM (0b01)

• If none of the conditions above are met, the default value of the SWx_STBY_MODE

bits at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_STBY_MODE bits are set to

0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_STBY_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_STBY_MODE[1:0] bits are loaded with 0b00 (OFF mode).

Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to

1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the

LDOx_RUN_EN bit is set to 0 (disabled) by default.

Upon power up, the standby registers are loaded with the same default OTP values as

the run mode. The MCU is expected to program the desired standby values during boot

up.

If any of the external regulators are disabled in the standby state, the power down

sequencer is engaged as described in Section 14.6.2 "Power down sequencing".

13.1.7 WD_Reset

When a hard watchdog reset is present, the state machine increments the

WD_EVENT_CNT[3:0] register and compares against the WD_MAX_CNT[3:0] register.

If WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0], the state machine detects a cyclic

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12-channel power management integrated circuit for high performance applications

watchdog failure, it powers down the external regulators and proceeds to the fail-safe

transition.

If WD_EVENT_CNT[3:0] < WD_MAX_CNT[3:0], the state machine performs a hard WD

reset.

A hard WD reset can be generated from either a transition in the WDI pin or a WD event

initiated by the internal watchdog counter as described in Section 15.11.2 "Watchdog

reset behaviors".

13.1.8 Power down state

During power down state, all regulators except VSNVS are disabled as configured in

the power down sequence. The power down sequence is programmable as defined in

Section 14.6.2 "Power down sequencing".

Two types of events may lead to the power down sequence:

• Non faulty turn off events: move directly into LP_Off state as soon as power down

sequence is finalized

• Turn off events due to a PMIC fault: move to the fail-safe transition as soon as the

power down sequence is finalized

13.1.9 Fail-safe transition

The fail-safe transition is entered if the PF8100/PF8200 initiates a turn off event due to a

PMIC fault.

If the fail-safe transition is entered, the PF8100/PF8200 provides four FAIL bits to

indicate the source of the failure:

• The PU_FAIL is set to 1 when the device shuts down due to a power up failure

• The WD_FAIL is set to 1 when the device shuts down due to a watchdog event counter

max out

• The REG_FAIL is set to 1 when the device shuts down due to a regulator failure (fault

counter maxed out or fault timer expired)

• The TSD_FAIL is set to 1 when the device shuts down due to a thermal shutdown

The value of the FAIL bits is retained as long as VIN > UVDET.

The MCU can read the FAIL bits during the system-on states in order to obtain

information about the previous failure and can clear them by writing a 1 to them, provided

the state machine is able to power up successfully after such failure.

In PF8200, when the state machine enters the fail-safe transition, a fail-safe counter is

compared and increased, if the FS_CNT[3:0] reaches the maximum count, the device

can be programmed to move directly to the fail-safe state to prevent a cyclic failure from

happening.

13.1.10 Fail-safe state (PF8200 only)

The fail-safe state works as a safety lock-down upon a critical device/system failure. It is

reached when the FS_CNT [3:0] = FS_MAX_CNT [3:0].

A bit is provided to enable or disable the device to enter the fail-safe state upon a cyclic

failure. When the OTP_FS_BYPASS = 1, the fail-safe bypass operation is enabled and

the device always move to the LP_Off state, regardless of the value of the FS_CNT[3:0].

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If the OTP_FS_BYPASS = 0, the fail-safe bypass is disabled, and the device moves to

the fail-safe state when the proper condition is met.

The maximum number of times the device can pass through the fail-safe

transition continuously prior to moving to a fail state is programmed by the

OTP_FS_MAX_CNT[3:0] bits. If the FS_MAX_CNT[3:0] = 0x00, the device moves into

the fail-safe state as soon as it fails for the very first time.

If the FSOB pin is programmed to assert upon a specific fault, the FSOB pin remains

asserted low during the fail-safe state if the corresponding fault is present when PF8200

reaches the fail-safe state.

The device can exit the fail-safe state only after a power cycle (VIN crossing UVDET)

event is present.

To avoid reaching the fail-safe state due to isolated fail-safe transition events,

the FS_CNT [3:0] is gradually decreased based on a fail-safe OK timer. The

OTP_FS_OK_TIME[2:0] bits select the default time configuration for the fail-safe OK

timer between 1 to 60 min.

Table 12.ꢀFail-safe OK timer configuration

OTP_FS_OK_TIME[2:0]

FS_CNT decrease period (min)

000

001

010

011

100

101

110

111

1

5

10

15

20

30

45

60

When the fail-safe OK timer reaches the configured time during the system-on states, the

state machine decreases the FS_CNT[3:0] bits by one and starts a new count until the

FS_CNT[3:0] is 0x00. The FS_CNT[3:0] may be manually cleared during the system on

state if the system wants to control this counter manually.

13.1.11 Coin cell state

When VIN is not present and LICELL pin has a valid voltage, the device is placed into

a coin cell state. In such state, only VSNVS remains on (if programmed to do so by the

OTP_VSNVSVOTL[1:0] bits) and is expected to provide power to the SNVS domain on

the MCU as long as the LICELL pin has a valid input suitable to supply the configured

VSNVS output voltage.

14 General device operation

14.1 UVDET

UVDET works as the main operation threshold for the PF8100/PF8200. Crossing UVDET

on the rising edge is a mandatory condition for OTP fuses to be loaded into the mirror

registers and allows the main PF8100/PF8200 operation.

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If VIN is below the UVDET threshold, the device remains in an unpowered state if no

valid LICELL is present, or in the LICELL mode if a valid LICELL voltage is present. A

200 mV hysteresis is implemented on the UVDET comparator to set the falling threshold.

Table 13.ꢀUVDET threshold

Symbol

UVDET

Parameter

Min

2.7

2.5

Typ

2.8

2.6

Max

2.9

Unit

V

Rising UVDET

Falling UVDET

2.7

V

14.2 VIN OVLO condition

The VIN_OVLO circuit monitors the main input supply of the PF8100/PF8200. When this

block is enabled, the PF8100/PF8200 monitors its input voltage and can be programmed

to react to an overvoltage in two ways:

• When the VIN_OVLO_SDWN = 0, the VIN_OVLO event triggers an OVLO interrupt but

does not turn off the device

• When the VIN_OVLO_SDWN = 1, the VIN_OVLO event initiates a power down

sequence

When the VIN_OVLO_EN = 0, the OVLO monitor is disabled and when the

VIN_OVLO_EN = 1, the OVLO monitor is enabled. The default configuration of the

VIN_OVLO_EN bit is set by the OTP_VIN_OVLO_EN bit in OTP. Likewise, the default

value of the VIN_OVLO_SDWN bit is set by the OTP_VIN_OVLO_SDWN upon power

up.

During a power up transition, if the OTP_VIN_OVLO_SDWN = 0 the device allows the

external regulators to come up and the PF8100/PF8200 announces the VIN_OVLO

condition through an interrupt. If the OTP_VIN_OVLO_SDWN = 1, the device stops the

power up sequence and returns to the corresponding off mode.

Debounce on the VIN_OVLO comparator is programmable to 10 µs, 100 µs or 1.0 ms, by

the VIN_OVLO_DBNC[1:0] bits. The default value for the VIN_OVLO debounce is set by

the OTP_VIN_OVLO_DBNC[1:0] bits upon power up.

Table 14.ꢀVIN_OVLO debounce configuration

VIN_OVLO_DBNC[1:0]

VIN OVLO debounce value (µs)

00

01

10

11

10

100

1000

Reserved

Table 15.ꢀVIN_OVLO specifications

Symbol

Parameter

Min

5.55

—

Typ

5.8

—

Max

6.0

Unit

V

[1]

VIN_OVLO

VIN overvoltage lockout rising

VIN_OVLO_HYS VIN overvoltage lockout hysteresis

200

mV

[1] Operating the device above the maximum VIN = 5.5 V for extended periods of time may degrade and cause permanent

damage to the device.

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14.3 IC startup timing with PWRON pulled up

The PF8100/PF8200 features a fast internal core power up sequence to fulfill system

power up timings of 5.0 ms or less, from power application until MCU is out of reset.

Such requirement needs a maximum ramp up time of 1.5 ms for VIN to cross the UVDET

threshold in the rising edge.

A maximum core biasing time of 1.5 ms from VIN crossing to UVDET until the beginning

of the power up sequence is ensured to allow up to 1.5 ms time frame for the voltage

regulators power up sequence.

Timing for the external regulators to start up is programmed by default in the OTP fuses.

The 5.0 ms power up timing requirement is only applicable when the PWRON pin

operates in level sensitive mode OTP_PWRON_MODE = 0, however turn on timing is

expected to be the same for both level or edge sensitive modes after the power on event

is present.

In applications using the VSNVS regulator, if VSNVS is required to reach regulation

before system regulators come up, the system should use the SEQ[7:0] bits to delay the

system regulators to allow enough time for VSNVS to reach regulation before the power

up sequence is started.

t

vin_rise

UVDET

VIN

1.6 V

V1P5D

t

stest_done

Final VSNVS Regulation

VSNVS

PWRON

t

first

STEST done

(internal signal)

Regulator Outputs

(enable signals)

t

reg2reset

RESETBMCU

Fuse

Load

Self

Test

aaa-028052

Figure 6.ꢀStartup with PWRON pulled up

Table 16.ꢀStartup timing requirements (PWRON pulled up)

Symbol

Parameter

Min

Typ

Max

Unit

t_{vin_rise}

Rise time of VIN from VPWR application to

UVDET (system dependent)

10

—

1500

µs

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Symbol

Parameter

Min

Typ

Max

Unit

t_{stest_done}

Time from VIN crossing UVDET to STEST_

done going high (self-test performed and

passed)

—

1.4

ms

t_first

Time from STEST_done to first slot of power up

sequence

—

100

1.5

µs

[1]

t_reg2reset

Time from first regulator enabled to

RESETBMCU asserted to guarantee 5.0 ms

PMIC boot up

ms

[1] External regulators power up sequence time (t_reg2reset) is programmed by OTP and may be longer than 1.5 ms. However, 1.5 ms is the maximum allowed

time to ensure power up within 5.0 ms.

14.4 IC startup timing with PWRON pulled low during VIN application

It is possible that PWRON is held low when VIN is applied. By default, LPM_OFF bit is

reset to 0 upon crossing UVDET, therefore the PF8100/PF8200 remains in the LP_Off

state as described in Section 13.1.2 "LP_Off state". In this scenario, quiescent current

in the LP_Off state is kept to a minimum. When PWRON goes high with LPM_OFF = 0,

the PMIC startup is expected to take longer, since it has to enable most of the internal

circuits and perform the self-test before starting a power up sequence.

Figure 7 shows startup timing with LPM_OFF = 0.

t

vin_rise

UVDET

1.6 V

VIN

V1P5D

Final Regulation

VSNVS

PWRON

t

pwrup_lpm

t

fuseLoad

Fuse load done

(internal signal)

t

first

STEST done

(internal signal)

Regulator Outputs

RESETBMCU

t

reg2reset

Fuse

Load

Self-Test

LP_OFF State

aaa-028053

Figure 7.ꢀStartup with PWRON driven high externally and bit LPM_OFF = 0

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Table 17.ꢀStartup with PWRON driven high externally and LPM_OFF = 0

Symbol

Parameter

Min

Typ

Max

Unit

t_{vin_rise}

Rise time of VIN from VPWR application to

UVDET (system dependent)

10

—

1500

µs

t_fuseload

t_{pwrup_lpm}

t_first

Time from VIN crossing UVDET to Fuse_Load_

done (fuse loaded correctly)

—

600

700

100

1.5

µs

ms

Time from PWRON going high to the STEST_

done (self-test performed and passed)

Time from STEST_done to first slot of power up

sequence

[1]

t_reg2reset

Time from first regulator enabled to

RESETBMCU asserted to guarantee 5.0 ms

PMIC boot up

[1] External regulators power up sequence time (t_reg2reset) is programmed by OTP and may be longer than 1.5 ms.

14.5 Power up

14.5.1 Power up events

Upon a power cycle (VIN > UVDET), the LPM_OFF bit is reset to 0, therefore the device

moves to the LP_Off state by default. The actual value of the LPM_OFF bit can be

changed during the run mode and is maintained until VIN crosses the UVDET threshold.

In either one of the off modes, the PF8100/PF8200 can be enabled by the following

power up events:

1. When OTP_PWRON_MODE = 0, PWRON pin is pulled high.

2. When OTP_PWRON_MODE = 1, PWRON pin experiences a high to low transition

and remains low for as long as the PWRON_DBNC timer.

A power up event is valid only if:

• VIN > UVDET

• VIN < VIN_OVLO (unless the OVLO is disabled or OTP_VIN_OVLO_SDWN = 0)

• Tj < thermal shutdown threshold

• TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

14.5.2 Power up sequencing

The power up sequencer controls the time and order in which the voltage regulators and

other controlling I/O are enabled when going from the off mode into the run state.

The OTP_SEQ_TBASE[1:0] bits set the default time base for the power up and power

down sequencer.

The SEQ_TBASE[1:0] bits can be modified during the system-on states in order to

change the sequencer timing during run/standby transitions as well as the power down

sequence.

Table 18.ꢀPower up time base register

OTP bits

Functional bits

Sequencer time base

(µs)

OTP_SEQ_TBASE[1:0]

SEQ_TBASE[1:0]

00

01

00

01

30

120

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OTP bits

Functional bits

Sequencer time base

(µs)

OTP_SEQ_TBASE[1:0]

SEQ_TBASE[1:0]

10

11

10

11

250

500

The power up sequence may include any of the following:

• Switching regulators

• LDO Regulators

• PGOOD pin if programmed as a GPO

• RESETBMCU

The default sequence slot for each one of these signals is programmed via the OTP

configuration registers. And they can be modified in the functional I²C register map to

change the order in which the sequencer behaves during the run/standby transitions as

well as the power down sequence.

The _SEQ[7:0] bits set the regulator/pin sequence from 0 to 254. Sequence code 0x00

indicates that the particular output is not part of the startup sequence and remains in off

(in case of a regulator) or remains low/disabled (in case of PGOOD pin used as a GPO).

Table 19.ꢀPower up sequence registers

OTP bits

Functional bits

Sequence slot

Startup time

(µs)

OTP_SWx_SEQ[7:0]/

OTP_LDOx_SEQ[7:0]/

OTP_PGOOD_SEQ[7:0]/

OTP_RESETBMCU_SEQ[7:0]

SWx_SEQ[7:0]/

LDOx_SEQ[7:0]/

PGOOD_SEQ[7:0]/

RESETBMCU_SEQ[7:0]

00000000

00000001

00000000

00000001

Off

0

Off

SLOT0

(right after PWRON event is

valid)

00000010

1

SEQ_TBASE x SLOT1

.

11111111

254

SEQ_TBASE x SLOT254

If RESETBMCU is not programmed in the OTP sequence, it will be enabled by default

after the last regulator programmed in the power up sequence.

When the _SEQ[7:0] bits of all regulators and PGOOD used as a GPIO are set to 0x00

(off) and a power on event is present, the device moves to the run state in slave mode.

In this mode, the device is enabled without any voltage regulator or GPO enabled. If the

RESETBMCU is not programed in a power up sequence slot, it is released when the

device enters the run state.

The slave mode is a special case of the power up sequence to address the scenario

where the PF8100/PF8200 is working as a slave PMIC, and supplies are meant to be

enabled by the MCU during the system operation. In this scenario, if RESETBMCU is

used, it is connected to the master RESETBMCU pin.

The PWRUP_I interrupt bit is asserted at the end of the power up sequence when the

time slot of the last regulator in the sequence has ended.

Figure 8 provides an example of the power up/down sequence coming from the off

modes.

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SW1

LDO1

SW5

RESETBMCU

System On

SW2

LDO2

INTB

Power up Seq.

Off to Run

Power down Seq.

Run to Off

End of

Start of

End of

PWRUP

PWRDN

aaa-028054

Figure 8.ꢀPower up/down sequence between off and system-on states

When transitioning from standby mode to run mode, the power up sequencer is activated

only if any of the external regulators is re-enabled during this transition. If none of the

regulators toggle from off to on and only voltage changes are being performed when

entering or exiting standby mode, the changes for the voltage regulators are made

simultaneously rather than going through the power up sequencer.

Figure 9 shows an example of the power up/down sequence when transitioning between

run and standby modes.

SW1

SW2

SW5

LDO1

LDO2

RESETBMCU

INTB

Run

Mode

PWRDN Sequence

from Run to STBY

STBY

Mode

PWRUP Sequence

from STBY to Run

PWRDN_l

PWRUP_l

aaa-028055

Figure 9.ꢀPower up/down sequence between run and standby

The PWRUP_I interrupt is set while transitioning from standby to run, even if the

sequencer is not used. This is used to indicate that the transition is complete and device

is ready to perform proper operation.

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14.6 Power down

14.6.1 Turn off events

Turn off events may be requested by the MCU (non-PMIC fault related) or due to a

critical failure of the PMIC (hard fault condition).

The following are considered non-PMIC failure turn off events:

1. When OTP_PWRON_MODE = 0, the device starts a power down sequence when the

PWRON pin is pulled low.

2. When OTP_PWRON_MODE = 1, the device starts a power down sequence when

the PWRON pin sees a transition from high to low and remains low for longer than

TRESET.

3. When bit PMIC_OFF is set to 1, the device starts a 500 µs shutdown timer. When the

shutdown timer is started, the PF8100/PF8200 sets the SDWN_I interrupt and asserts

the INTB pin provided it is not masked. At this point, the MCU can read the interrupt

and decide whether to continue with the turn off event or stop it in case it was sent by

mistake.

If the SDWN_I bit is cleared before the 500 µs shutdown timer is expired, the

shutdown request is cancelled and the shutdown timer is reset; otherwise, if the

shutdown timer is expired, the PF8100/PF8200 starts a power down sequence.

The PMIC_OFF bit self-clears after SDWN_I flag is cleared.

4. When VIN_OVLO_EN = 1 and VIN_OVLO_SDWN = 1, and a VIN_OVLO event is

present.

Turn off events due to a hard fault condition:

1. If an OV, UV or ILIM condition is present long enough for the fault timer to expire.

2. In the event that an OV, UV or ILIM condition appears and clears cyclically, and the

FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0].

3. If the watchdog fail counter is overflown, that is WD_EVENT_CNT = WD_MAX_CNT.

4. When Tj crosses the thermal shutdown threshold as the temperature rises.

When the PF8100/PF8200 experience a turn off event due to a hard fault condition, the

devices pass through the fail-safe transition after regulators have been powered down.

14.6.2 Power down sequencing

During a power down sequence, output voltage regulators can be turned off in two

different modes as defined by the PWRDWN_MODE bit.

1. When PWRDWN_MODE = 0, the regulators power down in sequential mode.

2. When PWRDWN_MODE = 1, the regulators power down by groups.

During transition from run to standby, the power down sequencer is activated in the

corresponding mode. If any of the external regulators are turned off in the standby

configuration. If external regulators are not turned off during this transition, the power

down sequencer is bypassed and the transition happens at once (any associated DVS

transitions could still take time).

The PWRDN_I interrupt is set at the end of the transition from run to standby when the

last regulator has reached its final state, even if external regulators are not turned off

during this transition.

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14.6.2.1 Sequential power down

When the device is set to the sequential power down, it uses the same _SEQ[7:0]

registers as the power up sequence to power down in reverse order.

All regulators with the _SEQ[7:0] bits set to 0x00, power down immediately and the

remaining regulators power down one OTP_SEQ_TBASE[1:0] delay after, in reverse

order as defined in the _SEQ[7:0] bits.

If PGOOD pin is used as a GPO, it is de-asserted as part of the power down sequence

as indicated by the PGOOD_SEQ[7:0] bits.

If the MCU requires a different power down sequence, it can change the values of the

SEQ_TBASE[1:0] and the _SEQ[7:0] bits during the system-on states.

When the state machine pass through any of the off modes, the contents of the

SEQ_TBASE[1:0] and _SEQ[7:0] bits are reloaded with the corresponding mirror register

(OTP) values before it starts the next power up sequence.

14.6.2.2 Group power down

When the device is configured to power down in groups, the regulators are assigned to a

specific power down group. All regulators assigned to the same group are disabled at the

same time when the corresponding group is due to be disabled.

Power down groups shut down in decreasing order starting from the lowest hierarchy

group with a regulator shutting down (for instance, Group 4 being the lowest hierarchy

and Group 1 the highest hierarchy group). If no regulators are set to the lowest hierarchy

group, the power down sequence timer starts off the next available group that contains a

regulator to power down.

Each regulator has its own _PDGRP[1:0] bits to set the power down group it belongs to

as shown in Table 20.

Table 20.ꢀPower down regulator group bits

OTP_SWx_PDGRP[1:0]

OTP_LDOx_PDGRP[1:0]

OTP_PGOOD_PDGRP[1:0]

SWx_PDGRP[1:0]

LDOx_PDGRP[1:0]

PGOOD_PDGRP[1:0]

Description

OTP_RESETBMCU_PDGRP[1:0] RESETBMCU_PDGRP[1:0]

00

01

10

11

00

01

10

11

Regulator belongs to Group 4

Regulator belongs to Group 3

Regulator belongs to Group 2

Regulator belongs to Group 1

If PGOOD pin is used as a GPO, the PGOOD_PDGRP[1:0] is used to turn off the

PGOOD pin in a specific group during the power down sequence. If PGOOD pin is used

in power good mode, it is recommended that the OTP_PGOOD_PDGRP bits are set

to 11 to ensure the group power down sequencer does not detect these bits as part of

Group 4.

Each one of power down groups have programmable time delay registers to set the time

delay after the regulators in this group have been turned off, and the next group can start

to power down.

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Table 21.ꢀPower down counter delay

OTP bits

Functional bits

GRPx_DLY[1:0]

Power down delay

(µs)

OTP_GRPx_DLY[1:0]

00

01

10

11

00

01

10

11

120

250

500

1000

If RESETBMCU is required to be asserted first before any of the external regulators from

the corresponding group, the RESETBMCU_DLY provides a selectable delay to disable

the regulators after RESETBMCU is asserted.

Table 22.ꢀProgrammable delay after RESETBMCU is asserted

OTP bits

Functional bits

RESETBMCU delay

(µs)

OTP_RESETBMCU_DLY[1:0]

RESETBMCU_DLY[1:0]

00

01

10

11

00

01

10

11

No delay

10

100

500

If RESETBMCU_DLY is set to 0x00, all regulators in the same power down group as

RESETBMCU is disabled at the same time RESETBMCU is asserted.

Figure 10 shows an example of the power down sequence when PWRDWN_MODE = 1.

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PDWN_GRP1

GPR1_DLY = 120 µs

SW1

PDWN_GRP2

GPR2_DLY = 120 µs

PDWN_GRP3

GPR3_DLY = 120 µs

LDO2

PDWN_GRP4

NA

SW2

SW3

SW4

LDO1

LDO3

LDO4

RESETBMCU_DLY = 10 µS

PWRON

LDO2

LDO3

LDO4

SW2

SW3

SW4

RESETBMCU

SW1

LDO1

120 µs

GRP3_DLY

120 µs

GRP2_DLY

10 µs

120 µs

GRP1_DLY

aaa-028056

Figure 10.ꢀGroup power down sequence example

14.6.2.3 Power down delay

After a power down sequence is started, the PWRON pin shall be masked until the

sequence is finished and the programmable power down delay is reached, then the

device can power up again if a power-up event is present. The power down delay time

can be programed on OTP via the OTP_PD_SEQ_DLY[1:0] bits.

Table 23.ꢀPower down delay selection

OTP_PD_SEQ_DLY[1:0]

Delay after power down sequence

00

01

10

11

No delay

1.5 ms

5.0 ms

10 ms

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power down delay

system on

state

power down

sequence

OFF state

shutdown

event

PWRON

regulator

outputs

VSNVS

RESETBMCU

power down

sequence

power down

delay

aaa-029211

Figure 11.ꢀPower down delay

The default value of the OTP_PD_SEQ_DLY[1:0] bits on an unprogrammed OTP device

shall be 00.

14.7 Fault detection

Three types of faults are monitored per regulator: UV, OV and ILIM. Faults are monitored

during power up sequence, run, standby and WD reset states. A fault event is notified to

the MCU through the INTB pin if the corresponding fault is not masked.

The fault configuration registers are reset to their default value after the power up

sequences, and system must configure them as required during the boot-up process via

I²C commands.

For each type of fault, there is an I²C bit that is used to select whether the regulator is

kept enabled or disabled when the corresponding regulator experience a fault event.

SWx_ILIM_STATE / LDOx_ILIM_STATE

• 0 = regulator disable upon an ILIM fault event

• 1 = regulator remains on upon an ILIM fault event

SWx_OV_STATE / LDOx_OV_STATE

• 0 = regulator disable upon an OV fault event

• 1 = regulator remains on upon an OV fault event

SWx_UV_STATE / LDOx_UV_STATE

• 0 = regulator disable upon an UV fault event

• 1 = regulator remains on upon an UV fault event

The following table lists the functional bits associated with enabling/disabling the external

regulators when they experience a fault.

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Table 24.ꢀRegulator control during fault event bits

Regulator

Bit to disable the

regulator during current regulator during

limit

Bit to disable the

regulator during

overvoltage

undervoltage

SW1

SW2

SW3

SW4

SW5

SW6

SW7

LDO1

LDO2

LDO3

LDO4

SW1_ILIM_STATE

SW2_ILIM_STATE

SW3_ILIM_STATE

SW4_ILIM_STATE

SW5_ILIM_STATE

SW6_ILIM_STATE

SW7_ILIM_STATE

LDO1_ILIM_STATE

LDO2_ILIM_STATE

LDO3_ILIM_STATE

LDO4_ILIM_STATE

SW1_UV_STATE

SW2_UV_STATE

SW3_UV_STATE

SW4_UV_STATE

SW5_UV_STATE

SW6_UV_STATE

SW7_UV_STATE

LDO1_UV_STATE

LDO2_UV_STATE

LDO3_UV_STATE

LDO4_UV_STATE

SW1_OV_STATE

SW2_OV_STATE

SW3_OV_STATE

SW4_OV_STATE

SW5_OV_STATE

SW6_OV_STATE

SW7_OV_STATE

LDO1_OV_STATE

LDO2_OV_STATE

LDO3_OV_STATE

LDO4_OV_STATE

ILIM faults are debounced for 1.0 ms before they can be detected as a fault condition. If

the regulator is programed to disable upon an ILIM condition, the regulator turns off as

soon as the ILIM condition is detected.

OV/UV faults are debounced as programmed by the OV_DB and UV_DB registers,

before they are detected as a fault condition. If the regulator is programmed to disable

upon an OV or UV, the regulator will turn off if the fault persist for longer than 300 µs after

the OV/UV fault has been detected.

RegX_STATE = 0 && Regx_FLT_REN = 0

OV/UV fault

REGx

REGx_EN

RegX_PG

PGOOD

User

Enabled

300 µs

RegX_STATE = 0 && Regx_FLT_REN = 0

ILIM fault

REGx

ILIM

I_REGx

REGx_EN

User

Enabled

aaa-028057

1 ms

Figure 12.ꢀRegulator turned off with RegX_STATE = 0 and FLT_REN = 0

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

When a regulator is programmed to disable upon an OV, UV, or ILIM fault, a bit is

provided to decide whether a regulator can return to its previous configuration or remain

disabled when the fault condition is cleared.

SWx_FLT_REN / LDOx_FLT_REN

• 0 = regulator remains disabled after the fault condition is cleared or no longer present

• 1 = regulator returns to its previous state if fault condition is cleared

If a regulator is programmed to remain disabled after clearing the fault condition,

the MCU can turn it back on during the system on states by toggling off and on the

corresponding mode/enable bits.

When the bit SWx_FLT_REN = 1, if a regulator is programmed to turn off upon an OV,

UV or ILIM condition, the regulator returns to its previous state 500 µs after the fault

condition is cleared. If the regulator is programmed to turn off upon an ILIM condition, the

device may take up to 1.0 ms to debounce the ILIM condition removal, in addition to the

500 µs wait period to re-enable the regulator.

RegX_STATE = 0 && FLT_REN = 1

OV/UV fault

REGx

REGx_EN

REGx_PG

PGOOD

300 µs

500 µs

RegX_STATE = 0 && FLT_REN = 1

ILIM fault

REGx

I_REGx

ILIM

REGx_EN

1 ms

1.5 ms

1 ms

1.5 ms

aaa-028058

Figure 13.ꢀRegulator turned off with RegX_STATE = 0 and FLT_REN = 1

When the LDO2 is controlled by hardware using the LDO2EN pin and programmed to

turn off upon an OV, UV or ILIM fault, the LDO2_FLT_REN bit still controls whether the

regulator returns to its previous state or not regardless the state of the LDO2EN pin.

If LDO2 controlled by LDO2EN pin is instructed to remain disabled by the

LDO2_FLT_REN bit, it recovers hardware control by modifying the LDO2_EN bits in the

I²C register maps. See Section 14.9.10 "LDO2EN" for details on hardware control of

LDO2 regulator.

To avoid fault cycling, a global fault counter is provided. Each time any of the external

regulators encounter a fault event, the PF8100/PF8200 compares the value of the

FAULT_CNT[3:0] against the FAULT_MAX_CNT, and if it not equal, it increments the

FAULT_CNT[3:0] and proceeds with the fault protection mechanism.

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

The processor is expected to read the counter value and reset it when the faults have

been cleared and the device returns to a normal operation. If the processor does not

reset the fault counter and it equals the FAULT_MAX_CNT[3:0] value, the state machine

initiates a power down sequence.

The default value of the FAULT_MAX_CNT[3:0] is loaded from the

OTP_FAULT_MAX_CNT[3:0] bits during the power up sequence.

When the FAULT_MAX_CNT[3:0] is set to 0x00, the system disables the turn-off events

due to a Fault Counter maxing out.

When a regulator experiences a fault event, a fault timer is started. While this timer

is in progress, the expectation is that the processor takes actions to clear the fault.

For example, it could reduce its load in the event of a current limit fault, or turn off the

regulator in the event of an overvoltage fault.

If the fault clears before the timer expires, the state machine resumes the normal

operation, and the fault timer gets reset. If the fault does not clear before the timer

expires, a power down sequence is initiated to turn off the voltage regulators.

The default value of the fault timer is set by the OTP_TIMER_FAULT[3:0], however the

duration of the fault timer can be changed during the system on states by modifying the

TIMER_FAULT[3:0] bits in the I²C registers.

Table 25.ꢀFault timer register configuration

OTP bits

Functional bits

Timer value

(ms)

OTP_TIMER_FAULT [3:0]

TIMER_FAULT [3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

4

8

16

32

64

128

256

512

1024

2056

Reserved

Disabled

Each voltage regulator has a dedicated I²C bit that is used to bypass the fault detection

mechanism for each specific fault.

SWx_ILIM_BYPASS / LDOx_ILIM_BYPASS

• 0 = ILIM protection enabled

• 1 = ILIM fault bypassed

SWx_OV_BYPASS / LDOx_OV_BYPASS

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

• 0 = OV protection enabled

• 1 = OV fault bypassed

SWx_UV_BYPASS / LDOx_UV_BYPASS

• 0 = UV protection enabled

• 1 = UV fault bypassed

Table 26.ꢀFault bypass bits

Regulator

Bit to bypass a current

limit

Bit to bypass an

undervoltage

Bit to bypass an

overvoltage

SW1

SW2

SW3

SW4

SW5

SW6

SW7

LDO1

LDO2

LDO3

LDO4

SW1_ILIM_BYPASS

SW2_ILIM_BYPASS

SW3_ILIM_BYPASS

SW4_ILIM_BYPASS

SW5_ILIM_BYPASS

SW6_ILIM_BYPASS

SW7_ILIM_BYPASS

LDO1_ILIM_BYPASS

LDO2_ILIM_BYPASS

LDO3_ILIM_BYPASS

LDO4_ILIM_BYPASS

SW1_UV_BYPASS

SW2_UV_BYPASS

SW3_UV_BYPASS

SW4_UV_BYPASS

SW5_UV_BYPASS

SW6_UV_BYPASS

SW7_UV_BYPASS

LDO1_UV_BYPASS

LDO2_UV_BYPASS

LDO3_UV_BYPASS

LDO4_UV_BYPASS

SW1_OV_BYPASS

SW2_OV_BYPASS

SW3_OV_BYPASS

SW4_OV_BYPASS

SW5_OV_BYPASS

SW6_OV_BYPASS

SW7_OV_BYPASS

LDO1_OV_BYPASS

LDO2_OV_BYPASS

LDO3_OV_BYPASS

LDO4_OV_BYPASS

The default value of the OV_BYPASS, UV_BYPASS and ILIM_BYPASS bits upon power

up can be configured by their corresponding OTP bits.

Bypassing the fault detection prevents the specific fault from starting any of the protective

mechanism:

• Increment the counter

• Start the Fault timer

• Disable the regulator if the corresponding _STATE bit is 0

• OV / UV condition asserting the PGOOD pin low

When a fault is bypassed, the corresponding interrupt bit is still set and the INTB pin is

asserted, provided the interrupt has not been masked.

14.7.1 Fault monitoring during power up state

An OTP bit is provided to select whether the output of the switching regulators is

verified during the power up sequence and used as a gating condition to release the

RESETBMCU or not.

• When OTP_PG_CHECK = 0, the output voltage of the regulators is not checked during

the power up sequence and power good indication is not required to de-assert the

RESETBMCU. In this scenario, the OV/UV monitors are masked until RESETBMCU

is released; after this event, all regulators may start checking for faults after their

corresponding blanking period.

• When OTP_PG_CHECK = 1, the output voltage of the regulators is verified during

the power up sequence and a power good condition is required to release the

RESETBMCU.

PF8100_PF8200

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Product data sheet

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

When OTP_PG_CHECK = 1, OV and UV faults during the power up sequence are

reported based on the internal PG (Power Good) signals of the corresponding external

regulator. The PGOOD pin can be used as an external indicator of an OV/UV failure

when the RESETBMCU is ready to be de-asserted and it has been configured in the

PGOOD mode. See Section 14.9.8 "PGOOD" for details on PGOOD pin operation and

configuration.

Regardless of the PGOOD pin configured as a power good indicator or not, the PF8100/

PF8200 masks the detection of an OV/UV failure until RESETBMCU is ready to be

released, at this point the device checks for any OV/UV condition for the regulators

turned on so far. If all regulators powered up before or in the same sequence slot

than RESETBMCU are in regulation, RESETBMCU is de-asserted and the power up

sequence can continue as shown in Figure 14.

RESETBMCU

PGOOD

(optional)

REG4_PG

REG4

REG3_PG

REG3

REG2_PG

REG2

REG1_PG

REG1

SYSTEM ON

aaa-028059

Figure 14.ꢀCorrect power up (no fault during power up)

If any of the regulators are powered up before RESETBMCU is out of regulator,

RESETBMCU is not de-asserted and the power up sequence is stopped for up to 2.0 ms.

If the fault is cleared and all internal PG signals are asserted within the 2.0 ms timer,

RESETBMCU is de-asserted and the power up sequence continues where it stopped as

shown in Figure 15.

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

RESETBMCU

PGOOD

(optional)

REG4_PG

REG4

REG3_PG

REG3

REG2_PG

REG2

REG1_PG

REG1

SYSTEM ON

Regulator

Recovery

< 2 ms

aaa-028060

Figure 15.ꢀPower up sequencer with a temporary failure

If the faulty condition is not cleared within the 2.0 ms timer, the power up sequence is

aborted and the PF8100/PF8200 turn off all voltage regulators enabled so far as shown

in Figure 16.

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

RESETBMCU

PGOOD

(optional)

REG4_PG

REG4

REG3_PG

REG3

REG2_PG

REG2

REG1_PG

REG1

2 ms (max)

Recovery

Reg Power down

aaa-028061

Figure 16.ꢀPower up sequencer aborted as fault persists for longer than 2.0 ms

Supplies enabled after RESETBMCU are checked for OV, UV and ILIM faults after

each of them is enabled. If an OV, UV or ILIM condition is present, the PF8100/PF8200

starts a fault detection and protection mechanism as described in Section 14.7 "Fault

detection". At this point, the MCU should be able to read the interrupt and react upon a

fault event as defined by the system.

When OTP_PG_CHECK=1, if PGOOD is used as a GPIO, it may be released at any time

in the power up sequence as long as the RESETBMCU is released after one or more of

the SW or LDO regulators.

If a regulator fault occurs after RESETBMCU is de-asserted but before the power

up sequence is finalized, the power up sequence continues to turn on the remaining

regulators as configured, even if a fault detection mechanism is active on an earlier

regulator.

14.8 Interrupt management

The MCU is notified of any interrupt through the INTB pin and various interrupt registers.

The interrupt registers are composed by three types of bits to help manage all the

interrupt requests in the PF8100/PF8200:

• The interrupt latch XXXX_I: this bit is set when the corresponding interrupt event

occurs. It can be read at any time, and is cleared by writing a 1 to the bit.

• The mask bit XXXX_M: this bit controls whether a given interrupt latch pulls the INTB

pin low or not.

• When the mask bit is 1, the interrupt latch does not control the INTB pin.

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

• When the mask bit is 0, INTB pin is pulled low as long as the corresponding latch bit is

set.

• The sense bit XXXX_S: if available, the sense bit provides the actual status of the

signal triggering the interrupt.

The INTB pin is a reflection of an “OR” logic of all the interrupt status bits which control

the pin.

Interrupts are stored in two levels on the interrupts registers. At first level, the SYS_INT

register provides information about the Interrupt register that originated the interrupt

event.

The corresponding SYS_INT bits will be set as long as the INTB pin is programmed to

assert with any of the interrupt bits of the respective interrupt registers.

• STATUS1_I: this bit is set when the interrupt is generated within the INT STATUS1

register

• STATUS2_I: this bit is set when the interrupt is generated within the INT STATUS2

register

• MODE_I: this bit is set when the interrupt is generated within the SW MODE INT

register

• ILIM_I: this bit is set when the interrupt is generated within any of the SW ILIM INT or

LDO ILIM INT registers

• UV_I: this bit is set when the interrupt is generated within any of the SW UV INT or

LDO UV INT registers

• OV_I: this bit is set when the interrupt is generated within any of the SW OV INT or

LDO OV INT registers

• PWRON_I: this bit is set when the interrupt is generated within the PWRON INT

register

• EWARN_I: is set when an early warning event occurs to indicate an imminent

shutdown

The SYS_INT bits are set when the INTB pin is asserted by any of the second level

interrupt bits that have not been masked in their corresponding mask registers. When

the second level interrupt bit is cleared, the corresponding first level interrupt bit on the

SYS_INT register will be cleared automatically.

The INTB pin will remain asserted if any of the first level interrupt bit is set, and it will be

de-asserted only when all the unmasked second level interrupts are cleared and thus all

the first level interrupts are cleared as well.

At second level, the remaining registers provide the exact source for the interrupt event.

Table 27 shows a summary of the interrupt latch, mask and sense pins available on the

PF8100/PF8200.

Table 27.ꢀInterrupt registers

Register name

INT STATUS1

INT MASK1

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

SDWN_I

SDWN_M

—

FREQ_RDY_I

FREQ_RDY_M

—

CRC_I

PWRUP_I

PWRDN_I

XINTB_I

FSOB_I

VIN_OVLO_I

VIN_OVLO_M

VIN_OVLO_S

THERM_80_I

THERM_80_M

THERM_80_S

SW1_MODE_I

SW1_MODE_M

CRC_M

PWRUP_M

—

PWRDN_M

—

XINTB_M

FSOB_M

INT SENSE1

—

XINTB_S

FSOB_S

THERM INT

WDI_I

WDI_M

WDI_S

—

FSYNC_FLT_I

FSYNC_FLT_M

FSYNC_FLT_S

SW7_MODE_I

SW7_MODE_M

THERM_155_I

THERM_155_M

THERM_155_S

SW6_MODE_I

SW6_MODE_M

THERM_140_I

THERM_140_M

THERM_140_S

SW5_MODE_I

SW5_MODE_M

THERM_125_I

THERM_125_M

THERM_125_S

SW4_MODE_I

SW4_MODE_M

THERM_110_I

THERM_110_M

THERM_110_S

SW3_MODE_I

SW3_MODE_M

THERM_95_I

THERM_95_M

THERM_95_S

SW2_MODE_I

SW2_MODE_M

THERM MASK

THERM SENSE

SW MODE INT

SW MODE MASK

—

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Register name

SW ILIM INT

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

—

SW7_ILIM_I

SW6_ILIM_I

SW5_ILIM_I

SW5_ILIM_M

SW5_ILIM_S

—

SW4_ILIM_I

SW4_ILIM_M

SW4_ILIM_S

LDO4_ILIM_I

LDO4_ILIM_M

LDO4_ILIM_S

SW4_UV_I

SW3_ILIM_I

SW3_ILIM_M

SW3_ILIM_S

LDO3_ILIM_I

LDO3_ILIM_M

LDO3_ILIM_S

SW3_UV_I

SW2_ILIM_I

SW2_ILIM_M

SW2_ILIM_S

LDO2_ILIM_I

LDO2_ILIM_M

LDO2_ILIM_S

SW2_UV_I

SW1_ILIM_I

SW1_ILIM_M

SW1_ILIM_S

LDO1_ILIM_I

LDO1_ILIM_M

LDO1_ILIM_S

SW1_UV_I

SW ILIM MASK

SW ILIM SENSE

LDO ILIM INT

LDO ILIM MASK

LDO ILIM SENSE

SW UV INT

—

SW7_ILIM_M

SW6_ILIM_M

—

SW7_ILIM_S

SW6_ILIM_S

—

SW7_UV_I

SW7_UV_M

SW7_UV_S

SW7_OV_I

SW7_OV_M

SW7_OV_S

—

SW6_UV_I

SW6_UV_M

SW6_UV_S

SW6_OV_I

SW6_OV_M

SW6_OV_S

—

SW5_UV_I

SW5_UV_M

SW5_UV_S

SW5_OV_I

SW5_OV_M

SW5_OV_S

—

SW UV MASK

SW UV SENSE

SW OV INT

—

SW4_UV_M

SW4_UV_S

SW4_OV_I

SW3_UV_M

SW3_UV_S

SW3_OV_I

SW2_UV_M

SW2_UV_S

SW2_OV_I

SW1_UV_M

SW1_UV_S

SW1_OV_I

—

SW OV MASK

SW OV SENSE

LDO UV INT

—

SW4_OV_M

SW4_OV_S

LDO4_UV_I

LDO4_UV_M

LDO4_UV_S

LDO4_OV_I

LDO4_OV_M

LDO4_OV_S

PWRON_2S_I

PWRON_2S_M

SW3_OV_M

SW3_OV_S

LDO3_UV_I

LDO3_UV_M

LDO3_UV_S

LDO3_OV_I

LDO3_OV_M

LDO3_OV_S

PWRON_1S_I

PWRON_1S_M

SW2_OV_M

SW2_OV_S

LDO2_UV_I

LDO2_UV_M

LDO2_UV_S

LDO2_OV_I

LDO2_OV_M

LDO2_OV_S

PWRON_REL_I

SW1_OV_M

SW1_OV_S

LDO1_UV_I

LDO1_UV_M

LDO1_UV_S

LDO1_OV_I

LDO1_OV_M

LDO1_OV_S

PWRON_PUSH_I

—

LDO UV MASK

LDO UV SENSE

LDO OV INT

—

LDO OV MASK

LDO OV SENSE

PWRON INT

—

BGMON_I

BGMON_M

PWRON_8S_I

PWRON_8S_M

PWRON_4S_I

PWRON_4S_M

PRON_3S_I

PRON_3S_M

PWRON MASK

PWRON_REL_M PWRON_PUSH_

M

PWRON SENSE

SYS INT

BGMON_S

EWARN_I

—

PWRON_S

STATUS1_I

PWRON_I

OV_I

UV_I

ILIM_I

MODE_I

STATUS2_I

14.9 I/O interface pins

The PF8100/PF8200 PMIC is fully programmable via the I²C interface. Additional

communication between MCU, PF8100/PF8200 and other companion PMIC is provided

by direct logic interfacing including INTB, RESETBMCU, PGOOD, among other pins.

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

V1P5A VDDIO

XINTB

PMIC1

PMIC2

XINTB

XFAILB

VIN/

VDDIO

VDDIO VDDIO

VDDIO

i.MX8 MCU

aaa-028062

Figure 17.ꢀI/O interface diagram

Table 28.ꢀI/O electrical specifications

Symbol

Parameter

Min

Typ

—

Max

Unit

PWRON_ V_IL

PWRON_ V_IH

STANDBY_ V_IL

STANDBY_ V_IH

PWRON low input voltage

PWRON high input voltage

STANDBY low input voltage

STANDBY high input voltage

—

0.4

5.5

0.4

5.5

V

1.4

—

1.4

—

RESETBMCU_ V_OLRESETBMCU low output voltage

10 mA load current

0

—

0.4

INTB_ V_OL

INTB low output voltage

10 mA load current

V

0

—

0.4

XINTB_ V_IL

XINTB_ V_IH

R_{XINTB_PU}

WDI_ V_IL

XINTB low input voltage

—

0.3*VDDIO

V

XINTB high input voltage

XINTB internal pullup resistance

WDI low input voltage

0.7*VDDIO

0.475

—

5.5

V

1.0

—

MΩ

V

—

0.3*VDDIO

WDI_ V_IH

WDI high input voltage

0.7*VDDIO

0.475

—

5.5

—

V

R_{WDI_PD}

WDI internal pull down resistance

1.0

MΩ

V

EWARN_ V_OH

EWARN high output voltage

2.0 mA load current

VDDIO − 0.5

—

VDDIO

PGOOD_ V_OL

PGOOD low output voltage

10 mA load current

V

0

—

1.0

0.4

VSELECT_ V_IL

VSELECT_ V_IH

R_{VSELECT_PD}

VSELECT low input voltage

—

0.3*VDDIO

V

VSELECT high input voltage

0.7*VDDIO

0.475

5.5

—

V

VSELECT internal pull down resistance

MΩ

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Symbol

Parameter

Min

Typ

—

Max

Unit

V

LDO2EN_ V_IL

LDO2EN_ V_IH

R_{LDO2EN_PD}

TBBEN_ V_IL

TBBEN_ V_IH

R_{TBBEN_PD}

LDO2EN low input voltage

LDO2EN high input voltage

LDO2EN internal pull down resistance

TBBEN low input voltage

TBBEN high input voltage

TBBEN internal pull down resistance

XFAILB low input voltage

XFAILB high input voltage

—

0.3*VDDIO

0.7*VDDIO

0.475

—

5.5

—

V

1.0

—

MΩ

V

0.4

5.5

—

1.4

—

V

0.475

—

1.0

—

MΩ

V

XFAILB_V_IL

XFAILB_V_IH

XFAILB_V_OH

0.4

5.5

1.4

—

V

XFAILB high output voltage

Pulled-up to V1P5A

V

V1P5A − 0.5

0

—

XFAILB_V_OL

FSOB_ V_OL

XFAILB low output voltage

10 mA load current

V

0.4

FSOB low output voltage

−10 mA

0

—

0.4

SCL_ V_IL

SCL_ V_IH

SDA_ V_IL

SDA_ V_IH

SDA_ V_OL

SCL low input voltage

SCL high input voltage

SDA low input voltage

SDA high input voltage

—

0.3*VDDIO

VDDIO

V

0.7*VDDIO

—

0.3*VDDIO

VDDIO

0.7*VDDIO

SDA low output voltage

−20 mA load current

0

—

0.4

14.9.1 PWRON

PWRON is an input signal to the IC that acts as a power up event signal in the PF8100/

PF8200.

The PWRON pin has two modes of operations as programed by the

OTP_PWRON_MODE bit.

When OTP_PWRON_MODE = 0 the PWRON pin operates in level sensitive mode. In

this mode, the device is in the corresponding off mode when the PWRON pin is pulled

low. Pulling the PWRON pin high is a necessary condition to generate a power on event.

PWRON may be pulled up to VSNVS or VIN with an external 100 kΩ resistor if device is

intended to come up automatically with VIN application. See Section 14.5 "Power up" for

details on power up requirements.

When OTP_PWRON_MODE = 1, the PWRON pin operates in edge sensitive mode. In

this mode, PWRON is used as an input from a push button connected to the PMIC.

When the switch is not pressed, the PWRON pin is pulled up to VIN externally through

a 100 kΩ resistor. When the switch is pressed, the PWRON pin should be shorted to

ground. The PWRON_S bit is high whenever the PWRON pin is at logic 0 and is low

whenever the PWRON pin is at logic 1.

The PWRON pin has a programmable debounce on the rising and falling edges as

shown below.

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Table 29.ꢀPWRON debounce configuration in edge detection mode

Bits

Value

Falling edge debounce

(ms)

Rising edge debounce

(ms)

PWRON_DBNC[1:0]

00

01

10

11

32

125

750

The default value for the power on debounce is set by the OTP_PWRON_DBNC[1:0]

bits.

Pressing the PWRON switch for longer than the debounce time starts a power on

event as well as generate interrupts which the processor may use to initiate PMIC state

transitions.

During the system-on states, when the PWRON button is pushed (logic 0) for longer than

the debounce setting, the PWRON_PUSH_I interrupt is generated. When the PWRON

button is released (logic 1) for longer than the debounce setting, the PWRON_REL_I

interrupt is generated.

The PWRON_1S_I, PWRON_2S_I, PWRON_3S_I, PWRON_4S_I and PWRON_8S_I

interrupts are generated when the PWRON pin is held low for longer than 1, 2, 3, 4 and 8

seconds respectively.

If PWRON_RST_EN = 1, pressing the PWRON for longer than the delay programmed by

TRESET[1:0] forces a PMIC reset. A PMIC reset initiates a power down sequence, wait

for 30 µs to allow all supplies to discharge and then it powers back up with the default

OTP configuration.

If PWRON_RST_EN = 0, the device starts a turn off event after push button is pressed

for longer than TRESET[1:0].

Table 30.ꢀ TRESET configuration

TRESET[1:0]

Time to reset

00

01

10

11

2 s

4 s

8 s

16 s

The default value of the TRESET delay is programmable through the OTP_TRESET[1:0]

bits.

14.9.2 STANDBY

STANDBY is an input signal to the IC, when this pin is asserted, the device enters the

standby mode and when de-asserted, the part exits standby mode.

STANDBY can be configured as active high or active low using the STANDBYINV bit.

Table 31.ꢀStandby pin polarity control

STANDBY (pin)

STANDBYINV (I²C bit)

STANDBY control

Not in standby mode

In standby mode

0

1

0

1

0

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STANDBY (pin)

STANDBYINV (I²C bit)

STANDBY control

1

Not in standby mode

14.9.3 RESETBMCU

RESETBMCU is an open-drain, active low output used to bring the processor (and

peripherals) in and out of reset.

The time slot RESETBMCU is de-asserted during the power up sequence is programmed

by the OTP_RESETBMCU_SEQ[7:0] bits, and it is a condition to enter the system-on

states.

During the system-on states, the RESETBMCU is de-asserted (pulled high), and it is

asserted (pulled low) as indicated in the power down sequence, when a system power

down or reset is initiated.

In the application, RESETBMCU can be pulled up to VDDIO or VSNVS by a 100 kΩ

external resistor.

14.9.4 INTB

INTB is an open-drain, active low output. This pin is asserted (pulled low) when any

interrupt occurs, provided that the interrupt is not masked.

INTB is de-asserted after the corresponding interrupt latch is cleared by software, which

requires writing a “1” to the interrupt bit.

An INTB_TEST bit is provided to allow a manual test of the INTB pin. When INTB_TEST

is set to 1, the interrupt pin asserts for 100 µs and then de-asserts to its normal state.

The INTB_TEST bit self-clears to 0 automatically after the test pulse is generated.

In the application, INTB can be pulled up to VDDIO with an external 100 kΩ resistor.

14.9.5 XINTB

XINTB is an input pin used to receive an external interrupt and trigger an interrupt event

on the PF8100/PF8200. It is meant to interact with the INTB pin of a companion PMIC, in

order to simplify MCU interaction to identify the source of the interrupt.

A high to low transition on the XINTB pin sets the XINTB_I interrupt bit and causes the

INTB to be asserted, provided the interrupt is not masked.

The XINTB_S bit follows the actual status of the XINTB pin even when the XINTB_I has

been cleared or the interrupt has been masked.

This pin is internally pulled up to VDDIO with a 1.0 MΩ resistors; therefore, it can be left

unconnected when the XINTB is not used.

14.9.6 WDI

WDI is an input pin to the PF8100/PF8200 and is intended to operate as an external

watchdog monitor.

When the WDI pin is connected to the watchdog output of the processor, this pin is used

to detect a pulse to indicate a watchdog event is requested by the processor. When the

WDI pin is asserted, the device starts a watchdog event to place the PMIC outputs in a

default known state.

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The WDI pin is monitored during the system on states. In the off modes and during the

power up sequence, the WDI pin is masked until RESETBMCU is de-asserted.

The WDI can be configured to assert on the rising or the falling edge using the

OTP_WDI_INV bit.

• When OTP_WDI_INV = 0, the device starts a WD event on the falling edge of the WDI.

• When OTP_WDI_INV = 1, the device starts a WD event on the rising edge of the WDI.

A 10 µs debounce filter is implemented on either rising or falling edge detection to

prevent false WDI signals to start a watchdog event.

The OTP_WDI_MODE bit allows the WDI pin to react in two different ways:

• When OTP_WDI_MODE = 1, a WDI asserted performs a hard WD reset.

• When OTP_WDI_MODE = 0, a WDI asserted performs a soft WD reset.

The WDI_STBY_ACTIVE bit allows the WDI pin to generate a watchdog event during the

standby state.

• When WDI_STBY_ACTIVE = 0, asserting the WDI will not generate a watchdog event

during the standby state.

• When WDI_STBY_ACTIVE = 1, asserting the WDI will start a watchdog event during

the standby state.

The OTP_WDI_STBY_ACTIVE is used to configure whether the WDI is active in the

standby state or not by default upon power up.

See Section 15.11 "Watchdog event management" for details on watchdog event.

14.9.7 EWARN

EWARN is an active high output, used to notify that an imminent power failure is about to

occur. It should be pulled down to GND by a 100 kΩ resistor.

When a power down is initiated due to a fault, the EWARN pin is asserted before the

device starts powering down as defined by the EWARN_TIME[1:0] bits in order to allow

the system to prepare for the imminent shutdown.

The following faults cause the EWARN pin to be asserted:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT

• Thermal Shutdown t_J> TSD

• VIN_OVLO event when VIN_OVLO_SDWN=1

Table 32.ꢀEWARN time configuration

OTP_EWARN_TIME[1:0]

EWARN delay time

00

01

10

11

100 μs

5.0 ms

20 ms

50 ms

When the EWARN pin is asserted, an interrupt will be generated and the EWARN_I bit

will be set to announce to the system of an imminent shutdown event.

In the Off modes, EWARN remains de-asserted (pulled low).

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In the event of a power loss (VIN removed), the EWARN pin is asserted upon crossing

the V_WARNTHthreshold to notify to the processor that VIN may be lost and allow some

time to prepare for the power loss.

Table 33.ꢀEarly warning threshold

Symbol

Parameter

Min

Typ

Max

Unit

V_WARNTH

Early warning threshold

2.7

2.8

2.9

V

14.9.8 PGOOD

PGOOD is an open drain output programmable as a Power Good indicator pin or GPO.

In the application, PGOOD can be pulled up to VDDIO with a 100 kΩ resistor.

When OTP_PG_ACTIVE = 0, the PGOOD pin is used as a general purpose output.

As a GPO, during the run state, the state of the pin is controlled by the RUN_PG_GPO

bit in the functional I²C registers:

• When RUN_PG_GPO = 1, the PGOOD pin is high

• When RUN_PG_GPO = 0, the PGOOD pin is low

During the standby state, the state of the pin is controlled by the STBY_PG_GPO bit in

the functional I²C registers:

• When STBY_PG_GPO = 1, the PGOOD pin is high

• When STBY_PG_GPO = 0, the PGOOD pin is low

When used as a GPO, the PGOOD pin can be enabled high as part of the

power up sequence as programmed by the OTP_SEQ_TBASE[1:0] and the

OTP_PGOOD_SEQ[7:0] bits. If enabled as part of the power up sequence, both the

RUN_PG_GPO and STBY_PG_GPO bits are loaded with 1, otherwise they are loaded

with 0 upon power up.

When OTP_PG_ACTIVE = 1, the PGOOD pin is in Power good (PG) mode and it acts as

a PGOOD indicator for the selected output voltages in the PF8100/PF8200.

There is an individual PG monitor for every regulator. Each monitor provide an internal

PG signal that can be selected to control the status of the PGOOD pin upon an OV or UV

condition when the corresponding SWxPG_EN / LDOxPG_EN bits are set. The status

of the PGOOD pin is a logic AND function of the internal PG signals of the selected

monitors.

• When the PG_EN = 1, the corresponding regulator becomes part of the AND function

that controls the PGOOD pin.

• When the PG_EN = 0, the corresponding regulator does not control the status of the

PGOOD pin.

The PGOOD pin is pulled low when any of the selected regulator outputs falls above

or below the programmed OV/UV thresholds and a corresponding OV/UV interrupt is

generated. If the faulty condition is removed, the corresponding OV_S/UV_S bit goes low

to indicate the output is back in regulation, however, the interrupt remains latched until it

is cleared.

The actual condition causing the interrupt (OV, UV) can be read in the fault interrupt

registers. For more details on handling interrupts, see Section 14.8 "Interrupt

management".

When a particular regulator is disabled (via OTP, or I²C, or by change in state of PMIC

such as going to standby mode), it no longer controls the PGOOD pin.

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In the Off mode and during the power up sequence, the PGOOD pin is held low until

RESETBMCU is ready to be released, at this point, the PG monitors are unmasked

and the PGOOD pin is released high if all the internal PG monitors are in regulation.

In the event that one or more outputs are not in regulation by the time RESETBMCU

is ready to de-assert, the PGOOD pin is held low and the PF8100/PF8200 performs

the corresponding fault protection mechanism as described in Section 14.7.1 "Fault

monitoring during power up state".

14.9.9 VSELECT

VSELECT is an input pin used to select the output voltage of LDO2 when bit

VSELECT_EN = 1.

• When VSELECT pin is low, the LDO2 output is programmed to 3.3 V.

• When VSELECT pin is high, the LDO2 output is programmed to 1.8 V.

When VSELECT_EN = 0, the output of LDO2 is given by the VLDO2_RUN[3:0] bits.

When the PF8100/PF8200 is in the standby mode, the output voltage of LDO2 follows

the configuration as selected by the VLDO2_STBY[3:0] bits, regardless of the value of

VSELECT_EN bit.

The default value of the VSELECT_EN bit is programmed by the OTP_VSELECT_EN bit

in the OTP fuses.

A read only bit is provided to monitor the actual state of the VSELECT pin. When the

VSELECT pin is low, the VSELECT_S bit is 0 and when the VSELECT pin is high, the

VSELECT_S bit is set to 1.

14.9.10 LDO2EN

LDO2EN is an input pin used to enable or disable LDO2 when the bit LDO2HW_EN = 1.

When LDO2HW_EN = 1, the status of LDO2 output can also be controlled by the

LDO2_RUN_EN bit in the run mode or the LDO2_STBY_EN bit in the standby mode.

Table 34.ꢀLDO control in run or standby mode

LDO2EN pin

LDO2HW_EN bit

LDO2_RUN_EN LDO2_

STBY_EN

LDO2 output

Do not care

Low

0

1

0

1

0

1

Disabled

Enabled

Disabled

Enabled

High

The default controlling mode for LDO2 is programed by the OTP_LDO2HW_EN bit in the

OTP fuses.

A read only bit is provided to monitor the actual state of the LDO2EN pin. When the

LDO2EN pin is low, the LDO2EN_S bit is 0 and when the LDO2EN pin is high, the

LDO2EN_S bit is set to 1.

14.9.11 FSOB (safety output)

The FSOB pin is a configurable, active low, open drain output used as a safety output to

keep the system in a safe state upon a power up and/or during a specific failure event.

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The FSOB pin is externally pulled up to VIN or VDDIO with a 470 kΩ resistor and it is de-

asserted high in normal operation.

The FSOB pin can be configured in active safe state mode or fault safe state mode as

programmed by the OTP_FSOB_ASS_EN bit in the OTP fuses.

The PF8200 device allows configuration of the FSOB pin to operate in active safe state

or fault safe state modes via the OTP_FSOB_ASS_EN bit in the OTP fuses. Additionally

on the PF8200 device, if the secure I2C write mechanism is enabled, all FSOB flags

require a secure write for them to be cleared (write 1 to clear + RANDOM_GEN read +

RANDOM_CHK write).

In the PF8100 device, the OTP_FSOB_ASS_EN bit is not available, therefore it can only

operate in fault safe state mode.

14.9.11.1 FSOB fault safe state

If the OTP_FSOB_ASS_EN = 0, the active safe state mode is disabled and the FSOB

operate in the fault safe state mode. In this mode, the FSOB pin may still be asserted if

programmed by other fault events.

In the fault safe state mode, the FSOB is de-asserted by default, and can be asserted as

programmed by the FSOB fault selection bits.

A bit is provided to enable the FSOB to be asserted when a regulator fault (OV, UV, ILIM)

is present.

• If FSOB_SOFTFAULT = 0, the FSOB pin is not asserted by any OV, UV, or ILIM fault.

• If FSOB_SOFTFAULT = 1, an OV, UV, or ILIM fault on any of the regulators causes

the FSOB pin to assert and remain asserted regardless of it being corrected or not, and

also asserts the FSOB_SFAULT_NOK flag.

A bit is provided to enable the FSOB to be asserted when a WD reset occurs due to a

WDI event.

• If FSOB_WDI = 0, the FSOB pin is not asserted by a WDI event.

• If FSOB_WDI = 1, a WDI event causes the FSOB pin to assert and the

FSOB_WDI_NOK flag to be set.

A bit is provided to enable the FSOB to be asserted when a WD reset occurs due to an

internal WD counter fault is present.

• If FSOB_WDC = 0, the FSOB pin is not asserted by a WD reset started by the internal

WD counter.

• If FSOB_WDC = 1, a WD reset is started by the internal WD counter causing the FSOB

pin to be asserted and the FSOB_WDC_NOK flag to be set.

A bit is provided to enable the FSOB to be asserted when a hard fault shutdown has

occurred.

• If FSOB_HARDFAULT = 0, the FSOB pin is not asserted by a hard fault.

• If FSOB_HARDFAULT = 1, any of the hard fault shutdown events cause the FSOB pin

to be asserted and the FSOB_HFAULT_NOK flag to be set.

Any of the following events are considered a hard fault shutdown:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT (regulator fault counter max out)

• WD_EVENT_CNT = WD_MAX_CNT (watchdog event counter max out)

• Power up failure

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• Thermal shutdown

The FSOB pin is released when all the FSOB fault flags are cleared or VIN falls below

the UVDET threshold.

14.9.11.2 FSOB active safe state (PF8200 only)

If the OTP_FSOB_ASS_EN = 1, the active safe state mode is enabled.

In the active safe state mode, the FSOB pin is programmed to be asserted low after OTP

fuses are loaded and remain asserted as long as the PMIC is forced in safe state.

In this mode of operation, the PMIC is forced in the safe state under following conditions:

• Any of the ABIST flags are set during the self-test at power up.

• The FSOB_WDI_NOK is set when FSOB is programmed to assert via the FSOB_WDI

bit

• The FSOB_SFAULT_NOK is set when FSOB is programmed to assert via the

FSOB_SOFTFAULT bit

• Hard WD Reset (voltage regulators and RESETBMCU reset)

• Device is in any of the off mode and the RESETBMCU is asserted low

• The FSOB_ASS_NOK flag is asserted

Each time the PMIC is forced into the safe state, the FSOB pin will be asserted low and

the FSOB_ASS_NOK flag will be set to 1 in order to keep the system in the safe state

until the MCU verify that it is safe to return to normal operation.

During the active safe state mode, the PMIC can exit the safe state and release the

FSOB pin if the following conditions are met:

• RESETBMCU is de-asserted (system on)

• All ABIST flags are all 0 (ABIST OK)

• No regulator faults are present

• The FSOB_WDI_NOK and/or FSOB_SFAULT_NOK faults are cleared if programmed

to be set by the FSOB_WDI and FSOB_SOFTFAULT bits respectively

• All other NOK flags in the FSOB_FLAGS register, including the FSOB_ASS_NOK flag,

are cleared

A soft WD reset may also assert the FSOB pin only if programmed by the FSOB_WDI bit.

Likewise, the FSOB_SOFTFAULT bit can select whether the FSOB pin is asserted as

soon as an OV, UV or ILIM fault is present even when this condition has not yet lead to a

fault shutdown. In this scenario the system is placed in a safe state while the MCU tries

to clear the fault and command the PF8200 to come out of the safe state when all faults

have been cleared.

14.9.12 TBBEN

The TBBEN is an input pin provided to allow the user to program the mirror registers

in order to operate the device with a custom configuration as well as programming the

default values on the OTP fuses.

• When TBBEN pin is pulled low to ground, the device is operating in normal mode.

• When TBBEN pin is pulled high to V1P5D device enables the TBB configuration mode.

See Section 17 "OTP/TBB and default configurations" for details on TBB and OTP

operation.

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When TBBEN pin is pulled high to V1P5D the following conditions apply:

• The device uses a fixed I²C device address (0x08)

• Disable the watchdog operation, including WDI monitoring and internal watchdog timer

• Disable the CRC and I²C secure write mechanism while no power up event is present

(TBB/OTP programming mode).

Disabling the watchdog operation may be required for in-line MCU programming where

output voltages are required but watchdog operation should be completely disabled.

14.9.13 XFAILB

XFAILB is a bidirectional pin with an open drain output used to synchronize the power up

and power down sequences of two or more PMIC's. It should be pulled up externally to

V1P5A supply.

The OTP_XFAILB_EN bit is used to enable or disable the XFAILB mode of operation.

• When OTP_XFAILB_EN = 0, the XFAILB mode is disabled and any events on this pin

are ignored

• When OTP_XFAILB_EN = 1, the XFAILB mode is enabled

When the XFAILB mode is enabled, and the PF8200 has a turn off event generated by

an internal fault, the XFAILB pin is asserted low 20 µs before starting the power down

sequence.

A power down event caused by the following conditions will assert the XFAILB pin:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT (regulator fault counter max out)

• WD_EVENT_CNT = WD_MAX_CNT (watchdog event counter max out)

• Power up failure

• Thermal shutdown

• Hard WD event

The XFAILB pin is forced low during the off mode.

During the system-on states, if the XFAILB pin is externally pulled low, it will detect an

XFAIL event after a 20 µs debounce. When an XFAIL event is detected, the XFAILB pin

is asserted low internally and the device starts a power down sequence.

If a PWRON event is present, the device starts a turn on event and proceeds to release

the XFAILB pin when its ready to start the power up sequence state. If the XFAILB pin

is pulled down externally during the power up event, the PF8200 will stop the power up

sequence until the pin is no longer pulled down externally. This will help both PMIC's to

synchronize the power up sequence allowing it to continue only when both PMIC's are

ready to initiate the power up sequence.

A hard WD event will set the XFAILB pin 20 µs before it starts its power down sequence.

After all regulators outputs have been turned off, the device will release the XFAILB pin

internally after a 30 µs delay, proceed to load the default OTP configuration and wait for

the XFAILB pin to be released externally before it can restart the power up sequence.

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bidirectional XFAILB (power up)

PWRON

power up

sequence

states

XFAILB

LP_Off

self-test QPU_Off

system on

RESETBMCU

POWER UP

sequence

aaa-029215

Figure 18.ꢀXFAILB behavior during a power up sequence

bidirectional XFAILB (power down)

power down

sequence

system ON

off mode

states

FAULT EVENT

EWARN

XFAILB

100 µs

20 µs

POWER DOWN

signal

POWER DOWN

sequence

aaa-029214

Figure 19.ꢀXFAILB behavior during a power down sequence

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dual PMIC interaction

(fault on master PMIC)

PWRON

FAULT EVENT

EWARN

XFAILB

MASTER

PMIC

100 µs

power up sequence is started

until both XFAILB are pulled high

20 µs

POWER DOWN

signal

POWER DOWN

sequence

POWER UP

sequence

EWARN

SLAVE

PMIC

pin externally pulled down

20 µs

XFAILB

debounced

POWER DOWN

signal

POWER DOWN

sequence

POWER UP

sequence

slave ready to start power

up sequence (waiting)

aaa-029212

Figure 20.ꢀBehavior during an external XFAILB event

XFAILB during power up

sequence

PWRON

POWER UP

sequence

RESETBMCU

2 ms

MASTER

PMIC

XFAILB

power up sequence is restarted

until both XFAILB are pulled high

POWER DOWN

signal

POWER UP

sequence

slave ready to start pwer up

sequence (waiting)

SLAVE

PMIC

XFAILB

pin externally pulled down

POWER DOWN

signal

aaa-029213

Figure 21.ꢀExternal XFAILB event during a power up sequence

14.9.14 SDA and SCL (I²C bus)

Communication with the PF8100/PF8200 is done through I²C and it supports high-speed

operation mode with up to 3.4 MHz operation. SDA and SCL are pulled up to VDDIO with

2.2 kΩ resistors. It is recommended to use 1.5 kΩ if 3.4 MHz I²C speed is required.

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The PF8100/PF8200 is designed to operate as a slave device during I²C communication.

The default I²C device address is set by the OTP_I2C_ADD[2:0].

Table 35.ꢀI²C address configuration

OTP_I2C_ADD[2:0]

Device address

0x08

000

001

010

011

100

101

110

111

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

See http://www.nxp.com/documents/user_manual/UM10204.pdf for detailed information

on the digital I²C communication protocol implementation.

During an I²C transaction, the communication will latch after the 8th bit is sent. If the data

sent is not a multiple of 8 bit, any word with less than 8 bits will be ignored. If only 7 bits

are sent, no data is written and the logic will not provide an ACK bit to the MCU.

From an IC level, a wrong I²C command can create a system level safety issue. For

example, though the MCU may have intended to set a given regulator’s output to 1.0 V, it

may be erroneously registered as 1.1 V due to noise in the bus.

To prevent a wrong I²C configuration, various protective mechanisms are implemented.

14.9.14.1 I²C CRC verification

When this feature is enabled, a selectable CRC verification is performed on each I²C

transaction.

• When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled.

• When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled.

After each I²C transaction, the device calculates the corresponding CRC byte to ensure

the configuration command has not been corrupted.

When a CRC fault is detected, the PF8100/PF8200 ignores the erroneous configuration

command and triggers a CRC_I interrupt asserting the INTB pin, provided the interrupt is

not masked.

The PF8100/PF8200 implements a CRC-8-SAE, per the SAE J1850 specification.

• Polynomial = 0x1D

• Initial value = 0xFF

2

MSB Data

I C CRS Polynominal

Seed: 1 1 1 1 1 1 1 1

7

6

5

4

3

2

1

0

aaa-028696

Figure 22.ꢀ8 bit SAE J1850 CRC polynomial

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14.9.14.2 I²C secure write

A secure write mechanism is implemented for specific registers critical to the functional

safety of the device.

• When OTP_I2C_ SECURE_EN = 0, the secure write is disabled.

• When OTP_I2C_ SECURE_EN = 1, the secure write is enabled.

When the secure write is enabled, a specific sequence must be followed in order to grant

writing access on the corresponding secure register.

Secure write sequence is as follows:

• MCU sends command to modify the secure registers

• PMIC generates a random code in the RANDOM_GEN register

• MCU reads the random code from the RANDOM_GEN register and writes it back on

the RANDOM_CHK register

The PMIC compares the RANDOM_CHK against the RANDOM_GEN register:

• If RANDOM_CHK [7:0] = RANDOM_GEN[7:0], the device applies the configuration

on the corresponding secure register, and self-clears both the RANDOM_GEN and

RANDOM_CHK registers.

• If RANDOM_CHK[7:0] different from RANDOM_GEN[7:0], the device ignores the

configuration command and self-clears both the RANDOM_GEN and RANDOM_CHK

registers.

In the event the MCU sends any other command instead of providing a value for the

RANDOM_CHK register, the state machine cancels the ongoing secure write transaction

and performs the new I²C command.

In the event the MCU does not provide a value for the RANDOM_CHK register, the I²C

transaction will time out 10 ms after the RANDOM_GEN code is generated, and device is

ready for a new transaction.

Table 36.ꢀSecure bits

Register

Bit

Description

ABIST OV1

AB_SW1_OV

Writing a 1 to this flag to clear the ABIST fault

notification

ABIST OV1

ABIST OV2

AB_SW2_OV

AB_SW3_OV

AB_SW4_OV

AB_SW5_OV

AB_SW6_OV

AB_SW7_OV

AB_LDO1_OV

AB_LDO2_OV

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

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Register

Bit

Description

ABIST OV2

AB_LDO3_OV

Writing a 1 to this flag to clear the ABIST fault

notification

ABIST OV2

ABIST UV1

ABIST UV2

AB_LDO4_OV

AB_SW1_UV

AB_SW2_UV

AB_SW3_UV

AB_SW4_UV

AB_SW5_UV

AB_SW6_UV

AB_SW7_UV

AB_LDO1_UV

AB_LDO2_UV

AB_LDO3_UV

AB_LDO4_UV

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

Writing a 1 to this flag to clear the ABIST fault

notification

ABIST RUN

FSOB FLAGS

CTRL1

AB_RUN

Writing a 1 starts an ABIST on demand

FSOB_ASS_NOK

FSOB_SFAULT_NOK

FSOB_WDI_NOK

FSOB_WDC_NOK

FSOB_HFAULT_NOK

TMP_MON_EN

Writing a 1 to this flag to clear the FSOB flag

Writing a 0 disables the thermal monitor, preventing

the thermal interrupts and thermal shutdown event

from being detected

CTRL1

VIN_OVLO_EN

Writing a 0 disables the VIN overvoltage lockout

monitor completely

VIN_OVLO_SDWN

Writing a 0 disables a shutdown event upon a VIN

overvoltage condition (only interrupts are provided)

CTRL1

WD_EN

Writing a 0 disables the watchdog counter block

WD_STBY_EN

Writing a 0 disables the watchdog counter during the

standby mode

CTRL1

WDI_STBY_ACTIVE

Writing a 0 disables the monitoring of WDI input

during standby mode

CTRL1

I2C_SECURE_EN

SW1VMON_EN

SW2VMON_EN

SW3VMON_EN

Writing a 0 disables de I²C secure write mode

Writing a 0 disables the OV/UV monitor for SW1

Writing a 0 disables the OV/UV monitor for SW2

Writing a 0 disables the OV/UV monitor for SW3

VMONEN1

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Register

Bit

Description

VMONEN1

VMONEN2

SW4VMON_EN

SW5VMON_EN

SW6VMON_EN

SW7VMON_EN

LDO1VMON_EN

LDO2VMON_EN

LDO3VMON_EN

LDO4VMON_EN

Writing a 0 disables the OV/UV monitor for SW4

Writing a 0 disables the OV/UV monitor for SW5

Writing a 0 disables the OV/UV monitor for SW6

Writing a 0 disables the OV/UV monitor for SW7

Writing a 0 disables the OV/UV monitor for LDO1

Writing a 0 disables the OV/UV monitor for LDO2

Writing a 0 disables the OV/UV monitor for LDO3

Writing a 0 disables the OV/UV monitor for LDO4

15 Functional blocks

15.1 Analog core and internal voltage references

All regulators use the main bandgap as the reference for the output voltage generations,

this bandgap is also used as reference for the internal analog core and digital core

supplies. The performance of the regulators is directly dependent on the performance of

the bandgap.

No external DC loading is allowed on V1P5A and V1P5D. V1P5D is kept powered as

long as there is a valid supply and/or valid coin cell and it may be used as a reference

voltage for the VDDOTP and TBBEN pins during system power on.

A second bandgap is provided as the reference for all the monitoring circuits. This

architecture allows the PF8200 to provide a reliable way to detect not only single point,

but also latent faults in order to meet the metrics required by an ASIL B level application.

Table 37.ꢀInternal supplies electrical characteristics

Symbol

V_1P5D

C_1P5D

V_1P5A

Parameter

Min

1.50

—

Typ

1.60

1.0

Max

1.65

—

Unit

V

V1P5D output voltage

V1P5D output capacitor

V1P5A output voltage

V1P5A output capacitor

µF

V

1.50

—

1.60

1.0

1.65

—

C_1P5A

µF

15.2 Coin cell charger

A coin cell or super capacitor may be connected to the LICELL pin, the PF8100/PF8200

features a simple constant current charger available at the LICELL pin.

The COINCHG_EN bit is used to enable or disable the coin cell charger during the

system-on states (run and standby) via I²C.

• When COINCHG_EN = 0 the coin cell charger is disabled in run or standby modes.

• When COINCHG_EN = 1 the coin cell charger is enabled in run or standby modes.

The COINCHG_EN bit is reset to 0, when VIN crosses the UVDET threshold.

During the run mode, the coin cell charger utilizes a 60 µA charging current. If enabled

during standby mode, the coin cell charger utilizes only a 10 µA charging current to be

able to maintain low power consumption while still being able to maintain the backup

battery voltage charged at all time.

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The COINCHG_OFF bit is used to enable or disable the coin cell charger during the

QPU_Off state via I²C. In this mode, the charger utilizes a 10 µA charging current.

• When COINCHG_OFF = 0 the coin cell charger is disabled in QPU_Off state.

• When COINCHG_OFF = 1 the coin cell charger is enabled in QPU_Off state.

If the system requires to allow charging of the coin cell during the QPU_Off, the system

should enable the COINCHG_OFF bit during the run mode and the charger turns on

during the QPU_Off state, if programmed to stay in this state after power down. The

COINCHG_OFF bit is reset to 0, when VIN crosses the UVDET threshold.

The VCOIN[3:0] bits set the target charging voltage for the LICELL pin as shown in the

table below. The OTP_VCOIN[3:0] bits are used to set the default voltage for the coin cell

battery charger.

Table 38.ꢀCoin cell charger voltage level

VCOIN[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Target LICELL voltage (V)

1.8

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.6

Table 39.ꢀCoin cell electrical characteristics

All parameters specified for T_A= −40 ºC to 105 ºC, VIN = 5.0 V, All output voltage settings, typical external components,

unless otherwise noted. Typical values are specified for T_A= 25 ºC, VIN = 5.0 V, typical external components, unless

otherwise noted.

Symbol

V_IN

Parameter

Min

2.5

Typ

—

Max

5.5

Unit

V

Input voltage range

V_COINACC

V_COINHDR

Voltage accuracy (2.6 V to 3.6 V)

Voltage accuracy (1.8 V to 2.5 V)

−3.0

−4.0

—

3.0

%

—

4.0

%

Input voltage headroom

mV

Minimum VIN headroom to guarantee V_COINregulation at I_COINHI

300

60

—

V_COINHYS

I_COINACC

I_COINHI

Charging hysteresis

100

—

200

30

—

mV

%

Current accuracy

−30

—

Coin cell charger current in run mode

Coin cell charger current in standby and QPU_Off

60

10

µA

I_COINLO

—

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Symbol

Parameter

Min

0

Typ

10

Max

20

Unit

µA

I_QCOINCH

Quiescent current when coin cell is charging

Reverse leakage comparator hysteresis

V_COINRLHYS

V_COINRLTR

50

100

170

mV

Reverse leakage comparator trip voltage at rising edge

(V_IN− V_COIN) at every VCOIN setting

100

0

200

100

300

250

V_COINRLTF

Reverse leakage comparator trip voltage at falling edge

(V_IN− V_COIN) at every VCOIN setting

mV

15.3 VSNVS LDO/switch

VSNVS is a 10 mA LDO/switch provided to power the RTC domain in the processor. In

systems using the i.MX 8 processors, it powers the VDD_SNVS_IN domain of the MCU.

Three scenarios may be possible during VIN application:

1. Coin cell was applied for the first time before VIN power up.

2. Coin cell is not present upon VIN power up.

3. Coin cell has been present after a previous power cycle.

If coin cell is first applied without VIN present, VSNVS remains disabled until VIN >

UVDET and the VSNVS gets loaded with the OTP fuse configuration.

When VIN is applied and no coin cell is present, VSNVS is initially disabled and it is only

enabled to its regulation point after OTP fuses are loaded.

If coin cell has been present after a previous power cycle, the VSNVS configuration is

reloaded from the OTP registers when the VIN crosses the UVDET threshold. This way,

if the VSNVS was modified via the I²C configuration bit, it will always be reset to the

default value after a VIN power cycle.

When VIN < V_WARNTH, a best of supply circuit decides whether VSNVS is powered by

VIN or LICELL.

• When VIN is rising and VIN > UVDET, VSNVS is powered by VIN. When operating

from VIN, it can regulate the output to 1.8 V, 3.0 V or 3.3 V. If the configured output

voltage is higher than the input source, the VSNVS operates in dropout mode to track

the input voltage.

• When operating from LICELL, it regulates the output when the output voltage is

selected at 1.8 V. VSNVS operates as a switch from LICELL when the output voltage

setting is selected to 3.0 V or 3.3 V.

The following table shows the expected operation of the VSNVS block for different

voltage settings and different input voltage conditions.

Table 40.ꢀVSNVS operation description

OTP_VSNVSVOLT[1:0]

VSNVS output voltage (V) VIN

Expected VSNVS output

00

01

10

11

Disabled

1.8

Do not care

VSNVS is disabled on OTP

< V_WARNTHfalling

> UVDET rising

< V_WARNTHfalling

> UVDET rising

< V_WARNTHfalling

> UVDET rising

Regulate to 1.8 V from the highest of VIN or LICELL ^[1]

1.8

Regulate to 1.8 V from VIN

3.0

Switch mode from the highest of VIN or LICELL

Regulate to 3.0 from VIN ^[1]

3.0

3.3

Switch mode from the highest of VIN or LICELL

Regulate to 3.3 from VIN ^[1]

3.3

[1] Regulator is in drop off mode, if input is not enough to regulate to set point.

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VIN

VSNVS

COIN CELL

SUPPLY

SELECTION

CHARGER

LICELL

OUTPUT

VOLTAGE

SELECTION

VSNVS

aaa-028063

Figure 23.ꢀVSNVS block diagram

The VSNVS output keeps regulation through all states, including the system-on, off

modes, power down sequence, watchdog reset, fail-safe transition and fail-safe state as

long as it has a valid input (VIN or LICELL), and the output has been configured by the

OTP_VSNVSVOLT[1:0] registers.

Table 41.ꢀVSNVS output voltage configuration

OTP_VSNVSVOLT[1:0]

VSNVSVOLT[1:0]

VSNVS output voltage (V)

00

01

10

11

00

01

10

11

Off

1.8

3.0

3.3

For system debugging purposes, the VSNVS output may be changed during the system-

on states by changing the VSNVSVOLT[1:0] bits in the functional I²C registers.

Table 42.ꢀVSNVS electrical characteristics

All parameters are specified at T_A= −40 °C to 105 °C, unless otherwise noted. Typical values are characterized at V_IN

5.0 V, and T_A= 25 °C, unless otherwise noted.

=

Symbol

Parameter

Min

2.5

Typ

—

Max

5.5

10

Unit

V

V_{IN_SNVS}

Operating voltage range from VIN

Operating voltage range from LICELL

VSNVS load current range

V_{LICELL_SNVS}

I_SNVS

V_{SNVS_ACC}

V_{SNVS_RDSON}

1.728

0

—

V

—

mA

%

VSNVS output voltage accuracy in LDO mode

−5.0

—

5.0

VSNVS LDO on resistance

VSNVSVOLT[1:0] = 10 or 11

Ω

—

20

—

VSNVS_IQ

V_{SNVS_HDR}

VSNVS quiescent current in LDO mode

5.0

µA

VSNVS LDO headroom voltage

mV

Minimum voltage above setting

VSNVSVOLT[1:0] = 10 or 11 to guarantee

regulation with 5 % tolerance

200

—

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Symbol

Parameter

Min

Typ

Max

Unit

V_{SNVS_HDR}

VSNVS LDO headroom voltage

mV

Minimum voltage above setting

VSNVSVOLT[1:0] = 01 to guarantee regulation

with 5 % tolerance

500

—

V_{SNVS_OS}

VSNVS startup overshoot

VSNVS load transient

—

200

100

mV

Ω

V_{SNVS_TRANS}

V_{SNVS_SW_R}

−100

VSNVS switch mode resistance

VSNVSVOLT[1:0] = 10 or 11

—

20

V_{SNVS_LICELL_IQ}

VSNVS quiescent current in switch mode

VSNVSVOLT[1:0] = 10 or 11

µA

—

1.0

—

V_{SNVS_ILIM}

V_{SNVS_TON}

VSNVS current limit

20

70

mA

ms

VSNVS turn on time

Block enabled to VSNVS at 90 % of final value

—

1.35

15.4 Type 1 buck regulators (SW1 to SW6)

The PF8100/PF8200 features six low-voltage regulators with input supply range from

2.5 V to 5.5 V and output voltage range from 0.4 V to 1.8 V in 6.25 mV steps. Each

voltage regulator is capable to supply 2.5 A and features a programmable soft-start and

DVS ramp for system power optimization.

VIN

SWxIN

SWxMODE

C

INSWx

SWxILIM

CONTROLLER

L

SWx

SWxLX

SWx

DRIVER

SWxPHASE

C

OSWx

I

SENSE

+

2

I C

2 to 3 MHz

clock

+

INTERFACE

slope

compensation

TYPE II INTERNAL

COMPENSATION

duty cycle

generator

R1

SWxFB

EA

R2

Z2

VSWx

DAC

aaa-028064

Figure 24.ꢀBuck regulator block diagram

The OTP_SWxDVS_RAMP bit sets the default step/time ratio for the power up ramp

during the power up/down sequence as well as the DVS slope during the system on.

The power down ramp and DVS rate of the Type 1 buck regulators can be modified

during the system-on states by changing the SWxDVS_RAMP bit on the I²C register

map.

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Table 43.ꢀDVS ramp speed configuration

SWxDVS_RAMP bit

DVS ramp speed

Slow DVS ramp

Fast DVS ramp

0

1

The DVS ramp rate is based on the internal clock configuration as shown in Table 44.

Table 44.ꢀRamp rates

All ramp rates are typical values.

Clock frequency tolerance = ± 6 %.

CLK_FREQ[3:0] Clock frequency Regulators

SWxDVS_RAMP = 0

DVS_Up (mV/µs)

SWxDVS_RAMP = 0

DVS_Down (mV/µs)

SWxDVS_RAMP = 1

DVS_Up (mV/µs)

SWxDVS_RAMP = 1

DVS_Down (mV/µs)

(MHz)

frequency (MHz)

0000

0001

0010

0011

0100

1001

1010

1011

1100

20

21

22

23

24

16

17

18

19

2.5

7.813

8.203

8.594

8.984

9.375

6.250

6.641

7.031

7.422

5.208

5.469

5.729

5.990

6.250

4.167

4.427

4.688

4.948

15.625

16.406

17.188

17.969

18.750

12.500

13.281

14.063

14.844

10.417

10.938

11.458

11.979

12.500

8.333

2.625

2.75

2.875

3

2

2.125

2.25

2.375

8.854

9.375

9.896

Type 1 Buck regulators use 8 bits to set the output voltage.

• The VSWx_RUN[7:0] set the output voltage during the run mode.

• The VSWx_STBY[7:0] set the output voltage during the standby mode.

The default output voltage configuration for the run and the standby modes is loaded

from the OTP_VSWx[7:0] registers upon power up.

Table 45.ꢀOutput voltage configuration

Set point

VSWx_RUN[7:0]

VSWx_STBY[7:0]

V_SWxFB(V)

0

1

2

3

00000000

00000001

00000010

00000011

0.40000

0.40625

0.41250

0.41875

.

175

10101111

1.49375

1.50000

1.80000

Reserved

176

10110000

177

10110001

178 to 255

10110010 to 11111111

DVS operation is available for all voltage settings between 0.4 V to 1.5 V. However,

the SWx regulator is not intended to perform DVS transitions to or from the 1.8 V

configuration. In the event a voltage change is requested between any of the low voltage

settings and 1.8 V, the switching regulator is automatically disabled first and then re-

enabled at the selected voltage level to avoid an uncontrolled transition to the new

voltage setting.

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Each regulator is provided with two bits to set its mode of operation.

• The SWx_RUN_MODE[1:0] bits allow the user to change the mode of operation of the

SWx regulators during the run state. If the regulator was programmed as part of the

power up sequence, the SWx_RUN_MODE[1:0] bits are loaded with 0b11 (autoskip) by

default. Otherwise, it is loaded with 0b00 (disabled).

• The SWx_STBY_MODE[1:0] bits allow the user to change the mode of operation of

the SWx regulators during the standby state. If the regulator was programmed as part

of the power up sequence, the SWx_STBY_MODE[1:0] bits are loaded with 0b11

(autoskip) by default. Otherwise, it is loaded with 0b00 (disabled).

Table 46.ꢀSW regulator mode configuration

SWx_MODE[1:0]

Mode of operation

OFF

00

01

10

11

PWM mode

PFM mode

Autoskip mode

The SWx_MODE_I interrupt asserts the INTB pin when any of the Type 1 regulators

have changed the mode of operation, provided the corresponding interrupt is not

masked.

To avoid potential detection of an OV/UV fault during SWx ramp up, it is recommended to

power up the regulator in PWM or autoskip mode.

The type 1 buck regulators use 2 bits SWxILIM[1:0], to program the current limit

detection.

Table 47.ꢀSWx current limit selection

SWxILIM[1:0]

Typical current limit

00

01

10

11

2.1 A

2.6 A

3.0 A

4.5 A

During single phase operation, all buck regulators use 3 bits (SWxPHASE[2:0]) to control

the phase shift of the switching frequency. Upon power up, the switching phase of all

regulators is defaulted to 0 degrees and can be modified during the system-on states.

Table 48.ꢀSWx phase configuration

SWx_PHASE[2:0]

Phase shift [degrees]

000

001

010

011

100

101

110

111

45

90

135

180

225

270

315

0 (default)

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Each one of the buck regulator provide 2 OTP bits to configure the value of the inductor

used in the corresponding block. The OTP_SWx_LSELECT[1:0] allow to choose the

inductor as shown in Table 49.

Table 49.ꢀSWx inductor selection bits

OTP_SWx_LSELECT[1:0]

Inductor value

1.0 µH

00

01

10

11

0.47 µH

1.5 µH

Reserved

15.4.1 SW6 VTT operation

SW6 features a selectable VTT mode to create VTT termination for DDR memories.

When SW6_VTTEN = 1, the VTT mode is enabled. In this mode, SW6 reference voltage

is internally connected to SW5FB output through a divider by 2.

During the VTT mode the DVS operation on SW6 is disabled and SW6 output is given by

V_SW5FB/ 2. In this mode, the minimum output voltage configuration for SW5 should be

800 mV to ensure the SW6 is still within the regulation range at its output.

During the power up sequence, the SW6 (VTT) may be turned on in the same or at a

later slot than SW5, as required by the system. When SW6 and SW5 are enabled in the

same slot, SW6 will always track the VSW5/2. When SW6 is enabled after SW5, it will

ramp up gradually to a predefined voltage and once this voltage is reached, it will start

tracking VSW5/2. The user may adjust the value at which the SW6 should start tracking

the voltage on the SW5 regulator by setting the OTP_VSW6 register accordingly.

During normal operation, if the SW5 is disabled via the I²C command, SW6 will track the

output of SW5 and both regulators will be discharged together and pulled down internally.

When SW5 is enabled back via the I²C commands, the SW5 output will ramp-up to the

corresponding voltage while SW6 is always VSW5/2.

When only SW6 is disabled, the PMIC uses the OTP_VTT_PDOWN bit to program

whether the SW6 regulator is disabled with the output in high impedance or discharged

internally.

• When OTP_VTT_PDOWN = 0, the output is disabled in high impedance mode.

• When OTP_VTT_PDOWN = 1, the output is disabled with the internal pull down

enabled.

When SW6 is requested to enable back again, the SW6 will ramp-up to the voltage set

on the VSW6_RUN or VSW6_STBY registers. Once it reaches the final DVS value, it will

change its reference to start tracking SW5 output again. Note that VSW6_RUN(STBY)

must be set to VSW5_RUN(STBY)/2 or the closest code by the MCU to ensure proper

operation.

When operating in VTT mode, the minimum output voltage configuration for SW5 should

be 800 mV to ensure the SW6 is still within the regulation range at its output.

15.4.2 Multiphase operation

Regulators SW1, SW2, SW3 and SW4 can be configured in quad phase mode. In this

mode, SW1 registers control the output voltage and other configurations. Likewise,

SW1FB pin becomes the main feedback node for the resulting voltage rail, however all

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four FB pins should be connected together. In quad phase operation, each phase can be

independently set via the corresponding SWxPHASE[1:0] bits.

Regulators SW1, SW2 and SW3 can be configured in triple phase mode. In this mode,

SW1 registers control the output voltage and other configurations. Likewise, SW1FB

pin becomes the main feedback node for the resulting voltage rail, however all three

FB pins should be connected together. In triple phase operation, each phase can be

independently set via the corresponding SWxPHASE[1:0] bits.

When SW1 to SW3 are configured in triple phase, the SW4 operates in single phase.

Regulators SW1 and SW2 can be configured in dual phase mode. In this mode, SW1

registers control the output voltage and other configurations. Likewise, SW1FB pin

becomes the main feedback node for the resulting voltage rail, however the two FB

pins should be connected together. In dual phase operation, each phase can be

independently set via the corresponding SWxPHASE[1:0] bits.

The OTP_SW1CONFIG[1:0] bits are used to select the dual phase configuration for

SW1/SW2, as well as triple or quad phase configuration.

Table 50.ꢀOTP_SW1CONFIG register description

OTP_SW1CONFIG[1:0]

Description

00

01

10

11

SW1 and SW2 operate in single phase mode

SW1/SW2 operate in dual phase mode

SW1/SW2/SW3/SW4 operate in quad phase mode

SW1/SW2/SW3 operate in triple phase mode

Regulators SW3 and SW4 can be configured in dual phase mode. In this mode, SW4

registers control the output voltage and other configurations. Likewise, SW4FB pin

becomes the main feedback node for the resulting voltage rail, however the two FB pins

should be connected together.

In dual phase operation, each phase can be independently set via the corresponding

SWxPHASE[1:0] bits.

The OTP_SW4CONFIG[1:0] bits are used to select the dual phase operation of SW3/

SW4.

Table 51.ꢀOTP SW4CONFIG register description

OTP_SW4CONFIG[1:0]

Description

00

01

10

11

SW3 and SW4 operate in single phase mode

SW3/SW4 operate in dual phase mode

Reserved

Configuring regulators SW1 through SW4 in quad phase or triple phase operation

overrides the configuration of the OTP_SW4CONFIG[1:0] bits.

Regulators SW5 and SW6 can be configured in dual phase mode. In this mode, SW5

registers control the output voltage and other configurations. Likewise, SW5FB pin

becomes the main feedback node for the resulting voltage rail, however the two FB pins

should be connected together.

In dual phase operation, each phase can be independently set via the corresponding

SWxPHASE[1:0] bits.

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The OTP_SW5CONFIG[1:0] bits are used to select single or dual phase configuration for

SW5/SW6.

Table 52.ꢀOTP_SW5CONFIG register description

OTP_SW5CONFIG[1:0]

Description

00

01

10

11

SW5 and SW6 operate in single phase mode

SW5/SW6 operate in dual phase mode

Reserved

VIN (2.5 to 5.5 V)

4.7 µF

x 2

SW1FB

SW1IN

VOUT

22 µF

x 4

1.0 µH

SW1LX

DUAL PHASE

CONFIGURATION

SW2FB

SW2IN

SW2LX

aaa-030479

Figure 25.ꢀDual phase configuration

VIN (2.5 to 5.5 V)

x4

SW1FB

VSW1/2/3

SW1IN

SW1LX

SW2FB

SW2IN

SW2LX

SW3FB

SW3IN

SW3LX

SW4FB

SW4IN

SW4LX

x6

TRIPLE PHASE

CONFIGURATION

VSW4

x2

aaa-032582

Figure 26.ꢀTriple phase configuration

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VIN (2.5 to 5.5 V)

4.7 µF

x 4

SW1FB

VOUT

SW1IN

SW1LX

SW2FB

SW2IN

SW2LX

SW3FB

SW3IN

SW3LX

SW4FB

SW4IN

SW4LX

22 µF

x 8

1.0 µH

QUAD PHASE

CONFIGURATION

aaa-030480

Figure 27.ꢀQuad phase configuration

15.4.3 Electrical characteristics

Table 53.ꢀType 1 buck regulator electrical characteristics

All parameters are specified at T_A= −40 to 105 °C, VIN = V_SWxIN= UVDET to 5.5 V, V_SWxFB= 1.0 V, I_SWx= 500 mA, typical

external component values, f_SW= 2.25 MHz, unless otherwise noted. Typical values are characterized at VIN = V_SWxIN= 5.0

V, V_SWxFB= 1.0 V, I_SWx= 500 mA, and T_A= 25 °C, unless otherwise noted.

Symbol

Parameter^[1][2]

Min

Typ

Max

Unit

V

[3]

V_SWxIN

Operating functional input voltage

UVDET

—

5.5

V_SWxACC

Output voltage accuracy

PWM mode

mV

−10

−2.0

−36

−57

—

10

2.0

36

57

0.4 V ≤ V_SWxFB≤ 0.8 V

0 ≤ I_SWx≤ 2.5 A

V_SWxACC

Output voltage accuracy

PWM mode

%

0.8 V < V_SWxFB≤ 1.5 V

0 ≤ I_SWx≤ 2.5 A

V_SWxACC

Output voltage accuracy

PWM mode

%

V_SWxFB= 1.8 V

0 ≤ I_SWx≤ 2.5 A

V_SWxACCPFM

Output voltage accuracy

PFM mode

mV

0.4 V ≤ V_SWxFB≤ 1.5 V

0 ≤ I_SWx≤ 100 mA

V_SWxACCPFM

Output voltage accuracy

PFM mode

V_SWxFB= 1.8 V

0 ≤ I_SWx≤ 100 mA

t_PFMtoPWM

I_SWx

I_{SWx_DP}

I_{SWx_TP}

PFM to PWM transition time

Max load current in single phase

Max load current in dual phase

Max load current in triple phase

30

—

µs

2500

5000

7500

mA

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Symbol

I_{SWx_QP}

I_SWxLIM

Parameter^[1][2]

Min

Typ

Max

Unit

mA

A

Max load current in quad phase

10000

—

Current limiter - inductor peak current detection

SWxILIM[1:0] = 00

1.6

2.0

2.4

2.1

2.6

3.0

2.5

3.1

3.7

I_SWxLIM

I_SW5LIM

Current limiter - inductor peak current detection

SWxILIM[1:0] = 01

A

Current limiter - inductor peak current detection

SWxILIM[1:0] = 10

[4]

[5]

Current limiter - inductor peak current detection

SWxILIM[1:0] = 11

3.6

3.9

4.5

5.45

Current limiter - inductor peak current detection

SW5ILIM[1:0] = 11

I_SWxNLIM

Negative current limit in single phase mode

0.6

3.2

4.0

4.8

7.2

4.8

6.0

7.2

10.8

7.2

8.0

9.6

14.4

−25

1.0

1.4

A

I_{SWxxLIM_DP}

Current limit in dual phase operation

SWxILIM = 00 (master)

4.2

5.0

I_{SWxxLIM_DP}

I_{SWxxLIM_TP}

I_{SWxxLIM_QP}

V_SWxOSH

Current limit in dual phase operation

SWxILIM = 01 (master)

A

5.2

6.2

Current limit in dual phase operation

SWxILIM = 10 (master)

A

6.0

7.4

Current limit in dual phase operation

SWxILIM = 11 (master)

A

9.0

10.9

7.5

Current limit in triple phase operation

SW1ILIM[1:0] = 00

A

6.3

Current limit in triple phase operation

SW1ILIM[1:0] = 01

A

7.8

9.3

Current limit in triple phase operation

SW1ILIM[1:0] = 10

A

9.0

11.1

16.35

10

Current limit in triple phase operation

SW1ILIM[1:0] = 11

A

13.5

8.4

Current limit in quad phase operation

SW1ILIM = 00

A

Current limit in quad phase operation

SW1ILIM = 01

A

10.4

12.0

18.0

25

12.4

14.8

21.8

50

Current limit in quad phase operation

SW1ILIM = 10

A

Current limit in quad phase operation

SW1ILIM = 11

A

Startup overshoot

mV

SWxDVS RAMP = 6.25 mV/µs

VSWxIN = 5.5 V, VSWxFB= 1.0 V

t_ONSWx

Turn on time

µs

From enable to 90 % of end value

SWxDVS RAMP = 0 (6.25 mV/µs)

VSWxIN = 5.5 V, VSWxFB= 1.0 V

—

160

—

t_ONSWxMAX

Maximum turn on time

From enable to 90 % of end value

SWxDVS RAMP = 0 (6.25 mV/µs)

VSWxIN = 5.5 V, VSWxFB= 1.5 V

—

310

t_{ONSWx_MIN}

Minimum turn on time

From enable to 90 % of end value

SWxDVS RAMP = 1 (12.5 mV/µs)

VSWxIN = 5.5 V, VSWxFB= 0.4 V

34.2

—

η_SWx

F_SWx

Efficiency (PFM mode, 1.0 V, 1.0 mA)

Efficiency (PFM mode, 1.0 V, 50 mA)

Efficiency ( PFM Mode, 1.0 V, 100 mA)

Efficiency (PWM mode, 1.0 V, 500 mA)

Efficiency (PWM mode, 1.0 V, 1000 mA)

Efficiency (PWM mode, 1.0 V, 2000 mA)

—

80

81

82

83

82

79

—

%

PWM switching frequency range

Frequency set by CLK_FREQ[3:0]

MHz

1.9

—

2.5

27

3.15

—

T_OFFminSWx

Minimum off time

ns

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Symbol

T_DBSWx

T_slew

Parameter^[1][2]

Min

—

Typ

3.0

—

Max

—

Unit

ns

Deadband time

Slewing time (10 % to 90 %)

Output ripple in PWM mode

—

5.0

1.0

ns

D_VSWx

—

%

V_SWxLOTR

Transient load regulation (overshoot/undershoot)

at 0.8 V < V_SWxFB≤ 1.2 V

mV

ILoad = 200 mA to 1.0 A, di/dt = 2.0 A/µs (single phase)

ILoad = 400 mA to 2.0 A, di/dt = 4.0 A/µs (dual phase)

ILoad = 600 mA to 3.0 A, di/dt = 6.0 A/µs (triple phase)

ILoad = 800 mA to 4.0 A, di/dt = 8.0 A/µs (quad phase)

Output capacitance = 44 µF per phase

−25

—

+25

V_SWxLOTR

Transient load regulation (overshoot/undershoot)

at 1.25 < V_SWxFB< 1.8 V

%

ILoad = 200 mA to 1.0 A, di/dt = 2.0 A/µs (single phase)

ILoad = 400 mA to 2.0 A, di/dt = 4.0 A/µs (dual phase)

ILoad = 600 mA to 3.0 A, di/dt = 6.0 A/µs (triple phase)

ILoad = 800 mA to 4.0 A, di/dt = 8.0 A/µs (quad phase)

Output capacitance = 44 µF per phase

−3.0

—

+3.0

I_RCS

DCM (skip mode) reverse current sense threshold

Current flowing from PGND to SWxLX

mA

µA

−200

—

200

—

I_SWxQ

Quiescent current

PFM mode

14

I_SWxQ

Quiescent current

Auto skip mode

—

160

200

240

—

250

I_{SWxQ_DP}

I_{SWxQ_QP}

R_ONSWxHS

R_ONSWxLS

R_SWxDIS

Quiescent current in dual phase PWM mode

Quiescent current in quad phase PWM mode

SWx high-side P-MOSFET R_DS(on)

320

µA

mΩ

Ω

480

135 ^[6]

80 ^[6]

SWx low-side N-MOSFET R_DS(on)

—

Discharge resistance

20

70

120

Regulator disabled and ramp down completed

[1] For VSWx configurations greater than 1.35 V, full parametric operation is guaranteed for 2.7 V < SWxVIN < 5.5 V. Below 2.7 V, the SWx regulators are

fully functional with degraded operation due to headroom limitation.

[2] For VSWx = 1.8 V, output capacitance should be kept at or below the maximum recommended value. Likewise, it is recommended to use the slow turn-

on/off ramp rate to ensure the output is discharged completely when it is disabled.

[3] VSWxIN must be connected to VIN to ensure proper device operation.

[4] Current limit applicable to SW1, SW2, SW3, SW4, and SW6

[5] Current limit applicable to SW5 to ensure maximum power requirement for the MEMC rail in i.MX8QM systems.

[6] Max R_DS(on)does not include bondwire resistance. Consider +50 % tolerance to account for bondwire and pin loss.

Table 54.ꢀRecommended external components

Symbol

Parameter

Min

Typ

Max

Unit

L

Output inductor

µH

Maximum inductor DC resistance 50 mΩ ^[1]

0.47

1.0

1.5

Minimum saturation current at full load: 3.0 A

C_out

Output capacitor

µF

Use 2 x 22 µF, 6.3 V X7T ceramic capacitor to reduce

output capacitance ESR.

—

44

—

C_in

Input capacitor

4.7 μF, 10 V X7R ceramic capacitor

4.7

[1] Keep inductor DCR as low as possible to improve regulator efficiency.

15.5 Type 2 buck regulator (SW7)

The PF8100/PF8200 also features one single phase low-voltage buck regulator (SW7)

with an input voltage range between 2.5 V and 5.5 V and an output voltage range from

1.0 V to 4.1 V.

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VIN

SW7IN

I

SENSE

SW7MODE

SW7ILIM

C

INSW7

CONTROLLER

L

SW7

SW7LX

SW7

DRIVER

SW7PHASE

C

OSW7

+

2

I C

slope

compensation

2 to 3 MHz

clock

INTERFACE

TYPE II INTERNAL

COMPENSATION

duty cycle

generator

R1

SW7FB

EA

R2

Z2

VSW7

DAC

aaa-028065

Figure 28.ꢀType 2 buck regulator block diagram

Buck regulator SW7 uses 5 bits to set the output voltage. The VSW7[4:0] sets the output

voltage during the run and the standby mode.

The SW7 is designed to have a fixed voltage for entire system operation. In the event a

system requires this regulator to change its output voltage during the system-on states,

when the SW7 is commanded to change its voltage via the I²C command, the output

will be discharged first and then enabled back to the new voltage level as stated in the

VSW7[4:0] bits.

The default output voltage configuration for the run and the standby modes is loaded

from the OTP_VSW7[4:0] registers upon power up.

Table 55.ꢀSW7 output voltage configuration

Set point

VSW7[4:0]

0 0000

0 0001

0 0010

0 0011

0 0100

0 0101

0 0110

0 0111

0 1000

0 1001

0 1010

0 1011

0 1100

V_SW7FB(V)

1.00

0

1

1.10

2

1.20

3

1.25

4

1.30

5

1.35

6

1.50

7

1.60

8

1.80

9

1.85

10

11

12

2.00

2.10

2.15

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Set point

13

VSW7[4:0]

0 1101

0 1110

0 1111

1 0000

1 0001

1 0010

1 0011

1 0100

1 0101

1 0110

1 0111

1 1000

1 1001

1 1010

1 1011

1 1100

1 1101

1 1110

1 1111

V_SW7FB(V)

2.25

2.30

2.40

2.50

2.80

3.15

3.20

3.25

3.30

3.35

3.40

3.50

3.80

4.00

4.10

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Regulator SW7 is provided with two bits to set its mode of operation.

• The SW7_RUN_MODE[1:0] bits allow the user to change the mode of operation of the

SW7 regulators during the run state. If the regulator was programmed as part of the

power up sequence, the SW7_RUN_MODE[1:0] bits are loaded with 0b11 (autoskip)

by default. Otherwise, it is loaded with 0b00 (disabled).

• The SW7_STBY_MODE[1:0] bits allow the user to change the mode of operation of

the SW7 regulators during the standby state. If the regulator was programmed as part

of the power up sequence, the SW7_STBY_MODE[1:0] bits are loaded with 0b11

(autoskip) by default. Otherwise it is loaded with 0b00 (disabled).

Table 56.ꢀSW7 regulator mode configuration

SW7_MODE[1:0]

Mode of operation

OFF

00

01

10

11

PWM mode

PFM mode

Autoskip mode

The SW7_MODE_I interrupt asserts the INTB pin when the SW7 regulator has changed

the mode of operation, provided the corresponding interrupt is not masked.

When the device toggles from run to standby mode, the SW7 output voltage

remains the same, unless the regulator is enabled/disabled by the corresponding

SW7_RUN_MODE[1:0] or SW7_STBY_MODE[1:0] bits.

The SW7ILIM [1:0] bits are used to program the current limit detection level of SW7.

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Table 57.ꢀSW7 current limit selection

SW7ILIM[1:0]

Typical current limit

00

01

10

11

2.1 A

2.6 A

3.0 A

4.5 A

Regulator SW7 use 3 bits (SWxPHASE[2:0]) to control the phase shift of the switching

frequency. Upon power up, the switching phase is defaulted to 0 degrees and can be

modified during the system-on states.

Table 58.ꢀSW7 phase configuration

SW7_PHASE[2:0]

Phase shift [degrees]

000

001

010

011

100

101

110

111

45

90

135

180

225

270

315

0

SW7 buck regulator provide 2 OTP bits to configure the value of the inductor used in the

power stage. The OTP_SW7_LSELECT[1:0] allow to choose the inductor as shown in

the following table.

Table 59.ꢀSW7 inductor selection bits

OTP_SW7_LSELECT[1:0]

Inductor value

1.0 µH

00

01

10

11

0.47 µH

1.5 µH

Reserved

15.5.1 Electrical characteristics

Table 60.ꢀType 2 buck regulator electrical characteristics

All parameters are specified at T_A= −40 to 105 °C, VIN = V_SW7IN= UVDET to 5.5 V, V_SW7FB= 1.8 V, I_SW7= 500 mA, typical

external component values, f_SW= 2.25 MHz, unless otherwise noted. Typical values are characterized at VIN = V_SW7IN= 5.0

V, V_SW7FB= 1.8 V, I_SW7= 500 mA, and T_A= 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

[1]

V_SW7IN

Operating input voltage range

V

UVDET

V_SW7FB+ 0.65

−2.0

—

5.5

1.2 V < V_SW7FB≤ 1.85 V, DCR ≤ 40 mΩ

[1]

V_SW7IN

Operating input voltage range

V

—

5.5

1.85 V < V_SW7FB< 4.1 V, DCR ≤ 40 mΩ

V_SW7ACC

Output voltage accuracy

PWM mode

%

—

2.0

0 ≤ I_SW7≤ 2.5 A

V_SW7ACC

Output voltage accuracy

PFM mode

%

−4.0

—

4.0

0 ≤ I_SW7≤ ΔI/2

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Symbol

t_PFMtoPWM

I_SW7

Parameter

Min

10

Typ

—

Max

—

Unit

µs

PFM to PWM transition time

Maximum output load

2500

—

mA

A

I_SW7LIM

Current limiter - inductor peak current detection

SW7ILIM = 00

1.6

2.0

2.4

2.1

2.6

3.0

2.5

3.1

3.7

I_SW7LIM

Current limiter - inductor peak current detection

SW7ILIM = 01

A

Current limiter - inductor peak current detection

SW7ILIM = 10

Current limiter - inductor peak current detection

SW7ILIM = 11

3.6

0.7

4.5

1.0

5.45

1.3

I_SW7NILIM

t_SW7RAMP

Negative current limit - inductor valley current detection

A

Soft-start ramp time during power up and power down

V_SW7FB= 1.8 V

µs

90

—

200

300

t_ONSW7

Turn on time

µs

100

180

From regulator enabled to 90 % of end value

V_SW7FB= 1.8 V

V_SW7OSH

η_SW7

Startup overshoot

−50

—

85

88

90

91

92

90

50

—

mV

%

Efficiency

PFM mode, 3.3 V, 1.0 mA, T_J= 125 °C

η_SW7

F_SWx

Efficiency

%

PFM mode, 3.3 V, 50 mA, T_J= 125 °C

Efficiency

%

PFM mode, 3.3 V, 100 mA, T_J= 125 °C

Efficiency

%

PWM mode, 3.3 V, 400 mA, T_J= 125 °C

Efficiency

%

PWM mode, 3.3 V, 1000 mA, T_J= 125 °C

Efficiency

%

PWM mode, 3.3 V, 2000 mA, T_J= 125 °C

PWM switching frequency range

Frequency set by CLK_FREQ[3:0]

MHz

1.9

—

2.5

50

3.15

—

T_ONminSW7

T_DBSW7

T_slew

Minimum on time

Deadband time

ns

—

3.0

—

Slewing time

10 % to 90 %

V_SW7IN= 5.5 V

—

5.0

1.0

ΔV_SW7

Output ripple

%

−1.0

Output cap ESR ~ 10 mΩ, 2 × 22 µF

V_SW7LOTR

Transient load regulation (overshoot/undershoot)

Transient load = 200 mA to 1.0 A step

di/dt = 2.0 A/ms

mV

−50

—

50

Cout = 20 µF effective

V_SW7FB= 1.8 V

I_RCS

DCM (skip mode) reverse current sense threshold

—

10

18

—

mA

µA

I_SW7Q

Quiescent current

PFM mode

I_SW7Q

Quiescent current

Auto skip mode

µA

—

150

—

250

R_ONSW7HS

R_ONSW7LS

R_SW7DIS

SW7 high-side P-MOSFET R_DS(on)

SW7 low-side N-MOSFET R_DS(on)

135 ^[2]

80 ^[2]

200

mΩ

Ω

—

SW7 discharge resistance (normal operation)

100

R_SW7TBB

SW7 discharge resistance during TBB mode

TBBEN = 1 and QPU_OFF state

kΩ

1.0

2

—

[1] VSW7IN must be connected to VIN to ensure proper operation.

[2] Max R_DS(on)does not include bondwire resistance. Consider +50 % tolerance to account for bondwire and pin loses.

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Table 61.ꢀRecommended external components

Symbol

Parameter

Min

Typ

Max

Unit

L

Output inductor

µH

Maximum inductor DC resistance 50 mΩ ^[1]

0.47

1.0

1.5

Minimum saturation current at full load: 3.0 A

C_out

Output capacitor

µF

Use 2 x 22 μF, 6.3 V X7T ceramic capacitor to reduce

output capacitance ESR

—

44

—

C_in

Input capacitor

4.7 μF, 10 V X7R ceramic capacitor

4.7

[1] Keep inductor DCR as low as possible to improve regulator efficiency.

15.6 Linear regulators

The PF8100/PF8200 has four low drop-out (LDO) regulators with the following features:

• 400 mA current capability

• Input voltage range from 2.5 V to 5.5 V

• Programmable output voltage between 1.5 V and 5.0 V

• Soft-start ramp control during power up (enable)

• Discharge mechanism during power down (disable)

• OTP programmable Load switch mode

2.5 to 5.5 V

VLDOxIN

V

BG1

LDOxEN

C

INLDOx

VLDOx

C

OLDOx

2

I C

INTERFACE

VLDOx[3:0]

discharge

aaa-028066

Figure 29.ꢀLDOx regulator block diagram

LDO1 and LDO2 share the same input supply; LDO12IN while LDO3 and LDO4 have

their own dedicated input supply pin, LDO3IN and LDO4IN respectively.

The four LDOs are provided with one bit to enable or disable its output during the

system-on states.

• When LDOx_RUN_EN = 0, the LDO is disabled during the run mode. If the regulator is

part of the power up sequence, this bit is set during the power up sequence. Otherwise

it is defaulted to 0.

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• When LDOx_STBY_EN = 0, the LDO is disabled during the standby mode. If

the regulator is part of the power up sequence, this bit is set during the power up

sequence. Otherwise it is defaulted to 0.

The mode of operation of the LDOx is selected on OTP via the OTP_LDOxLS bit.

Table 62.ꢀLDO operation description

LDOx_RUN_EN / LDOx_STBY_EN

OTP_LDOxLS

LDO operation mode

(Run or standby mode)

0

1

X

0

1

Disabled with output pull down active

Enabled in normal mode

Enabled in load switch configuration

The LDOs use four bits to set the output voltage.

• The VLDOx_RUN[3:0] sets the output voltage during the run mode.

• The VLDOx_STBY[3:0] sets the output voltage during standby mode.

The default output voltage configuration for the run and the standby mode is loaded from

the OTP_VLDOx[3:0] registers on power up.

Table 63.ꢀLDO output voltage configuration

Set point

VLDOx_RUN[3:0]

VLDOx_STBY[3 :0]

VLDOx output (V)

0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1.5

1

1.6

2

1.8

3

1.85

2.15

2.5

4

5

6

2.8

7

3.0

8

3.1

9

3.15

3.2

10

11

12

13

14

15

3.3

3.35

1.65

1.7

5.0

LDO2 can be controlled by hardware using the VSELECT and LDO2EN pins. When

controlling the LDO2 by hardware, the output voltage can be selectable by the VSELECT

pin as well as enable/disable by the LDO2EN pin.

15.6.1 LDO load switch operation

When the OTP_LDOxLS bit is set to 1, the corresponding LDO operates as a load

switch, allowing a pass-through from the LDOxVIN to the corresponding LDOxVOUT

output through a maximum 130 mΩ resistance. In this mode of operation, the input must

be kept inside the LDO operating input voltage range (2.5 V to 5.5 V)

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When the LDO regulator is set in Load switch mode, the LDOxEN bit is used to enable or

disable the switch.

15.6.2 LDO regulator electrical characteristics

Table 64.ꢀLDO regulator electrical characteristics

All parameters are specified at T_A= −40 to 105 °C, V_LDOxIN= 2.5 V to 5.5 V, V_LDOx= 1.8 V, I_LDOx= 100 mA, typical external

component values, unless otherwise noted. Typical values are characterized at V_LDOxIN= 5.5 V, V_LDOx= 1.8 V, I_LDOx= 100

mA, and T_A= 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Units

V_LDOxIN

LDOx operating input voltage range

1.5 V ≤ V_LDOx< 2.25 V

V

2.5

—

5.5

V_LDOxIN

LDOx operating input voltage range

2.25 V < V_LDOx< 5.0 V

V

VLDOxNOM + —

0.25

5.5

—

I_LDOx

Maximum load current

400

—

mA

%

V_LDOxTOL

Output voltage tolerance

1.5 V ≤ V_LDOx≤ 5.0 V

0 mA < I_LDOx≤ 400 mA

−3.0

—

3.0

V_LDOxLOR

V_LDOxLIR

I_LDOxLIM

Load regulation

Line regulation

—

0.1

—

0.20

20

mV/mA

mA

Current limit

I_LDOxwhen VLDOx is forced to V_LDOxNOM/2

450

—

850

7.0

1400

10

I_LDOxQ

Quiescent current (measured at T_A= 25 °C)

μA

R_DS(on)

Drop-out/load switch on resistance

V_LDOINx= 3.3 V (at T_J=125 °C)

mΩ

—

150 ^[1]

PSRR_VLDOx

TR_VLDOx

t_ONLDOx

DC PSRR

dB

μs

%

I_LDOx= 150 mA

VLDOx[3:0] = 0000 to 1111

V_LDOINx= V_LDOxINMIN

48

—

Turn on rise time (soft-start ramp)

10 % to 90 % of end value

V_LDOx= 3.3 V

—

220

—

360

400

3500

2.0

I_LDOx= 0.0 mA

Turn on time

Enable to 90 % of end value

V_LDOx= 5.0 V

I_LDOx= 0.0 mA

t_OFFLDOx

Turn off time

Disable to 10 % of initial value

V_LDOx= 5.0 V

—

I_LDOx= 0.0 mA

V_LDOxOSHT

Startup overshoot

V_LDOINx= V_LDOINxMIN

V_LDOx= 5.0 V

1.0

I_LDOx= 0.0 mA

V_LDOxLOTR

Transient load response

%

I_LDOx= 10 mA to 200 mA in 2.0 μs

−6.0

—

6.0

Peak of overshoot or undershoot of LDOx with

respect to final value

T_onLDOxLS

Load switch mode turn on rise time

150

300

µs

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Symbol

Parameter

Min

50

Typ

100

850

2.0

Max

300

1400

—

Units

R_dischLDOx

Output discharge resistance when LDO is disabled

LDO and Switch mode

Ω

I_LSxLIM

Load switch mode current limit when enabled

LSxILIM_EN = 1

mA

kΩ

450

1.0

R_LDOxTBB

LDOx pull down resistance during TBB mode

TBBEN = 1 & in QPU_OFF state

[1] Max R_DS(on)does not include bondwire resistance. Consider 40 % tolerance to account for bondwire and pin loses.

15.7 Voltage monitoring

The PF8100/PF8200 provides OV and UV monitoring capability for the following voltage

regulators:

• SW1 to SW7

• LDO1 to LDO4

A programmable UV threshold is selected via the OTP_SWxUV_TH[1:0] and

OTP_LDOxUV_TH[1:0] bits. UV threshold selection represents a percentage of the

nominal voltage programmed on each regulator.

Table 65.ꢀUV threshold configuration register

OTP_SWxUV_TH[1:0]

OTP_LDOxUV_TH[1:0]

UV threshold level

00

01

10

11

95 %

93 %

91 %

89 %

A programmable OV threshold is selected via the OTP_SWxOV_TH[1:0] and

OTP_LDOxOV_TH[1:0] bits. OV threshold selection represents a percentage of the

nominal voltage programmed on each regulator.

Table 66.ꢀOV threshold configuration register

OTP_SWxOV_TH

OTP_LDOxOV_TH

OV threshold level

00

01

10

11

105 %

107 %

109 %

111 %

Two functional bits are provided to program the UV debounce time for all the voltage

regulators.

Table 67.ꢀUV debounce timer configuration

UV_DB[1:0]

OV debounce Time

00

01

10

11

5 µs

15 µs

25 µs

40 µs

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The default value of the UV_DB[1:0] upon a full register reset is 0b10

Two functional bits to program the OV debounce time for all the voltage regulators.

Table 68.ꢀOV debounce timer configuration

OV_DB[1:0]

OV debounce Time

00

01

10

11

25 µs

50 µs

80 µs

125 µs

The default value of the OV_DB[1:0] upon a full register reset is 0b00

The VMON_EN bits enable or disable the OV/UV monitor for each one of the external

regulators (SWxVMON_EN, LDOxVMON_EN).

• When the VMON_EN bit of a specific regulator is 1, the voltage monitor for that specific

regulator is enabled.

• When the VMON_EN bit of a specific regulator is 0, the voltage monitor for that specific

regulator is disabled.

By default, the VMON_EN bits are set to 1 on power up.

When the I2C_SECURE_EN = 1, a secure write must be performed to set or clear the

VMON_EN bits to enable or disable the voltage monitoring for a specific regulator.

On enabling a regulator, the UV/OV monitor is masked until the corresponding regulator

reaches the point of regulation. If a voltage monitor is disabled, the UV_S and OV_S

indicators from that monitor are reset to 0.

Figure 30 shows the PF8100/PF8200 voltage monitoring architecture.

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SW1FB

SW1 VMON

OV

Hyst

OV

UV

Digital

Filter

OV_TH

UV_TH

OTP_SW1OV_TH[1:0]

PGOOD

GENERATOR

SW1_PG

OV/UV

TH Gen

VMON

LOGIC

CONTROL

Digital

Filter

OTP_SW1UV_TH[1:0]

SW1VMON_EN

UV

Hyst

SW6FB

SW6 VMON

OV

Hyst

OV

UV

Digital

Filter

OV_TH

UV_TH

OTP_SW6OV_TH[1:0]

PGOOD

GENERATOR

SW6_PG

OV/UV

TH Gen

VMON

LOGIC

CONTROL

Digital

Filter

OTP_SW6UV_TH[1:0]

SW6VMON_EN

UV

Hyst

SW7FB

SW7 VMON

OV

Hyst

OV

UV

Digital

Filter

OV_TH

UV_TH

OTP_SW7OV_TH[1:0]

MON_VREF

PGOOD

GENERATOR

SW7_PG

LDO1_PG

LDO4_PG

OV/UV

TH Gen

VMON

LOGIC

CONTROL

PGOOD

Digital

Filter

V

BG2

OTP_SW7UV_TH[1:0]

SW7VMON_EN

UV

Hyst

LDO1OUT

LDO1 VMON

OV

Hyst

OV

UV

Digital

Filter

OV_TH

UV_TH

OTP_LDO1OV_TH[1:0]

MON_VREF

PGOOD

GENERATOR

OV/UV

TH Gen

VMON

LOGIC

CONTROL

Digital

Filter

V

BG2

OTP_LDO1UV_TH[1:0]

LDO1VMON_EN

UV

Hyst

LDO4OUT

LDO4 VMON

OV

Hyst

OV

UV

Digital

Filter

OV_TH

UV_TH

OTP_LDO4OV_TH[1:0]

MON_VREF

PGOOD

GENERATOR

OV/UV

TH Gen

VMON

LOGIC

CONTROL

Digital

Filter

V

BG2

OTP_LDO4UV_TH[1:0]

LDO4VMON_EN

UV

Hyst

aaa-028067

Figure 30.ꢀVoltage monitoring architecture

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15.7.1 Electrical characteristics

Table 69.ꢀVMON Electrical characteristics

All parameters are specified at T_A= –40 °C to 105 °C, unless otherwise noted. Typical values are characterized at V_IN

= 5.0 V, V_xFB= 1.5 V (Type 1 Buck Regulator), 3.3 V (Type 2 Buck regulator, LDO Regulator), and T_A= 25 °C, unless

otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

I_QON

Block quiescent current, when block is enabled

One block per regulator

µA

—

10

—

13

I_OFF

Block leakage current when disabled

Voltage monitor settling time after enabled

Power good (UV) hysteresis

500

30

nA

µs

%

t_{ON_MON}

V_{xFBUVHysteresis}

Voltage difference between UV rising and

falling thresholds

0.5

—

1.0

V_{UV_Tol}

Undervoltage falling threshold accuracy

%

With respect to target feedback voltage

tolerance

−2

—

2

For type 2 switching regulator and LDO

regulator

For type 1 switching regulator when V_SWxFB

0.75 V

>

V_{UV_Tol}

Under voltage falling threshold accuracy

With respect to target feedback voltage

%

−3

—

3

For type 1 switching regulator when VSWxFB

≤ 0.75 V

Power good (UV) debounce time UV_DV = 00

Power good (UV) debounce time UV_DV = 01

Power good (UV) debounce time UV_DV = 10

Power good (UV) debounce time UV_DV = 11

Overvoltage rising threshold accuracy

2.5

10

20

25

5.0

15

30

40

7.5

20

40

55

µs

%

t_{UV_DB}

V_{OV_Tol}

With respect to target feedback voltage

tolerance

−2

—

2

For type 2 switching regulator and LDO

regulators

For type 1 switching regulator when V_SWxFB

0.75 V

>

≤

V_{OV_Tol}

Overvoltage rising threshold

%

With respect to target feedback voltage

tolerance

−3

—

3

For type 1 switching regulator when V_SWxFB

0.75 V

V_{xFBOVHysteresis}

Overvoltage (OV) hysteresis

Voltage difference between OV rising and

falling thresholds

0.5

1.0

Power good (OV) debounce time OV_DV = 00

Power good (OV) debounce time OV_DV = 01

Power good (OV) debounce time OV_DV = 10

Power good (OV) debounce time OV_DV = 11

20

35

55

90

30

40

µs

50

65

t_{OV_DB}

80

105

160

135

15.8 Clock management

The clock management provides a top-level management control scheme of internal

clock and external synchronization intended to be primarily used for the switching

regulators. The clock management incorporates various sub-blocks:

• Low power 100 kHz clock

• Internal high frequency clock with programmable frequency

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• Phase Locked Loop (PLL)

A digital clock management interface is in charge of supporting interaction among these

blocks.

The clock management provides clocking signals for the internal state machine, the

switching frequencies for the seven buck converters as well as the multiples of those

switching frequencies in order to enable phase shifting for multiple phase operation.

CLOCK MANAGEMENT BLOCK

INTERNAL

OSCILLATOR

100 kHz ± 5 %

100 kHz

system clock

DLY

f

+ 315°

+ 270°

+ 225°

+ 180°

+ 135°

+ 90°

1

16 to 24 MHz

0

16 to 24 MHz

CKL_FRQ[3:0]

FSS_RANGE

FSS_EN

MUX

1

INTERNAL

DIVIDE

BY

48

416.67 kHz

centered

OSCILLATOR

20 MHz ± 20 %

16 to 24 MHz

0

DIV 1

BY 8

333 kHz - 500 kHz

MUX

DIVIDE

BY

1 OR 6

SYNCIN

333 kHz - 500 kHz

1

333 to 500 kHz

or 2 - 3 MHz

+ 45°

FREQUENCY

WATCHDOG

FSYNC_RANGE

IN

OUT

PLL

X48

En

SYNCOUT

OTP_SYNCIN_EN

SYNCOUT_EN

I/O

aaa-028068

Figure 31.ꢀClock management architecture

15.8.1 Low frequency clock

A low power 100 kHz clock is provided for overall logic and digital control. Internal logic

and debounce timers are based on this 100 kHz clock.

15.8.2 High frequency clock

The PF8100/PF8200 features a high frequency clock with nominal frequency of 20 MHz.

Clock frequency is programmable over a range of ±20 % via the CLK_FREQ[3:0] control

bits.

15.8.3 Manual frequency tuning

The PF8100/PF8200 features a manual frequency tuning to set the switching frequency

of the high frequency clock. The CLK_FREQ [3:0] bits allow a manual frequency tuning of

the high frequency clock from 16 MHz to 24 MHz.

If a frequency change of two or more steps is requested by a single I²C command, the

device performs a gradual frequency change passing through all steps in between with a

5.2 µs time between each frequency step. When the frequency reaches the programmed

value, the FREQ_RDY_I asserts the INTB pin, provided it is not masked.

When the internal clock is used as the main frequency for the power generation, an

internal frequency divider by 8 is used to generate the switching frequency for all the

buck regulators. Adjusting the frequency of the high frequency clock allows for manual

tuning of the switching frequencies for the buck regulators from 2.0 MHz to 3.0 MHz.

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Table 70.ꢀManual frequency tuning configuration

CLK_FREQ[3:0]

High speed clock frequency

(MHz)

Switching regulators frequency

(MHz)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

20

2.500

21

2.625

22

2.750

23

2.875

24

3.000

Not used

16

Not used

2.000

17

2.125

18

2.250

19

2.375

Not used

The default switching frequency is set by the OTP_CLK_FREQ[3:0] bits.

Manual tuning cannot be applied when frequency spread-spectrum or external

clock synchronization is used. However, during external clock synchronization, it is

recommended to program the CLK_FREQ[3:0] bits to match the external frequency as

close as possible.

15.8.4 Spread-spectrum

The internal clock provides a programmable frequency spread spectrum with two ranges

for narrow spread and wide spread to help manage EMC in the automotive applications.

• When the FSS_EN = 1, the frequency spread-spectrum is enabled.

• When the FSS_EN = 0, the frequency spread-spectrum is disabled.

The default state of the FSS_EN bit upon a power up can be configured via the

OTP_FSS_EN bit.

The FSS_RANGE bit is provided to select the clock frequency range.

• When FSS_RANGE = 0, the maximum clock frequency range is ±5 %.

• When FSS_RANGE = 1, the maximum clock frequency range is ±10 %.

The default value of the FSS_RANGE bit upon a power up can be configured via the

OTP_FSS_RANGE bit.

The frequency spread-spectrum is performed at a 24 kHz modulation frequency when

the internal high frequency clock is used to generate the switching frequency for the

switching regulators. When the external clock synchronization is enabled, the spread-

spectrum is disabled.

Figure 32 shows implementation of spread-spectrum for the two settings.

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f

= 24 kHz

mod

5 %

f

osc

10.4 µs

SS_RANGE = 0

time

f

= 24 kHz

mod

10 %

f

osc

SS_RANGE = 1

time

5.2 µs

aaa-028069

Figure 32.ꢀSpread-spectrum waveforms

If the frequency spread-spectrum is enabled, the switching regulators should be set in

PWM mode to ensure clock synchronization at all time.

If the external clock synchronization is enabled, (SYNCIN_EN = 1), the spread spectrum

is disabled regardless of the value of the FSS_EN bit.

15.8.5 Clock Synchronization

An external clock can be fed via the SYNCIN pin to synchronize the switching regulators

to this external clock.

When the OTP_SYNCIN_EN = 0, the external clock synchronization is disabled. In this

case, the PLL is disabled, and the device always uses the internal high frequency clock

to generate the main frequency for the switching regulators.

When the OTP_SYNCIN_EN = 1, the external clock synchronization is enabled. In this

case, the internal PLL is always enabled and it uses either the internal high frequency

clock or the SYNCIN pin as it source to generate the main frequency for the switching

regulators.

If the SYNCIN function is not used, the pin should be grounded. If the external clock is

meant to start up after the PMIC has started, the SYNCIN pin must be maintained low

until the external clock is applied.

The SYNCIN pin is prepared to detect clock signals with a 1.8 V or 3.3 V amplitude and

within the frequency range set by the FSYNC_RANGE bit.

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• When the FSYNC_RANGE = 0, the input frequency range at SYNCIN pin should be

between 2000 kHz and 3000 kHz.

• When the FSYNC_RANGE = 1, the input frequency range at SYNCIN pin should be

between 333 kHz and 500 kHz.

The OTP_FSYNC_RANGE bit is used to select the default frequency range accepted in

the SYNCIN pin.

The external clock duty cycle at the SYNCIN pin should be between 40 % and 60 %. An

input frequency in the SYNCIN pin outside the range defined by the FSYNC_RANGE

bit is detected as invalid. If the external clock is not present or invalid, the device

automatically switches to the internal clock and sets the FSYNC_FLT_I interrupt, which in

turn asserts the INTB pin provided it is not masked.

The FSYNC_FLT_S bit is set to 1 as long as the input frequency is not preset or invalid,

and it is cleared to 0 when the SYNCIN has a valid input frequency.

The device switches back to the external switching frequency only when both, the

FSYNC_FLT_I interrupt has been cleared and the SYNCIN pin sees a valid frequency.

When the external clock is selected, the switching regulators should be set in PWM mode

to ensure clock synchronization at all time.

The SYNCOUT pin is used to synchronize an external device to the PF8100/PF8200.

The SYNCOUT pin outputs the main frequency used for the switching regulators in the

range of 2.0 MHz to 3.0 MHz. The SYNCOUT_EN bit can be used to enable or disable

the SYNCOUT feature via I²C during the system-on states.

• When SYNCOUT_EN = 0, the SYNCOUT feature is disabled and the pin is internally

pulled to ground.

• When SYNCOUT_EN = 1, the SYNCOUT pin toggles at the base frequency used by

the switching regulators.

The SYNCOUT function can be enabled or disabled by default by using the

OTP_SYNCOUT_EN bit.

Table 71.ꢀClock management specifications

All parameters are specified at T_A= −40 to 105 °C, unless otherwise noted. Typical values are characterized at V_IN= 5.0 V

and T_A= 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

Low frequency clock

I_Q100KHz

100 kHz clock quiescent current

100 kHz clock accuracy

—

3.0

5.0

µA

%

f_100KHzACC

−5.0

High frequency clock

f_20MHz

High frequency clock nominal frequency

MHz

via CLK_FREQ[3:0] = 0000

High frequency clock accuracy

Clock step transition time

—

20

—

f_20MzACC

−6.0

6.0

%

t_20MHzStep

µs

Minimum time to transition from one frequency

step to the next in manual tuning mode

—

5.2

—

FSS_RANGE

Spread-spectrum range

FSS_RANGE= 0

%

via CLK_FREQ[3:0]

±5.0

Spread-spectrum is done around center frequency

of 20 MHz

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Symbol

Parameter

Min

Typ

Max

Unit

FSS_RANGE

Spread-spectrum range

FSS_RANGE= 1

%

via CLK_FREQ[3:0]

—

±10

24

—

Spread-spectrum is done around center frequency

of 20 MHz

FSS_mod

Spread spectrum frequency modulation

kHz

Clock synchronization

f_SYNCIN

f_SYNCOUT

SYNCIN input frequency range

kHz

FSYNC_RANGE = 0

2000

333

—

3000

500

SYNCIN input frequency range

FSYNC_RANGE = 1

SYNCOUT output frequency range

via CLK_FREQ[3:0]

2000

—

1.0

—

3000

V_SYNCINLO

V_SYNCINHI

Input frequency low voltage threshold

Input frequency high voltage threshold

SYNCIN internal pull down resistance

Output frequency low voltage threshold

Output frequency high voltage threshold

—

0.3*VDDIO

V

0.7*VDDIO

0.475

—

V

R_{PD_SYNCIN}

V_SYNCOUTLO

V_SYNCOUTHI

__

0.4

—

MΩ

V

0

VDDIO − 0.5

V

15.9 Thermal monitors

The PF8100/PF8200 features ten temperature sensors spread around the die. These

sensors are located at the following locations:

1. Center of die

6. Vicinity of SW5

7. Vicinity of SW6

8. Vicinity of SW7

9. Vicinity of LDO1-2

10. Vicinity of LDO3-4

2. Vicinity of SW1

3. Vicinity of SW2

4. Vicinity of SW3

5. Vicinity of SW4

The temperature sensor at the center of the die is used to generate the thermal interrupts

and thermal shutdown.

The output of all temperature sensors are internally connected to the Analog MUX,

allowing the user to read the raw voltage equivalent to the temperature on each sensor.

The processor can read outputs of the other temperature sensors and take appropriate

action (such as reduce loading, or turning off regulator) if the temperature exceeds

desired limits at any point in the die.

Figure 33 shows a high level block diagram of the thermal monitoring architecture in

PF8100/PF8200.

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12-channel power management integrated circuit for high performance applications

Tsense

TEMP

SW5

Tsense

TEMP

SW6

Tsense

TEMP

SW7

Tsense

TEMP

LDO1-2

Tsense

TEMP

LDO3-4

COMP

V165C

(TSD)

V

Temp

Tsense

TEMP_IC

V155C

V140C

V125C

V110C

V95C

AMUX

DIGITAL LOGIC

STATE MACHINE

(THERMAL INTERRUPT

DECODING)

Tsense

TEMP

SW1

Tsense

TEMP

SW2

Tsense

TEMP

SW3

Tsense

TEMP

SW4

V80C

BG

aaa-028070

Figure 33.ꢀThermal monitoring architecture

Table 72.ꢀThermal monitor specifications

Symbol

Parameter ^[1]

Min

Typ

—

Max

Unit

V

V_IN

Operating voltage range of thermal circuit

Thermal sensor coefficient

UVDET

—

5.5

—

TCOF

V_TSROOM

–3.5

mV/ºC

V

Thermal sensor voltage

24 ºC

—

1.414

—

T_{SEN_RANGE}

V_{TEMP_MAX}

T_80C

Thermal sensor temperature range

Thermal sensor output voltage range

80 ºC temperature threshold

95 ºC temperature threshold

110 ºC temperature threshold

125 ºC temperature threshold

140 ºC temperature threshold

155 ºC temperature threshold

Thermal shutdown threshold

Thermal threshold hysteresis

Thermal shutdown hysteresis

–40

0

175

1.8

90

ºC

V

—

70

80

ºC

µs

T_95C

85

95

105

120

135

150

165

175

—

T_110C

100

115

130

145

155

—

110

125

140

155

165

5.0

10

T_125C

T_140C

T1_55C

T_SD

T_{WARN_HYS}

T_{SD_HYS}

t_temp_db

—

Debounce timer for temperature thresholds

(bidirectional)

—

10

—

t_Sinterval

Sampling interval time

ms

µs

When TMP_MON_AON = 1

—

3.0

—

t_Swindow

Sampling window

When TMP_MON_AON = 1

450

[1] Sensor temperature is calculated with the following formula: T [°C] = (V_TSENSE– 1.498 V) / TCOF, where V_TSENSEis the thermal sensor voltage measured

on the corresponding AMUX channel.

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aaa-028071

1.8

Tsense

voltage

(V)

1.6

1.4

1.2

1.0

0.8

-40

0

40

80

120

160

200

die temperature (°C)

Figure 34.ꢀThermal sensor voltage characteristics

As the temperature crosses the thermal thresholds, the corresponding interrupts are

set to notify the system. The processor may take appropriate action to bring down the

temperature (either by turning off external regulators, reducing load, or turning on a fan).

A 5 ºC hysteresis is implemented on a falling temperature in order to release the

corresponding THERM_x_S signal. When the shutdown threshold is crossed, the

PF8100/PF8200 initiates a thermal shutdown and it prevents from turning back on until

the 15 ºC thermal shutdown hysteresis is crossed as the device cools down.

The temperature monitor can be enabled or disabled via I²C with the TMP_MON_EN bit.

• When TMP_MON_EN = 0, the temperature monitor circuit is disabled.

• When TMP_MON_EN = 1, the temperature monitor circuit is enabled.

In the run state, the temperature sensor can operate in always on or sampling modes.

• When the TMP_MON_AON = 1, the device is always on during the run mode.

• When the TMP_MON_AON = 0, the device operates in sampling mode to reduce

current consumption in the system. In sampling mode, the thermal monitor is turned on

during 450 µs at a 3.0 ms sampling interval.

In the standby mode, the thermal monitor operates only in sampling mode as long as the

TMP_MON_EN = 1

Table 73.ꢀThermal monitor bit description

Bit(s)

Description

THERM_80_I, THERM_80_S, THERM_80_M

THERM_95_I, THERM_95_S, THERM_95_M

THERM_110_I, THERM_110_S, THERM_110_M

THERM_125_I, THERM_125_S, THERM_125_M

THERM_140_I, THERM_140_S, THERM_140_M

THERM_155_I, THERM_155_S, THERM_155_M

TMP_MON_EN

Interrupt, sense and mask bits for 80 ºC threshold

Interrupt, sense and mask bits for 95 ºC threshold

Interrupt, sense and mask bits for 110 ºC threshold

Interrupt, sense and mask bits for 125 ºC threshold

Interrupt, sense and mask bits for 140 ºC threshold

Interrupt, sense and mask bits for 155 ºC threshold

Disables temperature monitoring circuits when

cleared

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Bit(s)

Description

TMP_MON_AON

When set, the temperature monitoring circuit is always

ON.

When cleared, the temperature monitor operates in

sampling mode.

15.10 Analog multiplexer

A 24 channel Analog Multiplexer (AMUX) is provided to allow access to various internal

voltages within the PMIC. The selected voltage is buffered and made available on the

AMUX output pin during the system-on states.

When the AMUX_EN bit is 0, the AMUX block is disabled and the output remains pulled

down to ground.

When the AMUX_EN bit is 1, the AMUX block is enabled and the system may select the

channel to be read by using the AMUX_SEL[4:0] bits.

Table 74.ꢀAMUX channel selection

AMUX_EN

AMUX_SEL[4:0]

AMUX selection

Internal signal dividing ratio

0

X XXXX

AMUX disabled and pin

pulled-down to ground

N/A

1

0 0000

AMUX disabled in high

impedance mode

N/A

1

0 0001

0 0010

0 0011

0 0100

VIN

4

VSNVS

LICELL

SW1_FB

3.5

3

1.25 (1.8 V setting)

1 (all other settings)

1

0 0101

0 0110

0 0111

0 1000

0 1001

SW2_FB

SW3_FB

SW4_FB

SW5_FB

SW6_FB

1.25 (1.8 V setting)

1 (All other settings)

1.25 (1.8 V setting)

1 (all other settings)

1.25 (1.8 V setting)

1 (all other settings)

1.25 (1.8 V setting)

1 (all other settings)

1.25 (1.8 V setting)

1 (all other settings)

1

0 1010

0 1011

0 1100

0 1101

0 1110

0 1111

1 0000

1 0001

1 0010

1 0011

SW7_FB

LDO1

10/3.5 = 2.86

10/3 = 3.33

LDO2

10/3 = 3.33

LDO3

10/3 = 3.33

LDO4

10/3 = 3.33

TEMP_IC

TEMP_SW1

TEMP_SW2

TEMP_SW3

TEMP_SW4

1

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12-channel power management integrated circuit for high performance applications

AMUX_EN

AMUX_SEL[4:0]

1 0100

AMUX selection

TEMP_SW5

Internal signal dividing ratio

1

1 0101

TEMP_SW6

1

1 0110

TEMP_SW7

1

1 0111

TEMP_LDO1_2

TEMP_LDO3_4

Reserved

1

1 1000

1

1 1001 to 1 1111

N/A

All selectable input signals are conditioned internally to fall within an operating output

range from 0.3 V to 1.65 V, However, the AMUX pin is clamped to a maximum 2.5 V.

Table 75.ꢀAMUX specifications

Symbol

Parameter

Min

Typ

—

Max

5.5

Unit

V

V_IN

Operational voltage

UVDET

0.95

–6.25

—

I_REF

Current reference range

AMUX output voltage offset (input to output)

AMUX quiescent current

1.0

—

1.05

6.25

—

µA

mV

µA

µs

V_OFFSET

I_QAMUX

t_{AMUX_ON}

110

AMUX settling time (off to channel transition)

Max step size of 1.8 V; output cap 150 pF

—

50

t_{AMUX_CHG}

AMUX settling time (channel to channel transition)

Max step size of 1.8 V; output cap 150 pF

µs

—

50

V_CLAMP

AMUX clamping voltage

1.8

2.5

3.1

V

RA_{DIV_CH1}

Channel 1 Internal divider ratio

Input source = VIN

—

3.97

3.48

2.98

1.241

4.0

4.05

3.54

3.04

1.267

RA_{DIV_CH2}

RA_{DIV_CH3}

RA_{DIV_CH4_9}

Channel 2 internal divider ratio

Input source = VSNVS

—

3.5

Channel 3 internal divider ratio

Input source = LICELL

3.0

Channel 4 to 9 internal divider ratio

Input source = Type 1 regulators at 1.8 V

configuration

1.25

RA_{DIV_CH10}

Channel 10 internal divider ratio

Input source = Type 2 regulator

—

2.85

3.32

2.86

3.35

2.91

3.39

RA_{DIV_CH10_14}Channel 11 to 14 internal divider ratio

Input source = LDO regulators

15.11 Watchdog event management

A watchdog event may be started in two ways:

• The WDI pin toggles low due to a watchdog failure on the MCU

• The internal watchdog expiration counter reach the maximum value the WD timer is

allowed to expire

A watchdog event initiated by the WDI pin may perform a hard WD reset or a soft WD

reset as defined by the WDI_MODE bit. A watchdog event initiated by the internal

watchdog always performs a hard WD reset.

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15.11.1 Internal watchdog timer

The internal WD timer counts up and it expires when it reaches the value in the

WD_DURATION[3:0] register. When the WD timer starts counting, the WD_CLEAR

flag is set to 1. Clearing the WD_CLEAR flag within the valid window is interpreted as a

successful watchdog refresh and the WD timer gets reset. The MCU must write a 1 to

clear the WD_CLEAR flag.

The WD timer is reset when device goes into any of the off modes and does not start

counting until RESETBMCU is deasserted in the next power up sequence.

The OTP_WD_DURATION[3:0] selects the initial configuration for the watchdog window

duration between 1.0 ms and 32768 ms (typical values).

The watchdog window duration can change during the system-on states by modifying the

WD_DURATION[3:0] bits on the functional register map. If the WD_DURATION[3:0] bits

get changed during the system-on states, the WD timer is reset.

Table 76.ꢀWatchdog duration register

WD_DURATION[3:0]

Watchdog timer duration (ms)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

4

8

16

32

64

128

256

512

1024

2048

4096

8192

16384

32768

The WD_EXPIRE_CNT[2:0] counter is used to ensure no cyclic watchdog condition

occurs. When the WD_CLEAR flag is cleared successfully before the WD timer

expires, the WD_EXPIRE_CNT[2:0] is decreased by 1. Every time the WD

timer is not successfully refreshed, it gets reset and starts a new count and the

WD_EXPIRE_CNT[2:0] is increased by 2.

If WD_EXPIRE_CNT[2:0] = WD_MAX_EXPIRE[2:0], a WD event is initiated. The default

maximum amount of time the watchdog can expire before starting a WD Reset, is set

by the OTP_WD_MAX_EXPIRE[2:0]. Writing a value less than or equal to 0x02 on the

OTP_WD_MAX_EXPIRE causes the watchdog event to be initiated, as soon as the WD

Timer expires for the first time.

The OTP_WDWINDOW bit selects whether the watchdog is singled ended or window

mode.

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• When OTP_WDWINDOW = 0, the WD_CLEAR flag can be cleared within 100 % of the

watchdog timer.

• When OTP_WDWINDOW = 1, the WD_CLEAR flag can only be cleared within the

second half of the programmed watchdog timer. Clearing the WD_CLEAR flag within

the first half of the watchdog window is interpreted as a failure to refresh the watchdog.

WD_TIMER

100 % Window

WD_EXPIRE_CNT

WD refresh OK

0

WD refresh OK

WD refresh

NOK

1

WD refresh OK

WD refresh

NOK

2

WD_TIMER

Expired

WD refresh OK

WD refresh NOK

WD refresh

NOK

3

WD_TIMER

WD refresh OK

50 % Window

WD refresh

NOK

4

0

WD refresh OK

WD refresh

5

NOK

WD refresh

NOK

WD refresh OK

WD refresh NOK

n =

WD_MAX

_EXPIRE

WD_TIMER

Expired

WD EVENT

WD refresh NOK

aaa-028072

Figure 35.ꢀWatchdog timer operation

The watchdog function can be enabled or disabled by writing the WD_EN bit on the I²C

register map. When the I2C_SECURE_EN = 1, a secure write must be performed to

change the WD_EN bit.

• When WD_EN = 0 the internal watchdog timer operation is disabled.

• When WD_EN = 1 the internal watchdog timer operation is enabled.

The OTP_WD_EN bit is used to select the default status of the watchdog counter upon

power up.

The watchdog function can be programmed to be enabled or disabled during the

standby state by writing the WD_STBY_EN bit on the I²C register map. When the

I2C_SECURE_EN = 1, a secure write must be performed to modify the WD_STBY_EN

bit.

• When WD_STBY_EN = 0 the internal watchdog timer operation during standby is

disabled.

• When WD_STBY_EN = 1 the internal watchdog timer operation during standby is

enabled.

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The OTP_WD_STBY_EN bit selects whether the watchdog is active in standby mode by

default or not.

15.11.2 Watchdog reset behaviors

When a watchdog event is started, a watchdog (WD) reset is performed. There are two

types of watchdog reset:

• Soft WD reset

• Hard WD reset

A soft WD reset is used as a safe way for the MCU to force the PMIC to return to a

known default configuration without forcing a POR Reset on the MCU. During a soft WH

reset, the RESETBMCU remains deasserted all the time.

Upon a soft WD reset, a partial OTP register re-load is performed on the registers as

shown in Table 77.

Table 77.ꢀSoft WD register reset

Bit name

Register

Bits

Configuration registers

STANDBYINV

CTRL2

2

RUN_PG_GPO

STBY_PG_GPO

RESETBMCU_SEQ[7:0]

PGOOD_SEQ[7:0]

WD_EN

CTRL2

1

CRTL2

0

RESETBMCU PWRUP

PGOOD PWRUP

CTRL1

7:0

3

WD_DURATION[3:0]

WD_STBY_EN

WD CONFIG

CTRL1

3:0

2

WDI_STBY_ACTIVE

SW registers

CTRL1

1

SWx_WDBYPASS

SWx_PG_EN

SWx CONFIG1

SWx CONFIG2

SWx PWRUP

SWx MODE

1

0

SWxDVS_RAMP

SWxILIM[1:0]

5

4:3

2:0

7:0

5:4

3:2

1:0

7:0

4:0

6

SWxPHASE[2:0]

SWx_SEQ[7:0]

SWx_PDGRP[1:0]

SWx_STBY_MODE [1:0]

SWx RUN_MODE [1:0]

VSWx_RUN [7:0]

VSWx_STBY [7:0]

VSW7 [4:0]

SWx MODE

SWx RUN VOLT

SWx STBY VOLT

SW7 VOLT

SW6_VTTEN

SW6_CONFIG2

LDO registers

LDOx_WDBYPASS

LDOx_PG_EN

LDOx CONFIG1

1

0

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Bit name

Register

Bits

6:5

4

LDOx_PDGRP[1:0]

LDO2HW_EN

VSELECT_EN

LDOxLS

LDOx CONFIG2

LDO2 CONFIG2

LDOx CONFIG2

LDOx PWRUP

LDOx RUN VOLT

LDOx STBY VOLT

3

2

LDOx_RUN_EN

LDOx_STBY_EN

LDOx_SEQ [7:0]

VLDOx_RUN[3:0]

VLDOx_STBY[3:0]

1

0

7:0

3:0

A soft WD reset may require all or some regulators to be reset to their default OTP

configuration. In the event a regulator is required to keep its current configuration

during a soft WD reset, a watchdog bypass bit is provided for each regulator

(SWx_WDBYPASS / LDOx_WDBYPASS).

• When the WDBYPASS = 0, the watchdog bypass is disabled and the output of the

corresponding regulator is returned to its default OTP value during the soft WD reset.

• When the WDBYPASS = 1, the watchdog bypass is enabled and the output of the

corresponding regulator is not affected by the soft WD reset, keeping its current

configuration.

During a soft WD reset, only regulators that are activated in the power up sequence go

back to their default voltage configuration if their corresponding WDBYPASS = 0.

Switching regulators returning to their default voltages configuration, will gradually

reach the new output voltage using its DVS configuration. LDO regulators returning

to their default configuration, will change to the default output voltage configuration

instantaneously. Regulators with WDBYPASS = 0 and which are not activated during the

power up sequence will turn off immediately.

After all output voltages, have transitioned to their corresponding default values, the

device waits for at least 30 μs before returning to the run state and announces it has

finalized the soft WD reset by asserting the INTB pin, provided the WDI_I interrupt is not

masked.

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Soft WD Reset Behavior

WDI Event

WDI OK

WDI Event

WDI OK

Regulator with

WDBYPASS = 1

Configuration Maintained

Not in Power

up Sequence

Default OTP Configuration

WDBYPASS = 0

In Power up

Sequence

VSNVS

RESETBMCU

INTB

30 µs

Power Down

Sequence

System

ON

WD Reset

aaa-028073

Figure 36.ꢀSoft WD reset behavior

A hard WD reset is used to force a system power-on reset when the MCU has becomes

unresponsive. In this scenario, a full OTP register reset is performed.

During a hard WD reset, the device turn off all regulators and deassert RESETBMCU

as indicated by the power down sequence. If PGOOD is programmed as a GPO and

configured as part of the power up sequence, it will also be disabled accordingly.

After all regulator's outputs have gone through the power down sequence and the power

down delay is finished, the device waits for 30 µs before reloading the default OTP

configuration and gets ready to start a power up sequence if the XFAILB pin is not held

low externally.

Hard WD Reset Behavior

WDI Event

WD OK

WD Event

WD OK

Regulator

Outputs

Default OTP

VSNVS

RESETBMCU

Power down

Delay

30 µs

WD Reset

System

ON

Power Down

Sequence

Power Up

Sequence

aaa-028074

Figure 37.ꢀHard WD reset behavior

After a WD reset, the PMIC may enter the standby state depending on the status of

STANDBY pin.

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Every time a WD event occurs, the WD_EVENT_CNT[3:0] nibble is incremented.

To prevent continuous failures, if the WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0]

the state machine proceeds to the fail-safe transition. The MCU is expected to

clear the WD_EVENT_CNT[3:0] when it is able to do so in order to keep proper

operation. Upon power up, the WD_MAX_CNT[3:0] is loaded with the values on the

OTP_WD_MAX_CNT[3:0] bits.

Every time the device passes through the off states, the WD_EVENT_CNT[3:0] is reset

to 0x00, to ensure the counter has a fresh start after a device power down.

WD_EVENT_CNT

reset by MCU

0

WD EVENT

1

WD EVENT

2

WD EVENT

WD_EVENT_CNT

reset by Fail-safe

Transition

3

WD EVENT

4

WD EVENT

5

WD EVENT

n =

WD_MAX

_CNT

FAIL-SAFE

TRANSITION

aaa-028075

Figure 38.ꢀWatchdog event counter

16 I²C register map

The PF8100/PF8200 provide a complete set of registers for control and diagnostics of

the PMIC operation. The configuration of the device is done at two different levels.

At first level, the OTP Mirror registers provide the default hardware and software

configuration for the PMIC upon power up. These are one time programmable and

should be defined during the system development phase, and are not meant to be

modified during the application. See Section 17 "OTP/TBB and default configurations" for

more details on the OTP configuration feature.

At a second level, the PF8100/PF8200 provides a set of functional registers intended for

system configuration and diagnostics during the system operation. These registers are

accessible during the system-on states and can be modified at any time by the System

Control Unit.

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The device ID register provides general information about the PMIC.

• DEVICE_FAM[3:0]: indicates the PF8x00 family of devices

0100 (fixed)

• DEVICE_ID[3:0]: provides the device type identifier

0000 = PF8100

1000 = PF8200

Registers 0x02 and 0x03 provide a customizable program ID registers to identify the

specific OTP configuration programmed in the part.

• EMREV (Address 0x02): contains the MSB bits PROG_ID[8:11]

• PROG_ID (Address 0x03): contains the LSB bit PROG_ID[7:0]

16.1 PF8200 functional register map

RESET SIGNALS

R/W types

Read only

UVDET

Reset when VIN crosses UVDET threshold

Bits are loaded with OTP values (mirror register)

Reset when device goes to OFF mode

Self-clear after write

R

OFF_OTP

OFF_TOGGLE

SC

R/W

Read and Write

RW1C

R/SW

R/TW

Read, Write a 1 to clear

Read/Secure Write

Read/Write on TBB only

NO_VSNVS

Reset when BOS has no valid input

VIN < UVDET and coin cell < 1.8 V (VSNVS not present)

AD

DR

Register Name

R/W

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

00

01

02

03

04

05

06

07

08

09

0A

0B

DEVICE ID

REV ID

R

DEVICE_FAM[3:0]

FULL_LAYER_REV[3:0]

PROG_ID[11:8]

DEVICE_ID[3:0]

R

METAL_LAYER_REV[3:0]

EMREV

R

—

EMREV[2:0]

PROG ID

R

PROG_ID[7:0]

PWRDN_I

INT STATUS1

INT MASK1

INT SENSE1

THERM INT

THERM MASK

THERM SENSE

SW MODE INT

RW1C

R/W

R

SDWN_I

SDWN_M

—

FREQ_RDY_I

FREQ_RDY_M

—

CRC_I

PWRUP_I

XINTB_I

FSOB_I

VIN_OVLO_I

VIN_OVLO_M

VIN_OVLO_S

THERM_80_I

THERM_80_M

THERM_80_S

SW1_MODE_I

SW1_MODE_M

CRC_M

PWRUP_M

PWRDN_M

—

XINTB_M

FSOB_M

—

XINTB_S

FSOB_S

RW1C

R/W

R

WDI_I

WDI_M

WDI_S

—

FSYNC_FLT_I

FSYNC_FLT_M

FSYNC_FLT_S

SW7_MODE_I

SW7_MODE_M

THERM_155_I

THERM_155_M

THERM_155_S

SW6_MODE_I

SW6_MODE_M

THERM_140_I

THERM_140_M

THERM_140_S

SW5_MODE_I

SW5_MODE_M

THERM_125_I

THERM_125_M

THERM_125_S

SW4_MODE_I

SW4_MODE_M

THERM_110_I

THERM_110_M

THERM_110_S

SW3_MODE_I

SW3_MODE_M

THERM_95_I

THERM_95_M

THERM_95_S

SW2_MODE_I

SW2_MODE_M

RW1C

SW MODE MASK R/W

—

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

SW ILIM INT

RW1C

—

SW7_ILIM_I

SW7_ILIM_M

SW7_ILIM_S

—

SW6_ILIM_I

SW6_ILIM_M

SW6_ILIM_S

—

SW5_ILIM_I

SW5_ILIM_M

SW5_ILIM_S

—

SW4_ILIM_I

SW4_ILIM_M

SW4_ILIM_S

LDO4_ILIM_I

LDO4_ILIM_M

LDO4_ILIM_S

SW4_UV_I

SW3_ILIM_I

SW3_ILIM_M

SW3_ILIM_S

LDO3_ILIM_I

LDO3_ILIM_M

LDO3_ILIM_S

SW3_UV_I

SW2_ILIM_I

SW2_ILIM_M

SW2_ILIM_S

LDO2_ILIM_I

LDO2_ILIM_M

LDO2_ILIM_S

SW2_UV_I

SW1_ILIM_I

SW1_ILIM_M

SW1_ILIM_S

LDO1_ILIM_I

LDO1_ILIM_M

LDO1_ILIM_S

SW1_UV_I

SW ILIM MASK

SW ILIM SENSE

LDO ILIM INT

LDO ILIM MASK

LDO ILIM SENSE

SW UV INT

R/W

R

RW1C

R/W

R

—

RW1C

R/W

R

SW7_UV_I

SW7_UV_M

SW7_UV_S

SW7_OV_I

SW7_OV_M

SW7_OV_S

—

SW6_UV_I

SW6_UV_M

SW6_UV_S

SW6_OV_I

SW6_OV_M

SW6_OV_S

—

SW5_UV_I

SW5_UV_M

SW5_UV_S

SW5_OV_I

SW5_OV_M

SW5_OV_S

—

SW UV MASK

SW UV SENSE

SW OV INT

SW4_UV_M

SW4_UV_S

SW4_OV_I

SW3_UV_M

SW3_UV_S

SW3_OV_I

SW2_UV_M

SW2_UV_S

SW2_OV_I

SW1_UV_M

SW1_UV_S

SW1_OV_I

RW1C

R/W

R

SW OV MASK

SW OV SENSE

LDO UV INT

SW4_OV_M

SW4_OV_S

LDO4_UV_I

LDO4_UV_M

LDO4_UV_S

SW3_OV_M

SW3_OV_S

LDO3_UV_I

LDO3_UV_M

LDO3_UV_S

SW2_OV_M

SW2_OV_S

LDO2_UV_I

LDO2_UV_M

LDO2_UV_S

SW1_OV_M

SW1_OV_S

LDO1_UV_I

LDO1_UV_M

LDO1_UV_S

RW1C

R/W

R

LDO UV MASK

LDO UV SENSE

—

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

95 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

AD

DR

Register Name

R/W

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

21

22

23

24

25

26

27

LDO OV INT

RW1C

R/W

R

—

LDO4_OV_I

LDO4_OV_M

LDO4_OV_S

PWRON_2S_I

PWRON_2S_M

—

LDO3_OV_I

LDO3_OV_M

LDO3_OV_S

PWRON_1S_I

PWRON_1S_M

—

LDO2_OV_I

LDO2_OV_M

LDO2_OV_S

PWRON_REL_I

PWRON_REL_M

—

LDO1_OV_I

LDO OV MASK

LDO OV SENSE

PWRON INT

PWRON MASK

PWRON SENSE

SYS INT

—

LDO1_OV_M

LDO1_OV_S

PWRON_PUSH_I

PWRON_PUSH_M

PWRON_S

—

RW1C

R/W

R

BGMON_I

BGMON_M

BGMON_S

EWARN_I

PWRON_8S_I

PWRON_8S_M

—

PWRON_4S_I

PWRON_4S_M

—

PRON_3S_I

PRON_3S_M

—

R

PWRON_I

OV_I

UV_I

ILIM_I

MODE_I

STATUS2_I

STATUS1_I

29

2A

HARD FAULT

FLAGS

RW1C

R/SW

—

PU_FAIL

WD_FAIL

REG_FAIL

TSD_FAIL

FSOB FLAGS

FSOB_ASS_NOK

FSOB_SFAULT

_NOK

FSOB_WDI_NOK

FSOB_WDC_NOK

FSOB_HFAULT_

NOK

2B

2C

2D

2E

2F

30

31

FSOB SELECT

ABIST OV1

ABIST OV2

ABIST UV1

ABIST UV2

TEST FLAGS

ABIST RUN

R/W

—

FSOB_SOFTFAULT FSOB_WDI

FSOB_WDC

AB_SW2_OV

AB_LDO2_OV

AB_SW2_UV

AB_LDO2_UV

TRIM_NOK

—

FSOB_HARDFAULT

AB_SW1_OV

AB_LDO1_OV

AB_SW1_UV

AB_LDO1_UV

OTP_NOK

R/SW

R/TW

R/SW

AB_SW7_OV

AB_SW6_OV

AB_SW5_OV

AB_SW4_OV

AB_LDO4_OV

AB_SW4_UV

AB_LDO4_UV

VSELECT_S

—

AB_SW3_OV

AB_LDO3_OV

AB_SW3_UV

AB_LDO3_UV

STEST_NOK

—

AB_SW7_UV

AB_SW6_UV

AB_SW5_UV

—

LDO2EN_S

—

AB_RUN

33

34

35

36

37

38

39

3A

RANDOM GEN

RANDOM CHK

VMONEN1

VMONEN2

CTRL1

R

RANDOM_GEN[7:0]

RANDOM_CHK[7:0]

R/W

R/SW

R/W

—

SW7VMON_EN

—

SW6VMON_EN

—

SW5VMON_EN

SW4VMON_EN

LDO4VMON_EN

WD_EN

SW3VMON_EN

LDO3VMON_EN

WD_STBY_EN

STANDBYINV

—

SW2VMON_EN

LDO2VMON_EN

SW1VMON_EN

LDO1VMON_EN

—

VIN_OVLO_EN VIN_OVLO_SDWN

VIN_OVLO_DBNC[1:0]

OV_DB[1:0]

WDI_MODE

—

TMP_MON_EN

TMP_MON_AON

WDI_STBY_ACTIVE I2C_SECURE_EN

CTRL2

LPM_OFF

—

RUN_PG_GPO

PMIC_OFF

STBY_PG_GPO

INTB_TEST

CTRL3

UV_DB[1:0]

PWRUP CTRL

—

PWRDWN_MODE

PGOOD_PDGRP[1:0]

RESETBMCU_PDGRP[1:0]

SEQ_TBASE[1:0]

3C

RESETBMCU

PWRUP

R/W

RESETBMCU_SEQ[7:0]

PGOOD_SEQ[7:0]

3D

3E

3F

40

41

42

43

44

45

46

47

PGOOD PWRUP

PWRDN DLY1

PWRDN DLY2

FREQ CTRL

R/W

GRP4_DLY[1:0]

GRP3_DLY[1:0]

—

GRP2_DLY[1:0]

GRP1_DLY[1:0]

TRESET[1:0]

—

RESETBMCU_DLY[1:0]

SYNCOUT_EN

FSYNC_RANGE

FSS_EN

FSS_RANGE

COINCHG_OFF

PWRON_DBNC [1:0]

CLK_FREQ[3:0]

VCOIN[3:0]

PWRON_RST_EN

WD_DURATION[3:0]

COINCELL CTRL R/W

—

COINCHG_EN

PWRON

R/W

—

WD CONFIG

WD CLEAR

WD EXPIRE

WD COUNTER

R/W

—

R/W1C

R/W

—

WD_CLEAR

WD_MAX_EXPIRE[2:0]

WD_EXPIRE_CNT[2:0]

WD_EVENT_CNT [3:0]

R/W

WD_MAX_CNT [3:0]

FAULT

R/W

FAULT_MAX_CNT[3:0]

FAULT_CNT [3:0]

COUNTER

48

FSAFE

COUNTER

R/W

—

FS_CNT [3:0]

49

4A

FAULT TIMERS

AMUX

R/W

—

TIMER_FAULT[3:0]

AMUX_EN

AMUX_SEL [4:0]

4D

SW1 CONFIG1

R/W

SW1_UV_

BYPASS

SW1_OV_BYPASS

—

SW1_ILIM_BYPASS SW1_UV_STATE

SW1_OV_STATE

SW1_ILIM_STATE

SW1PHASE[2:0]

SW1_WDBYPASS

SW1_PG_EN

4E

4F

50

51

52

SW1 CONFIG2

SW1 PWRUP

SW1 MODE

R/W

SW1_FLT_REN

SW1DVS_RAMP

SW1_PDGRP[1:0]

SW1ILIM[1:0]

SW1_SEQ[7:0]

SW1_STBY_MODE[1:0]

VSW1_RUN[7:0]

VSW1_STBY[7:0]

—

SW1_RUN_MODE[1:0]

SW1 RUN VOLT

SW1 STBY VOLT R/W

55

SW2 CONFIG1

R/W

SW2_UV_

BYPASS

SW2_OV_BYPASS

—

SW2_ILIM_BYPASS SW2_UV_STATE

SW2_OV_STATE

SW2_ILIM_STATE

SW2_WDBYPASS

SW2PHASE[2:0]

SW2_PG_EN

56

57

58

59

5A

SW2 CONFIG2

SW2 PWRUP

SW2 MODE1

R/W

SW2_FLT_REN

SW2DVS_RAMP

SW2_PDGRP[1:0]

SW2ILIM[1:0]

SW2_SEQ[7:0]

SW2_STBY_MODE[1:0]

VSW2_RUN[7:0]

VSW2_STBY[7:0]

—

SW2_RUN_MODE[1:0]

SW2 RUN VOLT

SW2 STBY VOLT R/W

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

96 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

AD

DR

Register Name

R/W

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

5D

SW3 CONFIG1

R/W

SW3_UV_

BYPASS

SW3_OV_BYPASS

—

SW3_ILIM_BYPASS SW3_UV_STATE

SW3_OV_STATE

SW3_ILIM_STATE

SW3_WDBYPASS

SW3PHASE[2:0]

SW3_PG_EN

5E

5F

60

61

62

SW3 CONFIG2

SW3 PWRUP

SW3 MODE1

R/W

SW3_FLT_REN

SW3DVS_RAMP

SW3ILIM[1:0]

SW3_SEQ[7:0]

—

SW3_PDGRP[1:0]

SW3_STBY_MODE[1:0]

SW3_RUN_MODE[1:0]

SW3 RUN VOLT

VSW3_RUN[7:0]

VSW3_STBY[7:0]

SW3 STBY VOLT R/W

65

SW4 CONFIG1

R/W

SW4_UV_

BYPASS

SW4_OV_BYPASS

—

SW4_ILIM_BYPASS SW4_UV_STATE

SW4_OV_STATE

SW4_ILIM_STATE

SW4_WDBYPASS

SW4_PG_EN

66

67

68

69

6A

SW4 CONFIG2

SW4 PWRUP

SW4 MODE1

R/W

SW4_FLT_REN

SW4DVS_RAMP

SW4ILIM[1:0]

SW4PHASE[2:0]

SW4_SEQ[7:0]

—

SW4_PDGRP[1:0]

SW4_STBY_MODE[1:0]

SW4_RUN_MODE[1:0]

SW4 RUN VOLT

VSW4_RUN[7:0]

VSW4_STBY[7:0]

SW4 STBY VOLT R/W

6D

SW5 CONFIG1

R/W

SW5_UV_

BYPASS

SW5_OV_BYPASS

—

SW5_ILIM_BYPASS SW5_UV_STATE

SW5_OV_STATE

SW5_ILIM_STATE

SW5_WDBYPASS

SW5_PG_EN

6E

6F

70

71

72

SW5 CONFIG2

SW5 PWRUP

SW5 MODE1

R/W

SW5_FLT_REN

SW5DVS_RAMP

SW5_PDGRP[1:0]

SW5ILIM[1:0]

SW5_SEQ[7:0]

SW5_STBY_MODE[1:0]

VSW5_RUN[7:0]

VSW5_STBY[7:0]

SW5PHASE[2:0]

—

SW5_RUN_MODE[1:0]

SW5 RUN VOLT

SW5 STBY VOLT R/W

75

SW6 CONFIG1

R/W

SW6_UV_

BYPASS

SW6_OV_BYPASS

SW6_ILIM_BYPASS SW6_UV_STATE

SW6_OV_STATE

SW6_ILIM_STATE

SW6_WDBYPASS

SW6PHASE[2:0]

SW6_PG_EN

76

77

78

79

7A

SW6 CONFIG2

SW6 PWRUP

SW6 MODE1

R/W

SW6_FLT_REN SW6_VTTEN

SW6DVS_RAMP

SW6_PDGRP[1:0]

SW6ILIM[1:0]

SW6_SEQ[7:0]

—

SW6_STBY_MODE[1:0]

SW6_RUN_MODE[1:0]

SW6 RUN VOLT

VSW6_RUN[7:0]

VSW6_STBY[7:0]

SW6 STBY VOLT R/W

7D

SW7 CONFIG1

R/W

SW7_UV_

BYPASS

SW7_OV_BYPASS

—

SW7_ILIM_BYPASS SW7_UV_STATE

SW7_OV_STATE

SW7_ILIM_STATE

SW7_WDBYPASS

SW7_PG_EN

7E

7F

80

81

SW7 CONFIG2

SW7 PWRUP

SW7 MODE1

R/W

SW7_FLT_REN

—

SW7ILIM[1:0]

SW7_SEQ[7:0]

SW7PHASE[2:0]

—

SW7_PDGRP[1:0]

—

SW7_STBY_MODE[1:0]

SW7_RUN_MODE[1:0]

SW7 RUN VOLT

VSW7[4:0]

85

86

LDO1 CONFIG1

LDO1 CONFIG2

LDO1 PWRUP

R/W

LDO1_UV_

BYPASS

LDO1_OV_BYPASS LDO1_ILIM_

BYPASS

LDO1_UV_STATE

—

LDO1_OV_STATE

—

LDO1_ILIM_STATE

—

LDO1_WDBYPASS

LDO1_PG_EN

LDO1_FLT_

REN

LDO1_PDGRP[1:0]

LDO1_RUN_EN

LDO1_STBY_EN

87

88

89

LDO1_SEQ[7:0]

LDO1 RUN VOLT R/W

—

VLDO1_RUN[3:0]

VLDO1_STBY[3:0]

LDO1 STBY

VOLT

R/W

8B

8C

LDO2 CONFIG1

LDO2 CONFIG2

LDO2 PWRUP

R/W

LDO2_UV_

BYPASS

LDO2_OV_BYPASS LDO2_ILIM_

BYPASS

LDO2_UV_STATE

LDO2HW_EN

LDO2_OV_STATE

VSELECT_EN

LDO2_ILIM_STATE

LDO2_WDBYPASS

LDO2_RUN_EN

LDO2_PG_EN

LDO2_FLT_

REN

LDO2_PDGRP[1:0]

—

LDO2_STBY_EN

8D

8E

8F

LDO2_SEQ[7:0]

LDO2 RUN VOLT R/W

—

VLDO2_RUN[3:0]

VLDO2_STBY[3:0]

LDO2 STBY

VOLT

R/W

91

92

LDO3 CONFIG1

LDO3 CONFIG2

LDO3 PWRUP

R/W

LDO3_UV_

BYPASS

LDO3_OV_BYPASS LDO3_ILIM_

BYPASS

LDO3_UV_STATE

—

LDO3_OV_STATE

—

LDO3_ILIM_STATE

—

LDO3_WDBYPASS

LDO3_RUN_EN

LDO3_PG_EN

LDO3_FLT_

REN

LDO3_PDGRP[1:0]

LDO3_STBY_EN

93

94

LDO3_SEQ[7:0]

LDO3 RUN VOLT R/W

—

VLDO3_RUN[3:0]

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

97 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

AD

DR

Register Name

R/W

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

95

LDO3 STBY

VOLT

R/W

—

VLDO3_STBY[3:0]

97

98

LDO4 CONFIG1

LDO4 CONFIG2

LDO4 PWRUP

R/W

LDO4_UV_

BYPASS

LDO4_OV_BYPASS LDO4_ILIM_

BYPASS

LDO4_UV_STATE

—

LDO4_OV_STATE

—

LDO4_ILIM_STATE

—

LDO4_WDBYPASS

LDO4_RUN_EN

LDO4_PG_EN

LDO4_FLT_

REN

LDO4_PDGRP[1:0]

LDO4_STBY_EN

99

9A

9B

LDO4_SEQ[7:0]

LDO4 RUN VOLT R/W

—

VLDO4_RUN[3:0]

VLDO4_STBY[3:0]

LDO4 STBY

VOLT

R/W

9D

9F

VSNVS CONFIG1 R/W

—

VSNVSVOLT [1:0]

PAGE SELECT

R/TW

PAGE[2:0]

16.2 PF8200 OTP mirror register map (page 1)

Reset types

OFF_OTP

OTP

Register loads the OTP mirror register values during power up

Register available in OTP bank only, reset from fuses when VIN crosses UVDET threshold

Reset when BOS has no valid input. VIN < UVDET and coin cell < 1.8 V (VSNVS not present)

VSNVS

ADDR Register name

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

A0

A1

A2

A3

A4

OTP FSOB

SELECT

—

OTP_FSOB_

ASS_EN

OTP_FSOB_

SOFTFAULT

OTP_FSOB_

WDI

OTP_FSOB_

WDC

OTP_FSOB_

HARDFAULT

OTP I2C

—

OTP_I2C_

CRC_EN

OTP_I2C_ADD[2:0]

SECURE_EN

OTP CTRL1

OTP CTRL2

OTP CTRL3

—

OTP_EWARN_TIME[1:0]

OTP_FS_

BYPASS

OTP_

OTP_PG_

ACTIVE

OTP_PG_CHECK

STANDBYINV

OTP_FSS_EN

OTP_VTT_PDOWN

OTP_FSS_RANGE

OTP_SW6_VTTEN

—

OTP_XFAILB_EN

OTP_VIN_

OVLO_EN

OTP_VIN_OVLO_DBNC[1:0]

OVLO_SDWN

OTP_SW5CONFIG[1:0]

OTP_SW4CONFIG[1:0]

OTP_SW1CONFIG[1:0]

A5

A6

OTP FREQ

CTRL

OTP_SW_MODE

—

OTP_SYNCIN_

EN

OTP_SYNCOUT_

EN

OTP_FSYNC_

RANGE

OTP_CLK_FREQ[3:0]

OTP_VCOIN[3:0]

OTP

—

COINCELL

CTRL

A7

A8

OTP PWRON

—

OTP_PWRON_

MODE

OTP_PWRON_DBNC[1:0]

OTP_PWRON_RST_

EN

OTP_TRESET[1:0]

OTP WD

CONFIG

OTP_WDI_

MODE

OTP_WDI_INV

—

OTP_WD_EN

—

OTP_WD_

STBY_EN

OTP_WDI_

OTP_

STBY_ACTIVE

WDWINDOW

A9

AA

AB

AC

OTP WD

EXPIRE

—

OTP_WD_MAX_EXPIRE[2:0]

OTP WD

COUNTER

OTP_WD_DURATION[3:0]

OTP_WD_MAX_CNT [3:0]

OTP FAULT

COUNTERS

OTP_FS_MAX_CNT[3:0]

OTP_FAULT_MAX_CNT[3:0]

OTP_TIMER_FAULT[3:0]

OTP FAULT

TIMERS

—

OTP_FS_OK_TIMER[2:0]

AD

AE

AF

OTP PWRDN

DLY1

OTP_GRP4_DLY[1:0]

OTP_GRP3_DLY[1:0]

OTP_GRP2_DLY[1:0]

—

OTP_GRP1_DLY[1:0]

OTP PWRDN

DLY2

OTP_PD_SEQ_DLY[1:0]

—

OTP_RESETBMCU_DLY[1:0]

OTP_SEQ_TBASE[1:0]

OTP PWRUP

CTRL

—

OTP_PWRDWN_

MODE

OTP_PGOOD_PDGRP[1:0]

OTP_RESETBMCU_PDGRP[1:0]

B0

OTP

OTP_RESETBMCU_SEQ[7:0]

RESETBMCU

PWRUP

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

98 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

ADDR Register name

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

B1

OTP PGOOD

PWRUP

OTP_PGOOD_SEQ[7:0]

B2

B3

B4

B5

OTP SW1

VOLT

OTP_VSW1[7:0]

OTP SW1

PWRUP

OTP_SW1_SEQ[7:0]

OTP SW1

CONFIG1

OTP_SW1UV_TH[1:0]

OTP_SW1OV_TH[1:0]

OTP_SW1_PDGRP[1:0]

OTP_SW1ILIM[1:0]

OTP SW1

CONFIG2

OTP_SW1_LSELECT[1:0]

OTP_SW1PHASE[2:0]

OTP_SW1DVS_

OTP_SW1_PG_

EN

OTP_SW1_

WDBYPASS

RAMP

B6

B7

B8

B9

OTP SW2

VOLT

OTP_VSW2[7:0]

OTP SW2

PWRUP

OTP_SW2_SEQ[7:0]

OTP SW2

CONFIG1

OTP_SW2UV_TH[1:0]

OTP_SW2OV_TH[1:0]

OTP_SW3OV_TH[1:0]

OTP_SW4OV_TH[1:0]

OTP_SW5OV_TH[1:0]

OTP_SW6OV_TH[1:0]

OTP_SW7OV_TH[1:0]

OTP_SW2_PDGRP[1:0]

OTP_SW2ILIM[1:0]

OTP SW2

CONFIG2

OTP_SW2_LSELECT[1:0]

OTP_SW2PHASE[2:0]

OTP_SW2DVS_

OTP_SW2_PG_

EN

OTP_SW2_

WDBYPASS

RAMP

BA

BB

BC

BD

OTP SW3_

VOLT

OTP_VSW3[7:0]

OTP SW3

PWRUP

OTP_SW3_SEQ[7:0]

OTP SW3

CONFIG1

OTP_SW3UV_TH[1:0]

OTP_SW3_PDGRP[1:0]

OTP_SW3ILIM[1:0]

OTP SW3

CONFIG2

OTP_SW3_LSELECT[1:0]

OTP_SW3PHASE[2:0]

OTP_SW3DVS_

OTP_SW3_PG_

EN

OTP_SW3_

WDBYPASS

RAMP

BE

BF

C0

C1

OTP SW4

VOLT

OTP_VSW4[7:0]

OTP SW4

PWRUP

OTP_SW4_SEQ[7:0]

OTP SW4

CONFIG1

OTP_SW4UV_TH[1:0]

OTP_SW4_PDGRP[1:0]

OTP_SW4ILIM[1:0]

OTP SW4

CONFIG2

OTP_SW4_LSELECT[1:0]

OTP_SW4PHASE[2:0]

OTP_SW4DVS_

OTP_SW4_PG_

EN

OTP_SW4_

WDBYPASS

RAMP

C2

C3

C4

C5

OTP SW5

VOLT

OTP_VSW5[7:0]

OTP SW5

PWRUP

OTP_SW5_SEQ[7:0]

OTP SW5

CONFIG1

OTP_SW5UV_TH[1:0]

OTP_SW5_PDGRP[1:0]

OTP_SW5ILIM[1:0]

OTP SW5

CONFIG2

OTP_SW5_LSELECT[1:0]

OTP_SW5PHASE[2:0]

OTP_SW5DVS_

OTP_SW5_PG_

EN

OTP_SW5_

WDBYPASS

RAMP

C6

C7

C8

C9

OTP SW6

VOLT

OTP_VSW6[7:0]

OTP SW6

PWRUP

OTP_SW6_SEQ[7:0]

OTP SW6

CONFIG1

OTP_SW6UV_TH[1:0]

OTP_SW6_PDGRP[1:0]

OTP_SW6ILIM[1:0]

OTP SW6

CONFIG2

OTP_SW6_LSELECT[1:0]

OTP_SW6PHASE[2:0]

OTP_SW6DVS_

RAMP

OTP_SW6_PG_

EN

OTP_SW6_

WDBYPASS

CA

CB

CC

CD

OTP SW7

VOLT

—

OTP_VSW7[4:0]

OTP SW7

PWRUP

OTP_SW7_SEQ[7:0]

OTP SW7

CONFIG1

OTP_SW7UV_TH[1:0]

OTP_SW7_PDGRP[1:0]

—

OTP_SW7ILIM[1:0]

OTP SW7

CONFIG2

OTP_SW7_LSELECT[1:0]

OTP_SW7PHASE[2:0]

OTP_SW7_PG_

EN

OTP_SW7_

WDBYPASS

CE

CF

D0

OTP LDO1

VOLT

OTP_LDO1UV_TH[1:0]

OTP_LDO1OV_TH[1:0]

OTP_VLDO1[3:0]

OTP LDO1

PWRUP

OTP_LDO1_SEQ[7:0]

—

OTP LDO1

CONFIG

OTP_LDO1_PDGRP[1:0]

—

OTP_LDO1_PG_EN

OTP_LDO1_

WDBYPASS

OTP_LDO1LS

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

99 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

ADDR Register name

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

D1

D2

D3

OTP LDO2

VOLT

OTP_LDO2UV_TH[1:0]

OTP_LDO2OV_TH[1:0]

OTP_VLDO2[3:0]

OTP LDO2

PWRUP

OTP_LDO2_SEQ[7:0]

OTP LDO2

CONFIG

OTP_LDO2_PDGRP[1:0]

OTP_LDO3UV_TH[1:0]

OTP_VSELECT_

EN

OTP_LDO2HW_

EN

—

OTP_LDO2_PG_

EN

OTP_LDO2_

WDBYPASS

OTP_LDO2LS

D4

D5

D6

OTP LDO3

VOLT

OTP_LDO3OV_TH[1:0]

OTP_VLDO3[3:0]

OTP LDO3

PWRUP

OTP_LDO3_SEQ[7:0]

—

OTP LDO3

CONFIG

OTP_LDO3_PDGRP[1:0]

OTP_LDO4UV_TH[1:0]

—

OTP_LDO3_PG_

EN

OTP_LDO3_

WDBYPASS

OTP_LDO3LS

D7

D8

D9

OTP LDO4

VOLT

OTP_LDO4OV_TH[1:0]

OTP_VLDO4[3:0]

OTP LDO4

PWRUP

OTP_LDO4_SEQ[7:0]

—

OTP LDO4

CONFIG

OTP_LDO4_PDGRP[1:0]

—

OTP_LDO4_PG_

EN

OTP_LDO4_

WDBYPASS

OTP_LDO4LS

DA

OTP VSNVS

CONFIG

—

VSNVSVOLT [1:0]

DB

DC

DD

DE

DF

E0

OTP_OV_

BYPASS1

—

OTP_SW7_

OVBYPASS

OTP_SW6_

OVBYPASS

OTP_SW5_

OVBYPASS

OTP_SW4_

OVBYPASS

OTP_SW3_

OVBYPASS

OTP_SW2_

OVBYPASS

OTP_SW1_OVBYPASS

OTP_OV_

BYPASS2

—

OTP_LDO4_

OVBYPASS

OTP_LDO3_

OVBYPASS

OTP_LDO2_

OVBYPASS

OTP_LDO1_

OVBYPASS

OTP_UV_

BYPASS1

OTP_SW7_

UVBYPASS

OTP_SW6_

UVBYPASS

OTP_SW5_

UVBYPASS

OTP_SW4_

UVBYPASS

OTP_SW3_

UVBYPASS

OTP_SW2_

UVBYPASS

OTP_SW1_UVBYPASS

OTP_UV_

BYPASS2

—

OTP_LDO4_

UVBYPASS

OTP_LDO3_

UVBYPASS

OTP_LDO2_

UVBYPASS

OTP_LDO1_

UVBYPASS

OTP_ILIM_

BYPASS1

OTP_SW7_

ILIMBYPASS

OTP_SW6_

ILIMBYPASS

OTP_SW5_

ILIMBYPASS

OTP_SW4_

ILIMBYPASS

OTP_SW3_

ILIMBYPASS

OTP_SW2_

ILIMBYPASS

OTP_SW1_

ILIMBYPASS

OTP_ILIM_

BYPASS2

—

OTP_LDO4_

ILIMBYPASS

OTP_LDO3_

ILIMBYPASS

OTP_LDO2_

ILIMBYPASS

OTP_LDO1_

ILIMBYPASS

E3

OTP DEBUG1

—

BGMON_BYPASS

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

100 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

16.3 PF8100 functional register map

RESET SIGNALS

R/W types

Read only

UVDET

Reset when VIN crosses UVDET threshold

Bits are loaded with OTP values (mirror register)

Reset when device goes to OFF mode

Self-clear after write

R

OFF_OTP

OFF_TOGGLE

SC

R/W

Read and Write

RW1C

R/SW

R/TW

Read, Write a 1 to clear

Read/Secure Write

Read/Write on TBB only

NO_VSNVS

Reset when BOS has no valid input

VIN < UVDET and coin cell < 1.8 V (VSNVS not present)

AD

DR

Register Name

R/W

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

00

01

02

03

04

05

06

07

08

09

0A

0B

DEVICE ID

REV ID

R

DEVICE_FAM[3:0]

FULL_LAYER_REV[3:0]

PROG_ID[11-8]

DEVICE_ID[3:0]

R

METAL_LAYER_REV[3:0]

EMREV

R

—

EMREV[2:0]

PROG ID

R

PROG_ID[7:0]

PWRDN_I

INT STATUS1

INT MASK1

INT SENSE1

THERM INT

THERM MASK

THERM SENSE

SW MODE INT

RW1C

R/W

R

SDWN_I

SDWN_M

—

FREQ_RDY_I

FREQ_RDY_M

—

CRC_I

PWRUP_I

XINTB_I

FSOB_I

VIN_OVLO_I

VIN_OVLO_M

VIN_OVLO_S

THERM_80_I

THERM_80_M

THERM_80_S

SW1_MODE_I

SW1_MODE_M

CRC_M

PWRUP_M

PWRDN_M

—

XINTB_M

FSOB_M

—

XINTB_S

FSOB_S

RW1C

R/W

R

WDI_I

WDI_M

WDI_S

—

FSYNC_FLT_I

FSYNC_FLT_M

FSYNC_FLT_S

SW7_MODE_I

SW7_MODE_M

THERM_155_I

THERM_155_M

THERM_155_S

SW6_MODE_I

SW6_MODE_M

THERM_140_I

THERM_140_M

THERM_140_S

SW5_MODE_I

SW5_MODE_M

THERM_125_I

THERM_125_M

THERM_125_S

SW4_MODE_I

SW4_MODE_M

THERM_110_I

THERM_110_M

THERM_110_S

SW3_MODE_I

SW3_MODE_M

THERM_95_I

THERM_95_M

THERM_95_S

SW2_MODE_I

SW2_MODE_M

RW1C

SW MODE MASK R/W

—

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

SW ILIM INT

RW1C

—

SW7_ILIM_I

SW6_ILIM_I

SW5_ILIM_I

SW4_ILIM_I

SW4_ILIM_M

SW4_ILIM_S

LDO4_ILIM_I

LDO4_ILIM_M

LDO4_ILIM_S

SW4_UV_I

SW4_UV_M

SW4_UV_S

SW4_OV_I

SW4_OV_M

SW4_OV_S

LDO4_UV_I

LDO4_UV_M

LDO4_UV_S

LDO4_OV_I

LDO4_OV_M

LDO4_OV_S

PWRON_2S_I

PWRON_2S_M

—

SW3_ILIM_I

SW3_ILIM_M

SW3_ILIM_S

LDO3_ILIM_I

LDO3_ILIM_M

LDO3_ILIM_S

SW3_UV_I

SW2_ILIM_I

SW2_ILIM_M

SW2_ILIM_S

LDO2_ILIM_I

LDO2_ILIM_M

LDO2_ILIM_S

SW2_UV_I

SW1_ILIM_I

SW1_ILIM_M

SW1_ILIM_S

LDO1_ILIM_I

LDO1_ILIM_M

LDO1_ILIM_S

SW1_UV_I

SW ILIM MASK

SW ILIM SENSE

LDO ILIM INT

LDO ILIM MASK

LDO ILIM SENSE

SW UV INT

R/W

R

—

SW7_ILIM_M

SW6_ILIM_M

SW5_ILIM_M

—

SW7_ILIM_S

SW6_ILIM_S

SW5_ILIM_S

RW1C

R/W

R

—

RW1C

R/W

R

—

SW7_UV_I

SW6_UV_I

SW5_UV_I

SW UV MASK

SW UV SENSE

SW OV INT

—

SW7_UV_M

SW6_UV_M

SW5_UV_M

SW3_UV_M

SW3_UV_S

SW3_OV_I

SW3_OV_M

SW3_OV_S

LDO3_UV_I

LDO3_UV_M

LDO3_UV_S

LDO3_OV_I

LDO3_OV_M

LDO3_OV_S

PWRON_1S_I

PWRON_1S_M

—

SW2_UV_M

SW2_UV_S

SW2_OV_I

SW1_UV_M

SW1_UV_S

—

SW7_UV_S

SW6_UV_S

SW5_UV_S

RW1C

R/W

R

—

SW7_OV_I

SW6_OV_I

SW5_OV_I

SW1_OV_I

SW OV MASK

SW OV SENSE

LDO UV INT

—

SW7_OV_M

SW6_OV_M

SW5_OV_M

SW2_OV_M

SW2_OV_S

LDO2_UV_I

LDO2_UV_M

LDO2_UV_S

LDO2_OV_I

LDO2_OV_M

LDO2_OV_S

PWRON_REL_I

PWRON_REL_M

—

SW1_OV_M

SW1_OV_S

LDO1_UV_I

LDO1_UV_M

LDO1_UV_S

LDO1_OV_I

LDO1_OV_M

LDO1_OV_S

PWRON_PUSH_I

PWRON_PUSH_M

PWRON_S

—

SW7_OV_S

SW6_OV_S

SW5_OV_S

RW1C

R/W

R

—

LDO UV MASK

LDO UV SENSE

LDO OV INT

—

RW1C

R/W

R

—

LDO OV MASK

LDO OV SENSE

PWRON INT

—

RW1C

R/W

R

BGMON_I

BGMON_M

BGMON_S

EWARN_I

PWRON_8S_I

PWRON_8S_M

—

PWRON_4S_I

PWRON_4S_M

—

PRON_3S_I

PRON_3S_M

—

PWRON MASK

PWRON SENSE

SYS INT

R

PWRON_I

OV_I

UV_I

ILIM_I

MODE_I

STATUS2_I

STATUS1_I

29

2A

HARD FAULT

FLAGS

RW1C

R/SW

—

PU_FAIL

WD_FAIL

REG_FAIL

TSD_FAIL

FSOB FLAGS

FSOB_SFAULT_

NOK

FSOB_WDI_

NOK

FSOB_WDC_

NOK

FSOB_HFAULT_

NOK

2B

30

FSOB SELECT

R/W

—

FSOB_SOFTFAULT FSOB_WDI

FSOB_WDC

FSOB_HARDFAULT

TEST FLAGS

R/TW

LDO2EN_S

VSELECT_S

—

TRIM_NOK

OTP_NOK

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

101 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

AD

DR

Register Name

R/W

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

35

36

37

38

39

3A

VMONEN1

VMONEN2

CTRL1

R/SW

R/W

—

SW7VMON_EN

—

SW6VMON_EN

—

SW5VMON_EN

—

SW4VMON_EN

LDO4VMON_EN

WD_EN

SW3VMON_EN

LDO3VMON_EN

WD_STBY_EN

STANDBYINV

—

SW2VMON_EN

LDO2VMON_EN

WDI_STBY_ACTIVE

RUN_PG_GPO

PMIC_OFF

SW1VMON_EN

LDO1VMON_EN

—

VIN_OVLO_EN VIN_OVLO_SDWN

VIN_OVLO_DBNC[1:0]

OV_DB[1:0]

WDI_MODE

—

TMP_MON_EN

TMP_MON_AON

CTRL2

LPM_OFF

—

STBY_PG_GPO

INTB_TEST

CTRL3

R/W

UV_DB[1:0]

PWRUP CTRL

R/W

—

PWRDWN_MODE

PGOOD_PDGRP[1:0]

RESETBMCU_PDGRP[1:0]

SEQ_TBASE[1:0]

3C

RESETBMCU

PWRUP

R/W

RESETBMCU_SEQ[7:0]

3D

3E

3F

40

41

42

43

44

45

46

47

PGOOD PWRUP

PWRDN DLY1

PWRDN DLY2

FREQ CTRL

R/W

PGOOD_SEQ[7:0]

GRP2_DLY[1:0]

—

GRP4_DLY[1:0]

GRP3_DLY[1:0]

GRP1_DLY[1:0]

—

RESETBMCU_DLY[1:0]

SYNCOUT_EN

FSYNC_RANGE

FSS_EN

FSS_RANGE

CLK_FREQ[3:0]

VCOIN[3:0]

PWRON_RST_EN

COINCELL CTRL R/W

—

COINCHG_EN

COINCHG_OFF

PWRON

R/W

—

PWRON_DBNC [1:0]

TRESET[1:0]

WD CONFIG

WD CLEAR

WD EXPIRE

WD COUNTER

R/W

—

WD_DURATION[3:0]

—

R/W1C

R/W

—

WD_CLEAR

WD_MAX_EXPIRE[2:0]

WD_EXPIRE_CNT[2:0]

R/W

WD_MAX_CNT [3:0]

WD_EVENT_CNT [3:0]

FAULT_CNT [3:0]

FAULT

R/W

FAULT_MAX_CNT[3:0]

COUNTER

49

4A

FAULT TIMERS

AMUX

R/W

—

TIMER_FAULT[3:0]

AMUX_EN

AMUX_SEL [4:0]

4D

SW1 CONFIG1

R/W

SW1_UV_

BYPASS

SW1_OV_BYPASS

—

SW1_ILIM_BYPASS SW1_UV_STATE

SW1_OV_STATE

SW1_ILIM_STATE

SW1_WDBYPASS

SW1PHASE[2:0]

SW1_PG_EN

4E

4F

50

51

52

SW1 CONFIG2

SW1 PWRUP

SW1 MODE

R/W

SW1_FLT_REN

SW1DVS_RAMP

SW1_PDGRP[1:0]

SW1ILIM[1:0]

SW1_SEQ[7:0]

—

SW1_STBY_MODE[1:0]

SW1_RUN_MODE[1:0]

SW1 RUN VOLT

VSW1_RUN[7:0]

VSW1_STBY[7:0]

SW1 STBY VOLT R/W

55

SW2 CONFIG1

R/W

SW2_UV_

BYPASS

SW2_OV_BYPASS

—

SW2_ILIM_BYPASS SW2_UV_STATE

SW2_OV_STATE

SW2_ILIM_STATE

SW2_WDBYPASS

SW2_PG_EN

56

57

58

59

5A

SW2 CONFIG2

SW2 PWRUP

SW2 MODE1

R/W

SW2_FLT_REN

SW2DVS_RAMP

SW2ILIM[1:0]

SW2_SEQ[7:0]

SW2PHASE[2:0]

—

SW2_PDGRP[1:0]

SW2_STBY_MODE[1:0]

SW2_RUN_MODE[1:0]

SW2 RUN VOLT

VSW2_RUN[7:0]

VSW2_STBY[7:0]

SW2 STBY VOLT R/W

5D

SW3 CONFIG1

R/W

SW3_UV_

BYPASS

SW3_OV_BYPASS

—

SW3_ILIM_BYPASS SW3_UV_STATE

SW3_OV_STATE

SW3_ILIM_STATE

SW3_WDBYPASS

SW3_PG_EN

5E

5F

60

61

62

SW3 CONFIG2

SW3 PWRUP

SW3 MODE1

R/W

SW3_FLT_REN

SW3DVS_RAMP

SW3ILIM[1:0]

SW3_SEQ[7:0]

SW3PHASE[2:0]

—

SW3_PDGRP[1:0]

SW3_STBY_MODE[1:0]

SW3_RUN_MODE[1:0]

SW3 RUN VOLT

VSW3_RUN[7:0]

VSW3_STBY[7:0]

SW3 STBY VOLT R/W

65

SW4 CONFIG1

R/W

SW4_UV_

BYPASS

SW4_OV_BYPASS

—

SW4_ILIM_BYPASS SW4_UV_STATE

SW4_OV_STATE

SW4_ILIM_STATE

SW4_WDBYPASS

SW4_PG_EN

66

67

68

69

6A

SW4 CONFIG2

SW4 PWRUP

SW4 MODE1

R/W

SW4_FLT_REN

SW4DVS_RAMP

SW4_PDGRP[1:0]

SW4ILIM[1:0]

SW4_SEQ[7:0]

SW4PHASE[2:0]

—

SW4_STBY_MODE[1:0]

SW4_RUN_MODE[1:0]

SW4 RUN VOLT

VSW4_RUN[7:0]

VSW4_STBY[7:0]

SW4 STBY VOLT R/W

6D

SW5 CONFIG1

R/W

SW5_UV_

BYPASS

SW5_OV_BYPASS

—

SW5_ILIM_BYPASS SW5_UV_STATE

SW5_OV_STATE

SW5_ILIM_STATE

SW5_WDBYPASS

SW5_PG_EN

6E

6F

70

SW5 CONFIG2

SW5 PWRUP

SW5 MODE1

R/W

SW5_FLT_REN

SW5DVS_RAMP

SW5_PDGRP[1:0]

SW5ILIM[1:0]

SW5_SEQ[7:0]

SW5PHASE[2:0]

—

SW5_STBY_MODE[1:0]

SW5_RUN_MODE[1:0]

102 / 131

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

AD

DR

Register Name

R/W

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

71

72

SW5 RUN VOLT

R/W

VSW5_RUN[7:0]

VSW5_STBY[7:0]

SW5 STBY VOLT R/W

75

SW6 CONFIG1

R/W

SW6_UV_

BYPASS

SW6_OV_BYPASS

SW6_ILIM_BYPASS SW6_UV_STATE

SW6_OV_STATE

SW6_ILIM_STATE

SW6_WDBYPASS

SW6PHASE[2:0]

SW6_PG_EN

76

77

78

79

7A

SW6 CONFIG2

SW6 PWRUP

SW6 MODE1

R/W

SW6_FLT_REN SW6_VTTEN

SW6DVS_RAMP

SW6_PDGRP[1:0]

SW6ILIM[1:0]

SW6_SEQ[7:0]

—

SW6_STBY_MODE[1:0]

SW6_RUN_MODE[1:0]

SW6 RUN VOLT

VSW6_RUN[7:0]

VSW6_STBY[7:0]

SW6 STBY VOLT R/W

7D

SW7 CONFIG1

R/W

SW7_UV_

BYPASS

SW7_OV_BYPASS

—

SW7_ILIM_BYPASS SW7_UV_STATE

SW7_OV_STATE

SW7_ILIM_STATE

SW7_WDBYPASS

SW7_PG_EN

7E

7F

80

81

SW7 CONFIG2

SW7 PWRUP

SW7 MODE1

R/W

SW7_FLT_REN

—

SW7ILIM[1:0]

SW7_SEQ[7:0]

SW7PHASE[2:0]

—

SW7_PDGRP[1:0]

SW7_STBY_MODE[1:0]

SW7_RUN_MODE[1:0]

SW7 RUN VOLT

—

VSW7[4:0]

85

86

LDO1 CONFIG1

LDO1 CONFIG2

LDO1 PWRUP

R/W

LDO1_UV_

BYPASS

LDO1_OV_BYPASS LDO1_ILIM_

BYPASS

LDO1_UV_STATE

LDO1_OV_STATE

—

LDO1_ILIM_STATE

—

LDO1_WDBYPASS

LDO1_PG_EN

LDO1_FLT_

REN

LDO1_PDGRP[1:0]

—

LDO1_RUN_EN

LDO1_STBY_EN

87

88

89

LDO1_SEQ[7:0]

LDO1 RUN VOLT R/W

—

VLDO1_RUN[3:0]

VLDO1_STBY[3:0]

LDO1 STBY

VOLT

R/W

8B

8C

LDO2 CONFIG1

LDO2 CONFIG2

LDO2 PWRUP

R/W

LDO2_UV_

BYPASS

LDO2_OV_BYPASS LDO2_ILIM_

BYPASS

LDO2_UV_STATE

LDO2HW_EN

LDO2_OV_STATE

VSELECT_EN

LDO2_ILIM_STATE

LDO2_WDBYPASS

LDO2_RUN_EN

LDO2_PG_EN

LDO2_FLT_

REN

LDO2_PDGRP[1:0]

—

LDO2_STBY_EN

8D

8E

8F

LDO2_SEQ[7:0]

LDO2 RUN VOLT R/W

—

VLDO2_RUN[3:0]

VLDO2_STBY[3:0]

LDO2 STBY

VOLT

R/W

91

92

LDO3 CONFIG1

LDO3 CONFIG2

LDO3 PWRUP

R/W

LDO3_UV_

BYPASS

LDO3_OV_BYPASS LDO3_ILIM_

BYPASS

LDO3_UV_STATE

—

LDO3_OV_STATE

—

LDO3_ILIM_STATE

—

LDO3_WDBYPASS

LDO3_RUN_EN

LDO3_PG_EN

LDO3_FLT_

REN

LDO3_PDGRP[1:0]

LDO3_STBY_EN

93

94

95

LDO3_SEQ[7:0]

LDO3 RUN VOLT R/W

—

VLDO3_RUN[3:0]

VLDO3_STBY[3:0]

LDO3 STBY

VOLT

R/W

97

98

LDO4 CONFIG1

LDO4 CONFIG2

LDO4 PWRUP

R/W

LDO4_UV_

BYPASS

LDO4_OV_BYPASS LDO4_ILIM_

BYPASS

LDO4_UV_STATE

—

LDO4_OV_STATE

—

LDO4_ILIM_STATE

LDO4_WDBYPASS

LDO4_RUN_EN

LDO4_PG_EN

LDO4_FLT_

REN

LDO4_PDGRP[1:0]

—

LDO4_STBY_EN

99

9A

9B

LDO4_SEQ[7:0]

LDO4 RUN VOLT R/W

—

VLDO4_RUN[3:0]

VLDO4_STBY[3:0]

LDO4 STBY

VOLT

R/W

9D

9F

VSNVS CONFIG1 R/W

—

VSNVSVOLT [1:0]

PAGE SELECT

R/TW

PAGE[2:0]

PF8100_PF8200

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Product data sheet

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

16.4 PF8100 OTP mirror register map (page 1)

Reset types

OFF_OTP

OTP

Register loads the OTP mirror register values during power up

Register available in OTP bank only, reset from fuses when VIN crosses UVDET threshold

Reset when BOS has no valid input. VIN < UVDET and coin cell < 1.8 V (VSNVS not present)

VSNVS

AD

DR

Register name

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

A0

OTP FSOB

SELECT

—

OTP_FSOB_

SOFTFAULT

OTP_FSOB_WDI

OTP_FSOB_WDC

OTP_FSOB_

HARDFAULT

A1

A2

A3

OTP I2C

—

OTP_I2C_CRC_EN

—

OTP_I2C_ADD[2:0]

OTP_PG_ACTIVE

OTP CTRL1

OTP CTRL2

—

OTP_EWARN_TIME[1:0]

OTP_XFAILB_EN

OTP_STANDBYINV

OTP_VIN_OVLO_EN

OTP_PG_CHECK

OTP_FSS_EN

OTP_FSS_RANGE

—

OTP_VIN_OVLO_

SDWN

OTP_VIN_OVLO_DBNC[1:0]

A4

A5

OTP CTRL3

OTP_VTT_PDOWN

OTP_SW_MODE

OTP_SW6_VTTEN

OTP_SYNCIN_EN

OTP_SW5CONFIG[1:0]

OTP_SW4CONFIG[1:0]

OTP_SW1CONFIG[1:0]

OTP FREQ

CTRL

OTP_SYNCOUT_EN OTP_FSYNC_

RANGE

OTP_CLK_FREQ[3:0]

A6

A7

OTP COINCELL

CTRL

—

OTP_VCOIN[3:0]

OTP PWRON

OTP_PWRON_

MODE

OTP_PWRON_DBNC[1:0]

OTP_PWRON_

RST_EN

OTP_TRESET[1:0]

A8

OTP WD

CONFIG

—

OTP_WDI_MODE

OTP_WDI_INV

—

OTP_WD_EN

—

OTP_WD_STBY_EN

OTP_WDI_STBY_

ACTIVE

OTP_WDWINDOW

A9

AA

AB

AC

OTP WD

EXPIRE

—

OTP_WD_MAX_EXPIRE[2:0]

OTP WD

COUNTER

OTP_WD_DURATION[3:0]

OTP_WD_MAX_CNT [3:0]

OTP FAULT

COUNTERS

—

OTP_FAULT_MAX_CNT[3:0]

OTP_TIMER_FAULT[3:0]

OTP FAULT

TIMERS

AD

AE

AF

OTP PWRDN

DLY1

OTP_GRP4_DLY[1:0]

OTP_GRP3_DLY[1:0]

OTP_GRP2_DLY[1:0]

OTP_GRP1_DLY[1:0]

OTP PWRDN

DLY2

OTP_PD_SEQ_DLY[1:0]

—

OTP_RESETBMCU_DLY[1:0]

OTP_SEQ_TBASE[1:0]

OTP PWRUP

CTRL

—

OTP_PWRDWN_

MODE

OTP_PGOOD_PDGRP[1:0]

OTP_RESETBMCU_PDGRP[1:0]

B0

B1

OTP

RESETBMCU

PWRUP

OTP_RESETBMCU_SEQ[7:0]

OTP_PGOOD_SEQ[7:0]

OTP PGOOD

PWRUP

B2

B3

OTP SW1 VOLT

OTP_VSW1[7:0]

OTP SW1

PWRUP

OTP_SW1_SEQ[7:0]

B4

B5

OTP SW1

CONFIG1

OTP_SW1UV_TH[1:0]

OTP_SW1OV_TH[1:0]

OTP_SW1_PDGRP[1:0]

OTP_SW1ILIM[1:0]

OTP SW1

CONFIG2

OTP_SW1_LSELECT[1:0]

OTP_SW1PHASE[2:0]

OTP_SW1DVS_RAMP OTP_SW1_PG_EN

OTP_SW1_WDBYPASS

B6

B7

OTP SW2 VOLT

OTP_VSW2[7:0]

OTP SW2

PWRUP

OTP_SW2_SEQ[7:0]

B8

B9

OTP SW2

CONFIG1

OTP_SW2UV_TH[1:0]

OTP_SW2OV_TH[1:0]

OTP_SW2_PDGRP[1:0]

OTP_SW2ILIM[1:0]

OTP SW2

CONFIG2

OTP_SW2_LSELECT[1:0]

OTP_SW2PHASE[2:0]

OTP_SW2DVS_RAMP OTP_SW2_PG_EN

OTP_SW2_WDBYPASS

BA

BB

OTP SW3_

VOLT

OTP_VSW3[7:0]

OTP SW3

PWRUP

OTP_SW3_SEQ[7:0]

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

AD

DR

Register name

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

BC

OTP SW3

CONFIG1

OTP_SW3UV_TH[1:0]

OTP_SW3_LSELECT[1:0]

OTP_SW3OV_TH[1:0]

OTP_SW3_PDGRP[1:0]

OTP_SW3ILIM[1:0]

BD

OTP SW3

CONFIG2

OTP_SW3PHASE[2:0]

OTP_SW3DVS_RAMP OTP_SW3_PG_EN

OTP_SW3_WDBYPASS

BE

BF

OTP SW4 VOLT

OTP_VSW4[7:0]

OTP SW4

PWRUP

OTP_SW4_SEQ[7:0]

C0

C1

OTP SW4

CONFIG1

OTP_SW4UV_TH[1:0]

OTP_SW4OV_TH[1:0]

OTP_SW4_PDGRP[1:0]

OTP_SW4ILIM[1:0]

OTP SW4

CONFIG2

OTP_SW4_LSELECT[1:0]

OTP_SW4PHASE[2:0]

OTP_SW4DVS_RAMP OTP_SW4_PG_EN

OTP_SW4_WDBYPASS

C2

C3

OTP SW5 VOLT

OTP_VSW5[7:0]

OTP SW5

PWRUP

OTP_SW5_SEQ[7:0]

C4

C5

OTP SW5

CONFIG1

OTP_SW5UV_TH[1:0]

OTP_SW5OV_TH[1:0]

OTP_SW5_PDGRP[1:0]

OTP_SW5ILIM[1:0]

OTP SW5

CONFIG2

OTP_SW5_LSELECT[1:0]

OTP_SW5PHASE[2:0]

OTP_SW5DVS_RAMP OTP_SW5_PG_EN

OTP_SW5_WDBYPASS

C6

C7

OTP SW6 VOLT

OTP_VSW6[7:0]

OTP SW6

PWRUP

OTP_SW6_SEQ[7:0]

C8

C9

OTP SW6

CONFIG1

OTP_SW6UV_TH[1:0]

OTP_SW6OV_TH[1:0]

OTP_SW6PHASE[2:0]

OTP_SW6_PDGRP[1:0]

OTP_SW6ILIM[1:0]

OTP SW6

CONFIG2

OTP_SW6_LSELECT[1:0]

OTP_SW6DVS_RAMP OTP_SW6_PG_EN

OTP_VSW7[4:0]

OTP_SW6_WDBYPASS

CA

CB

OTP SW7 VOLT

—

OTP SW7

PWRUP

OTP_SW7_SEQ[7:0]

CC

CD

OTP SW7

CONFIG1

OTP_SW7UV_TH[1:0]

OTP_SW7OV_TH[1:0]

OTP_SW7_PDGRP[1:0]

OTP_SW7ILIM[1:0]

OTP SW7

CONFIG2

OTP_SW7_LSELECT[1:0]

OTP_SW7PHASE[2:0]

—

OTP_SW7_PG_EN

OTP_SW7_WDBYPASS

CE

CF

D0

OTP LDO1

VOLT

OTP_LDO1UV_TH[1:0]

OTP_LDO1OV_TH[1:0]

OTP_VLDO1[3:0]

OTP LDO1

PWRUP

OTP_LDO1_SEQ[7:0]

—

OTP LDO1

CONFIG

OTP_LDO1_PDGRP[1:0]

OTP_LDO2UV_TH[1:0]

—

OTP_LDO1_PG_EN

OTP_LDO1_

WDBYPASS

OTP_LDO1LS

D1

D2

D3

OTP LDO2

VOLT

OTP_LDO2OV_TH[1:0]

OTP_VLDO2[3:0]

OTP LDO2

PWRUP

OTP_LDO2_SEQ[7:0]

OTP LDO2

CONFIG

OTP_LDO2_PDGRP[1:0]

OTP_LDO3UV_TH[1:0]

OTP_VSELECT_EN

OTP_LDO2HW_EN

—

OTP_LDO2_PG_EN

OTP_LDO2_

WDBYPASS

OTP_LDO2LS

OTP_LDO3LS

OTP_LDO4LS

D4

D5

D6

OTP LDO3

VOLT

OTP_LDO3OV_TH[1:0]

OTP_VLDO3[3:0]

OTP LDO3

PWRUP

OTP_LDO3_SEQ[7:0]

—

OTP LDO3

CONFIG

OTP_LDO3_PDGRP[1:0]

OTP_LDO4UV_TH[1:0]

—

OTP_LDO3_PG_EN

OTP_LDO3_

WDBYPASS

D7

D8

D9

OTP LDO4

VOLT

OTP_LDO4OV_TH[1:0]

OTP_VLDO4[3:0]

OTP LDO4

PWRUP

OTP_LDO4_SEQ[7:0]

—

OTP LDO4

CONFIG

OTP_LDO4_PDGRP[1:0]

—

OTP_LDO4_PG_EN

OTP_LDO4_

WDBYPASS

DA

OTP VSNVS

CONFIG

—

VSNVSVOLT [1:0]

DB

DC

OTP_OV_

BYPASS1

—

OTP_SW7_

OVBYPASS

OTP_SW6_

OVBYPASS

OTP_SW5_

OVBYPASS

OTP_SW4_

OVBYPASS

OTP_SW3_

OVBYPASS

OTP_SW2_

OVBYPASS

OTP_SW1_OVBYPASS

OTP_OV_

BYPASS2

—

OTP_LDO4_

OVBYPASS

OTP_LDO3_

OVBYPASS

OTP_LDO2_

OVBYPASS

OTP_LDO1_

OVBYPASS

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

AD

DR

Register name

BIT7

—

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

DD

DE

DF

E0

E3

OTP_UV_

BYPASS1

OTP_SW7_

UVBYPASS

OTP_SW6_

UVBYPASS

OTP_SW5_

UVBYPASS

OTP_SW4_

UVBYPASS

OTP_SW3_

UVBYPASS

OTP_SW2_

UVBYPASS

OTP_SW1_UVBYPASS

OTP_UV_

BYPASS2

—

OTP_LDO4_

UVBYPASS

OTP_LDO3_

UVBYPASS

OTP_LDO2_

UVBYPASS

OTP_LDO1_

UVBYPASS

OTP_ILIM_

BYPASS1

—

OTP_SW7_

ILIMBYPASS

OTP_SW6_

ILIMBYPASS

OTP_SW5_

ILIMBYPASS

OTP_SW4_

ILIMBYPASS

OTP_SW3_

ILIMBYPASS

OTP_SW2_

ILIMBYPASS

OTP_SW1_

ILIMBYPASS

OTP_ILIM_

BYPASS2

—

OTP_LDO4_

ILIMBYPASS

OTP_LDO3_

ILIMBYPASS

OTP_LDO2_

ILIMBYPASS

OTP_LDO1_

ILIMBYPASS

OTP DEBUG1

—

BGMOM_BYPASS

17 OTP/TBB and default configurations

The PF8100/PF8200 supports OTP fuse bank configuration and a predefined hardwire

configurations to select the default power up configuration via the VDDOTP pin.

The default power up configuration is loaded into the functional I²C registers based on

the voltage on VDDOTP pin on register loading.

• If VDDOTP = GND, the device loads the configuration from the OTP mirror registers.

• If VDDOTP = V1P5D, the device loads the configuration from the default hardwire

configuration.

When OTP configuration is selected, the register loading occurs in two stages:

• In the first stage, the fuses are loaded in the OTP Mirror registers every time VIN

crosses the UVDET threshold in the rising edge.

• At the second stage, data from the mirror registers are loaded into the functional I²C

registers for device operation.

When VDDOTP = GND, the mirror registers hold the default configuration to be used on

a power-on event. The mirror registers can be modified during the TBB mode in order to

test a custom power up configuration and/or burn the configuration into the OTP fuses to

generate a customized default power up configuration.

When VDDOTP = V1P5D, the I²C functional register will always be loaded from the

hardwire configuration every time a default loading is required. Therefore, no TBB

operation is possible in this configuration.

In the event of a TRIM/OTP loading failure or a self-test failure, the corresponding fault

flag is set and any PWRUP event is ignored until the flags are cleared by writing a 1

during the QPU_OFF state.

The TRIM_NOK, OTP_NOK and STEST_NOK flags can only be written when the

TBBEN is set high (in TBB Mode). In normal operation, the TRIM_NOK, OTP_NOK and

STEST_NOK flags can only be read, but not cleared.

17.1 TBB (Try Before Buy) operation

The PF8100/PF8200 allows temporary configuration (TBB) to debug or test a customized

power up configuration in the system. In order to access the TBB mode, the TBBEN pin

should be set high .

In this mode of operation, the device ignores the default value of the LPM_OFF bit and

moves into the QPU_Off state, regardless of the result of the self-test. However, the

actual result of the self-test is notified by the STEST_NOK flag.

• When the self-test is successful the STEST_NOK flag is set to 0

• When the self-test has failed, the STEST_NOK flag is set to 1

PF8100_PF8200

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Product data sheet

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

In the TBB mode, the following conditions are valid:

• I²C communication uses standard communication with no CRC and secure write

disabled.

• Default I²C address is 0x08 regardless of the address configured by OTP.

• Watchdog monitoring is disabled (including WDI and internal watchdog timer).

• The PF8100/PF8200 can communicate through I²C as long as V_DDIOis provided to the

PMIC externally.

The PAGE[2:0] bits are provided to grant access to the mirror registers and other OTP

dedicated bits. When device is in the TBB mode, it can access the mirror registers in

the extended register Page 1. With the TBBEN pin pulled low, access to the extended

register pages is not allowed.

The mirror registers are preloaded with the values form the OTP configuration. These

may be modified to set the proper power up configuration during TBB operation.

If a power up event is present with the TBBEN pin set high, device will power up with the

proper configuration but limited functionality.

Limited functionality includes:

• Default I²C address = 0x08

• CRC and secure write disabled

• Watchdog operation/monitoring disable

In order to allow TBB operation with full functionality, the TBBEN pin must be low when

the power up event occurs.

The PF8100/PF8200 can operate normally using the TBB configuration, as long as VIN

does not go below the UVDET threshold. If VIN is lost (VIN < UVDET) the mirror register

will be reset and TBB configuration must be performed again.

17.2 OTP fuse programming

A permanent OTP configuration is possible by burning the OTP fuses. OTP fuse

burning is performed in the TBBEN mode during the QPU_Off state. Contact your NXP

representative for detailed information on OTP fuse programming.

17.3 Default hardwire configuration

If VDDOTP = V1P5D, the device loads the configuration from the default hardwire

configuration directly into the corresponding I²C functional registers every time the

registers need to be reloaded.

When using the hardwire configuration, the TRIM values are still loaded from the OTP

fuses. In the event of a TRIM loading failure, the corresponding fault flag is set to 1.

When the hardwire configuration is used, the PF8100/PF8200 does not allow TBB mode

operation. When TBBEN = V1P5D, the device enters a debug mode. In this mode of

operation, the device ignores the default value of the LPM_OFF bit and moves into the

QPU_Off state, regardless of the result of the self-test. However, the actual result of the

self-test is notified by the STEST_NOK flag.

• When the self-test is successful, the STEST_NOK flag is set to 0

• When the self-test has failed, the STEST_NOK flag is set to 1

During hardwire configuration, the OTP_NOK flag is always set to 0.

PF8100_PF8200

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Product data sheet

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

When any of the TRIM_NOK, OTP_NOK or STEST_NOK flags is set, any PWRUP

event is ignored until the flags are cleared by writing a 0. These flags can only be written

when the system is in the debug mode, (TBBEN = V1P5D). In normal operation, the

TRIM_NOK, OTP_NOK and STEST_NOK flags are read only.

Vin > UVDET

FUSE LOAD

Default

Config

OTP

Config

VDDOTP = V1P5D

2

I C Register

Map

Mirror

Registers

TBB Default

Configuration

TBBEN = V1P5D

· WDI disabled

LP_Off

· Watchdog Disabled

2

· l C CRC disabled

PWRON

event

2

· l C Address = 0x08

· Access Miscellaneous

Debug flags

Self-Test

QPU_Off

2

I C Register

Map

Mirror

Registers

POWER OFF

PWRON

event

Hardwire

Power up Configuration

2

I C Register

Map

POWER UP

SYSTEM ON

lf TBBEN = V1P5D

(Limited Functionality)

lf TBBEN = GND

(Full Functionality)

aaa-028077

Figure 39.ꢀHardwire operation diagram

For simplicity, the default hardwire configuration in PF8100/PF8200 is organized based

on the OTP register map as shown in Table 78.

Table 78.ꢀDefault hardwire configuration

ADDR

Register name

OTP FSOB SELECT

OTP I2C

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

Configuration

A0

0

Active Safe State disabled | FSOB pin not used

Secured I2C disabled | I2C CRC disabled | I2C address = 0x08

A1

PF8100_PF8200

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Product data sheet

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

ADDR

Register name

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

Configuration

A2

OTP CTRL1

0

1

0

100 µs EWARN | Fail-safe State enabled | STANDBY active high | PGOOD

indicator | PG not Check on power up

A3

A4

OTP CTRL2

OTP CTRL3

0

1

0

1

FSS disabled | FSS Range = 5 % | XFAILB Disabled | VIN_OVLO shutdown

disabled | VIN_OVLO enabled | VIN_OVLO debounce = 100 µs

VTT Hi-Z off | Single phase: SW6, SW5, SW4, SW3 | Dual phase: SW1/SW2

A5

OTP FREQ CTRL

0

SWx in APS | SYNCIN = Disabled | SYNCOUT disabled | SYNCIN range = 2 MHz

– 3 MHz | CLK Frequency = 2.5 MHz

A6

A7

A8

OTP COINCELL CTRL

OTP PWRON

0

1

0

1

0

1

0

VCOIN = 3.0 V

PWRON = Level sensitive

OTP WD CONFIG

WDI generates soft WD reset | WDI detect on rising edge | WD timer disabled | WD

Timer in standby disabled |WDI detect in standby disabled | WD windows = 100 %

A9

AA

AB

AC

OTP WD EXPIRE

0

1

0

1

0

1

0

1

0

1

Max WD expire count = 8

OTP WD COUNTER

OTP FAULT COUNTERS

OTP FAULT TIMERS

WD duration = 1024 ms | Max WD count = 16

Fail Safe MAX counter = 16 | Regulator fault max counter = 16

Fail safe OK timer = 1 minute | Regulator fault timer = Disabled

AD

OTP PWRDN DLY1

0

GRP4 delay = 125 μs | GRP 3 delay = 125 μs | GRP 2 delay = 125 μs | GRP 1

delay = 125 μs

AE

AF

B0

B1

OTP PWRDN DLY2

0

1

0

1

0

1

0

1

0

No power down delay | RESETBMCU delay = 10 μs

PD mirror sequence | RESETBMCU PD Group2 | TBASE = 250 μs

RESETBMCU SEQ = Slot 6

OTP PWRUP CTRL

OTP RESETBMCU PWRUP

OTP PGOOD PWRUP

PGOOD SEQ = OFF

B2

B3

B4

B5

OTP SW1 VOLT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage = 1.0 V

OTP SW1 PWRUP

OTP SW1 CONFIG1

OTP SW1 CONFIG2

SEQ = Slot 0

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM typ 4.5 A

L = 1 μH | Phase = 0º | DVS Ramp = 12.5 mV/μs | PG = EN | WDBYPASS =

Disable

B6

B7

B8

B9

OTP SW2 VOLT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage = 1.0 V

OTP SW2 PWRUP

OTP SW2 CONFIG1

OTP SW2 CONFIG2

SEQ = Slot 0

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM typ 4.5 A

L = 1 μH | Phase = 180º | DVS Ramp = 12.5 mV/µs | PG = EN | WDBYPASS =

Disable

BA

BB

BC

BD

OTP SW3_VOLT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage = 1.1 V

OTP SW3 PWRUP

OTP SW3 CONFIG1

OTP SW3 CONFIG2

SEQ = Slot 4

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min 4.5 A

L = 1 μH | Phase = 0º | DVS Ramp = 12.5 mV/µs | PG = EN | WDBYPASS =

Disable

BE

BF

C0

C1

OTP SW4 VOLT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage = 1.1 V

OTP SW4 PWRUP

OTP SW4 CONFIG1

OTP SW4 CONFIG2

SEQ = Slot 4

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min 4.5 A

L = 1 μH | Phase = 0º | DVS Ramp = 12.5 mV/μs | PG = EN | WDBYPASS =

Disable

C2

C3

C4

C5

OTP SW5 VOLT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage = 1.1 V

OTP SW5 PWRUP

OTP SW5 CONFIG1

OTP SW5 CONFIG2

SEQ = Slot 2 ( TBASE x 2 = 500 μs)

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min 4.5 A

L = 1 μH | Phase = 0º | DVS Ramp = 12.5 mV/us | PG = EN | WDBYPASS =

Disable

C6

C7

C8

C9

OTP SW6 VOLT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Voltage = 1.8 V

OTP SW6 PWRUP

OTP SW6 CONFIG1

OTP SW6 CONFIG2

SEQ = Slot 2 (TBASE x 2 = 500 μs)

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min 4.5 A

L = 1 μH | Phase = 0º | DVS Ramp = 12.5 mV/μs | PG = EN | WDBYPASS =

Disable

CA

CB

CC

CD

OTP SW7 VOLT

0

1

0

1

0

1

0

1

0

1

0

Voltage = 3.3 V

OTP SW7 PWRUP

OTP SW7 CONFIG1

OTP SW7 CONFIG2

SEQ = Slot 2 (TBASE x 2 = 500 μs)

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min 4.5 A

L = 1 μH | Phase = 0º | PG = EN | WDBYPASS = Disable

PF8100_PF8200

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ADDR

CE

Register name

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

Configuration

OTP LDO1 VOLT

OTP LDO1 PWRUP

OTP LDO1 CONFIG

0

1

0

1

0

1

0

1

0

Voltage = 1.8 V

CF

SEQ = Slot 0

D0

LDO PD Group 4 | PG = EN | WDBYPASS = Disable | LDO Mode

D1

D2

D3

OTP LDO2 VOLT

0

1

0

1

0

1

0

1

0

1

0

Voltage = 3.3 V

OTP LDO2 PWRUP

OTP LDO2 CONFIG

SEQ = Slot 2 (TBASE x 2 = 500 μs)

LDO PD Group 4 | VSELECT = EN | LDO2HW = EN | PG = EN | WDBYPASS =

Disable | LDO Mode

D4

D5

D6

OTP LDO3 VOLT

0

1

0

1

0

1

0

1

0

1

0

Voltage = 3.3 V

OTP LDO3 PWRUP

OTP LDO3 CONFIG

SEQ = OFF

LDO PD Group 4 | PG = EN | WDBYPASS = Disable | LDO Mode

D7

D8

D9

OTP LDO4 VOLT

0

1

0

1

0

1

0

1

0

1

0

Voltage = 3.3 V

OTP LDO4 PWRUP

OTP LDO4 CONFIG

SEQ = OFF

LDO PD Group 4 | PG = EN | WDBYPASS = Disable | LDO Mode

DA

OTP VSNVS CONFIG

0

1

0

Voltage = 3.0 V

DB

DC

DD

DE

DF

E0

E1

E2

OTP OV BYPASS1

OTP OV BYPASS2

OTP UV BYPASS1

OTP UV BYPASS2

OTP ILIM BYPASS1

OTP ILIM BYPASS2

OTP PROG IDH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OV bypass disabled on all SW regulators

OV bypass disabled on all LDO regulators

UV bypass disabled on all SW regulators

UV bypass disabled on all LDO regulators

ILIM bypass disabled on all SW regulators

ILIM bypass disabled on all LDO regulators

Prog ID = 0xFFF

OTP PROG IDL

Prog ID = 0xFFF

18 Functional safety

18.1 System safety strategy

The PF8200 is defined in a context of safety and shall provide a set of features to

achieve the safety goals on such context. It provides a flexible yet complete safety

architecture to comply with ASILB systems providing full programmability to enable

or disable features to address the safety goal. This architecture includes protective

mechanisms to avoid unwanted modification on the respective safety features, as

required by the system.

The following are features considered to be critical for the functional safety strategy:

• Internal watchdog timer

• External watchdog monitoring input (WDI)

• Fail -safe output (FSOB)

• Output voltage monitoring with dedicated bandgap reference

• Protected I²C protocol with CRC verification

• Input overvoltage protection

• Analog built-in self-test (ABIST)

18.2 Output voltage monitoring with dedicated bandgap reference

For the type 2 buck regulator and LDOs, the OV/UV monitors operate from a dedicated

bandgap reference for voltage monitoring.

For the type 1 buck regulators, the OV/UV monitor operate from the same reference

as the regulator. To ensure the integrity of the type 1 buck regulators, a comparison

PF8100_PF8200

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NXP Semiconductors

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between the regulator bandgap and the monitoring bandgap is performed. A 4 % to

12 % difference between the two bandgaps is an indicator of a potential regulation or

monitoring fault and is considered as a critical issue. Therefore, the device prevents the

switching regulators from powering up.

In PF8200, if a bandgap error is detected during a power up event, the self-test

will fail and prevent the device from powering up regardless of the value of the

OTP_BGMON_BYPASS bit.

During system-on states a drift between the two bandgaps is detected:

• when OTP_BGMON_BYPASS = 0, the power stage of the voltage regulators will be

shutdown

• when OTP_BGMON_BYPASS = 1, the bandgap monitor only sends an interrupt to the

system to announce the bandgap failure

The BGMON_I is asserted when a bandgap failure occurs, provided it is not masked.

The BGMON_S bit is set to 0 when the bandgaps are within range, and set to 1 when the

bandgaps are out of range.

18.3 ABIST verification

The PF8200 implements an ABIST verification of all output voltage monitors. The ABIST

verification on the output voltage monitoring behaves as follows:

• Device test the OV comparators for each individual SWx and LDOx supply during the

self-test routine

• Device test the UV comparators for each individual SWx and LDOx supply during the

self-test routine

• During the ABIST verification, it is required to ensure the corresponding OV/UV

comparators are able to toggle, which in turn is a sign of the integrity of these functions

• If any of the comparators is not able to toggle, a warning bit is set on the I²C register

map:

– The ABIST_OV1 register contain the AB_SWx_OV bits for all external regulators

– The ABIST_OV2 register contain the AB_LDOx_OV bits for all external regulators

– The ABIST_UV1 register contain the AB_SWx_UV bits for all external regulators

– The ABIST_UV2 register contain the AB_LDOx_UV bits for all external regulators

• The ABIST registers are cleared or overwritten every time the ABIST check is

performed

• The ABIST registers are part of the secure registers and will require an I²C secure write

to be cleared if this feature is enabled.

Once ABIST check is performed, the PF8200 can proceed with the power up sequence

and the MCU should be able to request the value of these registers and learn if ABIST

failed for any of the voltage monitors.

The AB_RUN bit is provided to perform an ABIST verification on demand.

When the AB_RUN bit is set to 1, the control logic performs an ABIST verification on all

OV/UV monitoring circuits. When the ABIST verification is finished, the AB_RUN bit self-

clear to 0 and a new ABIST verification can be commanded as needed.

When the secure write feature is enabled, the system must perform a secure write

sequence in order to start an ABIST verification on demand.

PF8100_PF8200

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NXP Semiconductors

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12-channel power management integrated circuit for high performance applications

When the PF8200 performs an ABIST verification on demand, the OV/UV fault

monitoring is blanked for a maximum period of 200 µs. During this time, the system must

ensure it is in a safe state, or it is safe to perform this action without violating the safety

goals of the system.

If a failure on the OV/UV monitor is detected during the ABIST on demand request,

the PMIC will assert the corresponding ABIST flags. It is responsibility of the system to

perform a diagnostic check after each ABIST verification to ensure it places the system in

safe state if an ABIST fault is detected.

19 IC level quiescent current requirements

Table 79.ꢀQuiescent current requirements

All parameters are specified at T_A= −40 to 105 °C, unless otherwise noted. Typical values are characterized at V_IN= 5.0 V

and T_A= 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

1.0

5.0

Max

Unit

I_LICELL

Coin cell mode

µA

VIN < UVDET

—

3.0

VSNVS = 3.0 V or 3.3 V

I_LICELL

Coin cell mode

VIN < UVDET

VSNVS = 1.8 V

—

7.0

µA

I_LPOFF

LP_Off state

LPM_OFF = 0

VIN > UVDET

VSNVS = ON

—

40

150

I_QPUOFF

QPU_Off

µA

LPM_OFF = 1

—

750

1000

System ready to power on

I_SYSON

System on core current

Run or standby and all regulators disabled

Coin cell charger disabled

AMUX disabled

750

40

1000

150

I_FSAFE

Fail-safe mode

VIN > UVDET

VSNVS = ON

µA

—

PF8100_PF8200

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12-channel power management integrated circuit for high performance applications

20 Typical applications

100 kΩ

V1P5A

100 kΩ

SW1FB

SW1LX

SW1IN

VSW1

VIN

XFAILB

to XFAILB

of PMIC2

1 µH

2 x 22 µF

4.7 µF

VSELECT

LDO2EN

VDDOTP

TBBEN

from MCU

SW2FB

SW2LX

SW2IN

VSW2

VIN

2 x 22 µF

4.7 µF

VDDIO

I/O Supply

SW3FB

SW3LX

SW3IN

0.1 µF

VSW3

VIN

2.2 kΩ

2 x 22 µF

4.7 µF

SCL

2

I

C CLK

SDA

2

I

C DATA

SYNCIN

SW4FB

SW4LX

SW4IN

from system CLK

to system CLK

to MCU ADC

V1P5A

VSW4

VIN

SYNCOUT

AMUX

2 x 22 µF

4.7 µF

PF8x00

V1P5A

1.0 µF

AGND

SW5FB

SW5LX

SW5IN

VSW5

VIN

V1P5D

DGND

2 x 22 µF

4.7 µF

V1P5D

VIN

1.0 µF

VIN

SW6FB

SW6LX

SW6IN

1.0 µF

0.22 µF

2.2 µF

VSW6

VIN

3.0 V coin cell

2 x 22 µF

4.7 µF

LICELL

VSNVS

+

-

SW7FB

SW7LX

SW7IN

VSNVS

VSW7

VIN

2 x 22 µF

4.7 µF

1.0 µF

4.7 µF

1.0 µF

4.7 µF

1.0 µF

4.7 µF

aaa-028078

Figure 40.ꢀTypical application diagram

PF8100_PF8200

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12-channel power management integrated circuit for high performance applications

21 Package information

21.1 Package outline for WF-type HVQFN56 (Automotive grade)

Figure 41.ꢀPackage outline for WF-type HVQFN56 (Automotive grade)

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Figure 42.ꢀPackage outline detail for WF-type HVQFN56 (Automotive grade)

Figure 43.ꢀPackage outline notes for WF-type HVQFN56 (Automotive grade)

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

21.2 PCB design guidelines for WF-type HVQFN56

Figure 44.ꢀSolder mask pattern for WF-type HVQFN56

PF8100_PF8200

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NXP Semiconductors

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12-channel power management integrated circuit for high performance applications

Figure 45.ꢀI/O pads and solderable areas for WF-type HVQFN56

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Figure 46.ꢀSolder paste stencil for WF-type HVQFN56

PF8100_PF8200

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NXP Semiconductors

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12-channel power management integrated circuit for high performance applications

21.3 Package outline for E-type HVQFN56 (Industrial grade)

Figure 47.ꢀPackage outline for E-type HVQFN56 (Industrial grade)

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Figure 48.ꢀPackage outline detail for E-type HVQFN56 (Industrial grade)

Figure 49.ꢀPackage outline notes for E-type HVQFN56 (Industrial grade)

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

21.4 PCB design guidelines for E-type HVQFN56

Figure 50.ꢀSolder mask pattern for E-type HVQFN56

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Figure 51.ꢀI/O pads and solderable areas for E-type HVQFN56

PF8100_PF8200

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NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Figure 52.ꢀSolder paste stencil for E-type HVQFN56

PF8100_PF8200

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12-channel power management integrated circuit for high performance applications

22 Revision history

Table 80.ꢀRevision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PF8100_PF8200 v.9.0

Modifications

20191119

Product data sheet

CIN 201909005I

PF8100_PF8200 v.8.0

•

Table 53: added values for I_SW5LIMand added note "Current limit applicable to SW5 to ensure maximum power

requirement for the MEMC rail in i.MX8QM systems"

•

Table 53: added note "Current limit applicable to SW1, SW2, SW3, SW4 and SW6" for I_SWxLIM(SWxILIM[1:0] = 11)

Section 14.9.11.1, Section 14.9.11.2: divided Section 14.9.11 content into two subtopics to clarify FSOB

configuration differences between PF8200 and PF8100 devices

PF8100_PF8200 v.8.0

Modifications

20190920

Product data sheet

CIN 201909005I

PF8100_PF8200 v.7.0

•

Table 2: added MC33PF8100FJES and MC34PF8100FJEP, deleted MC33PF8200DMES and MC33PF8200DNES,

added "not recommended for new designs" note for MC33PF8100CCES and MC34PF8100CCEP parts

Table 53: updated description (replaced "VSWxIN = UVDET to 5.5 V" by "VIN = VSWxIN = UVDET to 5.5 V" and

"VSWxIN = 5.0 V" by "VIN = VSWxIN = 5.0 V"), added note "VSWxIN must be connected to VIN to ensure proper

device operation"

•

Table 60: updated description (replaced "VSW7IN = 5.0 V" by "VIN = VSW7IN = 5.0 V"), added note "VSW7IN must

be connected to VIN to ensure proper operation"

Table 9: Added note "Input supply for switching regulators must be capable to sink current to avoid overvoltage

condition during the power down sequence of the device"

PF8100_PF8200 v.7.0

Modifications

20190429

Global: changed document status from Preliminary to Product

20190419 Preliminary data sheet

Section 4: updated Table 1 and added Table 2

Product data sheet

—

PF8100_PF8200 v.6.0

•

PF8100_PF8200 v.6.0

Modifications

—

PF8100_PF8200 v.5.0

•

Table 3: updated description for V1P5D AND V1P5A (replaced 1.5 by 1.6)

Table 3: updated description for VDDIO (replaced 1.7 V by 1.6 V)

Section 12.1: added "SW1, SW2 and SW3 configurable as a triple phase regulator with up to 7.5 A current

capability" to features list

•

Section 15.4.2: updated description and added Figure 26

Table 53: added values for I_{SWx_TP}and I_{SWxILIM_TP}and conditions for V_SWxLOTRand V_SWxLOTR

Table 37: updated min and typical values for V_1P5Dand V_1P5A(replaced 1.35 by 1.50 and 1.50 by 1.60)

Figure 6 and Figure 7: replaced 1.5 V by 1.6 V)

Table 39: updated the max value for V_COINRLHYS(replaced 150 by 170)

Table 15: updated VIN_OVLO min value (replaced 5.6 by 5.55)

Table 42: updated max value for V_COINHYS(replaced 140 by 200)

Section 21: updated package drawings and added drawings for industrial grade

PF8100_PF8200 v.5.0

Modifications

20181001

Updated max value for VIN_OVLO_HYS in Table 15 (replaced 100 by 200)

20180928 Advance information

Changed document status from technical data to advance information

20180926 Technical data

Objective data sheet

—

PF8100_PF8200 v.4.0

PF8100_PF8200 v.3.0

PF8100_PF8200 v.2.2

•

PF8100_PF8200 v.4.0

Modifications

—

•

PF8100_PF8200 v.3.0

—

PF8100_PF8200

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12-channel power management integrated circuit for high performance applications

Document ID

Release date

Data sheet status

Change notice

Supersedes

Modifications

•

Updated description for RESETBMCU_ V_OL, INTB_ V_OL, PGOOD_ V_OL, XFAILB_V_OLin Table 28 (replaced −2.0 mA

by 10 mA)

•

Updated max value for VSELECT_ V_ILand LDO2EN_ V_ILin Table 28 (replaced 0.4 by 0.3*VDDIO)

Updated min value for VSELECT_ V_IHand LDO2EN_ V_IHin Table 28 (replaced 1.4 by 0.7*VDDIO)

Updated max value for V_{SNVS_ILIM}in Table 42 (replaced 60 by 70)

Updated clock frequency tolerance (replaced ±5 % by ±6 %) in Table 44 description

Updated min value for t_PFMtoPWMin Table 53 (replaced 10 by 30)

Updated min and max values for I_SWxNLIMin Table 53 (replaced 0.7 by 0.6 and 1.3 by 1.4)

Updated max value for t_ONSWxMAXin Table 53 (replaced 279 by 310)

Updated description and min value for t_{ONSWx_MIN}in Table 53 (replaced 36 by 34.2)

Updated typical value for I_SWxQin Table 53 (replaced 12 by 14)

Updated min and max values for V_SWxACCin Table 53

Updated R_SWxDISvalues in Table 53

Added V_SWxACCPFMvalues to Table 53

Updated description for V_SW7INin Table 60 (replaced 4.5 by 4.1)

Updated min and max values for V_SW7ACCin Table 60 (replaced −3.0 by −4.0 and 3.0 by 4.0)

Updated R_dischLDOxvalues in Table 64 (replaced 45 by 50 and 500 by 300)

Updated values for t_SW7RAMP, t_ONSW7, I_SW7Qin Table 60

Updated typical and max values for I_LDOxLIMand I_LSxLIMin Table 64 (replaced 800 by 850 and 1200 to 1400)

Updated typical and max values for I_LDOxQin Table 64 (replaced 9.4 by 7.0 and 12.5 to 10)

Updated max values for t_ONLDOxand t_OFFLDOxin Table 64 (replaced 500 by 300 and 2500 by 3500)

Updated min and max values for V_LDOxLOTRin Table 64 (replaced −3.0 by −6.0 and 3.0 by 6.0)

Updated typical and max values for T_onLDOxLSin Table 64 (replaced 100 by 150 and 500 by 300)

Updated min and max values for R_dischLDOxin Table 64 (replaced 45 by 50 and 500 by 300)

Updated description and values for t_{UV_DB}and t_{OV_DB}in Table 69

Updated min and max values for f_20MzACCin Table 71 (replaced −5.0 by −6.0 and 5.0 by 6.0)

Updated values in Table 75

Updated package outline

PF8100_PF8200 v.2.2

Modifications

20180611

Product preview

—

PF8100_PF8200 v.2.1

PF8100_PF8200 v.2.0

•

Minor typo corrections

PF8100_PF8200 v.2.1

Modifications

20180522

•

Changed document id from PF8x00 to PF8100_PF8200

Updated PF8200 OTP mirror register table (deleted E0, E1 and added E3)

Updated PF8100 OTP mirror register table (deleted E0, E1 and added E3)

PF8100_PF8200 v.2.0

Modifications

20180116

Product preview

—

PF8100_PF8200 v.1.0

—

•

Updates to reflect silicon B0

PF8100_PF8200 v.1.0

20170512

Product preview

—

PF8100_PF8200

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23 Legal information

23.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

23.2 Definitions

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

23.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

126 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

23.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP — is a trademark of NXP B.V.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

127 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Tab. 7.

Device options ...................................................2

Tab. 40. VSNVS operation description ..........................58

Tab. 41. VSNVS output voltage configuration ............... 59

Tab. 42. VSNVS electrical characteristics ..................... 59

Tab. 43. DVS ramp speed configuration ....................... 61

Tab. 44. Ramp rates ......................................................61

Tab. 45. Output voltage configuration ........................... 61

Tab. 46. SW regulator mode configuration ....................62

Tab. 47. SWx current limit selection ..............................62

Tab. 48. SWx phase configuration ................................ 62

Tab. 49. SWx inductor selection bits .............................63

Tab. 50. OTP_SW1CONFIG register description .......... 64

Tab. 51. OTP SW4CONFIG register description ...........64

Tab. 52. OTP_SW5CONFIG register description .......... 65

Ordering information ..........................................2

HVQFN56 pin description ................................. 5

Absolute maximum ratings ................................7

ESD ratings .......................................................7

Thermal characteristics ..................................... 7

QFN56 thermal resistance and package

dissipation ratings ............................................. 8

Operating conditions ......................................... 8

Voltage supply summary .................................10

Tab. 8.

Tab. 9.

Tab. 10. Device differences ...........................................11

Tab. 11. State machine transition definition .................. 12

Tab. 12. Fail-safe OK timer configuration ......................20

Tab. 13. UVDET threshold ............................................ 21

Tab. 14. VIN_OVLO debounce configuration ................ 21

Tab. 15. VIN_OVLO specifications ................................21

Tab. 16. Startup timing requirements (PWRON pulled

up) ................................................................... 22

Tab. 53. Type

1

buck

regulator

electrical

characteristics ..................................................66

Tab. 54. Recommended external components ..............68

Tab. 55. SW7 output voltage configuration ................... 69

Tab. 56. SW7 regulator mode configuration ..................70

Tab. 57. SW7 current limit selection ..............................71

Tab. 58. SW7 phase configuration ................................71

Tab. 59. SW7 inductor selection bits .............................71

Tab. 17. Startup with PWRON driven high externally

and LPM_OFF = 0 ..........................................24

Tab. 18. Power up time base register ........................... 24

Tab. 19. Power up sequence registers ..........................25

Tab. 20. Power down regulator group bits .................... 28

Tab. 21. Power down counter delay ..............................29

Tab. 22. Programmable delay after RESETBMCU is

asserted ...........................................................29

Tab. 23. Power down delay selection ............................30

Tab. 24. Regulator control during fault event bits ..........32

Tab. 25. Fault timer register configuration .....................34

Tab. 26. Fault bypass bits .............................................35

Tab. 27. Interrupt registers ............................................ 39

Tab. 28. I/O electrical specifications ..............................41

Tab. 29. PWRON debounce configuration in edge

detection mode ................................................43

Tab. 30. TRESET configuration .....................................43

Tab. 31. Standby pin polarity control .............................43

Tab. 32. EWARN time configuration ............................. 45

Tab. 33. Early warning threshold ...................................46

Tab. 34. LDO control in run or standby mode ............... 47

Tab. 35. I2C address configuration ............................... 53

Tab. 36. Secure bits ...................................................... 54

Tab. 37. Internal supplies electrical characteristics ....... 56

Tab. 38. Coin cell charger voltage level ........................ 57

Tab. 39. Coin cell electrical characteristics ................... 57

Tab. 60. Type

2

buck

regulator

electrical

characteristics ..................................................71

Tab. 61. Recommended external components ..............73

Tab. 62. LDO operation description .............................. 74

Tab. 63. LDO output voltage configuration ....................74

Tab. 64. LDO regulator electrical characteristics ...........75

Tab. 65. UV threshold configuration register .................76

Tab. 66. OV threshold configuration register .................76

Tab. 67. UV debounce timer configuration ....................76

Tab. 68. OV debounce timer configuration ....................77

Tab. 69. VMON Electrical characteristics ......................79

Tab. 70. Manual frequency tuning configuration ............81

Tab. 71. Clock management specifications ...................83

Tab. 72. Thermal monitor specifications ........................85

Tab. 73. Thermal monitor bit description .......................86

Tab. 74. AMUX channel selection .................................87

Tab. 75. AMUX specifications ....................................... 88

Tab. 76. Watchdog duration register ............................. 89

Tab. 77. Soft WD register reset .....................................91

Tab. 78. Default hardwire configuration .......................108

Tab. 79. Quiescent current requirements .................... 112

Tab. 80. Revision history .............................................124

Figures

Fig. 1.

Fig. 2.

Fig. 3.

Fig. 4.

Fig. 5.

Fig. 6.

Fig. 7.

Simplified application diagram ...........................2

Internal block diagram .......................................4

Pin configuration for HVQFN56 .........................5

Functional block diagram ................................ 10

State diagram ..................................................12

Startup with PWRON pulled up .......................22

Startup with PWRON driven high externally

Fig. 8.

Fig. 9.

Power up/down sequence between off and

system-on states ............................................. 26

Power up/down sequence between run and

standby ............................................................26

Fig. 10. Group power down sequence example ...........30

Fig. 11. Power down delay ...........................................31

Fig. 12. Regulator turned off with RegX_STATE = 0

and FLT_REN = 0 ...........................................32

and bit LPM_OFF = 0 ..................................... 23

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

128 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Fig. 13. Regulator turned off with RegX_STATE = 0

Fig. 35. Watchdog timer operation ...............................90

Fig. 36. Soft WD reset behavior ...................................93

Fig. 37. Hard WD reset behavior ................................. 93

Fig. 38. Watchdog event counter ................................. 94

Fig. 39. Hardwire operation diagram ..........................108

Fig. 40. Typical application diagram ...........................113

Fig. 41. Package outline for WF-type HVQFN56

(Automotive grade) ........................................114

and FLT_REN = 1 ...........................................33

Fig. 14. Correct power up (no fault during power up) ....36

Fig. 15. Power up sequencer with a temporary failure .. 37

Fig. 16. Power up sequencer aborted as fault

persists for longer than 2.0 ms ........................38

Fig. 17. I/O interface diagram .......................................41

Fig. 18. XFAILB behavior during

a power up

sequence .........................................................51

Fig. 19. XFAILB behavior during a power down

sequence .........................................................51

Fig. 20. Behavior during an external XFAILB event ......52

Fig. 21. External XFAILB event during a power up

sequence .........................................................52

Fig. 22. 8 bit SAE J1850 CRC polynomial ................... 53

Fig. 23. VSNVS block diagram .....................................59

Fig. 24. Buck regulator block diagram ..........................60

Fig. 25. Dual phase configuration ................................ 65

Fig. 26. Triple phase configuration ...............................65

Fig. 27. Quad phase configuration ...............................66

Fig. 28. Type 2 buck regulator block diagram .............. 69

Fig. 29. LDOx regulator block diagram ........................ 73

Fig. 30. Voltage monitoring architecture .......................78

Fig. 31. Clock management architecture ......................80

Fig. 32. Spread-spectrum waveforms ...........................82

Fig. 33. Thermal monitoring architecture ......................85

Fig. 34. Thermal sensor voltage characteristics ...........86

Fig. 42. Package outline detail for WF-type

HVQFN56 (Automotive grade) ...................... 115

Fig. 43. Package outline notes for WF-type

HVQFN56 (Automotive grade) ...................... 115

Fig. 44. Solder mask pattern for WF-type HVQFN56 .. 116

Fig. 45. I/O pads and solderable areas for WF-type

HVQFN56 ......................................................117

Fig. 46. Solder paste stencil for WF-type HVQFN56 ...118

Fig. 47. Package outline for E-type HVQFN56

(Industrial grade) ........................................... 119

Fig. 48. Package outline detail for E-type HVQFN56

(Industrial grade) ........................................... 120

Fig. 49. Package outline notes for E-type HVQFN56

(Industrial grade) ........................................... 120

Fig. 50. Solder mask pattern for E-type HVQFN56 .... 121

Fig. 51. I/O pads and solderable areas for E-type

HVQFN56 ......................................................122

Fig. 52. Solder paste stencil for E-type HVQFN56 ..... 123

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

129 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Contents

1

2

3

4

5

6

7

7.1

7.2

8

9

10

Overview .............................................................. 1

14.9.5

14.9.6

14.9.7

14.9.8

14.9.9

XINTB .............................................................. 44

WDI ..................................................................44

EWARN ............................................................45

PGOOD ............................................................46

VSELECT .........................................................47

Features ............................................................... 1

Simplified application diagram ..........................2

Ordering information .......................................... 2

Applications .........................................................3

Internal block diagram ........................................4

Pinning information ............................................ 5

Pinning ...............................................................5

Pin description ...................................................5

Absolute maximum ratings ................................7

ESD ratings ..........................................................7

Thermal characteristics ......................................7

Operating conditions ..........................................8

General description ............................................ 8

Features .............................................................8

Functional block diagram .................................10

Power tree summary ....................................... 10

Device differences ........................................... 11

State machine ....................................................11

States description ............................................ 15

OTP/TRIM load ................................................15

LP_Off state .....................................................15

Self-test routine (PF8200 only) ........................15

QPU_Off state ................................................. 16

Power up sequence .........................................16

System-on states .............................................17

14.9.10 LDO2EN ...........................................................47

14.9.11 FSOB (safety output) .......................................47

14.9.11.1 FSOB fault safe state ...................................... 48

14.9.11.2 FSOB active safe state (PF8200 only) ............ 49

14.9.12 TBBEN .............................................................49

14.9.13 XFAILB .............................................................50

14.9.14 SDA and SCL (I2C bus) ..................................52

14.9.14.1 I2C CRC verification ........................................53

14.9.14.2 I2C secure write .............................................. 54

15

15.1

15.2

15.3

11

12

12.1

12.2

12.3

12.4

13

13.1

13.1.1

13.1.2

13.1.3

13.1.4

13.1.5

13.1.6

Functional blocks ..............................................56

Analog core and internal voltage references ....56

Coin cell charger ............................................. 56

VSNVS LDO/switch ......................................... 58

Type 1 buck regulators (SW1 to SW6) ............ 60

SW6 VTT operation .........................................63

Multiphase operation ....................................... 63

Electrical characteristics .................................. 66

Type 2 buck regulator (SW7) .......................... 68

Electrical characteristics .................................. 71

Linear regulators ..............................................73

LDO load switch operation .............................. 74

LDO regulator electrical characteristics ........... 75

Voltage monitoring ...........................................76

Electrical characteristics .................................. 79

Clock management ..........................................79

Low frequency clock ........................................80

High frequency clock ....................................... 80

Manual frequency tuning ................................. 80

Spread-spectrum ............................................. 81

Clock Synchronization ..................................... 82

Thermal monitors .............................................84

Analog multiplexer ........................................... 87

Watchdog event management .........................88

15.4

15.4.1

15.4.2

15.4.3

15.5

15.5.1

15.6

15.6.1

15.6.2

15.7

15.7.1

15.8

15.8.1

15.8.2

15.8.3

15.8.4

15.8.5

15.9

13.1.6.1 Run state ......................................................... 17

13.1.6.2 Standby state ...................................................18

13.1.7

13.1.8

13.1.9

13.1.10 Fail-safe state (PF8200 only) .......................... 19

13.1.11 Coin cell state ..................................................20

14

14.1

14.2

14.3

14.4

WD_Reset ........................................................18

Power down state ............................................19

Fail-safe transition ........................................... 19

General device operation ................................. 20

UVDET .............................................................20

VIN OVLO condition ........................................ 21

IC startup timing with PWRON pulled up .........22

IC startup timing with PWRON pulled low

15.10

15.11

during VIN application ..................................... 23

Power up ......................................................... 24

Power up events ..............................................24

Power up sequencing ......................................24

Power down .....................................................27

Turn off events ................................................ 27

Power down sequencing ................................. 27

15.11.1 Internal watchdog timer ................................... 89

15.11.2 Watchdog reset behaviors ...............................91

14.5

14.5.1

14.5.2

14.6

14.6.1

14.6.2

16

I2C register map ................................................94

PF8200 functional register map .......................95

PF8200 OTP mirror register map (page 1) ...... 98

PF8100 functional register map .....................101

PF8100 OTP mirror register map (page 1) .... 104

OTP/TBB and default configurations ............ 106

TBB (Try Before Buy) operation .................... 106

OTP fuse programming ................................. 107

Default hardwire configuration .......................107

Functional safety .............................................110

System safety strategy .................................. 110

Output voltage monitoring with dedicated

16.1

16.2

16.3

16.4

17

17.1

17.2

17.3

18

14.6.2.1 Sequential power down ................................... 28

14.6.2.2 Group power down ..........................................28

14.6.2.3 Power down delay ...........................................30

14.7

14.7.1

14.8

Fault detection .................................................31

Fault monitoring during power up state ............35

Interrupt management ..................................... 38

I/O interface pins ............................................. 40

PWRON ........................................................... 42

STANDBY ........................................................43

RESETBMCU .................................................. 44

INTB .................................................................44

18.1

18.2

14.9

14.9.1

14.9.2

14.9.3

14.9.4

bandgap reference .........................................110

ABIST verification .......................................... 111

IC level quiescent current requirements .......112

Typical applications ........................................113

18.3

19

20

PF8100_PF8200

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.0 — 19 November 2019

130 / 131

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

21

Package information .......................................114

21.1

Package outline for WF-type HVQFN56

(Automotive grade) ........................................ 114

PCB design guidelines for WF-type

HVQFN56 ...................................................... 116

Package outline for E-type HVQFN56

21.2

21.3

(Industrial grade) ............................................119

PCB design guidelines for E-type HVQFN56 ..121

Revision history .............................................. 124

Legal information ............................................126

21.4

22

23

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 November 2019

Document identifier: PF8100_PF8200


型号：	MC33PF8100ERES
厂家：	NXP
描述：	12-channel power management integrated circuit for high performance applications
文件：	总131页 (文件大小：1164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33PF8100ERES [NXP]

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