MC33PT2000AF_技术文档

Document Number: MC33PT2000

Rev. 10.0, 9/2017

NXP Semiconductors

Data sheet: Advance Information

Programmable solenoid controller

PT2000

The PT2000 is a SMARTMOS programmable gate driver IC for precision

solenoid control applications, which makes the component very flexible and

relieves the main microcontroller from the heavy task of the actuator control.

The chip integrates six microcores used to control, seven external MOSFET

high-side pre-drivers, eight external MOSFET low-side pre-drivers (two of them

with higher switching frequency can be used for DC/DC converters), an

integrated end of injection detection, six current measurements, and

diagnostics for both the high-side and low-side.

PROGRAMMABLE SOLENOID

CONTROLLER

PT2000 includes two internal regulators with overvoltage and undervoltage

monitoring and protection, V_CCPfed from the battery line supplying the pre-

driver section and V_CC2P5fed from an external 5.0 V generating supply for the

digital block.

Interface with the MCU is achieved via serial peripheral interface (SPI) and 16

configurable I/O signals. I/O are supplied by an external 3.3 V or 5.0 V regulator

connected to V_CCIO

.

AF SUFFIX

98ASA00505D

80 LQFP

These features along with cost effective packaging, make the PT2000 ideal for

power train engine control applications.

Features

Applications

• Battery voltage range, 5.0 V < V_BATT< 72 V

• Battery and boost voltage monitoring

• Automotive (12 V), truck and industrial (24 V) power

train

• Diesel and gasoline direct injection (three banks)

• Transmission

• Valve control

• Pre-drive operating voltage up to 72 V

• Seven high-side/ eight low-side pre-drive PWM capability up to 100 kHz-

30 nC

• All pre-drivers have four selectable slew rates

• Eight selectable, pre-defined V_DSmonitoring thresholds

• Measurement function for end of injection detection

• Encryption for microcode protection

• Integrated 1.0 MHz back-up clock

V

BAT

V

/V

BAT BOOST

5.0 V

V

BOOST

VSENSEPx

VSENSENx

x3 Bank

V

BOOST

V

BAT

VSENSEPx

VSENSENx

Figure 1. PT2000 simplified application diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Table of Contents

1

Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Cipher key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Power supply electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 High-side pre-driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 Low-side (LS1-LS6) pre-driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5 Low-side high-speed (LS7-LS8) pre-driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.6 High-side VDS VSRC monitoring electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7 Low-side VDS VSRC monitoring electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.8 Load bias electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.9 Current measurement electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.9.1 Current measurement for positive current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.9.2 Current measurement for negative currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.10 Analog output (OAx) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.11 Clock / PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.12 Digital input/output electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.13 Serial peripheral interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.1 VCC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.2 VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.3 VCC2P5 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.4 VCCP regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1.5 Battery voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1.6 Boost voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2 Clock subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3 High-side pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.3.1 High-side pre-driver slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.2 Safe state of high-side pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.4 High-side VDS and VSRC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.4.1 HS1, 3, 5, 7 VDS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.4.2 HS2, 4, 6 VDS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.5 Low-side pre-driver (LS1-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5.1 Low-side pre-driver slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.5.2 LS1 - LS6 VDS monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.6 Low-side pre-driver for DC/DC converter (LS7 and LS8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.6.1 Low-side pre-driver slew rate control (LS7 and LS8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.6.2 Low-side VDS monitor D_ls7/D_ls8 for DC/DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2

3

4

5

6

PT2000

NXP Semiconductors

2

6.7 Current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.7.1 General purpose current measurement block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.7.2 Current measurement for DC/DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.8 OA_x output pins, multiplexer and T & H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.8.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.8.2 OA_2 Pin digital I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.8.3 OAx output offset and offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Functional device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1.1 Power-up sequence of VCC5, VCC2P5, and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1.2 Power-up sequence VCCP and bootstrap capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2 DC/DC converter control (LS7/8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.3 Device clock manager and PLL init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.4 SW initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.4.1 Power supply, reset, and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.4.2 SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.4.3 Clock monitor, flash enable, and DrvEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.5 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.5.1 MBIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.5.2 LBIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.6 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.7 Cipher unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.8 Ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.9 Shutoff path via the DrvEn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Digital core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.1 Logic channels description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.1.1 Microcores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.1.2 Dual microcore arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.1.3 Signature unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.1.4 SPI backdoor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.1.5 CRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.1.6 DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.2 Serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.2.1 SPI read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.2 SPI write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.2.3 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3 SPI address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.3.1 Selection register (3FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.3.2 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.3.3 IO configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

8.3.4 Main configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

8.3.5 Diagnostics configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

9.1 Application diagram: 3 bank, 6 cylinder with DC/DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

9.2 Application diagram: 3 bank, 3 cylinder (full overlap) with DC/DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

7

8

9

10 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

11 Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

PT2000

3

NXP Semiconductors

1

Orderable parts

Table 1. Orderable part variations

Part number

MC33PT2000AF ⁽¹⁾

Notes

Temperature (T )

Package

A

-40 °C to 125 °C

80-pin LQFP with exposed pad

1. To order parts in tape and reel, add the R2 suffix to the part number.

1.1

Cipher key

Contact a NXP sales representative to obtain devices with a specific encryption key and the associated code encryptor.

PT2000

NXP Semiconductors

4

2

Internal block diagram

B_HS1

G_HS1

S_HS1

B_HS2

G_HS2

S_HS2

B_HS3

G_HS3

S_HS3

B_HS4

G_HS4

S_HS4

B_HS5

G_HS5

S_HS5

B_HS6

G_HS6

S_HS6

B_HS7

G_HS7

S_HS7

HS Pre-driver 1

VDS Monitor 1

Logic

Control

Logic

Channel 1

CLK

HS Pre-driver 2

VDS Monitor 2

RESETB

IRQB

Controls

Digital

Microcore

(Uc0Ch1)

HS Pre-driver 3

VDS Monitor 3

MISO

MOSI

SCLK

CSB

Digital

Microcore

(Uc1Ch1)

HS Pre-driver 4

VDS Monitor 4

SPI

Interface

HS Pre-driver 5

VDS Monitor 5

Code RAM

Data RAM

HS Pre-driver 6

VDS Monitor 6

DBG

FLAG0

FLAG1

FLAG2

FLAG3

Debug

Interface

HS Pre-driver 7

VDS Monitor 7

Logic

Channel 2

LS Pre-driver 1

VDS Monitor 1

D_LS1

G_LS1

LS Pre-driver 2

VDS Monitor 2

D_LS2

G_LS2

Digital

Microcore

(Uc0Ch2)

START1

START2

START3

START4

START5

START6

START7

START8

LS Pre-driver 3

VDS Monitor 3

D_LS3

G_LS3

Digital

Microcore

(Uc1Ch2)

LS Pre-driver 4

VDS Monitor 4

D_LS4

G_LS4

LS Pre-driver 5

VDS Monitor 5

D_LS5

G_LS5

Code RAM

Data RAM

LS Pre-driver 6

VDS Monitor 6

D_LS6

G_LS6

LS Pre-driver 7

VDS Monitor 7

D_LS7 (DC/DC)

G_LS7 (DC/DC)

Supplies

LS Pre-driver 8

VDS Monitor 8

D_LS8 (DC/DC)

G_LS8 (DC/DC)

VBOOST

VBATT

BOOST

Monitor

VSENSEP1

VSENSEN1

OA_1

Current

Measure 1

Charge

Pump

OA Mux Out 1

Logic

Channel 3

BAT

Monitor

VSENSEP3

Current

Measure 3

VSENSEN3

VSENSEP2

Digital

Microcore

(Uc0Ch3)

VCCP

LDO

UV Monitor

Current

Measure 2

VSENSEN2

OA_2

VCCP

VCC5

OA Mux Out 2

Digital

Microcore

(Uc1Ch3)

VCC5

Monitor

VSENSEP4

VSENSEN4

OA_3

Current

Measure 4

OA Mux Out 3

VCC2P5

Regulator

Code RAM

Data RAM

VCC2P5

VSENSEP5 (DC/DC)

Current

Measure 5

VSENSEN5 (DC/DC)

VSENSEP6 (DC/DC)

IO Buffers

Supply

VCCIO

DRVEN

Current

Measure 6

VSENSEN6 (DC/DC)

DGND

AGND

PGND (Exposed Pad)

Figure 2. PT2000 simplified internal block diagram

PT2000

5

NXP Semiconductors

3

Pin connections

Transparent

top view

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

DRVEN

RESETB

START1

START2

START3

START4

START5

START6

START7

FLAG0

FLAG1

FLAG2

FLAG3

CSB

S_HS7

G_HS7

B_HS7

VBOOST

G_LS1

G_LS2

G_LS3

G_LS4

G_LS5

G_LS6

G_LS7

G_LS8

VCCP

VBATT

D_LS1

D_LS2

D_LS3

D_LS4

D_LS5

D_LS6

1

2

3

4

5

6

7

8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

9

10

11

12

13

14

15

16

17

18

19

20

MOSI

MISO

SCLK

VCCIO

DBG

DGND

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Figure 3. PT2000 pin connections

Functional descriptions of many of these pins can be found in the Functional block description section beginning on page 34.

Table 2. PT2000 pin definitions ^{(2), (3), (4)}

Pull

Pin name

Pin function

Definition

configuration

1

2

DRVEN

Input

Weak PD

Driver enable input

Reset pin

RESETB

Weak PU

PU/PD

Configurable

3

4

5

6

7

START1

START2

START3

START4

START5

Input/output

Trigger pin actuator 1 / Flag_bus(5)

Trigger pin actuator 2 / Flag_bus(6)

Trigger pin actuator 3 / Flag_bus(7)

Trigger pin actuator 4 / Flag_bus(8)

Trigger pin actuator 5 / Flag_bus(9)

PU/PD

Configurable

PU/PD

Configurable

PU/PD

Configurable

PU/PD

Configurable

PT2000

NXP Semiconductors

6

Table 2. PT2000 pin definitions ^{(2), (3), (4)}(continued)

Pull

Pin name

Pin function

Definition

configuration

PU/PD

Configurable

8

START6

START7

FLAG 0

FLAG 1

FLAG 2

FLAG 3

Input/output

Trigger pin actuator 6 / Flag_bus(10)

Trigger pin actuator 7 / Flag_bus(11)

PU/PD

Configurable

9

Flag_bus(0) (general purpose I/O)/command for external free-wheeling MOSFTET

pre-driver 1

10

11

12

13

Weak PD

Flag_bus(1) (general purpose I/O)/command for external free-wheeling MOSFTET

pre-driver 2

Flag_bus(2) (general purpose I/O)/command for external free-wheeling MOSFTET

pre-driver 3

Flag_bus(3) (general purpose I/O)/command for external free-wheeling MOSFTET

pre-driver 4

14

15

16

17

18

19

20

21

22

23

CSB

MOSI

Input

PU

SPI chip select

Weak PU

SPI slave input

MISO

Output

Input

—

SPI slave output

SCLK

VCCIO

DBG

Weak PU

SPI clock

Input

—

Digital I/O voltage supply 3.3 V or 5.0 V (supplied externally)

Debug port / Flag_bus (15)

Digital ground

Input/output

Ground

Output

Input

Weak PU

DGND

VCC2P5

VCC5

AGND

—

Internal 2.5 V voltage regulator decoupling

Power supply 5.0 V (supplied externally)

Analog ground

Ground

PU/PD

Configurable

24

VSENSEN4

Input/output

Current sense input comparator - / Start8 / Flag(12)

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

VSENSEP4

VSENSEN1

VSENSEP1

VSENSEN2

VSENSEP2

VSENSEN3

VSENSEP3

VSENSEN5

VSENSEP5

VSENSEN6

VSENSEP6

OA_1

Input/output

Input

Weak PD

Current sense input comparator + /Flag(4) (general purpose I/O)

Current sense input comparator 1 -

Current sense input comparator 1 +

Current sense input comparator 2 -

Current sense input comparator 2 +

Current sense input comparator 3 -

Current sense input comparator 3 +

DC-DC current sense input comparator -

DC-DC current sense input comparator +

DC-DC current sense input comparator -

DC-DC current sense input comparator +

Analog output 1

—

Input

—

Input

—

Input

—

Input

—

Input

—

Input

—

Input

—

Input

—

Output

Input/output

Output

Input

—

OA_2

Weak PD

—

Analog output 2/Flag_bus (14)

OA_3

Analog output 3

D_LS8

—

Drain pin low-side MOSFET for DC/DC converter

Drain pin low-side MOSFET actuator 6

Drain pin low-side MOSFET actuator 5

D_LS7

Input

—

D_LS6

Input

—

D_LS5

Input

—

PT2000

7

NXP Semiconductors

Table 2. PT2000 pin definitions ^{(2), (3), (4)}(continued)

Pull

Pin name

Pin function

Definition

Drain pin low-side MOSFET actuator 4

configuration

43

44

45

46

47

D_LS4

D_LS3

D_LS2

D_LS1

VBATT

Input

—

Drain pin low-side MOSFET actuator 3

Drain pin low-side MOSFET actuator 2

Drain pin low-side MOSFET actuator 1

Battery voltage input

Output: Internal 7.0 V voltage regulator

Input: External 7.0 V voltage regulator (supplied externally)

48

VCCP

Input/output

—

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

G_LS8

G_LS7

G_LS6

G_LS5

G_LS4

G_LS3

G_LS2

G_LS1

VBOOST

B_HS7

G_HS7

S_HS7

B_HS6

G_HS6

S_HS6

B_HS5

G_HS5

S_HS5

B_HS4

G_HS4

S_HS4

B_HS3

G_HS3

S_HS3

B_HS2

G_HS2

S_HS2

B_HS1

G_HS1

S_HS1

IRQB

Output

Input

-

—

Gate pin low-side high speed MOSFET can be used for DC/DC converter

Gate pin low-side MOSFET actuator 6

Gate pin low-side MOSFET actuator 5

Gate pin low-side MOSFET actuator 4

Gate pin low-side MOSFET actuator 3

Gate pin low-side MOSFET actuator 2

Gate pin low-side MOSFET actuator 1

Boost voltage and drain pin for boost pre-drivers

Bootstrap pin high-side MOSFET 7

Gate pin high-side MOSFET 7

—

Output

Input

-

—

Source pin high side MOSFET 7

—

Bootstrap pin Boost MOSFET 6

Output

Input

-

—

Gate pin Boost MOSFET 6

—

Source pin Boost MOSFET 6

—

Bootstrap pin high-side MOSFET 5

Gate pin high-side MOSFET 5

Output

Input

-

—

Source pin high side MOSFET 5

—

Bootstrap pin boost MOSFET 4

Output

Input

-

—

Gate pin boost MOSFET 4

—

Source pin boost MOSFET 4

—

Bootstrap pin high-side MOSFET 3

Gate pin high-side MOSFET 3

Output

Input

-

—

Source pin high-side MOSFET 3

—

Bootstrap pin boost MOSFET 2

Output

Input

-

—

Gate pin boost MOSFET 2

—

Source pin boost MOSFET 2

Bootstrap pin high-side MOSFET 1

Gate pin high-side MOSFET 1

Output

Input

Input/output

Input

—

Source pin high-side MOSFET 1

Weak PD

Weak PU

Interrupt output/Flag_bus (13)

CLK

Clock pin (low-frequency reference for internal PLL)

PT2000

NXP Semiconductors

8

Table 2. PT2000 pin definitions ^{(2), (3), (4)}(continued)

Pull

Pin name

Pin function

Definition

configuration

ePAD

PGND

Ground

—

Power ground (to be soldered on GND PCB)

Notes

2. External 7.0 V is required in case the typical battery voltage is 24 V (See External VCCP (vccp_ext_en='1') on page 35).

3. Except for supply and ground, it is guaranteed by design unused pins can be kept open without any impact on the device.

4. Unused VSENSEPx and VSENSENx pins can both be connected to GND.

Table 3. Resistor types

Pin type

Description

PU

Pull-up to VCCIO (nominal value: 120 kΩ)

Weak pull-up to VCCIO (nominal value: 480 kΩ)

Pull-down to AGND (nominal value: 120 kΩ)

Weak pull-down to AGND (nominal value: 480 kΩ)

Weak PU

PD

Weak PD

PT2000

9

NXP Semiconductors

4

Functional description

4.1

Introduction

The PT2000 is a mixed signal IC for engine injector and electrical valve control, which provides a cost effective, flexible, and smart, high-

side and low-side MOSFET gate driver. The device includes both individual charge pump outputs for each high-side pre-driver and high-

voltage DC/DC converter pre-driver. Gate drive, diagnostics, and protection against external faults, are managed through six independent

and concurrent digital microcores. Each of the three logic channels including two microcores and their own code RAM and data RAM. The

internal microcode is protected against theft via encryption and corruption via check sums. Those microcores are optimized to control

power MOSFET with a small latency time. The PT2000 can control three banks of two injectors each or three banks with one injector per

bank for full overlap,

4.2

Features

High-side and low-side pre-drivers

• Seven high-side pre-drivers for logic level N-channel MOSFETs using four programmable slew rates

• Six low-side pre-drivers for logic level N-channel MOSFETs using four programmable slew rates

• Integrated bootstrap circuitry for each high-side pre-driver

• Integrated charge pump circuitry for each high-side pre-driver with 100% duty cycle capability

• Configurable automatic freewheeling capability between high-side and low-side

DC/DC converter

• Two low-side pre-driver, for a logic level N-channel MOSFET, can be optionally dedicated to providing a boost DC-DC converter with

four programmable slew rates

• Three different control modes to reduce power dissipation (manual, hysteretic, resonant)

Current measurement

• Four independent current measurement blocks

• Two current measurements (channel 5 and 6) are optionally configurable to support DC/DC converters

Diagnostics and monitoring

• V_DSand V_SRCmonitoring (programmable values) for fault protection and diagnostics

• V_BOOSTmonitoring

• V_BATmonitoring

• Temperature monitoring

Integrated end of injection detection

• Accurate detection of end of injection for each high-side source and low-side drain without any external component needed.

Power supplies

• Integrated 7.0 V linear regulator (VCCP) for the HS/LS gate power supply ⁽²⁾

• Integrated 2.5 V linear regulator (VCC2P5) for the digital core supply based on the VCC5 input supply

• External 5.0 V supply (VCC5)

• Selectable VCCIO external supply (5.0 V or 3.3 V) for digital I/O

Digital block

• Six digital microcores, each with their own ALU, and full access to the system crossbar switch

• Three memory banks: 1024 x 16-bit of code RAM with built-in error detection and 64 x 16-bit of data RAM

• Memory BIST and Logic BIST activated by the SPI, with pass/fail status

Control interface

• 16-bit slave SPI up to 10 MHz - two protocols - programmable slew rate

• 16 general purpose digital IOs able to sustain up to 36 V

• Independent direct pre-driver inhibition input for safety purposes

PT2000

NXP Semiconductors

10

5

Electrical characteristics

5.1

Maximum ratings

Table 4. Maximum ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Electrical ratings

V_BOOSTMAX

V_BATT

Ratings

Min.

Max.

Unit

Notes

DC voltage at VBOOST

DC voltage at VBATT

DC voltage at VCC5

DC voltage at VCCIO

DC voltage at VCC2P5

0

72

36

3.0

36

V

-0.3

V_CC5

V_CCIO

V_CC2P5

V_DIG

DC voltage at CLK, MISO, MOSI, SCLK, CSB, IRQB, RESETB

DC voltage at DRVEN

V_{DRV_EN}

V_STARTX

V_FLAGX

DC voltage at STARTx

DC voltage at FLAGx

-1.0

18

36

(5)

V_START8_V_SENSEStart8 voltage of pins multiplexed with V_SENSEN4

V

-2.5

18

36

V_FLAG4_V_SENSE

Flag4 voltage of pins multiplexed with V_SENSEP4

V_DBG

V_{OA_OUTX}

V_DGND

V_AGND

V_CCP

DC voltage at DBG

-0.3

36

V

DC voltage at OA_1, OA_2, OA_3

DC voltage at DGND

0.3

9.0

DC voltage at AGND

DC voltage at VCCP

S_HSx

• DC voltage

• Transients t <800 ns

• Transients t <400 ns

—

(6)

-3.0

-6.0

-8.0

V_BOOSTMAX

V_{S_HSX}

V

B_HSx

—

(6)

• V_BATT-V_{B_HSx}must not exceed 40 V

-0.3

-2.0

-4.0

V_{S_HSX}

V_{BS_HSX_CL}

+

V_{B_HSX}

V_{G_HSX}

V_{G_LSX}

V

• Transients t <800 ns

• Transients t <400 ns

DC voltage at G_HSx

V_{S_HSx}- 0.3 V_{B_HSx}+0.3

G_LSx

• DC voltage

-0.3

-1.5

V_CCP+ 0.3

V_CCP+ 1.5

—

• Transients t < 5.0 μs; V_{CCP_MAX}= 8.0 V; energy of pulses < 0 V or > V_CCPis

limited to 2.0 μJ due to capacitive coupling

(6)

D_LSx

• DC voltage

• Transients t < 400 ns

—

V_{D_LSX}

-3.0

-8.0

75

V

(6)

PT2000

11

NXP Semiconductors

Table 4. Maximum ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Ratings

Min.

Max.

Unit

Notes

DC voltage at VSENSEN1/2/3

• Static at VCC5 < 10 V

• Dynamic for max 5.0 μs, 1.0 kHz repetition rate at VCC5, 5.25 V

• Dynamic for max 1.0 μs at VCC5 < 5.25 V

—

(6)

-1.0

-5.0

-15

1.0

5.0

15

V_VSENSEN1/2/3

V

DC voltage at VSENSEP1/2/3

• DC voltage at VCC5 < 10 V

• Dynamic for max 5.0 μs, 1.0 kHz repetition rate at VCC5 < 5.25 V

• Dynamic for max 1.0 μs at VCC5 < 5.25 V

—

(6)

-2.5

-5.0

-15

2.5

5.0

15

V_VSENSEP1/2/3

V

DC voltage at VSENSEN5/6

• DC voltage at VCC5 < 10 V

• Dynamic for max 5.0 μs, 1.0 kHz repetition rate at VCC5 < 5.25 V

• Dynamic for max 1.0 μs at VCC5 < 5.25 V

—

(6)

-3.0

-5.0

-15

1.0

5.0

15

V_VSENSEN5/6

DC voltage at VSENSEP5/6

• DC voltage at VCC5 < 10 V

• Dynamic for max 5.0 μs, 1.0 kHz repetition rate at VCC5 < 5.25 V

• Dynamic for max 1.0 μs at VCC5 < 5.25 V

—

(6)

-4.2

-5.0

-15

2.5

5.0

15

V_VSENSEP5/6

ESD voltage

• Human body model (HBM)

VBOOST, VBATT, S_HSx

D_LSx

V

-4000

-8000

-2000

4000

8000

2000

ESD-HBM1

ESD-HBM2

ESD-HBM3

(7), (8)

V

All other pins

• Machine model

Corner pins

V

-750

-500

750

500

ESD-CDM1

ESD-CDM2

All other pins

Thermal ratings

Operating temperature

• Ambient

• Junction

T

A

-40

125

150

°C

T

J

T

Temperature monitoring threshold

Storage ambient temperature

167

-55

187

150

°C

THRESHOLD

T

STG

Thermal resistance

R_θJA

(9)

Thermal resistance junction to ambient

Thermal resistance junction to case top

Thermal resistance junction to case bottom

—

25.3

13.2

0.8

°C/W

(10)

(11)

R_θJCTOP

R_θJCBOTTOM

Notes

5. With series resistor of 3.3 kΩ ±±20 at the pin

6. Guaranteed by design.

7. Human body model (HBM) per JESD22-A114 - 100 pF, 1.5 kΩ

8. Charge device model (CDM) per JESD22-C101.

9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal

10. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1).

11. Thermal resistance between the die and the solder pad on the bottom of the package based on the simulation without internal resistance

PT2000

NXP Semiconductors

12

5.2

Power supply electrical characteristics

Table 5. PT2000 static electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

VBATT input supply

VBATT power supply input voltage, normal operation

• Internal VCCP regulator

• External VCCP regulator

V_BATT

5.0

13.5

—

16

72

V

(12)

VBATT power supply input voltage during load dump duration <

500 ms

V_{BATT_LOADDUMP}

18

—

40

• Internal VCCP regulator

VBATT power supply current in reset state, V_CC5= V_CCIO= 0.0 V

• V_BATT= 13.5 V

I_{VBATT_LEAK}

I_{VBATT_OPER}

I_{VBATT_LEAK}

—

150

600

180

800

μA

mA

μA

• V_BATT= 40 V

VBATT power supply current in normal operation V_BATT= 16 V

• DRVEN low, internal VCCP reg. off

• DRVEN low, Internal VCCP reg. on

—

0.9

4.5

104.5

2.5

6.0

106

• DRVEN high, VCCP max. load 100 mA

VBATT power supply current in reset state, V_CC5= V_CCIO= 0.0 V

• V_BATT= 13.5 V

—

150

600

180

800

• V_BATT= 40 V

VBOOST input supply

Leakage current from V_BOOST, during reset state with

V

_CC5= V_CCIO= 5.0 V

• V_BOOST= V_BAT= 13.5 V

65

240

400

—

90

370

600

I_{VBOOST_LEAK}

μA

• V_BOOST= V_BAT= 40 V

• V_BOOST= V_BAT= 65 V

Contributors (13.5 V): V_BOOSTvolt. div.: 65 μA

I_{VBOOST_OPER}

VCC5 input supply

V_CC5

Operating current from V_BOOST= 65 V

—

3.9

5.75

mA

VCC5 supply input voltage

4.75

4.0

5.0

5.25

V

(12)

V_{CC5_DIGITAL}

VCC5 supply input voltage for digital part functional only

VCC5 supply current

• f_SYS= 24 MHz, 7 HS load biasing enabled, no microcore running

—

53

65

40

66.4

81.4

50

I_VCC5

mA

• f_SYS= 24 MHz, 7 HS load biasing enabled, all microcores running

• LBIST running, bias disabled

V_OVVCC5

V_{OVVCC5_VCCP}

V_UVVCC5-

VCC5 overvoltage threshold

7.5

6.2

4.3

4.35

30

8.5

6.9

4.45

4.5

50

10

7.5

4.7

4.75

85

V

VCC5 overvoltage threshold for VCCP shutdown

VCC5 undervoltage low-voltage threshold

VCC5 undervoltage high-voltage threshold

VCC5 undervoltage hysteresis

V

V_UVVCC5+

V

V_{UVVCC5_HYST}

mV

Notes

12. Guaranteed by design.

PT2000

13

NXP Semiconductors

Table 5. PT2000 static electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

1.3

—

Max.

Unit

Notes

VCC5 input supply (continued)

T_{FILTER_UVVCC5}

VCC5 UV anti-glitch filter delay time

0.8

2.0

μs

VCCIO INPUT SUPPLY

V_CCIO

VCCIO supply input voltage

3.0

5.25

V

VCCIO supply current

• f_SYS= 24 MHz, no microcore running

• f_SYS= 24 MHz, all microcores running

—

I_VCCIO

—

38

1.5

70

—

μA

mA

(13)

VCCP input supply

V_CCP

VCCP output voltage, 0.0 mA < I_VCCP< 100 mA

V_CCPinput voltage range (V_CCPexternally supplied)

V_CCPexternal output capacitor

6.5

5.0

1.0

7.0

—

7.5

9.0

14

V

V_{CCP_EXT}

C_VCCP

(14)

4.7

μF

V_BATTto V_CCPvoltage dropout

• V_BATT= 5.0 V and I_VCCP= -50 mA

—

180

110

40

• V_BATT= 5.0 V and I_VCCP= -30 mA

• V_BATT= 5.0 V and I_VCCP= -10 mA

• V_BATT= 5.0 V and I_VCCP= -100 mA

ΔV_VCCP

mV

350

V_UVVCCP-

V_UVVCCP+

VCCP undervoltage low-voltage threshold

VCCP undervoltage high-voltage threshold

VCCP undervoltage hysteresis

4.3

4.4

30

4.5

4.55

50

4.68

4.73

70

V

V_{UVVCCP_HYST}

mV

V_CCPoutput current (average during PWM operation)

9.0 V < V_BATT< 18 V

I_VCCP

—

100

mA

I_{VCCP_MAX}

VCCP output current limitation

150

0.8

200

1.3

250

2.0

mA

t_{FILTER_UVVCCP}

VCCP UV anti-glitch filter delay time

μs

VCC2P5 internal regulator

V_CC2P5

VCC2P5 supply output voltage

2.375

0.5

2.5

1.0

2.625

3.0

V

(15)

C_VCC2P5

VCC2P5 external output capacitor

μF

VCC2P5 supply output current

• f_SYS= 24 MHz, all microcores running

I_VCC2P5

—

-15

-50

mA

I_{VCC2P5_LIM}

V_PORESETB-

V_PORESETB+

VCC2P5 supply output current limit

-50

2.0

2.07

50

93

2.11

2.19

75

140

2.21

2.3

mA

V

VCC2P5 voltage threshold for asserting PORESETB

VCC2P5 voltage threshold for deasserting PORSETB

V

V_{PORESETB_HYST}PORESETB voltage hysteresis

t_{D_PORESETB}PORESETB switching time

Notes

13. Guaranteed by design.

100

1.5

mV

μs

—

0.7

14. For VCCP: “For EMC purpose adding 1.0 μF + 100 nF caps in parallel connected to PGND is recommended

15. For VCC2P5: “For EMC purpose adding 1.0 μF + 100 nF caps in parallel connected to DGND is recommended

PT2000

NXP Semiconductors

14

Table 5. PT2000 static electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Battery voltage monitor

(16)

V_{BATT_MONITOR}

R_{VBATT_IN}

Input voltage range

5.0

350

—

500

36

—

V

Input impedance

kΩ

G_{VBATT_DIV}

V_BATTvoltage divider ratio

1/16

15.5

2.5

—

f_{CVBATT_DIV}

V_BATTanalog filter cutoff frequency

DAC reference voltage

DAC LSB

10

20

kHz

V

V_{VBATT_REF}

V_{VBATT_DAC_LSB}

2.475

—

2.525

—

39.06

mV

DAC minimum output voltage

• DAC code = 0h

V_{VBATT_DAC_OUT_}

—

0.0

—

V

MIN

DAC maximum output voltage

• DAC code = 3Fh

V_{VBATT_DAC_OUT_}

2.461

MAX

ε_VBATT

V_BATTmeasurement total error (V_BATT> 5.0 V)

V_BATTDAC settling time

-5.0

—

1.0

—

5.0

0.9

%

t_{VBATT_DAC}

μs

Boost voltage monitor

V_BOOSTMAX

R_{VBOOST_IN}

G_{VBOOST_DIV}

Input voltage range

0.0

400

—

640

1/32

1/4

72

—

V

Input impedance

kΩ

V_BOOSTvoltage divider ratio (boost monitor mode)

1/32* 0.996

1/4* 0.996

—

1/32* 1.004

1/4* 1.004

—

G_{UV_VBOOST_DIV}V_BOOSTvoltage divider ratio (UV V_BOOSTmode)

V_{VBOOST_DAC_LSB}DAC LSB

9.77

—

mV

%

ε_VBOOST

Notes

V_BOOSTmeasurement total error (4.85 V to 72 V)

-2.0

2.0

16. This limitation is only for the V_BATADC, if V_BATis > 36 V, then V_BATmonitoring results will saturate. It means in case V_BAT> 36 V, the V_BAT

monitoring feature will not work but device will be 100 % functional until V_BAT= 72 V.

PT2000

15

NXP Semiconductors

5.3

High-side pre-driver electrical characteristics

Table 6. High-side pre-driver electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

High-side pre-driver

S_HSx pin operating voltage

Transients t <400 ns

Transients t <800 ns

-3.0

-6.0

-8.0

—

V_BOOSTMAX

(17)

V_{S_HSX}

—

V

V_{S_HSX}

4.0

+

V_{S_HSX}

8.0

+

V_{B_HSX}

B_HSx pin operating voltage

—

(18)

(17)

V_{BS_HSX_CL}

V_{G_HSX}

B_HSx-S_HSx clamp voltage

G_HSx operating voltage

6.5

7.3

—

8.0

V

V_{S_HSX}

V_{B_HSX}

S_HSx leakage current biasing switched Off:

• V_{S_HSX}= V_BOOSTMAX

—

1000

250

120

100

• V_{S_HSX}= 13.5 V

• V_{S_HSX}= 7.0 V

• V_{S_HSX}= 4.0 V

I_{S_HSX_SINK_OFF}

μA

S_HSx leakage current when pre-driver on (biasing switched Off)

• V_{S_HSX}= 7.0 V

I_{S_HSX_SINK_ON}

—

220

μA

PWM frequency

• Internal V_CCPand V_BATT≥ 9.0 V

• Internal V_CCPand 5.0 V ≤ V_BATT≤ 9.0 V

• External V_CCPand 9.0 V ≤ V_BATT

0.0

—

100

50

100

(17)

f_{G_HSX_PWM}

kHz

DC_{G_HSX}

Duty cycle

0.0

—

100

1.0

%

t_{ON_HSX_MIN}

High-side driver minimum PWM on time

μs

External high-side MOSFET effective gate charge

• f_PWM≤ f

• f_PWM≤ 67 kHz

Q_{G_HSX}

—

40

55

50

75

nC

G_HSx_PWM

G_HSx current (average during PWM operation) Q = Q

,

(17)

G

G_HSX

I_{G_HSX_PWM}

—

4.0

5.0

mA

f

_PWM= 100 kHz

Peak source gate drive current

Peak sink gate drive current

High-side pre-driver dynamic

t_{R_G_HSX}

t_{F_G_HSX}

(17)

I_{G_HSx_SRC}

I_{G_HSx_SINK}

—

230

440

—

mA

(17)

Turn on rise time, 10%-90% of out voltage, V_CCP= 7.0 V, at open pin

Turn off fall time, 90%-10% of out voltage, V_CCP= 7.0 V, at open pin

Max permissible slew rate at the S_HSX pin

4.5

5.0

-125

40

—

25

ns

25

(17)

SR_{S_HSX}

600

100

125

100

V/μs

ns

(17)(19)

t_{DON_G_HSX_300}

t_{DOFF_G_HSX_300}

t_{DON_G_HSX_50}

t_{DOFF_G_HSX_50}

Notes

Turn on propagation delay at 300 V/μs slew rate

Turn off propagation delay at 300 V/μs slew rate

40

ns

Turn on propagation delay at 50 V/μs slew rate

65

ns

Turn off propagation delay at 50 V/μs slew rate

50

ns

17. Guaranteed by design.

18. VB_HSx has to be 2.0 V above PGND for full function (switch on) of the pre-driver

19. 10% of output voltage change, C_LOAD= 4.7 nF; R_G= 40.2 Ω, V_CCP= 7.0 V

PT2000

NXP Semiconductors

16

Table 6. High-side pre-driver electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

High-side pre-driver dynamic (continued)

(20)(21)

t_{DON_G_HSX_25}

t_{DOFF_G_HSX_25}

t_{DON_G_HSX_12.5}

Turn on propagation delay at 25 V/μs slew rate

Turn off propagation delay at 25 V/μs slew rate

Turn on propagation delay at 12.5 V/μs slew rate,

100

70

—

200

150

310

170

ns

160

90

t_{DOFF_G_HSX_12.5}Turn off propagation delay at 12.5 V/μs slew rate

HS pre-driver safe off

R_{PD_HSX}

Slew rate control

R_{DS_HSX_P (00)}

R_{DS_HSX_N (00)}

R_{DS_HSX_P (01)}

R_{DS_HSX_N (01)}

R_{DS_HSX_P (10)}

R_{DS_HSX_N (10)}

R_{DS_HSX_P (11)}

R_{DS_HSX_N (11)}

G_HSX to S_HSX pull-down resistor

500

—

2000

kΩ

G_HSx pMOS R_DS(on)(00) 300 V/μs

G_HSx nMOS R_DS(on)(00) 300 V/μs

G_HSx pMOS R_DS(on)(01) 50 V/μs

G_HSx nMOS R_DS(on)(01) 50 V/μs

G_HSx pMOS R_DS(on)(10) 25 V/μs

G_HSx nMOS R_DS(on)(10) 25 V/μs

G_HSx pMOS R_DS(on)(11) 12.5 V/μs

G_HSx nMOS R_DS(on)(11) 12.5 V/μs

7.5

2.5

61

14.6

5.9

85

31.4

16.5

115

50

Ω

23

35

122

47

169

69

230

100

460

199

245

94

337

138

Notes

20. Guaranteed by design.

21. 10% of output voltage change, C_LOAD= 4.7 nF; R_G= 40.2 Ω, V_CCP= 7.0 V

5.4

Low-side (LS1-LS6) pre-driver electrical characteristics

Table 7. Low-side pre-driver electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Low-side pre-driver LS1-6

(22)

V

G_LSx operating voltage

0.0

—

V_CCP

V

G_LSx

D_LSx leakage current (biasing switched off)

• V

= 13.5 V

= 40 V

I

10

—

110

320

μA

D_LSx

S_LSx_sink

PWM frequency

• Nominal

• Short period of switching during 50 μs every 1ms

(22)

f

0.0

—

100

200

kHz

%

G_LSx_PWM

DC

Duty cycle

0.0

—

100

G_LSx

External low-side MOSFET effective gate charge

• f_PWM≤ f_{G_LSx_PWM}

• f_PWM≤ 67 kHz

• f_PWM≤ 50 kHz

—

30

55

—

50

75

100

Q

nC

G_LSx

Notes

22. Guaranteed by design.

PT2000

17

NXP Semiconductors

Table 7. Low-side pre-driver electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Low-side pre-driver LS1-6 (continued)

G_LSx current (average during PWM operation)

• QG = QG_LSX; f_PWM= 100 kHz

(23)

I

—

3.0

5.0

mA

G_LSx_PWM

(23), (24)

I

Peak source gate drive current

Peak sink gate drive current

—

230

440

—

mA

G_LSx_SRC

I

G_LSx_SINK

Dynamic low-side pre-driver LS1-6

Turn on rise time, 10% to 90% of output voltage; VCCP = 7.0 V; at

open pin

(23)

T_{R_G_LSX}

5.0

—

25

ns

Turn off fall time, 90% to 10% of output voltage; VCCP = 7.0 V; at open

T_{F_G_LSX}

(23), (25)

T_{DON_G_LSX_300}

Turn on propagation delay at 300 V/μs slew rate

10

15

—

70

ns

T_{DOFF_G_LSX_300}Turn off propagation delay at 300 V/μs slew rate

T_{DON_G_LSX_50}

T_{DOFF_G_LSX_50}

T_{DON_G_LSX_25}

T_{DOFF_G_LSX_25}

T_{DON_G_LSX_12.5}

Turn on propagation delay at 50 V/μs slew rate

Turn off propagation delay at 50 V/μs slew rate

Turn on propagation delay at 25 V/μs slew rate

Turn off propagation delay at 25 V/μs slew rate

Turn on propagation delay at 12.5 V/μs slew rate

80

120

150

T_{DOFF_G_LSX_12.5}Turn off propagation delay at 12.5 V/μs slew rate

LS pre-driver safe off

R_{PD_LSX}

G_LSX to PGND pull-down resistor

25

50

90

kΩ

Low-side pre-driver LS1-6

R_{DS_LSX_P (00)}

R_{DS_LSX_N (00)}

R_{DS_LSX_P (01)}

R_{DS_LSX_N (01)}

R_{DS_LSX_P (10)}

R_{DS_LSX_N (10)}

R_{DS_LSX_P (11)}

R_{DS_LSX_N (11)}

G_LSx pMOS R_DS(on)(00) 300 V/μs

7.5

2.5

61

14.6

5.9

84

31.3

16.5

115

50

Ω

G_LSx nMOS R_DS(on)(00) 300 V/μs

G_LSx pMOS R_DS(on)n (01) 50 V/μs

G_LSx nMOS R_DS(on)(01) 50 V/μs

G_LSx pMOS R_DS(on)(10) 25 V/μs

G_LSx nMOS R_DS(on)(10) 25 V/μs

G_LSx pMOS R_DS(on)(11) 12.5 V/μs

G_LSx nMOS R_DS(on)(11) 12.5 V/μs

23

35

122

47

170

69

230

100

460

199

245

94

337

138

Notes

23. Guaranteed by design.

24.

25.

V

= V

= 7.0 V and fastest slew rate

CCP

GS

10% of output voltage change; C_LOAD= 4.7 nF; R = 40.2 Ω; V_CCP= 7.0 V

G

PT2000

NXP Semiconductors

18

5.5

Low-side high-speed (LS7-LS8) pre-driver electrical characteristics

Table 8. High-speed low-side pre-driver electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Low-side pre-driver 7 and 8

(26)

(27)

V_{G_LS7/8}

f_{G_LS7/8_PWM}

DC_{G_LS7/8}

G_LS7/8 operating voltage

0.0

—

V_CCP

400

V

kHz

%

PWM frequency

Duty cycle

100

External low-side MOSFET gate charge

• f_PWM= 400 kHz

• f_PWM= 300 kHz

• f_PWM= 240 kHz

—

30

60

75

100

Q_{G_LS7/8}

nC

G_LS7/8 current (average during PWM operation)

• f_PWM= 400 kHz

—

12

9.0

3.0

1.5

24

22.5

7.5

(27)

• f_PWM= 300 kHz

• f_PWM= 100 kHz

• f_PWM= 50 kHz

I_{G_LS7/8_PWM}

mA

3.75

(27), (27)

I_{G_LS7/8_SRC}

I_{G_LS7/8_SINK}

Peak source gate drive current

Peak sink gate drive current

—

680

—

mA

2200

Dynamic low-side pre-driver L7 and 8

Turn on rise time

(27)

t_{R_G_LS7/8_1500}

t_{F_G_LS7/8_1500}

t_{R_G_LS7/8}

• at 1500 V/μs slew rate 10% to 90% of out voltage; V_CCP=7.0 V; at

the open pin

3.5

5.0

—

11

25

ns

Turn off fall time

• at 1500 V/μs slew rate 90% to 10% of out voltage; V_CCP= 7.0 V; at

the open pin

Turn on rise time

• at 300-25 V/μs slew rate 10% to 90% of out voltage; V_CCP= 7.0 V;

at the open pin

Turn off fall time

t_{F_G_LS7/8}

• at 300-25 V/μs slew rate 90% to 10% of out voltage; V_CCP= 7.0 V;

at the open pin

Turn on propagation delay

• at 1500 V/μs slew rate 10% of out voltage change

(27), (28)

t_{DON_G_LS7_1500}

t_{DOFF_G_LS7_1500}

t_{DON_G_LS7_300}

10

—

50

70

ns

Turn off propagation delay

• at 1500 V/μs slew rate 10% of out voltage change

Turn on propagation delay

• at 300 V/μs slew rate 10% of out voltage change

Turn off propagation delay

• at 300 V/μs slew rate 10% of out voltage change

t_{DOFF_G_LS7_300}

Notes

26. Guaranteed by design.

27. At the fastest slew rate setting with minimum R_{G_LS8}of 2.0 Ω and V_CCP/V_GS= 7.0 V

28. C_LOAD= 4.7 nF; R_G= 40.2 Ω, V_CCP= 7.0 V

PT2000

19

NXP Semiconductors

Table 8. High-speed low-side pre-driver electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Dynamic low-side pre-driver L7 and 8

Turn on propagation delay

• at 50 V/μs slew rate 10% of out voltage change

(29), (30)

t_{DON_G_LS7_50}

t_{DOFF_G_LS7_50}

t_{DOFF_G_LS7_25}

15

—

100

120

ns

Turn off propagation delay

• at 50 V/μs slew rate 10% of out voltage change

Turn off propagation delay

• at 25 V/μs slew rate 10% of out voltage change

Turn off propagation delay

• at 25 V/μs slew rate 10% of out voltage change

t_{DOFF_G_LS7_25}

R_{PD_LS7/8}

15

25

—

120

90

ns

G_LS7/8 to PGND pull-down resistor

50

kΩ

Slew rate control low-side 7 and 8

R_{DS_HSX_P (00)}

R_{DS_HSX_N (00)}

R_{DS_HSX_P (01)}

R_{DS_HSX_N (01)}

R_{DS_HSX_P (10)}

R_{DS_HSX_N (10)}

R_{DS_HSX_P (11)}

R_{DS_HSX_N (11)}

G_LS7/8 pMOS R_DS(on)(00) 1500 V/μs

2.6

0.5

7.5

2.5

61

5.0

1.1

14.6

5.9

85

10.7

2.9

Ω

G_LS7/8 nMOS R_DS(on)(00) 1500 V/μs

G_LS7/8 pMOS R_DS(on)(01) 300 V/μs

G_LS7/8 nMOS R_DS(on)(01) 300 V/μs

G_LS7/8 pMOS R_DS(on)(10) 50 V/μs

G_LS7/8 nMOS R_DS(on)(10) 50 V/μs

G_LS7/8 pMOS R_DS(on)(11) 25 V/μs

G_LS7/8 nMOS R_DS(on)(11) 25 V/μs

31.3

16.5

115

50

23

35

122

47

170

69

230

100

Notes

29. Guaranteed by design.

30.

C_LOAD= 4.7 nF; R_G= 40.2 Ω, V_CCP= 7.0 V

5.6

High-side VDS VSRC monitoring electrical characteristics

Table 9. High-side VDS/SRC monitor electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

High-side V_DS/SRCmonitor

High-side V_DS/SRCmonitoring functional range S_HSx

• DC voltage

• Transients t < 400 ns

-3.0

-6.0

-8.0

—

72

(31)

V_{S_HS_VDS}

V

• Transients t < 800 ns

High-side V_DS/SRCmonitoring functional range S_HSx

• Full functionality

V_{VBATT_VDS}

5.5

5.0

—

72

5.5

V

• Limited functionality (V

3.5 V is at 3.0 V min)

DS_HS_Th

High-side V_DS/SRCmonitoring functional range VBOOST

• Full functionality

V_{VBOOST_VDS}

5.5

5.0

—

72

5.5

• Limited functionality (V

3.5 V is at 3.0 V min)

DS_HS_Th

Notes

31. Guaranteed by design.

PT2000

NXP Semiconductors

20

Table 9. High-side VDS/SRC monitor electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

High-side V_DS/SRCmonitor (continued)

V_{DS_HS_TH (0000)}

V_{DS_HS_TH (1001)}

V_{DS_HS_TH (1010)}

V_{DS_HS_TH (1011)}

V_{DS_HS_TH (1100)}

V_{DS_HS_TH (0001)}

V_{DS_HS_TH (0010)}

V_{DS_HS_TH (0011)}

V_{DS_HS_TH (0100)}

V_{DS_HS_TH (0101)}

V_{DS_HS_TH (0110)}

High-side V_DSthreshold (0000)

High-side V_DSthreshold (1001)

-0.03

0.07

0.155

0.25

0.345

0.44

0.9

0.0

0.10

0.2

0.03

0.13

0.245

0.35

0.455

0.56

1.1

V

High-side V_DSthreshold (1010)

High-side V_DSthreshold (1011)

High-side V_DSthreshold (1100)

High-side V_DSthreshold (0001)

High-side V_DSthreshold (0010)

High-side V_DSthreshold (0011)

High-side V_DSthreshold (0100)

High-side V_DSthreshold (0101)

High-side V_DSthreshold (0110)

0.3

0.4

0.5

1.0

1.35

1.8

1.5

1.65

2.2

2.0

2.29

2.76

2.45

2.95

2.61

3.14

High-side V_DSthreshold (0111)

• V_{VBATT_VDS}= 5.5 V to 72 V, V_{VBOOST_VDS}= 5.5 V to 72 V

V_{DS_HS_TH (0111)}

3.23

3.00

3.45

3.67

V

• V_{VBATT_VDS}= 5.0 V to 5.5 V, V_{VBOOST_VDS}= 5.0 V to 5.5 V

t_{TH_HSVDS}

High-side V_DS/SRCthreshold settling time

—

0.4

0.0

0.10

0.2

0.3

0.4

0.5

1.0

1.5

2.0

2.55

3.0

3.5

1.0

0.03

0.13

0.245

0.35

0.455

0.56

1.1

μs

V

V_{SRC_HS_TH (0000)}High-side V_SRCthreshold (0000)

V_{SRC_HS_TH (1001)}High-side V_SRCthreshold (1001)

V_{SRC_HS_TH (1010)}High-side V_SRCthreshold (1010)

V_{SRC_HS_TH (1011)}High-side V_SRCthreshold (1011)

V_{SRC_HS_TH (1100)}High-side V_SRCthreshold (1100)

V_{SRC_HS_TH (0001)}High-side V_SRCthreshold (0001)

V_{SRC_HS_TH (0010)}High-side V_SRCthreshold (0010)

V_{SRC_HS_TH (0011)}High-side V_SRCthreshold (0011)

V_{SRC_HS_TH (0100)}High-side V_SRCthreshold (0100)

V_{SRC_HS_TH (0101)}High-side V_SRCthreshold (0101)

V_{SRC_HS_TH (0110)}High-side V_SRCthreshold (0110)

V_{SRC_HS_TH (0111)}High-side V_SRCthreshold (0111)

-0.03

0.07

0.155

0.25

0.345

0.44

0.9

1.35

1.8

1.65

2.2

2.38

2.85

3.33

2.72

3.15

3.68

PT2000

21

NXP Semiconductors

5.7

Low-side VDS VSRC monitoring electrical characteristics

Table 10. Low-side V_DS/SRCmonitor electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Low-side V_DSmonitor

Low-side V_DSmonitoring functional range D_LSx

• DC voltage

• Transients t < 400 ns

V_{D_LSX_VDS}

-3.0

-8.0

—

75

V

V_{DS_LS_TH (0000)}

V_{DS_LS_TH (1001)}

V_{DS_LS_TH (1010)}

V_{DS_LS_TH (1011)}

V_{DS_LS_TH (1100)}

V_{DS_LS_TH (0001)}

V_{DS_LS_TH (0010)}

V_{DS_LS_TH (0011)}

V_{DS_LS_TH (0100)}

V_{DS_LS_TH (0101)}

V_{DS_LS_TH (0110)}

V_{DS_LS_TH (0111)}

t_{TH_LSVDS}

Low-side V_DSthreshold (0000)

Low-side V_DSthreshold (1001)

Low-side V_DSthreshold (1010)

Low-side V_DSthreshold (1011)

Low-side V_DSthreshold (1100)

Low-side V_DSthreshold (0001)

Low-side V_DSthreshold (0010)

Low-side V_DSthreshold (0011)

Low-side V_DSthreshold (0100)

Low-side V_DSthreshold (0101)

Low-side V_DSthreshold (0110)

Low-side V_DSthreshold (0111)

Low-side V_DSthreshold settling time

-0.03

0.07

0.155

0.25

0.345

0.44

0.9

0.0

0.10

0.2

0.3

0.4

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.4

0.03

0.13

0.245

0.35

0.455

0.56

1.1

V

μs

1.35

1.8

1.65

2.2

2.38

2.85

3.33

—

2.63

3.15

3.68

1.0

(32)

Low-side V_DSmonitor D_ls7/D_ls8 for DC/DC

V_{D_LSX_VDS}

Low-side V_DSvoltage range D_LSx

-3.0

1.8

—

75

V

V_{DS_LS_TH_DC}

Low-side V_DSthreshold for DC/DC (0100)

2.06

2.2

(0100)

V_{DS_LS_TH_DC}

Low-side V_DSthreshold for DC/DC (0101)

2.25

2.5

2.75

V

(0101)

(32)

t_{VDS_DCDC_PD}

R_{VDS_78_IN}

Notes

32. Guaranteed by design.

Comparator propagation delay time

—

50

—

ns

Input impedance V_{DS_78}

200

350

kΩ

PT2000

NXP Semiconductors

22

5.8

Load bias electrical characteristics

Table 11. Load bias electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Load biasing structures

(33)

(34)

(35)

I_{BIAS_HS}

Current source normal S_HSx (x = 1…7)

2.8

4.2

4.0

6.0

10

5.2

7.8

13

mA

I_{BIAS_HS_STRONG}Current source strong S_HSx (x = 2, 4)

I_{BIAS_HS_BOTH}

I_{BIAS_HS_MAX}

I_{BIAS_LS}

Current source strong + normal S_HSx (x = 2, 4)

Total maximum current source S_HSx source current

Current source D_LSx sink saturation current

7.0

36.4

0.98

—

1.09

1.2

S_HSx bias voltage regulation

• V_BATT> 8.0 V, V_CC5> 4.75 V

3.8

—

V_CC5

(V_BATT/2)

200 mV

V_{BIAS_HS}

V

(V_BATT/2) (V_BATT/2)

• V_BATT< 8.0 V, V_CC5> 4.75 V

-200 mV

0.5

-200 mV

—

Equivalent resistance of LS current source

R_{BIAS_LS}

Notes

1.5

kΩ

• V

< 1.0 V

D_LSx

33. Current source can be connected to maximum two D_LSx

34. Current source can be connected to maximum three D_LSx

35. Current source can be connected to maximum five D_LSx

PT2000

23

NXP Semiconductors

5.9

Current measurement electrical characteristics

Current measurement for positive current

5.9.1

This section is applicable for all current measurement paths for positive currents:

• Current measurement channel 1- 4

• Differential amplifier 1- 4

• DAC 1- 4

• Comparator 1- 4

• Current measurement channel 5 - 6

• Differential amplifier 5 - 6

• DAC 5 - 6H and DAC 5 - 6L

• Comparator 5 - 6H and 5 - 6L

Table 12. Current measurement for positive currents

Statistically

evaluated

Symbol

Characteristic

Unit

Notes

Overall current sense error including gain errors and offsets at DAC range of 75% -

100%, after analog offset compensation

• at GDA_diff (00) = 5.8

• at GDA_diff (01) = 8.7

• at GDA_diff (10) = 12.6

• at GDA_diff (11) = 19.3

±3.5

(36) (37)

%

,

ε_CS

At DAC range of 25% to 75%, after analog offset compensation

• at GDA_diff (00) = 5.8

• at GDA_diff (01) = 8.7

• at GDA_diff (10) = 12.6

• at GDA_diff (11) = 19.3

±5.3

(36) (37)

%

,

Notes

36. Guaranteed by design.

37. The tolerance of the 10 mΩ shunt resistor is assumed as ±2.0% (at 4.5 σ). All other input tolerances from the device specification are assumed

at 6 σ.

Table 13. Differential amplifier 1, 2, 3, 4, 5, and 6

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

-1.0

Typ.

—

Max.

1.0

Unit

V

Notes

V_{VSENSENX_DA}

V_{VSENSEPX_DA}

Differential amplifier x functional range V_SENSENx(x = 1…6)

Differential amplifier x functional range V_SENSEPx(x = 1…6)

Differential input voltage range (00)

—

1.5

V

V_{DA_DIFF_IN (00)}

V_{DA_DIFF_IN (01)}

V_{DA_DIFF_IN (10)}

V_{DA_DIFF_IN (11)}

-25.9

-17.3

-12

—

387

258

179

116

mV

• G

= 5.8

DA_DIFF(00)

Differential input voltage range (01)

• G = 8.7

DA_DIFF(01)

Differential input voltage range (10)

• G = 12.6

DA_DIFF(10)

Differential input voltage range (11)

• G = 19.3

-7.8

DA_DIFF(11)

G_{DA_DIFF (00)}

G_{DA_DIFF (01)}

G_{DA_DIFF (10)}

Differential voltage gain (00)

Differential voltage gain (01)

Differential voltage gain (10)

5.71

8.55

5.79

8.68

5.87

8.81

12.32

12.53

12.74

PT2000

NXP Semiconductors

24

Table 13. Differential amplifier 1, 2, 3, 4, 5, and 6 (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Differential voltage gain (11)

Min.

Typ.

19.25

—

Max.

19.58

2.0

Unit

Notes

G_{DA_DIFF (11)}

t_{DA_GAIN_SW}

18.92

(38)

Gain switching settling time

μs

Input impedance V_SENSENx(x = 1…4)

• 1.0 V common mode voltage

R_{VSENSENX_IN}

R_{VSENSEPX_IN}

C_VSENSE

10

—

26

—

kΩ

Input impedance V_SENSEPx(x = 1…4)

• 1.0 V common mode voltage

kΩ

Differential amplifier EMI filter C. It is recommended to place a filter C

between V_SENSEN and P close to the IC for EMI.

330

pF

V_{DA_BIAS}

V_{DA_OUT_OFF}

V_{DA_OUT}

Output bias voltage

240

-140

0.1

250

—

265

220

2.7

mV

V

Maximum output offset voltage error at maximum gain

Differential amplifier x output voltage range

—

DAC 1, 2, 3, 4, 5H, 6H, and 6L (8-bit)

V_{DAC_LSB}

DAC LSB

—

9.77

0.0

—

mV

V

DAC minimum output voltage

• DAC code = 0h

V_{DAC_OUT_MIN}

DAC maximum output voltage

• DAC code = FFh

V_{DAC_OUT_MAX}

—

2.49

—

V

ε_{DAC_DNL}

ε_{DAC_INL}

V_{DAC_OUT_OFF}

t_DAC

DAC differential linearity error

DAC integral linearity error

DAC maximum output offset

DAC settling time

-0.5

-1.0

0.0

—

0.5

1.0

10

LSB

mV

μs

0.9

Voltage comparator 1, 2, 3, 4, 5H, 5L, 6H, and 6L

V_{COMP_IN}

Comparator input voltage

0.0

-25

—

2.7

10

V

V_{COMP_IN_OFF}

Comparator input offset voltage

mV

Current measurement channel 1, 2, 3, 4, 5, and 6 (H and L) detection delays

Detection delay coming from differential amplifier and comparator at

GDA_DIFF(00) = 5.8

(38)

t_{D_CS}

20

500

ns

Notes

38. Guaranteed by design.

PT2000

25

NXP Semiconductors

Table 13. Differential amplifier 1, 2, 3, 4, 5, and 6 (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Differential amplifier 1, 2, 3, 4, 5, and 6 analog offset compensation

Offset compensation voltage range referred to amplifier output offset

at maximum gain

V_{OFFDAC_OUT_MAX}

_POS

(40)

mV

• Offset DAC value = +31

• Offset DAC value = -31

V_{OFFDAC_OUT_MAX}

150

-310

—

310

-150

_NEG

Offset compensation step size referred to amplifier output offset at

maximum gain

V_{OFFDAC_LSB}

5.0

—

10

-5.0

-50

—

5.0

50

LSB

mV

(39)

(41)

V_{CS_OFF_TEMP}

Differential amplifier output offset temperature drift

-0.61

-6.1

—

0.39

3.9

LSB

mV

Residual offset after offset compensation at diff amplifier output for

path shunt ≥ comparator output

V_{CS_OFF_GD}

(40)

t_{OFFCOMP_STEP}

t_OFFCOMP

Offset compensation minimum step time

—

2.0

μs

(40)(42)

Offset compensation runtime to finish compensation

2.0*31 = 62

Notes

39. Guaranteed by design.

40. Gain set to G

= 19.3

DA_DIFF(11)

41. The offset compensation algorithm is implemented so the compensation always stops when the comparator output signal is low, assuming a zero

DAC gain error and INL.

42. Assuming the start from an offset compensation DAC value of 0 is worst case, it has to go to one extreme value (-31 or 31).

5.9.2

Current measurement for negative currents

This section is applicable for all current measurement paths for negative currents:

• Current measurement channel 5 and 6

• Differential amplifier 5 and 6 negative

• DAC 5 and 6 negative

• Comparator 5 and 6 negative

Table 14. PT2000 static electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Overall current sense performance for negative

Overall current sense error including gain errors and offsets

Characteristic

Min.

Typ.

Max.

Unit

Notes

(43) (44)

• at DAC range of 75% to 100% at G

= -2.0

ε_CSNEG

—

±4.4

±8.9

%

,

DANEG_DIFF

• at DAC range of 25% to 75% at G

= -2.0

DANEG_DIFF

Differential amplifier 5, 6 negative

Differential amplifier 5 and 6 negative (negative currents) functional

range V_SENSEN5/6

V_VSENSEN5/

6_DANEG

(43)

-3.0

-4.2

—

1.0

V

Differential amplifier 5 and 6 negative (negative currents) functional

range V_SENSEP5/6

V_VSENSEP5/

6_DANEG

Differential input voltage range

(43)

V_{DANEG_DIFF_IN}

G_{DANEG_DIFF}

-1.125

-1.966

6.0

—

-2.0

—

0.0

-2.034

14

V

• G

= -2.0

DANEG_DIFF

Differential voltage gain

Input impedance V_SENSEN5/6

• 1.0 V common mode voltage

R_{VSENSEN5/6_IN}

kΩ

PT2000

NXP Semiconductors

26

Table 14. PT2000 static electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Differential amplifier 5, 6 negative (continued)

Input impedance V_SENSEP5/6

R_{VSENSEP5/6_IN}

6.0

—

14

kΩ

• 1.0 V common mode voltage

V_{DANEG_IN_OFF}

V_{DANEG_BIAS}

Differential amplifier maximum input offset voltage

-20

—

20

mV

Output bias voltage

240

250

265

Maximum output offset voltage error, including amplifier input offset

and bias voltage offset.

V_{DANEG_OUT_OFF}

V_{DANEG_OUT}

-60

0.0

—

60

mV

V

Differential amplifier x output voltage range

2.7

DAC 5 Neg and 6 Neg (4 Bit)

V_{DACNEG_LSB}

DAC LSB

—

156.3

0.0

—

mV

V

DAC minimum output voltage

• DAC code = 0h

V_{DACNEG_OUT_MIN}

DAC maximum output voltage

• DAC code = Fh

V_{DACNEG_OUT_MAX}

—

2.344

—

V

DAC maximum gain error

• Error of bandgap reference voltage

ε_{DACNEG_GAIN}

-1.0

1.0

%

ε_{DACNEG_DNL}

ε_{DACNEG_INL}

DAC differential linearity error

DAC integral linearity error

-0.063

0.0

—

0.063

10

LSB

mV

μs

V_{DACNEG_OUT_OFF}DAC maximum output offset

t_DACNEGDAC settling time

Voltage comparator 5 Neg and 6 Neg

—

0.9

V_{COMP_IN}

Comparator input voltage

Comparator input offset voltage

0.0

-25

—

2.7

10

V

V_{COMP_IN_OFF}

mV

Current measurement channel 5 Neg and 6 Neg detection delays

Detection delay coming from differential amplifier and comparator

• GDANEG_DIFF = -2.0

(45)

t_{D_CSNEG}

20

—

500

ns

Notes

43. Guaranteed by design.

44. The tolerance of the 10 mΩ shunt resistor is assumed as ±2.0% (at 4.5 σ). All other input tolerances from the device specification are assumed at

6 σ

45. Guaranteed by design.

PT2000

27

NXP Semiconductors

5.10

Analog output (OAx) electrical characteristics

Table 15. Analog output static electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

OAx output PiNS, multiplexer and T&H

V_OAX

OAx output voltage range

OAx output bandwidth

0.0

—

V_CC5

—

V

(46)

BW_OAX

100

kHz

OAx permissible capacitive load

• without series resistor, for digital function

• R_MIN= 200 Ω

• R_MIN= 100 Ω

• R_MIN= 75 Ω

• R_MIN= 50 Ω

—

1.0

5.0

15

—

50

5.0

15

50

100

pF

nF

(46)

C_OAX

50

(46)

PSRR_OAX

G_OAX(00)

G_OAX(01)

G_OAX(10)

G_OAX(11)

G_OAX(ADC)

t_{OAX_GAIN}

OAx power supply rejection

OAx output gain (00)

—

1.33

2.0

3.0

5.33

1.0

—

103

1.357

2.060

3.090

5.49

1.02

2.0

dB

1.303

1.940

2.91

5.17

0.98

—

OAx output gain (01)

OAx output gain (10)

OAx output gain (11)

OAx output gain (ADC)

OAx output gain switching time

(46)

μs

OAx output offset voltage from OAx amplifier

• G_OAx= 1.0

-14

-18

-28

-30

-53

—

14

18

28

30

53

• G_OAx= 1.33

• G_OAx= 2.0

• G_OAx= 3.0

• G_OAx= 5.33

V_{OAX_OFFSET}

mV

OA1/3 input impedance when OaENx = 0

• 2.0 V, impedance to GND

R_{OA1/3_EN0}

—

8000

kΩ

OA2 input impedance when OaENx = 0

• 2.0 V, impedance to GND

R_{OA2_EN0}

t_{OAX_MUX}

350

—

500

10

kΩ

μs

(46)

OAx multiplexer switching time

OAx output voltage drift of T&H in ADC mode over time

• at V_OAx= 1.5 V and after 20 μs

V_{OAX_DRIFT_ADC}

-50

50

mV

Notes

46. Guaranteed by design.

PT2000

NXP Semiconductors

28

5.11

Clock / PLL electrical characteristics

Table 16. Clock / PLL electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Backup clock

f_CLK

Characteristic

Min.

Typ.

Max.

Unit

Notes

CLK pin input frequency

CLK pin input duty cycle

CLK pin voltage

0.94

45

1.0

50

—

1.06

55

MHz

%

DC_CLK

V_CLK

0.0

1.5

1.0

0.3

-25

0.95

48

V_CCIO

2.2

V

V_{IH_CLK}

CLK pin high input voltage threshold

CLK pin low input voltage threshold

CLK pin hysteresis

—

V

V_{IL_CLK}

—

1.65

—

V

V_{HYST_CLK}

t_{CLK_JITTER}

f_{CLK_BACK}

DC_{CLK_BACK}

PLL

—

V

(47)

CLK pin clock edge jitter

—

25

ns

MHz

%

Backup oscillator clock frequency

Backup oscillator clock duty cycle

1.0

50

1.05

52

f_CKSYS24

f_{CKSYS_MOD}

t_{PLL _LOCK}

Cksys output clock frequency 24 MHz

Cksys modulation frequency

PLL lock time

f

*23.5

f

*24

f *24.5

CLK

MHz

kHz

μs

CLK

(48)

—

25

—

40

Cksys rising edge to cksys_cram rising edge T1 CRAM address setup

phase

(49)

t_{CKSYS_T1}

t_{CKSYS_T2}

t_{CKSYS_T3}

Notes

8.75

19.44

—

12.32

—

ns

Cksys rising edge to cksys_c/dram rising edge T2 CRAM/DRAM

address setup phase

Cksys_c/dram rising edge to cksys rising edge T3 CRAM/DRAM

access time

—

47. Guaranteed by design.

48. Divider value is changed every 10 μs

49. The following values take into account an input clock at 0.95 MHz to 1.05 MHz, a PLL multiplication factor of 47 to 49, and an output duty cycle of

45% to 55%.

T1

PLL 48MHz

Cksys 24MHz

Cksys CRAM/

DRAM 24MHz

T2

T3

Figure 4. PLL, DRAM/CRAM system clock

PT2000

29

NXP Semiconductors

5.12

Digital input/output electrical characteristics

Table 17. PT2000 static electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Digital I/OS

Digital pins voltage (IRQB, MISO, MOSI, SCLK, CSB, Startx, Flagx,

DBG, OAx)

V_IOVCCIO

0.0

—

V_CCIO

V

V_IOVCC5

Digital pins voltage (RESETB, DRVEN)

Digital output ready time after POResetB deactivation

RESETB filter time

0.0

—

V_CC5

100

2.0

V

t_DIGIOREADY

t_{FILT_RESETB}

μs

0.2

Digital pins high input voltage threshold (RESETB, IRQB, MOSI,

SCLK, CSB, DRVEN, Startx, Flagx, DBG, OAx)

V_{IH_IO}

V_{IL_IO}

1.5

1.0

0.3

—

2.2

1.65

—

V

Digital pins low input voltage threshold (RESETB, IRQB, MOSI, SCLK,

CSB, DRVEN, STARTx, FLAGx, DBG, OAx)

Digital pins hysteresis (RESETB, IRQB, MOSI, SCLK, CSB, DRVEN,

STARTx, FLAGx, DBG, OAx)

V_{HYST_IO}

Digital pins high output voltage (IRQB, MISO, START1-7, FLAG0-3,

DBG)

• I_OUT> -1.0 mA, no higher current at other I/Os

V_{OH_IO}

V_CCIO-0.3

—

V

Digital pins low output voltage (IRQB, MISO, START1-7, FLAG0-3,

DBG)

V_{OL_IO}

—

0.3

• I_OUT< 1.0 mA, no higher current at other I/Os

Digital pins high output voltage (Start8, Flag4)

• I_OUT> -200 μA

V_{OH_ START8/FLAG4}

V_CC0-0.6

—

V

Digital pins low output voltage (Start8, Flag4)

• I_OUT> -200 μA

V_{OL_ START8/FLAG4}

—

0.6

Digital pins high output voltage (OA2)

• G_OAx= 1.33, IOUT > -1.0 mA

V_{OH_OA2}

2.8

V_CC5-0.6

—

V

• G_OAx= 2.0, IOUT > -1.0 mA

V_{OL_OA2}

t_{R_XXX}

Digital pins low output voltage (OA2), I_OUT< 0.5 mA

—

0.3

12

V

Digital pins output rise time (IRQB, START1-7, FLAG0-3, DBG)

• C_LOAD= 30 pF, 10%-90% of out voltage

3.0

ns

Digital pins output fall time (IRQB, START1-7, FLAG0-3, DBG)

• C_LOAD= 30 pF, 90%-10% of out voltage

t_{F_XXX}

3.0

2.0

—

12

10

ns

Digital pins output delay (IRQB, START1-7, FLAG0-3, DBG)

• C_LOAD= 30 pF, 10% of out voltage

t_{D_XXX}

PT2000

NXP Semiconductors

30

Table 17. PT2000 static electrical characteristics (continued)

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Digital I/OS (continued)

Digital pins output rise time (OA2), 10%-90% of out voltage

• C_LOAD= 30 pF with V_CCIO= 3.3 V

(50)

t_{R_OA2}

t_{F_OA2}

t_{D_OA2}

—

1.4

2.0

μs

• C_LOAD= 30 pF with V_CCIO= 5.0 V

Digital pins output fall time (OA2), 90%-10% of out voltage

• C_LOAD= 30 pF with V_CCIO= 3.3 V

(50)

—

1.4

3.2

• C_LOAD= 30 pF with V_CCIO= 5.0 V

Digital pins output delay (OA2), 10% of out voltage

• C_LOAD= 30 pF with V_CCIO= 3.3 V

(50)

—

2.7

3.0

• C_LOAD= 30 pF with V_CCIO= 5.0 V

Digital pins output rise time (START8, FLAG4)

• CLOAD = 30 pF, 10%-90% of out voltage

(50)

t_{R_START8/FLAG4}

t_{F_START8/FLAG4}

t_{D_START8/FLAG4}

60

—

200

20

ns

Digital pins output fall time (START8, FLAG4)

• CLOAD = 30 pF, 90%-10% of out voltage

Digital pins output delay (START8, FLAG4)

• CLOAD = 30 pF, 10% of out voltage

5.0

(50)

C_{PIN_XXX}

C_{PIN_MISO}

C_{PIN_MOSI}

Digital pins equivalent pin capacitance (IRQB, STARTx, FLAGx, DBG)

Digital pin equivalent pin capacitance (MISO)

—

10

pF

Digital pin equivalent pin capacitance (MOSI)

Pull-up/down resistors

R_{W_PU/PD}Weak pull-up/down resistor

R_PU/PDPull-up/down resistor

200

50

480

120

800

200

kΩ

Notes

50. Guaranteed by design.

PT2000

31

NXP Semiconductors

5.13

Serial peripheral interface electrical characteristics

CSB

(8)

(2)

(1)

(3)

(9)

SCLK

(4)

(7)

MISO

MSB

(6)

LSB

MSB

LSB

MOSI

(5)

Figure 5. SPI timing

Table 18. SPI electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

SPI

(51)

f_SCLK

SCLK pin input frequency - (1)

—

12.5

—

MHz

ns

t_{CSBF_SCLKR}

t_{SCLKF_CSBR}

CSB fall to first SCLK rise - (2)

Last SCLK fall to CSB rise - (3)

1/f_SCLK

—

ns

10 +

t_{R_MISO}

(51)

t_{MISO_VAL}

MISO valid time - (4)

—

ns

(51)

t_{MOSI_SET}

t_{MOSI_HOLD}

t_{CSBR_MISOT}

t_{SCLKF_CSBF}

t_{CSBR_CLKR}

t_{SPI_RESETB_t0}

t_{SPI_RESETB}

MOSI setup time - (5)

10

12.5

—

15

—

ns

μs

MOSI hold time - (6)

CSB rise to MISO tri-state - (7)

SCLK fall (other device) to CSB fall - (8)

CSB rise to SCLK rise (other device) - (9)

SPI setup time after first RESETB rising edge

SPI setup time after each following RESETB rising edge

13

15

100

30

Notes

51. See Figure 5

PT2000

NXP Semiconductors

32

Table 18. SPI electrical characteristics

Characteristics noted under conditions -40 ºC < T_A< +125 ºC, referenced to ground, unless otherwise noted. Typical values noted reflect

the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

SPI MISO driver with VCCIO = 3.3 V

MISO rise time slow setting:

• CL = 30 pF

• CL = 75 pF

• CL = 150 pF

10

20

40

—

30

50

90

t_{R_MISO_S3.3}

t_{F_MISO_S3.3}

t_{R_MISO_F3.3}

t_{F_MISO_F3.3}

ns

MISO fall time slow setting:

• CL = 30 pF

• CL = 75 pF

10

20

40

—

30

50

90

ns

• CL = 150 pF

MISO rise time fast setting:

• CL = 30 pF

• CL = 75 pF

1.5

2.7

4.4

—

13.4

17.1

23.9

ns

• CL = 150 pF

MISO fall time fast setting:

• CL = 30 pF

• CL = 75 pF

1.5

2.7

4.4

—

13.4

17.1

23.9

ns

• CL = 150 pF

SPI MISO driver with VCCIO = 5.0 V

MISO rise time slow setting:

• CL = 30 pF

• CL = 75 pF

• CL = 150 pF

9.0

20

35

—

25

47

77

t_{R_MISO_S5.0}

t_{F_MISO_S5.0}

t_{R_MISO_F5.0}

t_{F_MISO_F5.0}

ns

MISO fall time slow setting:

• CL = 30 pF

• CL = 75 pF

9.0

20

35

—

25

47

77

• CL = 150 pF

MISO rise time fast setting:

• CL = 30 pF

• CL = 75 pF

1.1

2.1

3.6

—

9.6

12.5

17.8

• CL = 150 pF

MISO fall time fast setting:

• CL = 30 pF

• CL = 75 pF

1.1

2.1

3.6

—

9.6

12.5

17.8

• CL = 150 pF

PT2000

33

NXP Semiconductors

6

Functional block description

6.1

Power supplies

6.1.1

VCC5

The PT2000 works with an external supply voltage of 5.0 V connected to the VCC5 pin. This voltage is used for the VCC2P5 regulator,

the load biasing, and to supply the analog blocks. The VCC5 overvoltage monitor is used to disconnect the device from the VCC5 supply

in any overvoltage condition at this pin. This is done to guarantee 36 V robustness of the VCC5 pin.

The VCC5 undervoltage monitor is used to disable all the pre-drivers, as long as the supply voltage at the VCC5 pin is not high enough

to guarantee full functionality of the analog modules of the device. An interrupt request (in case it is enabled) is issued to the

microcontroller as soon as uv_vcc5 is asserted.

6.1.2

VCCIO

The interfaces toward the ECU microcontroller uses the VCCIO voltage for the output drivers and receives the same levels on its inputs.

The voltage level of the I/O pins interfacing the device with the microcontroller (STARTx, FLAGx, RESETB, DBG, SPI pins, CLK, IRQB,

DRVEN, and OA_x, when used as digital I/O) can be selected between 3.3 V and 5.0 V by supplying the device with the desired voltage

at the VCCIO pin. This does not change the possible output voltage range of the analog outputs OA_x when used as analog outputs

because they are supplied by VCC5

Note that the DRVEN and RESETB input pins can operate with an input level of 5.0 V, even when VCCIO is 3.3 V.

6.1.3

VCC2P5 regulator

An integrated voltage regulator, fed by the VCC5 supply pin, provides 2.5 V to supply the logic core of the device. An external buffer

capacitor (1.0 μF recommended) needs to be connected at the VCC2P5 pin. The regulator, as well as the buffer capacitor, is referenced

to digital ground (DGND pin).

If the VCC2P5 voltage is below the undervoltage threshold (VPORESETB- for a minimum duration of t_PORESETB), the power on reset

signal (VCC2P5) is asserted to the logic core after a delay of t_{D_PORESETB}and resets the logic core and all device internal modules.

Figure 6. PORESETB

PT2000

NXP Semiconductors

34

6.1.4

VCCP regulator

6.1.4.1

Internal V

(vccp_ext_en='0')

CCP

The voltage source at the VBATT input pin provides power for the V_CCPregulator. This integrated linear regulator provides typically 7.0 V

at the VCCP pin, to supply the pre-driver section of the device. The regulator uses low drop out features to extend the system's operating

range when V_BATTtemporarily falls below its normal operating range, for example during engine crank conditions. This avoids problems

caused by insufficient gate voltage, such as slow MOSFET switching and increased on-state losses. A capacitor (4.7 μF recommended)

is required at the VCCP pin to provide the high peak currents required when charging a MOSFET gate.

At low V_CC5, the regulator may be active, but with an increased dropout voltage. The low dropout mode of the regulator is active only when

the voltage at VCC5 is above the V_CC5undervoltage threshold V_UVVCC5+

.

If V_CC5is not present or low, POResetB is active and disables the V_CCPregulator.

V_CCPduring bootstrap initialization:

1. If the DBG pin is not used as a digital I/O, the DBG pin logic level is ‘1’ during reset due to the device internal weak pull-up resistor.

As result, the internal VCCP regulator is switched on during the HS pre-driver bootstrap initialization phase. (refer to See Power-up

sequence VCCP and bootstrap capacitors on page 58).

2. If the DBG pin is used as a digital I/O. This means the DBG pin logic level is undefined during reset and may be '0'. As result, the

internal VCCP regulator's On status during HS pre-driver bootstrap init phase can only be guaranteed if vccp_ext_en is set to '0'.

The bit has to be configured as soon as possible during device init, to start the pre-charging of the bootstrap capacitors soon

enough (refer to Table 148, Driver_config_Part 2 (1A6h)).

Note that this regulator also needs a charge pump voltage coming from the VBOOST pin. Due to this, the V_CCPregulator is not functional

when the voltage on the VBOOST pin is below 4.7 V.

6.1.4.2

External V

(vccp_ext_en='1')

CCP

The VCCP can also be powered by an external voltage source connected to the VCCP pin. The internal V_CCPregulator is sized for 12 V

system operation, including the ISO voltage transients specified for those systems. But for 24 V system operation, the internal V_CCPlinear

regulator dissipates too much power. In this case, the internal V_CCPregulator should be switched off by setting the vccp_ext_en bit of the

driver_config_part2 register (1A6h) to '1' and an external regulator needs to be used.

VCCP during initialization VCCP:

1. If is not possible to turn on the internal V_CCPregulator for a limited time in parallel to the external voltage source, the DBG pin has

to be tied to logic level '0' and the SPI configuration bit has to stay at '1', to strictly avoid the internal regulator to be switched on at

any time. The logic level of the DBG pin should be forced by a pull-down resistor towards GND.

2. On the other hand, if it is possible to switch on the internal regulator for some limited time in parallel with the external voltage supply

without destroying it, no special measures have to be taken during startup. After bootstrap initialization, the vccp_ext_en bit has to

be set to '1' (refer to Table 148, Driver_config_Part 2 (1A6h)).

6.1.4.3

V

undervoltage

CCP

V_CCPvoltage is internally monitored by a voltage comparator to detect if it is in the operating range. In case of an undervoltage when falling

below the lower threshold, the gate driver outputs are switched off by the digital core.

This prevents possible malfunctions and/or failures: in case of an undervoltage, operations are stopped before any malfunction, due to

insufficient gate driver supply voltage. Moreover, in case of a battery voltage disconnection, all MOSFETs are switched off (and therefore

inductive loads are disconnected) before the electrolytic capacitors on the V_BATTline are completely discharged. This prevents any

negative voltage on the V_BATTline, which may cause failures on the VBATT, VCCP, D_HSx and B_HSx pins due to exceeding its

maximum ratings.

PT2000

35

NXP Semiconductors

6.1.5

Battery voltage monitor

The device includes a battery voltage measurement block which measures the voltage at the VBATT pin with a DAC and comparator

running in ADC mode. Figure 7 shows the structure of the analog part of the block. The battery voltage is divided with a voltage divider

by 16. The battery voltage can be measured in the range of 5.0 V to 36 V with a resolution of 6 bits. The digital core permanently performs

the battery voltage measurements. The result is available both via a SPI register and the internal microcore memory map.

VBAT

MC33PT2000

Battery monitoring

VBAT

RBD1

RBD2

CVBAT

Vbat_div

/16

Bat_results

ADC

control

Comp

BAT

DAC

dac_bat_value (5:0)

AGND

Figure 7. Battery voltage monitoring

The battery voltage threshold can be calculated using the following formula. Table 19 shows some example values.

V_BAT= (DAC_VALUE * 39.06 mV) * 16

Table 19. V_BATvoltage DAC values

DAC value

V_BATupper threshold

DAC output voltage/mV

HEX

08

DEC

8

Min./V

....

Typ./V

5.0

Max./V

313

…

...

…

...

…

...

…

16

22

…

859.4

…

...

13.75

…

39

57

2226.6

...

35.63

6.1.6

Boost voltage monitor

The boost voltage monitor implements the voltage regulation of the DC/DC converter without external components. The boost voltage

monitor contains:

• A high accuracy internal voltage divider dividing the voltage at the VBOOST pin to a smaller level V_{BOOST_DIV}

• A programmable DAC (8 bits) either by the SPI (refer to Table 113. Boost_dac (17Fh)) or by microcode creating a reference voltage

• A comparator comparing the reference voltage with the V_{BOOST_DIV}

PT2000

NXP Semiconductors

36

V_BOOST

MC33PT2000

VBOOST

C_VBOOST

Boost monitoring

Vboost_mon_en

Vboost_div

RBD3 = 480 k

/4

Boost_fbk

R^BD2= 140 k

R^BD1= 20 k

/32

Boost

Filter

Comp

uv_vboost

BOOST

DAC

Vboost_disable_en

dac_boost_value (7:0)

AGND

Figure 8. Boost voltage monitor block diagram

When boost voltage is required to drive injectors, the boost voltage monitor use a voltage comparator with a very accurate DAC threshold,

whether the V_BOOSTboost voltage exceeds the desired target value. All high-side pre-drivers are disabled when the voltage at the

VBOOST pin is less than its undervoltage lockout threshold, which is around 4.7 V.

In applications without boost voltage, the battery voltage is connected to the VBOOST pin to supply the internal charge pump. In such

applications, the boost voltage monitor can be used to detect an undervoltage at the VBOOST pin (vboost_mon_en = 0). This means the

VBOOST pin is used to detect battery undervoltage.

6.1.6.1

Application with V

voltage

BOOST

The boost voltage threshold can be calculated using the following formula. Table 20 shows some example values.

• V_BOOST= (DAC_VALUE * 312.5 mV)

Due to the compensation, concept values below 08h should not be used. Values higher than E1h must not be used, because this results

in a boost voltage higher than 72 V which destroys the device. The real maximum value for the boost set point threshold in the application

is even lower due to dynamic effects like voltage drop in the boost capacitor. It is not recommendable to use a DAC value above D0h

(65 V).

Table 20. Boost voltage DAC values

DAC value

V_BOOSTupper threshold

DAC output voltage/mV

HEX

08

…

BIN

8

Min./V

2.45

…

Typ./V

2.50

…

Max./V

2.55

…

78

…

9A

…

154

…

1504

…

47.16

…

48.13

…

49.09

…

B0

…

176

…

1719

…

53.90

…

55.00

…

56.10

…

D0

…

208

…

2031

…

63.70

…

65.00

…

66.30

…

E1

225

2197

68.91

70.31

71.72

PT2000

37

NXP Semiconductors

6.1.6.2

Application without boost voltage

For this purpose, it is possible to change the internal voltage divider ratio from 1/32 to 1/4 by setting the signal boost_mon_en high. To

detect undervoltage and use the signal uv_vboost to disable the pre-drivers, the uv_vboost bit needs to be set to “1” (refer to Table 162,

driver_status (1B2h)). The uv_vboost signal goes high as soon as the voltage at the VBOOST pin is below the threshold, if the V_BOOST

UV monitor is enabled (Vboost_disable_en = 1).

The same digital filter used for the V_BOOSTvoltage measurement is also used for the V_BOOSTUV monitoring mode. The DAC set point

value in this mode has to be chosen to fulfill two requirements:

• The pre-drivers must not be disabled at a battery voltage above 5.0 V

• The device internal charge pump only works properly down to a battery voltage of 4.7 V

The V_BOOSTUV threshold can be calculated using the following formula.

• V_BOOST= (DAC_VALUE * 39.1 mV)

6.1.7

Charge pump

The PT2000 provides one charge pump with independent outputs for each of the seven high-side drivers. The independent outputs allow

complete flexibility of the topology used, meaning all high-sides can drive MOSFETs with the drain connected to V_BOOSTor V_BAT. But

there is a limitation on the diagnostics only HS2, 4, and 6 can use the V_BOOSTfor monitoring (for example, V_BATor V_BOOST).

In most operating topologies and conditions, the bootstrap is the primary source of charge for the bootstrap capacitor, and the charge

pump sustains the voltage at each bootstrap capacitor when it is not being charged by low-side switching.

This charge pump allows 100% duty cycle operation of the high-side MOSFETs while the bootstrap circuitry is not operating (VS_HSx

voltage never goes significantly below the V_CCPvoltage). In this condition, the charge pump provides current maintaining each bootstrap

capacitor charged via independent current sources, to guarantee a minimum V_GSvoltage.

The charge pump, supplied by VBOOST, creates gate drive voltages of about 8.0 V greater than the voltage at VBOOST. However, their

current capacity is sufficient only for low frequency switching. The charge pump is not running as long as the POResetB reset signal is

active.

The internal CP can be used to charge the bootstrap capacitors during init with a guaranteed current of 20 μA per HS pre-driver. This

current is only available if there is no leakage current from B_HSx pin. Any possible leakage current has to be subtracted from this

available charge current (See Using the charge pump to charge bootstrap capacitors on page 59).

6.2

Clock subsystem

The digital logic is supplied by a clock (cksys) generated by the PLL from the 1.0 MHz clock forced externally on CLK pin. Two internal

clocks are derived from the PLL:

• the main logic clock cksys

• the code RAM clock cksys_cram inverted in respect to cksys

• the Data RAM clock cksys_dram inverted in respect to cksys

If an unsuitable signal is applied on the CLK pin, the device automatically switches to the internal backup clock. The PLL output frequency

can be modulated for EMC purposes. Modulation activation is enabled by default, but can be disabled by the SPI. Refer to Table 151

PLL_Config (1A7h).

PT2000

NXP Semiconductors

38

6.3

High-side pre-driver

The PT2000 provides seven independent high-side pre-drivers designed to drive the gate of external high-side configuration N-channel

logic level MOSFETs. These pre-drivers are dedicated to load driving like injectors or solenoids, and integrate diagnostics features.

Internal to the device is a gate to source pull-down resistor holding the external MOSFETs in the off state while the device is in a power

on reset state (RSTB low). The external FET can be connected to either VBATT or a higher voltage VBOOST, limitation in the diagnostics

is described in the next chapter, only HS2, 4, and 6 can use V_BOOSTvoltage for diagnostics.

The high-side pre-drivers are supplied by an external bootstrap capacitor connected between the S_HSX and B_HSX pins. The driver

slew rate can be selected individually for each of the seven drivers, among a set of four value pairs by the SPI registers (refer to Table 99,

Hs_slewrate (171h)).

VBAT VCCP

VBOOST

VCC5

Charge

Pump

V_BOOST/V_BAT

B_HSx

LDO

hsx_slewrate

hsx_command

hsx_drven

G_HSx

S_HSx

uv_vcc5

uv_vccp

uv_vboost

cksys_drven

hsx_in

Load

D_LSx

G_LSx

hs5/7_en_ovr

MC33PT2000

hs1/2/3/4/6

AGND

DRVEN

PGND

Figure 9. High-side pre-driver block diagram

The high-side pre-driver is intended to drive the gate of an external logic level MOSFET in a high-side configuration. The logic command,

hsx_command, to switch the external MOSFET, is provided by the microcores. This command is generated for taking into account the

following signals:

• Logic command coming from channel logic (hsx_in)

• VCCP undervoltage signals (uv_vccp) from VCCP UV monitor: in case of an undervoltage, the external MOSFET is switched off

• VCC5 undervoltage signals (uv_vcc5) from VCC5 UV monitor: in case of an undervoltage, the external MOSFET is switched off

• VBOOST undervoltage signals (uv_vboost) from boost voltage monitor: in case of an undervoltage, the external MOSFET is

switched off if this feature is enabled (refer to Table 162, driver_status (1B2h)

• Signal cksys_drven coming from the clock monitoring: in case of a missing clock (PLL not locked), the external MOSFET is switched

off. This function is disabled by default and can be enabled by setting the cksys_missing_disable_driver bit high (refer to Table 152,

backup_clock_status (1A8h))

• At the high-side pre-driver block signal, DrvEn is added to the control signal for the driver. As long as the DrvEn signal is negated

(low), the high-side pre-driver is switched off. The high-side pre-driver 5 and 7 include a feature to override the switch off path via

the DrvEn signal. As long as the signal hsx_en_ovr is high (only for HS5 and HS7), the pre-driver is not influenced by DrvEn. (refer

to Table 178, HSx_output_config (1DA, 1DDh, 1E0h, 1E3h, 1E6h, 1E9h))

PT2000

39

NXP Semiconductors

The truth table describing the status of hsx_command signal is given in Figure 21.

Table 21. High-side pre-driver truth table

DRV_EN

hs5/7_en_ovr

uv_vccp

uv_vcc5

uv_vboost

cksys_drven

hsx_in

hsx_command Driver status

0

-

1

-

0

off

-

1

-

1

-

0

-

0

on (hs5/7) / off

(other hsx)

0

1

-

0

1

on

The pre-driver G_HSx output is set according to hsx_command:

• When the hsx_command is high, the G_HSx pin is driven high (pull-up to B_HSx voltage);

• When the hsx_command is low, the G_HSx pin is driven low (pull-down to S_HSx voltage).

6.3.1

High-side pre-driver slew rate control

The driver strength can be selected individually for each of the drivers among a set of values by the SPI registers. There are four selectable

driver strengths. The strength for the rising and falling edge can be chosen individually for each driver. Changing the rising edge affects

the falling edge such as to retain the same absolute slew rate. The given value of voltage slew rate is only an indication and is dependent

on the used MOSFET and the additional gate circuit (refer to Slew rate high-side and low-side selection register).

Table 22. Slew rate settings for HS pre-drivers

R_{DS(ON)_PMOS}

(switching on)/Ω

R_{DS(ON)_NMOS}

(switching off)/Ω

hsx_slewrate(1:0)

Slew-rate/ V/µS

00

01

10

11

300

50

14.6

85

5.9

35

25

169

337

69

12.5

138

6.3.2

Safe state of high-side pre-driver

When reset (RSTB) is asserted or DRV_EN is negated, the G_HSx output is immediately forced to a low level, thus switching off the

external MOSFET, to guarantee a safe condition while the device is not operating. In addition to this, an integrated pull-down resistor

R_{PD_HSX}between G_HSx and S_HSx of about 1.0 MΩ keeps the external MOSFET in the off state even when the bootstrap voltage is low.

PT2000

NXP Semiconductors

40

6.3.3

High-side pre-drivers in low-side configuration

All high-side pre-drivers can be used as low-side pre-drivers. In this configuration, an external bootstrap capacitor is still required because

B_HSx can't be connected to VCCP directly. The drain contact of this high-side pre-driver is still connected to V_BOOSTor V_BATTinternally,

so the V_DSmonitoring for this low-side MOSFET is not functional.

VBAT VCCP

VBOOST

VCC5

Charge

Pump

B_HSx

LDO

Load

hsx_slewrate (1:0)

hsx_command

hsx_drven

G_HSx

S_HSx

uv_vcc5

uv_vccp

uv_vboost

cksys_drven

hsx_in

Rpd_hsx

HS Pre Driver

Rsense

PGND

hs5/7_en_ovr

MC33PT2000

AGND

DRVEN

Figure 10. High-side pre-driver in low-side configuration

PT2000

41

NXP Semiconductors

6.4

High-side VDS and VSRC monitor

The PT2000 monitors VDS and VSRC for diagnostic purposes across each high-side to detect any fault occurring on the external

MOSFET. The drain and source voltages of the connected MOSFETs are needed for V_DSmonitoring. To save pins, the high-side V_DS

monitors have no dedicated drain pins, and the drain voltage of the MOSFETs is available via pins VBATT, for the MOSFETs connected

to battery voltage (HS1, HS3, HS5, HS7) and V_{BOOST or}V_BATTfor the MOSFETs connected to boost or battery voltage (HS2, HS4, and

HS6).

6.4.1

HS1, 3, 5, 7 V_DSmonitoring

VBATT

VCC5

Voltage

hsx_vds_threshold (3:0)

Threshold

+

VBOOST / VBAT

hsx_vds_Vbatt_fbk

–

B_HSx

G_HSx

S_HSx

+

hsx_src_fbk

–

Voltage

Load

hsx_src_threshold (3:0)

Threshold

VCCP

HS1/3/5/7

D_LSx

+

lsx_vds_fbk

G_LSx

–

Voltage

lsx_vds_threshold (3:0)

Threshold

LS1-6

PGND

Figure 11. High-side 1, 3, 5, and 7 V VSRC and LS1-6 V monitoring

DS

Four high-side V_DSmonitors for high-side pre-drivers 1, 3, 5, and 7 are composed of two comparators with programmable thresholds, the

first one sensing the voltage between V_BATTand the source pin S_HSx and the second one sensing the voltage between the source pin

S_HSx and PGND (voltage across the free-wheeling element, either a diode or a MOSFET). A simplified schematic of the high-side V_DS

monitors of HS pre-driver 1, 3, 5, and 7 is shown in Figure 11.

V_DSand V_SRCthreshold are selectable by the SPI using registers vds_threshold_hs and vsrc_thresholds_hs (refer to VDS and VSRC

threshold selection). Selectable values are shown in Table 23.

PT2000

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42

6.4.2

HS2, 4, 6 V_DSmonitoring

VBATT

VBOOST

VCC5

hsx_vds_threshold (3:0)

hsx_vds_vboost_fbk

Voltage

Threshold

+

VBOOST / VBAT

–

B_HSx

+

hsx_vds_vbatt_fbk

–

G_HSx

S_HSx

Load

+

–

VCCP

hsx_src_fbk

Voltage

Threshold

D_LSx

hsx_src_threshold (3:0)

HS2/4/6

G_LSx

PGND

Figure 12. V monitors and load biasing HS2, 4, and 6

DS

The three high-side VDS monitors of pre-drivers 2, 4, and 6 are composed of three comparators with programmable thresholds, the first

one sensing the voltage between V_BOOSTand the source pin S_HSx (V_DSof the high-side MOSFET used as the boost MOSFET) and the

second one sensing the voltage between V_BATTand the source pin S_HSx (V_DSof the high-side MOSFET used for battery MOSFET and

voltage information for voltage based diagnostics when the MOSFET is in boost configuration) and the third one sensing the voltage

between the source pin S_HSx and PGND (voltage across the free-wheeling element, either a diode or a MOSFET). A simplified

schematic of the high-side V_DSmonitors of HS pre-driver 2, 4, and 6 is shown in Figure 12.

The selection between “VBATT” or VBOOST is done with the microcode command slfbk (reference Programming Guide and Instruction

Set). V_DSand V_SRCthreshold are selectable by the SPI using registers vds_threshold_hs and vsrc_thresholds_hs (refer to VDS and VSRC

threshold selection). Selectable values are shown in Table 23.

Table 23. V monitor threshold selection

DS

hsx_vds/src_threshold(3:0)

Threshold voltage HS VDS / HS VSRC

0000

1001

1010

1011

1100

0001

0010

0011

0.00

0.10

0.20

0.30

0.40

0.50

1.0

1.5

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NXP Semiconductors

Table 23. V monitor threshold selection (continued)

DS

hsx_vds/src_threshold(3:0)

Threshold voltage HS VDS / HS VSRC

0100

0101

0110

0111

2.0

2.5

3.0

3.5

The high-side V_DScomparator compares V_DSof the high-side MOSFET, acquired through VBOOST, VBATT, and the S_HSx pins, with

the selected threshold. In actual implementation, the selected threshold voltage is subtracted to the V_BOOSTor V_BATTvoltage and

compared to the S_HSx voltage.

The high-side V_SRCcomparator compares the voltage across the freewheeling element, acquired through the S_HSx pins and PGND,

with the selected threshold. In actual implementation, the selected threshold voltage is added to PGND voltage and compared to the

S_HSx voltage.

6.5

Low-side pre-driver (LS1-6)

There are six general purpose low-side pre-drivers and all drive external N-Channel logic level type power MOSFETs used in low-side

configurations.

VBAT VCCP

MC33PT2000

Load

D_LSx

LDO

LS Pre-driver

lsx_slewrate (1:0)

uv_vcc5

lsx_command

uv_vccp

lsx_drven

G_LSx

cksys_drven

lsx_in

Rpd_lsx

R_SENSE

ls6_en_ovr

PGND

other lsx

DRVEN

PGND

Figure 13. Low-side pre-driver block diagram

Internal to the device, a gate to source pull-down resistor RPD_LSX holds the external MOSFETs in the off state, while the device is in a

power on reset state (RSTB low).

The low-side pre-drivers are supplied by V_CCPvoltage. The low-side pre-driver is intended to drive the gate of an external logic level

MOSFET in low-side configuration. The logic command lsx_command, to switch the external MOSFET, is provided by the digital block.

This command is generated, taking into account the following signals:

• Logic command coming from channel logic (lsx_in).

• V_CCPundervoltage signals (uv_vccp) from the VCCP UV monitor: In case of an undervoltage, the external MOSFET is switched off.

• V_CC5undervoltage signals (uv_vcc5) from VCC5 UV monitor: In case of an undervoltage the external MOSFET is switched off.

PT2000

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44

• Signal cksys_drven coming from the clock monitoring: In case of a missing clock (PLL not locked), the external MOSFET is switched

off. This function is disabled by default and can be enabled by setting the cksys_missing_disable_driver bit high (refer to Table 152,

backup_clock_status (1A8h)).

• For safety purpose DRV_EN is added to the control signal for the driver. As long as DRV_EN signal is negated (low) the low-side

pre-driver is switched off. The low-side pre-driver 6 includes a feature to override the switch off path via the DRV_EN signal (refer to

Table 174, LSx_output_config (1C2h, 1C5h,1C8h, 1CBh, 1CEh, 1D1h)).

The truth table describing the status of lsx_command signal is given in Table 24.

Table 24. Low-side pre-driver truth table

DRV_EN

ls6_en_ovr

uv_vccp

uv_vcc5

cksys_drven

lsx_in

lsx_command

Driver Status

0

-

1

-

0

1

off

on

-

1

-

0

-

0

1

-

1

-

0

1

The pre-driver G_LSx output is set according to lsx_command:

• When lsx_cmd is high, the G_LSx pin is driven high (pull-up to V_CCPvoltage)

• When lsx_cmd is low, the G_LSx pin is driven low (pull-down to PGND voltage)

6.5.1

Low-side pre-driver slew rate control

All low-side pre-drivers feature a programmable slew-rate control. The settings can be changed independently for each pre-driver by the

signals lsx_slewrate(1:0) coming from the digital core. The given value of voltage slew-rate is only an indication and is dependant on the

used MOSFET and the additional gate circuit.(refer to Slew rate high-side and low-side selection register).

Table 25. Slew rate settings for LS pre-drivers 1-6

R_{DS(ON)_PMOS}(switching R_{DS(ON)_NMOS}(switching

lsx_slewrate(1:0)

Slew-rate/ V/µS

on)/Ω

14.6

84

off)/Ω

00

01

10

11

300

50

5.9

35

25

170

337

69

12.5

138

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NXP Semiconductors

6.5.2

LS1 - LS6 V_DSmonitor

VCCP

Load

D_LSx

+

–

lsx_vds_fbk

G_LSx

Voltage

lsx_vds_threshold (3:0)

Threshold

LS1-6

PGND

Figure 14. V monitoring LS1 to LS6

DS

For V_DSmonitoring of the external low-side MOSFET, a comparator with programmable threshold is provided, sensing the voltage

between the drain pin D_LSx and PGND (V_DSof the low-side MOSFET). If a sense resistor is connected between the low-side MOSFET

and ground, the voltage drop on the resistor is included in the measurement. V_DSthreshold are selectable by the SPI using

vds_threshold_ls registers (refer to Table 96, Vds_threshold_ls_Part 1 (16Fh)) and Table 97, Vds_threshold_ls_Part 2 (170h)). Selectable

values are shown in Table 26.

Table 26. Low-side V monitor threshold selection

DS

lsx_vds _threshold(3:0)

Threshold Voltage LS V_DS

0000

1001

1010

1011

1100

0001

0010

0011

0100

0101

0110

0111

0.00

0.10

0.20

0.30

0.40

0.50

1.0

1.5

2.0

2.5

3.0

3.5

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46

6.6

Low-side pre-driver for DC/DC converter (LS7 and LS8)

There are two low-side pre-drivers (LS7-8) targeted for DC/DC converter applications. All are to drive external N-channel logic level type

power MOSFETs used in low-side configurations. If no DC/DC is required, they can be used as general purpose low-side.

VBAT VCCP

MC33PT2000

Load

D_LSx

LDO

LS DCDC

Pre Driver

ls7/8_slewrate_p (1:0)

uv_vcc5

uv_vccp

cksys_drven

ls7/8_in

ls7/8_slewrate_n (1:0)

ls7/8_command

ls7/8_drven

G_LSx

Rpd_ls7/8

Rsense

Ls7/8_en_ovr

PGND

DRVEN

PGND

Figure 15. Low-side pre-driver for DC/DC converter (LS7 and LS8)

Internal to the device, a gate to source pull-down resistor R_{PD_LSX}holds the external MOSFETs in the off state, while the device is in a

power on reset state (RSTB low). The low-side pre-drivers are supplied by V_CCPvoltage.

The low-side pre-driver is intended to drive the gate of an external logic level MOSFET in low-side configuration. The logic command

lsx_command, to switch the external MOSFET, is provided by the digital block. This command is generated, taking into account the

following signals:

• Logic command coming from channel logic (ls7/8_in).

• V_CCPundervoltage signals (uv_vccp) from VCCP UV monitor: in case of undervoltage, the external MOSFET is switched off.

• V_CC5undervoltage signals (uv_vcc5) from VCC5 UV monitor: in case of undervoltage, the external MOSFET is switched off.

• Signal cksys_drven coming from the clock monitoring: in case of a missing clock (PLL not locked), the external MOSFET is switched

off. This function is disabled by default and can be enabled by setting the cksys_missing_disable_driver bit high (refer to Table 152,

backup_clock_status (1A8h)).

• For safety purpose DRV_EN is added to the control signal for the driver. As long as DRV_EN signal is negated (low) the low-side

pre-driver is switched off. The low-side pre-driver for the DC/DC converter includes a feature to override the switch off path via signal

DrvEn. As long as the signals ls7/8_en_ovr are high, the pre-driver is not influenced by DrvEn (refer to Table 175, LS7_output_config

(1D4h) & LS8_output_config (1D7h)).

The pre-driver is capable of PWM operation up to 400 kHz according to the following table.

Table 27. Low-side pre-driver LS7/8 PWM frequency and load

PWM Frequency / kHz

Gate Charge / nC

400

300

240

60

75

100

A maximum duty cycle of 100% is allowed during PWM operations.

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47

NXP Semiconductors

6.6.1

Low-side pre-driver slew rate control (LS7 and LS8)

The driver strength can be selected among a set of four values by the SPI registers. The strength for the rising and falling edge can be

chosen independently by means of the bits slew rate_ls7/8_rising(1:0) and slew rate_ls7/8_falling(1:0) (refer to Table 101,

Ls_slewrate_Part 2 (173h))

The slew rate is determined by the PMOS and NMOS R_DS(on)of the push/pull driver circuitry. The typical gate slew rate values are defined

in Table 28 and Table 29. These values are given as reference and are impacted by the external circuitry.

Table 28. Slew rate settings for LS pre-drivers 7/8 PMOS

RDSON_PMOS

LS7/8_slewrate_p(1:0)

Slew-rate/ V/µS

(switching on)/Ω

00

01

10

11

1500

300

50

5.0

14.6

85

25

170

Table 29. Slew rate settings for LS pre-drivers 7/8 NMOS

RDSON_PMOS

(switching on)/Ω

LS7/8_slewrate_n(1:0)

Slew-rate/ V/µS

00

01

10

11

1500

300

50

1.1

5.9

35

25

69

6.6.2

Low-side V_DSmonitor D_ls7/D_ls8 for DC/DC

lsx_vds_fast_fbk

lsx_vds_highspeed_en

VCCP

Load

D_LS7/8

G_LS7/8

lsx_vds_fbk

C^RES

Voltage

Threshold

(only resonant

lsx_vds_threshold (3:0)

mode)

Figure 16. Low-side 7 and 8 V monitor

DS

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NXP Semiconductors

48

Two comparators are implemented for the V_DSmonitoring function of D_LS7/8. One is used for normal V_DSmonitoring (See LS1 - LS6

VDS monitor on page 46), and the other is a high-speed comparator used for the DC/DC resonant converter application.

Normal V monitoring:

DS

• Input impedance of D_LSx has to be switched to low speed by setting l_{SX_VDS_HIGHSPEED_EN}to “0” via the SPI register bit (refer to

Table 116, Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h))

• l_{SX_VDS_FBK}is used for diagnostics

• Clamp voltage = 3.5 V

Fast VDS monitoring (DC/DC resonant converter):

• Input impedance of D_LSx has to be switched to high speed by setting l_{SX_VDS_HIGHSPEED_EN}to “1” via SPI register bit (refer to

Table 116, Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h))

• lsx_vds_dcdc is used for resonant detection

• VDS Threshold needs to be set to 2.5 V

For more details on the DC/DC mode See DC/DC converter control (LS7/8) on page 61.

6.7

Current measurement

There are six total input pairs to measure currents with external shunt resistors in a four-wire configuration.

• Four general purpose blocks (#1, 2, 3, and 4).

• Two extended mode block for DC-DC converters (#5 and 6).

The shunt resistors are used in low-side configuration with one of the shunt terminals tied to ground for all the blocks. This means the

PT2000 measures a differential voltage over the two input pins.

6.7.1

General purpose current measurement block

The actuator current flowing in an external sense resistor is measured to implement a closed loop current control. The current

measurement block is comprised of a differential amplifier, sensing the voltage across the sense resistor, a voltage comparator, and an

8-bit current DAC.

MC33PT2000

Load

G_LSz

VSENSEPx

+

Diff Ampx

VSENSENx

+

–

curx_fbk

Filter x

Comp x

DACx

OA_y

dacx_value (7:0)

Current Measurement (1, 2, 3, 4)

AGND

Figure 17. General purpose current measurement block diagram

The differential amplifier gain is selectable among four different values by means of the opamapx_gain (1:0) signal, to get the suitable

signal amplification. The gain can be changed at runtime by the microcore using the stgn instruction (reference Programming Guide and

Instruction Set). The differential amplifier also adds a constant offset to its output. Therefore, the output of the amplifier is always positive.

The desired actuator current level can be selected and changed at runtime by the microcore, setting the proper dacx_Value (7:0) threshold

value in the DAC. Each current measurement channel can be used in ADC mode. A track and hold circuit is implemented to keep the

voltage at the comparator input stable during the ADC conversion.

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49

NXP Semiconductors

The differential amplifier output can be routed to an external pin (OA_1, OA_2, and OA_3). In this configuration, the device output is

usually connected to an ADC input of the MCU for safety and test purposes. The output multiplexer block contains an output amplifier with

selectable gain by means of the oa_gainy(1:0) signal, providing full swing output on OA_y for A/D conversion, if used with 3.3 V or 5.0 V

applications. The target for overall accuracy is about 3.7% at 75% DAC range (see Table 12). This includes the external resistor which is

assumed to have a worst case error of 2.0%.

6.7.1.1

Current sense amplifier

The current sense amplifier provides a voltage which can be monitored through the OA_x pins. A 250 mV offset is added to monitor

negative current, this way output of the amplifier is always positive. The amplifier is fully operational down to an output voltage of typically

100 mV. The current sense amplifier output voltage can be calculated using the following formula:

V_DASENSE= (V_VSENSEPx– V_VSENSENx) × G_DADIFF+ V_DABIAS

V_DABIASis fixed value of 250 mV applied to the differential amplifier output.

The G_DADIFFgain value is configurable at runtime (opampx_gain(1:0)), this gain can be selected using the instruction stgn. The allowed

differential mode input voltages depend on the chosen gain value.

6.7.1.2

Current sense DAC

In order to select the proper threshold for current control, an 8-bit current DAC is implemented to provide a threshold to the voltage

comparator (dac_value (7:0)). The current threshold can be calculated using the following formula.

((DACVALUE × V

)–V

)

DABIAS

DACLSB

--------------------------------------------------------------------------------------------------------------------

I =

G

⋅ R

DADIFF SENSE

DAC_VALUE is selected and changed at runtime by the digital microcore by means of the signal dacx_value (7:0). A DAC_VALUE below

the hexadecimal value 0Ah, must be avoided, as the current sense differential amplifier does not operate with full performance at output

voltages below 100 mV.

V_{DAC_LSB}is the DAC resolution = 9.77 mV.

V_{DA_BIAS}is the fixed voltage biasing applied to the differential amplifier output = 250 mV. G_{DA_DIFF}is the gain value configurable at

runtime by the SPI (opampx_gain(1:0)). This gain can be selected using the instruction stgn.

R_SENSEXis the external sense resistor of the current measurement channel x.

Table 30. Current sense DAC values with a 10 mΩ shunt

DAC value

Current threshold with 10 mΩ shunt/A

DAC output voltage / mV

HEX

BIN

10

Gain = 5.79

-2.63

…

Gain = 8.68

-1.76

…

Gain = 12.53

-1.22

…

Gain = 19.25

-0.79

…

0A

…

98

…

19

1A

1B

…

25

244

254

264

…

-0.10

0.07

-0.07

0.05

-0.05

0.03

-0.03

0.02

26

27

0.24

0.16

0.11

0.07

…

FF

255

2490

38.69

25.81

17.88

11.64

PT2000

NXP Semiconductors

50

6.7.1.3

Current measurement offset compensation

An analog offset compensation is done which compensates the input offset of the current measurement amplifiers one to six. The offset

compensation is started and stopped from the digital microcores using the instruction stoc. The offset compensation must be started while

there is no current flow in the shunt of the related measurement channel.

The compensation uses a small 6-bit DAC (5-bit plus sign) which injects a current at the input stage of the differential amplifier to

compensate the input offset. The offset compensation is finished after a maximum time of 31 x 2.0 μs = 62 μs. This process is completely

automatic and only the start and stop has to be handled by the microcore.

The offset compensation uses the “ck_ofscmp” generated from the ck_sys. The prescaler can be set using this register (refer to Table 146,

Ck_ofscmp_Prescaler(1A4h)). Because the offset compensation minimum step time can be up to 2.0 μs (refer to Table 13), it is mandatory

to set the ck_ofscmp to a maximum of 500 kHz.

Each new offset compensation is started based on the result of the previous offset compensation run for this current measurement

channel. If the offset compensation is stopped from the digital microcore when the analog offset compensation is not finished, the

procedure is aborted, maintaining the last compensation value reached when the procedure was interrupted. This strategy guarantees

each offset compensation decreases the offset of the current measurement amplifier independent of it being finished.

Due to a temperature drift of the differential amplifier input offset, the offset compensation must be performed each time a huge change

in device temperature is expected. If this is not possible, an increased residual offset due to the temperature drift has to be taken into

account.

MC33PT2000

Load

250 mV

Bias Voltage

G_LSz

VSENSEPx

Offset Comp

DACx

(5+1bits)

Diff Amp

VSENSENx

curx_fbk

Filter x

Comp x

DACx

OAy

dacx_value (7:0)

Current Measurement

Offset Compensation

(x:1,2,3,4,5,6)

PGND

Figure 18. Offset compensation block diagram

PT2000

51

NXP Semiconductors

6.7.2

Current measurement for DC/DC

The inputs of the 5th and 6th current sense need to support a very wide range of applications.

Typical applications use the 5th and 6th current sense e.g.

• Just identical to the other current sense blocks or

• To control a DC/DC converter with a low-side current measurement and concurrently provide an overcurrent supervision at the booster

capacitor

The two-point current control of a DC/DC converter results in challenging requirements on latency of the control loop. This means:

• The path from sense input to low-side driver output must achieve a very small delay

• There is no time to change the DAC setting after each switching event.

VBAT

MC33PT2000

VBOOST

G_LS7/8

VSENSEP5/6

+

Diff Ampx

+

VSENSEN5/6

Filter

xL

curxl_fbk

Comp xL

–

DACxL

DACxH

dacxl_value (7:0)

+

Filter

xH

curxh_fbk

curxneg_fbk

Comp xH

–

dacxh_value (7:0)

+

Diff Ampx

+

–

Filter

xNeg

Comp xNeg

–

DACxNeg

dacxneg_value (3:0)

OA_3

DCDC Current Measurement (x=5, 6)

Figure 19. DC/DC current measurement (5 & 6) block diagram

Along with the number of concurrent thresholds to supervise, the key feature of the current measurement block for DC/DC is the ability to

provide a short delay from the VSENSE inputs to the G_LS7/8 output. For this application, the digital core contains a hardwired logic for

a two-point current regulation using the cur5/6h_fbk and cur5/6l_fbk signals as inputs to directly control the LS7 or LS8 low-side driver.

Using the negative comparator it is possible to detect boost overcurrent. During this time the low-side is Off and the current flows from the

boost tank capacitor to the load. (See Negative current differential amplifier on page 53)

PT2000

NXP Semiconductors

52

6.7.2.1

Negative current differential amplifier

The key characteristic of the second differential amplifier is it works at negative differential input voltages and therefore has a negative

gain. This is used to detect overcurrent when the low-side is Off.

Table 31. Boost overcurrent sense amplifier overall gain

Gain value

Normal differential mode input voltage Full scale range current with 10 mΩ shunt

DAC resolution with 10 mΩ shunt

-2.0

-1047 mV …0

-104.7 A

-7.81 A

The current threshold can be calculated using the following formula.

((DACVALUE × V

) – 250mV)

DACLSB

⋅ R

------------------------------------------------------------------------------------------------------------

I =

G

DADIFF

SENSE

DAC_VALUE is selected and changed at runtime by the digital microcore by means of the signal dacx_value (3:0).

V_{DAC LSB}is the DAC resolution = 156.25 mV.

V_{DA_BIAS}is the fixed voltage biasing applied to the differential amplifier output = 250 mV.

The Gain Value G_{DA_DIFF}is fixed to -2.0.

R_SENSEXis the external sense resistor of the current measurement channel x.

6.7.2.2

Current measurement offset compensation

The analog offset compensation for the differential amplifier 5 and 6 of channel 5 and 6 is done in the same way for channel 1 to 4. The

DAC5/6L and the signal Cur5/6l_fbk are used for the offset compensation. Since the accuracy is not actually critical to detect the

overcurrent, the differential amplifier 5 and 6 negative do not have offset compensation (see Figure 19).

6.8

OA_x output pins, multiplexer and T & H

General features

6.8.1

The output signals of the six current sensing amplifiers are available via three external pins OA_1, OA_2, and OA_3 of the device (refer

to Figure 20). With the OAGainx (1:0) and OAxG1 signal, it is possible to select between five different output gains. This feature is used

to adapt the device to an ADC input range of 3.3 V or 5.0 V, and also to add the possibility of amplifying the output signal even higher for

some special measurement functions. The maximum output voltage at the OA_x pins of VCC5 always has to be taken into account.

For the two higher gains of 3.0 and 5.33, the bias voltage of nominal 250 mV of the input signal is removed before amplifying the signal

and adding again to the amplified signal afterwards.

Table 32. OA_x amplifier gain selection and output voltage

Oagainx(1:0)

OAxG1

Gain value

1.0

Output voltage

V_IN* Gain

d.c.

00

01

10

11

1

0

1.33

V_IN* Gain

2.0

V_IN* Gain

3.0

(V_IN– 250 mV) * Gain +250 mV

5.33

The OA1/2/3 output pins includes the possibility of switching to hi-impedance mode to enable the direct connection of two of these output

pins to one micro-controller ADC input. All OA_x output multiplexers can also be switched to VCC2P5 as a third option. This is used to

check the connection between the PT2000 and the microcontroller ADC on the ECU level.

PT2000

53

NXP Semiconductors

Feedback to

DAC + comp

(adc mode)

OA_Sel1(2:0)

OA_Cur1

OA_Enable

OA_Cur3

Lowpass

Filter

OA_1

VCC2P5

OaGain1(1:0)

Opamp_flag_in2

Feedback to

DAC + comp

(adc mode)

OA_Sel2(2:0)

OA_Cur2

OA_Enable

Opamp_flag_out2

OA_Cur4

OA_2/Flag(14)

Lowpass

Filter

OaGain2(1:0)

VCC2P5

Opamp_pin_

source2

OA_Sel3(2:0)

Feedback to

DAC + comp

(adc mode)

OA_Enable

OA_Cur5L

OA_Cur6L

Lowpass

Filter

OA_3

VCC2P5

OaGain2(1:0)

Figure 20. OA_x multiplexer

Table 33, Table 34, and Table 35 show the output configuration of the OA_x multiplexers, control is done by register oa_out_config (See

Analog output (OAx) configuration register on page 116).

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NXP Semiconductors

54

Table 33. OA_1 multiplexer logic table

OaSel1(2:0)

OaEN1

Signal at Output OA_1

000

1

OA_Cur 1 (Feedback of current measurement 1)

001

1

OA_Cur 3 (Feedback of current measurement 3)

010-100

101

1

0

Reserved

VCC2P5

Reserved

HiZ

110-111

xxx

Table 34. OA_2 multiplexer truth table

OaSel2(2:0)

000

OaEN2

Signal at Output OA_2

1

0

OA_Cur 2 (Feedback of current measurement 2)

001

OA_Cur 4 (Feedback of current measurement 4)

010-100

101

Reserved

VCC2P5

Reserved

HiZ

110-111

xxx

Table 35. OA_3 multiplexer truth table

OaSel3(2:0)

000

OaEN3

Signal at Output OA_3

1

0

OA_Cur 5 (Feedback of current measurement 5)

001

OA_Cur 6 (Feedback of current measurement 6)

010-100

101

Reserved

VCC2P5

Reserved

HiZ

110-111

xxx

The multiplexer must not be switched to a signal currently processing via another OAx analog output or an internal path. Switching the

multiplexer can cause a glitch on the signal being processed.

6.8.2

OA_2 Pin digital I/O function

General requirements

6.8.2.1

The OA_2 pin can also be used as a digital flag bus input or output flag (14). It can be selected by the SPI configuration of the PT2000

using the registers flags_source and flags_direction (refer to Table 138, Flag_direction (1A1h)). The flag pin (14) has a higher rise/fall time

of about 3.0 μs, compared to the other external flag bus pins of the device. For the digital output functionality, the same output stage is

used as with the analog function. As soon as the pin is configured as a digital input, the buffer is switched to hi-impedance. Table 36 shows

how the enable signal is created.

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Table 36. OA2 enable truth table

opamp_pin_source OaEN2

OA2 Buffer

state

flags_source flags_direction

Description

(2) (reset=0)

(reset=0)

0

1

d.c.

1

0

1

0

1

-

HiZ

On

HiZ

On

OA2 pin is used as analog output, enable signal is low

OA2 pin is used as analog output, enable signal is high

OA2 pin is used as digital input

0

-

OA2 pin is used as digital output

6.8.2.2

OA_2 pin I/O voltage

The I/O voltage of the OA_2 pins is not automatically set according to the V_CCIOvoltage supplied to the device. The OA_2 output amplifier

which is also used for the digital output function is supplied by V_CC5. The digital input signal to the OA_2 output amplifier is a V_CC2P5based

signal. The I/O voltage has to be selected by choosing the right gain of the OA_2 output amplifier. Table 37 shows how to select the proper

I/O voltage.

Table 37. OA_2 amplifier gain selection (I/O voltage)

OaGain2(1:0)

Gain value

1.33

Used for

3.3 V I/O

5.0 V I/O

00 (reset value)

01

10

11

2.0

3.0

5.33

There is a weak pull-down resistor at the OA_2 input/output. This resister is always present, regardless if the digital or analog functionality

is selected.

6.8.3

OAx output offset and offset error

It is important to have a close look at the output offset of the OAx pins and the output voltage values corresponding to load current values.

The current measurement amplifiers output signal has a fixed offset of 250 mV and also some variable offset of -28.6 mV to +36.4 mV for

this path after analog offset compensation. This offset is independent of the current measurement amplifiers gain setting, but is amplified

by the OAx amplifier gain. The OAx amplifier also adds some input offset of ±10…13.5 mV to this calculation. So in sum there is a fixed

offset of 250 mV and a variable offset at the input of the OAx amplifier.

For the two higher gains of 3.0 and 5.33, the bias voltage of nominal 250 mV of the input signal is removed before amplifying the signal

and added again to the amplified signal afterwards. Table 38 gives some examples for load currents, gain settings, and corresponding

output voltage ranges. Note that this calculation only takes into account the offset errors. There are also other errors which have to be

considered in a full error calculation.

Table 38. OAx input and output values

Load current at 10 mΩ

Current measurement

amplifier gain setting

OAx amplifier gain OAx output voltage OAx output voltage OAx output voltage

shunt/A

setting

Min./mV

Typ./mV

Max./mV

0

25.8

0

8.68

1.33

276

333

399

1.33

3256

45

3312

250

3378

497

19.25

5.33

1

5.33

1071

2610

1276

2815

1523

3062

2.5

5.33

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7

Functional device operation

7.1

Power-up/down sequence

During power-up, the voltage at the VBATT pin can be clearly higher than the voltage at the VBOOST pin. The functionality of the PT2000

within its functional limits and outside its functional limits (no destruction of connected devices) has to be guaranteed independently from

the slope of the voltage ramp up of the supply voltages (V_CC5, V_CCIO, V_BATT) and the starting value.

7.1.1

Power-up sequence of VCC5, VCC2P5, and reset

After the internal POResetB signal is deactivated, it takes a maximum time of t_DIGIOREADY= 100 μs until the digital outputs of the device

are functional. CLK can be sent even before this t_DIGIOREADY, but it is not taken into account. Inside the logic core, POResetB is combined

with the external reset signal ResetB (active low) and the SPIResetB signal coming from the SPI interface. As long as RSTB is asserted,

the SPI module is inactive. After the first RESETB rising edge, it is required to wait t_{_SPIREADY_t0}= 100 μs to allow time for the fuses to

load.

Note that the logic core is properly supplied at 2.5 V when 5.0 V is present at the VCC5 pin (thus allowing logic core operations and SPI

communication with the microcontroller), even if no voltage is provided at the VBATT pin and by consequence no voltage is present on

the VCCP pin.

VBATT

Vboost level

Vbat level

VBOOST

VCCIO (5V or 3.3V)

Vcc5_uv

VCC5 (5V)

V2p5_uv

VCC2P5

VCCP

tD_POResetB

POReset

tDIGIOREADY

CLK (from MCU)

tPLL_lock

RESETB

tSPI_ResetB_t0

SPI download

ChannelX Flash enable

(100h, 120h, 140h)

External power supplies

Internal regulators

External Digital Signals

Internal Digital Signals

Figure 21. Power-up diagram

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7.1.2

Power-up sequence VCCP and bootstrap capacitors

Bootstrap switch control

7.1.2.1

During initialization phase, the control of the boostrap switch needs to be carefully controlled. The following device configurations are

affected.

• Hsx_bs_lowcurrent: the low-current limit (280 μA), which is set only during init independently for each HS pre-driver;

• Vsrc_threshold: the V_SRCthresholds of each HSx, which during init is set first to 0.5 V and after some time to 1.0 V. After init phase is

finished the V_SRCthreshold returns to the value defined in the appropriate register (refer to Table 94, Vsrc_threshold_hs_Part2 (16Eh)).

• Ls_bias: all ls_bias are set active for all LSx outputs during init phase of any HS pre-driver, and then go back to the configuration defined

in the appropriate register (refer to register Table 126, Ls_bias_config (18Ch)) when all HS pre-drivers are out of the init phase.

• Hs_bias: the hs_bias is set inactive for the HSx outputs during init and then returns to the configuration defined in the appropriate

register (refer to Table 125, Hs_bias_config (18Bh)).

During the init phase of the bootstrap capacitors, the vccp_external_enable signal is affected according to what is defined in Table 150,

VCCP external enable setting. In particular, as long as at least one HS pre-driver is in bootstrap init mode, the vccp_external_enable

setting is set to '0' (internal regulator active), if the value of the DBG pin sampled at reset (POResetB and ResetB) was '1'.

The charging of the bootstrap capacitors starts after reset is deactivated and as soon as the V_CCPvoltage is ramped up. As soon as the

V_CCPvoltage is above the V_CCPundervoltage threshold, a global timer for all hs pre-drivers running on cksys with an end of count value

of 36 ms is started. As soon as the timer reaches the end of count value, the Vsrc_threshold is changed from 0.5 V to 1.0 V for all drivers

still in init mode. At the same moment, the hsx_src_1V bit is set to '1' for all these drivers.

The bootstrap init for each HS pre-driver ends if one of the following conditions is met:

• The bs ready comparator shows the B_HSx voltage is close to the V_CCPvoltage and at the same time the S_HSx voltage is below

0.5 V or 1.0 V,

• The clamp is activated and at the same time the S_HSx voltage is below 0.5 V or 1.0 V;

• An LS pre-driver connected to the same HS pre-driver is switched on and the corresponding hsx_lsx_act signal is set to '1';

• The connection between LS pre-drivers and HS pre-driver is disabled (hsx_ls_act_dis signal = '1'); or

• The same HS pre-driver is switched on.

In applications where two HS pre-drivers are connected to the same node by their S_HSx pin directly or via a diode, care must be taken.

It is not allowed in these configurations to turn on the hs_bias via the SPI register or the microcode command before all HS pre-drivers

finished their bootstrap init. Otherwise an active hs_bias from one pre-driver may block the init of the other. The init mode of each HS pre-

driver can be quit by setting the corresponding “hsx_ls_act_dis” bit to '1' (refer to Table 127, Bootstrap_charged (18Dh)). This should be

done for each HS pre-driver not used in an application.

7.1.2.2

Using D_LSx pull-down sources to charge bootstrap capacitors

After reset release and after the V_CCPvoltage is above the UV_VCCP threshold, the charging of the HS pre-driver's bootstrap capacitors

via the D_LSx pull-down sources starts automatically, as long as there is a current path from S_HSx of the HS pre-driver to at least one

D_LSx pin or to GND. To make this possible, there is a requirement to switch the current limitation of the bootstrap path from about 95 mA

to min. 280 μA.

Table 39 shows how long it takes to charge a bootstrap capacitor to 7.0 V using the D_LSx current sources and a bootstrap path current

limitation of 280 μA, plus the charge pump current of 20 μA.

Table 39. Charge times bootstrap Cs using D_LSx sources

Bootstrap capacitor size (typ.)

Charge time (typ.)/ms

100 nF

330 nF

1.0 µF

2.2 µF

2.3

7.7

23.3

51.3

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7.1.2.3

Using the charge pump to charge bootstrap capacitors

If there is no current path from S_HSx pin to D_LSx or GND, only the internal CP can be used to charge the bootstrap capacitors during

init with a guaranteed current of 20 μA per HS pre-driver. This current is only available if there is no leakage current from B_HSx pin. Any

possible leakage current has to be subtracted from this available charge current.

It is not necessary to turn on either the LS MOSFETs or the D_LSx pull-down current sources to charge the bootstrap capacitors during

the init phase, if there is at minimum the current loop via the body diode of the external high-side MOSFET present. In addition, there is

some leakage current path from S_HSx to PGND. The charge pump starts charging the bootstrap capacitors as soon as the device is

supplied with V_CC5and a voltage greater 4.7 V at the VBOOST pin and POResetB is deactivated. Table 40 shows how long it takes to

charge a bootstrap capacitor to 7.0 V using the charge pump current of 20 μA.

Table 40. Charge times bootstrap Cs using CP

Bootstrap capacitor size (typ.)

Charge time (typ.)/ms

100 nF

330 nF

1.0 μF

2.2 μF

35

116

350

770

7.1.2.4

Using LS MOSFETs to charge bootstrap capacitors

After reset release of the device, the charging of the bootstrap capacitors via the D_LSx pull-downs and the internal charge pump starts

automatically. If there is the requirement to speed up the initial charging of the bootstrap capacitors, it is possible to switch on an LS

MOSFET connected to the HS MOSFET. If the device is configured in a proper way (refer Table 131, Hsx_ls_act (18Fh - 195h)) the

bootstrap switch current limit changes to the high limit of about 95 mA as soon as the LS pre-driver is turned on. Because the bootstrap

init mode is left for this HS pre-driver, it must be guaranteed that the internal V_CCPregulator is already switched on via the SPI bit, if

required.

After switching on the internal V_CCPregulator, the output buffer capacitor at the VCCP pin is charged. The device is still in a V_CCP

undervoltage condition, no external MOSFET (HS or LS) can be switched on, and the bootstrap diodes are also kept in the Off state. During

ramp up the voltage on the VCCP pin crosses the V_CCPundervoltage threshold. After the voltage is above this threshold (plus a minimum

16 μs delay), it is possible to switch on the LS MOSFETs.

There are two possible solutions to charge the HS pre-driver bootstrap capacitors using the path via the LS MOSFETs:

1. Wait for some specific time after V_CCPregulator is activated to ensure the V_CCPoutput voltage has reached it's nominal value of

about 7.0 V. This is only possible if the V_BATTvoltage is at a nominal value. Switch on the LS MOSFET(s) to charge the bootstrap

capacitors. If the V_CCPvoltage was high enough and the bootstrap capacitors are small compared to the V_CCPoutput buffer

capacitor, this leads to a transfer of charge without crossing the V_{CCP_UV}threshold again. Figure 22 shows this strategy.

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7V

uv_vccp

1

VCB_HSx

VCCP

0V

Lowside_command

Boostrap_charged

3

Tcharge_VCCP

2

Wait until VCCP is

charged (depend

on C^Vccpvalue)

Switch on low side

with microcore

(sto lsx on)

Switch on VCCP

(Vccp_en=1)

1

2

3

Figure 22. Power-up: V

and bootstrap capacitors - after V

fully charged

CCP

2. Switch on the LS MOSFET(s) as soon as possible after the V_CCPvoltage is above the V_{CCP_UV}threshold. This causes the V_CCP

voltage to cross the V_{CCP_UV}threshold again and thereby the LS MOSFET(s) and the bootstrap diode are switched off again. The

V_CCPvoltage recovers from undervoltage and after the delay min. of 16 μs, the LS MOSFET(s) and the bootstrap diode are switch

on again. This pulsed charging of the bootstrap capacitors with a frequency of below 50 kHz continues until the voltage of the

bootstrap capacitors is above the V_{CCP_UV}threshold. Figure 23 shows this strategy.

7V

uv_vccp

delay

uv_vccp_threshold

1

0V

VCCP

VCB_HSx

3

Lowside_on

Lowside_command

Boostrap_charged

2

Low side will switch ON/

OFF automatically due to

uv_vccp

Switch on VCCP

(Vccp_en=1)

Turn on low side

with microcore

1

2

3

Figure 23. Power-up: VCCP and bootstrap capacitors - before VCCP fully charged

Strategy 2 is preferred, because it adds less constraints to the size of the bootstrap capacitors and the SW implementation. If strategy 1

is tried, but some of the premises are not fulfilled (V_BATT/V_CCPvoltage, size of bootstrap capacitors), the result is the same pulsed charging

described in strategy 2.

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7.2

DC/DC converter control (LS7/8)

The two DC/DC converters implemented each support three DC/DC converter control modes. These modes can be chosen via microcode

instruction “stdcctl”. This command affects the ls pre-driver which is set as shortcut two of the microcore (see instruction “stdcctl” in the

programming guide).

Table 41. DC/DC converter control modes

DC/DC mode

Microcode instruction

stdcctl sync

Short description

1

2

3

LSx manual mode (LSx controlled by microcode)

stdcctl async

LSx hysteretic mode direct controlled by curYh and curYl feedback signals)

LSx resonant converter mode. (direct controlled by VdsX_dcdc and curYh_fbk)

stdcctl async_vds

7.2.1

General description

The operation modes of the DC/DC converter can be activated by the microcode instruction “stdcctl sync/async/async_vds”. Every

microcore which has access to the LS7/8 pre-driver, according to the crossbar configuration, can activate the DC/DC control modes using

this microcode instruction. The LS7/8 outputs can be controlled by standard control method - microcode instruction (mode1) or automatic

DC/DC converter control modes (mode 2/3).

As soon as a microcore having access to the LS7/8 is unlocked, the automatic DC/DC control is switched off. Mode 2 and mode 3 can be

used to achieve a very fast asynchronous regulation. The current can be changed either through microcode or by writing the DAC

Registers via the SPI (See DAC 1-6 values registers on page 112).

7.2.1.1

Mode 1 (manual mode)

The DC/DC converter control mode 1 is chosen by microcode and is set as the default. The current_feedback_5/6 is monitored by

microcode and the LS7/8 is controlled completely via microcode. The low-side is controlled directly by the microcore using the “sto”

instruction.

7.2.1.2

Mode 2 (hysteretic control)

Mode 2 is intended to be used for standard current controlled ‘asychronous’ DC/DC converters. A very fast current regulation between the

current thresholds 5/6H (higher limit) and 5/6L (lower limit) can be achieved. These two current thresholds can be supplied either from

microcode or by writing to the DAC register (refer to See DAC 1-6 values registers on page 112).

The LSx output is switched on when current_feedback_5/6L is low and switched off when current_feedback_5/6H is high. The path from

the shunt resistor to the LS7/8 output is completely asynchronous to any clock of the device. The current feedback of DAC 5/6H takes

priority, so in cases where both feedbacks are active (DAC 5/6H feedback high and DAC 5/6L feedback is low), the output LS7/8 is driven

low. This mode is used for standard DC/DC control.

Note that when this mode is used LS7, it should be paired with current sense 5 and LS8 with current sense 6.

G_LS7/8

ISENSE5_HIGH

ISENSE5/6

ISENSE5_LOW

Figure 24. DC/DC mode 2: hysteretic control

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7.2.1.3

Mode 3 (LS7/8 resonant mode V monitoring)

DS

Mode 3 can be used for controlling resonant converters which require a V_DSthreshold based activation of the MOSFET. In this case, a

small capacitor (~10 nF) C_RESin parallel with the external MOSFET has to be connected, to avoid oscillation when the low-side is off.

To use Mode 3, the signal l_{SX_VDS_HIGHSPEED_EN}has to be set to a “1” via the control bit in the vds7/8_dcdc_config register (see

Table 116, Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h)).

V_DSfast monitoring of D_LS7/8 uses the same threshold generator as the normal V_DSmonitoring, but only the threshold voltages of 2.0 V

and 2.5 V can be used.

Functionality:

As soon as V_DS7/8 drops below the threshold voltage, the MOSFET activates. To switch Off the MOSFET, the Cur5/6H - Feedback signal

is used. The cur5/6h_dcdc current feedback takes priority if both feedbacks are high. LS7 or LS8 is driven low. This event is not

guaranteed in every condition. When LS is off, there is an oscillation on V_DS(hence the resonant name) whose amplitude depends on the

"V_BOOST-V_BAT" value, so a timeout is used to make sure the LS can be enabled again.

Timeout functionality:

If V_BOOSTdrops below V_BATx2, the V_DSthreshold of 2.5 V is not crossed. The MOSFET cannot be activated again, which means the DC/

DC converter stops. A timeout must be started each time the lower current threshold is reached (cur5/6l_fbk signal changed to low). When

V_DSfeedback is set low during this timeout period, the timeout monitor stops and is reset. If the V_DSfeedback cannot set to a low during

this timeout period, the MOSFET activates directly by the timeout logic.

Vboost

ISENSE5/6_HIGH

ISENSE5/6

Cur5/6h_fbk

Ls7/8_command

Ls7/8_vds_fast_fbk

tVDS_DCDC_PD

D_LS7/8

2.5V threshold

Internal Logic

External_Voltage

External_current

Figure 25. DC/DC mode 3 resonant (threshold 2.5 V used)

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7.3

Device clock manager and PLL init

After 100 μs the clock monitor is enabled, Table 42 shows different strategies to start the device.

The clock manager duty is to detect a low frequency (or missing) input reference or a PLL malfunction. To do so, it monitors the PLL output,

to check if the output clock frequency is within acceptable range.This is achieved counting the number of pll_output_clock cycles inside

six periods of the backup reference clock (six periods of 1.0 MHz clock = 6.0 μs). The expected number depends on the selected PLL

multiplication factor;

• when the factor is 24, it is detected an invalid clock condition when it is possible to count more than 165 or less than 125

pll_output_clock cycles.

• when the factor is 12, it is detected an invalid clock condition when it is possible to count more than 84 or less than 61 pll_output_clock

cycles.

After requesting the switch back to the external clock reference the device cannot be accessed via the SPI (see Table 152,

backup_clock_status (1A8h)) for about:

• 100 μs if there is a valid external clock available

• 290 μs (250 μs+40 μs re-lock time) if there is no valid input clock available and the device has to go back to the backup clock again.

The SPI word transmitted to set the Switch to clock pin bit has to be the last word within a SPI burst.

Table 42. Device clock manager and PLL init

Initial state

1. Step

2. Step

3. Step

Result

Device supplied, but in reset

(ResetB), no ext. clock

Supply external 1.0 MHz

clock at CLK input

Device accessible after 40 μs (PLL lock

Deactivate ResetB

—

time) and running on ext. clock

Device supplied, but in reset

(ResetB), no ext. clock

Supply external 1.0 MHz

clock at CLK input

Device accessible immediately and running

on ext. clock

Wait for t > 20 μs

Deactivate ResetB

—

Device supplied, but in reset

(ResetB), no ext. clock

Device accessible after 140 μs and running

Deactivate ResetB

—

on backup clock

Supply external

1.0 MHz clock at CLK

input at t < 100 μs

Device supplied, but in reset

(ResetB), no ext. clock

Device accessible 40 μs (PLL lock time)

after CLK available and running on ext. clock

—

Device running on backup clock, Supply external 1.0 MHz

no ext. clock clock at CLK input

Request switch to

external clock

Device accessible 100 μs after switch

—

request and running on ext. clock

Device running on backup clock, Request switch to external

no ext. clock clock

Device accessible 290 μs after switch

request and running on backup clock

—

7.4

SW initialization flow

7.4.1

Power supply, reset, and clock

• Supply device

• The device needs 5.0 V supply voltage on the VCC5 pin and 3.3 V or 5.0 V supply voltage on the VCCIO pin

• A voltage at the VBATT and/or VBOOST pin is not mandatory for device initialization

• As soon as the device is properly supplied at the VCC5 pin, VCC2P5 regulator is started

• When V_CC2P5is above a specific threshold, the internal POResetB signal is deactivated

• After the internal POResetB signal is deactivated, it takes a maximum time of 100 μs until the digital outputs of the device are

functional

• Setup external reference clock of 1.0 MHz at the CLK pin

• The PLL is locked about 25 μs after the external CLK is enabled

• If the external clock signal availability cannot be guaranteed within this period, it is recommended to reset the device via ResetB

immediately, or switch to the external clock reference later via the SPI command

• Deactivate ResetB signal

• The external reset signal ResetB has to be deactivated if it has been active

• As soon as there is no POResetB and ResetB signal active, the internal reset RSTB is deactivated

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7.4.2

SPI configuration

The whole SPI configuration can be done while the device is using the internal backup clock reference. The device registers are not locked

after device reset.

• Check if device is accessible via the SPI

• Check if the device is accessible via the SPI by reading the ID/REV register

• Init the main configuration registers

• Init the main configuration registers including the Clock Prescaler, Flag pin setup,…

• If the application uses the internal V_CCPregulator to supply the pre-drivers, this regulator must be switched on now

• Set code width

• If the microcode transmits using one single SPI burst, it is mandatory to write the code width register of each channel used

• If the microcode is transmitted using multiple bursts which include information about the number of words, the code width register

can also be written

• The code width must be set before setting the pre_flash_enable bit, because the checksum calculation information is required

• Download microcode

• Download microcode via the SPI for each channel used

• Set the CRC32 checksum

• Set the checksum_l/h register (32-bit) of each channel used

• Init diagnostics configuration registers

• Init I/O configuration registers

• Init channel configuration registers

• Init DRAM values for the first time

• Depending on the application and the microcode, it could be required to set up DRAM parameters of the channels used

• Set the lock bit in the device_lock register (optional)

7.4.3

Clock monitor, flash enable, and DrvEn

• Check if the device is running on an external reference clock

• It is recommended to verify the device is running on the external clock reference. This can be checked by reading a bit in the

driver_status SPI register

• If the device is running on the backup clk, it is possible to switch the clock manager to external reference via a SPI command

• This is only mandatory if the external clock reference is not available in time and the device is running on the backup oscillator’s clock

• The clock manager is forced to try to switch back to the external reference by a SPI write to a dedicated bit

• SPI transfers have to be avoided when switching the clock reference. The SPI module is in reset as long as there is no valid clock

• Do not switch the clock reference while the first checksum calculation is running

• Set the pre_flash_enable bit

• Set the pre_flash_enable bit of the used channel(s)

• This bit “freezes” the CRAM and enables the signature unit to perform the CRC32 check for the first time

• After the signature unit has finished the first CRC32 check successfully, it sets the flash_enable bit to start the microcore(s) of the

used channel(s)

• The microcode should check for the flash_enable bit with a timeout ensuring the microcores are running

• Activate the DrvEn signal

• Depending on the application and the microcode, it could be required to activate the DrvEn signal if deactivated

7.5

BIST

The device has a built-in self test (BIST) for the memory (MBIST for CRAM and DRAM) and for the logic core (LBIST). The BIST can be

started by the SPI (see Table 170, Bist_interface in write mode (1BDh)). A full LBIST check of the device digital core and MBIST check

of the device memories can be required accessing the BIST_register in Write mode and writing a 16-bit password. This request is

accepted only if all three CRAMs are unlocked. It is recommended to run MBIST and LBIST during the initialization phase, since the DRAM

and CRAM are erased during BIST.

After this request is performed, the LBIST and MBIST check starts and its evolution can be monitored accessing the same BIST_register

in read mode.

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7.5.1

MBIST

The MBIST is started by writing the MBIST password (B157h) to the BIST register (see Table 170, Bist_interface in write mode (1BDh)).

The overall MBIST operation takes about 2.2 ms (at 24 MHz) to complete. During the memory BIST five different tests are performed using

different patterns to test the RAM. The patterns are:

• All 00, All 11

• All 55, All AA

• All 0F, All F0

• All 00, All FF

• All FF, All 00

While the MBIST is running the digital core of the device is functional. The SPI interface can be used. It is not possible to use the CRAM

and DRAM.

7.5.2

LBIST

The LBIST is started by writing the LBIST password (0666h) to the BIST register (see Table 170, Bist_interface in write mode (1BDh)).

The overall LBIST operation takes about 32 ms (at 24 MHz) to complete. The coverage of the LBIST is > 92%.

The SPI interface is also covered by the LBIST. During the LBIST the device is no longer accessible via the SPI. When the LBIST is started

it takes control of the IRQB pin, which is used as a digital output signal to show the LBIST is busy. The IRQB pin is set low while the LBIST

is running. When the LBIST is finished, the IRQB signal goes high again.

The LBIST could fail in a way the IRQB signal never goes high again. In this case, the microcontroler needs to monitor this and reset the

device. When LBIST is finished (IRQB signal high), the device can be accessed by the SPI again and the LBIST result is available in the

BIST register (see Table 171, Bist_interface in read mode (1BDh)). After reading the results, the LBIST needs to be cleared by sending a

CLEAR command (refer to Table 170, Bist_interface in write mode (1BDh)). This releases the logic and the device returns to its original

state. It is recommended to check if the LBIST result is reset to “00” to ensure the LBIST clear command was successful.

The LBIST can be interrupted by a hardware reset via the RESETB pin. There is a second way to stop the LBIST after it is started by

writing the LBIST password. This is done by setting the Flag0 input pin to high. There is information in the LBIST result indicating the LBIST

was stopped by Flag0. Also in this case, an LBIST clear command (C1A0h) has to be sent or the RESETB pin must be set low to return

to normal operation mode. The FLAG0 pin has a weak PD resistor. If the pin is not connected, the LBIST runs and cannot be stopped by

Flag0.

7.6

Reset sources

The device has three possible reset sources:

• the resetb input reset pin is driven low

• the poresetb (power on reset) signal generated by the internal voltage regulator, incase an undervoltage is detected on VCC2P5

• a SPIresetb request received through SPI, when the appropriate code is written to the “global reset registers” (refer to See SPIReset

global reset register 1 and 2 on page 126). It is kept asserted for a fixed time (333 ns) then it is released.

Reset source can be determined reading the Reset_source register (refer to Table 168, Reset_Source (1B7h)).

CVCC2P5

VCC5

VCC2P5

POResetB

SPIResetB

Power On

Reset

VCC2P5

Regulator

RSTB

logic

ResetB

RESETB

AGND

Figure 26. VCC2P5 and reset sources

PT2000

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NXP Semiconductors

As long as RSTB is asserted, the SPI module is also inactive. In order to understand when the device has gone out of reset state, the

microcontroller should poll the device on the SPI. This can be done by either sending any message to the device and checking for the

control pattern (A8h) on the MISO during the command word or by reading out any register with a reset value not equal to zero (e.g. ID

register).

7.7

Cipher unit

This block has the function to secure the code downloaded by the microcontroller into the code RAM via the SPI. The data loaded at device

startup must be encrypted with the suitable cipher. This block receives an encoded SPI stream and decodes it at runtime. The decoded

microcode is then stored in the code RAM. This feature cannot be disabled. The cipher algorithm is re-initialized every time the code

memory is selected by a write operation to the Selection register (3FFh).

7.8

Ground connections

The device integrates three separate ground pins: PGND, DGND, and AGND:

• PGND is the substrate connection and is only connected to the package exposed pad, to guarantee a low-impedance connection and

get optimized EMC performances. PGND is the reference ground for the V_CCPregulator, some analog functions, and all of the low-side

pre-drivers. It is highly recommended to directly connect PGND to the ECU ground plane.

• DGND is the reference ground for the digital logic core. It is highly recommended to directly connect DGND to the ECU ground

plane.The microcontroller as well as other logic devices communicating with the device should share the same reference ground

connected to the ground plane to prevent noise.

• AGND is the ground for all the noise sensitive analog blocks integrated into the device. This pin should be connected to the analog

ground of the ECU. A star connection is recommended to guarantee a clean analog signal acquisition of the OAX_x pins from the MCU.

Due to their functionality, some analog functions are referred to PGND:

• VDS monitors the low-side drivers

• VSRC monitors the high-side drivers

• The load biasing S_HSX regulator and the D_LSx pull-down

All the ground pins of the device should be connected to the same ground voltage. Even during transient conditions, the voltage difference

between PGND, DGND, and AGND must be limited to ±0.3 V. The layout of the ground connection of the ECU should be carefully

designed to limit the ground noise generated as much as possible, for instance during fast switching of the external power MOSFETs.

The decoupling and filter capacitors at the different supply voltage pins should be implemented as described by the following:

• VCC5 to AGND

• VCCIO to DGND

• VCC2P5 to DGND

• VCCP to PGND

• VBATT to PGND

• VBOOST to AGND or PGND

7.8.1

Detection of missing GND connections

The PT2000 can detect any single or multiple missing connection of any ground pin (PGND, DGND, AGND) of the device. At least one

ground must remain connected to allow the loss of ground detection. If the ground disconnection is detected, the internal signal uv_vccp

is asserted and all the pre-drivers are disabled. The ground lost detection is filtered to allow the device to work in a proper way for a time

of typically t_{FILTER_UVVCCP}via the uv_vccp signal.

7.9

Shutoff path via the DrvEn pin

The device includes a shutoff path via the DrvEn pin, which is used to safely disable the solenoid injection power stage in a fault condition

of the ECU. When the DrvEn pin is negated, all pre-drivers (w/o configuration option for DrvEn) must be switched off. Status of the DRVEN

pin can be read back by the SPI (refer to Table 162).

The shutoff path also works in a defined way (switch off all pre-drivers) when DrvEn is negated, even when the PT2000 is stressed with

a voltage of up to 36 V at the supply and/or microcore interface (SPI, Startx,…) pins. Digital interface pins of the PT2000 are self-protected

against a voltage of up to 36 V: CLK, IRQB, ResetB, DrvEn, MISO, MOSI, SCLK, CSB, Dbg, Startx (7x), Flagx (4x), OA_x (3x).

PT2000

NXP Semiconductors

66

7.9.1

DrvEn shutoff path of the high-side pre-driver

The DrvEn path for the HS pre-drivers HS1 to HS4 and HS6 is implemented to ensure a high safety level. It is designed with a high level

of independence, because there is a direct wire from this pin to the HS pre-driver input and the failure rate of this functionally is very low.

If any of the following failures occur, the shut off path is still functional or the driver must be in a safe off state. These failures are:

• Missing clock signal for the device digital core

• Missing supply voltage for the device digital core

• Missing supply voltage of level shifter

• Missing supply voltage (V_BS) of HS pre-driver

• Single damaged pre-driver

Table 43. DrvEn path for HS pre-drivers

HS pre-driver

HS1

Implementation

HS2

HS3

Direct wire from the DrvEn pin to the HS pre-driver input. High independence and low FIT rate.

HS4

HS6

HS5

Configuration option for the DrvEn path. The signal is routed via the digital core only.

HS7

7.9.2

DrvEn Shutoff path of the low-side pre-driver

The DrvEn path for the LS pre-drivers LS1 to LS5 is implemented to ensure a high safety level. It is designed with a high level of

independence, because there is a direct wire from this pin to the HS pre-driver input and the failure rate of this functionally is very low.

If any of the following failures occur, the shut off path is still functional or the driver must be in a safe off state. These failures are:

• Missing clock signal for the device digital core

• Missing supply voltage for the device digital core

• Missing supply voltage VCCP of LS pre-driver

• Single damaged pre-driver

Table 44. DrvEn path for LS pre-drivers

LS Pre-driver

LS1

Implementation

LS2

LS3

Direct wire from the DrvEn pin to the LS pre-driver input. High independence and low FIT rate.

LS4

LS6

LS5

Configuration option for the DrvEn path. The signal is routed via the digital core only.

LS7

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NXP Semiconductors

8

Digital core

The digital core controls the actuation of the electro-actuators. The digital core serves as the main microcore features for actuator control,

structures for HW configuration, and the communication interface with the ECU microcontroller.

There are six total microcores which can run concurrently and independently. The microcores are arranged in channels. Each channel

contains two microcores, one instruction RAM (CRAM), and one data RAM (DRAM). This architecture of shared RAM allows efficient use

of the RAM when multiple actuators need to be controlled in parallel with identical microcode. Each digital core communicates with the

external microcontroller through a SPI bus and by means of a set of single wire I/O. Accessible by the SPI are:

a). Registers with dedicated function

b). Data RAM

To avoid access conflicts, a time division multiplex scheme controls the access to the RAMs by the different entities. Thus, microcode

runtime of one microcore is not influenced by RAM access from the SPI or the other microcores.

8.1

Logic channels description

This section describes the features and operation of the microcores (central processing unit, or CPU, and development support functions)

used in the PT2000.

The PT2000 provides a set of three logic channels each channels which include:

• Two 16-bit processing units (microcores) having a specific programming model

• One Code RAM - 1023 x 16-bit. The memory dedicated to microcode storage is shared between the two microcores of logic channel

• One Data RAM - 64 x 16-bit. The memory dedicated to variable storage is shared between the two microcores of a logic channel

Figure 27 describes logic channel 1. The other channels are identical.

SPI Interface

SPI Backdoor

CRAM

1023 x 16bits

microCore1

(uc1ch1)

microCore0

(uc0ch1)

Signature

Unit

DRAM

64 x 16 bits

Out_cmd,

dac, gain,

diag...

Dual Microcore Arbiter

Flags

LOGIC CHANNEL 1

Flags management

Output interface

Figure 27. Logic channel 1 diagram

PT2000

NXP Semiconductors

68

8.1.1

Microcores

The microcores are actually small microprocessor cores. These are typically programmed to implement software based finite state

machines controlling the actuator operation. The microcores have access to the analog input and output functions, but are also able to

communicate with each other by a flag bus.

μCore

6

Data RAM

Address Base + Address

6

16

6

Code RAM

Uprogram_counter

10

uPC

10

Instruction_

decoder

10

Auxiliary

Register

start_gen

Interrupt

Return

Register

output commands

DAC

10

Internal_re

g_mux

tc1

16

voltage feedbacks

current feedbacks

Counter 1

3

16

6

eoc_reg1

automatic diasgnostic interrupt

vboost voltage

tc2

16

Counter 2

ALU

16

eoc_reg2

tc3

16

Counter 3

16

eoc_reg3

16

tc4

16

Counter 4

16

eoc_reg4

Signal

Data bus

Data

Flag Bus

Figure 28. Microcore block diagram

For further detail on how to program the microcores, (reference Programming Guide and Instruction Set).

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NXP Semiconductors

8.1.2

Dual microcore arbiter

This block handles the access to code RAM and data RAM memories by the different possible users:

• the two microcores

• the signature unit (code RAM only)

• the SPI interface

8.1.2.1

Access sequence to code RAM

When the device is operating in single microcore mode, access slots to code RAM are granted according to Table 45.

Table 45. Code RAM access sequence (single microcore mode)

Ck_per

flash_enable

T0

T1

T2

T3

Teven

Todd

1

2

3

4

1

0

1

0

1

0

1

0

uc0

SPI r/w

uc0

CHKSM

SPI r/w

CHKSM

SPI r/w

CHKSM

SPI r/w

CHKSM

SPI r/w

-

CHKSM

SPI r/w

CHKSM

SPI r/w

CHKSM

SPI r/w

-

SPI r/w

uc0

-

SPI r

SPI r/w

SPI r

SPI r/w

-

SPI r/w

uc0

-

CHKSM

SPI r/w

SPI r

SPI r/w

The clock divider = ck_per +1 (refer to Table 136, Clock_Prescaler (1A0h)). Teven represents all the time slots with an even number id

from T4, and following T4. Todd represents all the time slots with an odd number id from T5 and following T5. When the device is operating

in dual microcore mode, access slots to Code RAM are granted according to Table 46.

Table 46. Code RAM Access Sequence (dual microcore mode)

Cycle stealing when

Ck_per

flash_enable

T0

T1

T2

T3

Teven

Todd

uc0/1 are in wait

1

2

3

4

1

0

1

0

1

0

1

0

uc0

SPI r/w

uc0

uc1

SPI r/w

uc1

CHKSM

SPI r/w

CHKSM

SPI r/w

CHKSM

SPI r/w

CHKSM

SPI r/w

uc0

SPI r/w

uc1

SPI r

SPI r/w

SPI r

-

SPI r/w

uc0

SPI r/w

uc1

-

CHKSM

SPI r/w

SPI r

SPI r/w

The PT2000 allows using a dual sequencer with a ck_per = 1, which means with a clock at 12 MHZ, however some restrictions apply on

the DRAM access (See Access sequence to data RAM on page 71).

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70

8.1.2.2

Access sequence to data RAM

When the device is operating in single microcore mode, access slots to data RAM are granted according to Table 47.

Table 47. Data RAM access sequence (single microcore mode)

Ck_per

flash_enable

T0

T1

T2

T3

Tother

Tlast

1

0

1

0

1

0

1

0

SPI r/w

uc0

-

SPI r/w

-

2

uc0

-

2

SPI r/w

-

3

uc0

-

3

SPI r/w

-

4+

4

SPI r/w

uc0

SPI r/w

The clock divider = ck_per +1’ (refer to Table 136, Clock_Prescaler (1A0h)). Tlast represents the last time slot. Tother represent all time

slots (if any) between T3 and Tlast. When the device is operating in dual microcore mode, access slots to data RAM are granted according

to Table 48

Table 48. Data RAM Access Sequence (dual microcore mode)

Cycle stealing when uc0/

Ck_per

flash_enable

T0

T1

T2

T3

Teven

Todd

1 are in wait

1

2

3

4

1

0

1

0

1

0

1

0

uc1

SPI r/w

uc1

uc0

SPI r/w

uc0

SPI r/w

uc1

SPI r/w

uc0

-

SPI r/w

uc1

SPI r/w

-

SPI r/w

uc0

SPI r/w

Note that when ck_per is equal to 1 and dual microcore mode is enabled, there are some limitations for the DRAM access.

As shown in Table 48 when “ck_per = 1” the SPI has no dedicated access slot to the DRAM. At the same time it is clear for most

applications, both microcores do not have to access the DRAM every microcontroler clock cycle. It is possible to use some unused slots

from the microcores for the SPI.

The limit with the 12 MHz dual sequencing access to the data RAM: there is a strong limit on how many instructions in a row the data ram

can access (load, store instructions). This limit depends on the SPI frequency used in the application.

As a consequence, the microcore 0 and 1 must not block the DRAM access slots for longer than the given number of ck cycles minus 1.

If this limit is achieved, it automatically be reported by the NXP IDE (compiler).

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NXP Semiconductors

Table 49 shows the smallest period in μs and ck (12 MHz) clock cycles between the address available and first read data bit for SPI read

access, which could occur based on a given SPI baud rate.

Table 49. SPI baud rate and DRAM access sequence for the ck_prescaler = “1”

Minimum SPI read address to first read data bit delay (5 bits)

SPI baud rate (MHz)

ck Cycles (12 MHz)

μs

1.0

2.0

4.0

8.0

10

5.0

2.5

60

30

1.25

0.625

0.5

15

7.5

6.0

8.1.3

Signature unit

The task of the signature unit is to compute a checksum of the CRAM to detect possible memory corruption.

The computation is first started when the corresponding CRAM is locked by the pre_flash_enable (see Table 58, Flash_enable (100h,

120h, 140h)). When the computation is complete, the result of the computation is compared to the checksum registers (see Table 66,

checksum_h (108h, 128h, 148h)) and Table 67, checksum_l (109h, 129h, 149h)). These registers contain the golden checksum, provided

during the init phase through the SPI and calculated automatically by the PT2000 IDE.

If the result is correct, the signature unit sets the flash_enable bit (see Table 58, Flash_enable (100h, 120h, 140h)). If the result is not

correct, an interrupt (optional, refer to Table 58, Flash_enable (100h, 120h, 140h)) is issued towards the microcontroller and both

microcores accessing the same CRAM are disabled.

The signature unit can be disabled by writing the Checksum_failure_disable bit in the flash_enable_reg (refer to Table 58, Flash_enable

(100h, 120h, 140h)). When the signature is disabled, the flash_enable bit is set immediately after the pre_flash_enable bit and a failed

checksum causes only a warning (set the appropriate bit in the flash_enable register) without disabling code execution.

The computation requires a different time according to the ck_per value and to the code_width (refer to Table 65, code_width (107h, 127h,

147h)). The worst case computation time for a ck_per of 1 and higher (ck = cksys/2+1 or smaller) is 20 * t_CKSYS* (code_width-2). For

example, for a completely used memory, a ck_per of 2 and a cksys clock frequency of 24 MHz (ck at 6.0 MHz), the computation takes

851 μs.

The signature unit works only for a code width of 3 or larger. If a shorter code of 1 to 2 words is used, the signature unit has to be disabled.

8.1.4

SPI backdoor

It is also possible to access (both to read and to write) to all the registers normally accessible through the SPI by using an SPI backdoor.

Both the SPI read and write operations are multi cycle operations. Table 51 shows the number of cycles needed. The registers must not

be changed while the operation is in progress.

To read an SPI register, first the 8 LSBs of the address must be provided in the 8 LSBs of the “SPI address” at internal memory map

address. A read operation must then be requested with the “rdspi” instruction (refer to programming guide). The result is available at the

“SPI data” address of the internal memory map.

To write an SPI register, first the 8 LSBs of the address must be provided in the 8 LSBs of the “SPI address” address and the data to write

must be provided at the “SPI data” address. Then a write operation must be requested with the “wrspi” instruction (refer to programming

guide).

There are some access limitations when requesting write access to SPI registers via the SPI backdoor:

• First of all, it is only possible to write to SPI registers which are not locked at the moment the write operation “wrspi” is requested.

• For some special registers there are additional limitations dependant on the configuration of the device. Table 51 shows the different

limitations.

PT2000

NXP Semiconductors

72

Both the SPI read and write operations are multi cycle operations. Table 50 shows the number of cycles needed. The registers and the

SPI address mode (set using “slsa” instruction) must not be changed while the operation is in progress.

Table 50. Cycles for SPI backdoor read/write

ck_prescaler value

Cycles for SPI backdoor r/w

1

2

4

3

2

3+

Table 51. SPI backdoor access limitation

SPI_registers

Configuration

controlling access rule

Access rule

vds_threshold_hs,

vsrc_threshold_hs,

vds_threshold_ls

Only microcores which are allowed to control a certain HS or LS pre-driver are

allowed to change the corresponding V_DSand V_SRCthreshold. Changes to all other

out_acc_seqXchY

V_DSand V_SRCvalues are ignored.

Only microcores which are allowed to control a certain HS or LS pre-driver are

allowed to change the corresponding slew rate setting. Changes to all other slew

rate settings are ignored.

hs_slewrate,

ls_slewrate

out_acc_seqXchY

Only microcores which are allowed to control a certain HS or LS pre-driver are

allowed to control the corresponding biasing source. Changes to all other biasing

sources are ignored

hs_bias_config

ls_bias_config

Only microcores which are allowed to control the LS7 or LS8 pre-driver are allowed

to change the corresponding vds_dcdc_timeout register setting. All other changes

are ignored

vds7_dcdc_config

vds8_dcdc_config

dac1, dac2, dac3, dac4, dac5l, dac5h,

dac5neg, dac6l, dac6h, dac6neg,

boost_dac

No access is possible through the SPI backdoor

8.1.5

CRAM

The code RAM is a 1024x16 single port RAM memory defined to store the micro-code for the entire channel (both microcore0 and

microcore1 if dual microcore mode is enabled).

When enabled, the two microcores can execute either exactly the same code or separate codes, in which case the memory space

dedicated to each microcore are a subset of the overall CRAM. This use of the CRAM memory is controlled by configuration registers

defining the entry point (meaning the starting address) of each microcore (refer to Table 68, uc0_entry_point (10Ah, 12Ah, 14Ah)and

Table 69, uc1_entry_point (10Bh, 12Bh, 14Bh)).

8.1.6

DRAM

The data RAM is a 64x16-bit RAM which can be used as an interface between microcores and the external microprocessor, and also to

store data used only internally by the microcores. The data RAM is accessed as a “flat” memory, where all the 64 memory locations can

be accessed by the external microcontroller and both microcores.

PT2000

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NXP Semiconductors

8.2

Serial peripheral interface

The communication between the PT2000 and the main microcontroller is managed with a 16-bit SPI interface.

This block is the module providing the SPI connection features. The block is full-duplex, so it can receive and transmit at the same time.

The device requires a cphase value of 1 and a cpol value of 0. This means the SPI module samples the MOSI signal, during write

operations, on the falling edge of the serial clock. Likewise, during read operations, the SPI module always puts the output value available

on the MISO signal on the rising edge of the sclk clock.

CSB

SCLK

16 CLK

CPOL= 0

MISO

MSB

LSB

CPHA = 1

MOSI

Figure 29. SPI protocol diagram

While the PT2000 component has many memory locations to access, it was necessary to develop a protocol to manage this.The protocol

is implemented in such a way, so after a reset occurs and after any burst transaction on the SPI connection, the protocol always waits for

a control word. This is a 16-bit word built as follows:

Table 52. SPI protocol

control_word

control_word (bit 15)

Meaning

r_w: read (1)/write (0) operations

offset: start address

control_word (bits 14 to 5)

control_word (bits 4 to 0)

number: number of operations

When this control word is received, the protocol understands the external micro-controller wants to perform a read (when this bit is set to

1) or write (when this bit is set to 0) operation looking at the r_w bit. Looking at the number value, the protocol then understands how many

concurrent read of write operations the external microcontroller wants to perform (max 31). Finally, looking at the offset value, the protocol

understands where these operations should start, meaning what is the first address in this burst of operations to be accessed.

PT2000

NXP Semiconductors

74

8.2.1

SPI read access

A SPI burst for read access consists of 2 to 32 16-bit words. The way the number of words is defined depends on the SPI mode used (A

or B). Table 53 shows the data transmitted on MOSI and MISO. During the command word the check byte and the SPI error status is

transmitted via the MISO line.

Table 53. SPI read access

MOSI word 1 (control word) – read access

Bit

15

r_w

1

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Value

offset

0 to 1023

MISO word 1 (control word) – read access

number

n=0 to 31

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cksys

frame

word

Name

Values

check byte

missing error

error

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Value

HEX

A

8

MOSI word 2 (data) – read access

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Value

empty (don’t care)

0

MISO word 2 (data) – read access

10

Bit

15

14

13

12

11

9

8

7

6

5

4

3

2

1

0

Name

read data 1

MOSI word n+1 (data) – read access

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Value

empty (don’t care)

0

MISO word n+1 (data) – read access

10

Bit

15

14

13

12

11

9

8

7

6

5

4

3

2

1

0

Name

read data n

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NXP Semiconductors

8.2.2

SPI write access

A SPI burst for write access consists of 2 to 32 16-bit words. The way the number of words is defined depends on the SPI mode used (A

or B). Table 54 shows the data transmitted on MOSI and MISO. During the command word and all data words, the check byte, and the

SPI error status is transmitted via the MISO line.

Table 54. SPI write access

MOSI word 1 (control word) - write access

Bit

15

r_w

0

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Value

offset

0 to 1023

MISO word 1 (control word) - write access

number

n=0 to 31

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cksys

frame

word

Name

Values

check byte

missing error

error

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Value

HEX

A

8

MOSI word 2 (data) - write access

10

Bit

15

14

13

12

11

9

8

7

6

5

4

3

2

1

0

Name

write data 1

MISO word 2 (data) - write access

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

cksys

frame

word

Name

Values

check byte

missing error

error

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Value

HEX

A

8

MOSI word n+1 (data) - write access

10

Bit

15

14

13

12

11

9

8

7

6

5

4

3

2

1

0

Name

write data n

MISO word n+1 (data) - write access

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

cksys

frame

word

Name

Values

check byte

missing error

error

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Value

HEX

A

8

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8.2.3

SPI protocol

Mode A

8.2.3.1

CSB

MOSI

(read)

control word

SPI watchdog

MISO

(read)

check byte

error bits

data 1

data n+1

MOSI

(write)

control word

MISO

(write)

check byte

error bits

check byte

error bits

check byte

error bits

Figure 30. SPI protocol mode A CSB, MOSI, and MISO

The maximum delay between data belonging to the same burst is specified by the spi_watchdog parameter (refer to Table 153, Spi_config

(1A9h)). Between one data transfer and the next, the SPI chip select can be asserted. If the delay exceeds the watchdog time, the SPI

interface goes into the error state.

It is possible to perform long burst transfers by sending a control word with the parameters number and offset set to zero. The effect varies

according to the current value of the channel select register (refer to Table 56, selection_register (3FFh)):

• If the value of channel select register is “0xxxxx001”, the protocol performs a burst of operations starting from address 0; the number

of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel

1. This command is used to write the whole CRAM of channel 1 with only one command word.

• If the value of channel select register is “0xxxxx010”, the protocol performs a burst of operations starting from address 0; the number

of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel

2. This command is used to write the whole CRAM of channel 2 with only one command word.

• If the value of channel select register is “0xxxxx100”, the protocol performs a burst of operations starting from address 0; the number

of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel

3. This command is used to write the whole CRAM of channel 3 with only one command word.

• If the value of channel select register is “0xxxxx011”, the protocol performs a burst of operations starting from address 0; the number

of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel

1. This command is used to fully write the CRAMs of channel 1 and 2 (with exactly the same code) with only one command word.

• If the value of channel select register is “0xxxxx101”, the protocol performs a burst of operations starting from address 0; the number

of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel

1. This command is used to fully write the CRAMs of channel 1 and 3 (with exactly the same code) with only one command word.

• If the value of channel select register is “0xxxxx110”, the protocol performs a burst of operations starting from address 0; the number

of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel

2. This command is used to fully write the CRAMs of channel 2 and 3 (with exactly the same code) with only one command word.

• If the value of channel select register is “0xxxxx111”, the protocol performs a burst of operations starting from address 0; the number

of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel

1. This command is used to fully write the CRAMs of channel 1, 2 and 3 (with exactly the same code) with only one command word.

• If the value of channel select register is “1xxxxx000”, the protocol performs a burst of operations starting from address 0; the number

of operations is 192. This command is used to fully write the DRAMs of all three channels with only one command word.

• For all the other values of channel select register, the command is neglected.

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Sending a control word with the parameter number set to zero and the parameter offset greater than zero is not allowed. This leads to

data corruption in the registers or DRAM.

For example, to initialize the values of 24 LS pre-driver diagnosis configuration registers, it is necessary to:

• Select the communication interface as the target: this is done by writing the value 0100h at the address 3FFh. First send the data

“0_1111111111_00001” (7FE1h) via the SPI. As the ASIC is in idle conditions, it uses this data as a command word. In particular,

this specific command word of the example means: write (because of the initial 0) starting from address 3FFh (the ten bits

immediately after) 1 word (the five bits at the end). The next data to send is 0100h. The SPI block is expecting a write to 3FFh, so

write 0100h in the location 3FFh. As the number of word expected is arrived, the SPI block returns to the idle state;

• Write the value of the 24 registers: the SPI block is waiting for a command word. The correct data to send is “0_0111000000_11000”.

This means write (0) starting form address 1C0h (0111000000) 24 words (11000). The next 24 words are written to the

communication interface registers.

8.2.3.2

Mode B

CSB

MOSI

(read)

control word

MISO

(read)

check byte

error bits

data 1

data n+1

MOSI

(write)

control word

MISO

(write)

check byte

error bits

check byte

error bits

check byte

error bits

Figure 31. SPI protocol mode B CSB, MOSI, and MISO

For the duration of a burst of data, the SPI chip select must be asserted, even between data transfers. The first word after the chip select

assertion is considered to be the command word and the following words are the data. If the number parameter is not zero, the SPI

interface goes into error state if:

• the chip select is de-asserted and the number of words transferred is lower than the number parameters required by the command

word,

• the number of word transferred is equal to the number parameter + 1.

If the number parameter is zero, there is no check on the number of words transferred, and the length of the burst is decided only by the

assertion of SPI chip select. It is not recommended to read from any register which is “reset on read” nor from any register which is located

one address before such a register using a mode B burst with the number parameter set to zero. This may lead to the effect of a register

reset, which is not a read out via the SPI. This problem does not occur if the number parameter is equal to the number of data words

transmitted.

Note: If one additional data word is sent it is detected, but also written. For example:

• SPI write access mode B, parameter number set to 3 and 3 data words written with no error

• SPI write access mode B, parameter number set to 3 and 4 data words written with a SPI frame error after the 4th data word, but the

4th data word is written to RAM or the register.

• SPI write access mode B, parameter number set to 3 and 6 data words written with a SPI frame error after the 4th data word, but the

4th data word is written to RAM or the register. 5th and 6th data words are not written to memory.

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8.3

SPI address map

Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

0

...

“0…001” /

ch_sel_1(1)

Code RAM of

channel 1

yes

Code RAM of channel 1, See CRAM on page 73

3FE

0

“0…010”/

ch_sel_2(1)

Code RAM of

channel 2

...

yes

no

Code RAM of channel 2, See CRAM on page 73

Code RAM of channel 3, See CRAM on page 73

Data RAM of channel 1, See DRAM on page 73

3FE

0

“0…100”/

ch_sel_3(1)

Code RAM of

channel 3

...

3FE

0

...

2F

30

...

“1…000” /

ch_sel_1(0)

Data RAM of

channel 1

yes Data RAM of channel 1, private area, See DRAM on page 73

3F

40

...

no

Data RAM of channel 2, See DRAM on page 73

6F

70

...

“1…000” /

ch_sel_2(0)

Data RAM of

channel 2

yes Data RAM of channel 2, private area, See DRAM on page 73

7F

80

...

no

Data RAM of channel 3, See DRAM on page 73

9F

A0

...

“1…000” /

ch_sel_3(0)

Data RAM of

channel 3

yes Data RAM of channel 3, private area, See DRAM on page 73

BF

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Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

C0

…

64 free address

FF

100

101

102

103

104

105

106

107

108

109

10A

10B

10C

10D

10E

10F

110

111

112

113

114

...

yes

no

flash_enable of channel 1

ctrl_reg_uc0 of channel 1

Table 58

Table 59

Table 60

Table 61

Table 62

Table 63

Table 64

Table 65

Table 66

no

ctrl_reg_uc1 of channel 1

yes

-

start_config_reg_part 1 of channel 1

start_config_reg_part 2 of channel 1

status_reg_uc0 of channel 1

status_reg_uc1 of channel 1

code_width of channel 1

-

yes

no

checksum_h of channel 1

Configuration

registers of

channel 1

checksum_l of channel 1

Table 67

Table 68

Table 69

Table 70

Table 71

Table 72

Table 73

Table 74

Table 75

Table 77

“1…000” /

ch_sel_1(2)

uc0_entry_point of channel 1

uc1_entry_point of channel 1

diag_routine_addr of channel 1

driver_disabled_routine_addr of channel 1

sw_interrupt_routine_addr of channel 1

uc0_irq_status of channel 1

uc1_irq_status of channel 1

counter34_prescaler of channel 1

dac_rxtx_cr_config of channel 1

unlock_word of channel 1

no

yes

no

12 free addresses

11F

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80

Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

120

121

122

123

124

125

126

127

128

129

12A

12B

12C

12D

12E

12F

130

131

132

133

134

...

yes

no

flash_enable of channel 2

ctrl_reg_uc0 of channel 2

Table 58

Table 60

Table 61

Table 62

Table 63

Table 64

Table 65

Table 66

Table 67

no

ctrl_reg_uc1 of channel 2

yes

-

start_config_reg_part1 of channel 2

start_config_reg_part2 of channel 2

status_reg_uc0 of channel 2

status_reg_uc1 of channel 2

code_width of channel 2

-

yes

no

checksum_h of channel 2

checksum_l of channel 2

uc0_entry_point of channel 2

uc1_entry_point of channel 2

diag_routine_addr of channel 2

driver_disabled_routine_addr of channel 2

sw_interrupt_routine_addr of channel 2

uc0_irq_status of channel 2

uc1_irq_status of channel 2

counter34_prescaler of channel 2

dac_rxtx_cr_config of channel 2

unlock_word of channel 2

Table 68

Configuration

registers of

channel 2

“1…000” /

ch_sel_2(2)

Table 69

Table 70

Table 71

Table 72

Table 73

Table 74

Table 75

Table 77

no

yes

no

12 free addresses

13F

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Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

140

141

142

143

144

145

146

147

148

149

14A

14B

14C

14D

14E

14F

150

151

152

153

yes

no

flash_enable of channel 3

ctrl_reg_uc0 of channel 3

Table 58

Table 60

Table 61

Table 62

Table 63

Table 64

Table 65

Table 66

no

ctrl_reg_uc1 of channel 3

yes

-

start_config_reg_part1 of channel 3

start_config_reg_part2 of channel 3

status_reg_uc0 of channel 3

status_reg_uc1 of channel 3

code_width of channel 3

-

yes

no

checksum_h of channel 3

Configuration

registers of

channel 3

checksum_l of channel 3

Table 67

Table 68

Table 69

Table 70

Table 71

Table 72

Table 73

Table 74

Table 75

Table 77

“1…000” /

ch_sel_3(2)

uc0_entry_point of channel 3

uc1_entry_point of channel 3

diag_routine_addr of channel 3

driver_disabled_routine_addr of channel 3

sw_interrupt_routine_addr of channel 3

uc0_irq_status of channel 3

uc1_irq_status of channel 3

counter34_prescaler of channel 3

dac_rxtx_cr_config of channel 3

unlock_word of channel 3

no

yes

no

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Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

154

155

156

157

158

159

15A

15B

15C

15D

15E

15F

160

161

162

163

164

165

166

167

168

169

16A

16B

16C

16D

16E

16F

170

171

yes

no

fbk_sens_uc0_ch1_part1

fbk_sens_uc0_ch1_part2

fbk_sens_uc1_ch1_part1

fbk_sens_uc1_ch1_part2

fbk_sens_uc0_ch2_part1

fbk_sens_uc0_ch2_part2

fbk_sens_uc1_ch2_part1

fbk_sens_uc1_ch2_part2

fbk_sens_uc0_ch3_part1

fbk_sens_uc0_ch3_part2

fbk_sens_uc1_ch3_part1

fbk_sens_uc1_ch3_part2

out_acc_uc0_ch1

Table 81

Table 82

Table 81

Table 82

Table 81

Table 82

Table 81

Table 82

Table 81

Table 82

Table 81

Table 82

Table 83

out_acc_uc1_ch1

out_acc_uc0_ch2

Table 83

“1…000” /

ext_sel_io

IO configuration

registers

out_acc_uc1_ch2

Table 83

out_acc_uc0_ch3

Table 83

Table 85

Table 86

Table 87

Table 88

Table 90

Table 91

Table 92

Table 93

Table 94

Table 96

Table 97

Table 99

out_acc_uc1_ch3

cur_block_access_part1

cur_block_access_part2

cur_block_access_part3

fw_link

fw_ext_req

vds_thresholds_hs_part1

vds_thresholds_hs_part2

vsrc_thresholds_hs_part1

vsrc_thresholds_hs_part2

vds_thresholds_ls_part1

vds_thresholds_ls_part2

hs_slewrate

no

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Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

172

173

174

175

176

177

178

179

17A

17B

17C

17D

17E

17F

180

181

182

183

184

185

186

187

188

189

18A

18B

18C

18D

18E

18F

no

yes

no

yes

no

-

ls_slewrate_part1

ls_slewrate_part2

offset_compensation12

offset_compensation34

offset_compensation56

adc12_result

Table 100

Table 101

Table 102

Table 103

Table 104

Table 105

Table 106

Table 107

Table 108

Table 109

Table 110

Table 111

Table 112

Table 113

adc34_result

adc56_result

current_filter12

current_filter34

current_filter5l5h

current_filter6l6h

current_filter5neg6neg

boost_dac

boost_dac_access

boost_filter

Table 114

“1…000” /

ext_sel_io

IO configuration

registers

Table 115

vds7_dcdc_config

vds8_dcdc_config

batt_result

Table 116

Table 118

Table 119

Table 120

Table 121

Table 122

Table 123

Table 124

Table 125

Table 126

Table 127

Table 128

Table 131

no

-

dac12_value

dac34_value

dac5l5h_value

dac5neg_value

dac6l6h_value

dac6neg_value

hs_bias_config

ls_bias_config

bootstrap_charged

bootstrap_timer

hs1_ls_act

-

yes

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Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

190

191

192

193

194

195

196

197

198

199

19A

…

yes

no

hs2_ls_act

hs3_ls_act

Table 131

hs4_ls_act

hs5_ls_act

hs6_ls_act

hs7_ls_act

“1…000” /

ext_sel_io

IO configuration

Table 132

dac_settling_time

oa_out1_config

oa_out2_config

oa_out3_config

registers

Table 133

Table 134

Table 135

no

6 free addresses

19F

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NXP Semiconductors

Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

1A0

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

1A9

1AA

1AB

1AC

1AD

1AE

1AF

1B0

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

-

yes

no

yes

no

-

Clock_Prescaler

Flags_Direction

Flags_Polarity

Flags_source

Table 136

Table 138

Table 141

Table 145

Table 146

Table 147

Table 148

Table 151

Table 152

Table 153

Table 154

Table 155

Table 156

Table 157

Offset_compensation_prescaler

Driver_Config_part1

Driver_Config_part2

PLL_config

Backup_Clock_Status

SPI_config

Trace_start

Trace_stop

Trace_config

Device_lock

Main

configuration

registers

Reset_behavior

Device_unlock

Global_reset_code_part1

Global_reset_code_part2

Driver_Status

SPI_error_code

Interrupt_register_part1

Interrupt_register_part2

Device_Identifier

Reset_source

----

Table 158

Table 159

Table 160

Table 161

Table 162

Table 163

Table 164

Table 165

Table 167

Table 168

“1000” /

ext_sel_mcr

-

no

-

no

-

----

1BC

1BD

1BE

1BF

----

no

BIST_interface

----

Table 170

----

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Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

1C0

1C1

1C2

1C3

1C4

1C5

1C6

1C7

1C8

1C9

1CA

1CB

1CC

1CD

1CE

1CF

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1D9

1DA

1DB

1DC

1DD

1DE

1DF

1E0

1E1

yes

ls1_diag_config1

ls1_diag_config2

ls1_output_config

ls2_diag_config1

ls2_diag_config2

ls2_output_config

ls3_diag_config1

ls3_diag_config2

ls3_output_config

ls4_diag_config1

ls4_diag_config2

ls4_output_config

ls5_diag_config1

ls5_diag_config2

ls5_output_config

ls6_diag_config1

ls6_diag_config2

ls6_output_config

ls7_diag_config1

ls7_diag_config2

ls7_output_config

ls8_diag_config1

ls8_diag_config2

ls8_output_config

hs1_diag_config1

hs1_diag_config2

hs1_output_config

hs2_diag_config1

hs2_diag_config2

hs2_output_config

hs3_diag_config1

hs3_diag_config2

hs3_output_config

hs4_diag_config1

Table 172

Table 173

Table 174

Table 172

Table 173

Table 174

Table 172

Table 173

Table 174

Table 172

Table 173

Table 174

Table 172

Table 173

Table 174

Table 172

Table 173

diagnostics

configuration

registers

“1…000” /

ext_sel_diag

Table 174

Table 172

Table 173

Table 175

Table 172

Table 173

Table 175

Table 176

Table 177

Table 178

Table 176

Table 177

Table 178

Table 176

Table 177

Table 178

Table 176

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Table 55. MC33PT2000 address map

Selection register

[8:0]/chip select

Address

(Hex)

Lock

Description

Table number Area addressed

1E3

1E4

1E5

1E6

1E7

1E8

1E9

1EA

1EB

1EC

1ED

1EE

1EF

1F0

1F1

1F2

1F3

1F4

1F5

1F6

1F7

1F8

1F9

1FA

1FB

1FC

1FD

1FE

1FF

200

-

yes

hs4_output_config

hs5_diag_config1

hs5_diag_config2

hs5_output_config

hs6_diag_config1

hs6_diag_config2

hs6_output_config

hs7_diag_config1

hs7_diag_config2

hs7_output_config

err_uc0ch1_part1

err_uc0ch1_part2

err_uc0ch1_part3

err_uc1ch1_part1

err_uc1ch1_part2

err_uc1ch1_part3

err_uc0ch2_part1

err_uc0ch2_part2

err_uc0ch2_part3

err_uc1ch2_part1

err_uc1ch2_part2

err_uc1ch2_part3

err_uc0ch3_part1

err_uc0ch3_part2

err_uc0ch3_part3

err_uc1ch3_part1

err_uc1ch3_part2

err_uc1ch3_part3

diagnostics_option

Table 178

Table 176

Table 177

Table 178

Table 176

Table 177

Table 178

Table 176

Table 177

Table 178

Table 179

Table 180

Table 181

Table 179

Table 180

yes

-

diagnostics

configuration

registers

-

Table 181

Table 179

Table 180

Table 181

Table 179

Table 180

Table 181

Table 179

Table 180

Table 181

Table 179

Table 180

Table 181

Table 182

“1…000” /

ext_sel_diag

-

yes

511 free addresses

Selection_register

3FE

3FF

N/A

no

Table 56 Selection Register

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8.3.1

Selection register (3FFh)

The selection register is a 4-bit register aimed to select, before starting the read/write operations toward a given address, which internal

code RAM is accessed or to select all the other addresses (including the 3 data RAMs and all the registers).

Table 56. selection_register (3FFh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

comm.

page

sel

CRAM_ CRAM_ CRAM_

ch3_sel ch2_sel ch1_sel

Name

Reserved

R/W

Lock

-

r/w

no

0

-

r/w

no

0

r/w

no

0

r/w

no

0

-

Reset

0000000

00000

Table 57 details the meaning of the 4 bits in this register. Not all possible values are allowed for this register.

Table 57. Selection register

Selection register

comm. page sel

Selection register

CRAM chx

Element addressed

‘0’

‘1’

“000”

“001”

“010”

“100”

“011”

“101”

“110”

“111”

d.c.

Nothing selected. Further SPI operation, except for the one concerning this register is ignored.

Channel 1 Code RAM selected

Channel 2 Code RAM selected

Channel 3 Code RAM selected

Write operation affects the Code RAM of channel 1 and 2. Read operation is not possible.

Write operation affects the Code RAM of channel 1 and 3. Read operation is not possible.

Write operation affects the Code RAM of channel 2 and 3. Read operation is not possible.

Write operation affects the all three channel’s Code RAM. Read operation is not possible.

Common page selected. The lower three bits are ignored. “100000000” is written to the register.

This selection register is accessible at address 3FFh and is the only register accessed anyway from the SPI, whatever the value of the

selection register. This means address 3FFh can only be used for this purpose, even if any of the code RAMs is selected, so each 1024x16

code RAM in the MC33PT2000 can actually only store 1023 data. Note that 2 or 3 code RAMs can be written in parallel during normal

mode.

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8.3.2

Configuration register

Flash_enable register

8.3.2.1

Table 58. Flash_enable (100h, 120h, 140h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

pre

flash_en

able

checksum flash_en

en_dual_

uc

chksum_irq chksum_f

Name

R/W

Reserved

_disable

able

_en

ailure

-

r/w

r

r/w

-

r/w

r

yes, by

pre flash

enable

yes, by

pre flash

enable

yes, by

itself

Lock

Reset

-

yes

0

-

000000000

0

This is a 6 bit configuration register which includes the following parameters:

• Checksum_disable. If set, this bit disables the effects of a failed checksum, so microcore execution is not stopped

• Pre_flash_enable. This bit “freezes” the CRAM so the micro-controller cannot further modify the configuration code unless a specific

unlock code is written into register unlock_reg. It enables the signature_unit (See Signature unit on page 72)

• Flash_enable. This bit enables the microcores. It can only be set by the signature_unit after a successful checksum calculation

• En_dual_microcore. This bit is used to enable the dual microcore mode. Note that when using dual microcore ck_per (refer to

Table 136, Clock_Prescaler (1A0h)) set to lower than three, there are some limitations regarding C/DRAM access.

• Checksum_irq_en. If this bit is '1', an interrupt on the_irq_device pin is done in case a CRAM corruption detected

• Checksum_failure. This bit sets to '1' when a mismatch is found between the calculated checksum and the checksum code stored in

the appropriate registers (refer to Table 66, checksum_h (108h, 128h, 148h) and Table 67, checksum_l (109h, 129h, 149h)). This bit

sets when a checksum calculation fails, even if the checksum is disabled. This bit resets each time the pre_flash_enable bit sets to '1'

to lock the memory.

8.3.2.2

Control register microcore0

Table 59. Ctrl_reg_uc0 (101h, 121h, 141h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Control_register_Shared

Control_register

R/W

Lock

configurable r or r/w

r/w

no

Reset

00000000

• Control_register: these 8 bits can be used to control the execution of the micro-program of uc0, providing control bits which can be read

by the micro-program. For instance one bit could be used to enable/disable recharge pulses on the channel or to re-enable the actuation

after an error condition has been detected.

• Control_register_shared: according to a configuration bit stored in the “control_register_split” register (refer to Table 77,

Dac_rxtx_cr_config (112h, 132h, 152h)), these 8 bits can be used either as control (like the other 8 bits) or like status (like the status

register, refer to Table 63, status_reg_uc0 (105h, 125h, 145h)and Table 64, status_reg_uc1 (106h, 126h, 146h)). In this case, they can

only be read through the SPI, while they can be set by the “set control register bit” instruction.

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8.3.2.3

Control register microcore1

Table 60. ctrl_reg_uc1 (102h, 122h, 142h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Control_register_Shared

Control_register

R/W

Lock

configurable r or r/w

r/w

no

Reset

00000000

• Control register: these 8 bits can be used to control the execution of the micro-program of uc0, providing control bits which can be read

by the micro-program itself. For instance one bit could be used to enable/disable recharge pulses on the channel or to re-enable the

actuation after an error condition has been detected.

• Control register shared: according to a configuration bit stored in the “control register split” register (refer to Table 77,

Dac_rxtx_cr_config (112h, 132h, 152h)), these 8 bits can be used either as control (like the other 8 bits) or like status (like the status

register, refer to Table 63, status_reg_uc0 (105h, 125h, 145h)and Table 64, status_reg_uc1 (106h, 126h, 146h)). In this case they can

only be read through the SPI, while they can be set by the “set control register bit” instruction.

8.3.2.4

Start configuration register

These are two configuration registers where it is possible to configure the sensitivity of each microcore to the start signals. It is also

possible to enable a smart start mode for each microcore (reference Programming Guide and Instruction Set).

Table 61. start_config_reg_Part1 (103h, 123h, 143h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

start8_ start7_ start6_ start5_ start4_ start3_ start2_ start1_ start8_ start7_ start6_ start5_ start4_ start3_ start2_ start1_

Name sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u

c1

r/w

yes

0

c1

r/w

yes

0

c1

r/w

yes

0

c1

r/w

yes

0

c1

r/w

yes

0

c1

r/w

yes

0

c1

r/w

yes

0

c1

r/w

yes

0

c0

r/w

yes

0

c0

r/w

yes

0

c0

r/w

yes

0

c0

r/w

yes

0

c0

r/w

yes

0

c0

r/w

yes

0

c0

r/w

yes

0

c0

r/w

yes

0

R/W

Lock

Reset

Table 62. start_config_reg_Part2 (104h, 124h, 144h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

smart_ smart_

start_u start_u

Name

reserved

c1

r/w

yes

0

c0

r/w

yes

0

R/W

Lock

-

Reset

00000000

• start1_sens_uc0: This bit is '1' if the uc0_is sensitive to start1, '0' otherwise

• start2_sens_uc0: This bit is '1' if the uc0_is sensitive to start2, '0' otherwise

• start3_sens_uc0: This bit is '1' if the uc0_is sensitive to start3, '0' otherwise

• start4_sens_uc0: This bit is '1' if the uc0_is sensitive to start4, '0' otherwise

• start5_sens_uc0: This bit is '1' if the uc0_is sensitive to start5, '0' otherwise

• start6_sens_uc0: This bit is '1' if the uc0_is sensitive to start6, '0' otherwise

• start7_sens_uc0: This bit is '1' if the uc0_is sensitive to start7, '0' otherwise

• start8_sens_uc0: This bit is '1' if the uc0_is sensitive to start8, '0' otherwise

• start1_sens_uc1: This bit is '1' if the uc1_is sensitive to start1, '0' otherwise

• start2_sens_uc1: This bit is '1' if the uc1_is sensitive to start2, '0' otherwise

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• start3_sens_uc1: This bit is '1' if the uc1_is sensitive to start3, '0' otherwise

• start4_sens_uc1: This bit is '1' if the uc1_is sensitive to start4, '0' otherwise

• start5_sens_uc1: This bit is '1' if the uc1_is sensitive to start5, '0' otherwise

• start6_sens_uc1: This bit is '1' if the uc1_is sensitive to start6, '0' otherwise

• start7_sens_uc1: This bit is '1' if the uc1_is sensitive to start7, '0' otherwise

• start8_sens_uc1: This bit is '1' if the uc1_is sensitive to start8, '0' otherwise

• smart_start_uc0: This bit is '1' if the smart start mode is enabled for uc0, '0' otherwise (reference Programming Guide and Instruction

Set).

• smart_start_uc1: This bit is '1' if the smart start mode is enabled for uc1, '0' otherwise (reference Programming Guide and Instruction

Set).

8.3.2.5

Status register microcore0

This 16-bit register is a read-only register and only provides information about the uc0_status to the external microcontroller. The register

can be used to exchange application dependent information (status bits, for instance regarding the execution phase of the micro-program,

diagnostics results) between the microcore and the main microcontroller according to the way the micro-program is designed. The

registers can be configured so they reset after a SPI read operation to the register (see Table 158, Reset_Behavior (1AEh)).

Table 63. status_reg_uc0 (105h, 125h, 145h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

status_register

R/W

Lock

r

-

Reset

on read

configurable

Reset

0000000000000000

8.3.2.6

Status register microcore1

This 16-bit register is a read-only register and only provides information about the uc1_status to the external microcontroller. The register

can be used to exchange application dependent information (status bits, for instance regarding the execution phase of the micro-program)

between the microcore and the main microcontroller according to the way the micro-program is designed. The registers can be configured

so they reset after a SPI read operation to the register (see Table 158, Reset_Behavior (1AEh)).

Table 64. status_reg_uc1 (106h, 126h, 146h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

status_register

R/W

Lock

r

-

Reset

on read

configurable

Reset

0000000000000000

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8.3.2.7

Code_width register

This 10-bit register provides the length of the section of the CRAM used to store the code. This information has two uses:

• It is used by the SPI interface to determine the length of the special burst transfer used for CRAM initialization (refer to See SPI protocol

on page 77).

• The signature unit computes the checksum only of the used part of the CRAM. This signature unit only works if the code with is bigger

than 3 lines, if it is not the case signature unit has to be disabled (refer to Table 58, Flash_enable (100h, 120h, 140h))

This allows the application not to write all the CRAM, but only the part which is really used.

Table 65. code_width (107h, 127h, 147h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

code width

R/W

Lock

-

r/w

yes

-

Reset

000000

0000000000

8.3.2.8

Checksum high register

This 16-bit register contains the 16 MSBs of the checksum of the code contained in the CRAM. The signature_unit (refer to See Signature

unit on page 72) compares the result of its computation to this register and checksum_l.

Table 66. checksum_h (108h, 128h, 148h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

checksum_high

R/W

Lock

r/w

yes

Reset

0000000000000000

8.3.2.9

Checksum low register

This 16-bit register contains the 16 LSBs of the checksum of the code contained in the CRAM. The signature_unit (refer to section See

Signature unit on page 72) compares the result of its computation to checksum_h and this register.

Table 67. checksum_l (109h, 129h, 149h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Checksum_low

R/W

Lock

r/w

yes

Reset

0000000000000000

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8.3.2.10 Microcore0 entry point address register

This 10-bit register contains the CRAM address of the first instruction to be executed by microcontroller0.

Table 68. uc0_entry_point (10Ah, 12Ah, 14Ah)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

entry_point_address

R/W

Lock

-

r/w

yes

-

Reset

000000

0000001000

8.3.2.11 Microcore1 entry point address register

This 10-bit register contains the CRAM address of the first instruction to be executed by uc1. This is done to allow the two microcores to

execute completely independent microcodes (when the two entry point differ), while still having the capability to execute the same program

in case the two entry points coincide.

Table 69. uc1_entry_point (10Bh, 12Bh, 14Bh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

entry_point_address

R/W

Lock

-

r/w

yes

-

Reset

000000

0000001000

8.3.2.12 Diagnostics interrupt routine address register

Table 70. Diag_routine_addr (10Ch, 12Ch, 14Ch)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

diagnostics_routine_address_uc1

diagnostics_routine_address_uc0

R/W

Lock

-

r/w

yes

r/w

yes

Reset

0000

000000

• diagnostics_routine_address_uc0. The complete address is “0000” & “diagnostics routine address uc0”: this is the CRAM address of

the first instruction of the interrupt routine to be executed by uc0_when an automatic diagnostics exception is raised.

• diagnostics_routine_address_uc1. The complete address is “0000” & “diagnostics routine address uc1”: this is the CRAM address of

the first instruction of the interrupt routine to be executed by uc1_when an automatic diagnostics exception is raised.

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8.3.2.13 Driver disabled interrupt routine address register

Table 71. Driver_disable_routine_addr (10Dh, 12Dh, 14Dh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

driver_disable_routine_address_uc1

driver_disable_routine_address_uc0

R/W

Lock

-

r/w

yes

r/w

yes

Reset

0000

000000

• driver_disable_routine_address_uc0. The complete address is “0000” & “driver disable routine address uc0”: This is the CRAM address

of the first instruction of the interrupt routine to be executed by uc0_when a disabled driver or cksys missing exception is raised.

• driver_disable_routine_address_uc1. The complete address is “0000” & “driver disable routine address uc1”: This is the CRAM address

of the first instruction of the interrupt routine to be executed by uc1_when a disabled driver or cksys missing exception is raised.

The following events can trigger this interrupt (all configurable):

• DrvEn pin going low

• UV_VCCP

• UV_VCC5

• UV_VBOOST

• cksys missing

• Overtemperature

8.3.2.14 Software interrupt routine address register

Table 72. Sw_interrupt_routine_addr (10Eh, 12Eh, 14Eh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

sw_irq_fall sw_irq_risi sw_irq_falli sw_irq_risi

Name

ing_edge_ ng_edge_ ng_edge_ ng_edge_ software_interrupt_routine_address_uc1

start_uc1 start_uc1 start_uc0 start_uc0

software_interrupt_routine_address_uc0

R/W

Lock

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

r/w

yes

Reset

000000

• software_interrupt_routine_address_uc0. The complete address is “0000” & “software interrupt routine address uc0”: This is the CRAM

address of the first instruction of the interrupt routine to be executed by uc0_when a software interrupt is requested.

• software_interrupt_routine_address_uc1. The complete address is “0000” & “software interrupt routine address uc1”: This is the CRAM

address of the first instruction of the interrupt routine to be executed by uc1_when a software interrupt is requested.

• sw_irq_rising_edge_start_uc0. When this bit is set to '1', the software interrupt 0 is generated towards microcore 0 if a rising edge is

detected on the gen_start signal. When set to '0', no software interrupt is required.

• sw_irq_falling_edge_start_uc0. When this bit is set to '1', the software interrupt 0 is generated towards microcore 0 if a falling edge is

detected on the gen_start signal. When set to '0', no software interrupt is required.

• sw_irq_rising_edge_start_uc1. When this bit is set to '1', the software interrupt 1 is generated towards microcore 1 if a rising edge is

detected on the gen_start signal. When set to '0', no software interrupt is required.

• sw_irq_falling_edge_start_uc1. When this bit is set to '1', the software interrupt 1 is generated towards microcore 1 if a falling edge is

detected on the gen_start signal. When set to '0', no software interrupt is required.

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8.3.2.15 Microcore0 interrupt status register

This 13-bit register stores the information about the interrupt currently being served by uc0. If no interrupt is being served, this register is

cleared.

Table 73. uc0_irq_status (10Fh, 12Fh, 14Fh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

interrupt_ro

Name

Reserved utine_in_pro

gress

irq_source

iret_address

R/W

Lock

-

r

no

0

no

Reset

00

000

1111111111

• Interrupt_routine_in_progress: '1' when an interrupt is being served.

• Irq_source:

• “000”: serving start rising edge interrupt

• “001”: serving driver disable interrupt request

• “010”: serving automatic diagnostics interrupt request

• “011”: serving start falling edge interrupt

• “100”: serving software interrupt request 0

• “101”: serving software interrupt request 1

• “110”: serving software interrupt request 2

• “111”: serving software interrupt request 3

• Iret_address: the value of the return address after the interrupt is served.

The return address after an interrupt is always the address where the code execution would continue if no interrupt had occurred. For wait

and conditional jump instructions, the address is defined considering the status of the feedback at the moment the interrupt request took

place.

8.3.2.16 Microcore1 interrupt status register

This 13-bit register stores the information about the interrupt currently being served by uc1. If no interrupt is being served, this register is

cleared.

Table 74. uc1_irq_status (110h, 130h, 150h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

interrupt_ro

Name

Reserved utine_in_pro

gress

irq_source

iret_address

R/W

Lock

-

r

no

0

no

Reset

00

000

1111111111

• Interrupt_routine_in_progress: '1' when an interrupt is being served.

• Irq_source:

• “000”: serving start rising edge interrupt

• “001”: serving driver disable interrupt request

• “010”: serving automatic diagnostics interrupt request

• “011”: serving start falling edge interrupt

• “100”: serving software interrupt request 0

• “101”: serving software interrupt request 1

• “110”: serving software interrupt request 2

• “111”: serving software interrupt request 3

• Iret_address: the value of the return address after the interrupt is served.

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The return address after an interrupt is always the address where the code execution would continue if no interrupt had occurred. For wait

and conditional jump instructions, the address is defined considering the status of the feedback at the moment the interrupt request took

place.

8.3.2.17 Counter 3 and 4 prescaler register

Table 75. Counter_34_prescaler (111h, 131h, 151h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

counter_4_per_uc1

counter_3_per_uc1

counter_4_per_uc0

counter_3_per_uc0

R/W

Lock

r/w

yes

r/w

yes

r/w

yes

r/w

yes

Reset

0000

The counter 3 and 4 of both microcores uses a clock whose period can be programmed to be a multiple of the ck period. Note that the

actual ratio is according to Table 76, Counter prescaler.

Example:

cksys set to 24 MHz (default) with ck_per = 3, resulting with ck at 6.0 MHz

counter_4_per_uc1 = 0001b -> prescaler of 3

counter4_freq = ck /counter_Y_per_ucx = 6.0 MHz /3 = 2.0 MHz

Table 76. Counter prescaler

counter_3/4_per_ucx

Prescaler

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

3

4

5

6

7

8

9

10

11

12

14

16

32

64

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8.3.2.18 DAC Rxtx configuration register

Each microcore can only access four out of six current measurement channel DACs via the internal address map. In addition, either the

two special DACs of current measurement channel five or six can be used. The two DACs linked to their own channel can always be

addressed via sssc and ossc. In addition, the two DACs of one other channel can be addressed via the ssoc and osoc parameter. It can

be decided by register bits or microcode instruction slocdac for each microcore, which of the two other channels (next channel or previous

channel), DACs are accessible and if DACs H and NEG of channel five or six are accessible.

Only one microcore can be addressed at the same time in the channel communication register (rxtx register in the memory map). This

can be decided by register bits or microcode instruction sl56dac.

Table 77. Dac_rxtx_cr_config (112h, 132h, 152h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

oc_dac oc_dac CR_sh CR_sh

_sel_uc _sel_uc ared_u ared_u

dac56_ dac56_

sel_uc1 sel_uc0

Name

Reserved

rxtx_link_sel_uc1

rxtx_link_sel_uc0

Reserved

1

r/w

no

0

r/w

no

0

c1

r/w

yes

0

c0

r/w

yes

0

R/W

Lock

-

r/w

no

r/w

no

-

r/w

no

0

r/w

no

0

Reset

00

000

00

• CR_shared_uc0: if set to '0', all 16 of the bits of the control register uc0_are used as control bits. If set to '1', the 8 MSBs of the control

register (control register shared) are used as status bits.

• CR_shared_uc1: if set to '0', all 16 of the bits of the control register uc1_are used as control bits. If set to '1', the 8 MSBs of the control

register (control register shared) are used as status bits.

• oc_dac_sel_uc0: selects the other dac for microcore 0.

• ‘0', channel 1: ssoc refers to dac3, osoc refers to dac4 (next channel = 2)

• ‘0', channel 2: ssoc refers to dac5, osoc refers to dac6 (next channel = 3)

• ‘0', channel 3: ssoc refers to dac1, osoc refers to dac2 (next channel = 1)

• ‘1', channel 1: ssoc refers to dac5, osoc refers to dac6 (prev. channel = 3)

• ‘1', channel 2: ssoc refers to dac1, osoc refers to dac2 (prev. channel = 1)

• ‘1', channel 3: ssoc refers to dac3, osoc refers to dac4 (prev. channel = 2)

• oc_dac_sel_uc1: selects the other dac for microcore 1.

• '0', channel 1: ssoc refers to dac4, osoc refers to dac3 (next channel = 2)

• '0', channel 2: ssoc refers to dac6, osoc refers to dac5 (next channel = 3)

• '0', channel 3: ssoc refers to dac2, osoc refers to dac1 (next channel = 1)

• '1', channel 1: ssoc refers to dac6, osoc refers to dac5 (prev. channel = 3)

• '1', channel 2: ssoc refers to dac2, osoc refers to dac1 (prev. channel = 1)

• '1', channel 3: ssoc refers to dac4, osoc refers to dac3 (prev. channel = 2)

• dac56_sel_ucX: selects the dac5/6 for microcore X.

• '0': dac56h56n refers to dac5

• '1': dac56h56n refers to dac6

Table 78. Other dac configuration

oc_dac_sel_ucX =’0’ (next channel)

oc_dac_sel_ucX =’1’ (previous channel)

Microcore

dac sssc dac ossc

dac ssoc

dac3

dac osoc

dac4

dac ssoc

dac5

dac osoc

dac6

uc0, channel 1

uc1, channel 1

uc0, channel 2

uc1, channel 2

uc0, channel 3

uc1, channel 3

dac1

dac2

dac3

dac4

dac5

dac6

dac2

dac1

dac4

dac3

dac6

dac5

dac4

dac3

dac6

dac5

dac6

dac1

dac2

dac6

dac5

dac2

dac1

dac2

dac3

dac4

dac2

dac1

dac4

dac3

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• rxtx_link_sel_ucX: selects the target for the channel communication register (rxtx) in the internal memory map for microcore X (can also

be done using the 'stcrt instruction').

• '0': same uc same channel (sssc)

• '1': other uc same channel (ossc)

• '2': same uc next channel (ssnc)

• '3': other uc next channel (osnc)

• '4': sum of highest 4 bits of all rxtx registers (sumh)

• '5': sum of second highest 4 bits of all rxtx registers (suml)

• '6': same uc previous channel (sspc)

• '7': other uc previous channel (ospc)

Table 79. Rxtx register link configuration

Microcore

sssc

ossc

ssnc

osnc

sspc

ospc

uc0, channel 1

uc1, channel 1

uc0, channel 2

uc1, channel 2

uc0, channel 3

uc1, channel 3

uc0Ch1

uc1Ch1

uc0Ch2

uc1Ch2

uc0Ch3

uc1Ch3

uc1Ch1

uc0Ch1

uc1Ch2

uc0Ch2

uc1Ch3

uc0Ch3

uc0Ch2

uc1Ch2

uc0Ch3

uc1Ch3

uc0Ch1

uc1Ch1

uc1Ch2

uc0Ch2

uc1Ch3

uc0Ch3

uc1Ch1

uc0Ch1

uc0Ch3

uc1Ch3

uc0Ch1

uc1Ch1

uc0Ch2

uc1Ch2

uc1Ch3

uc0Ch3

uc1Ch1

uc0Ch1

uc1Ch2

uc0Ch2

8.3.2.19 Unlock word register

The actuation channel execution can be stopped by writing the unlock code at this SPI address. The unlock code is “1011111011101111”

(binary) or “BEEF” (hexadecimal). As this is not a register, no SPI read operations can be performed at this address.

Table 80. Unlock_word (113h, 133h, 153h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Unlock_word

R/W

Lock

w

no

-

Reset

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8.3.3

IO configuration registers

8.3.3.1

Feedback microcore sensitivities registers

These 12 registers (two for each microcore). Select the feedback to which each microcore is sensitive (e.g. configures if ucX chY is

sensitive to V_DSerrors on HS1).

Table 81. Fbk_sens_ucxchy_part1 (154h, 156h, 158h, 15Ah, 15Ch, 15Eh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Hs7_V Hs6_V Hs5_V Hs4_V Hs3_V Hs2_V Hs1_V

src_se src_se src_se src_se src_se src_se src_se

Hs7_V Hs6_V Hs5_V Hs4_V Hs3_V Hs2_V Hs1_V

sd_sen sd_sen sd_sen sd_sen sd_sen sd_sen sd_sen

Reserv

ed

Reserv

ed

Name

ns

r/w

yes

0

ns

r/w

yes

0

ns

r/w

yes

0

ns

r/w

yes

0

ns

r/w

yes

0

ns

r/w

yes

0

ns

r/w

yes

0

s

r/w

yes

0

s

r/w

yes

0

s

r/w

yes

0

s

r/w

yes

0

s

r/w

yes

0

s

r/w

yes

0

s

r/w

yes

0

R/W

Lock

-

Reset

0

Table 82. Fbk_sens_ucxchy_part2 (155h, 157h, 159h, 15Bh, 15Dh, 15Fh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Ls7_V

ds_sen

s

Ls1_V

ds_sen

s

Ls8_Vd

s_sens

Ls6_Vd Ls5_Vd Ls4_Vd Ls3_Vd Ls2_Vd

s_sens s_sens s_sens s_sens s_sens

Name

Reserved

R/W

Lock

-

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

-

Reset

00000000

8.3.3.2

Microcores output access registers

These six registers are designed to provide access rights to manage the control signals (output_command, V_DSthreshold, V_SRCthreshold,

fw auto, en_halt_x) of each output block to the required microcores. Each bit controls the access from one microcore to manage the control

signals of an output: if the value is set to 1, the microcore can drive the control signals (output_command, V_DSthreshold, V_SRCthreshold,

fw auto, en_halt_x), otherwise access is denied.

Table 83. Out_acc_ucx_chy (160h, 161h, 162h, 163h, 164h, 165h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Acc_uc Acc_uc Acc_uc Acc_uc Acc_uc Acc_uc Acc_uc Acc_uc

Name X_chY X_chY X_chY X_chY X_chY X_chY X_chY X_chY

Acc_uc Acc_uc Acc_uc Acc_uc Acc_uc Acc_uc Acc_uc

X_chY X_chY X_chY X_chY X_chY X_chY X_chY

Reserv

ed

_ls8

r/w

yes

0

_ls7

r/w

yes

0

_ls6

r/w

yes

0

_ls5

r/w

yes

0

_ls4

r/w

yes

0

_ls3

r/w

yes

0

_ls2

r/w

yes

0

_ls1

r/w

yes

0

_hs7

r/w

yes

0

_hs6

r/w

yes

0

_hs5

r/w

yes

0

_hs4

r/w

yes

0

_hs3

r/w

yes

0

_hs2

r/w

yes

0

_hs1

r/w

yes

0

R/W

Lock

-

Reset

0

The requests coming from the microcores are not continuous; instead the microcores perform a request each time a change to a control

signal (output_command, V_DSthreshold, V_SRCthreshold, fw auto, en_halt_x) is required. If multiple microcores have access to the same

output block, as a shared resource, this block is able to handle the collision: if more than one microcore wants to change one of the control

signals in the same ck cycle, priorities are used as defined in Table 84, Out_acc_ucxchy collision handling.

If one of the microcores which have access to a pre-driver not locked, the other microcore can switch on the pre-driver for only one ck

cycle maximum. After one ck cycle the output is switched off again, because this request comes from the disabled microcore. This is a

safety feature of the device. If requests to change a control signal are received from different microcores (assuming both have access

rights) in different ck cycles, all the requested changes are applied in sequence.

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Table 84. Out_acc_ucxchy collision handling

Microcore

uc0-ch1

uc1-ch1

uc0-ch2

uc1-ch2

uc0-ch3

uc1-ch3

Priority

1 (highest)

2

3

4

5

6 (lowest)

8.3.3.3

Microcore current sense access registers

This register is designed to provide access rights to manage the control signals (DAC value, Opamp gain, Ofscomp request) of each

current measure block to the required microcores. Each bit controls the access from one microcore to manage the control signals of a

current measure block: if the value is set to 1, the microcore can drive those input signals, otherwise access is denied.

The pins of the current measurement channel 4 are multiplexed with digital IO pins. The current measurement function is activated via the

flags_source (refer to Table 145, Flag_source (1A3h)) and flags_direction register (refer to Table 138, Flag_direction (1A1h)). Current

measure blocks 5 and 6 are different, as it requires 3 DAC values instead of just one as in the others. The “acc ucX chY curr 5/6L” bits

grants access to all the control signals (DAC value 5/6L, ofscmp request, opamp gain) save for the DAC values 5/6H and 5/6Neg, which

are controlled by the “acc ucX chY curr 5/6H 5/6Neg” bits.

Table 85. Cur_block_access_part1 channel1 (166h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

acc_uc

1_ch1_

curr6H

_6Neg

acc_uc

1_ch1_

curr5H

_5Neg

acc_uc

0_ch1_

curr6H

_6Neg

acc_uc

0_ch1_

curr5H

_5Neg

acc_uc

1_ch1_

curr6L

acc_uc acc_uc acc_uc acc_uc acc_uc

1_ch1_ 1_ch1_ 1_ch1_ 1_ch1_ 1_ch1_

acc_uc

0_ch1_

curr6L

acc_uc acc_uc acc_uc acc_uc acc_uc

0_ch1_ 0_ch1_ 0_ch1_ 0_ch1_ 0_ch1_

Name

curr5L curr4

curr3

curr2

curr1

curr5L curr4

curr3

curr2

curr1

R/W

Lock

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

Reset

Table 86. Cur_block_access_part2 channel2 (167h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

acc_uc

1_ch2_

curr6H

_6Neg

acc_uc

1_ch2_

curr5H

_5Neg

acc_uc

0_ch2_

curr6H

_6Neg

acc_uc

0_ch2_

curr5H

_5Neg

acc_uc

1_ch2_

curr6L

acc_uc acc_uc acc_uc acc_uc acc_uc

1_ch2_ 1_ch2_ 1_ch2_ 1_ch2_ 1_ch2_

acc_uc

0_ch2_

curr6L

acc_uc acc_uc acc_uc acc_uc acc_uc

0_ch2_ 0_ch2_ 0_ch2_ 0_ch2_ 0_ch2_

Name

curr5L curr4

curr3

curr2

curr1

curr5L curr4

curr3

curr2

curr1

R/W

Lock

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

Reset

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Table 87. Cur_block_access_part3 channel3 (168h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

acc_uc

1_ch3_

curr6H

_6Neg

acc_uc

1_ch3_

curr5H

_5Neg

acc_uc

0_ch3_

curr6H

_6Neg

acc_uc

0_ch3_

curr5H

_5Neg

acc_uc

1_ch3_

curr6L

acc_uc acc_uc acc_uc acc_uc acc_uc

1_ch3_ 1_ch3_ 1_ch3_ 1_ch3_ 1_ch3_

acc_uc

0_ch3_

curr6L

acc_uc acc_uc acc_uc acc_uc acc_uc

0_ch3_ 0_ch3_ 0_ch3_ 0_ch3_ 0_ch3_

Name

curr5L curr4

curr3

curr2

curr1

curr5L curr4

curr3

curr2

curr1

R/W

Lock

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

Reset

The requests coming from the microcores are not continuous, but they perform a request each time a change to a control signal (Dac,

opamp gain, ofscmp request) is required. If multiple microcores have access to the same current measure block, as a shared resource,

this block is able to handle the collision: if more than one microcore wants to change one of the control signals in the same moment, only

one of the requested values is applied. If requests to change a control signal are received from different microcores (assuming both have

access rights) in different ck cycles, all the requested changes are applied in sequence.

8.3.3.4

Freewheeling link register

Due to some HS pre-driver having two possible fw slaves, there is the need to select which of the links is affected by the stfw instruction

(refer to programming guide for more details on this instruction). This configuration is done in the fw_link register.

Table 88. Fw_link (169h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserve Flag3_f Flag2_f Flag1_f Flag0_f

Hs7_f Reserv Ls7_fw Ls6_fw Ls5_fw Ls4_fw Ls3_fw Ls2_fw Ls1_fw

Name

Reserved

d

w_link

ed

_link

R/W

Lock

-

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

-

r/w

yes

0

-

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

Reset

0

00

0

• Ls1_fw_link: if set, the Ls1 is driven as a fw relative to Hs1, when activated via stfw instruction.

• Ls2_fw_link: if set, the Ls2 is driven as a fw relative to Hs2, when activated via stfw instruction.

• Ls3_fw_link: if set, the Ls3 is driven as a fw relative to Hs3, when activated via stfw instruction.

• Ls4_fw_link: if set, the Ls4 is driven as a fw relative to Hs4, when activated via stfw instruction.

• Ls5_fw_link: if set, the Ls5 is driven as a fw relative to Hs5, when activated via stfw instruction.

• Ls6_fw_link: if set, the Ls6 is driven as a fw relative to Hs6, when activated via stfw instruction.

• Ls7_fw_link: if set, the Ls7 is driven as a fw relative to Hs7, when activated via stfw instruction.

• Hs7_fw_link: if set, the Hs7 is driven as a fw relative to Hs1, when activated via stfw instruction.

• Flag0_fw_link: if set, the Flag0 is driven as a fw relative to Hs4, when activated via stfw instruction.

• Flag1_fw_link: if set, the Flag1 is driven as a fw relative to Hs5, when activated via stfw instruction.

• Flag2_fw_link: if set, the Flag2 is driven as a fw relative to Hs6, when activated via stfw instruction.

• Flag3_fw_link: if set, the Flag3 is driven as a fw relative to Hs7, when activated via stfw instruction.

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Table 89. Freewheeling link register

Freewheeling pre-driver output

Related pre-driver high-side

LS1

LS2

HS1

HS2

HS3

HS4

HS5

HS6

HS7

HS4

HS5

HS6

HS7

LS3

LS4

LS5

LS6

LS7

Flag0

Flag1

Flag2

Flag3

8.3.3.5

Freewheeling external request configuration register

After the freewheeling configuration (see Table 89, Freewheeling link register) it is possible to activate automatic freewheeling by writing

the corresponding bit of this register even when the microcode is not running. This can also be enabled by the stfw instruction.

Table 90. Fw_external_request (16ah)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Hs7_f Hs6_f Hs5_f Hs4_f Hs3_f Hs2_f Hs1_f

w_en w_en w_en w_en w_en w_en w_en

Name

Reserved

R/W

Lock

-

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

-

Reset

000000000

• Hs1_fw_en: if set, the fw relative to Hs1 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

• Hs2_fw_en: if set, the fw relative to Hs2 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

• Hs3_fw_en: if set, the fw relative to Hs3 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

• Hs4_fw_en: if set, the fw relative to Hs4 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

• Hs5_fw_en: if set, the fw relative to Hs5 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

• Hs6_fw_en: if set, the fw relative to Hs6 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

• Hs7_fw_en: if set, the fw relative to Hs7 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

V_BAT

G_HS1

HS1 command

LS1 FW command

G_LS1

FW

tFWDLY

Figure 32. Automatic freewheeling example

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8.3.3.6

V

and V

threshold selection

DS

SRC

Each comparator threshold is expressed on 4 bits. These registers can be written through the SPI. The microcores can change the value

of each field at runtime, provided they have the access right to control the related output (refer to Table 83, Out_acc_ucx_chy (160h, 161h,

162h, 163h, 164h, 165h)).

Table 91. Vds_threshold_hs_Part1 (16Bh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Vds_thr_Hs4

Vds_thr_Hs3

Vds_thr_Hs2

Vds_thr_Hs1

R/W

Lock

r/w

no

r/w

no

r/w

no

r/w

no

Reset

0000

Table 92. Vds_threshold_hs_Part2 (16Ch)

Bit

15

14

13

12

11

10

9

6

5

2

1

Name

Reserved

Vds_thr_Hs7

Vds_thr_Hs6

Vds_thr_Hs5

R/W

Lock

-

r/w

no

r/w

no

r/w

no

Reset

0000

Table 93. Vsrc_threshold_hs_Part1 (16Dh)

Bit

15

14

13

12

11

10

9

6

5

2

1

Name

Vsrc_thr_Hs4

Vsrc_thr_Hs3

Vsrc_thr_Hs2

Vsrc_thr_Hs1

R/W

Lock

r/w

no

r/w

no

r/w

no

r/w

no

Reset

0000

Table 94. Vsrc_threshold_hs_Part2 (16Eh)

Bit

15

14

13

12

11

10

9

6

5

2

1

Name

Reserved

Vsrc_thr_Hs7

Vsrc_thr_Hs6

Vsrc_thr_Hs5

R/W

Lock

-

r/w

no

r/w

no

r/w

no

Reset

0000

Note that when reading back this register, what is actually read from the SPI is not the content of the register, but the real configuration

of the thresholds, in particular the HSx Vsrc thresholds. (see See Bootstrap switch control on page 58).

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Table 95. Vsrc_threshold_hs and vds_threshold_hs value

hsx_vds/src_threshold(3:0)

Threshold voltage HS VDS / HS VSRC (V)

0000

1001

1010

1011

1100

0001

0010

0011

0100

0101

0110

0111

0.00

0.10

0.20

0.30

0.40

0.50

1.0

1.5

2.0

2.5

3.0

3.5

Table 96. Vds_threshold_ls_Part 1 (16Fh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Vds thr Ls4

Vds thr Ls3

Vds thr Ls2

Vds thr Ls1

R/W

Lock

r/w

no

r/w

no

r/w

no

r/w

no

Reset

0000

Table 97. Vds_threshold_ls_Part 2 (170h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Vds thr Ls8

Vds thr Ls7

Vds thr Ls6

Vds thr Ls5

R/W

Lock

r/w

no

r/w

no

r/w

no

r/w

no

Reset

0000

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Table 98. Vds_threshold_ls value

lsx_vds _threshold(3:0)

Threshold Voltage LS V_DS(V)

0000

1001

1010

1011

1100

0001

0010

0011

0100

0101

0110

0111

0.00

0.10

0.20

0.30

0.40

0.50

1.0

1.5

2.0

2.5

3.0

3.5

8.3.3.7

Slew rate high-side and low-side selection register

These registers store the slew rate configuration value for each output driver. The microcores can change the value of each field at

runtime, provided they have the access right to control the related output (refer to Table 83, Out_acc_ucx_chy (160h, 161h, 162h, 163h,

164h, 165h)). Each output has the same slew rate for the rising and falling edge, save for the low-side 7 and 8.

Table 99. Hs_slewrate (171h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

slewrate_hs7

slewrate_hs6

slewrate_hs5

slewrate_hs4

slewrate_hs3

slewrate_hs2

slewrate_hs1

R/W

Lock

-

r/w

no

00

r/w

no

00

r/w

no

00

r/w

no

00

r/w

no

00

r/w

no

00

r/w

no

00

Reset

00

Refer to Table 22 for the slew rates values.

Table 100. Ls_slewrate_Part 1 (172h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

slewrate_ls6

slewrate_ls5

slewrate_ls4

slewrate_ls3

slewrate_ls2

slewrate_ls1

R/W

Lock

-

r/w

no

00

r/w

no

00

r/w

no

00

r/w

no

00

r/w

no

00

r/w

no

00

Reset

0000

Refer to Table 25 for slew rates values.

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Table 101. Ls_slewrate_Part 2 (173h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

slewrate_LS8_ri slewrate_LS8_fa slewrate_LS7_ri slewrate_LS7_f

Name

Reserved

sing

r/w

no

lling

r/w

no

sing

r/w

no

alling

R/W

Lock

-

r/w

-

no

Reset

00000000

00

Refer to Table 28 and Table 29 for slew rates values.

8.3.3.8

Offset compensation results registers

It is possible to measure the offset of each current measure block, including opamp, DAC and comparator; for current measure block 5

and 6, only comparator 5L and 6L, the relative opamp, and the DAC 5L and 6L are considered. The measured offset is automatically

compensated during normal operation. The compensation must be enabled by the microcores (when the input current to the current

measurement block is 0) with the “stoc” instruction (refer to programming user guide).

The offset can be read through the SPI registers. It is also possible to change the value compensated by writing these registers. If the

offset compensation is requested by microcores, it starts from the precedent result (or from the data forced through the SPI). As the offset

can be both positive and negative, all the values in these registers are represented as two’s complement.

Table 102. Offset_compensation12 (174h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

Offset_current_measure_block_2

Reserved

Offset_current_measure_block_1

R/W

Lock

-

r/w

no

-

r/w

no

Reset

00

000000

00

000000

Table 103. Offset_compensation34 (175h)

Bit

15

14

13

12

11

10

9

7

6

4

3

2

1

Name

Reserved

Offset_current_measure_block_4

Reserved

Offset_current_measure_block_3

R/W

Lock

-

r/w

no

-

r/w

no

Reset

00

000000

00

000000

Table 104. Offset_compensation56 (176h)

Bit

15

14

13

12

11

10

9

7

6

4

3

2

1

Name

Reserved

Offset_current_measure_block_6

Reserved

Offset_current_measure_block_5

R/W

Lock

-

r/w

no

-

r/w

no

Reset

00

000000

00

000000

The offset values are stored in registers using the two’s complement notation. The values can range from -32 to 31. The value is then

converted to sign-module notation before being transferred to the analog section.

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107

NXP Semiconductors

8.3.3.9

ADC conversion results registers

It is possible to use the current measure block to perform an ADC conversion. A conversion is performed when requested by a microcore

(reference Programming Guide and Instruction Set) with the correct access rights (refer to Table 83, Out_acc_ucx_chy (160h, 161h, 162h,

163h, 164h, 165h)). The DAC5L and 6L is used when performing an ADC conversion using current measurement channel 5 and 6.

A signal path via the OAx multiplexer, a track and hold circuit, the OAx amplifier, and the DACfb multiplexer is used for ADC mode. While

using ADC mode on current measurement channel 1 and 3, the OA1 output is blocked. While using ADC mode on channel 2 or 4, the

OA2 output is blocked, and while using ADC mode on channel 5 or 6, the OA3 output is blocked (see Figure 20). The OAx multiplexer

must be set to the right input and the OAx output must be enabled manually. The OAx amplifier is set to a gain of 1.0 automatically. It is

not possible to do ADC conversion at the same time at channel 1 and 3, on channel 2 and 4, or on channel 5 and 6.

The conversion takes 11 ck_ofscmp clock cycles (refer to Table 146, Ck_ofscmp_Prescaler(1A4h)). 4 ck_ofscmp clock cycles are needed

for the first bit, because the OAx amplifier output has to settle first after changing the gain. After the first bit 1, a clock cycle is needed for

every of the 7 following bits. The PT2000 has a “track and hold” circuit for the ADC mode. The switch of the track and hold circuit is opened

before the ADC conversion starts and is closed again when ADC mode is switched off. The result of the conversion is stored in the

corresponding adc register after the conversion is finished. It is available to the microcore as long as the ADC mode is on and available

via the SPI register until the next ADC conversion is started.

To trigger a new conversion, switch off the ADC mode and switch it on again, note that a minimum of 1 ck_ofscmp clock cycle is needed

between “stadc on” and “stadc off” (reference Programming Guide and Instruction Set). The result can be read via the SPI registers

(Table 105, Adc12_results (177h), Table 106, Adc34_results (178h), and Table 107, Adc56_results (179h)).

Table 105. Adc12_results (177h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

conversion_2_value

conversion_1_value

R/W

Lock

r

no

Reset

10000000

Table 106. Adc34_results (178h)

Bit

15

14

13

12

11

4

3

Name

conversion_4_value

conversion_3_value

R/W

Lock

r

no

Reset

10000000

Table 107. Adc56_results (179h)

Bit

15

14

13

12

11

4

3

Name

conversion_6_value

conversion_5_value

R/W

Lock

r

no

Reset

10000000

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108

8.3.3.10 Current filters configuration registers

The 10 current feedback are filtered before feeding them to the microcores. The filters of all the current feedback are independent.

Table 108. Current_filter12 (17Ah)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Filter_Ty

pe2

Filter_Ty

pe1

Name

Reserved

Filter_length_2

Reserved

Filter_length_1

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

0

-

r/w

yes

Reset

00

00001

00

00001

Table 109. Current_filter34 (17Bh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Filter_Typ

e4

Filter_Ty

pe3

Name

Reserved

Filter_length_4

Reserved

Filter_length_3

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

0

-

r/w

yes

Reset

00

00001

00

00001

Table 110. Current_filter5l5h (17Ch)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Filter_Type5

H

Filter_Typ

e5L

Name

Reserved

Filter_length_5H

Reserved

Filter_length_5L

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

0

-

r/w

yes

Reset

00

00001

00

00001

Table 111. Current_filter6l6h (17Dh)

Bit

15

14

13

12

11

10

9

7

6

5

4

3

2

1

0

Filter_Type6

H

Filter_Typ

e6L

Name

Reserved

Filter_length_6H

Reserved

Filter_length_6L

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

0

-

r/w

yes

Reset

00

00001

00

00001

Table 112. Current_filter5neg6neg (17Eh)

Bit

15

14

13

12

11

10

9

7

6

5

4

3

2

1

0

Filter

Type

6Neg

Filter

Type

5Neg

Name

Reserved

Filter length 6Neg

Reserved

Filter length 5Neg

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

0

-

r/w

yes

Reset

00

00001

00

00001

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109

NXP Semiconductors

• Filter_type. This 1 bit parameter selects the type of filter used for the relative current feedback:

• if 0 - Any different sample resets the filter counter

• if 1 - Any different sample decreases the filter counter

• Filter_lenght. This 5-bit parameter set the filtering time for the current feedback signal.

t_FTN= t_CKx (Filter_length + 1)

8.3.3.11 Boost DAC configuration registers

This block contains the threshold for the boost DAC. This register can be set either from the SPI interface or from a microcore. It is possible

to limit the microcore access to the boost_dac register by setting access rights. End of line offset compensation is provided for the boost

monitoring, requiring no microcode operation.

Table 113. Boost_dac (17Fh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

boost_threshold

R/W

Lock

-

r/w

no

-

Reset

00000000

Table 114. Boost_dac_access (180h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

uc1_ch uc0_ch uc1_ch uc0_ch uc1_ch uc0_ch

Name

Reserved

3 acc

r/w

yes

0

3 acc

r/w

yes

0

2 acc

r/w

yes

0

2 acc

r/w

yes

0

1 acc

r/w

yes

0

1 acc

r/w

yes

0

R/W

Lock

-

Reset

0000000000

• Boost_threshold. This 8-bit parameter is the threshold used for boost voltage monitoring.

• ucX chY acc. This 1-bit parameter (active high) grants access to the dac_boost register.

Table 115. Boost_filter (181h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

filter_ty

pe

Name

Reserved

Boost_fbk_filter

R/W

Lock

-

r/w

yes

0

r/w

yes

Reset

000

000000000001

• Filter_type: This 1 bit parameter selects the type of filter used:

• if 0 - Any different sample resets the filter counter

• if 1 - Any different sample decreases the filter counter

• Boost_fbk_filter: This 12-bit parameter sets the filtering time for the output of the vboost comparator.

The filtering time is: t_FTN= t_CKx (x_filter + 1)

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110

8.3.3.12

V

low-side 7/8 configuration register

DS

These two registers are used for configuring the timeout for V_DSmonitoring of DC/DC resonant converter. If V_BOOSTdrops below 2 x V_BAT

,

V_DSwould not fall below the V_DSthreshold of 2.5 V, which would not activate the MOSFET in resonant DC/DC converter mode again.

Therefore this timeout is required to force the MOSFET to be switched on. The access for this register is only via the SPI.

Table 116. Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

lsx_vds_hig Cur_dcdc

hspeed_en x_fbk_sel

vdsx_

to_en

Name

dcdcx mode

Reserved

vdsx_dcdc_timeout

R/W

Lock

r

-

r/w

no

0

r/w

no

0

r/w

no

0

r/w

no

Reset

00

000

00000000

• Vdsx_dcdc timeout: This 8 bit parameter defines the time duration of the DC/DC converter (V_DS7/8monitoring Ls7/8). It is needed only

if the async_vds mode is used. Timeout is used if the VDS threshold 2.5 V is not reached.

• The timeout is: t_FTN= t_CKx (x_filter + 1)

• Vdsx_to_en: V_DS7/8timeout is enabled. MOSFET is activated automatically when the timeout has been exceeded

• Cur_dcdcx_fbk_sel for async_vds and async mode:

• For LS7:

• 0: selects cur5h_dcdc feedback signal

• 1: selects cur6h_dcdc feedback signal

• For LS8:

• 0: selects cur6h_dcdc feedback signal

• 1: selects cur5h_dcdc feedback signal

• Lsx_vds_highspeed_en: Enable high speed V_DScomparator for DC/DC control

• 0: standard low speed V_DSmonitor enabled

• 1: high speed V_DSmonitor for DC/DC control enabled

• dcdcx_mode. This bits shows when the automatic DC/DC control feature for LS7/8 is enabled. Refer to See DC/DC converter control

(LS7/8) on page 61 for the behavior of LS7/8 during this mode.

Table 117. DC/DC mode

DC/DC Mode

Description

00, 10

01

Sync mode enabled. LS7/8 controlled by microcore command

Async mode enabled with two current thresholds.

Async mode enabled with one current threshold and V_DSmonitor.

11

8.3.3.13 Battery monitoring results

This block contains the result of the batt DAC plus comparator in ADC mode. This register can be read either from the SPI interface or

from a microcore.

Table 118. batt_results (184h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

batt_result

R/W

Lock

-

r

-

no

Reset

00000000

000000

The ofs_comp_prescaler is used to define the step length of the ADC conversion. The ADC mode is running continuously. One conversion

needs 7 cycles.

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NXP Semiconductors

8.3.3.14 DAC 1-6 values registers

Other than from microcores, it is possible to set the DAC for the current measure blocks by writing to these registers.

Table 119. Dac12_value (185h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

DAC 2 value

DAC 1 value

R/W

Lock

r/w

no

r/w

no

Reset

00000000

Table 120. Dac34_value (186h)

Bit

15

14

13

12

11

10

9

8

4

3

2

1

0

Name

DAC 4 value

DAC 3 value

R/W

Lock

r/w

no

r/w

no

Reset

00000000

Table 121. Dac5l5h_value (187h)

Bit

15

14

13

12

11

10

9

8

4

3

2

1

0

Name

DAC 5H value

DAC 5L value

R/W

Lock

r/w

no

r/w

no

Reset

00000000

Table 122. Dac5neg_value (188h)

Bit

15

14

13

12

11

10

9

7

6

5

4

3

2

1

Name

Reserved

DAC 5Neg value

R/W

Lock

-

r/w

no

-

Reset

000000000000

0000

Table 123. Dac6l6h_value (189h)

Bit

15

14

13

12

11

10

9

7

6

5

4

3

2

1

Name

DAC 6H value

DAC 6L value

R/W

Lock

r/w

no

r/w

no

Reset

00000000

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112

Table 124. Dac6neg_value (18Ah)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

DAC 6Neg value

R/W

Lock

-

r/w

no

-

Reset

000000000000

0000

8.3.3.15 Load bias configuration register

These two registers configure the biasing for each output. The microcores can change the value of each field at runtime, provided they

have the access right to control the related output (refer to Table 83, Out_acc_ucx_chy (160h, 161h, 162h, 163h, 164h, 165h)). High-side

2 and high-side 4 have two biasing structures, one identical (hsx_en_pu) to the other high-sides and one stronger (hsx_en_s_pu).

Note that when reading back this register, what is actually read from the SPI is not the content of the register, but the real configuration of

the HS and LS bias, therefore after the masks imposed by the init phase of the bootstrap switch (see See Bootstrap switch control on page

58). Low-side bias is enabled by default, and they stay ON even after boostrap charge.

Table 125. Hs_bias_config (18Bh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

hs4_en Re-ser- hs2_en

hs7_en hs6_en hs5_en hs4_en hs3_en hs2_en hs1_en

Name

Reserved

s_pu

r/w

no

ved

s_pu

r/w

no

_pu

r/w

no

0

_pu

r/w

no

0

_pu

r/w

no

0

_pu

r/w

no

0

_pu

r/w

no

0

_pu

r/w

no

0

_pu

r/w

no

0

R/W

Lock

-

Reset

0000

0

00

Table 126. Ls_bias_config (18Ch)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ls8_en ls7_en ls6_en ls5_en ls4_en ls3_en ls2_en ls1_en

Name

Reserved

_pd

r/w

no

1

_pd

r/w

no

1

_pd

r/w

no

1

_pd

r/w

no

1

_pd

r/w

no

1

_pd

r/w

no

1

_pd

r/w

no

1

_pd

r/w

no

1

R/W

Lock

-

Reset

00000000

8.3.3.16 Boostrap charged/timer status registers

This register reads the charge status of the HS bootstrap capacitors during initialization phase. (See Bootstrap switch control on page 58).

Table 127. Bootstrap_charged (18Dh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

hs7_bs hs6_bs hs5_bs hs4_bs hs3_bs hs2_bs hs1_bs

_charg _charg _charg _charg _charg _charg _charg

Reserv hs7_sr hs6_sr hs5_sr hs4_sr hs3_sr hs2_sr hs1_sr Reserv

Name

ed

c_1V

ed

R/W

Lock

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

Reset

0

1

PT2000

113

NXP Semiconductors

Table 128. Bootstrap_timer (18Eh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

bootstrap_init_timer

Reserved

R/W

Lock

r

-

Reset

000000

0000000000

• hsx_bs_charged: when '0', the bootstrap capacitor for HSx is charged

• hsx_src_1V: when '1' it was necessary for this pre-driver to switch the V_SRCthreshold to 1.0 V to finish the bootstrap init

• bootstrap init timer: this shows the current value of the six MSBs of the bootstrap init timer. The value is '110100' when the timer expires

Table 129, Bootstrap_charged Bits shows the exact meaning of the bits hsx_bs_charged and hsx_src_1V.

Table 129. Bootstrap_charged Bits

hsx_bs_charged

hsx_src_1V

Description

1

0

1

0

1

Bootstrap capacitor not charged, bootstrap init timer not lapsed, V_SRC= 0.5 V (reset value)

Bootstrap capacitor not charged, timer lapsed, V_SRC= 1.0 V

Bootstrap capacitor charged, V_SRC= 0.5 V when charging finished

Bootstrap capacitor charged, V_SRC= 1.0 V when charging finished

The bootstrap init timer value can be used, together with the other bits of the register, to identify in detail how much time has passed since

V_CCPvoltage was stable and which threshold is used to detect the charge of the bootstrap capacitor.

Table 130. Bootstrap init timer

Bit value

000000

Description

V_CCPvoltage is not stable (undervoltage)

000001

V_CCPvoltage is stable since 0.68 ms (2¹⁴/ 24 MHz ⁽⁵²⁾). Source HS voltage threshold used to detect bootstrap charge is 0.5 V

…

100000

V_CCPvoltage is stable since 21.8 ms ⁽⁵²⁾. Source HS voltage threshold used to detect bootstrap charge is 0.5 V

…

110011

V_CCPvoltage is stable since 34.8 ms ⁽⁵²⁾. Source HS voltage threshold used to detect bootstrap charge is 0.5 V

V_CCPvoltage is stable since at least 35.5 ms ⁽⁵²⁾. Source HS voltage threshold used to detect bootstrap charge is 1.0 V.

110100 (final value)

Notes

52. PLL factor set to 1 means 24 MHz cksys. This calculation will be different if PLL factor is set to 0.

PT2000

NXP Semiconductors

114

8.3.3.17 High-side 1-7 ground reference configuration registers

Table 131. Hsx_ls_act (18Fh - 195h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

hsx ls

act dis

hsx_ls_ hsx_ls7 hsx_ls6 hsx_ls5 hsx_ls4 hsx_ls3 hsx_ls2 hsx_ls1

Name

Reserved

act_dis _act

_act

r/w

yes

1

_act

r/w

yes

1

_act

r/w

yes

1

_act

r/w

yes

1

_act

r/w

yes

1

_act

r/w

yes

1

R/W

Lock

r/w

yes

0

-

r/w

yes

1

r/w

yes

1

-

Reset

0000000

These seven registers are used to configure the ground reference of the hs1 to hs7 source pins.

The hsx_ls_act signal is high if any of the LSX pins connected to the HSX source pin is switched on or if the function is disabled by the

hsx_ls_act_dis bit.

• hsx_ls1_act: must be set to '1' if ls1 is connected to the same load as hsx.

• hsx_ls2_act: must be set to '1' if ls2 is connected to the same load as hsx.

• hsx_ls3_act: must be set to '1' if ls3 is connected to the same load as hsx.

• hsx_ls4_act: must be set to '1' if ls4 is connected to the same load as hsx.

• hsx_ls5_act: must be set to '1' if ls5 is connected to the same load as hsx.

• hsx_ls6_act: must be set to '1' if ls6 is connected to the same load as hsx.

• hsx_ls7_act: must be set to '1' if ls7 is connected to the same load as hsx.

• hsx_ls8_act: must be set to '1' if ls8 is connected to the same load as hsx.

• hsx_ls_act_dis: set this bit to disable the link between hsx and ls pre-drivers. If this bit is set the hsx_ls_act signal is forced to '0'

regardless if an ls is active or not.

8.3.3.18 DAC settling time register

This register is used to set the DAC settling time: while this time is being counted, no micro-code checks on the related current feedback

is true. This is not applicable to the VBoost Dac.

Table 132. Dac_settling_time (196h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

dac_settling_time

R/W

Lock

-

r/w

yes

-

Reset

0000000000

000000

Every time the value of related DAC register is written, the current feedback is marked as invalid for

t_X= t_CKx (dac_settling_time + Filter_length + 4)

The filter_length value can be set in the current filter registers (refer to See Current filters configuration registers on page 109 and See

Boost DAC configuration registers on page 110). Since filter configuration can be different for each DAC, the settling time is also different.

PT2000

115

NXP Semiconductors

8.3.3.19 Analog output (OAx) configuration register

These three registers configure the function of the three OA_OUTx pins.

Table 133. Oa_out1_config (197h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

oa1_g1

oa_sel1

oa1_gain

oa1_en

R/W

Lock

-

r/w

no

0

r/w

no

r/w

no

00

r/w

no

0

-

Reset

000000000

000

• oa1 en: when '1', the selected source is sent to the OA_OUT1 pin, otherwise it is put in high-impedance to connect all OAx pins to the

same MCU ADC.

• oa1 gain: select the gain to apply to the signal

• “00”: gain 1.33

• “01”: gain 2.0

• “10”: gain 3.0

• “11”: gain 5.33

• oa1 g1: select the gain to apply to the signal

• “0”: gain according to oa1 gain

• “1”: gain forced to 1.0

• oa_sel1: select the signal to send to the OA_OUT1 pin.

• “000”: output from current measurement block 1

• “001”: output from current measurement block 3

• “101”: 2.5 Volt

Table 134. Oa_out2_config (198h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

oa2_g1

oa_sel2

oa2_gain

oa2_en

R/W

Lock

-

r/w

no

0

r/w

no

r/w

no

00

r/w

no

0

-

Reset

000000000

000

• oa2 en: when '1' the selected source is sent to OA_OUT2.

• oa2 gain: select the gain to apply to the signal.

• “00”: gain 1.33

• “01”: gain 2.0

• “10”: gain 3.0

• “11”: gain 5.33

• oa2 g1: select the gain to apply to the signal

• “0”: gain according to oa2 gain

• “1”: gain forced to 1.0

• oa_sel2: select the signal to send to the OA_OUT2 pin.

• “000”: output from current measurement block 2

• “001”: output from current measurement block 4

• “101”: 2.5 Volt

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NXP Semiconductors

116

Table 135. Oa_out3_config (199h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

oa3_g1

oa_sel3

oa3_gain

oa3_en

Name

Reserved

R/W

Lock

-

r/w

no

0

r/w

no

r/w

no

r/w

no

0

-

Reset

000000000

000

00

• oa3 en: when '1', the selected source is sent to the OA_OUT3 pin, otherwise it is put in high-impedance to connect all OAx pins to the

same MCU ADC.

• oa3 gain: select the gain to apply to the signal

• “00”: gain 1.33

• “01”: gain 2.0

• “10”: gain 3.0

• “11”: gain 5.33

• oa3 g1: select the gain to apply to the signal.

• “0”: gain according to oa3 gain

• “1”: gain forced to 1.0

• oa_sel3: select the signal to send to the OA_OUT3 pin.

• “000”: output from current measurement block 5

• “001”: output from current measurement block 6

• “101”: 2.5 Volt

• “111”: V_CCA

8.3.4

Main configuration registers

8.3.4.1

“Ck” clock prescaler configuration register

This is a 6-bit register setting the divider ratio to generate the ck clock starting from cksys (24 MHz or 12 MHz refer to Table 151,

PLL_Config (1A7h)). The ck_per register must not be changed again after the microcores are running. During operation the register should

be locked. Note that the actual divider ratio is ck = cksys/(ck_per+1). Therefore setting ck_per to “000100” sets ck = cksys/ (4+1).

Table 136. Clock_Prescaler (1A0h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

ck_per

R/W

Lock

-

r/w

yes

-

Reset

0000000000

000000

Depending on the ck_per setting, different device/channel operation modes is possible according to Table 137, Ck_per and device modes

and See Dual microcore arbiter on page 70.

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Table 137. Ck_per and device modes

microcore frequency

Clock divider at 24 MHz cksys (PLL

factor = 1)

SPI access (r/w) to

CRAM after flash

enable

SPI access (r/w) to

registers and DRAM

Single/dual

microcore

Drive outputs from

flag pins

ck_per

0

1

0+1=1

1+1=2

2+1=3

≥4

-

yes (r/w)

no

12 MHz ⁽⁵³⁾

8.0 MHz

≤6.0 MHz

no

yes

2

yes (r)

≥3

Notes

53. Some limitations apply on the number of consecutive DRAM access and SPI frequency (See Dual microcore arbiter on page 70).

8.3.4.2

Flags direction configuration register

This is a 16-bit register where each bit sets the direction of the corresponding flag as shown in Table 139, Flags_source & Flags_direction

registers. The value of this register is used only for the flags which drive or can be driven by a device pin as specified in the flag_source

register.

Table 138. Flag_direction (1A1h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir flag_dir

Name

15

Dbg

r/w

yes

1

14

OA2

r/w

yes

1

13

Irq

r/w

yes

1

12

11

10

9

8

7

6

5

4

3

2

1

0

Start8 Start7 Start6 Start5 Start4 Start3 Start2 Start1 Flag4 Flag3 Flag2 Flag1 Flag0

R/W

Lock

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

Reset

Table 139. Flags_source & Flags_direction registers

flags_source(x)

flags_direction(x)

flag_bus(x) source

The corresponding pin is used for its non-flag function (start,_irq, analog OA2, extFWx, etc.).

Flag_bus(x) is driven by int_flags(x).

0

0/1

The corresponding pin is used as an output flag. The device pin is driven by int_flags(x).

Flag_bus(x) is driven by int_flags(x).

1

0

1 (reset value)

The corresponding pin is used as an input flag. The Flag_bus(x) is driven by the device pin.

Table 140. Flags_source & Flags_direction registers for Flag 4 and 12

flags_source flags_source flags_direction flags_direction

flag_bus (12) source

flag_bus (4) source

(12)

(4)

(12)

(4)

The pin is used for current measurement The pin is used for current measurement

-

0

-

channel VsenseN4.

channel VsenseP4.

The pin is used for its non-flag function

start8.

The corresponding pin is used as an

output flag.

0

1

-

0

The pin is used for its non-flag function

start8.

The corresponding pin is used as an

input flag.

0 (reset value) 1 (reset value)

1 (reset value)

The corresponding pin is used as an

output flag.

The corresponding pin is used as an

output flag.

1

0

1

The corresponding pin is used as an input The corresponding pin is used as an

flag. input flag.

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Table 140. Flags_source & Flags_direction registers for Flag 4 and 12

flags_source flags_source flags_direction flags_direction

flag_bus (12) source

flag_bus (4) source

(12)

(4)

(12)

(4)

The corresponding pin is used as an input The corresponding pin is used as an

flag. output flag.

1

0

The corresponding pin is used as an input The corresponding pin is used as an

flag. input flag.

1

8.3.4.3

Flags polarity register

This is a 16-bit register where each bit sets the polarity of the corresponding flag as shown in Table 142, Flags_polarity. If a 1 is set, the

corresponding flag inverts. The value of this register is only used for the flags driven by or drive a device pin, as specified in the flag_source

register.

Table 141. Flag_polarity (1A2h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po flag_po

Name

l_15

Dbg

r/w

yes

0

l14

OA2

r/w

yes

0

l13

Irq

r/w

yes

0

l12

l11

l10

l9

l8

l7

l6

l5

l4

l3

l2

l1

l0

Start8 Start7 Start6 Start5 Start4 Start3 Start2 Start1 Flag4 Flag3 Flag2 Flag1 Flag0

R/W

Lock

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

Reset

Table 142. Flags_polarity

flags_polarity(x)

flag_bus(x) condition

as it is

0

1

inverted

Some bits of this register are also used to set the polarity of the start pins when they are not used as flag I/O.

Table 143. Flag_polarity register (1A2h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

start_p start_p start_p start_p start_p start_p start_p start_p

Name

-

ol8

r/w

yes

0

ol7

r/w

yes

0

ol6

r/w

yes

0

ol5

r/w

yes

0

ol4

r/w

yes

0

ol3

r/w

yes

0

ol2

r/w

yes

0

ol1

r/w

yes

0

R/W

Lock

-

Reset

0

Table 144. Start_polarity

flags_polarity(x)

flag_bus(x) condition

Start active high

0

1

Start active Low

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8.3.4.4

Flags source register

All of the 16 flags have a configurable source. This is a 16-bit register where each bit sets the source of the corresponding flag as shown

in Table 139, Flags_source & Flags_direction registers. The flag 12 pin can even be used for three different functions (refer to Table 140,

Flags_source & Flags_direction registers for Flag 4 and 12)

Table 145. Flag_source (1A3h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr flag_sr

Name

c15

c14

c13

Irq

c12

c11

c10

c9

c8

c7

c6

c5

c4

c3

c2

c1

c0

Vsense

4

Dbg

OA2

Start8 Start7 Start6 Start5 Start4 Start3 Start2 Start1

Flag3 Flag2 Flag1 Flag0

R/W

Lock

r/w

yes

1

r/w

yes

0

r/w

yes

1

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

r/w

yes

1

Reset

8.3.4.5

Offset compensation and ADC clock (ck_ofscmp) prescaler

This is an 8-bit register setting the divider ratio to generate the ck_ofscmp clock starting from cksys. This clock feeds the following blocks:

• Current measurement block (See Current measurement offset compensation on page 51)

• Battery voltage measurement (See Battery voltage monitor on page 36)

• ADC conversion (See ADC conversion results registers on page 108)

Note that the actual divider ratio is ck_ofscmp = ck_ofscmp_per + 1. Therefore setting ck_ofscmp_per to “00001000” ck_ofscmp is

cksys/9. The reset value is 2.0 μs (cksys at 24 MHz).

Table 146. Ck_ofscmp_Prescaler(1A4h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

ck_ofscmp_per

R/W

Lock

-

r/w

yes

-

Reset

00000000

00101111

8.3.4.6

Driver interrupt configuration registers

These two registers can configure which conditions concur to the driver disable, which conditions concur to the interrupt generation, and

if the interrupt request must be generated toward the microcontroller and the microcores.

Table 147. Driver_config_Part 1 (1A5h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Overte

mp_irq

_en

Irq_uc1 Irq_uc0 Irq_uc1 Irq_uc0 Irq_uc1 Irq_uc0

Iret_en _ch3_e _ch3_e _ch2_e _ch2_e _ch1_e _ch1_e

Drv_en Vboost Vcc5_ir Vccp_ir

Irq_uc_

en

Name

Reserved

_irq_en _irq_en q_en

q_en

n

r/w

yes

0

n

r/w

yes

0

n

r/w

yes

0

n

r/w

yes

0

n

r/w

yes

0

n

r/w

yes

0

R/W

Lock

-

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

Reset

000

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Table 148. Driver_config_Part 2 (1A6h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Vboost Vboost

_mon_ _disabl

vccp_e

xt_en

Name

Reserved

en

r/w

yes

0

e_en

r/w

yes

0

R/W

Lock

r/w

yes

1

-

Reset

0000000000000

The driver_enable block generates a local interrupt masking the five possible disable conditions with the following bits:

• Drv_en_irq_en: if set, the drv_en generates the local interrupt

• Vboost_irq_en: if set, an undervoltage on V_BOOSTgenerates the local interrupt

• Vcc5_irq_en: if set, an undervoltage on V_CC5generates the local interrupt

• Vccp_irq_en: if set, an undervoltage on V_CCPgenerates the local interrupt

• Overtemp_irq_en: if set, the over temperature condition generates the local interrupt

If a local interrupt is generated, it is possible to propagate it to an external device (micro controller) and to the six microcores. This is done

when the following bits are set:

• Irq_uc_en, for the external device using the IRQB pin

• Irq_uc0_ch1_en, for the microcore 0 of channel 1

• Irq_uc1_ch1_en, for the microcore 1 of channel 1

• Irq_uc0_ch2_en, for the microcore 0 of channel 2

• Irq_uc1_ch2_en, for the microcore 1 of channel 2

• Irq_uc0_ch3_en, for the microcore 1 of channel 3

• Irq_uc1_ch3_en, for the microcore 1 of channel 3

Table 149. Truth table for propagation of UV Vboost_irq

Configuration

Resulting behavior

irq_to µC (Irqb

pin)

Vboost_irq_en

Vboost_disable_en

Irq_ ucx_chy_en

Irq_uc_en

UV Vboost bit set irq_to microcore

0

1

0

1

0

1

d.c.

0

d.c.

0

no

yes

no

1

no

0

yes

no

0

1

no

yes

no

1

0

yes

1

yes

This register also contains some other configuration bit concerning the output drivers:

• iret_en: the driver_enable block automatically generates an iret request toward all the microcores (this request can be filtered by

microcode if not required). No iret request is generated if the interrupt was triggered by a loss of clock. It is possible to select two types

of iret:

• If iret_en is set to '0', an iret request is sent to the microcores when the drivers are re-enabled after a disable condition

• If iret_en is set to '1', an iret request is sent to the microcores when the drivers_status register is cleared. For the iret to happen, either

write the driver status register or to read it while the reset on read configuration is active

• Vboost_disable_en: if set, an undervoltage of V_BOOSTdisables the output drivers

• Vboost_mon_en: this signal configures the divider on the V_BOOSTvoltage

• If Vboost_mon_en is set to '0', V_BOOSTis divided by 32 and then compared with a threshold.

• If Vboost_mon_en is set to '1', V_BOOSTis divided by 4 and then compared with a threshold.

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• vccp_ext_enable: if set to '0', the internal voltage regulator is enabled and the corresponding pin is used only to connect a bypass

capacitor. If set to '1', the internal voltage regulator is disabled and the V_CCPvoltage must be supplied externally through the

corresponding pin. During bootstrap switch init (See Bootstrap switch control on page 58), this setting is bypassed and the value of the

vccp_ext_enable signal is set to the inverted value of the DBG pin sampled at reset (POResetB and ResetB). This is better defined in

Table 150, VCCP external enable setting. This means the DBG pin, at reset, needs to be configured as an input whose value is latched

at the rising edge of the POResetB and ResetB signal, and used to set the configuration of the V_CCPinternal regulator during the init

phase of the bootstrap switch. A SPI reset leaves the latched information unchanged. The DBG pin has an internal weak pull-up resistor

so its value is '1' when not connected (n.c.).

Table 150. V

external enable setting

CCP

dbg pin (latched)

SPI bit

BS Init (min. 1 HS)

VCCP external enable

0 (internal reg ON)

1 (internal reg OFF)

0 (internal reg ON)

1 (internal reg OFF)

0 (internal reg ON)

1 (n.c.)

0

-

1

0

-

1

0

1

0

-

8.3.4.7

PLL factor and speed configuration register

Table 151. PLL_Config (1A7h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_spre

ad_disabl

e

PLL_fact

or

Name

Reserved

R/W

Lock

-

r/w

yes

0

r/w

yes

1

-

Reset

00000000000000

• PLL_factor: if set to '0', the PLL multiplication factor is 12, otherwise it is 24

• PLL_spread_disable: if set to '0' the PLL output clock has a spread, otherwise it has no spread

The PLL factor is changed synchronously with clock monitor cycle to avoid a clock monitor alert when changing between 12 MHz and

24 MHz. This register is reset by POReset, ResetB, and the SPI reset.

8.3.4.8

Backup clock status register

Table 152. backup_clock_status (1A8h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cksys_mi

ssing_dis

able_driv

er

uc1_ch uc0_ch

3_irq_e 3_irq_e

uc0_ch uc1_ch uc0_ch

2_irq_e 1_irq_e 1_irq_e

switch_to

_clock_pi

n

uc1_ch

2 rq en

uc_irq_

en

loss_of

_clock

Name Reserved

Reserved

n

R/W

Lock

-

r/w

yes

0

-

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

yes

0

r/w

no

0

r

no

0

Reset

0

00000

This 11-bit register is meant to provide the external microcontroller a way to monitor the status of the clock signal. This is done by latching

the information occurring on a switch to the backup_reference signal:

• Loss_of_clock: this read_only bit (loss_of_clock) latches the condition when the input reference is missing

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• Switch_to_clock_pin: this bit (active on rising edge) is used to provide a way to reset the loss of clock condition. If this bit is set during

a loss of clock condition it is reset as soon as the clock manager switches the PLL input to the external reference. If this bit sets while

there is no loss of clock, the bit resets immediately without any effect.

• uc_irq_en: enable the generation of an interrupt request to the external micro controller when cksys missing is detected. This interrupt

is active until this register is read

• uc0_ch1_irq_en: enable the generation of an interrupt request to microcore 0 channel 1 when cksys missing is detected

• uc1_ch1_irq_en: enable the generation of an interrupt request to microcore 1 channel 1 when cksys missing is detected

• uc0_ch2_irq_en: enable the generation of an interrupt request to microcore 0 channel 2 when cksys missing is detected

• uc1_ch2_irq_en: enable the generation of an interrupt request to microcore 1 channel 2 when cksys missing is detected

• uc0_ch3_irq_en: enable the generation of an interrupt request to microcore 0 channel 3 when cksys missing is detected

• uc1_ch3_irq_en: enable the generation of an interrupt request to microcore 1 channel 3 when cksys missing is detected

• cksys_missing_disable_driver: if set, the output drivers are disabled via the signal cksys_drven as long as the cksys_missing signal

is '1'.

Once the loss_of_clock bit sets, it can be reset only by completing a “switch to clock” pin. For this operation to complete, it must be

requested when the main clock input pin again provides a valid clock frequency.

The interrupt to the external micro and to the microcores is triggered as long as the cksys_missing signal is set. The microcore is able to

process the interrupt as soon as there is a clock available. It is triggered every time the clock manager switches to the internal clock

reference and when the clock manager tries to switch back to the external clock reference, due to a SPI request. The interrupt can even

occur multiple times during cksys_missing state.

8.3.4.9

SPI configuration register

The spi_config register (address 1A9h) is an 8-bit register storing the SPI protocol configuration and SPI diagnostics.

Table 153. Spi_config (1A9h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MISO_sle protocol_

Name

Reserved

irq_en

watchdog

wrate

mode

R/W

Lock

-

r/w

yes

0

r/w

yes

-

yes

0

yes

0

Reset

00000000

01010

• Miso_slewrate: selects one of the two possible values for the slew rate of the MISO pin.

• 0 slow slew rate

• 1 fast slew rate

• Protocol_mode: select the type of burst transmission accepted by the protocol, '0' means mode A, '1' means mode B.

• irq_enable: enable the SPI interface to request an interrupt toward the microcontroller if an incorrect SPI transmission is received.

• Watchdog: when using mode A, the maximum time the SPI chip select can be inactive during a burst is expressed as follows:

t_WATCHDOG= t_CKSYS((watchdog + 1) ≠ 32768)

where t_CKSYSis the period of the cksys internal clock.

When changing the SPI protocol mode by a write access to this register, it has to be done using a SPI transmission which is compatible

to mode A and B (see See Mode A on page 77 and See Mode B on page 78). This means it must not use '0' as number of operations for

the SPI transmission, and must not deassert the chip select during the transmission. Changing the protocol mode can be done as often

as required.

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8.3.4.10 Tracer start/stop registers

Table 154. Trace_start (1AAh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

start_address

R/W

Lock

-

r/w

no

-

Reset

000000

0000000000

The trigger_address field contains the address used to synchronize the PT2000 trace_unit with the external tracer. If the trace operation

is enabled and the trace unit is in the idle state, when the uPC value of the selected microcore reaches this address, the sync code is

transmitted on the DBG pin. Then the trace_unit goes to the next phase.trace_stop Register (1ABh)

Table 155. Trace_stop (1ABh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

stop_address

R/W

Lock

-

r/w

no

-

Reset

000000

0000000000

The stop_address field contains the address used to finalize the trace operation. If the trace operation is ongoing (trace phase), when the

uPC value of the selected microcore reaches this address, the trace_unit goes to the next phase (post trigger phase).

8.3.4.11 Tracer configuration register

Table 156. Trace_config (1ACh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Trace

enable

Name

Reserved

uc select

Post trigger length

R/W

Lock

r/w

no

0

-

r/w

no

r/w

no

Reset

0000

000

00000000

• Trace enable. When this bit is set to '1', the trace_unit starts the first phase of the trace operation. This bit can be set to '0' by the user,

to immediately stop the PT2000 trace unit transmission. This bit is automatically reset after the trace operation is complete (all the four

phases are finished).

• uc select. Select which is the microcore target of the trace operation:

• “000”: microcore 0, channel 1

• “001”: microcore 1, channel 1

• “010”: microcore 0, channel 2

• “011”: microcore 1, channel 2

• “100”: microcore 0, channel 3

• “101”: microcore 1, channel 3

• Post trigger length. This field selects the duration of the post trigger phase, expressed as number of ck clock cycles. Writing 255 in the

post_trigger_length field of the trace_config register causes the trace unit to output a continuos stream after the stop point. With this,

run the trace operation for an unlimited amount of time and simply deactivate it by writing zero in the trace_enable bit of the trace config

register.

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8.3.4.12 Lock device register

It is possible to lock some registers of the PT2000. Locked registers can be read but cannot be written. The lock is not mandatory for the

correct working of the device; it is only a safety feature. It is possible to reset this lock by writing an unlock password. It is also possible to

independently lock a section of each Data RAM, the last 16 addresses.

Table 157. Device_Lock (1ADh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Dram3_pr Dram2_pr Dram1_pr

ivate_are ivate_are ivate_are

Dev_l

ock

Name

Reserved

a_lock

R/W

Lock

-

no

r/w

yes

0

yes, by

itself

yes, by

itself

yes, by

itself

Reset

000000000000

0

The dev_lock bit can be set by writing the device lock register. It cannot be reset by writing the device_lock register, but only by writing

the correct password in “unlock password”. If the device lock bit is set, all the register bits marked as “lock = yes” in this documentation

can no longer be changed by the SPI. Note that there are some bits not locked by the device lock bit, but locked by other mechanism.

Each of the lock bits for a DRAM is locked by itself and not by the dev lock bit as all the other registers in the device. When the correct

“unlock password” is provided, these three bit are also reset (refer to Table 80, Unlock_word (113h, 133h, 153h)).

8.3.4.13 Reset register behavior

Some registers of the device can be configured to reset when read by an external device through the SPI; read accesses by microcores

using the SPI backdoor never reset those registers.

Table 158. Reset_Behavior (1AEh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SR_uc SR_uc SR_uc SR_uc SR_uc SR_uc

diag_u diag_u diag_u diag_u diag_u diag_u

1_ch3_ 0_ch3_ 1_ch2_ 0_ch2_ 1_ch1_ 0_ch1_ Reserved c1_ch3 c0_ch3 c1_ch2 c0_ch2 c1_ch1 c0_ch1

Driver_en Reserv

Name

able_RB

ed

RB

r/w

no

0

RB

r/w

no

0

RB

r/w

no

0

RB

r/w

no

RB

r/w

no

B

_RB

r/w

no

_RB

r/w

no

_RB

r/w

no

_RB

r/w

no

_RB

r/w

no

_RB

r/w

no

R/W

Lock

r/w

no

0

-

r/w

no

-

Reset

0

• Driver enable reset behavior: if set to '1' driver_status register is reset on read (refer to Table 162, driver_status (1B2h))

• Automatic diagnostics uc0_ch1 reset behavior: if set to '1' err_uc register of microcore 0 of channel 1 is reset on read (See Automatic

diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read

• Automatic diagnostics uc1_ch1 reset behavior: if set to '1' err_uc register of microcore 1 of channel 1 is reset on read (See Automatic

diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read

• Automatic diagnostics uc0_ch2 reset behavior: if set to '1' err_uc register of microcore 0 of channel 2 is reset on read (See Automatic

diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read

• Automatic diagnostics uc1_ch2 reset behavior: if set to '1' err_uc register of microcore 1 of channel 2 is reset on read (See Automatic

diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read

• Automatic diagnostics uc0_ch3 reset behavior: if set to '1' err_uc register of microcore 0 of channel 3 is reset on read (See Automatic

diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read

• Automatic diagnostics uc1_ch3 reset behavior: if set to '1' err_uc register of microcore 1 of channel 3 is reset on read (See Automatic

diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read

• Status register uc0_ch1 reset behavior: if set to '1' the status register of microcore 0 of channel 1 is reset on read (See Status register

microcore0 on page 92 and See Status register microcore1 on page 92)

• Status register uc1_ch1 reset behavior: if set to '1' the status register of microcore 1 of channel 1 is reset on read (See Status register

microcore0 on page 92 and See Status register microcore1 on page 92)

• Status register uc0_ch2 reset behavior: if set to '1' the status register of microcore 0 of channel 2 is reset on read (See Status register

microcore0 on page 92 and See Status register microcore1 on page 92)

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• Status register uc1_ch2 reset behavior: if set to '1' the status register of microcore 1 of channel 2 is reset on read (See Status register

microcore0 on page 92 and See Status register microcore1 on page 92)

• Status register uc0_ch3 reset behavior: if set to '1' the status register of microcore 0 of channel 3 is reset on read (See Status register

microcore0 on page 92 and See Status register microcore1 on page 92)

• Status register uc1_ch3 reset behavior: if set to '1' the status register of microcore 1 of channel 3 is reset on read (See Status register

microcore0 on page 92 and See Status register microcore1 on page 92)

The reset on read feature is implemented so no data is lost when the reset of the register is requested and at the same time there is a

request to set a bit in the register from the microcode. The bit sets and transmits via the SPI the next time the register is read.

8.3.4.14 Unlock device register

Table 159. Device_Unlock (1AFh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Unlock_password

R/W

Lock

w

-

Reset

-

Writing the password 1337h in the unlock password field, resets the device_lock register (refer to Table 157, Device_Lock (1ADh)).

8.3.4.15 SPIReset global reset register 1 and 2

This 32-bit register is divided into two 16-bit slices. When the correct “global reset code” is written in this register, a SPIreset is generated.

This reset lasts for eight cksys clock cycles, then the global reset registers are reset. The global reset code is “F473h” for Global reset

register 1 and “57A1h” for Global reset register 2.

Table 160. Global_Reset_code_part1 (1B0h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Global_Reset_Register_code_1

R/W

Lock

w

no

Reset

0000h

Table 161. Global_Reset_code_part2 (1B1h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Global_Reset_Register_code_2

R/W

Lock

w

no

Reset

0000h

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8.3.4.16 Driver disable status register

This 7-bit register is meant to provide the external micro-controller a way to monitor the status of the output drivers. This is done latching

any error condition which disables the output drivers. Some of these error conditions must be enabled (refer to Table 152,

backup_clock_status (1A8h) and Table 147, Driver_config_Part 1 (1A5h)).

Table 162. driver_status (1B2h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cksys_ DrvEn DrvEn_ Overte uv_vboo

Name

Reserved

uv_vcc5 uv_vccp

missing _latch value

mp

st

R/W

Lock

-

r

-

r

-

r

-

r

-

r

-

r

-

Reset

0000000000000

0

1

0

• cksys_missing: this bit is set if the cksys missing condition it disables the drivers. This condition can be configured (refer to Table 152,

backup_clock_status (1A8h)).

• DrvEn_latch: this bit latches the condition when the DRVEN input pin is inactive. The bit is reset to 1.

1: DRVEN pin was NOT low since last reset of the driver_status register

0: DRVEN pin was low since the last reset of the driver_status register

• DrvEn_value: this bit is not an error condition; it is only a “living copy” of the drv_en pin.

1: DRVEN pin is high

0: DRVEN pin is low

• Overtemperature: this bit latches the condition where an over temperature is present. It is not used to disable the drivers.

• Uv_vboost: this bit is set if the undervoltage on the vboost disables the high-side drivers. This condition can be configured (refer to

Table 147, Driver_config_Part 1 (1A5h)).

• Uv_Vcc5: this bit latches the undervoltage condition on Vcc5.

• Uv_vccp: this bit latches the undervoltage condition on Vccp and the error from GND loss detection.

Once an error bit has been set, it can only be reset by an SPI write operation in this register (if the corresponding error is no more present).

The same error bits are reset even upon SPI read operations but only when a proper enable bit is set (refer to Table 158, Reset_Behavior

(1AEh)).

8.3.4.17 SPI error status register

Table 163. Spi_error (1B3h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cksys_mi frame_err word_err

Name

Reserved

ssing

or

R/W

Lock

-

r

-

r

-

Reset

0000000000000

0

The spi_error register is a 3-bit register split in this way:

• spi_error(2): cksys_missing error condition

• spi_error(1): frame incomplete error condition

• spi_error(0): word incomplete error condition

The duty of this block is to monitor the spi_protocol and the spi_interface to find errors during the communication with the microcontroller.

If an error is detected, the corresponding code is stored in the spi_error_code register. To warn the microcontroller, during the write transfer

(from microcontroller to asic), the MISO signal transfers a diagnostic word: the first 13 bits of this word are constant (“1010101010101”)

and are used to detect short-circuits on the MISO line. The last three bits copy the three LSBs of the spi_error register.

After an error code writes in this register, the register becomes write-protected to latch the error condition and is blind to other occurring

errors. This is because after one error, others are often generated: for example for an incomplete word, which can cause an incorrect

interpretation of a command word and lead to a frame incomplete error.

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By latching only the first occurring error, it is possible to read the cause of the failure in the communication, without having to see all the

side effects. Furthermore, the PT2000 has the possibility to generate an interrupt request toward the microcontroller by setting the

appropriate bit in the spi_config register (refer to Table 153, Spi_config (1A9h)).

When an error is met in the SPI connection, the SPI protocol inside the PT2000 moves to a state where it only accepts a specific two word

SPI transmission with command word (B661h) meant to read the spi_error register (refer to Table 163, Spi_error (1B3h)). This command

causes the device to transmit a single word to the SPI master and then reset the protocol (along with the interrupt if enabled). If the value

of the selection register was set to the value 0100h (selecting the generic configuration registers) before the error, the word transmitted

is the error code and the error code register is reset immediately, otherwise a random word is sent and the error state of the SPI protocol

is reset. In this second case, the error code register can be read (and thus reset) in a following burst. The following are the possible kind

of errors and their relative codes (during correct operations the value of the register is 0000h).

• cksys_missing: this error is set if a SPI transfer is required (which means if the SPI chip select CSB is pulled low) while the cksys clock

is missing.

• frame_error: this error is set if the number of data words in a burst is not the expected number programmed in the command word:

• Mode A is selected, the slave_protocol block received a control word specifying n word transfers, but the microcontroller performs

less operations and then ends the communication. In this case, this module provides a watchdog function if during a programmed

transfer, the communication with the microcontroller is inactive for a time longer than a prefixed limit, so the transfer is considered

aborted and an error is detected.

• Mode B is selected, the number parameter is not zero in the command word and the number of transferred words is different from

the one programmed in the command word.

• A frame error can also occur when the access limitations to DRAM in dual sequencer mode at maximum ck are violated (refer to

Table 49)

• word_error: during the transfer of a word long data, the device receives or sends an incorrect number of bits (15 or 17 instead of 16,

for example). If multiple words are being transferred in a row with the chip select always active (the fastest way), the error is detected

at the end of the sequence and it is not possible to say which is the incorrect word. To be sure of the incorrect data, the chip select

must be deactivated and reactivated between each word transfer.

8.3.4.18 Interruption status registers

These two registers latch the status of all the interrupt requests toward the external microcontroller. They also latch the halt signal

generated by the automatic diagnostics toward the six microcores.

Table 164. Interrupt_Register_Part1 (1B4h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

irq_uc1 irq_uc0 irq_uc1 irq_uc0 irq_uc1 irq_uc0

halt_uc halt_uc halt_uc halt_uc halt_uc halt_uc

1_ch3 0_ch3 1_ch2 0_ch2 1_ch1 0_ch1

Name

Reserved

_ch3

_ch2

_ch1

R/W

Lock

-

r

-

r

no

00

no

0

no

0

no

0

no

0

no

0

no

0

no

00

no

0

no

0

no

0

no

0

no

0

no

0

Reset

Table 165. Interrupt_Register_Part2 (1B5h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

checks checks cksys_

um_ch um_ch missin SPI_irq drv_irq

checksu

m_ch3

Name

Reserved

2

1

g

R/W

Lock

-

r

-

no

00

no

0

no

0

no

0

no

0

no

0

no

0

no

Reset

00000000

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Table 166. Interrupt register bit description

Bit name

Function

halt uc0_ch1

halt uc1_ch1

halt uc0_ch2

halt uc1_ch2

halt uc0_ch3

halt uc1_ch3

irq_uc0_ch1

irq_uc1_ch1

irq_uc0_ch2

irq_uc1_ch2

irq_uc0_ch3

irq_uc1_ch3

Drv_irq

‘1’ if the automatic diagnostics has detected a short-circuit on uc0_ch1

‘1’ if the automatic diagnostics has detected a short-circuit on uc1_ch1

‘1’ if the automatic diagnostics has detected a short-circuit on uc0_ch2

‘1’ if the automatic diagnostics has detected a short-circuit on uc1_ch2

‘1’ if the automatic diagnostics has detected a short-circuit on uc0_ch3

‘1’ if the automatic diagnostics has detected a short-circuit on uc1_ch3

‘1’ if the microcode of uc0_ch1 has asserted its interrupt request

‘1’ if the microcode of uc1_ch1 has asserted its interrupt request

‘1’ if the microcode of uc0_ch2 has asserted its interrupt request

‘1’ if the microcode of uc1_ch2 has asserted its interrupt request

‘1’ if the microcode of uc0_ch3 has asserted its interrupt request

‘1’ if the microcode of uc1_ch3 has asserted its interrupt request

‘1’ if the driver status block has disabled the output drivers

SPI_irq

‘1’ if the SPI interface has detected an error on the SPI communication

‘1’ if the clock monitor has detected a cksys missing condition

‘1’ if the checksum of the code RAM of ch1 is wrong

cksys_missing

Checksum_ch1

Checksum_ch2

Checksum_ch3

‘1’ if the checksum of the code RAM of ch2 is wrong

‘1’ if the checksum of the code RAM of ch3 is wrong

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8.3.4.19 Interrupt subsystem overview

Figure 33 gives an overview over the handling and configuration of the different interrupt sources of the device.

i o n

i n s t r R u e c q t i

n o i u c t t r i n q r s S t i

u p r t r i n e r t e o r o c M i c

( 1 0 0 h , 1 2 0 h , 1 4 0 c h k ) s u C m h e i r q e n = 1

I r q e n = 1 ( 1 A 9 h )

= n 1 ( 1 A 5 h ) u c X c h X e

I r q u c e n & i r q

Figure 33. Interrupt subsystem

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8.3.4.20 Device identifier register

Table 167. Device_Identifier (1B6h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Device_id

Mask_id

Sw_id

R/W

Lock

r

-

r

-

Reset

10101110

0011

0010

This register provide a device identifier for the component. The three fields are:

• Device id is a constant. It identifies the PT2000 device.

• Mask id is a version number of the mask set used for the device. Different mask sets must have a different mask id.

• Sw id is a version number related to the mask set.

8.3.4.21 Reset source status register

This 3-bit register identifies which resets were asserted since the last time this register was read. Each time this register is accessed, it is

also reset.

Table 168. Reset_Source (1B7h)

Bit

Name

R/W

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

SPI reset Po resetb resetb

-

r

-

r

-

r

-

Lock

Reseton

read

-

yes

*

yes

*

yes

*

Reset

0000000000000

Table 169. Reset Source Register Bits

Bit Name

function

SPI reset

Poresetb

resetb

‘1’ if the global SPI reset was asserted since the last time this register was read

‘1’ if the power on reset was asserted since the last time this register was read

‘1’ if the reset pin was asserted since the last time this register was read. After POResetB this bit is in an unknown state.

8.3.4.22 BIST configuration register

The BIST register is used in write mode to trigger the BIST execution.

Table 170. Bist_interface in write mode (1BDh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

BIST activation password

R/W

Lock

w

no

-

Reset

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The BIST passwords are:

• B157h: MBIST

• 0666h: LBIST

• C1A0: Clear LBIST (need to be sent after LBIST is done)

Note that after a LBIST is done a clear BIST command needs to be sent to reenable the logic.

In Read mode the register shows the BIST result.

Table 171. Bist_interface in read mode (1BDh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

LBIST_result

MBIST_result

R/W

Lock

-

r

-

no

00

no

00

Reset

000000000000

• MBIST result: set to “00” if the memory BIST was never requested

• MBIST result: set to “01” if the memory BIST operation is in progress

• MBIST result: set to “10” if the memory BIST operation was successfully completed

• MBIST result: set to “11” if the memory BIST operation has failed

• LBIST result: set to “00” if the logic BIST was never requested or a clear command has been sent

• LBIST result: set to “10” if the logic BIST operation was successfully completed

• LBIST result: set to “11” if the logic BIST operation has failed

• LBIST result: set to “01” if the logic BIST was stopped by Flag0

8.3.5

Diagnostics configuration registers

Automatic diagnostics reaction time

8.3.5.1

If the disable window is exceeded and the automatic diagnostics detects an error between the HSx_in and the filtered HSx_Vds_fbk signal,

an interrupt is generated toward the microcore. This interrupts the program counter of the microcore and sets to the first instruction of the

error routine (refer to Table 70, Diag_routine_addr (10Ch, 12Ch, 14Ch)).

It takes four clock cycles (666 ns at 6.0 MHz) until the execution of the first microcode operation of the error routine is completed. This

means if the first microcode command is used to switch off all pre-drivers, this action is delayed by four clock cycles. In more detail, it

takes one clock cycle to detect the error, one clock cycle to generate the interrupt, one clock cycle to move the program counter to the

error routine, and one clock cycle to execute the first instruction.

Disable Windows

Gate

Feedback V^DS

Filtered Feedback VDS

Mosfet

Filter

Switching

Delay

Time

Figure 34. Example of V_DSautomatic diagnostics filtering and disable windows

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8.3.5.2

LS1 to LS6 output/filter/diag configuration register

These registers define the automatic diagnostics parameter and output routing option from the low-side 1-6 output.

Table 172. LSx_diag_config1 (1C0h, 1C3h, 1C6h, 1C9h, 1CCh, 1CFh, 1D2h, 1D5h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Filter_t

ype

Name

Reserved

Filter_length

Disable_window

R/W

Lock

-

r/w

yes

0

r/w

yes

r/w

yes

Reset

00

000000

0000000

Table 173. LSx_diag_config2 (1C1h, 1C4h, 1C7h, 1CAh, 1CDh, 1D0h, 1D3h, 1D6h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

Error_table

R/W

Lock

-

r/w

yes

-

Reset

000000000000

0000

Table 174. LSx_output_config (1C2h, 1C5h,1C8h, 1CBh, 1CEh, 1D1h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LSx_ov

r

Name

Reserved

output_routing

inv

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

0

-

Reset

0000000000

11111

• Filter_type. This 1-bit parameter selects the type of filter used:

• if 0 - Any different sample resets the filter counter

• if 1 - Any different sample decreases the filter counter

• Filter_lenght. This 6 bits parameter set the filtering time for the input feedback signal.

t_FTN= t_CKx (Filter_length + 1)

• Error_table. This 4-bit parameter defines the logical value of an error signal, starting from the output and the related V_DSfeedback

signal. This table defines the output of the coherency check between the driven output and the acquired feedback. A logic 1 value

means there is no coherency in the check and an error signal towards the micro-microcore should be generated.

output_command = 0

output_command = 1

(pre-driver switched off)

(pre-driver switched on)

LSx_Vds_feed = 0 (V_DSbelow threshold)

LSx_Vds_feed = 1 (V_DSabove threshold)

error_table(0)

error_table (1)

error_table (2)

error_table (3)

• Disable_window. This 7-bit parameter configures a time period during which any check on the LSx_Vds_feed signal is disabled after

any change on the output_command signal.

t_DTL= t_CKx (Disable_window + 4)

• Output_routing. This 4-bit parameter defines if the LSx output is controlled by the microcores or by an input flag pin. When an input flag

pin is selected, the signal from the flag pin and the control signal from the microcores are combined by a logic OR. When a flag pin is

selected to drive the output, it is possible to control low-sides without programming the microcore.

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output_routing

flag ⁽⁵⁴⁾

Flag0

Flag1

Flag2

Flag3

Vsense4

Start1

Start2

Start3

Start4

Start5

Start6

Start7

Start8

Irq

output_command

driven from flag0

driven from flag1

driven from flag2

driven from flag3

driven from flag4

driven from flag5

driven from flag6

driven from flag7

driven from flag8

driven from flag9

driven from flag10

driven from flag11

driven from flag12

driven from flag13

driven from flag14

driven from flag15

driven from the microcores

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16-31

OA2

Dbg

Notes

54. Configuration is linked to the value of flag source register (see Table 145).

• Invert: This parameter inverts the polarity of the LSx output signal, with respect to the polarity defined by the microcore. This affects

the output command toward the pre-drivers, but the error_table of the associated feedback is not affected since diagnostics already

takes into account the pre-driver status (even when the invert bit is set). The invert bit doesn't affect the polarity of the pre-driver when

it is driven from a flag pin.

• LSx_ovr: if set to '1', the low-side x output driver is not influenced by the drv_en.

This bit is only writeable for LS6. For all the other pre-drivers, this feature is not available. The drv_en path is always active (hard wired).

8.3.5.3

LS7 and LS8 output/filter/diag configuration register

For LS7 and LS8, the LSx_diag_config1/2 registers have the same layout as for LS1-6 (refer to Table 172, LSx_diag_config1 (1C0h,

1C3h, 1C6h, 1C9h, 1CCh, 1CFh, 1D2h, 1D5h) and Table 173, LSx_diag_config2 (1C1h, 1C4h, 1C7h, 1CAh, 1CDh, 1D0h, 1D3h, 1D6h).

Table 175, LS7_output_config (1D4h) & LS8_output_config (1D7h) shows the layout of the LS7/8_output_config register.

Table 175. LS7_output_config (1D4h) & LS8_output_config (1D7h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LSx_ov

r

Name

Reserved

output_routing

inv

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

0

-

Reset

000000000

11111

• Output_routing: This 4-bit parameter defines if the LSx output is controlled by the microcores or by an input flag pin. When an input flag

pin is selected, the signal from the flag pin and the control signal from the microcores are combined by a logic OR. When a flag pin is

selected to drive the output, it is possible to control low-sides without programming the microcore.

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output_routing

flag ⁽⁵⁵⁾

Flag0

Flag1

Flag2

Flag3

Vsense4

Start1

Start2

Start3

Start4

Start5

Start6

Start7

Start8

Irq

output_command

driven from flag0

driven from flag1

driven from flag2

driven from flag3

driven from flag4

driven from flag5

driven from flag6

driven from flag7

driven from flag8

driven from flag9

driven from flag10

driven from flag11

driven from flag12

driven from flag13

driven from flag14

driven from flag15

driven from the microcores

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16-31

OA2

Dbg

Notes

55. Configuration is linked to the value of flag source register (see Table 145).

• Invert: This parameter inverts the polarity of the LSx output signal, with respect to the polarity defined by the microcore. The invert bit

doesn't affect the polarity of the pre-driver when it is driven from a flag pin.

• LSx_ovr: if set to '1', the low-side x output driver is not influenced by the drv_en.

8.3.5.4

HSx output/filter/diag configuration register

These registers define the automatic diagnostics parameter and output routing option fro the high-side X output.

Table 176. HSx_diag_config1 (1D8h, 1DBh, 1DEh, 1E0h, 1E4h, 1E7h, 1EAh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Filter_t

ype

Name

Reserved

Filter_length

Disable_window

R/W

Lock

-

r/w

yes

0

r/w

yes

r/w

yes

Reset

00

000000

0000000

Table 177. HSx_diag_config2 (1D9h, 1DCh, 1DFh, 1E2h, 1E5h, 1E8h, 1EBh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Reserved

Error_table_src

Error_table_vds

R/W

Lock

-

r/w

yes

r/w

yes

-

Reset

00000000

0000

PT2000

135

NXP Semiconductors

Table 178. HSx_output_config (1DA, 1DDh, 1E0h, 1E3h, 1E6h, 1E9h)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name HSx ovr

reserved

dead_time

output_routing

inv

R/W

Lock

r/w

yes

0

-

r/w

yes

r/w

yes

r/w

yes

0

Reset

000

00000

11111

• Error_table_vds: This 4-bit parameter defines the logical value of an error signal, starting from the output and the related V_DSfeedback

signal. This table defines the output of the coherency check between the driven output and the acquired feedback. A logic 1 value

means there is no coherency in the check and then an error signal towards the micro-microcore should be generated.

output_command = 0

output_command = 1

(Pre-driver switched off)

(Pre-driver switched on)

HSx_Vds_feed = 0

(V_DSbelow threshold)

error_table(0)

error_table (1)

error_table (2)

error_table (3)

HSx_Vds_feed = 1

(V_DSabove threshold)

• Disable_window: This 7-bit parameter configures a time period during which any check on the HSx_Vds_feed and HSx_Vsrc_feed

signals is disabled after any change on the output_command signal.

t_DTL= t_CKx (Disable_window + 4)

• Error_table_src: This 4-bit parameter defines the logical value of an error signal, starting from the output and the related V_SRCfeedback

signal. This table defines the output of the coherency check between the driven output and the acquired feedback. A logic 1 value

means there is no coherency in the check and then an error signal towards the micro-microcore should be generated.

output_command = 0

output_command = 1

(pre-driver switched off)

(pre-driver switched on)

HSx_Vsrc_feed = 0

(V_SRCbelow threshold)

error_table(0)

error_table (1)

error_table (2)

error_table (3)

HSx_Vsrc_feed = 1

(V_SRCabove threshold)

• Filter_type. This 1 bit parameter selects the type of filter used:

• if 0 - Any different sample resets the filter counter

• if 1 - Any different sample decreases the filter counter

• Dead_time: This 5-bit register is used to store the value of the dead_time end of count used in the generation of the free wheeling output

(delay between the high-side output and the free wheeling output). The FW command goes high after a programmable time (t_FWDLY

)

with respect to the high-side falling edge. In this mode the high-side command rising edge is always delayed of the same programmable

time (t_FWDLY) with respect to the rising edge requested by the microcores.

t_FWDLY= Tck x (Dead_time + 1)

• Output_routing: This 4-bit parameter defines if the HSx output is controlled by the microcores or by an input flag pin. When an input

flag pin is selected, the signal from the flag pin and the control signal from the microcores are combined by a logic OR. When a flag pin

is selected to drive the output, it is possible to control low-sides without programming the microcore.

output_routing

flag ⁽⁵⁶⁾

Flag0

output_command

driven from flag0

driven from flag1

driven from flag2

driven from flag3

driven from flag4

driven from flag5

0

1

2

3

4

5

Flag1

Flag2

Flag3

Vsense4

Start1

PT2000

NXP Semiconductors

136

output_routing

flag ⁽⁵⁶⁾

Start2

Start3

Start4

Start5

Start6

Start7

Start8

Irq

output_command

driven from flag6

6

7

driven from flag7

8

driven from flag8

9

driven from flag9

10

11

12

13

14

15

16-31

driven from flag10

driven from flag11

driven from flag12

driven from flag13

driven from flag14

driven from flag15

driven from the microcores

OA2

Dbg

Notes

56. Configuration is linked to the value of flag source register (see Table 145).

• Invert: This parameter inverts the polarity of the HSx output signal, with respect to the polarity defined by the microcore. This affects

the output command towards the pre-drivers, but the error_table of the associated feedback is not affected since diagnostics already

takes into account the pre-driver status (even when the invert bit is set). The invert bit doesn't affect the polarity of the pre-driver when

it is driven from a flag pin.

• Filter_lenght. This 6-bit parameter sets the filtering time for the input feedback signal.

• t_FTN= t_CKx (Filter_length + 1)

• HSx ovr: if set to '1', the high-side x output driver is not influenced by the drv_en. This bit is only writeable for HS5 and HS7. For all the

other pre-drivers this feature is not available, the drv_en path is always active (hard wired).

8.3.5.5

Automatic diagnostics error status register

This is the status register controlled by automatic diagnostics: one for each microcore. This register stores all meaningful information

whenever an error condition is detected on any of the pairs (output / feedback) to which the microcore is sensitive. The information stored

in the register with regards to the output commands and the related voltage (V_DSand V_SRC) feedback.

A cksys_missing (PLL output clock not valid) condition does not trigger the err_ucXchY to be latched. If the register is latched, the

cksys_missing bit shows the cksys status at the same moment when the automatic diagnostics error occurred. The cksys_missing bit sets

when the PLL output clock was not valid at the time the automatic diagnostics error occurred. The registers can be configured as reset on

read. Refer also to section Table 158, Reset_Behavior (1AEh). Those three registers are reset when the err_ucXchY_3 register is read.

Note that automatic diagnostics are enabled using the endiag or endiaga instructions (reference Programming Guide and Instruction Set).

Table 179. Err_ucxchy_part1 (1EDh, 1F0h, 1F3h, 1F6h, 1F9h, 1FCh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserv cmd_H Vsrc_H Vds_H cmd_H Vsrc_H Vds_H cmd_H Vsrc_H Vds_H cmd_H Vsrc_H Vds_H cmd_H Vsrc_H Vds_H

Name

ed

s5

s4

s3

s2

s1

R/W

Lock

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

r

-

Reset on

read

-

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

Reset

0

PT2000

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NXP Semiconductors

Table 180. Err_ucxchy_part2 (1EEh, 1F1h, 1F4h, 1F7h, 1FAh, 1FDh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cksys_mi

ssing

cmd_

Hs7

Vsrc_

Hs7

Vds_

Hs7

cmd_

Hs6

Vsrc_

Hs6

Vds_

Hs6

Name

Reserved

R/W

Lock

r

-

r

-

r

-

r

-

r

-

r

-

r

-

Reset

on read

conf.

0

-

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

Reset

000000000

Table 181. Err_ucxchy_part3 (1EFh, 1F2h, 1F5h, 1F8h, 1FBh, 1FEh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cmd_L Vds_Ls cmd_L Vds_Ls cmd_L Vds_Ls cmd_L Vds_Ls cmd_L Vds_Ls cmd_L Vds_Ls cmd_L Vds_Ls cmd_L Vds_Ls

Name

S8

8

S7

7

s6

6

s5

5

s4

4

s3

3

s2

2

s1

1

R/W

Lock

r

-

r

-

r

-

Reseton

read

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

conf.

0

Reset

8.3.5.6

Automatic diagnostics command/feedback coherency

The PT2000 performs automatic diagnostics by checking the coherency between the commands it sends to the MOSFETs and the V_DS

/

V_SRCfeedback it gets. The following register configure if the check is between:

• diag_option = 0 => coherency check between what the microcore wants to drive, using instructions like sto/stos/ldca/ldcd and the

feedback from the MOSFETS

• diag_option = 1 => coherency check between what the device is really driving, using instructions like sto/stos/ldca/ldcd, but also

including the status of overtemperature/drven pin/undervoltages/etc. and the feedback from the MOSFETS

For example, in case of an overtemperature/drven pin/undervoltages/etc., drivers are disabled:

In case of diag_option =0 =>, automatic diagnosis coherency check fails and detects an error (microcores are trying to drive but the output

does not move due to a disabled driver, V_DS/V_SRCfeedback incoherent with driving request => fail)

In case of diag_option =1 =>, automatic diagnosis coherency check does not detect anything (microcores are trying to drive, but the output

does not move due to a disabled driver, V_DS/V_SRCfeedback is in this case first compared to “no driving” => ok)

To summarize if the diag_option = 0 then automatic diagnostics is able to cover all kind of faults.

Table 182. diagnostics_option register (1FFh)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Diag_opt

ion

Name

Reserved

R/W

Lock

-

r/w

yes

1

Reset

000000000000000

PT2000

NXP Semiconductors

138

9

Typical applications

The PT2000 can be configured in several applications. Figure 35 and Figure 36 shows the PT2000 in a typical application.

9.1

Application diagram: 3 bank, 6 cylinder with DC/DC

INJECTOR6

INJECTOR5

D N P G

D N D G

D N A G

B Q I R

K C L

T E S R E

N E V D R

O

C C V I

5 C V C

L K S C

I S M O

O S M I

B C S

5 P 2 C V C

C C V P

G

D B

T A V B

3 G A F L

2 G A F L

1 G A F L

0 G A F L

3 N _ E S N E V S

3 P _ E S N E V S

7 T R A S T

6 T R A S T

8 S G _ L

8 S D _ L

5 T R A S T

4 T R A S T

3 T R A S T

2 T R A S T

1 T R A S T

7 S S _ H

Ω

3 3 0

7 S G _ H

F n 1 0 0

7 S B _ H

P M P U

C D A U M C

1 R O T C E J I N

3 R O T C E J I N

2 R O T C E J I N

4 R O T C E J I N

Figure 35. Example of application circuit (6 cylinder 3 bank with DC/DC)

PT2000

139

NXP Semiconductors

9.2

Application diagram: 3 bank, 3 cylinder (full overlap) with DC/DC

3 R O T C E J I N

3

F W

D N P G

D N D G

D N A G

B Q I R

K C L

T E S R E

N E V D R

O

C C V I

5 C V C

L K S C

I S M O

O S M I

B C S

5 P 2 C V C

C C V P

G

D B

T A V B

3 G A F L

2 G A F L

1 G A F L

0 G A F L

3 N _ E S N E V S

3 P _ E S N E V S

7 T R A S T

6 T R A S T

8 S G _ L

8 S D _ L

5 T R A S T

4 T R A S T

3 T R A S T

2 T R A S T

1 T R A S T

7 S S _ H

Ω

3 3 0

7 S G _ H

F n 1 0 0

7 S B _ H

P M P U

C D A U M C

1

F W

2

F W

1 R O T C E J I N

2 R O T C E J I N

Figure 36. Application diagram 3 bank, 3 cylinder with synchronous rectification and DC/DC

PT2000

NXP Semiconductors

140

10

Packaging

10.1

Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and

perform a keyword search for the drawing’s document number.

Package

Suffix

Package outline drawing number

98ASA00505D

80-Pin LQFP

AF

PT2000

141

NXP Semiconductors

PT2000

NXP Semiconductors

142

PT2000

143

NXP Semiconductors

PT2000

NXP Semiconductors

144

11

Reference section

Table 183. PT2000 reference

Description

URL

Programming guide and instruction set http://www.nxp.com/files/analog/doc/user_guide/PT2000SWUG.pdf

Product summary page

http://www.nxp.com/PT2000

PT2000

145

NXP Semiconductors

12

Revision history

Revision

Date

Description of changes

1.0

3/2015

• Initial release

• Made minor corrections

• Corrected typo error on High-side V_DSThreshold in Table 8

• Corrected typo error on Low-side V_DSThreshold in Table 9

2.0

4/2015

• Changed Current Measurement for DC/DC title to heading 3

• Updated reset value in Table 122 (low-side pull-down disable by default)

• Updated figure 35 and 36 to use current sense measurement 6 for Bank 3, recommended in order to use OA3 for Bank3

• Added Shutoff path via the DrvEn pin section.

• I_{VBATT_OPER}value updated to fit with maximum current allowed on VCCP in Table 5

• I_VCC5updated with 6 microcores ON and biasing enabled in Table 5

4/2015

6/2015

• Total Error εV_{BOOST_DAC}updated in Table 5

• OAx Input impedance updated in Table 15

• LBIST clear command added in LBIST

3.0

• Corrected Figure 20

• Added description detail to section 7.2.1.3

• Updated I_VCC5characteristic in Table 5

• Added Table 50

• Added note ⁽¹⁸⁾

11/2015

12/2015

• Updated section 6.1.4.1

• Updated section 8.2.3.2

• Updated section 8.3.3.12

• Updated the example in section 8.3.2.17

4.0

• Corrected package suffix

• Added the VCS_OFF_GD parameter

• Corrected Table 167

• Corrected table titles for Table 172, Table 173, Table 174, Table 176, Table 177, Table 178, Table 179, Table 180, and

Table 181

• Updated the formula for calculating current threshold

• Update Figure 33

• Updated package drawing

5.0

6.0

4/2016

6/2016

• Updated form and style

• Added SPI timings to Table 18

• added clarification to Section 7.1.1. Power-up sequence of VCC5, VCC2P5, and reset, page 57

• Updated Figure 21

• Added Table 3, Resistor types

(3) (4)

• Added Pull resistor type column to Table 2, PT2000 pin definitions ⁽²⁾

,

7.0

8.0

9/2016

4/2017

• Added notes ⁽³⁾and ⁽⁴⁾

.

• Made minor correction to Section 7.2.1.3. Mode 3 (LS7/8 resonant mode VDS monitoring), page 62

• Updated Figure 3 (replaced VSENSEN8 by VSENSEN2)

• Updated min. value for V_BATTand S_RVCCC5in Table 5

• Updated typical value for I_VCCIOin Table 5

• Added note ⁽¹⁶⁾and ⁽⁵²⁾

• Made minor corrections to Application without boost voltage, Low-side VDS monitor D_ls7/D_ls8 for DC/DC, VDS low-

side 7/8 configuration register, and DAC settling time register

• Updated Table 145

PT2000

NXP Semiconductors

146

Revision

Date

Description of changes

• Deleted S_RVCCC5characteristic from Table 5

9.0

4/2017

• Updated Figure 1

10.0

9/2017

• Updated Table 126 (changed all reset values to 1)

• Updated Table 152

PT2000

147

NXP Semiconductors

Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

NXP.com

Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or

Document Number: MC33PT2000

Rev. 10.0

9/2017


型号：	MC33PT2000AF
厂家：	NXP
描述：	Analog Circuit
文件：	总148页 (文件大小：1547K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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