MC34129D_技术文档

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MC145481/D

The MC145481 is a general purpose per channel PCM Codec–Filter with pin

selectable Mu–Law or A–Law companding, and is offered in 20–pin SOG and

SSOP packages. This device performs the voice digitization and reconstruction

as well as the band limiting and smoothing required for PCM systems. This

device is designed to operate in both synchronous and asynchronous

applications and contains an on–chip precision reference voltage.

This device has an input operational amplifier whose output is the input to the

encoder section. The encoder section immediately low–pass filters the analog

signal with an active R–C filter to eliminate very high frequency noise from being

modulated down to the passband by the switched capacitor filter. From the

active R–C filter, the analog signal is converted to a differential signal. From this

point, all analog signal processing is done differentially. This allows processing

of an analog signal that is twice the amplitude allowed by a single–ended

design, which reduces the significance of noise to both the inverted and

non–inverted signal paths. Another advantage of this differential design is that

noise injected via the power supplies is a common–mode signal that is

cancelled when the inverted and non–inverted signals are recombined. This

dramatically improves the power supply rejection ratio.

DW SUFFIX

SOG PACKAGE

CASE 751D

20

1

SD SUFFIX

SSOP

CASE 940C

20

1

ORDERING INFORMATION

MC145481DW

MC145481SD

SOG Package

SSOP

PIN ASSIGNMENT

After the differential converter, a differential switched capacitor filter band–

passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized

by the differential compressing A/D converter.

The decoder accepts PCM data and expands it using a differential D/A

converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X

compensated by a differential switched capacitor filter. The signal is then filtered

by an active R–C filter to eliminate the out–of–band energy of the switched

capacitor filter.

The MC145481 PCM Codec–Filter has a high impedance V

reference pin

AG

which allows for decoupling of the internal circuitry that generates the

mid–supply V reference voltage to the V power supply ground. This

AG

SS

reduces clock noise on the analog circuitry when external analog signals are

referenced to the power supply ground.

The MC145481 PCM Codec–Filter accepts a variety of clock formats,

including Short Frame Sync, Long Frame Sync, IDL, and GCI timing

environments. This device also maintains compatibility with Motorola’s family of

Telecommunication products, including the MC14LC5472 and MC145572

U–Interface Transceivers, MC145474/75 and MC145574 S/T–Interface Trans-

ceivers, MC145532 ADPCM Transcoder, MC145422/26 UDLT–1,

MC145421/25 UDLT–2, and MC3419/MC33120 SLICs.

The MC145481 PCM Codec–Filter utilizes CMOS due to its reliable

low–power performance and proven capability for complex analog/digital VLSI

functions.

•

Single 2.7 to 5.25 V Power Supply

Typical Power Dissipation of 8 mW @ 3 V, Power–Down of 0.01 mW

Fully–Differential Analog Circuit Design for Lowest Noise

Transmit Band–Pass and Receive Low–Pass Filters On–Chip

Active R–C Pre–Filtering and Post–Filtering

Mu–Law and A–Law Companding by Pin Selection

On–Chip Precision Reference Voltage of 0.886 V for a – 5 dBm TLP

@ 600 Ω

•

Push–Pull 300 Ω Power Drivers with External Gain Adjust

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 2

11/98

TN98111300

For More Information On This Product,

Go to: www.freescale.com

1

Freescale Semiconductor, Inc.

Figure 1. MC145481 3 V PCM Codec–Filter Block Diagram

which increment. When the chord bits increment, the step

DEVICE DESCRIPTION

bits double their voltage weighting. This results in an effec-

tive resolution of six bits (sign + chord + four step bits) across

a 42 dB dynamic range (seven chords above 0, by 6 dB per

chord).

A PCM Codec–Filter is used for digitizing and reconstruct-

ing the human voice. These devices are used primarily for

the telephone network to facilitate voice switching and trans-

mission. Once the voice is digitized, it may be switched by

digital switching methods or transmitted long distance (T1,

microwave, satellites, etc.) without degradation. The name

codec is an acronym from ‘‘COder’’ for the analog–to–digital

converter (ADC) used to digitize voice, and ‘‘DECoder’’ for

the digital–to–analog converter (DAC) used for reconstruct-

ing voice. A codec is a single device that does both the ADC

and DAC conversions.

To digitize intelligible voice requires a signal–to–distortion

ratio of about 30 dB over a dynamic range of about 40 dB.

This may be accomplished with a linear 13–bit ADC and

DAC, but will far exceed the required signal–to–distortion

ratio at larger amplitudes than 40 dB below the peak ampli-

tude. This excess performance is at the expense of data per

sample. Two methods of data reduction are implemented by

compressing the 13–bit linear scheme to companded

pseudo–logarithmic 8–bit schemes. The two companding

schemes are: Mu–255 Law, primarily in North America and

Japan; and A–Law, primarily used in Europe. These com-

panding schemes are accepted world wide. These compand-

ing schemes follow a segmented or ‘‘piecewise–linear’’ curve

formatted as sign bit, three chord bits, and four step bits. For

a given chord, all sixteen of the steps have the same voltage

weighting. As the voltage of the analog input increases, the

four step bits increment and carry to the three chord bits

In a sampling environment, Nyquist theory says that to

properly sample a continuous signal, it must be sampled at a

frequency higher than twice the signal’s highest frequency

component. Voice contains spectral energy above 3 kHz, but

its absence is not detrimental to intelligibility. To reduce the

digital data rate, which is proportional to the sampling rate, a

sample rate of 8 kHz was adopted, consistent with a band-

width of 3 kHz. This sampling requires a low–pass filter to

limit the high frequency energy above 3 kHz from distorting

the in–band signal. The telephone line is also subject to

50/60 Hz power line coupling, which must be attenuated

from the signal by a high–pass filter before the analog–to–

digital converter.

The digital–to–analog conversion process reconstructs a

staircase version of the desired in–band signal, which has

spectral images of the in–band signal modulated about the

sample frequency and its harmonics. These spectral images

are called aliasing components, which need to be attenuated

to obtain the desired signal. The low–pass filter used to at-

tenuate these aliasing components is typically called a re-

construction or smoothing filter.

The MC145481 PCM Codec–Filter has the codec, both

presampling and reconstruction filters, and a precision volt-

age reference on–chip.

For More Information On This Product,

Go to: www.freescale.com

2

Freescale Semiconductor, Inc.

come high impedance and the V

Ref pin is pulled to the

power supply with a non–linear, high–impedance circuit.

PIN DESCRIPTIONS

AG

V

DD

POWER SUPPLY

The device will operate normally when a logic 1 is applied to

this pin. The device goes through a power–up sequence

when this pin is taken to a logic 1 state, which prevents the

DT PCM output from going low impedance for at least two

V

DD

Positive Power Supply (Pin 6)

This is the most positive power supply and is typically con-

nected to + 3 V. This pin should be decoupled to V

0.1 µF ceramic capacitor.

FST cycles. The V

and V Ref circuits and the signal pro-

AG

with a

SS

cessing filters must settle out before the DT PCM output or

the RO– receive analog output will represent a valid analog

signal.

V

SS

Negative Power Supply (Pin 15)

ANALOG INTERFACE

This is the most negative power supply and is typically

connected to 0 V.

TI+

Transmit Analog Input (Non–Inverting) (Pin 19)

V

AG

This is the non–inverting input of the transmit input gain

setting operational amplifier. This pin accommodates a differ-

ential to single–ended circuit for the input gain setting op

Analog Ground Output (Pin 20)

This output pin provides a mid–supply analog ground. This

amp. This allows input signals that are referenced to the V

pin should be decoupled to V

pacitor. All analog signal processing within this device is ref-

erenced to this pin. If the audio signals to be processed are

with a 0.01 µF ceramic ca-

SS

pin to be level shifted to the V

pin with minimum noise.

AG

This pin may be connected to the V

pin for an inverting

AG

amplifier configuration if the input signal is already refer-

enced to the V pin. The common mode range of the TI+

referenced to V , then special precautions must be utilized

SS

to avoid noise between V

and the V pin. Refer to the ap-

AG

SS

and TI– pins is from 1.2 V, to V

gate input.

minus 1.2 V. This is an FET

plications information in this document for more information.

The V pin becomes high impedance when this device is in

DD

AG

the powered–down mode.

The TI+ pin also serves as a digital input control for the

transmit input multiplexer. Connecting the TI+ pin to V will

DD

V

AG

Ref

place this amplifier’s output (TG) into a high–impedance

state, and selects the TG pin to serve as a high–impedance

Analog Ground Reference Bypass (Pin 1)

input to the transmit filter. Connecting the TI+ pin to V

will

SS

This pin is used to capacitively bypass the on–chip circuit-

also place this amplifier’s output (TG) into a high–impedance

state, and selects the TI– pin to serve as a high–impedance

input to the transmit filter.

ry that generates the mid–supply voltage for the V

output

AG

pin. This pin should be bypassed to V

ic capacitor using short, low inductance traces. The V

with a 0.1 µF ceram-

SS

Ref

AG

pin is only used for generating the reference voltage for the

pin. Nothing is to be connected to this pin in addition to

TI–

V

AG

the bypass capacitor. All analog signal processing within this

device is referenced to the V pin. If the audio signals to be

Transmit Analog Input (Inverting) (Pin 18)

This is the inverting input of the transmit gain setting op-

erational amplifier. Gain setting resistors are usually con-

nected from this pin to TG and from this pin to the analog

signal source. The common mode range of the TI+ and TI–

AG

processed are referenced to V , then special precautions

SS

must be utilized to avoid noise between V

and the V

pin.

SS

AG

Refer to the applications information in this document for

more information. When this device is in the powered–down

pins is from 1.2 V to V

– 1.2 V. This is an FET gate input.

DD

The TI– pin also serves as one of the transmit input multi-

plexer pins when the TI+ pin is connected to V . When TI+

mode, the V

a non–linear, high–impedance circuit.

Ref pin is pulled to the V

power supply with

AG

DD

SS

is connected to V , this pin is ignored. See the pin descrip-

DD

CONTROL

tions for the TI+ and the TG pins for more information.

Mu/A

TG

Mu/A Law Select (Pin 16)

Transmit Gain (Pin 17)

This pin controls the compression for the encoder and the

expansion for the decoder. Mu–Law companding is selected

This is the output of the transmit gain setting operational

amplifier and the input to the transmit band–pass filter. This

op amp is capable of driving a 2 kΩ load. Connecting the TI+

when this pin is connected to V

selected when this pin is connected to V

and A–Law companding is

DD

.

SS

pin to V

will place the TG pin into a high–impedance state,

DD

PDI

and selects the TG pin to serve as a high–impedance input to

the transmit filter. All signals at this pin are referenced to the

Power–Down Input (Pin 10)

This pin puts the device into a low power dissipation mode

when a logic 0 is applied. When this device is powered down,

all of the clocks are gated off and all bias currents are turned

V

pin. When TI+ is connected to V , this pin is ignored.

AG

SS

See the pin descriptions for the TI+ and TI– pins for more in-

formation. This pin is high impedance when the device is in

the powered–down mode.

off, which causes RO–, PO–, PO+, TG, V , and DT to be-

AG

For More Information On This Product,

Go to: www.freescale.com

3

Freescale Semiconductor, Inc.

RO–

this pin to the clock at FST (8 kHz) and will automatically

accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For

MCLK frequencies of 256 and 512 kHz, MCLK must be syn-

chronous and approximately rising edge aligned to FST. For

optimum performance at frequencies of 1.536 MHz and

higher, MCLK should be synchronous and approximately ris-

ing edge aligned to the rising edge of FST. In many ap-

plications, MCLK may be tied to the BCLKT pin.

Receive Analog Output (Inverting) (Pin 2)

This is the inverting output of the receive smoothing filter

from the digital–to–analog converter. This output is capable

of driving a 2 kΩ load to 0.886 V peak referenced to the V

pin. If the device is operated half–channel with the FST pin

clocking and FSR pin held low, the receive filter input will be

conencted to the V

AG

voltage. This minimizes transients at

AG

the RO– pin when full–channel operation is resumed by

clocking the FSR pin. This pin is high impedance when the

device is in the powered–down mode.

FST

Frame Sync, Transmit (Pin 14)

This pin accepts an 8 kHz clock that synchronizes the out-

put of the serial PCM data at the DT pin. This input is com-

patible with various standards including IDL, Long Frame

Sync, Short Frame Sync, and GCI formats. If both FST and

FSR are held low for several 8 kHz frames, the device will

power down.

PI

Power Amplifier Input (Pin 3)

This is the inverting input to the PO– amplifier. The non–

inverting input to the PO– amplifier is internally tied to the

V

pin. The PI and PO– pins are used with external resis-

AG

BCLKT

Bit Clock, Transmit (Pin 12)

tors in an inverting op amp gain circuit to set the gain of the

PO+ and PO– push–pull power amplifier outputs. Connect-

ing PI to V

will power down the power driver amplifiers and

This pin controls the transfer rate of transmit PCM data. In

the IDL and GCI modes it also controls the transfer rate of

the receive PCM data. This pin can accept any bit clock fre-

quency from 64 to 4096 kHz for Long Frame Sync and Short

Frame Sync timing. This pin can accept clock frequencies

from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz

to 6.176 MHz for GCI timing mode.

DD

the PO+ and PO– outputs will be high impedance.

PO–

Power Amplifier Output (Inverting) (Pin 4)

This is the inverting power amplifier output, which is used

to provide a feedback signal to the PI pin to set the gain of

the push–pull power amplifier outputs. This pin is capable of

driving a 300 Ω load to PO+. The PO+ and PO– outputs are

differential (push–pull) and capable of driving a 300 Ω load to

1.772 V peak, which is 3.544 V peak–to–peak. The bias volt-

DT

Data, Transmit (Pin 13)

This pin is controlled by FST and BCLKT and is high im-

pedance except when outputting PCM data. When operating

in the IDL or GCI mode, data is output in either the B1 or B2

channel as selected by FSR. This pin is high impedance

when the device is in the powered down mode.

age and signal reference of this output is the V

pin. The

pin cannot source or sink as much current as this pin,

AG

V

AG

and therefore low impedance loads must be between PO+

and PO–. The PO+ and PO– differential drivers are also ca-

pable of driving a 100 Ω resistive load or a 100 nF Piezoelec-

tric transducer in series with a 20 Ω resister with a small

increase in distortion. These drivers may be used to drive re-

sistive loads of ≥ 32 Ω when the gain of PO– is set to 1/4 or

FSR

Frame Sync, Receive (Pin 7)

When used in the Long Frame Sync or Short Frame Sync

mode, this pin accepts an 8 kHz clock, which synchronizes

the input of the serial PCM data at the DR pin. FSR can be

asynchronous to FST in the Long Frame Sync or Short

Frame Sync modes. When an ISDN mode (IDL or GCI) has

been selected with BCLKR, this pin selects either B1 (logic 0)

or B2 (logic 1) as the active data channel.

less. Connecting PI to V

will power down the power driver

DD

amplifiers and the PO+ and PO– outputs will be high imped-

ance. This pin is also high impedance when the device is

powered down by the PDI pin.

PO+

Power Amplifier Output (Non–Inverting) (Pin 5)

BCLKR

Bit Clock, Receive (Pin 9)

This is the non–inverting power amplifier output, which is

an inverted version of the signal at PO–. This pin is capable

When used in the Long Frame Sync or Short Frame Sync

mode, this pin accepts any bit clock frequency from 64 to

4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,

and DR become IDL Interface compatible. When this pin is

held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-

face compatible.

of driving a 300 Ω load to PO–. Connecting PI to V

will

DD

power down the power driver amplifiers and the PO+ and

PO– outputs will be high impedance. This pin is also high im-

pedance when the device is powered down by the PDI pin.

See PI and PO– for more information.

DIGITAL INTERFACE

DR

MCLK

Data, Receive (Pin 8)

Master Clock (Pin 11)

This pin is the PCM data input, and when in a Long Frame

Sync or Short Frame Sync mode is controlled by FSR and

BCLKR. When in the IDL or GCI mode, this data transfer is

controlled by FST and BCLKT. FSR and BCLKR select the

B channel and ISDN mode, respectively.

This is the master clock input pin. The clock signal applied

to this pin is used to generate the internal 256 kHz clock and

sequencing signals for the switched–capacitor filters, ADC,

and DAC. The internal prescaler logic compares the clock on

For More Information On This Product,

Go to: www.freescale.com

4

Freescale Semiconductor, Inc.

tors. The PO+ amplifier has a gain of minus one, and is in-

FUNCTIONAL DESCRIPTION

ternally connected to the PO– output. This complete power

amplifier circuit is a differential (push–pull) amplifier with ad-

justable gain that is capable of driving a 300 Ω load to

+7 dBm. The power amplifier may be powered down inde-

pendently of the rest of the chip by connecting the PI pin to

ANALOG INTERFACE AND SIGNAL PATH

The transmit portion of this device includes a low–noise,

three–terminal op amp capable of driving a 2 kΩ load. This

op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its

output is TG (Pin 17). This op amp is intended to be confi-

gured in an inverting gain circuit. The analog signal may be

applied directly to the TG pin if this transmit op amp is inde-

pendently powered down by connecting the TI+ input to the

V

.

DD

POWER–DOWN

There are two methods of putting this device into a low

power consumption mode, which makes the device nonfunc-

tional and consumes virtually no power. PDI is the power–

down input pin which, when taken low, powers down the

device. Another way to power the device down is to hold both

the FST and FSR pins low while the BCLKT and MCLK pins

V

power supply. The TG pin becomes high impedance

DD

when the transmit op amp is powered down. The TG pin is

internally connected to a 3–pole anti–aliasing pre–filter. This

pre–filter incorporates a 2–pole Butterworth active low–pass

filter, followed by a single passive pole. This pre–filter is fol-

lowed by a single–ended to differential converter that is

clocked at 512 kHz. All subsequent analog processing uti-

lizes fully–differential circuitry. The next section is a fully–dif-

ferential, 5–pole switched–capacitor low–pass filter with a

3.4 kHz frequency cutoff. After this filter is a 3–pole

switched–capacitor high–pass filter having a cutoff fre-

quency of about 200 Hz. This high–pass stage has a trans-

mission zero at dc that eliminates any dc coming from the

analog input or from accumulated op amp offsets in the pre-

ceding filter stages. The last stage of the high–pass filter is

an autozeroed sample and hold amplifier.

are clocked. When the chip is powered down, the V , TG,

AG

RO–, PO+, PO–, and DT outputs are high impedance and

the V

Ref pin is pulled to the V power supply with a non–

AG

DD

linear, high–impedance circuit. To return the chip to the pow-

er–up state, PDI must be high and the FST frame sync pulse

must be present while the BCLKT and MCLK pins are

clocked. The DT output will remain in a high–impedance

state for at least two 8 kHz FST pulses after power–up.

MASTER CLOCK

Since this codec–filter design has a single DAC architec-

ture, the MCLK pin is used as the master clock for all analog

signal processing including analog–to–digital conversion,

digital–to–analog conversion, and for transmit and receive fil-

tering functions of this device. The clock frequency applied to

the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,

1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-

vice has a prescaler that automatically determines the proper

divide ratio to use for the MCLK input, which achieves the re-

quired 256 kHz internal sequencing clock. The clocking re-

quirements of the MCLK input are independent of the PCM

data transfer mode (i.e., Long Frame Sync, Short Frame

Sync, IDL mode, or GCI mode).

One bandgap voltage reference generator and digital–to–

analog converter (DAC) are shared by the transmit and re-

ceive sections. The autozeroed, switched–capacitor

bandgap reference generates precise positive and negative

reference voltages that are virtually independent of tempera-

ture and power supply voltage. A binary–weighted capacitor

array (CDAC) forms the chords of the companding structure,

while a resistor string (RDAC) implements the linear steps

within each chord. The encode process uses the DAC, the

voltage reference, and a frame–by–frame autozeroed

comparator to implement a successive–approximation con-

version algorithm. All of the analog circuitry involved in the

data conversion (the voltage reference, RDAC, CDAC, and

comparator) are implemented with a differential architecture.

The receive section includes the DAC described above, a

sample and hold amplifier, a 5–pole, 3400 Hz switched ca-

pacitor low–pass filter with sinX/X correction, and a 2–pole

active smoothing filter to reduce the spectral components of

the switched capacitor filter. The output of the smoothing fil-

ter is buffered by an amplifier, which is output at the RO– pin.

DIGITAL I/O

The MC145481 is pin selectable for Mu–Law or A–Law.

Table 1 shows the 8–bit data word format for positive and

negative zero and full scale for both companding schemes.

Table 2 shows the series of eight PCM words for both Mu–

Law and A–Law that correspond to a digital milliwatt. The

digital mW is the 1 kHz calibration signal reconstructed by

the DAC that defines the absolute gain or 0 dBm0 Transmis-

sion Level Point (TLP) of the DAC. The timing for the PCM

data transfer is independent of the companding scheme se-

lected. Refer to Figure 2 for a summary and comparison of

the four PCM data interface modes of this device.

This output is capable of driving a 2 kΩ load to the V

pin.

AG

The MC145481 also has a pair of power amplifiers that are

connected in a push–pull configuration. The PI pin is the in-

verting input to the PO– power amplifier. The non–inverting

input is internally tied to the V

pin. This allows this amplifier

to be used in an inverting gain circuit with two external resis-

AG

For More Information On This Product,

Go to: www.freescale.com

5

Freescale Semiconductor, Inc.

Table 1. PCM Codes for Zero and Full Scale

Mu–Law

Chord Bits

0 0 0

A–Law

Level

+ Full Scale

+ Zero

Sign Bit

Step Bits

0 0 0 0

1 1 1 1

0 0 0 0

Sign Bit

Chord Bits

0 1 0

Step Bits

1 0 1 0

0 1 0 1

1 0 1 0

1

0

1

0

1 1 1

1 0 1

– Zero

1 1 1

1 0 1

– Full Scale

0 0 0

0 1 0

Table 2. PCM Codes for Digital mW

Mu–Law

A–Law

Chord Bits

0 1 1

Phase

π/8

Sign Bit

Chord Bits

0 0 1

Step Bits

1 1 1 0

1 0 1 1

1 1 1 0

1 0 1 1

1 1 1 0

Sign Bit

Step Bits

0 1 0 0

0 0 0 1

0 1 0 0

0 0 0 1

0 1 0 0

0

1

0

1

3π/8

0 0 0

0 1 0

5π/8

0 0 0

0 1 0

7π/8

0 0 1

0 1 1

9π/8

0 0 1

0 1 1

11π/8

13π/8

15π/8

0 0 0

0 1 0

0 0 0

0 1 0

0 0 1

0 1 1

For More Information On This Product,

Go to: www.freescale.com

6

Freescale Semiconductor, Inc.

Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking)

Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking)

Figure 2c. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common Clocking)

Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking)

Figure 2. Digital Timing Modes for the PCM Data Interface

For More Information On This Product,

Go to: www.freescale.com

7

Freescale Semiconductor, Inc.

Long Frame Sync

used for two specific synchronizing functions. The first is to

synchronize the PCM data word transfer, and the second is

to control the internal analog–to–digital and digital–to–analog

conversions. The term ‘‘Sync’’ refers to the function of syn-

chronizing the PCM data word onto or off of the multiplexed

serial PCM data bus, which is also known as a PCM high-

way. The term ‘‘Short’’ comes from the duration of the frame

sync measured in PCM data clock cycles. Short Frame Sync

timing occurs when the frame sync is used as a ‘‘pre–syn-

chronization’’ pulse that is used to tell the internal logic to

clock out the PCM data word under complete control of the

data clock. The Short Frame Sync is held high for one falling

data clock edge. The device outputs the PCM data word be-

ginning with the following rising edge of the data clock. This

results in the PCM output going low impedance with the ris-

ing edge of the transmit data clock, and remaining low im-

pedance until the middle of the LSB (seven and a half PCM

data clock cycles).

The device recognizes Short Frame Sync clocking when

the frame sync is held high for one and only one falling edge

of the transmit data clock. The transmit logic decides on each

frame sync whether it should interpret the next frame sync

pulse as a Long or a Short Frame Sync. This decision is used

for receive circuitry also. The device is designed to prevent

PCM bus contention by not allowing the PCM data output to

go low impedance for at least two frame sync cycles after

power is applied or when coming out of the powered down

mode.

The receive side of the device is designed to accept the

same frame sync and data clock as the transmit side and to

be able to latch its own transmit PCM data word. Thus the

PCM digital switch needs to be able to generate only one

type of frame sync for use by both transmit and receive sec-

tions of the device.

The falling edge of the receive data clock latching a high

logic level at the receive frame sync input tells the device to

start latching the 8–bit serial word into the receive data input

on the following eight falling edges of the receive data clock.

The internal receive logic counts the receive data clock

cycles and transfers the PCM data word to the digital–to–

analog converter sequencer on the rising data clock edge af-

ter the LSB has been latched into the device.

Long Frame Sync is the industry name for one type of

clocking format that controls the transfer of the PCM data

words. (Refer to Figure 2a.) The ‘‘Frame Sync’’ or ‘‘Enable’’ is

used for two specific synchronizing functions. The first is to

synchronize the PCM data word transfer, and the second is

to control the internal analog–to–digital and digital–to–analog

conversions. The term ‘‘Sync’’ refers to the function of syn-

chronizing the PCM data word onto or off of the multiplexed

serial PCM data bus, which is also known as a PCM high-

way. The term ‘‘Long’’ comes from the duration of the frame

sync measured in PCM data clock cycles. Long Frame Sync

timing occurs when the frame sync is used directly as the

PCM data output driver enable. This results in the PCM out-

put going low impedance with the rising edge of the transmit

frame sync, and remaining low impedance for the duration of

the transmit frame sync.

The implementation of Long Frame Sync has maintained

compatibility and been optimized for external clocking sim-

plicity. This optimization includes the PCM data output going

low impedance with the logical AND of the transmit frame

sync (FST) with the transmit data bit clock (BCLKT). The op-

timization also includes the PCM data output (DT) remaining

low impedance until the middle of the LSB (seven and a half

PCM data clock cycles) or until the FST pin is taken low,

whichever occurs last. This requires the frame sync to be

approximately rising edge aligned with the initiation of the

PCM data word transfer, but the frame sync does not have a

precise timing requirement for the end of the PCM data word

transfer. The device recognizes Long Frame Sync clocking

when the frame sync is held high for two consecutive falling

edges of the transmit data clock. The transmit logic decides

on each frame sync whether it should interpret the next

frame sync pulse as a Long or a Short Frame Sync. This de-

cision is used for receive circuitry also. The device is de-

signed to prevent PCM bus contention by not allowing the

PCM data output to go low impedance for at least two frame

sync cycles after power is applied or when coming out of the

powered down mode.

The receive side of the device is designed to accept the

same frame sync and data clock as the transmit side and to

be able to latch its own transmit PCM data word. Thus the

PCM digital switch needs to be able to generate only one

type of frame sync for use by both transmit and receive sec-

tions of the device.

The logical AND of the receive frame sync with the receive

data clock tells the device to start latching the 8–bit serial

word into the receive data input on the falling edges of the

receive data clock. The internal receive logic counts the re-

ceive data clock cycles and transfers the PCM data word to

the digital–to–analog converter sequencer on the ninth data

clock rising edge.

This device is compatible with four digital interface modes.

To ensure that this device does not reprogram itself for a dif-

ferent timing mode, the BCLKR pin must change logic state

no less than every 125 µs. The minimum PCM data bit clock

frequency of 64 kHz satisfies this requirement.

Interchip Digital Link (IDL)

The Interchip Digital Link (IDL) Interface is one of two

standard synchronous 2B+D ISDN timing interface modes

with which this device is compatible. In the IDL mode, the de-

vice can communicate in either of the two 64 kbps B chan-

nels (refer to Figure 2c for sample timing). The IDL mode is

selected when the BCLKR pin is held high for two or more

FST (IDL SYNC) rising edges. The digital pins that control

the transmit and receive PCM word transfers are repro-

grammed to accommodate this mode. The pins affected are

FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of

four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT),

and IDL RX (DR). The IDL interface mode provides access to

both the transmit and receive PCM data words with common

control clocks of IDL Sync and IDL Clock. In this mode, the

This device is compatible with four digital interface modes.

To ensure that this device does not reprogram itself for a dif-

ferent timing mode, the BCLKR pin must change logic state

no less than every 125 µs. The minimum PCM data bit clock

frequency of 64 kHz satisfies this requirement.

Short Frame Sync

Short Frame Sync is the industry name for the type of

clocking format that controls the transfer of the PCM data

words (refer to Figure 2b). The ‘‘Frame Sync’’ or ‘‘Enable’’ is

For More Information On This Product,

Go to: www.freescale.com

8

Freescale Semiconductor, Inc.

FSR pin controls whether the B1 channel or the B2 channel

The FSC (FST, Pin 14) is the input for the GCI frame syn-

chronization signal. The signal at this pin is nominally rising

edge aligned with the DCL clock signal. (Refer to Figure 6

and the GCI Timing specifications for more details.) This

event identifies the beginning of the GCI frame. The frequen-

cy of the FSC synchronization signal is 8 kHz. The rising

edge of the FSC (FST) should be aligned approximately with

the rising edge of MCLK. MCLK must be one of the clock fre-

quencies specified in the Digital Switching Characteristics

table, and is typically tied to DCL (BCLKT).

The DCL (BCLKT, Pin 12) is the input for the clock that

controls the PCM data transfers. The clock applied at the

DCL input is twice the actual PCM data rate. The GCI frame

begins with the logical AND of the FSC with the DCL. This

event initiates the PCM data word transfers for both transmit

and receive. This pin accepts a GCI data clock frequency of

512 kHz to 6.176 MHz for PCM data rates of 256 kHz to

3.088 MHz.

is used for both transmit and receive PCM data word trans-

fers. When the FSR pin is low, the transmit and receive PCM

words are transferred in the B1 channel, and for FSR high

the B2 channel is selected. The start of the B2 channel is ten

IDL CLK cycles after the start of the B1 channel.

The IDL SYNC (FST, Pin 14) is the input for the IDL frame

synchronization signal. The signal at this pin is nominally

high for one cycle of the IDL Clock signal and is rising edge

aligned with the IDL Clock signal. (Refer to Figure 4 and the

IDL Timing specifications for more details.) This event identi-

fies the beginning of the IDL frame. The frequency of the IDL

Sync signal is 8 kHz. The rising edge of the IDL SYNC (FST)

should be aligned approximately with the rising edge of

MCLK. MCLK must be one of the clock frequencies specified

in the Digital Switching Characteristics table, and is typically

tied to IDL CLK (BCLKT).

The IDL CLK (BCLKT, Pin 12) is the input for the PCM

data clock. All IDL PCM transfers and data control sequenc-

ing are controlled by this clock following the IDL SYNC. This

pin accepts an IDL data clock frequency of 256 kHz to 4.096

MHz.

The IDL TX (DT, Pin 13) is the output for the transmit PCM

data word. Data bits are output for the B1 channel on se-

quential rising edges of the IDL CLK signal beginning after

the IDL SYNC pulse. If the B2 channel is selected, then the

PCM word transfer starts on the eleventh IDL CLK rising

edge after the IDL SYNC pulse. The IDL TX pin will remain

low impedance for the duration of the PCM word until the

LSB after the falling edge of IDL CLK. The IDL TX pin will re-

main in a high impedance state when not outputting PCM

data or when a valid IDL Sync signal is missing.

The GCI D

(DT, Pin 13) is the output for the transmit

out

PCM data word. Data bits are output for the B1 channel on

alternate rising edges of the DCL clock signal, beginning with

the FSC pulse. If the B2 channel is selected, then the PCM

word transfer starts on the seventeenth DCL rising edge after

the FSC rising edge. The D

for 15–1/2 DCL clock cycles. The D

pin will remain low impedance

pin becomes high

out

impedance after the second falling edge of the DCL clock

during the LSB of the PCM word. The D pin will remain in

out

a high–impedance state when not outputting PCM data or

when a valid FSC signal is missing.

The D (DR, Pin 8) is the input for the receive PCM data

in

word. Data bits are latched in for the B1 channel on alternate

rising edges of the DCL clock signal, beginning with the se-

cond DCL clock after the rising edge of the FSC pulse. If the

B2 channel is selected then the PCM word is latched in start-

ing on the eighteenth DCL rising edge after the FSC rising

edge.

The IDL RX (DR, Pin 8) is the input for the receive PCM

data word. Data bits are input for the B1 channel on sequen-

tial falling edges of the IDL CLK signal beginning after the

IDL SYNC pulse. If the B2 channel is selected, then the PCM

word is latched in starting on the eleventh IDL CLK falling

edge after the IDL SYNC pulse.

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

General Circuit Interface (GCI)

The MC145481 is manufactured using high–speed CMOS

VLSI technology to implement the complex analog signal

processing functions of a PCM Codec–Filter. The fully–differ-

ential analog circuit design techniques used for this device

result in superior performance for the switched capacitor fil-

ters, the analog–to–digital converter (ADC) and the digital–

to–analog converter (DAC). Special attention was given to

the design of this device to reduce the sensitivities of noise,

including power supply rejection and susceptibility to radio

frequency noise. This special attention to design includes a

fifth order low–pass filter, followed by a third order high–pass

filter whose output is converted to a digital signal with greater

than 75 dB of dynamic range, all operating on a single 3 V

power supply. This results in an LSB size for small audio sig-

nals of about 216 µV. The typical idle channel noise level of

this device is less than one LSB. In addition to the dynamic

range of the codec–filter function of this device, the input

gain–setting op amp has the capability of greater than 30 dB

of gain intended for an electret microphone interface.

The General Circuit Interface (GCI) is the second of two

standard synchronous 2B+D ISDN timing interface modes

with which this device is compatible. In the GCI mode, the

device can communicate in either of the two 64 kbps B–

channels. (Refer to Figure 2d for sample timing.) The GCI

mode is selected when the BCLKR pin is held low for two or

more FST (FSC) rising edges. The digital pins that control

the transmit and receive PCM word transfers are repro-

grammed to accommodate this mode. The pins affected are

FST, FSR, BCLKT, DT, and DR. The GCI Interface consists

of four pins: FSC (FST), DCL (BCLKT), D

(DT), and D

out

in

(DR). The GCI interface mode provides access to both the

transmit and receive PCM data words with common control

clocks of FSC (frame synchronization clock) and DCL (data

clock). In this mode, the FSR pin controls whether the B1

channel or the B2 channel is used for both transmit and re-

ceive PCM data word transfers. When the FSR pin is low, the

transmit and receive PCM words are transferred in the B1

channel, and for FSR high the B2 channel is selected. The

start of the B2 channel is 16 DCL cycles after the start of the

B1 channel.

This device was designed for ease of implementation, but

due to the large dynamic range and the noisy nature of the

environment for this device (digital switches, radio tele-

For More Information On This Product,

Go to: www.freescale.com

9

Freescale Semiconductor, Inc.

phones, DSP front–end, etc.) special care must be taken to

assure optimum analog transmission performance.

6. Use a short, wide, low inductance trace to connect the

groundpintothepowersupplyground. TheV pin

V

SS

is the digital ground and the most negative power supply

pin for the analog circuitry. All analog signal processing

PC BOARD MOUNTING

is referenced to the V

circuitry will probably be powered by this same ground,

care must be taken to minimize high frequency noise in

pin, but because digital and RF

AG

It is recommended that the device be soldered to the PC

board for optimum noise performance. If the device is to be

used in a socket, it should be placed in a low parasitic pin

inductance (generally, low–profile) socket.

the V

trace. Depending on the application, a double–

ground plane connecting all of the

pins together would be a good

SS

sided PCB with a V

SS

digital and analog V

POWER SUPPLY, GROUND, AND NOISE

CONSIDERATIONS

SS

grounding method. A multilayer PC board with a ground

plane connecting all of the digital and analog V pins

SS

This device is intended to be used in switching applica-

tions which often require plugging the PC board into a rack

with power applied. This is known as ‘‘hot–rack insertion.’’ In

these applications care should be taken to limit the voltage

together would be the optimal ground configuration.

These methods will result in the lowest resistance and

the lowest inductance in the ground circuit. This is

important to reduce voltage spikes in the ground circuit

resulting from the high speed digital current spikes. The

magnitude of digitally induced voltage spikes may be

hundreds of times larger than the analog signal the

device is required to digitize.

on any pin from going positive of the V

the V

SS

pins, or negative of

pins. One method is to extend the ground and power

DD

contacts of the PCB connector. The device has input protec-

tion on all pins and may source or sink a limited amount of

current without damage. Current limiting may be accom-

plished by series resistors between the signal pins and the

connector contacts.

The most important considerations for PCB layout deal

with noise. This includes noise on the power supply, noise

generated by the digital circuitry on the device, and cross

coupling digital or radio frequency signals into the audio sig-

nals of this device. The best way to prevent noise is to:

1. Keep digital signals as far away from audio signals as

possible.

7. Use a short, wide, low inductance trace to connect the

V

power supply pin to the 3 V power supply.

DD

Depending on the application, a double–sided PCB with

bypass capacitors to the V ground plane, as

V

DD

SS

described above, may complete the low impedance

coupling for the power supply. For a multilayer PC board

with a power plane, connecting all of the V

power plane would be the optimal power distribution

method. The integrated circuit layout and packaging

considerations for the 3 V V

DD

essentially the same as for the V

pins to the

DD

power circuit are

ground circuit.

2. Keep radio frequency signals as far away from the audio

signals as possible.

SS

8. The V

AG

pin is the reference for all analog signal

processing. In some applications the audio signal to be

digitized may be referenced to the V ground. To

3. Use short, low inductance traces for the audio circuitry

to reduce inductive, capacitive, and radio frequency

noise sensitivities.

SS

reduce the susceptibility to noise at the input of the ADC

section, the three–terminal op amp may be used in a

differential to single–ended circuit to provide level

4. Use short, low inductance traces for digital and RF

circuitry to reduce inductive, capacitive, and radio

frequency radiated noise.

conversion from the V

ground to the V ground with

SS

AG

noise cancellation. The op amp may be used for more

than30dBofgaininmicrophoneinterfacecircuits, which

will require a compact layout with minimum trace lengths

as well as isolation from noise sources. It is recom-

mended that the layout be as symmetrical as possible to

avoid any imbalances which would reduce the noise

cancelling benefits of this differential op amp circuit.

Refer to the application schematics for examples of this

circuitry.

5. Bypass capacitors should be connected from the V

,

DD

V

Ref, andV pinstoV withminimaltracelength.

AG

SS

Ceramic monolithic capacitors of about 0.1 µF are

acceptablefortheV andV Refpinstodecouplethe

DD AG

device from its own noise. The V

capacitor helps

DD

supply the instantaneous currents of the digital circuitry

in addition to decoupling the noise which may be

generated by other sections of the device or other

circuitry on the power supply. The V

capacitor is effecting a low–pass filter to isolate the

mid–supply voltage from the power supply noise gener-

Ref decoupling

AG

If possible, reference audio signals to the V

pin. Handset receivers and tele-

AG

instead of to the V

SS

ated on–chip as well as external to the device. The V

phone line interface circuits using transformers may be

audio signal referenced completely to the V pin. Re-

AG

decoupling capacitor should be about 0.01 µF. This

helps to reduce the inpedance of the V pin to V at

AG

fer to the application schematics for examples of this

circuitry. The V pin cannot be used for ESD or line

AG SS

frequencies above the bandwidth of the V generator,

AG

which reduces the susceptibility to RF noise.

AG

protection.

For More Information On This Product,

Go to: www.freescale.com

10

Freescale Semiconductor, Inc.

MAXIMUM RATINGS (Voltages Referenced to V

Pin)

SS

Rating

Symbol

Value

Unit

V

DC Supply Voltage

V

DD

– 0.5 to 6

Voltage on Any Analog Input or Output Pin

Voltage on Any Digital Input or Output Pin

Operating Temperature Range

Storage Temperature Range

V

– 0.3 to V

+ 0.3

V

SS

DD

V

SS

T

– 40 to + 85

– 85 to +150

°C

A

T

stg

POWER SUPPLY (T = – 40 to + 85°C)

A

Characteristics

Min

Typ

Max

Unit

V

DC Supply Voltage

2.7

3.0

5.25

Active Power Dissipation (V

= 3 V)

(No Load, PI ≥ V

(No Load, PI ≤ V

– 0.5 V)

– 1.0 V)

—

2.0

2.2

2.8

3.0

mA

DD

Power–Down Current (V

DD

= 3 V, V for Logic Levels

IH

PDI = V

FST and FSR = V , PDI = V

—

1.0

10.0

80

100

µA

SS

DD

Must be ≥ V

– 0.5 V)

DD

SS

DIGITAL LEVELS (V

= 2.7 to 3.6 V, V = 0 V, T = – 40 to + 85°C)

SS A

DD

Characteristics

Symbol

Min

—

Max

0.6

—

Unit

V

Input Low Voltage

Input High Voltage

V

IL

V

IH

2.2

—

V

Output Low Voltage (DT Pin, I = 1.6 mA)

OL

V

OL

0.4

—

V

Output High Voltage (DT Pin, I

OH

= – 1.6 mA)

V

I

V

– 0.5

V

OH

DD

Input Low Current (V

≤ V ≤ V

in DD

)

I

IL

– 10

—

+ 10

10

µA

pF

SS

Input High Current (V

≤ V ≤ V

in DD

)

SS

IH

Output Current in High Impedance State (V

SS

≤ DT ≤ V

DD

)

I

OZ

Input Capacitance of Digital Pins (Except DT)

Input Capacitance of DT Pin when High–Z

C

in

C

—

15

out

For More Information On This Product,

Go to: www.freescale.com

11

Freescale Semiconductor, Inc.

ANALOG ELECTRICAL CHARACTERISTICS (V

= 2.7 to 3.6 V, V = 0 V, T = – 40 to + 85°C)

SS A

DD

Characteristics

Min

—

Typ

Max

± 1.0

—

Unit

µA

Input Current

TI+, TI–

± 0.1

—

Input Resistance to V

(V

AG AG

– 0.3 V ≤ V ≤ V

in AG

+ 0.3 V)

10

—

MΩ

pF

Input Capacitance

—

10

Input Offset Voltage of TG Op Amp

Input Common Mode Voltage Range

Input Common Mode Rejection Ratio

—

± 5

mV

V

1.2

—

V – 1.2

DD

60

3000

95

—

dB

Gain Bandwidth Product (10 kHz) of TG Op Amp (R ≥ 10 kΩ)

—

kHz

dB

L

DC Open Loop Gain of TG Op Amp (R ≥ 10 kΩ)

—

L

Equivalent Input Noise (C–Message) Between TI+ and TI– at TG

Output Load Capacitance for TG Op Amp

—

– 28

—

dBrnC

pF

0

100

Output Voltage Range for TG

Output Current (0.5 V ≤ V

(R = 2 kΩ to V

AG

)

0.4

± 1.0

2

—

V

DD

– 0.4

V

L

≤ V

– 0.5 V)

TG, RO–

RO–

—

mA

kΩ

Ω

out

DD

Output Load Resistance to V

Output Impedance

—

AG

—

1

—

Output Load Capacitance

RO–

0

—

200

± 25

/2 + 0.05

—

pF

DC Output Offset Voltage of RO– Referenced to V

AG

—

mV

V

AG

Output Voltage Referenced to V

(No Load)

V

DD

/2 – 0.05

V

/2

V

DD

SS

DD

V

AG

Output Current with ± 25 mV Change in Output Voltage

± 1.0

± 2.0

mA

dBC

Power Supply Rejection Ratio , V

DD

= 3.0 V

Transmit

Receive

40

60

—

(0 to 100 kHz @100 mVrms Applied to V

,

DD

C–Message Weighting, All Analog Signals

Referenced to V Pin)

AG

Power Drivers PI, PO+, PO–

Input Current (V

AG

– 0.3 V ≤ PI ≤ V

AG

+ 0.3 V)

PI

—

10

—

± 0.05

—

± 1.0

—

µA

MΩ

mV

mA

Ω

Input Resistance (V

AG

– 0.3 V ≤ PI ≤ V + 0.3 V)

AG

Input Offset Voltage

Output Offset Voltage of PO+ Relative to PO– (Inverted Unity Gain for PO–)

Output Current (V + 0.4 V ≤ PO+ or PO– ≤ V – 0.4 V)

—

± 20

± 50

—

± 6

—

SS

DD

PO+ or PO– Output Resistance (Inverted Unity Gain for PO–)

Gain Bandwidth Product (10 kHz, Open Loop for PO–)

1

—

1000

—

kHz

pF

Load Capacitance (PO+ or PO– to V , or PO+ to PO–)

AG

0

1000

+ 0.2

Gain of PO+ Relative to PO– (R = 300 Ω, + 3 dBm0 @ 1 kHz)

– 0.2

0

dB

L

Total Signal to Distortion at PO+ and PO– with a Differential Load of:

300 Ω

45

—

60

40

—

dBC

100 nF in series with ≥ 20 Ω

≥ 100 Ω

Power Supply Rejection Ratio

(0 to 25 kHz @ 50 mVrms Applied to V

0 to 4 kHz

4 to 25 kHz

40

—

55

40

—

dB

.

DD

PO– Connected to PI. Differential or Measured

Referenced to V Pin.)

AG

For More Information On This Product,

Go to: www.freescale.com

12

Freescale Semiconductor, Inc.

ANALOG TRANSMISSION PERFORMANCE

(V

DD

= 2.7 to 3.6 V, V

= 0 V, All Analog Signals Referenced to V , 0 dBm0 = 0.436 Vrms = – 5 dBm @ 600 Ω, FST = FSR = 8 kHz,

SS

AG

BCLKT = MCLK = 2.048 MHz Synchronous Operation, T = – 40 to + 85°C, Unless Otherwise Noted)

A

A/D

D/A

Typ

0.886

—

Characteristics

Units

Vpk

dB

Min

—

Typ

0.886

—

Max

Min

Max

—

Peak Single Frequency Tone Amplitude without Clipping

T

max

—

Absolute Gain (0 dBm0 @ 1.02 kHz, T = 25°C, V

= 3.0 V)

– 0.25

+ 0.25 – 0.25

+ 0.25

A

DD

Absolute Gain Variation with Temperature @ 3.0 V

(Referenced to 25°C, V

= 3.0 V)

– 40 to + 85°C

—

± 0.02 ± 0.05

—

± 0.02 ± 0.05

dB

DD

—

Absolute Gain Variation with Power Supply (T = 25°C)

—

± 0.02 ± 0.05

—

± 0.02 ± 0.05

A

Gain vs Level Tone (Mu–Law, Relative to – 10 dBm0, 1.02 kHz)

+ 3 to – 40 dBm0 – 0.20

– 40 to – 50 dBm0 – 0.40

– 50 to – 55 dBm0 – 0.80

—

+ 0.20 – 0.20

+ 0.40 – 0.40

+ 0.80 – 0.80

—

+ 0.20

+ 0.40

+ 0.80

Gain vs Level Pseudo Noise, CCITT G.712

(A–Law, Relative to – 10 dBm0)

– 10 to – 40 dBm0 – 0.25

– 40 to – 50 dBm0 – 0.30

– 50 to – 55 dBm0 – 0.45

—

+ 0.25 – 0.25

+ 0.30 – 0.30

+ 0.45 – 0.45

—

+ 0.25

+ 0.30

+ 0.45

dB

dBC

dB

Total Distortion, 1.02 kHz Tone (Mu–Law, C–Message Weighting)

+ 3 dBm0

0 to – 30 dBm0

– 40 dBm0

34

35.5

30

—

34

36

30

25

—

– 45 dBm0

25

Total Distortion, Pseudo Noise, CCITT G.714 (A–Law)

– 3 dBm0

– 6 to – 27 dBm0

– 34 dBm0

30

—

30

36

34.2

30

—

35.0

34.5

28.5

13.5

– 40 dBm0

– 55 dBm0

15

Idle Channel Noise (For A/D, See Note 1)

(Mu–Law, C–Message Weighted)

(A–Law, Psophometric Weighted)

—

18

– 69

—

14

– 76

dBrnc0

dBm0p

Frequency Response (Relative to 1.02 kHz @ 0 dBm0)

15 Hz

50 Hz

60 Hz

—

– 3

—

– 3

—

– 40

– 30

– 26

—

– 0.5

—

– 3

—

0

dB

165 Hz

200 Hz – 1.0

300 to 3000 Hz – 0.20

3000 to 3200 Hz – 0.20

3300 Hz – 0.35

– 0.4

+ 0.20 – 0.20

+ 0.20 – 0.35

0

—

+ 0.20

0

—

– 14

– 30

3400 Hz – 0.85

3600 Hz

4000 Hz

– 0.85

—

– 14

– 32

4600 Hz to 100 kHz

—

In–Band Spurious (1.02 kHz @ 0 dBm0, Transmit and Receive)

300 to 3200 Hz

dB

—

48

—

48

Out–of–Band Spurious at V

AG

Ref (300 to 3400 Hz @ 0 dBm0 in)

4600 to 7600 Hz

7600 to 8400 Hz

—

– 30

– 40

– 30

8400 to 100,000 Hz

Idle Channel Noise Selective (8 kHz, Input = V , 30 Hz Bandwidth)

AG

—

– 70

205

dBm0

µs

Absolute Delay (1600 Hz)

315

Group Delay Referenced to 1600 Hz

500 to 600 Hz

—

210

130

70

35

70

– 40

– 30

—

85

µs

600 to 800 Hz

800 to 1000 Hz

1000 to 1600 Hz

1600 to 2600 Hz

2600 to 2800 Hz

2800 to 3000 Hz

95

145

—

110

175

Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2)

—

– 90

– 75

—

– 90

– 75

dB

Intermodulation Distortion of Two Frequencies of Amplitudes

(– 4 to – 21 dBm0 from the Range 300 to 3400 Hz)

—

– 41

—

– 41

NOTES:

1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.

2. Selectively measured while stimulated with 2667 Hz @ – 50 dBm0.

For More Information On This Product,

Go to: www.freescale.com

13

Freescale Semiconductor, Inc.

DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC

(V

DD

= 2.7 to 3.6 V, V

= 0 V, All Digital Signals Referenced to V , T = – 40 to + 85°C, C = 150 pF, Unless Otherwise Noted)

SS

A

L

Ref.

No.

Characteristics

Min

Typ

Max

Unit

1

Master Clock Frequency for MCLK

—

256

512

—

kHz

1536

1544

2048

2560

4096

1

2

MCLK Duty Cycle for 256 kHz Operation

45

50

—

50

64

50

20

80

0

—

55

—

%

ns

kHz

ns

Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)

Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)

Rise Time for All Digital Signals

3

—

4

50

—

5

Fall Time for All Digital Signals

6

Setup Time from MCLK Low to FST High

7

Setup Time from FST High to MCLK Low

—

8

Bit Clock Data Rate for BCLKT or BCLKR

4096

—

9

Minimum Pulse Width High for BCLKT or BCLKR

Minimum Pulse Width Low for BCLKT or BCLKR

Hold Time from BCLKT (BCLKR) Low to FST (FSR) High

Setup Time for FST (FSR) High to BCLKT (BCLKR) Low

Setup Time from DR Valid to BCLKR Low

10

11

12

13

14

—

Hold Time from BCLKR Low to DR Invalid

50

—

LONG FRAME SPECIFIC TIMING

15

16

17

18

Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low

Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data

Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data

50

—

10

—

60

ns

Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge

of FST to DT Output High Impedance

19

Minimum Pulse Width Low for FST or FSR

50

—

ns

SHORT FRAME SPECIFIC TIMING

20

21

22

23

Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low

Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low

Delay Time from BCLKT High to DT Data Valid

50

10

—

60

ns

Delay Time from the 8th BCLKT Low to DT Output High Impedance

For More Information On This Product,

Go to: www.freescale.com

14

Freescale Semiconductor, Inc.

Figure 3. Long Frame Sync Timing

For More Information On This Product,

Go to: www.freescale.com

15

Freescale Semiconductor, Inc.

Figure 4. Short Frame Sync Timing

For More Information On This Product,

Go to: www.freescale.com

16

Freescale Semiconductor, Inc.

DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE

(V

DD

= 2.7 to 3.6 V, T = – 40 to + 85°C, C = 150 pF, See Figure 5 and Note 1)

A L

Ref.

No.

31

32

33

34

35

36

37

38

39

40

41

Characteristics

Min

Max

Unit

Time Between Successive IDL Syncs

Note 2

Hold Time of IDL SYNC After Falling Edge of IDL CLK

Setup Time of IDL SYNC Before Falling Edge IDL CLK

IDL Clock Frequency

20

60

256

50

20

75

10

—

ns

kHz

ns

4096

—

IDL Clock Pulse Width High

IDL Clock Pulse Width Low

—

Data Valid on IDL RX Before Falling Edge of IDL CLK

Data Valid on IDL RX After Falling Edge of IDL CLK

Falling Edge of IDL CLK to High–Z on IDL TX

Rising Edge of IDL CLK to Low–Z and Data Valid on IDL TX

Rising Edge of IDL CLK to Data Valid on IDL TX

—

50

60

50

NOTES:

1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.

2. In IDL mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words

are accessed during the B2 channel as shown in Figure 5. IDL accesses must occur at a rate of 8 kHz (125 µs interval).

Figure 5. IDL Interface Timing

For More Information On This Product,

Go to: www.freescale.com

17

Freescale Semiconductor, Inc.

DIGITAL SWITCHING CHARACTERISTICS FOR GCI MODE

(V

DD

= 2.7 to 3.6 V, T = – 40 to + 85°C, C = 150 pF, See Figure 6 and Note 1)

A L

Ref.

No.

42

43

44

45

46

47

48

49

50

51

52

53

Characteristics

Min

Max

Unit

Time Between Successive FSC Pulses

DCL Clock Frequency

Note 2

512

50

20

60

—

6176

—

kHz

ns

DCL Clock Pulse Width High

DCL Clock Pulse Width Low

—

Hold Time of FSC After Falling Edge of DCL

Setup Time of FSC to DCL Falling Edge

Rising Edge of DCL (After Rising Edge of FSC) to Low Impedance and Valid Data of D

—

60

50

—

out

Rising Edge of FSC (While DCL is High) to Low Impedance and Valid Data of D

out

—

Rising Edge of DCL to Valid Data on D

out

—

Second DCL Falling Edge During LSB to High Impedance of D

out

10

20

—

Setup Time of D Before Rising Edge of DCL

in

Hold Time of D After DCL Rising Edge

in

60

NOTES:

1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.

2. In GCI mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words

are accessed during the B2 channel as shown in Figure 6. GCI accesses must occur at a rate of 8 kHz (125 µs interval).

Figure 6. GCI Interface Timing

For More Information On This Product,

Go to: www.freescale.com

18

Freescale Semiconductor, Inc.

µ

Ω

µ

Ω

µ

Ω

µ

Figure 7. MC145481 Test Circuit — Signals Referenced to V

AG

µ

Ω

µ

Ω

≥

Ω

µ

Ω

≥

Ω

µ

Figure 8. MC145481 Test Circuit — Signals Referenced to V

SS

For More Information On This Product,

Go to: www.freescale.com

19

Freescale Semiconductor, Inc.

Ω

µ

Figure 9. Long Frame Sync Clock Circuit for 2.048 MHz

Ω

µ

Ω

µ

Ω

µ

Figure 10. MC145481 Analog Interface to Handset

For More Information On This Product,

Go to: www.freescale.com

20

Freescale Semiconductor, Inc.

µ

Ω

µ

Ω

µ

Figure 11. MC145481 Step–Up Transformer Line Interface

For More Information On This Product,

Go to: www.freescale.com

21

Freescale Semiconductor, Inc.

PACKAGE DIMENSIONS

DW SUFFIX

SOG PACKAGE

CASE 751D–04

–A–

10X P

–B–

20X D

J

F

R X 45

C

–T–

M

18X G

K

SD SUFFIX

SSOP

CASE 940C–02

B

–R–

C

A

–P–

N

L

J

M

G

F

H

D

NOTE 4

For More Information On This Product,

Go to: www.freescale.com

22

Freescale Semiconductor, Inc.

This page intentionally left blank.

For More Information On This Product,

Go to: www.freescale.com

23

Freescale Semiconductor, Inc.

Home Page:

www.freescale.com

email:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

(800) 521-6274

480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku

Tokyo 153-0064, Japan

0120 191014

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

+81 2666 8080

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be

provided in Freescale Semiconductor data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate,

Tai Po, N.T., Hong Kong

+800 2666 8080

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor

Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

(800) 441-2447

303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor

@hibbertgroup.com

Semiconductor was negligent regarding the design or manufacture of the part.

MC145481/D

◊

For More Information On This Product,

Go to: www.freescale.com


型号：	MC34129D
厂家：	NXP
描述：	IC,SMPS CONTROLLER,CURRENT-MODE,BIPOLAR,SOP,14PIN,PLASTIC 开关光电二极管
文件：	总24页 (文件大小：560K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC34129D [NXP]

相关型号：

MC34129EF

MC34129P

MC34129P

MC3412L

MC3414

MC34142FN

MC34151

MC34151D

MC34151D

MC34151DG

MC34151DR2

MC34151DR2G