MC34910BAC,557_技术文档

MC33910G5AC/MC3433910G5AC

Document Number: MC33910

Rev. 9.0, 7/2016

NXP Semiconductors

Technical Data

LIN system basis chip with

high-side drivers

33910

The 33910G5/BAC is a SMARTMOS Serial Peripheral Interface (SPI) controlled

System Basis Chip (SBC), combining many frequently used functions in an MCU

based system, plus a Local Interconnect Network (LIN) transceiver. The 33910

has a 5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting

features. The device provides full SPI readable diagnostics and a selectable

timing watchdog for detecting errant operation. The LIN Protocol Specification

2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry which can be

disabled for higher data rates.

SYSTEM BASIS CHIP WITH LIN

2^NDGENERATION

Two 50 mA/60 mA high-side switches with optional pulse-width modulated

(PWM) are implemented to drive small loads. One high voltage input is available

for use in contact monitoring, or as external wake-up input. This input can be

used as high voltage Analog Input. The voltage on this pin is divided by a

selectable ratio and available via an analog multiplexer.

The 33910 has three main operating modes: Normal (all functions available),

Sleep (V_DDoff, wake-up via LIN, wake-up inputs (L1), cyclic sense and forced

wake-up), and Stop (V_DDon with limited current capability, wake-up via CS, LIN

bus, wake-up inputs, cyclic sense, forced wake-up and external reset).

AC SUFFIX (Pb-FREE)

98ASH70029A

The 33910 is compatible with LIN Protocol Specification 2.0, 2.1, and

SAEJ2602-2.

32-PIN LQFP

Features

• Full-duplex SPI interface at frequencies up to 4.0 MHz

• LIN transceiver capable of up to 100 kbps with wave shaping

• Two 50 mA/60 mA high-side switches

• One high voltage analog/logic Input

• Configurable window watchdog

Applications

• Window lift

• Mirror switch

• Door lock

• Sunroof

• 5.0 V low drop regulator with fault detection and low voltage reset (LVR)

circuitry

• Light control

• Switched/protected 5.0 V output (used for Hall sensors)

33910

V_BAT

VSENSE

HS1

VS1

VS2

L1

VDD

PWMIN

ADOUT0

LIN INTERFACE

LIN

MCU

MOSI

MISO

SCLK

CS

RXD

TXD

IRQ

HVDD

HS2

WDCONF

RST

Figure 1. 33910 simplified application diagram

1

Orderable parts

The 33910G5 data sheet is within MC33910G5 product specifications - page 3 to page 49

The 33910BAC data sheet is within MC33911BAC product specifications - page 50 to page 95

Table 1. Orderable part variations ⁽¹⁾

Device

Temperature

Package

Changes

MC33910G5AC/R2

-40 °C to 125 °C

• Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 Ω test

conditions) performance to achieve 6.0 kV min on the LIN pin.

• Immunity against ISO7637 pulse 3b

• Reduce EMC emission level on LIN

• Improve EMC immunity against RF – target new specification including 3x68 pF

• Comply with J2602 conformance test

MC34910G5AC/R2

-40 °C to 85 °C

32 LQFP

MC33910BAC/R2

MC34910BAC/R2

-40 °C to 125 °C

-40 °C to 85 °C

Initial release

Notes

1. To order parts in Tape & Reel, add the R2 suffix to the part number.

33910

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NXP Semiconductors

1

MC33910G5 product specifications - page 3 to page 49

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NXP Semiconductors

3

2

Internal block diagram

RST IRQ

VS2

VS1

VDD

INTERRUPT CONTROL

MODULE

AGND

PGND

VOLTAGE REGULATOR

LVI, HVI,

ALL OT (VDD, HS, LIN, SD)

RESET CONTROL

MODULE

LVR, WD, EXT ΜC

5.0 V OUTPUT

MODULE

HVDD

WINDOW

WATCHDOG

MODULE

VS2

HIGH-SIDE

CONTROL

MODULE

PWMIN

HS1

HS2

VS2

MISO

MOSI

SCLK

SPI

&

CONTROL

V_BAT

SENSE MODULE

VSENSE

CS

CHIP TEMPERATURE

SENSE MODULE

ADOUT0

L1

ANALOG INPUT

MODULE

WAKE-UP MODULE

DIGITAL INPUT MODULE

RXD

TXD

LIN PHYSICAL

LAYER

LIN

LGND

WDCONF

Figure 2. 33910 simplified internal block diagram

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NXP Semiconductors

3

Pin connections

3.1

Pinout diagram

RXD

TXD

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

HS2

L1

MISO

NC*

PGND

NC*

MOSI

SCLK

CS

ADOUT0

PWMIN

* See Recommendation in Table below

Figure 3. 33910 pin connections

3.2

Pin definitions

A functional description of each pin can be found in the Functional pin description.

Table 2. 33910 pin definitions

Pin name

Formal name

Definition

This pin is the receiver output of the LIN interface which reports the state of the bus voltage

to the MCU interface.

1

2

3

RXD

TXD

Receiver Output

Transmitter Input

SPI Output

This pin is the transmitter input of the LIN interface which controls the state of the bus output.

SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the high-impedance

state.

MISO

4

5

6

7

8

MOSI

SCLK

SPI Input

SPI Clock

SPI (Serial Peripheral Interface) data input.

SPI (Serial Peripheral Interface) clock Input.

CS

SPI Chip Select

SPI (Serial Peripheral Interface) chip select input pin. CS is active low.

ADOUT0

PWMIN

Analog Output Pin 0 Analog Multiplexer Output.

PWM Input High-side Pulse Width Modulation Input.

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NXP Semiconductors

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Table 2. 33910 pin definitions (continued)

Pin name

Formal name

Definition

Bidirectional Reset I/O pin - driven low when any internal reset source is asserted. RST is

active low.

9

RST

Internal Reset I/O

Internal Interrupt

Output

Interrupt output pin, indicating wake-up events from Stop modemode or events from Normal

and Normal request modes. IRQ is active low.

10

11

12

IRQ

NC

Not Connected

This pin must not be connected.

Watchdog

Configuration Pin

This input pin is for configuration of the watchdog period and allows the disabling of the

watchdog.

WDCONF

13

14

LIN

LIN Bus

This pin represents the single-wire bus transmitter and receiver.

LGND

LIN Ground Pin

This pin is the device LIN ground connection. It is internally connected to the PGND pin.

15, 16, 17, 19,

20, 21 & 22

NC

PGND

L1

Not Connected

Power Ground Pin

Wake-up Input

This pin must not be connected or connected to ground.

18

23

This pin is the device low-side ground connection. It is internally connected to the LGND pin.

This pin is the wake-up capable digital input⁽²⁾. In addition, L1 input can be sensed analog

via the analog multiplexer.

24

25

HS2

HS1

High-side Outputs

Power Supply Pin

High-side switch outputs.

26

27

VS2

VS1

These pins are device battery level power supply pins. VS2 is supplying the HSx drivers

while VS1 supplies the remaining blocks.⁽³⁾

28

29

NC

Not Connected

This pin can be left opening or connected to any potential ground or power supply

Battery voltage sense input.⁽⁴⁾

VSENSE

Voltage Sense Pin

Hall Sensor Supply

Output

30

31

HVDD

+5.0 V switchable supply output pin.⁽⁵⁾

Voltage Regulator

Output

VDD

+5.0 V main voltage regulator output pin.⁽⁶⁾

32

AGND

Analog Ground Pin

This pin is the device analog ground connection.

Notes

2. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.

3. Reverse battery protection series diodes must be used externally to protect the internal circuitry.

4. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It is

strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

5. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.

6. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required.

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NXP Semiconductors

4

Electrical characteristics

4.1

Maximum ratings

Table 3. Maximum ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Ratings

Value

Unit

Notes

Electrical ratings

Supply Voltage at VS1 and VS2

• Normal Operation (DC)

• Transient Conditions (load dump)

V_SUP(SS)

V_SUP(PK)

-0.3 to 27

-0.3 to 40

V

V_DD

Supply Voltage at VDD

-0.3 to 5.5

(7)

(8)

Input/Output Pins Voltage

• CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD, HVDD

• Interrupt Pin (IRQ)

V_IN

-0.3 to V_DD+0.3

-0.3 to 11

V

V_IN(IRQ)

V_HS

-0.3 to V_SUP+0.3

HS1 and HS2 Pin Voltage (DC)

L1 Pin Voltage

• Normal Operation with a series 33 k resistor (DC)

• Transient input voltage with external component (according to ISO7637-2)

(See Figure 5)

V_L1DC

V_L1TR

-18 to 40

±100

V

A

V_VSENSE

VSENSE Pin Voltage (DC)

-27 to 40

LIN Pin Voltage

• Normal Operation (DC)

• Transient input voltage with external component (according to ISO7637-2)

(See Figure 5)

V_BUSDC

V_BUSTR

-18 to 40

-150 to 100

I_VDD

VDD Output Current

Internally Limited

ESD Capability

• AECQ100

V_ESD1-1

V_ESD1-2

V_ESD1-3

• Human Body Model - JESD22/A114 (C

= 100 pF, R

= 1500 Ω)

ZAP

±8.0 k

±6.0 k

±2000

• LIN Pin

• L1

• all other Pins

• Charge Device Model - JESD22/C101 (C

= 4.0 pF)

±750

±500

V_ESD2-1

V_ESD2-2

ZAP

• Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)

• All other Pins (Pins 2-7, 10-15, 18-23, 26-31)

• According to LIN Conformance Test Specification / LIN EMC Test

Specification, August 2004 (C = 150 pF, R = 330 Ω)

V

ZAP

±20 k

±11 k

>±12 k

±6000

• Contact Discharge, Unpowered

• LIN pin with 220 pF

• LIN pin without capacitor

V_ESD3-1

V_ESD3-2

V_ESD3-3

V_ESD3-4

• VS1/VS2 (100 nF to ground)

• L1 input (33 kΩ serial resistor)

• According to IEC 61000-4-2 (C

= 150 pF, R

= 330 Ω)

ZAP

• Unpowered

• LIN pin with 220 pF and without capacitor

• VS1/VS2 (100 nF to ground)

V_ESD4-1

V_ESD4-2

V_ESD4-3

±8000

• L1 input (33 kΩ serial resistor)

Notes

7. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.

8. Extended voltage range for programming purpose only.

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Table 3. Maximum ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Ratings

Value

Unit

Notes

Thermal ratings

Operating Ambient Temperature

• 33910

• 34910

(9)

T

A

-40 to 125

-40 to 85

°C

T

J

Operating Junction Temperature

Storage Temperature

-40 to 150

-55 to 150

°C

T_STG

Thermal Resistance, Junction to Ambient

Natural Convection, Single Layer board (1s)

Natural Convection, Four Layer board (2s2p)

(9), (10)

(9), (11)

R_θJA

85

56

°C/W

(12)

R_θJC

Thermal Resistance, Junction to Case

23

°C/W

(13), (14)

T_PPRT

Peak Package Reflow Temperature During Reflow

Note 14

°C

Notes

9. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

10. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

11. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

12. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

13. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

14. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

Moisture Sensitivity Levels (MSL), go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all

orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

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NXP Semiconductors

4.2

Static electrical characteristics

Table 4. Static electrical characteristics

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Supply voltage range (VS1, VS2)

V_SUP

5.5

–

18

27

40

V

Nominal Operating Voltage

Functional Operating Voltage

Load Dump

(15)

V_SUPOP

V_SUPLD

–

Supply current range (V_SUP= 13.5 V)

(16)

I_RUN

Normal Mode (I_OUTat V

= 10 mA), LIN Recessive State

–

4.5

10

mA

µA

DD

Stop Mode, VDD ON with I_OUT= 100 µA, LIN Recessive State

• 5.5 V < V_SUP< 12 V

(16), (17),

–

47

62

180

80

90

400

I_STOP

(18) (19)

• V_SUP= 13.5 V

,

• 13.5 V < V_SUP< 18 V

Sleep Mode, VDD OFF, LIN Recessive State

• 5.5 V < V_SUP< 12 V

–

27

33

160

35

48

300

(16), (18)

(20)

I_SLEEP

µA

• V_SUP= 13.5 V

• 13.5 V ≤ V_SUP< 18 V

I_CYCLIC

Cyclic Sense Supply Current Adder

–

10

–

Supply under/overvoltage detections

Power-On Reset (BATFAIL)

V_BATFAIL

(21) (20)

1.5

–

3.0

0.9

3.9

–

• Threshold (measured on VS1)

• Hysteresis (measured on VS1)

V

,

V_{BATFAIL_HYS}

V_SUPUndervoltage Detection (VSUV Flag) (Normal and Normal

Request Modes, Interrupt Generated)

• Threshold (measured on VS1)

• Hysteresis (measured on VS1)

V_SUV

V_{SUV_HYS}

5.55

–

6.0

0.2

6.6

–

V_SUPOvervoltage Detection (VSOV Flag) (Normal and Normal

Request Modes, Interrupt Generated)

• Threshold (measured on VS1)

• Hysteresis (measured on VS1)

V

V_SOV

V_{SOV_HYS}

18

–

19.25

1.0

20.5

–

Notes

15. Device is fully functional. All features are operating.

16. Total current (I_VS1+ I_VS2) measured at GND pins excluding all loads, cyclic sense disabled.

17. Total I_DDcurrent (including loads) below 100 µA.

18. Stop and Sleep modes current increases if V_SUPexceeds13.5 V.

19. This parameter is guaranteed after 90 ms.

20. This parameter is guaranteed by process monitoring but not production tested.

21. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.

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9

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Voltage regulator ⁽²²⁾(VDD)

Normal Mode Output Voltage

• 1.0 mA < I < 50 mA; 5.5 V < V

V_DDRUN

I_VDDRUN

V_DDDROP

4.75

60

–

5.00

110

0.1

5.25

200

V

mA

V

< 27 V

SUP

VDD

Normal Mode Output Current Limitation

Dropout Voltage

(23)

0.25

• I

= 50 mA

VDD

Stop Mode Output Voltage

• I < 5.0 mA

V

4.75

6.0

5.0

13

5.25

36

V

DDSTOP

VDD

I

Stop Mode Output Current Limitation

Line Regulation

mA

VDDSTOP

LR

• Normal mode, 5.5 V < V

< 18 V; I

= 10 mA

VDD

RUN

–

25

mV

SUP

LR

• Stop mode, 5.5 V < V

< 18 V; I

= 1.0 mA

VDD

STOP

SUP

Load Regulation

LD

• Normal mode, 1.0 mA < I

< 50 mA

RUN

–

80

50

mV

°C

VDD

LD

• Stop mode, 0.1 mA < I

< 5.0 mA

STOP

VDD

Overtemperature Prewarning (Junction)

• Interrupt generated, VDDOT Bit Set

(24)

T

PRE

90

–

115

13

140

–

(24)

T

Overtemperature Prewarning Hysteresis

°C

PRE_HYS

T

Overtemperature Shutdown Temperature (Junction)

Overtemperature Shutdown Hysteresis

150

–

170

13

190

–

SD

T

SD_HYS

Hall sensor supply output ⁽²⁵⁾(HVDD)

V

Voltage matching H_VDDACC= (HVDD-VDD) / VDD * 100%

DD

H

-2.0

20

–

2.0

50

%

VDDACC

• I_HVDD= 15 mA

I

Current Limitation

35

mA

mV

HVDD

Dropout Voltage

• I_{HVDD =}15 mA; I_VDD= 5.0 mA

H

160

300

VDDDROP

Line Regulation

• I_HVDD= 5.0 mA; I_VDD= 5.0 mA

LR

LD

–

40

20

mV

HVDD

Load Regulation

• 1.0 mA > I_HVDD> 15 mA; I_VDD= 5.0 mA

Notes

22. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

23. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).

24. This parameter is guaranteed by process monitoring but not production tested.

25. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

33910

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NXP Semiconductors

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

RST input/output pin (RST)

V_RSTTH

V_OL

VDD Low Voltage Reset Threshold

4.3

0.0

4.5

–

4.7

0.9

V

Low-state Output Voltage

• I_OUT= 1.5 mA; 3.5 V ≤ V_SUP≤ 27 V

I_OH

High-state Output Current (0 V < V_OUT< 3.5 V)

-150

1.5

-250

–

-350

8.0

µA

mA

Pull-down Current Limitation (internally limited)

V_OUT= V_DD

I_{PD_MAX}

V_IL

V_IH

0.3 x V_DD

V_DD+0.3

Low-state Input Voltage

High-state Input Voltage

-0.3

–

V

0.7 x V_DD

MISO SPI output pin (MISO)

Low-state Output Voltage

• I = 1.5 mA

V_OL

0.0

–

1.0

V

OUT

High-state Output Voltage

• I_OUT= -250 µA

V_OH

V_DD-0.9

V_DD

Tri-state Leakage Current

I_TRIMISO

-10

10

µA

• 0 V ≤ V_MISO≤ V_DD

SPI input pins (MOSI, SCLK, CS)

V_IL

V_IH

0.3 x V_DD

V_DD+0.3

Low-state Input Voltage

High-state Input Voltage

-0.3

–

V

0.7 x V_DD

MOSI, SCLK Input Current

I_IN

-10

10

–

10

30

µA

• 0 V ≤ V_IN≤ V_DD

CS Pull-up Current

• 0 V < V_IN< 3.5 V

I_PUCS

20

Interrupt output pin (IRQ)

Low-state Output Voltage

• I_OUT= 1.5 mA

V_OL

V_OH

I_OUT

0.0

–

0.8

V

High-state Output Voltage

• I_OUT= -250 µA

V_DD-0.8

V_DD

Leakage Current

• V_DD≤ V_OUT≤ 10 V

–

2.0

mA

Pulse width modulation input pin (PWMIN)

V_IL

V_IH

0.3 x V_DD

V_DD+0.3

Low-state Input Voltage

High-state Input Voltage

-0.3

–

V

0.7 x V_DD

Pull-up current

• 0 V < V_IN< 3.5 V

I_PUPWMIN

10

20

30

µA

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Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

High-side outputs HS1 and HS2 pins (HS1, HS2)

Output Drain-to-Source On Resistance

• T_J= 25 °C, I_LOAD= 50 mA; V_SUP> 9.0 V

–

7.0

10

14

R_DS(on)

Ω

(26)

• T_J= 150 °C, I_LOAD= 50 mA; V_SUP> 9.0 V

• T_J= 150 °C, I_LOAD= 30 mA; 5.5 V < V_SUP< 9.0 V

Output Current Limitation

I_LIMHSX

(27)

(28)

60

–

90

5.0

–

250

7.5

10

mA

µA

• 0 V < V_OUT< V_SUP- 2.0 V

I_OLHSX

I_LEAK

Open Load Current Detection

Leakage Current

• -0.2 V < V_HSX< V_S2+ 0.2 V

–

Short-circuit Detection Threshold

• 5.5 V < V_SUP< 27 V

(29)

V_THSC

V_SUP-2.0

–

V

(30), (31)

(31)

T_HSSD

T_{HSSD_HYS}

Overtemperature Shutdown

140

–

160

10

180

–

°C

Overtemperature Shutdown Hysteresis

L1 input pin (L1)

Low Detection Threshold

• 5.5 V < V_SUP< 27 V

(32)

V_THL

V_THH

V_HYS

2.0

3.0

0.4

2.5

3.5

0.8

3.0

4.0

1.4

V

High Detection Threshold

• 5.5 V < V_SUP< 27 V

Hysteresis

• 5.5 V < V_SUP< 27 V

Input Current

• -0.2 V < V_IN< VS1

(33)

(34)

I_IN

-10

–

10

µA

R_L1IN

Analog Input Impedance

800

1300

2000

kΩ

Analog Input Divider Ratio (RATIO_L1= V_L1/ V_ADOUT0

• L1DS (L1 Divider Select) = 0

• L1DS (L1 Divider Select) = 1

)

RATIO_L1

0.95

3.42

1.0

3.6

1.05

3.78

Analog Output Offset Ratio

• L1DS (L1 Divider Select) = 0

• L1DS (L1 Divider Select) = 1

V_{RATIOL1-OFFSET}

-80

-22

6.0

2.0

80

22

mV

%

Analog Inputs Matching

• L1DS (L1 Divider Select) = 0

• L1DS (L1 Divider Select) = 1

L1_MATCHING

96

100

104

Notes

26. This parameter is production tested up to T_A= 125 °C, and guaranteed by process monitoring up to T_J= 150 °C.

27. When overcurrent occurs, the corresponding high-side stays ON with limited current capability and the HSxCL flag is set in the HSSR.

28. When open load occurs, the flag (HSxOP) is set in the HSSR.

29. HS automatically shutdown if HSOT occurs or if the HVSE flag is enabled and an overvoltage occurs.

30. When overtemperature shutdown occurs, both high-sides are turned off. All flags in HSSR are set.

31. Guaranteed by characterization but not production tested

32. If L1 pin is unused it must be connected to ground.

33. Analog multiplexer input disconnected from L1 input pin.

34. Analog multiplexer input connected to L1 input pin.

33910

12

NXP Semiconductors

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Window watchdog configuration pin (WDCONF) ⁽³⁵⁾

R

External Resistor Range

20

–

200

15

kΩ

EXT

Watchdog Period Accuracy with External Resistor (Excluding Resistor

Accuracy)

(36)

WD

-15

%

ACC

Analog multiplexer

Temperature Sense Analog Output Voltage

• T_A= -40 °C

2.0

2.8

3.6

-

3.0

-

2.8

3.6

4.6

V_{ADOUT0_TEMP}

V

• T_A= 25 °C

• T_A= 125 °C

Temperature Sense Analog Output Voltage per characterization

• T_A= 25 °C

(37)

V_{ADOUT0_25}

3.1

3.15

3.2

S_TTOV

Internal Chip Temperature Sense Gain

9.0

9.9

10.5

10.2

12

mV/K

Internal Chip Temperature Sense Gain per characterization at three

temperatures. See Figure 16, Temperature sense gain

S_{TTOV_3T}

10.5

VSENSE Input Divider Ratio (RATIO_VSENSE= V_VSENSE/ V_ADOUT0

• 5.5 V < V_SUP< 27 V

)

RATIO_VSENSE

5.0

5.25

5.5

VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per

characterization

• 5.5 <Vsup< 27 V

(37)

RATIO_VSENSECZ

OFFSET_VSENSE

5.15

5.35

VSENSE Output Related Offset

-30

-10

30

0

mV

OFFSET_VSENSE

VSENSE Output Related Offset per characterization

-12.6

_CZ

Analog output (ADOUT0)

Maximum Output Voltage

V_{OUT_MAX}

V_DD-0.35

0.0

V_DD

0.35

–

V

• -5.0 mA < I_O< 5.0 mA

Minimum Output Voltage

• -5.0 mA < I_O< 5.0 mA

V_{OUT_MIN}

RxD output pin (LIN physical layer) (RxD)

Low-state Output Voltage

• I_OUT= 1.5 mA

V_OL

0.0

–

0.8

V

High-state Output Voltage

• I_OUT= -250 µA

V_OH

V_DD-0.8

V_DD

Notes

35. For V_SUP4.7 V to 18 V

36. Watchdog timing period calculation formula: t_PWD[ms] = [0.466 * (R_EXT- 20)] + 10 with (R_EXTin kΩ)

37. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed by

production test.

33910

NXP Semiconductors

13

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

TXD input pin (LIN physical layer) (TXD)

V_IL

V_IH

0.3 x V_DD

V_DD+0.3

30

Low-state Input Voltage

High-state Input Voltage

-0.3

–

V

0.7 x V_DD

I_PUIN

Pin Pull-up Current, 0 V < V_IN< 3.5 V

10

20

µA

LIN physical layer with J2602 feature enabled (bit DIS_J2602 = 0)

V_{TH_UNDER_}

VOLTAGE

LIN Undervoltage threshold

• Positive and Negative threshold (V_THP, V_THN

5.0

6.0

V

)

V_{J2602_DEG}

Hysteresis (V_THP- V_THN

)

400

mV

LIN physical layer, transceiver (LIN)⁽³⁸⁾

V_BAT

V_SUP

Operating Voltage Range

Supply Voltage Range

8.0

7.0

18

40

V

V_{SUP_NON_OP}

Voltage Range within which the device is not destroyed

-0.3

Current Limitation for Driver Dominant State

• Driver ON, V_BUS= 18 V

I_{BUS_LIM}

40

-1.0

–

90

–

200

–

mA

µA

Input Leakage Current at the receiver

• Driver off; V_BUS= 0 V; V_BAT= 12 V

I_{BUS_PAS_DOM}

I_{BUS_PAS_REC}

I_{BUS_NO_GND}

Leakage Output Current to GND

–

20

1.0

• Driver Off; 8.0 V < V_BAT< 18 V; 8.0 V < V_BUS< 18 V; V_BUS≥ V_BAT

Control Unit Disconnected from Ground

(39)

(40)

-1.0

–

mA

• GND_DEVICE= V_SUP; V_BAT= 12 V; 0 < V

< 18 V

BUS

I_{BUSNO_BAT}

V_BUSDOM

V

Disconnected; V_{SUP_DEVICE}= GND; 0 V < V

< 18 V

BUS

–

100

0.4

µA

BAT

V_SUP

Receiver Dominant State

Receiver Recessive State

V_BUSREC

V_{BUS_CNT}

V_HYS

0.6

0.475

–

0.5

–

Receiver Threshold Center

• (V_{TH_DOM}+ V_{TH_REC})/2

V_SUP

0.525

0.175

Receiver Threshold Hysteresis

• (V_{TH_REC}- V_{TH_DOM}

V_SUP

)

V_SERDIODE

V_{SHIFT_BAT}

V_{SHIFT_GND}

Voltage Drop at the Serial Diode in Pull-up Path

0.4

0

1.0

V

V_BAT

VBAT_SHIFT

GND_SHIFT

11.5%

0

Notes

38. Parameters guaranteed for 7.0 V ≤ V_SUP≤ 18 V.

39. Loss of local ground must not affect communication in the residual network.

40. Node has to sustain the current which can flow under this condition. Bus must remain operational under this condition.

33910

14

NXP Semiconductors

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

LIN physical layer, transceiver (LIN) (continued)⁽³⁸⁾

(41)

V_BUSWU

R_SLAVE

LIN Wake-up threshold from Stop or Sleep Mode

5.3

30

5.8

60

180

–

V

LIN Pull-up Resistor to V

SUP

20

140

–

kΩ

°C

(42)

T_LINSD

Overtemperature Shutdown

160

10

T_{LINSD_HYS}

Overtemperature Shutdown Hysteresis

Notes

41. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, NXP does not

guarantee this parameter during the product's life time.

42. When overtemperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.

33910

NXP Semiconductors

15

4.3

Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

SPI interface timing (see Figure 13)

f

t

SPI Operating Frequency

SCLK Clock Period

–

4.0

N/A

MHz

ns

SPIOP

250

110

100

40

CLK

PS

(43)

t

SCLK Clock High Time

SCLK Clock Low Time

ns

SCLKH

W

t

ns

SCLKL

W

t

Falling Edge of CS to Rising Edge of SCLK

Falling Edge of SCLK to CS Rising Edge

MOSI to Falling Edge of SCLK

Falling Edge of SCLK to MOSI

MISO Rise Time

ns

LEAD

t_LAG

ns

t

ns

SISU

t

40

ns

SIH

(43)

t_RSO

–

40

–

ns

• C = 220 pF

L

MISO Fall Time

• C = 220 pF

L

t

FSO

Time from Falling or Rising Edges of CS to:

• MISO Low-impedance

• MISO High-impedance

(43)

t

0.0

–

50

ns

SOEN

t

SODIS

Time from Rising Edge of SCLK to MISO Data Valid

• 0.2 x V_DD≤ MISO ≥ 0.8 x V_DD, C_L= 100 pF

t

0.0

–

75

VALID

RST output pin

t

Reset Low-level Duration After V_DDHigh (see Figure 12)

Reset Deglitch Filter Time

0.65

350

1.0

1.35

900

ms

ns

RST

t

480

RSTDF

Window watchdog configuration pin (WDCONF)

Watchdog Time Period

• External Resistor R_EXT= 20 kΩ (1%)

• External Resistor R_EXT= 200 kΩ (1%)

• Without External Resistor R_EXT(WDCONF Pin Open)

8.5

79

110

10

94

150

11.5

108

205

(44)

t

ms

PWD

Notes

43. This parameter is guaranteed by process monitoring but not production tested.

44. Watchdog timing period calculation formula: t_PWD[ms] = [0.466 * (R_EXT- 20)] + 10 with (R_EXTin kΩ)

33910

16

NXP Semiconductors

Table 5. Dynamic electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

L1 input

Characteristic

Min.

Typ.

Max.

Unit

Notes

(45)

t

L1 Filter Time Deglitcher

8.0

20

38

μs

WUF

State machine timing

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop

Command) and Stop Mode Activation

(45)

t_STOP

–

5.0

μs

t

Normal Request Mode Timeout (see Figure 12)

Cyclic Sense ON Time from Stop and Sleep Mode

Cyclic Sense Accuracy

110

130

-35

150

200

205

270

+35

ms

µs

%

NRTOUT

T_ON

(46)

(45)

Delay Between SPI Command and HS Turn On

• 9.0 V < V_SUP< 27 V

(47)

t_S-ON

–

10

μs

Delay Between SPI Command and HS Turn Off

• 9.0 V < V_SUP< 27 V

(47)

(45)

t_S-OFF

–

10

μs

Delay Between Normal Request and Normal Mode After a Watchdog

Trigger Command (Normal Request Mode)

t_SNR2N

Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:

• Normal Request mode, VDD ON and RST HIGH

• First Accepted SPI Command

t_WUCS

t_WUSPI

9.0

90

15

—

80

N/A

μs

t_2CS

Minimum Time Between Rising and Falling Edge on the CS

4.0

—

J2602 deglitcher

V_SUPDeglitcher

• (DIS_J2602 = 0)

(48)

t_{J2602_DEG}

35

50

70

μs

LIN physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec according to LIN physical layer specification^{(49), (50)}

Duty Cycle 1:

• TH_REC(MAX)= 0.744 * V_SUP

D1

D2

0.396

—

• TH_DOM(MAX)= 0.581 * V_SUP

• D1 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT= 50 µs, 7.0 V ≤ V_SUP≤ 18 V

Duty Cycle 2:

• TH_REC(MIN)= 0.422 * V_SUP

0.581

• TH_DOM(MIN)= 0.284 * V_SUP

• D2 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT= 50 µs, 7.6 V ≤ V_SUP≤ 18 V

Notes

45. This parameter is guaranteed by process monitoring but not production tested.

46. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, NXP does not

guarantee this parameter during the product's life time.

47. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.

48. This parameter has not been monitoring during operating life test.

49. Bus load R_BUSand C_BUS1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold

defined at each parameter. See Figure 6.

50. See Figure 7.

33910

NXP Semiconductors

17

Table 5. Dynamic electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec according to LIN physical layer specification ^{(51), (52)}

Duty Cycle 3:

• TH_REC(MAX)= 0.778 * V_SUP

D3

D4

0.417

—

20

—

0.590

—

• TH_DOM(MAX)= 0.616 * V_SUP

• D3 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT= 96 µs, 7.0 V ≤ V_SUP≤ 18 V

Duty Cycle 4:

• TH_REC(MIN)= 0.389 * V_SUP

• TH_DOM(MIN)= 0.251 * V_SUP

• D4 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT= 96 µs, 7.6 V ≤ V_SUP≤ 18 V

LIN physical layer: driver characteristics for fast slew rate

SR

LIN Fast Slew Rate (Programming Mode)

—

V/μs

FAST

LIN physical layer: characteristics and wake-up timings ⁽⁵³⁾

Propagation Delay and Symmetry

t_{REC_PD}

(54)

• Propagation Delay of Receiver, t_{REC_PD}=MAX (t_{REC_PDR}, t_{REC_PDF}

• Symmetry of Receiver Propagation Delay, t_{REC_PDF}- t_{REC_PDR}

)

—

-2.0

4.2

—

6.0

2.0

μs

t_{REC_SYM}

(55) (59)

,

t_PROPWL

Bus Wake-Up Deglitcher (Sleep and Stop modes)

42

70

95

(56)

Bus Wake-Up Event Reported

• From Sleep mode

• From Stop mode

(57)

(58)

t_{WAKE_SLEEP}

t_{WAKE_STOP}

—

9.0

—

27

1500

35

μs

t_TXDDOM

TXD Permanent Dominant State Delay

0.65

1.0

1.35

s

Pulse width modulation input pin (PWMIN)

PWMIN pin

f_PWMIN

(59)

—

10

—

kHz

• Max. frequency to drive HS output pins

Notes

51. Bus load R_BUSand C_BUS1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold

defined at each parameter. See Figure 6.

52. See Figure 8.

53. V_SUPfrom 7.0 to 18 V, bus load R_BUSand C_BUS1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to

LIN signal threshold defined at each parameter. See Figure 6.

54. See Figure 9.

55. See Figure 10, for Sleep and Figure 11, for Stop mode.

56. This parameter is tested on automatic tester but has not been monitoring during operating life test.

57. The measurement is done with 1.0 µF capacitor and 0 mA current load on V_DD. The value takes into account the delay to charge the capacitor.

The delay is measured between the bus wake-up threshold (V_BUSWU) rising edge of the LIN bus and when V

reaches 3.0 V. See Figure 10.

DD

The delay depends of the load and capacitor on V_DD

.

58. In Stop mode, the delay is measured between the bus wake-up threshold (V_BUSWU) and the falling edge of the IRQ pin. See Figure 11.

59. This parameter is guaranteed by process monitoring but not production tested.

33910

18

NXP Semiconductors

4.4

Timing diagrams

33910

TRANSIENT PULSE

GENERATOR

1.0 nF

LIN

(

NOTE

)

GND

PGND LGND AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

Figure 4. Test circuit for transient test pulses (LIN)

33910

Transient Pulse

Generator

(Note)

1.0 nF

L1

10 k

Ω

GND

PGND LGND AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.

Figure 5. Test circuit for transient test pulses (L1)

V_SUP

R0

LIN

TXD

RXD

R0 AND C0 COMBINATIONS:

• 1.0 KΩ and 1.0 nF

• 660 Ω and 6.8 nF

• 500 Ω and 10 nF

C0

Figure 6. Test circuit for LIN timing measurements

33910

NXP Semiconductors

19

TXD

t_BIT

t

BUS_REC

(MAX)

(MIN)

BUS_DOM

V_{LIN_REC}

74.4% V_SUP

Thresholds of

receiving node 1

TH

REC(MAX)

DOM(MAX)

58.1% V

SUP

TH

LIN

Thresholds of

receiving node 2

42.2% V

28.4% V

SUP

TH

REC(MIN)

SUP

TH

DOM(MIN)

t

BUS_DOM(MIN)

t

BUS_REC(MAX)

RXD

Output of receiving Node 1

t

REC_PDF(1)

t

REC_PDR(1)

RXD

Output of receiving Node 2

t

REC_PDF(2)

t

REC_PDR(2)

Figure 7. LIN timing measurements for normal slew rate

TXD

t_BIT

t

BUS_REC(MIN)

BUS_DOM(MAX)

V_{LIN_REC}

77.8% V_SUP

Thresholds of

receiving node 1

TH

REC(MAX)

DOM(MAX)

61.6% V

SUP

TH

LIN

Thresholds of

receiving node 2

38.9% V

25.1% V

SUP

TH

REC(MIN)

SUP

TH

DOM(MIN)

t

BUS_DOM(MIN)

t

BUS_REC(MAX)

RXD

Output of receiving Node 1

t

REC_PDF(1)

t

REC_PDR(1)

RXD

Output of receiving Node 2

t

REC_PDF(2)

t

REC_PDR(2)

Figure 8. LIN timing measurements for slow slew rate

33910

20

NXP Semiconductors

V_{LIN_REC}

0.6% V

0.4% V

SUP

V

BUSREC

V

SUP

LIN BUS SIGNAL

SUP

V

BUSDOM

RXD

t

REC_PDF

REC_PDR

Figure 9. LIN receiver timing

V

LIN_REC

LIN

5.0 V

DOMINANT LEVEL

V_BUSWU

3.0 V

VDD

t

WAKE_SLEEP

t

WL

PROP

Figure 10. LIN wake-up sleep mode timing

V

LIN_REC

LIN

5.0 V

V_BUSWU

DOMINANT LEVEL

t

IRQ

WAKE_STOP

t

WL

PROP

Figure 11. LIN wake-up stop mode timing

33910

NXP Semiconductors

21

V

SUP

V

DD

RST

t

NRTOUT

t

RST

Figure 12. Power on reset and normal request timeout timing

t

PSCLK

CS

t

WSCLKH

LEAD

t

LAG

SCLK

t

WSCLKL

t

SIH

SISU

MOSI

MISO

UNDEFINED

D0

DON’T CARE

D7

DON’T CARE

t

VALID

t

SODIS

t

SOEN

D0

D7

DON’T CARE

Figure 13. SPI timing characteristics

33910

22

NXP Semiconductors

5

Functional description

5.1

Introduction

The 33910 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For

automotive body electronics, the 33910 is well suited to perform keypad applications via the LIN bus. Power switches are provided on the

device configured as high-side outputs. Other ports are also provided, which include a Hall Sensor port supply, and one wake-up capable

pin. An internal voltage regulator provides power to a MCU device. Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device to be compatible with 3-wire bus systems, where one wire is used for

communication, one for battery, and one for ground.

5.2

Functional pin description

See Figure 1, 33910 simplified application diagram, for a graphic representation of the various pins referred to in the following paragraphs.

Also, see Pin connections for a description of the pin locations in the package.

5.2.1 Receiver output pin (RXD)

The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD Low when LIN

bus is dominant, RXD High when LIN bus is recessive.

5.2.2 Transmitter input pin (TXD)

The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD

is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating.

5.2.3 LIN bus pin (LIN)

The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN

bus specification 2.0, 2.1, and SAE J2602-2. The LIN interface is only active during Normal mode. See Table 6, Operating modes

overview.

5.2.4 Serial data clock pin (SCLK)

The SCLK pin is the SPI clock input. MISO data changes on the positive transition of the SCLK. MOSI is sampled on the negative edge

of the SCLK.

5.2.5 Master out slave in pin (MOSI)

The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the negative edge of SCLK.

5.2.6 Master in slave out pin (MISO)

The MISO pin sends data to an SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this

output pin changes on the positive edge of the SCLK. When CS is High, this pin remains in the high-impedance state.

5.2.7 Chip select pin (CS)

CS is an active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in the

same SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched.

A valid transmission must consist of 8 bits only. While in STOP mode, a low-to-high level transition on this pin generates a wake-up

condition for the 33910.

33910

NXP Semiconductors

23

5.2.8 Analog multiplexer pin (ADOUT0)

The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer,

including the VSENSE and L1 input voltages, and the internal junction temperature.

5.2.9 PWM input control pin (PWMIN)

This digital input can control the high-sides drivers in Normal Request and Normal mode. To enable PWM control, the MCU must perform

a write operation to the High-side Control Register (HSCR). This pin has an internal 20 μA current pull-up.

5.2.10 Reset pin (RST)

This bidirectional pin is used to reset the MCU in case the 33910 detects a reset condition, or to inform the 33910 the MCU has just been

reset. After release of the RST pin, Normal Request mode is entered. The RST pin is an active low filtered input and output formed by a

weak pull-up and a switchable pull-down structure which allows this pin to be shorted either to V_DDor to GND during software

development, without the risk of destroying the driver.

5.2.11 Interrupt pin (IRQ)

The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request mode or to signal a wake-

up from Stop mode. This active low output transitions to high only after the interrupt is acknowledged by a SPI read of the respective status

bits.

5.2.12 Watchdog configuration pin (WDCONF)

The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window

watchdog period. When connected directly to ground, the watchdog is disabled. When this pin is left open, the watchdog period is fixed

to its lower precision internal default value (150 ms typical).

5.2.13 Ground connection pins (AGND, PGND, LGND)

The AGND, PGND, and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator

module. The PGND and LGND pins are used for high current load return as in the LIN interface pin.

Note: PGND, AGND and LGND pins must be connected together.

5.2.14 Digital/analog pin (L1)

The L1 pin is multi purpose input. It can be used as a digital input, which can be sampled by reading the SPI and used for wake-up when

33910 is in low power mode or used as analog input for the analog multiplexer. When used to sense voltage outside the module, a

33 kohm series resistor must be used on the input.

When used as wake-up input L1 can be configured to operate in cyclic-sense mode. In this mode one or both of the high-side switches

are configured to be periodically turned on and sample the wake-up input. If a state change is detected between two cycles a wake-up is

initiated. The 33910 can also wake-up from Stop or Sleep by a simple state change on L1. When used as analog input, the voltage present

on the L1 pin is scaled down by an selectable internal voltage divider and can be routed to the ADOUT0 output through the analog

multiplexer.

Note: If L1 input is selected in the analog multiplexer, it is disabled as the digital input and remains disabled in low power mode. No wake-

up feature is available in this condition. When the L1 input is not selected in the analog multiplexer, the voltage divider is disconnected

from this input.

5.2.15 High-side output pins (HS1 and HS2)

These two high-side switches are able to drive loads such as relays or lamps. Their structures are connected to the VS2 supply pin. The

pins are short-circuit protected and both outputs are also protected against overheating. HS1 and HS2 are controlled by SPI and can

respond to a signal applied to the PWMIN input pin. HS1 and HS2 outputs can also be used during low-power mode for the cyclic-sense

of the wake inputs.

33910

24

NXP Semiconductors

5.2.16 Power supply pins (VS1 and VS2)

Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection

and negative transient voltages with external components. These pins sustain standard automotive voltage conditions such as a load

dump at 40 V. The high-side switches (HS1 and HS2) are supplied by the VS2 pin. All other internal blocks are supplied by the VS1 pin.

5.2.17 Voltage sense pin (VSENSE)

This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input

is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery

voltage. The ESD structure on this pin allows for excursion up to +40 V and down to -27 V, allowing this pin to be connected directly to

the battery line. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

5.2.18 Hall sensor switchable supply pin (HVDD)

This pin provides a switchable supply for external hall sensors. While in Normal mode, this current limited output can be controlled through

the SPI. The HVDD pin needs to be connected to an external capacitor to stabilize the regulated output voltage.

5.2.19 +5.0 V main regulator output pin (VDD)

An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply a

microcontroller. The pin is current limited against shorts to GND and overtemperature protected. During Stop mode, the voltage regulator

does not operate with its full drive capabilities and the output current is limited. During Sleep mode, the regulator output is completely shut

down.

33910

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25

6

Functional device operations

6.1

Operational modes

6.1.1 Introduction

The 33910 offers three main operating modes: Normal (Run), Stop, and Sleep (Low Power). In Normal mode, the device is active and is

operating under normal application conditions. The Stop and Sleep modes are low power modes with wake-up capabilities. In Stop mode,

the voltage regulator still supplies the MCU with V_DD(limited current capability), while in Sleep mode the voltage regulator is turned off

(V_DD= 0 V).

Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset and the voltage regulator is

turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the Mode Control Register (MCR). Figure 14

describes how transitions are done between the different operating modes. Table 6 gives an overview of the operating modes.

6.1.2 Reset mode

The 33910 enters the Reset mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, it enters

the Normal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (V_DDlow, watchdog

trigger fail, after wake-up from Sleep mode, Normal Request mode timeout occurs).

6.1.3 Normal request mode

This is a temporary mode automatically accessed by the device after the Reset mode, or after a wake-up from Stop mode. In Normal

Request mode, the VDD regulator is ON, the RESET pin is High, and the LIN is operating in RX Only mode. As soon as the device enters

in the Normal Request mode an internal timer is started for 150 ms (typical value). During these 150 ms, the MCU must configure the

Timing Control Register (TIMCR) and the Mode Control Register (MCR) with MOD2 and MOD1 bits set = 0, to enter the Normal mode. If

within the 150 ms timeout, the MCU does not command the 33910 to Normal mode, it enters in Reset mode. If the WDCONF pin is

grounded in order to disable the watchdog function, it goes directly in Normal mode after the Reset mode.

6.1.4 Normal mode

In Normal mode, all 33910 functions are active and can be controlled by the SPI interface and the PWMIN pin. The VDD regulator is ON

and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog

function is enabled. The wake-up input (L1) can be read as digital input or have its voltage routed through the analog-multiplexer.

The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0, 2.1 and SAEJ2602. The LIN bus can transmit

and receive information. The high-side switches are active and have PWM capability according to the SPI configuration. The interrupts

are generated to report failures for V_SUPover/undervoltage, thermal shutdown, or thermal shutdown prewarning on the main regulator.

6.1.5 Sleep mode

The Sleep mode is a low power mode. From Normal mode, the device enters into Sleep mode by sending one SPI command through the

Mode Control Register (MCR), or (V_DDlow > 150 ms) with V_SUV= 0. When in Reset mode, a V_DDundervoltage condition with no V_SUP

undervoltage (V_SUV= 0) sends the device to Sleep mode. All blocks are in their lowest power consumption condition. Only some wake-

up sources (wake-up input with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. The

internal low-power oscillator may be active if the IC is configured for cyclic-sense. In this condition, one of the high-side switches is turned

on periodically and the wake-up input is sampled. Wake-up from Sleep mode is similar to a power-up. The device goes in Reset mode

except the SPI reports the wake-up source and the BATFAIL flag is not set.

6.1.6 Stop mode

The Stop mode is the second low power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The

application MCU is always supplied while the 33910 is operating in Stop mode. The device can enter into Stop mode only by sending the

SPI command. When the application is in this mode, it can wake-up from the 33910 side (for example: cyclic sense, force wake-up, LIN

bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode transitions the 33910 to Normal Request mode and

generates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin.

33910

26

NXP Semiconductors

Normal Request Timeout Expired (t_NRTOUT

)

Normal Request timeout expired (NR_TOUT

)

V

Low

V

DD

V_DDHigh and

Power Up

Reset Delay (t

) Expired

V_DDHigh and Reset Delay (t_RST) expired

RST

Power

Down

Normal

Request

Reset

V_DDLow

Normal

WD Failed

WD failed

V_DD_LL_owO₍W_>NR(>t_N

_re_T) Expired

d

V_DD

)

_TOUTR

e

T

x

O

pi

U

and VSUV = 0

Sleep Command

SLEEP Command

W_Wak_ae_ke-_-u_Up_p(_(RR_ee_ss_ete₎t)

Sleep

Stop

V_VLow

_DDLow

DD

Legend

WD: Watchdog

Notes:

WD Disabled: Watchdog disabled (WDCONF pin connected to GND)

WD - means Watchdog

WD Trigger: Watchdog is triggered by SPI command

WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)

WD Failed: No watchdog trigger or trigger occurs in closed window

WD trigger – means Watchdog is triggered by SPI command

Stop Command: Stop command sent via SPI

WD failed – means no Watchdog trigger or trigger occurs in closed window

Sleep Command: Sleep command sent via SPI

STOP Command - means STOP command sent via SPI

Wake-up from Stop mode: L1 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.

SLEEP Command - means SLEEP command send via SPI

Wake-up from Sleep mode: L1 state change, LIN bus wake-up, Periodic wake-up.

Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Figure 14. Operating modes and transitions

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Table 6. Operating modes overview

Function

VDD

Reset mode

Normal request mode

Normal mode

Stop mode

Sleep mode

Full

-

Full

SPI

Stop

-

SPI ⁽⁶⁰⁾

HVDD

SPI/PWM ⁽⁶¹⁾

SPI

Note ⁽⁶²⁾

Note ⁽⁶³⁾

HSx

Analog Mux

L1

-

SPI/PWM

SPI

-

Input

Wake-up

-

LIN

-

Rx-Only

Full/Rx-Only

Rx-Only/Wake-up

On ⁽⁶⁴⁾/Off

V_SUP/V_DD

Watchdog

-

150 ms (typ.) timeout

V_SUP/V_DD

-

V_SUP/V_DD

V_DD

Voltage Monitoring

-

Notes

60. Operation can be enabled/controlled by the SPI.

61. Operation can be controlled by the PWMIN input.

62. HSx switches can be configured for cyclic sense operation in Stop mode.

63. HSx switches can be configured for cyclic sense operation in Sleep mode.

64. Windowing operation when enabled by an external resistor.

6.1.7 Interrupts

Interrupts are used to signal a microcontroller a peripheral needs to be serviced. The interrupts which can be generated, change according

to the operating mode. While in Normal and Normal Request modes, the 33910 signals through interrupts special conditions which may

require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the Interrupt Source Register

(ISR).

While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts. Wake-up is performed by

powering-up the MCU. In Normal and Normal Request mode the wake-up source can be read by SPI. The interrupts are signaled to the

MCU by a low logic level of the IRQ pin, which remains low until the interrupt is acknowledged by a SPI read command of the ISR register.

The IRQ pin is then driven high. Interrupts are only asserted while in Normal, Normal Request and Stop mode. Interrupts are not generated

while the RST pin is low. The following is a list of the interrupt sources in Normal and Normal Request modes. Some of these can be

masked by writing to the SPI - Interrupt Mask Register (IMR).

6.1.7.1

Low-voltage interrupt

Signals when the supply line (VS1) voltage drops below the VSUV threshold (V_SUV).

6.1.7.2

High-voltage interrupt

Signals when the supply line (VS1) voltage increases above the VSOV threshold (V_SOV).

6.1.7.3

Overtemperature prewarning

Signals when the 33910 temperature has reached the pre-shutdown warning threshold. It is used to warn the MCU an overtemperature

shutdown in the main 5.0 V regulator is imminent.

6.1.7.4

LIN overtemperature shutdown/TXD stuck at dominant/RXD short-circuit

These signal fault conditions within the LIN interface causes the LIN driver to be disabled. In order to restart the operation, the fault must

be removed and TXD must go recessive.

6.1.7.5

High-side overtemperature shutdown

Signals a shutdown in the high-side outputs.

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NXP Semiconductors

6.1.8 Reset

To reset a MCU the 33910 drives the RST pin low for the time the reset condition lasts. After the reset source is removed, the state

machine drives the RST output low for at least 1.0 ms (typical value) before driving it high. In the 33910, four main reset sources exist:

6.1.8.1

5.0 V regulator low-voltage-reset (V

)

RSTTH

The 5.0 V regulator output V_DDis continuously monitored against brown outs. If the supply monitor detects the voltage at the VDD pin has

dropped below the reset threshold V_RSTTHthe 33910 issues a reset. In case of overtemperature, the voltage regulator is disabled and the

voltage monitoring issues a VDDOT Flag independently of the V_DDvoltage.

6.1.8.2

Window watchdog overflow

If the watchdog counter is not properly serviced while its window is open, the 33910 detects an MCU software run-away and resets the

microcontroller.

6.1.8.3

Wake-up from sleep mode

During Sleep mode, the 5.0 V regulator is not active, hence all wake-up requests from Sleep mode require a power-up/reset sequence.

6.1.8.4

External reset

The 33910 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low.

The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality

is also active in Stop mode. After the RST pin is released, there is no extra t_RSTto be considered.

6.1.9 Wake-up capabilities

Once entered into one of the low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation.

In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode the wake-up is performed by activating the 5.0 V

regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers and reading the

Interrupt Source Register. There is no specific SPI register bit to signal a CS wake-up or external reset. If necessary this condition is

detected by excluding all other possible wake-up sources.

6.1.9.1

Wake-up from wake-up input (L1) with cyclic sense disabled

The wake-up line is dedicated to sense state changes of external switch and wake-up the MCU (in Sleep or Stop mode). In order to select

and activate direct wake-up from L1 input, the Wake-up Control Register (WUCR) must be configured with appropriate L1WE input

enabled or disabled. The wake-up input’s state is read through the Wake-up Status Register (WUSR). L1 input is also used to perform

cyclic-sense wake-up.

Note: Selecting an L1 input in the analog multiplexer before entering low power mode disables the wake-up capability of the L1 input

6.1.9.2

Wake-up from wake-up input (L1) with cyclic sense timer enabled

The SBCLIN can wake-up at the end of a cyclic sense period if on the wake-up input line (L1) a state change occurs. One or both HSx

switch can be activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wake-up are exclusive. If cyclic sense is

enabled, the force wake-up can not be enabled. In order to select and activate the cyclic sense wake-up from the L1 input, before entering

in low power modes (Stop or Sleep modes), the following SPI set-up has to be performed:

In WUCR: select the L1 input to WU-enable.

In HSCR: enable the desired HSx.

• In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits.

• Perform Goto Sleep/Stop command.

33910

NXP Semiconductors

29

6.1.9.3

Forced wake-up

The 33910 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and Forced wake-up are

exclusive. If Forced wake-up is enabled, the Cyclic Sense can not be enabled. To determine the wake-up period, the following SPI set-

up has to be sent before entering in low power modes:

• In TIMCR: select the CS/WD bit and determine the low power mode period with CYSTx bits.

• In HSCR: all HSx bits must be disabled.

6.1.9.4

CS wake-up

While in Stop mode, a rising edge on the CS causes a wake-up. The CS wake-up does not generate an interrupt, and is not reported on

SPI.

6.1.9.5

LIN wake-up

While in the low-power mode, the 33910 monitors the activity on the LIN bus. A dominant pulse larger than t_PROPWLfollowed by a dominant

to recessive transition causes a LIN wake-up. This behavior protects the system from a short to ground bus condition. The bit RXONLY = 1

from LINCR Register disables the LIN wake-up from Stop mode.

6.1.9.6

RST wake-up

While in Stop mode, the 33910 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, the 33910

changes to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an

interrupt and is not reported via SPI.

From Stop mode, the following wake-up events can be configured:

• Wake-up from L1 input without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

• CS wake-up

• LIN wake-up

• RST wake-up

From Sleep mode, the following wake-up events can be configured:

• Wake-up from L1 input without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

• LIN wake-up

6.1.10 Window watchdog

The 33910 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external

resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears

are performed by writing through the SPI in the MOD bits of the Mode Control Register (MCR).

During the first half of the SPI timeout, watchdog clears are not allowed, but after the first half of the SPI timeout window, the clear

operation opens. If a clear operation is performed outside the window, the 33910 resets the MCU, in the same way as when the watchdog

overflows.

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NXP Semiconductors

WINDOW CLOSED

NO WATCHDOG CLEAR

ALLOWED

WINDOW OPEN

FOR WATCHDOG

CLEAR

WD TIMING X 50%

WD PERIOD (t

)

PWD

WD TIMING SELECTED BY RESISTOR

ON WDCONF PIN

Figure 15. Window watchdog operation

To disable the watchdog function in Normal mode the user must connect the WDCONF pin to ground. This measure effectively disables

Normal Request mode. The WDOFF bit in the Watchdog Status Register (WDSR) is set. This condition is only detected during Reset

mode. If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of

150 ms (typ.) and signals the faulty condition through the Watchdog Status Register (WDSR).

The watchdog timebase can be further divided by a prescaler which can be configured by the Timing Control Register (TIMCR). During

Normal Request mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. In

case of a timeout, the 33910 enters into Reset mode, resetting the microcontroller before entering again into Normal Request mode.

6.1.11 Faults detection management

The 33910 has the capability to detect faults like an overvoltage or undervoltage on VS1, TxD in permanent Dominant State,

Overtemperature on HS, LIN. It is able to take corrective actions accordingly. Most of faults are monitoring through SPI and the Interrupt

pin. The microcontroller can also take actions. The following table summarizes all fault sources the device is able to detect with associated

conditions. The status for a device recovery and the SPI or pins monitoring are also described.

Table 7. Fault detection management conditions

Monitoring ⁽⁶⁶⁾

Block

Fault

Mode

Condition

Fallout

Recovery

Reg (flag, bit)

Interrupt

V

_SUP<3.0 V (typ)

VSR (BATFAIL,

0)

Battery Fail

All modes

-

Condition gone

-

then power-up

In Normal mode, Conditiongone,to

IRQ low +

ISR (0101) ⁽⁶⁷⁾

V_SUP> 19.25 V

(typ)

HS shutdown if bit

HVSE=1 (reg

MCR)

re-enable HS

write to HSCR

registers

Vsup Overvoltage

VSR (VSOV,3)

Normal, Normal

Request

V_SUP

Undervoltage

IRQ low + ISR

(0101)

V_SUP< 6.0 V (typ)

V_DD< 4.5 V (typ)

Power Supply

-

VSR (VSUV,2)

Reset ⁽⁶⁵⁾

-

V

_DDUndervoltage

All except Sleep

-

Condition gone

V_DDOvertemp

Prewarning

Temperature >

115 °C (typ)

IRQ low + ISR

(0101)

VSR (VDDOT,1)

All except Low

Power modes

V_DD

Temperature >

170 °C (typ)

VDD shutdown,

Reset then Sleep

-

Overtemperature

Rxd Pin Short

Circuit

RXD pin shorted

to GND or 5.0 V

LIN trans

shutdown

LINSR,

(RXSHORT,3)

LIN transmitter re-

enabled once the

condition is gone

and TXD is high

Txd Pin

Permanent

Dominant

TXD pin low for

more than 1.0 s

(typ)

IRQ low + ISR

(0100) ⁽⁶⁷⁾

Normal, Normal

Request

LINSR

(TXDOM,2)

LIN

LIN transmitter

shutdown

Lin Driver

Overtemperature

Temperature >

160 °C (typ)

LINSR (LINOT,1)

33910

NXP Semiconductors

31

Table 7. Fault detection management conditions (continued)

Monitoring ⁽⁶⁶⁾

Block

Fault

Mode

Condition

Fallout

Recovery

Reg (flag, bit)

Interrupt

Conditiongone,to

re-enable HS

write to HSCR reg

IRQ low + ISR

(0010) ⁽⁶⁷⁾

High-side Drivers

Overtemperature

Temperature >

160 °C (typ)

Both HS thermal

shutdown

All flags in HSSR

are set

Hs1 Open Load

Detection

HSSR

(HS1OP,1)

Current through

HSx < 5.0 mA

(typ)

Normal, Normal

Request

-

High-side

Hs2 Open-load

Detection

HSSR

(HS2OP,3)

Condition gone

-

Hs1 Overcurrent

Hs2 Overcurrent

Current through

HSx tends to rise

above the current capability 60 mA

HSx on with

limited current

HSSR (HS1CL,0)

HSSR (HS2CL,2)

limit 60 mA (min)

(min)

The MCU did not

command the

device to Normal

mode within the

150 ms timeout

after reset

Normal Request

Time-out Expired

Normal Request

Reset

-

WD timeout or

WD clear within

the window

closed

Watchdog

-

Watchdog

Timeout

WDSR (WDTO,

3)

Normal

Reset

WD internal lower

precision

timebase 150 ms

(typ)

Connect

WDCONF to a

resistor or to GND

WDCONF pin is

floating

WDSR (WDERR,

2)

Watchdog Error

Notes

65. When in Reset mode a VDD undervoltage condition combined with no V_SUPundervoltage (VSUV = 0) sends the device to Sleep mode.

66. Registers to be read when back in Normal Request or Normal mode depending on the fault. Interrupts only generated in Normal, Normal Request

and Stop modes

67. Unless masked, If masked IRQ remains high and the ISR flags are not set.

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NXP Semiconductors

6.1.12 Temperature sense gain

The analog multiplexer can be configured via SPI to allow the ADOUT0 pin to deliver the internal junction temperature of the device.

Figure 16 illustrates the internal chip temp sense obtained per characterization at 3 temperatures with 3 different lots and 30 samples.

Temperature Sense Analog Output Voltage

5

4.5

4

3.5

3

2.5

2

-50

0

50

100

150

Temperature (°C)

Figure 16. Temperature sense gain

6.1.13 High-side output pins HS1 and HS2

These outputs are two high-side drivers intended to drive small resistive loads or LEDs incorporating the following features:

• PWM capability (software maskable)

• Open load detection

• Current limitation

• Overtemperature shutdown (with maskable interrupt)

• High-voltage shutdown (software maskable)

• Cyclic sense

The high-side switches are controlled by the bits HS1:2 in the High-side Control Register (HSCR).

6.1.13.1 PWM capability (direct access)

Each high-side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in

the High-side Control Register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low.

This applies to HS2 configuring HS2 and PWMHS2 bits.

33910

NXP Semiconductors

33

Interrupt

Control

Module

V_DD

HVSE

V_DD

PWMIN

PWMHSx

VS2

MOD1:2

HSx

HIgh-side Driver

charge pump

open load detection

current limitation

on/off

Control

HSxOP

HSxCL

Status

overtemperture shutdown (interrupt maskable)

High-voltage shutdown (maskable)

HSx

Wake-up

Module

Figure 17. High-side drivers HS1 and HS2

6.1.13.2 Open load detection

Each high-side driver signals an open load condition if the current through the high-side is below the open load current threshold. The

open load condition is indicated with the bits HS1OP and HS2OP in the High-side Status Register (HSSR).

6.1.13.3 Current limitation

Each high-side driver has an output current limitation. In combination with the overtemperature shutdown the high-side drivers are

protected against overcurrent and short-circuit failures. When the driver operates in the current limitation area, it is indicated with the bits

HS1CL and HS2CL in the HSSR.

Note: If the driver is operating in current limitation mode, excessive power might be dissipated.

6.1.13.4 Overtemperature protection (HS interrupt)

Both high-side drivers are protected against overtemperature. In case of an overtemperature condition both high-side drivers are shut

down and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source Register

(ISR). A thermal shutdown of the high-side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. If the bit HSM is set

in the Interrupt Mask Register (IMR), then an interrupt (IRQ) is generated. A write to the High-side Control Register (HSCR), when the

overtemperature condition is gone, re-enables the high-side drivers.

6.1.13.5 High-voltage shutdown

In case of a high voltage condition and if the high voltage shutdown is enabled (bit HVSE in the Mode Control Register (MCR) is set both

high-side drivers are shut down. A write to the High-side Control Register (HSCR), when the high voltage condition is gone, re-enables

the high-side drivers.

6.1.13.6 Sleep and stop mode

The high-side drivers can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 6, Operating modes overview.

33910

34

NXP Semiconductors

6.1.14 Lin physical layer

The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to

meet the LIN physical layer specification and has the following features:

•

LIN physical layer 2.0, 2.1 and SAEJ2602 compliant

Slew rate selection

Overtemperature shutdown

Advanced diagnostics

The LIN driver is a low-side MOSFET with thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no

external pull-up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time

from recessive to dominant is controlled. The symmetry between both slopes is guaranteed.

6.1.14.1 LIN pin

The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance.

WAKE-UP

MODULE

LIN

Wake-up

MOD1:2

LSR0:1

VS1

LIN DRIVER

J2602

Slope and Slew Rate Control

RXONLY

RXSHORT

TXDOM

LINOT

Overtemperature Shutdown (interrupt maskable)

30 K

LIN

TXD

RXD

SLOPE

CONTROL

LGND

WAKE-UP

FILTER

RECEIVER

Figure 18. LIN interface

6.1.14.2 Slew rate selection

The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew

rate can be adapted with the bits LSR1:0 in the LIN Control Register (LINCR). The initial slew rate is optimized for 20 kBit/s.

6.1.14.3 J2602 conformance

To be compliant with the SAE J2602-2 specification, the J2602 feature has to be enabled in the LINCR Register (bit DIS_J2602 sets to

0). The LIN transmitter is disabled in case of a V_SUPundervoltage condition occurs and TXD is in Recessive State: the LIN bus goes in

Recessive State and RXD goes high. The LIN transmitter is not disabled if TXD is in Dominant State. A deglitcher on V_SUP(t_{J2602_DEG}

)

is implemented to avoid false switching.

If the (DIS_J2602) bit is set to 1, the J2602 feature is disabled and the communication TXD-LIN-RXD works for V_SUPdown to 4.6 V (typical

value) and then the communication is interrupted. The (DIS_J2602) bit is set per default to 0.

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6.1.14.4 Overtemperature shutdown (LIN interrupt)

The output low-side FET is protected against overtemperature conditions. In case of an overtemperature condition, the transmitter is shut

down and the LINOT bit in the LIN Status Register (LINSR) is set. If the LINM bit is set in the Interrupt Mask Register (IMR), an Interrupt

IRQ is generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high.

6.1.14.5 RXD short-circuit detection (LIN interrupt)

The LIN transceiver has a short-circuit detection for the RXD output pin. If the device transmits and in case of a short-circuit condition,

either 5.0 V or Ground, the RXSHORT bit in the LIN Status Register (LINSR) is set and the transmitter is shutdown. If the LINM bit is set

in the Interrupt Mask Register (IMR), an Interrupt IRQ is generated. The transmitter is automatically re-enabled once the condition is gone

(transition on RXD) and TXD is high. A read of the LIN Status Register (LINSR) without the RXD pin short-circuit condition clears the bit

RXSHORT.

6.1.14.6 TXD dominant detection (LIN interrupt)

The LIN transceiver monitors the TXD input pin to detect a stuck in dominant (0 V) condition. In case of a stuck condition (TXD pin 0 V for

more than 1 second (typ.)), the transmitter is shut down and the TXDOM bit in the LIN Status Register (LINSR) is set. If the LINM bit is

set in the IMR, an Interrupt IRQ is generated. The transmitter is automatically re-enabled once TXD is high. A read of the LIN Status

Register (LINSR) with the TXD pin at 5.0 V clears the bit TXDOM.

6.1.14.7 LIN receiver operation only

While in Normal mode, the activation of the RXONLY bit disables the LIN TXD driver. In case of a LIN error condition, this bit is

automatically set. If Stop mode is selected with this bit set, the LIN wake-up functionality is disabled and the RXD pin reflects the state of

the LIN bus.

6.1.14.8 Stop mode and wake-up feature

During Stop mode operation, the transmitter of the physical layer is disabled. The receiver is still active and able to detect wake-up events

on the LIN bus line. A dominant level longer than T_PROPWLfollowed by a rising edge generates a wake-up interrupt, and is reported in the

Interrupt Source Register (ISR). Also see Figure 11.

6.1.14.9 Sleep mode and wake-up feature

During Sleep mode operation, the transmitter of the physical layer is disabled. The receiver must be active to detect wake-up events on

the LIN bus line. A dominant level longer than T_PROPWLfollowed by a rising edge generates a system wake-up (Reset), and is reported

in the Interrupt Source Register (ISR). Also see Figure 10.

6.2

Logic commands and registers

6.2.1 33910 SPI interface and configuration

The serial peripheral interface creates the communication link between a microcontroller (master) and the 33910. The interface consists

of four pins (see Figure 19):

•

CS—Chip Select

MOSI—Master-out Slave-in

MISO—Master-in Slave-out

SCLK—Serial Clock

A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0)

and the slave replies with four system status bits (VMS, LINS, HSS, n.d.) + 4 bits of status information (S3:S0).

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CS

Register Write Data

A0 C3 C2

MOSI

MISO

A3

A2

A1

C1

S1

C0

S0

Register Read Data

VMS LINS HSS S3 S2

-

SCLK

Read Data Latch

Write Data Latch

Rising: 33910 changes MISO/

MCU changes MOSI

Falling: 33910 samples MOSI/

MCU samples MISO

Figure 19. SPI protocol

During the inactive phase of the CS (HIGH), the new data transfer is prepared. The falling edge of the CS indicates the start of a new data

transfer and puts the MISO in the low-impedance state and latches the analog status data (Register read data). With the rising edge of

the SPI clock (SCLK), the data is moved to MISO/MOSI pins. With the falling edge of the SPI clock (SCLK), the data is sampled by the

receiver.

The data transfer is only valid if exactly eight sample clock edges are present during the active (low) phase of CS. The rising edge of the

Chip Select CS indicates the end of the transfer and latches the write data (MOSI) into the register. The CS high forces MISO to the high-

impedance state. Register reset values are described along with the reset condition. Reset condition is the condition causing the bit to be

set to its reset value. The main reset conditions are:

- Power-On Reset (POR): the level at which the logic is reset and BATFAIL flag sets.

- Reset mode

- Reset done by the RST pin (ext_reset)

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6.3

SPI register overview

Table 8. System status register

BIT

Adress(A3:A0)

Register Name / Read/Write Information

SYSSR - System Status Register

7

6

5

4

R

VMS

LINS

HSS

-

$0 - $F

Table 9 summarizes the SPI Register content for Control Information (C3:C0) = W and status information (S3:S0) = R.

Table 9. SPI register overview

BIT

Adress(A3:A0)

Register Name / Read/Write Information

3

2

1

0

W

R

HVSE

0

MOD2

MOD1

MCR - Mode Control Register

VSR - Voltage Status Register

WUCR - Wake-up Control Register

WUSR - Wake-up Status Register

LINCR - LIN Control Register

LINSR - LIN Status Register

$0

$1

$2

$3

$4

$5

$6

$7

VSOV

VSUV

0

VDDOT

0

BATFAIL

L1WE

L1

R

W

R

0

-

R

-

L1

W

R

DIS_J2602

RXSHORT

PWMHS2

HS2OP

RXONLY

TXDOM

PWMHS1

HS2CL

WD2

LSR1

LINOT

HS2

LSR0

0

LINSR - LIN Status Register

R

0

HSCR - High-side Control Register

HSSR - High-side Status Register

W

R

HS1

HS1OP

WD1

CYST1

WDOFF

MX1

HS1CL

WD0

CYST0

WDWO

MX0

R

TIMCR - Timing Control Register

W

CS/WD

$A

CYST2

WDERR

MX2

WDSR - Watchdog Status Register

AMUXCR - Analog Multiplexer Control Register

CFR - Configuration Register

R

WDTO

L1DS

HVDD

HSM

$B

$C

$D

W

R

CYSX8

0

IMR - Interrupt Mask Register

LINM

ISR1

VMM

ISR0

$E

$F

ISR - Interrupt Source Register

ISR3

ISR2

ISR - Interrupt Source Register

R

ISR3

ISR2

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6.3.1 Register definitions

6.3.1.1

System status register - SYSSR

The System Status Register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It

summarizes the status of the Voltage Monitor Status (VMS), LIN Status (LINS) and High-side Status (HSS).

Table 10. System status register

S7

S6

S5

S4

Read

VMS

LINS

HSS

-

This read-only bit indicates one or more bits in the VSR are set.

1 = Voltage Monitor bit set

0 = None

BATFAIL

VDDOT

VSUV

VMS

VSOV

Figure 20. Voltage monitor status

This read-only bit indicates one or more bits in the LINSR are set.

1 = LIN Status bit set

0 = None

LINOT

LINS

TXDOM

RXSHORT

Figure 21. LIN status

This read-only bit indicates one or more bits in the HSSR are set.

1 = High-side Status bit set

0 = None

HS1CL

HS1OP

HS2CL

HS2OP

HSS

Figure 22. High-side status

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6.3.1.2

Mode control register - MCR

The Mode Control Register (MCR) allows switching between the operation modes and to configure the 33910. Writing the MCR returns

the VSR.

Table 11. Mode control register - $0

C3

HVSE

1

C2

0

C1

C0

Write

MOD2

MOD1

Reset Value

Reset Condition

0

-

POR

This write-only bit enables/disables automatic shutdown of the high-side drivers during a high-voltage VSOV condition.

1 = automatic shutdown enabled

0 = automatic shutdown disabled

These write-only bits select the operating mode and allow clearing the watchdog in accordance with Table 9, Mode Control Bits.

Table 12. Mode control bits

MOD2

MOD1

Description

0

1

0

1

0

1

Normal Mode

Stop Mode

Sleep Mode

Normal Mode + Watchdog Clear

6.3.1.3

Voltage status register - VSR

Returns the status of the several voltage monitors. This register is also returned when writing to the Mode Control Register (MCR).

Table 13. Voltage status register - $0/$1

S3

S2

S1

S0

Read

VSOV

VSUV

VDDOT

BATFAIL

6.3.1.3.1

VSOV - V

overvoltage

SUP

This read-only bit indicates an overvoltage condition on the VS1 pin.

1 = Overvoltage condition.

0 = Normal condition.

6.3.1.3.2

VSUV - V

undervoltage

SUP

This read-only bit indicates an undervoltage condition on the VS1 pin.

1 = Undervoltage condition.

0 = Normal condition.

6.3.1.3.3

VDDOT - main voltage regulator overtemperature warning

This read-only bit indicates the main voltage regulator temperature reached the Overtemperature Prewarning Threshold.

1 = Overtemperature Prewarning

0 = Normal

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6.3.1.3.4

BATFAIL - battery fail flag

This read-only bit is set during power-up and indicates the 33910 had a Power-On-Reset (POR). Any access to the MCR or VSR clears

the BATFAIL flag.

1 = POR Reset has occurred

0 = POR Reset has not occurred

6.3.1.4

Wake-up control register - WUCR

This register is used to control the digital wake-up input. Writing the WUCR returns the Wake-Up Status Register (WUSR).

Table 14. Wake-up Control Register - $2

C3

C2

C1

C0

Write

0

1

0

1

0

1

L1WE

1

Reset Value

Reset Condition

POR, Reset mode or ext_reset

6.3.1.4.1

L1WE - wake-up input enable

This write-only bit enables/disables the L1 input. In Stop and Sleep mode the L1WE bit activates the L1 input for wake-up. If the L1 input

is selected on the analog multiplexer, the L1WE is masked to 0.

1 = Wake-up Input enabled.

0 = Wake-up Input disabled.

6.3.1.5

Wake-up status register - WUSR

This register is used to monitor the digital wake-up input and is also returned when writing to the WUCR.

Table 15. Wake-up status register - $2/$3

S3

S2

S1

S0

Read

-

L1

6.3.1.5.1

L1 - wake-up input 1

This read-only bit indicates the status of the L1 input. If the L1 input is not enabled, then the Wake-up status returns 0. After a wake-up

from Stop or Sleep mode this bit also allows to verify the L1 input has caused the wake-up, by first reading the Interrupt Status Register

(ISR) and then reading the WUSR. The source of the wake-up is only reported on the first WUCR or WUSR access.

1 = L1 pin high, or L1 is the source of the wake-up.

0 = L1 pin low, disabled or selected as an analog input.

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6.3.1.6

LIN control register - LINCR

This register controls the LIN physical interface block. Writing the LIN Control Register (LINCR) returns the LIN Status Register (LINSR).

Table 16. LIN control register - $4

C3

C2

C1

C0

Write

DIS_J2602

0

RXONLY

0

LSR1

0

LSR0

0

Reset Value

POR, Reset mode, ext_reset

or LIN failure gone*

Reset Condition

POR

* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag resets automatically when the failure is gone.

6.3.1.6.1

J2602 - LIN dominant voltage select

This write-only bit controls the J2602 circuitry. If the circuitry is enabled (bit sets to 0), the TXD-LIN-RXD communication works down to

the battery undervoltage condition is detected. Below, the bus is in recessive state. If the circuitry is disabled (bit sets to 1), the

communication TXD-LIN-RXD works down to 4.6 V (typical value).

0 = Enabled J2602 feature.

1 = Disabled J2602 feature.

6.3.1.6.2

RXONLY - LIN receiver operation only

This write-only bit controls the behavior of the LIN transmitter. In Normal mode, the activation of the RXONLY bit disables the LIN

transmitter. In case of a LIN error condition, this bit is automatically set. In Stop mode this bit disables the LIN wake-up functionality, and

the RXD pin reflects the state of the LIN bus.

1 = only LIN receiver active (Normal mode) or LIN wake-up disabled (Stop mode).

0 = LIN fully enabled.

6.3.1.6.3

LSRx - LIN slew rate

This write-only bit controls the LIN driver slew rate in accordance with Table 18.

Table 17. LIN slew rate control

LSR1

LSR0

Description

0

1

0

1

0

1

Normal Slew Rate (up to 20 kb/s)

Slow Slew Rate (up to 10 kb/s)

Fast Slew Rate (up to 100 kb/s)

Reserved

6.3.1.7

LIN status register - LINSR

This register returns the status of the LIN physical interface block and is also returned when writing to the LINCR.

Table 18. LIN status register - $4/$5

S3

S2

S1

S0

Read

RXSHORT

TXDOM

LINOT

0

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6.3.1.7.1

RXSHORT - RXD pin short-circuit

This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The short-circuit delay must be

a worst case of 8.0 µs to be detected and to shut down the driver. To clear this bit, it must be read after the condition is gone (transition

detected on RXD pin). The LIN driver is automatically re-enabled once the condition is gone and TXD is high.

1 = RXD short-circuit condition.

0 = None.

6.3.1.7.2

TXDOM - TXD permanent dominant

This read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LIN

transmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second (typical value). To clear this bit,

it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes High.

1 = TXD stuck at dominant fault detected.

0 = None.

6.3.1.7.3

LINOT - LIN driver overtemperature

This read-only bit signals the LIN transceiver was shutdown due to overtemperature. The transmitter is automatically re-enabled after the

overtemperature condition is gone and TXD is high. The LINOT bit is cleared after SPI read once the condition is gone.

1 = LIN overtemperature shutdown

0 = None

6.3.1.8

High-side control register - HSCR

This register controls the operation of the high-side drivers. Writing to this register returns the High-side Status Register (HSSR).

Table 19. High-side control register - $6

C3

C2

C1

C0

Write

PWMHS2 PWMHS1

HS2

0

HS1

0

Reset Value

0

POR, Reset mode, ext_reset, HSx

overtemp or (VSOV & HVSE)

Reset Condition

POR

6.3.1.8.1

PWMHSx - PWM input control enable

This write-only bit enables/disables the PWMIN input pin to control the respective high-side switch. The corresponding high-side switch

must be enabled (HSx bit).

1 = PWMIN input controls HSx output.

0 = HSx is controlled only by SPI.

6.3.1.8.2

HSx - HSx switch control

This write-only bit enables/disables the corresponding high-side switch.

1 = HSx switch on.

0 = HSx switch off.

6.3.1.9

High-side status register - HSSR

This register returns the status of the high-side switches and is also returned when writing to the HSCR.

Table 20. High-side Status Register - $6/$7

S3

S2

S1

S0

Read

HS2OP

HS2CL

HS1OP

HS1CL

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6.3.1.9.1

High-side thermal shutdown

A thermal shutdown of the high-side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously.

6.3.1.9.2

HSxOP - high-side switch open load detection

This read-only bit signals the high-side switches are conducting current below a certain threshold indicating possible load disconnection.

1 = HSx Open Load detected (or thermal shutdown)

0 = Normal

6.3.1.9.3

HSxCL - high-side current limitation

This read-only bit indicates the respective high-side switch is operating in current limitation mode.

1 = HSx in current limitation (or thermal shutdown)

0 = Normal

6.3.1.10 Timing control register - TIMCR

This register allows to configure the watchdog, the cyclic sense and Forced Wake-up periods. Writing to the Timing Control Register

(TIMCR) also returns the Watchdog Status Register (WDSR).

Table 21. Timing control register - $A

C3

C2

C1

C0

WD2

CYST2

0

WD1

CYST1

0

WD0

CYST0

0

Write

CS/WD

Reset Value

-

Reset Condition

POR

6.3.1.10.1 CS/WD - cyclic sense or watchdog prescaler select

This write-only bit selects which prescaler is being written to, the Cyclic Sense/Forced Wake-up prescaler or the Watchdog prescaler.

1 = Cyclic Sense/Forced Wake-up Prescaler selected

0 = Watchdog Prescaler select

6.3.1.10.2 WDx - watchdog prescaler

This write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 22.

This configuration is valid only if windowing watchdog is active.

Table 22. Watchdog prescaler

WD2

WD1

WD0

Prescaler divider

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

6

8

10

12

14

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6.3.1.10.3 CYSTx - cyclic sense period prescaler select

This write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the Configuration Register (CFR)

(See Configuration register - CFR on page 47). This option is only active if one of the high-side switches is enabled when entering in Stop

or Sleep mode. Otherwise, a timed wake-up is performed after the period shown in Table 23.

Table 23. Cyclic sense and force wake-up interval

CYSX8 ⁽⁶⁸⁾

CYST2

CYST1

CYST0

Interval

No cyclic sense ⁽⁶⁹⁾

20 ms

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

40 ms

60 ms

80 ms

100 ms

120 ms

140 ms

160 ms

320 ms

480 ms

640 ms

800 ms

960 ms

1120 ms

Notes

68. Bit CYSX8 is located in Configuration Register (CFR)

69. No Cyclic Sense and no Force Wake-up available.

6.3.1.11 Watchdog status register - WDSR

This register returns the Watchdog status information and is also returned when writing to the TIMCR.

Table 24. Watchdog status register - $A/$B

S3

S2

S1

S0

Read

WDTO

WDERR WDOFF WDWO

6.3.1.11.1 WDTO - watchdog timeout

This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the Watchdog within the window

closed. Any access to this register or the Timing Control Register (TIMCR) clears the WDTO bit.

1 = Last reset caused by watchdog timeout

0 = None

6.3.1.11.2 WDERR - watchdog error

This read-only bit signals the detection of a missing watchdog resistor. In this condition, the watchdog is using the internal, lower precision

timebase. The Windowing function is disabled.

1 = WDCONF pin resistor missing

0 = WDCONF pin resistor not floating

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6.3.1.11.3 WDOFF - watchdog off

This read-only bit signals the watchdog pin connected to Ground and therefore disabled. In this case watchdog timeouts are disabled and

the device automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming the

Flash memory.

1 = Watchdog is disabled

0 = Watchdog is enabled

6.3.1.11.4 WDWO - watchdog window open

This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case

WDERR is High.

1 = Watchdog window open

0 = Watchdog window closed

6.3.1.12 Analog multiplexer control register - MUXCR

This register controls the analog multiplexer and selects the divider ration for the L1 input divider.

Table 25. Analog Multiplexer Control Register -$C

C3

C2

C1

C0

Write

L1DS

1

MX2

0

MX1

0

MX0

0

Reset Value

POR, Reset mode or

ext_reset

Reset Condition

POR

6.3.1.12.1 L1DS - L1 analog input divider select

This write-only bit selects the resistor divider for the L1 analog input. Voltage is internally clamped to VDD.

0 = L1 Analog divider: 1

1 = L1 Analog divider: 3.6 (typ.)

6.3.1.13 MXx - analog multiplexer input select

These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 26. When disabled or when in Stop

or Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption.

Table 26. Analog multiplexer channel select

MX2

MX1

MX0

Meaning

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Disabled

Reserved

Die Temperature Sensor ⁽⁷⁰⁾

VSENSE input

L1 input

Reserved

Notes

70. Accessing the Die Temperature Sensor directly from the Disabled state is not

recommended. If this transition must be performed and to avoid the intermediate

state, wait at least 1.0 ms, then start the die temp measurement. Possible access is

^Disabled→ Vsense input → Die Temperature Sensor.

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6.3.1.14 Configuration register - CFR

This register controls the Hall Sensor Supply enable/disable and the cyclic sense timing multiplier.

Table 27. Configuration register - $D

C3

C2

C1

C0

Write

HVDD

0

CYSX8

0

Reset Value

POR, Reset mode

or ext_reset

Reset Condition

POR

6.3.1.14.1 HVDD - hall sensor supply enable

This write-only bit enables/disables the state of the hall sensor supply.

1 = HVDD on

0 = HVDD off

6.3.1.14.2 CYSX8 - cyclic sense timing x eight

This write-only bit influences the cyclic sense and Forced Wake-up period as shown in Table 23.

1 = Multiplier enabled

0 = None

6.3.1.15 Interrupt mask register - IMR

This register allows masking of some of the interrupt sources. No interrupt is generated to the MCU and no flag is set in the ISR register.

The 5.0 V Regulator overtemperature prewarning interrupt and undervoltage (VSUV) interrupts can not be masked and always causes

an interrupt. Writing to the IMR returns the ISR.

Table 28. Interrupt mask register - $E

C3

C2

C1

C0

Write

HSM

1

0

1

LINM

1

VMM

1

Reset Value

Reset Condition

POR

6.3.1.15.1 HSM - high-side interrupt mask

This write-only bit enables/disables interrupts generated in the high-side block.

1 = HS Interrupts Enabled

0 = HS Interrupts Disabled

6.3.1.15.2 LINM - LIN interrupts mask

This write-only bit enables/disables interrupts generated in the LIN block.

1 = LIN Interrupts Enabled

0 = LIN Interrupts Disabled

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47

6.3.1.15.3 VMM - voltage monitor interrupt mask

This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor

Block is the V_SUPovervoltage interrupt.

1 = Interrupts Enabled

0 = Interrupts Disabled

6.3.1.16 Interrupt source register - ISR

This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges

the interrupt and leads IRQ pin to high, if there are no other pending interrupts. If there are pending interrupts, IRQ is driven high for 10 µs

and then be driven low again.

This register is also returned when writing to the Interrupt Mask Register (IMR).

Table 29. Interrupt source register - $E/$F

S3

S2

S1

S0

Read

ISR3

ISR2

ISR1

ISR0

6.3.1.16.1 ISRx - interrupt source register

These read-only bits indicate the interrupt source following Table 30. If no interrupt is pending then all bits are 0. If more than one interrupt

is pending, the interrupt sources are handled sequentially multiplex.

Table 30. Interrupt sources

Interrupt source

ISR3 ISR2 ISR1 ISR0

Priority

none maskable

maskable

0

1

0

1

0

1

0

1

0

no interrupt

none

L1 Wake-up from Stop and Sleep mode

-

highest

-

HS Interrupt (Overtemperature)

Reserved

-

LIN Wake-up

LIN Interrupt (RXSHORT, TXDOM, LIN OT)

Voltage Monitor Interrupt

(Low Voltage and VDD overtemperature)

Voltage Monitor Interrupt

(High Voltage)

0

1

0

1

0

Forced Wake-up

-

lowest

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7

Typical application

The 33910 can be configured in several applications. The figure below shows the 33910 in the typical slave node application.

V

BAT

D1

C2

C1

VDD

IRQ

Interrupt

Control Module

LVI, HVI, HTI, OCI

Voltage Regulator

C5

C4

C3

AGND

HVDD

5.0 V Output Module

Hall Sensor Supply

VDD

Reset

Control Module

LVR, HVR, HTR, WD,

RST

IRQ

RST

Window

R1

Watchdog Module

PWMIN

TIMER

High-side Control

Module

HS1

HS2

MISO

MOSI

SCLK

CS

Chip Temp Sense Module

SPI

&

CONTROL

SPI

VSENSE

VBAT Sense Module

Analog Input Module

MCU

R2

L1

ADOUT0

A/D

Wake-up Module

Digital Input Module

RXD

TXD

LIN Physical Layer

SCI

A/D

LIN

C6

Typical Component Values:

C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 220 pF

R1 = 10 kΩ; R2 = 20 kΩ-200 kΩ

R7

Recommended Configuration of the not Connected Pins (NC):

Pin 15, 16, 17, 19, 20, 21, 22 = GND

Pin 11 = open (floating)

Pin 28 = this pin is not internally connected and may be used for PCB routing

optimization.

33910

NXP Semiconductors

49

8

MC33911BAC product specifications - page 50 to page 95

33910

50

NXP Semiconductors

9

Internal block diagram

RST IRQ

VS2

VS1

VDD

INTERRUPT

CONTROL

MODULE

AGND

PGND

VOLTAGE REGULATOR

LVI, HVI, HTI, OCI

RESET CONTROL

MODULE

LVR, HVR, HTR, WD

5V OUTPUT

MODULE

HVDD

WINDOW

WATCHDOG

MODULE

VS2

HIGH-SIDE

CONTROL

MODULE

PWMIN

HS1

HS2

VS2

MISO

MOSI

SCLK

SPI

&

CONTROL

V_BAT

SENSE MODULE

VSENSE

CS

CHIP TEMPERATURE

SENSE MODULE

ADOUT0

L1

ANALOG INPUT

MODULE

WAKE-UP MODULE

DIGITAL INPUT MODULE

RXD

TXD

LIN PHYSICAL

LAYER

LIN

LGND

WDCONF

Figure 23. 33910 Simplified internal block diagram

33910

NXP Semiconductors

51

10 Pin connections

10.1 Pinout diagram

RXD

TXD

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

HS2

L1

MISO

NC*

PGND

NC*

MOSI

SCLK

CS

ADOUT0

PWMIN

* Special Configuration Recommended /

Mandatory for Marked NC Pins

Figure 24. 33910 pin connections

10.2 Pin definitions

A functional description of each pin can be found in the Functional pin description.

Table 31. 33910 pin definitions

Pin name

Formal name

Definition

This pin is the receiver output of the LIN interface which reports the state of the bus

voltage to the MCU interface.

1

RXD

Receiver Output

This pin is the transmitter input of the LIN interface which controls the state of the bus

output.

2

TXD

Transmitter Input

3

4

5

6

7

8

MISO

MOSI

SPI Output

SPI Input

SPI data output. When CS is high, the pin is in the high-impedance state.

SPI data input.

SCLK

SPI Clock

SPI clock Input.

CS

SPI Chip Select

SPI chip select input pin. CS is active low.

ADOUT0

PWMIN

Analog Output Pin 0 Analog multiplexer output.

PWM Input High-side pulse width modulation input.

33910

52

NXP Semiconductors

Table 31. 33910 pin definitions (continued)

Pin name

Formal name

Definition

Bidirectional reset I/O pin - driven low when any internal reset source is asserted. RST

is active low.

9

RST

Internal Reset I/O

Internal Interrupt

Output

Interrupt output pin, indicating wake-up events from Stop mode or events from Normal

and Normal Request modes. IRQ is active low.

10

IRQ

NC

11, 15-17,

19-22, 28

No connect

Watchdog

Configuration Pin

This input pin is for configuration of the watchdog period and allows the disabling of the

watchdog.

12

WDCONF

13

14

LIN

LIN Bus

This pin represents the single-wire bus transmitter and receiver.

LGND

LIN Ground Pin

This pin is the device LIN ground connection. It is internally connected to the PGND pin.

This pin is the device power ground connection. It is internally connected to the LGND

pin.

18

PGND

Power Ground Pin

This pin is a wake-up capable digital input ⁽⁷¹⁾. In addition, L1 can be sensed analog via

the analog multiplexer.

23

24, 25

26, 27

29

L1

Wake-up Input

High-side Outputs

Power Supply Pin

Voltage Sense Pin

HS2, HS1

VS2, VS1

VSENSE

HVDD

High-side switch outputs.

These pins are device battery level power supply pins. VS2 is supplying the HS1 driver

while VS1 supplies the remaining blocks.⁽⁷²⁾

Battery voltage sense input.⁽⁷³⁾

Hall Sensor Supply

Output

30

+5.0 V switchable supply output pin.⁽⁷⁴⁾

Voltage Regulator

Output

31

32

VDD

+5.0 V main voltage regulator output pin.⁽⁷⁵⁾

This pin is the device analog ground connection.

AGND

Analog Ground Pin

Notes

71. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.

72. Reverse battery protection series diodes must be used externally to protect the internal circuitry.

73. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It is

strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

74. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.

75. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required.

33910

NXP Semiconductors

53

11 Electrical characteristics

11.1 Maximum ratings

Table 32. Maximum ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Ratings

Value

Unit

Notes

Electrical ratings

Supply Voltage at VS1 and VS2

• Normal Operation (DC)

• Transient Conditions (load dump)

V

-0.3 to 27

-0.3 to 40

SUP(SS)

V

V_SUP(PK)

V_DD

Supply Voltage at VDD

-0.3 to 5.5

(76)

(77)

Input / Output Pins Voltage

• CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD

• Interrupt Pin (IRQ)

V

-0.3 to V_DD+0.3

-0.3 to 11

IN

V

IN(IRQ)

V

-0.3 to V_SUP+0.3

HS1 Pin Voltage (DC)

HS2 Pin Voltage (DC)

V

HS1

V

HS2

L1 Pin Voltage

V

-18 to 40

±100

L1DC

• Normal Operation with a series 33 kΩ resistor (DC)

• Transient input voltage with external component (according to ISO7637-2)

(See Figure 26)

V

A

V

L1TR

V_VSENSE

VSENSE Pin Voltage (DC)

-27 to 40

LIN Pin Voltage

• Normal Operation (DC)

• Transient input voltage with external component (according to ISO7637-2)

(See Figure 26)

V_BUSDC

V_BUSTR

-18 to 40

-150 to 100

I

VDD output current

Internally Limited

VDD

ESD Voltage

V

ESD1-1

ESD1-2

±8000

±2000

±150

• Human Body Model - LIN Pin

• Human Body Model - all other Pins

• Machine Model

(78)

(79)

V

ESD2

• Charge Device Model

±750

±500

V

• Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25, and 32)

• All other Pins (Pins 2-7, 10-15, 18-23, 26-31)

ESD3-1

ESD3-2

V_NC

NC Pin Voltage (NC pins 11, 15, 16, 17, 19, 20, 21, 22, and 28)

Note 79

Notes

76. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.

77. Extended voltage range for programming purpose only.

78. Testing is performed in accordance with the Human Body Model (C

= 100 pF, R

= 1500 Ω), the Machine Model (C = 200 pF,

ZAP

R

= 0 Ω), and the Charge Device Model, Robotic (C

= 4.0 pF).

ZAP

79. Special configuration recommended / mandatory for marked NC pins. Please refer to the typical application.

33910

54

NXP Semiconductors

Table 32. Maximum ratings (continued)

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Ratings

Value

Unit

Notes

Thermal ratings

Operating Ambient Temperature

• 33910

• 34910

(80)

T

A

-40 to 125

-40 to 85

°C

T

J

Operating Junction Temperature

Storage Temperature

-40 to 150

-55 to 150

°C

T_STG

Thermal Resistance, Junction to Ambient

• Natural Convection, Single Layer board (1s)

• Natural Convection, Four Layer board (2s2p)

(81), (82)

(81), (83)

R_θJA

85

56

°C/W

(84)

R_θJC

Thermal Resistance, Junction to Case

23

°C/W

(85), (86)

T_PPRT

Peak Package Reflow Temperature During Reflow

Note 86

°C

Notes

80. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.

81. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

82. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

83. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

84. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

85. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

86. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

Moisture Sensitivity Levels (MSL), Go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all

orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

33910

NXP Semiconductors

55

11.2 Static electrical characteristics

Table 33. Static electrical characteristics

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Supply voltage range (VS1, VS2)

V_SUP

5.5

–

18

27

40

V

Nominal Operating Voltage

Functional Operating Voltage

Load Dump

(87)

V_SUPOP

V_SUPLD

–

Supply current range (V_SUP= 13.5 V)

(88)

I_RUN

Normal Mode (I_OUTat V

= 10 mA), LIN Recessive State

–

4.5

10

mA

µA

DD

Stop Mode, VDD ON with I_OUT= 100 µA, LIN Recessive State

• 5.5 V < V_SUP< 12 V

(88), (89),

(90)

I_STOP

–

48

58

80

90

• V_SUP= 13.5 V

Sleep Mode, VDD OFF, LIN Recessive State

• 5.5 V < V_SUP< 12 V

(88), (90)

(91)

I_SLEEP

–

27

37

35

48

µA

• 12 V ≤ V_SUP< 13.5 V

I_CYCLIC

Cyclic Sense Supply Current Adder

–

10

–

Supply under/overvoltage detections

Power-On Reset (BATFAIL)

• Threshold (measured on VS1)

• Hysteresis (measured on VS1)

V_BATFAIL

(92), (91)

1.5

–

3.0

0.9

3.9

–

V

V_{BATFAIL_HYS}

V_SUPundervoltage detection (VSUV Flag) (Normal and Normal

Request modes, Interrupt Generated)

• Threshold (measured on VS1)

• Hysteresis (measured on VS1)

V_SUV

V_{SUV_HYS}

5.55

–

6.0

1.0

6.6

–

V_SUPovervoltage detection (VSOV Flag) (Normal and Normal

Request modes, Interrupt Generated)

• Threshold (measured on VS1)

• Hysteresis (measured on VS1)

V

V_SOV

V_{SOV_HYS}

18

–

19.25

1.0

20.5

–

Notes

87. Device is fully functional. All features are operating.

88. Total current (I_VS1+ I_VS2) measured at GND pins excluding all loads, Cyclic Sense disabled.

89. Total I_DDcurrent (including loads) below 100 µA.

90. Stop and Sleep mode currents increases if V_SUPexceeds 13.5 V.

91. This parameter is guaranteed by process monitoring but, not production tested.

92. The flag is set during power up sequence. To clear the flag, a SPI read must be performed.

33910

56

NXP Semiconductors

Table 33. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Voltage regulator ⁽⁹³⁾(VDD)

Normal Mode Output Voltage

• 1.0 mA < I < 50 mA; 5.5 V < V

V_DDRUN

I_VDDRUN

V_DDDROP

4.75

60

–

5.00

110

0.1

5.25

200

V

mA

V

< 27 V

SUP

VDD

Normal Mode Output Current Limitation

Dropout Voltage

(94)

0.25

• I

= 50 mA

VDD

Stop Mode Output Voltage

• I < 5.0 mA

V

4.75

6.0

5.0

12

5.25

36

V

DDSTOP

VDD

I

Stop Mode Output Current Limitation

Line Regulation

mA

VDDSTOP

LR

• Normal mode, 5.5 V < V

< 18 V; I

= 10 mA

VDD

RUN

–

20

5.0

25

mV

SUP

LR

• Stop mode, 5.5 V < V

< 18 V; I

= 1.0 mA

VDD

STOP

SUP

Load Regulation

LD

• Normal mode, 1.0 mA < I

< 50 mA

RUN

–

15

10

80

50

mV

°C

VDD

LD

• Stop mode, 0.1 mA < I

< 5.0 mA

STOP

VDD

Overtemperature Prewarning (Junction)

• Interrupt generated, Bit VDDOT Set

(95)

T

110

125

140

PRE

(95)

T

Overtemperature Prewarning hysteresis

–

155

–

10

170

10

–

185

–

°C

PRE_HYS

T

Overtemperature Shutdown Temperature (Junction)

Overtemperature Shutdown hysteresis

SD

T

SD_HYS

Hall sensor supply output ⁽⁹⁶⁾(HVDD)

V

Voltage matching H_VDDACC= (H_VDD-V_DD) / V_DD* 100%

DD

H

-2.0

20

–

2.0

50

%

VDDACC

• I_HVDD= 15 mA

I

Current Limitation

30

mA

mV

HVDD

Dropout Voltage

• I_{HVDD =}15 mA; I_VDD= 5.0 mA

H

160

300

VDDDROP

Line Regulation

• I_HVDD= 5.0 mA; I_VDD= 5.0 mA

LR

–

25

10

40

20

mV

HVDD

Load Regulation

• 1.0 mA > I_HVDD> 15 mA; I_VDD= 5.0 mA

LD

Notes

93. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

94. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).

95. This parameter is guaranteed by process monitoring but, not production tested.

96. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

33910

NXP Semiconductors

57

Table 33. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

RST input/output pin (RST)

V_RSTTH

V_OL

VDD Low Voltage Reset Threshold

4.3

0.0

4.5

–

4.7

0.9

V

Low-state Output Voltage

• I_OUT= 1.5 mA; 3.5 V ≤ V_SUP≤ 27 V

I_OH

High-state Output Current (0 < V_OUT< 3.5 V)

-150

1.5

-250

–

-350

8.0

µA

mA

Pull-down Current Limitation (internally limited)

V_OUT= V_DD

I_{PD_MAX}

V_IL

V_IH

0.3 x V_DD

V_DD+ 0.3

Low-state Input Voltage

High-state Input Voltage

-0.3

–

V

0.7 x V_DD

MISO SPI output pin (MISO)

Low-state Output Voltage

• I = 1.5 mA

V_OL

0.0

–

1.0

V

OUT

High-state Output Voltage

• I_OUT= -250 µA

V_OH

V_DD- 0.9

V_DD

Tri-state Leakage Current

I_TRIMISO

-10

10

µA

• 0 V ≤ V_MISO≤ V_DD

SPI input pins (MOSI, SCLK, CS)

V_IL

V_IH

0.3 x V_DD

V_DD+ 0.3

Low-state Input Voltage

High-state Input Voltage

-0.3

–

V

0.7 x V_DD

MOSI, SCLK Input Current

I_IN

-10

10

–

10

30

µA

• 0 V ≤ V_IN≤ V_DD

CS Pull-up current

• 0 V < V_IN< 3.5 V

I_PUCS

20

Interrupt output pin (IRQ)

Low-state Output Voltage

• I_OUT= 1.5 mA

V_OL

V_OH

0.0

–

0.8

V

High-state Output Voltage

• I_OUT= -250 µA

V_DD- 0.8

V_DD

Leakage current

• V_DD≤ V_OUT≤ 10 V

–

2.0

mA

Pulse width modulation input pin (PWMIN)

V_IL

V_IH

0.3 x V_DD

V_DD+ 0.3

Low-state Input Voltage

High-state Input Voltage

-0.3

–

V

0.7 x V_DD

Pull-up current

• 0 V < V_IN< 3.5 V

I_PUPWMIN

10

20

30

µA

33910

58

NXP Semiconductors

Table 33. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

High-side output HS1 and HS2 pins (HS1, HS2)

Output Drain-to-Source On Resistance

Characteristic

Min.

Typ.

Max.

Unit

Notes

• T_J= 25 °C, I_LOAD= 50 mA; V_SUP> 9.0 V

• T_J= 150 °C, I_LOAD= 50 mA; V_SUP> 9.0 V

• T_J= 150 °C, I_LOAD= 30 mA; 5.5 V < V_SUP< 9.0 V

–

7.0

10

14

(97)

R_DS(on)

Ω

Output Current Limitation

• 0 V < V_OUT< V_SUP- 2.0 V

(98)

(99)

I_LIMHS1

60

120

250

mA

I_OLHSx

I_LEAK

Open Load Current Detection

–

5.0

–

7.5

10

mA

µA

Leakage Current (-0.2 V < V_HSx< V_S2+ 0.2 V)

Short-circuit Detection Threshold

• 5.5 V < V_SUP< 27 V

(100)

V_THSC

V_SUP- 2

–

V

(101),

(102)

T_HSSD

Overtemperature Shutdown

150

–

165

10

180

–

°C

(102)

T_{HSSD_HYS}

Overtemperature Shutdown Hysteresis

L1 input pin (L1)

Low Detection Threshold

• 5.5 V < V_SUP< 27 V

V_THL

V_THH

V_HYS

2.0

3.0

0.5

2.5

3.5

1.0

3.0

4.0

1.5

V

High Detection Threshold

• 5.5 V < V_SUP< 27 V

Hysteresis

• 5.5 V < V_SUP< 27 V

Input Current

• -0.2 V < V_IN< VS1

(103)

(104)

I_IN

-10

–

10

–

µA

R_L1IN

Analog Input Impedance

800

1550

kΩ

Analog Input Divider Ratio (RATIO_L1= V_L1/ V_ADOUT0

• L1DS (L1 Divider Select) = 0

• L1DS (L1 Divider Select) = 1

)

RATIO_L1

0.95

3.42

1.0

3.6

1.05

3.78

Analog Output Offset Ratio

• L1DS (L1 Divider Select) = 0

• L1DS (L1 Divider Select) = 1

V_{RATIOL1-OFFSET}

-80

-22

0.0

80

22

mV

%

Analog Inputs Matching

• L1DS (L1 Divider Select) = 0

• L1DS (L1 Divider Select) = 1

L1_MATCHING

96

100

104

Notes

97. This parameter is production tested up to T_A= 125 °C and guaranteed by process monitoring up to T_J= 150 °C.

98. When overcurrent occurs, the high-side stays ON with limited current capability and the HS1CL flag is set in the HSSR.

99. When open-load occurs, the flag (HS1OP) is set in the HSSR.

100. When short circuit occurs and if HVSE flag is enabled, HS1 automatic shutdown.

101. When overtemperature shutdown occurs, both high-sides are turned off. All flags in HSSR are set.

102. Guaranteed by characterization but, not production tested

103. Analog multiplexer input disconnected from L1 input pin.

104. Analog multiplexer input connected to L1 input pin.

33910

NXP Semiconductors

59

Table 33. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Window watchdog configuration pin (WDCONF)

R

External Resistor Range

20

–

200

15

kΩ

EXT

Watchdog Period Accuracy with External Resistor (Excluding Resistor

Accuracy)

(105)

WD

-15

%

ACC

Analog multiplexer

S_TTOV

Internal Chip Temperature Sense Gain

–

10.5

5.25

–

mV/K

mV

VSENSE Input Divider Ratio (RATIO_VSENSE= V_VSENSE/ V_ADOUT0

• 5.5 V < V_SUP< 27 V

)

RATIO_VSENSE

5.0

5.5

VSENSE Output Related Offset

• -40 °C < T_A< -20 °C

-30

-45

–

30

45

OFFSET_VSENSE

Analog output (ADOUT0)

Maximum Output Voltage

V_{OUT_MAX}

V_DD- 0.35

0.0

V_DD

0.35

–

V

• -5.0 mA < I_O< 5.0 mA

Minimum Output Voltage

• -5.0 mA < I_O< 5.0 mA

V_{OUT_MIN}

RXD output pin (LIN physical layer) (RXD)

Low-state Output Voltage

• I_OUT= 1.5 mA

V_OL

0.0

–

0.8

V

High-state Output Voltage

• I_OUT= -250 µA

V_OH

V_DD-0.8

V_DD

TXD input pin (LIN physical layer) (TXD)

V_IL

V_IH

0.3 x nV_DD

V_DD+ 0.3

30

Low-state Input Voltage

-0.3

–

V

0.7 x V_DD

High-state Input Voltage

I_PUIN

Pin Pull-up Current, 0 < V_IN< 3.5 V

10

20

µA

Notes

105. Watchdog timing period calculation formula: t_PWD[ms] = 0.466 * (R_EXT- 20) + 10 (R_EXTin kΩ)

33910

60

NXP Semiconductors

Table 33. Static electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

LIN physical layer, transceiver (LIN)⁽¹⁰⁶⁾

Output Current Limitation

I_BUSLIM

40

120

200

mA

• Dominant State, V_BUS= 18 V

Leakage Output Current to GND

• Dominant State; V_BUS= 0 V; V_BAT= 12 V

I_{BUS_PAS_DOM}

I_{BUS_PAS_REC}

-1.0

–

20

mA

µA

• Recessive State; 8.0 V < V_BAT< 18 V; 8.0 V < V_BUS< 18 V;

V_BUS≥ V_BAT

• GND Disconnected; GND_DEVICE= V_SUP; V_BAT= 12 V; 0 < V

18 V

I_{BUS_NO_GND}

I_BUS

-1.0

–

1.0

mA

µA

<

BUS

100

• V

disconnected; V_{SUP_DEVICE}= GND; 0 < V

< 18 V

BUS

BAT

Receiver Input Voltages

• Receiver Dominant State

• Receiver Recessive State

• Receiver Threshold Center (V_{TH_DOM}+ V_{TH_REC})/2

• Receiver Threshold Hysteresis (V_{TH_REC}- V_{TH_DOM}

V_BUSDOM

V_BUSREC

V_{BUS_CNT}

V_HYS

–

0.6

0.475

–

0.5

–

0.4

–

0.525

0.175

V_SUP

)

LIN Transceiver Output Voltage

• Recessive State, TXD HIGH, I

V_{LIN_REC}

V_SUP-1

–

= 1.0 µA

OUT

V_{LIN_DOM_0}

1.1

1.4

• Dominant State, TXD LOW, 500 Ω External Pull-up Resistor,

LDVS = 0

V

V_{LIN_DOM_1}

–

1.7

2.0

• Dominant State, TXD LOW, 500 Ω External Pull-up Resistor,

LDVS = 1

R_SLAVE

T_LINSD

LIN Pull-up Resistor to V

SUP

20

150

–

30

165

10

60

180

–

kΩ

°C

(107)

Overtemperature Shutdown

T_{LINSD_HYS}

Overtemperature Shutdown Hysteresis

Notes

106. Parameters guaranteed for 7.0 V ≤ V_SUP≤ 18 V.

107. When Overtemperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.

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11.3 Dynamic electrical characteristics

Table 34. Dynamic electrical characteristics

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

SPI interface timing (Figure 34)

f_SPIOP

t_PSCLK

t_WSCLKH

t_WSCLKL

t_LEAD

SPI Operating Frequency

SCLK Clock Period

–

4.0

N/A

MHz

ns

250

110

100

40

(108)

SCLK Clock High Time

SCLK Clock Low Time

ns

Falling Edge of CS to Rising Edge of SCLK

Falling Edge of SCLK to CS Rising Edge

MOSI to Falling Edge of SCLK

Falling Edge of SCLK to MOSI

MISO Rise Time

ns

t_LAG

ns

t_SISU

ns

t_SIH

40

ns

(108)

t_RSO

–

40

–

ns

• C = 220 pF

L

MISO Fall Time

• C = 220 pF

L

t_FSO

Time from Falling or Rising Edges of CS to:

• MISO Low-impedance

• MISO High-impedance

(108)

t_SOEN

t_SODIS

0.0

–

50

ns

Time from Rising Edge of SCLK to MISO Data Valid

• 0.2 x V_DD≤ MISO ≥ 0.8 x V_DD, C_L= 100 pF

t_VALID

0.0

–

75

RST output pin

t_RST

Reset Low-level Duration after V_DDHigh (See Figure 33)

Reset Deglitch Filter Time

0.65

350

1.0

1.35

900

ms

ns

t_RSTDF

600

Window watchdog configuration pin (WDCONF)

Watchdog Time Period

• External Resistor R_EXT= 20 kΩ (1%)

• External Resistor R_EXT= 200 kΩ (1%)

• Without External Resistor R_EXT(WDCONF Pin Open)

8.5

79

110

10

94

150

11.5

108

205

(109)

t_PWD

ms

Notes

108. This parameter is guaranteed by process monitoring but, not production tested.

109. Watchdog timing period calculation formula: t_PWD[ms] = 0.466 * (R_EXT- 20) + 10 (R_EXTin kΩ)

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Table 34. Dynamic electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

L1 input

t_WUF

Characteristic

Min.

Typ.

Max.

Unit

Notes

Wake-up Filter Time

8.0

20

38

μs

State machine timing

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop

Command) and Stop Mode Activation

(110)

(111)

t_STOP

μs

–

5.0

t_NRTOUT

Normal Request Mode Timeout (see Figure 33)

110

150

205

ms

Delay Between SPI Command and HS Turn On

• 9.0 V < V_SUP< 27 V

t_S-ON

–

10

μs

Delay Between SPI Command and HS Turn Off

• 9.0 V < V_SUP< 27 V

(111)

(110)

t_S-OFF

–

10

μs

Delay Between Normal Request and Normal Mode After a Watchdog

Trigger Command (Normal Request mode)

t_SNR2N

Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:

• Normal Request mode, VDD ON and RST HIGH

• First Accepted SPI Command

t_WUCS

t_WUSPI

9.0

90

15

—

80

N/A

μs

t_2CS

Minimum Time Between Rising and Falling Edge on the CS

4.0

—

LIN physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec ^{(112), (113)}

Duty Cycle 1: D1 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT= 50 µs

D1

0.396

—

• 7.0 V ≤ V_SUP≤ 18 V

Duty Cycle 2: D2 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT= 50 µs

D2

0.581

• 7.6 V ≤ V_SUP≤ 18 V

LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec ^(112),(114)

Duty Cycle 3: D3 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT= 96 µs

D3

0.417

—

μs

• 7.0 V ≤ V_SUP≤ 18 V

Duty Cycle 4: D4 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT= 96 µs

D4

0.590

• 7.6 V ≤ V_SUP≤ 18 V

Notes

110. This parameter is guaranteed by process monitoring but, not production tested.

111. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.

112. Bus load R_BUSand C_BUS1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold

defined at each parameter. See Figure 27.

113. See Figure 28.

114. See Figure 29.

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Table 34. Dynamic electrical characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40 °C ≤ T_A≤ 125 °C for the 33910 and -40 °C ≤ T_A≤ 85 °C for the 34910,

unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Symbol

LIN physical layer: driver characteristics for fast slew rate

SR_FAST

Characteristic

Min.

Typ.

Max.

Unit

Notes

LIN Fast Slew Rate (Programming mode)

—

20

—

V/μs

LIN physical layer: characteristics and wake-up timings ⁽¹¹⁵⁾

Propagation Delay and Symmetry

t_{REC_PD}

(116)

(117)

• Propagation Delay Receiver, t_{REC_PD}= max (t_{REC_PDR}, t_{REC_PDF}

• Symmetry of Receiver Propagation Delay t_{REC_PDF}- t_{REC_PDR}

)

—

-2.0

3.0

—

6.0

2.0

μs

s

t_{REC_SYM}

t_PROPWL

Bus Wake-up Deglitcher (Sleep and Stop modes)

42

70

95

Bus Wake-up Event Reported

• From Sleep mode

• From Stop mode

(118)

(119)

t_WAKE

—

9.0

—

13

1500

17

t_TXDDOM

TXD Permanent Dominant State Delay

0.65

1.0

1.35

Pulse width modulation input pin (PWMIN)

PWMIN pin

f_PWMIN

(120)

—

10

—

kHz

• Max. frequency to drive HS output pins

Notes

115.

V

_SUPfrom 7.0 V to 18 V, bus load R_BUSand C_BUS1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to

LIN signal threshold defined at each parameter. See Figure 6.

116. See Figure 9.

117. See Figure 10, for Sleep and Figure 11, for Stop mode.

118. The measurement is done with 1.0 µF capacitor and 0 mA current load on V_DD. The value takes into account the delay to charge the capacitor.

The delay is measured between the bus wake-up threshold (V_BUSWU) rising edge of the LIN bus and when V reaches 3.0 V. See Figure 10. The

DD

delay depends of the load and capacitor on V_DD

.

119. In Stop mode, the delay is measured between the bus wake-up threshold (V_BUSWU) and the falling edge of the IRQ pin. See Figure 11.

120. This parameter is guaranteed by process monitoring but, not production tested.

11.4 Timing diagrams

33910

TRANSIENT PULSE

GENERATOR

1.0 nF

LIN

(

NOTE

)

GND

PGND LGND AGND

NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

Figure 25. Test circuit for transient test pulses (LIN)

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NXP Semiconductors

33910

TRANSIENT PULSE

GENERATOR

(NOTE)

1.0 nF

L1

10 kΩ

GND

PGND LGND AGND

NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

Figure 26. Test circuit for transient test pulses (L1)

V_SUP

R0

LIN

TXD

RXD

R0 AND C0 COMBINATIONS:

• 1.0 kΩ and 1.0 nF

• 660 Ω and 6.8 nF

• 500 Ω and 10 nF

C0

Figure 27. Test circuit for LIN timing measurements

TXD

t

BIT

t

(MAX)

t

(MIN)

BUS_REC

BUS_DOM

V_{LIN_REC}

t

- MAX

t

- MIN

REC

DOM

74.4% V

60.0% V

SUP

t

- MIN

DOM

LIN

58.1% V

40.0% V

58.1% V

40.0% V

SUP

28.4% V

SUP

28.4% V

SUP

42.2% V

SUP

t

- MIN

REC

t

- MAX

t

(MIN)

BUS_DOM

DOM

t

(MAX)

BUS_REC

RXD

t

RREC

RDOM

Figure 28. LIN timing measurements for normal slew rate

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TXD

t

BIT

t

(MAX)

t

(MIN)

BUS_REC

BUS_DOM

V_{LIN_REC}

t

- MAX

t

- MIN

REC

DOM

77.8% V

60.0% V

SUP

t

- MIN

DOM

LIN

61.6% V

40.0% V

61.6% V

40.0% V

SUP

25.1% V

SUP

25.1% V

SUP

38.9% V

SUP

t

- MIN

REC

t

- MAX

t

(MIN)

BUS_DOM

DOM

t

(MAX)

BUS_REC

RXD

t

RREC

RDOM

Figure 29. LIN timing measurements for slow slew rate

V_{LIN_REC}

V

BUSrec

V

SUP

LIN BUS SIGNAL

V

BUSdom

RXD

t

RX_PDF

t

RX_PDR

Figure 30. LIN receiver timing

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V

LIN_REC

LIN

0.4 V

SUP

DOMINANT LEVEL

VDD

t

WL

t

WAKE

PROP

Figure 31. LIN wake-up sleep mode timing

V

LIN_REC

LIN

0.4 V

SUP

DOMINANT LEVEL

IRQ

t

WL

t

WAKE

PROP

Figure 32. LIN wake-up stop mode timing

V

SUP

V

DD

RST

t

NRTOUT

t

RST

Figure 33. Power on reset and normal request timeout timing

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67

t

PSCLK

CS

t

WSCLKH

LEAD

t

LAG

SCLK

t

WSCLKL

t

SIH

SISU

MOSI

MISO

UNDEFINED

D0

DON’T CARE

D7

DON’T CARE

t

VALID

t

SODIS

t

SOEN

D0

D7

DON’T CARE

Figure 34. SPI timing characteristics

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12 Functional description

12.1 Introduction

The 33910 is designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For

automotive body electronics, the 33910 is well suited to perform keypad applications via the LIN bus. Two power switches are provided

on the device configured as high-side outputs. Other ports are also provided, which include a wake-up capable pin and a Hall Sensor port

supply. An internal voltage regulator provides power to a MCU device. Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device to be compatible with 3-wire bus systems, where one wire is used for

communication, one for battery, and one for ground.

12.2 Functional pin description

See Table 1, 33910 simplified application diagram, for a graphic representation of the various pins referred to in the following paragraphs.

Also, see the 33910 pin connections for a description of the pin locations in the package.

12.2.1 Receiver output (RXD)

The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD low when LIN

bus is dominant, RXD high when LIN bus is recessive.

12.2.2 Transmitter input (TXD)

The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD

is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating.

12.2.3 LIN bus (LIN)

The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN

bus specification 2.0. The LIN interface is only active during Normal and Normal Request modes.

12.2.4 Serial data clock (SCLK)

The SCLK pin is the SPI clock input pin. MISO data changes on the negative transition of the SCLK. MOSI is sampled on the positive

edge of the SCLK.

12.2.5 Master out slave in (MOSI)

The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the positive edge of SCLK.

12.2.6 Master in slave out (MISO)

The MISO pin sends data to an SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this

output pin changes on the negative edge of the SCLK. When CS is High, this pin remains in high-impedance state.

12.2.7 Chip select (CS)

CS is a active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in the

same SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched.

A valid transmission must consist of 8 bits only. While in STOP mode a low-to-high level transition on this pin generates a wake-up

condition for the 33910.

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12.2.8 Analog multiplexer (ADOUT0)

The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer,

including the L1 input voltage and the internal junction temperature.

12.2.9 PWM input control (PWMIN)

This digital input can control the high-sides in Normal Request and Normal mode. To enable PWM control, the MCU must perform a write

operation to the high-side control register (HSCR). This pin has an internal 20 μA current pull-up.

12.2.10Reset (RST)

This bidirectional pin is used to reset the MCU in case the 33910 detects a reset condition, or to inform the 33910 the MCU has just been

reset. After release of the RST pin Normal Request mode is entered. The RST pin is an active low filtered input and output formed by a

weak pull-up and a switchable pull-down structure which allows this pin to be shorted either to V_DDor to GND during software development

without the risk of destroying the driver.

12.2.11Interrupt (IRQ)

The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request mode or to signal a wake-

up from Stop mode. This active low output transitions to high, only after the interrupt is acknowledged by a SPI read of the respective

status bits.

12.2.12Watchdog configuration (WDCONF)

The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window

watchdog period. When connected directly to ground, the watchdog is disabled. When this pin is left open, the watchdog period is fixed

to its lower precision internal default value (150 ms typical).

12.2.13Ground connection (AGND, PGND, LGND)

The AGND, PGND and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator.

The PGND and LGND pins are used for high current load return as in the LIN interface pin.

Note: PGND, AGND and LGND pins must be connected together.

12.2.14Digital/analog (L1)

The L1 pin is a multi purpose input. It can be used as a digital input, which can be sampled by reading the SPI and used for wake-up when

33910 is in Low Power mode or used as analog inputs for the analog multiplexer. When used to sense voltage outside the module, a

33kohm series resistor must be used on each input.

When used as a wake-up input L1 can be configured to operate in Cyclic-sense mode. In this mode, one of the high-side switches is

configured to be periodically turned on and sample the wake-up input. If a state change is detected between two cycles a wake-up is

initiated. The 33910 can also wake-up from Stop or Sleep by a simple state change on L1. When used as analog input, the voltage present

on the L1 pins is scaled down by an selectable internal voltage divider and can be routed to the ADOUT0 output through the analog

multiplexer.

Note: If L1 input is selected in the analog multiplexer, it is disabled as digital input and remains disabled in Low-power mode. No wake-

up feature is available in this condition.

When the L1 input is not selected in the analog multiplexer, the voltage divider is disconnected from this input.

12.2.15High-side outputs (HS1 and HS2)

These high-side switches are able to drive loads such as relays or lamps. Their structure is connected to the VS2 supply pin. The pins

are short-circuit protected and also protected against overheating. HS1and HS2 are controlled by SPI and can respond to a signal applied

to the PWMIN input pin. The HS1 and HS2 outputs can also be used during Low-power mode for the cyclic-sense of the WAKE input.

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NXP Semiconductors

12.2.16Power supply (VS1 and VS2)

Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection

and negative transient voltages, with external components. These pins sustain standard automotive voltage conditions such as load dump

at 40 V. The high-side switches (HS1 and HS2) are supplied by the VS2 pin, all other internal blocks are supplied by VS1 pin.

12.2.17Voltage sense pin (VSENSE)

This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input

is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery

voltage. The ESD structure on this pin allows for excursion up to +40 V, and down to -27 V, allowing this pin to be connected directly to

the battery line. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

12.2.18Hall sensor switchable supply pin (HVDD)

This pin provides a switchable supply for external hall sensors. While in Normal mode, this current limited output can be controlled through

the SPI. The HVDD pin needs to be connected to an external capacitor to stabilize the regulated output voltage.

12.2.19+5.0 V main regulator output (VDD)

An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply a

microcontroller. The pin is current limited against shorts to GND and overtemperature protected. During Stop mode the voltage regulator

does not operate with its full drive capabilities and the output current is limited. During Sleep mode the regulator output is completely shut

down.

12.3 Functional internal block description

MC33910 - Functional Block Diagram

Integrated Supply

Hall Sensor Supply

Voltage Regulator

HVDD

VDD

Analog Circuitry

Window Watchdog

Wake-Up

High Side Drivers

HS1 - HS2

Digital / Analog Input

Voltage & Temperature Sense

LIN Physical Layer

Interface

MCU Interface and Output Control

SPI Interface

Reset & IRQ Logic

HS - PWM Control

LIN Interface / Control

Analog Output 0

Integrated Supply

Analog Circuitry

MCU Interface and Output Control

Drivers

Figure 35. Functional internal block diagram

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12.3.1 Analog circuitry

The 33910 is designed to operate under automotive operating conditions. A fully configurable window watchdog circuit resets the

connected MCU in case of an overflow. Two Low-power modes are available with several different wake-up sources to reactivate the

device. One analog / digital input can be sensed or used as the wake-up source. The device is capable of sensing the supply voltage

(VSENSE) and the internal chip temperature (CTEMP).

12.3.2 High-side drivers

Two current and temperature protected High-side drivers with PWM capability are provided to drive small loads such as Status LED’s or

small lamps. Both Drivers can be configured for periodic sense during Low-power modes.

12.3.3 MCU interface

The 33910 is providing its control and status information through a standard 8-bit SPI interface. Critical system events such as Low- or

High-voltage/Temperature conditions as well as overcurrent conditions in any of the driver stages can be reported to the connected MCU

via IRQ or RST. The high-side driver outputs can be controlled via the SPI register as well as the PWMIN input. The integrated LIN physical

layer interface can be configured via SPI register and its communication is driven through the RXD and TXD device pins. All internal

analog sources are multiplexed to the ADOUT0 pin.

12.3.4 Voltage regulator outputs

Two independent voltage regulators are implemented on the 33910. The VDD main regulator output is designed to supply a MCU with a

precise 5.0 V. The switchable HVDD output is dedicated to supply small peripherals as hall sensors.

12.3.5 LIN physical layer interface

The 33910 provides a LIN 2.0 compatible LIN physical layer interface with selectable slew rate and various diagnostic features.

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NXP Semiconductors

13 Functional device operations

13.1 Operational modes

13.1.1 introduction

The 33910 offers three main operating modes: Normal (Run), Stop, and Sleep (Low Power). In Normal mode the device is active and is

operating under normal application conditions. The Stop and Sleep modes are Low-power modes with wake-up capabilities. In Stop mode

the voltage regulator still supplies the MCU with V_DD(limited current capability) and in Sleep mode the voltage regulator is turned off

(V_DD= 0 V).

Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset and the voltage regulator is

turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the mode control register (MCR). Figure 36

describes how transitions are done between the different operating modes and Table 35, gives an overview of the Operating mode.

13.1.2 Reset mode

The 33910 enters the Reset mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, the 33910

enters the Normal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (V_DDlow,

watchdog trigger fail, after a wake-up from Sleep mode, Normal Request mode timeout occurs).

13.1.3 Normal request mode

This is a temporary mode automatically accessed by the device after the Reset mode or after a wake-up from Stop mode. In Normal

Request mode, the VDD regulator is ON, the Reset pin is high and the LIN is operating in Rx Only mode.

As soon as the device enters the Normal Request mode an internal timer is started for 150 ms (typical value). During these 150 ms, the

MCU must configure the timing control register (TIMCR) and the MCR with MOD2 and MOD1 bits ste = 0 to enter in Normal mode. If

within the 150 ms timeout the MCU does not command the 33910 to Normal mode, it enters in Reset mode. If the WDCONF pin is

grounded in order to disable the watchdog function, the 33910 goes directly in Normal mode after the Reset mode. If the WDCONF pin is

open, the 33910 stays typically for 150 ms in Normal Request before entering in Normal mode.

13.1.4 Normal mode

In Normal mode, all 33910 functions are active and can be controlled by the SPI and the PWMIN pin. The VDD regulator is ON and delivers

its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog function is

enabled. The wake-up input (L1) can be read as a digital input or have its voltage routed through the analog-multiplexer.

The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0. The LIN bus can transmit and receive

information. The high-side switches are active and have PWM capability according to the SPI configuration. The interrupts are generated

to report failures 5 for V_SUPover/undervoltage, thermal shutdown, or thermal shutdown prewarning on the main regulator.

13.1.5 Sleep mode

The Sleep mode is a Low-power mode. From Normal mode, the device enters the Sleep mode by sending one SPI command through the

MCR. All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up input with or without cyclic sense,

forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. The internal Low-power oscillator may be active if the IC is

configured for cyclic-sense. In this condition, one of the high-side switches is turned on periodically and the wake-up inputs are sampled.

Wake-up from Sleep mode is similar to a power-up. The device goes in Reset mode except the SPI reports the wake-up source and the

BATFAIL flag is not set.

13.1.6 Stop mode

The Stop mode is the second Low-power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The

application MCU is always supplied while the 33910 is operating in Stop mode. The device can enter in Stop mode only by sending the

SPI command. When the application is in this mode, it can wake-up from the 33910 side (for example: cyclic sense, force wake-up, LIN

bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode transitions the 33910 to Normal Request mode and

generates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin.

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Normal Request Timeout Expired (t

)

NRTOUT

V

LOW

DD

V

HIGH AND

DD

Power Up

RESET DELAY (t_RST) EXPIRED

POWER

DOWN

NORMAL

REQUEST

RESET

V

LOW

DD

NORMAL

WD FAILED

V

LOW (>t ) EXPIRED

NRTOUT

DD

AND VSUV = 0

SLEEP COMMAND

WAKE-UP (RESET)

STOP

SLEEP

V

LOW

DD

Legend

WD: Watchdog

WD Disabled: Watchdog disabled (WDCONF pin connected to GND)

WD Trigger: Watchdog is triggered by SPI command

WD Failed: No watchdog trigger or trigger occurs in closed window

Stop Command: Stop command sent via the SPI

Sleep Command: Sleep command sent via the SPI

Wake-up from Stop mode: L1 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.

Wake-up from Sleep mode: L1 state change, LIN bus wake-up, Periodic wake-up.

Figure 36. Operating modes and transitions

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Table 35. Operating modes overview

Function

VDD

Reset mode Normal request mode Normal mode

Stop mode

Sleep mode

-

full

-

full

stop

-

SPI⁽¹²¹⁾

HVDD

SPI

-

SPI/PWM⁽¹²²⁾

Note ⁽¹²³⁾

-

Note ⁽¹²⁴⁾

HSx

Analog Mux

L1

-

SPI/PWM

SPI

-

SPI

Input

-

Input

Wake-up

LIN

-

Rx-Only

full/Rx-Only Rx-Only/Wake-up

Wake-up

On⁽⁶⁴⁾/Off

-

Watchdog

VSENSE

-

150 ms (typ.) timeout

On

-

On

VDD

Notes

121. Operation can be enabled/controlled by the SPI.

122. Operation can be controlled by the PWMIN input.

123. HSx switches can be configured for cyclic sense operation in Stop mode.

124. HSx switches can be configured for cyclic sense operation in Sleep mode.

125. Windowing operation when enabled by an external resistor.

13.1.7 Interrupts

Interrupts are used to signal a microcontroller a peripheral needs to be serviced. The interrupts which can be generated change according

to the Operating mode. While in Normal and Normal Request modes the 33910 signals through interrupts special conditions which may

require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the interrupt source register

(ISR).

While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts, wake-up is performed by powering-

up the MCU. In Normal and Normal Request mode the wake-up source can be read by SPI. The interrupts are signaled to the MCU by a

low logic level of the IRQ pin, which remains low until the interrupt is acknowledged by a SPI read. The IRQ pin is then driven high.

Interrupts are only asserted while in Normal-, Normal Request and Stop mode. Interrupts are not generated while the RST pin is low. The

following is a list of the interrupt sources in Normal and Normal Request modes. Some of those can be masked by writing to the SPI-

interrupt mask register (IMR).

13.1.7.1 Low voltage interrupt

Signals when the supply line (VS1) voltage drops below the VSUV threshold (V_SUV).

13.1.7.2 High voltage interrupt

Signals when the supply line (VS1) voltage increases above the VSOV threshold (V_SOV).

13.1.7.3 Overtemperature prewarning

Signals when the 33910 temperature has reached the pre-shutdown warning threshold. It is used to warn the MCU an overtemperature

shutdown in the main 5.0 V regulator is imminent.

13.1.7.4 LIN overcurrent shutdown/overtemperature shutdown/TXD stuck at dominant/

RXD short-circuit

These signal faulty conditions in the LIN interface (except the LIN overcurrent) which led to disable the LIN driver. In order to restart

operation, the fault must be removed and must be acknowledged by reading the SPI. The LINOC bit functionality in the LIN status register

(LINSR) is to indicate an LIN overcurrent occurred and the driver stays enabled.

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13.1.7.5 High-side overtemperature shutdown

Signals a shutdown of the high-side outputs.

13.1.8 Reset

To reset an MCU, the 33910 drives the RST pin low for the time the reset condition lasts. After the reset source has been removed the

state machine drives the RST output low for at least 1.0 ms typical value before driving it high. In the 33910 four main reset sources exist:

13.1.8.1 5.0 V regulator low-voltage-reset (V

)

RSTTH

The 5.0 V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects the voltage at the VDD pin

has dropped below the reset threshold V_RSTTHthe 33910 issues a reset. In case of overtemperature, the voltage regulator is disabled and

the voltage monitoring issues a VDDOT Flag independently of the V_DDvoltage.

13.1.8.2 Window watchdog overflow

If the watchdog counter is not properly serviced while its window is open, the 33910 detects a MCU software runaway and resets the

microcontroller.

13.1.8.3 Wake-up from sleep mode

During Sleep mode, the 5.0 V regulator is not active, hence all wake-up requests from Sleep mode require a power-up/reset sequence.

13.1.8.4 External reset

The 33910 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low.

The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality

is also active in Stop mode. After the RST pin is released, there is no extra t_RSTto be considered.

13.1.9 Wake-up capabilities

Once entered in to one of the Low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation.

In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode the wake-up is performed by activating the 5.0 V

regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers. There is no

specific SPI register bit to signal a CS wake-up or external reset. If necessary this condition is detected by excluding all other possible

wake-up sources.

13.1.9.1 Wake-up from wake-up input (L1) with cyclic sense disabled

The wake-up line is dedicated to sense state changes of external switches and wake-up the MCU (in Sleep or Stop mode). In order to

select and activate direct wake-up from the L1 input, the wake-up control register (WUCR) must be configured with L1WE input enabled.

The wake-up input state is read through the wake-up status register (WUSR). L1 input is also used to perform cyclic-sense wake-up.

Note: Selecting the L1 input in the analog multiplexer before entering Low-power mode disables the wake-up capability of the L1 input.

13.1.9.2 Wake-up from wake-up input (L1) with cyclic sense timer enabled

The SBCLIN can wake-up at the end of a cyclic sense period if on the wake-up input lines (L1) a state change occurs. The HSx switch is

activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wake-up are exclusive. If cyclic sense is enabled, the

force wake-up can not be enabled. To select and activate the cyclic sense wake-up from the L1 input, prior to entering in low power modes

(Stop or Sleep modes), the following SPI set-up has to be performed:

•

In WUCR: select the L1 input to WU-enable.

In HSCR: enable HSx.

In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits.

Perform Goto Sleep/Stop command.

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13.1.9.3 Forced wake-up

The 33910 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and forced wake-up are

exclusive. If forced wake-up is enabled, the cyclic sense can not be enabled. To determine the wake-up period, the following SPI set-up

has to be sent before entering in Low-power modes:

•

In TIMCR: select the CS/WD bit and determine the Low-power mode period with CYSTx bits.

In HSCR: the HSx bit must be disabled.

13.1.9.4 CS wake-up

While in Stop mode, a rising edge on the CS causes a wake-up. The CS wake-up does not generate an interrupt and is not reported on

the SPI.

13.1.9.5 LIN wake-up

While in the Low-power modes the 33910 monitors the activity on the LIN bus. A dominant pulse larger than t_PROPWLfollowed by a

dominant to recessive transition causes a LIN wake-up. This behavior protects the system from a short-to-ground bus condition.

13.1.9.6 RST wake-up

While in Stop mode, the 33910 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, the 33910

changes to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an

interrupt and is not reported via the SPI.

From Stop mode, the following wake-up events can be configured:

•

Wake-up from L1 input without cyclic sense

Cyclic sense wake-up inputs

Force wake-up

CS wake-up

LIN wake-up

RST wake-up

From Sleep mode, the following wake-up events can be configured:

•

Wake-up from L1 input without cyclic sense

Cyclic sense wake-up inputs

Force wake-up

LIN wake-up

13.1.10Window watchdog

The 33910 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external

resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears

are performed by writing through the SPI in the MOD bits of the MCR.

During the first half of the SPI timeout watchdog clears are not allowed; but after the first half of the PSPI-timeout window the clear

operation opens. If a clear operation is performed outside the window, the 33910 resets the MCU, in the same way as when the watchdog

overflows.

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WINDOW CLOSED

NO WATCHDOG CLEAR

ALLOWED

WINDOW OPEN

FOR WATCHDOG

CLEAR

WD TIMING X 50%

WD PERIOD (t

)

PWD

WD TIMING SELECTED BY REGISTER

ON WDCONF PIN

Figure 37. Window watchdog operation

To disable the watchdog function in Normal mode, the user must connect the WDCONF pin to ground. This measure effectively disables

Normal Request mode. The WDOFF bit in the WDSR is set. This condition is only detected during Reset mode. If neither a resistor nor a

connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms (typ.) and signals the faulty

condition through the WDSR.

The watchdog timebase can be further divided by a prescaler which can be configured by the TIMCR. During Normal Request mode, the

window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. In case of a timeout, the 33910

enters into Reset mode, resetting the microcontroller before entering again into Normal Request mode.

13.1.11High-side output pins HS1 and HS2

These outputs are two high-side drivers intended to drive small resistive loads or LEDs incorporating the following features:

•

PWM capability (software maskable)

Open load detection

Current limitation

Overtemperature shutdown (with maskable interrupt)

High-voltage shutdown (software maskable)

Cyclic sense

The high-side switches are controlled by the bits HS1:2 in the High-side Control Register (HSCR).

13.1.11.1 PWM capability (direct access)

Each high-side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in

the High-side Control Register (HSCR), the HS1 driver is turned on if the PWMIN pin is high and turned off if the PWMIN pin is low. This

applies to HS2 configuring HS2 and PWMHS2 bits.

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Interrupt

Control

Module

V_DD

HVSE

V_DD

PWMIN

PWMHSx

VS2

MOD1:2

HSx

HIgh-side - Driver

charge pump

open load detection

current limitation

on/off

Control

HSxOP

HSxCL

Status

overtemperture shutdown (interrupt maskable)

High-voltage shutdown (maskable)

HSx

Wake-up

Module

Figure 38. High-side drivers HS1 and HS2

13.1.11.2 Open load detection

Each high-side driver signals an open load condition if the current through the high-side is below the open load current threshold. The

open load condition is indicated with the bits HS1OP and HS2OP in the High-side Status Register (HSSR).

13.1.11.3 Current limitation

Each high-side driver has an output current limitation. In combination with the overtemperature shutdown the high-side drivers are

protected against overcurrent and short-circuit failures. When the driver operates in the current limitation area, it is indicated with the bits

HS1CL and HS2CL in the HSSR.

Note: If the driver is operating in current limitation mode, excessive power might be dissipated.

13.1.11.4 Overtemperature protection (HS interrupt)

Both high-side drivers are protected against overtemperature. If an overtemperature condition occurs, both high-side drivers are shut

down and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source Register

(ISR).

A thermal shutdown of the high-side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. If the bit HSM is set in the

Interrupt Mask Register (IMR), then an interrupt (IRQ) is generated. A write to the High-side Control Register (HSCR), when the

overtemperature condition is gone, re-enables the high-side drivers.

13.1.11.5 High-voltage shutdown

In case of a high-voltage condition and if the high-voltage shutdown is enabled (bit HVSE in the Mode Control Register (MCR) is set) both

high-side drivers are shutdown. A write to the High-side Control Register (HSCR), when the high-voltage condition is gone, re-enables

the high-side drivers.

13.1.11.6 Sleep and stop mode

The high-side driver can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 35, Operating modes overview.

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13.1.12LIN physical layer

The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to

meet the LIN physical layer specification and has the following features:

•

LIN physical layer 2.0 compliant

Slew rate selection

Overcurrent shutdown

Overtemperature shutdown

LIN pull-up disable in Stop and Sleep modes

Advanced diagnostics

LIN dominant voltage level selection

The LIN driver is a low-side MOSFET with overcurrent and thermal shutdown. An internal pull-up resistor with a serial diode structure is

integrated, so no external pull-up components are required for the application in a Slave mode. The fall time from dominant to recessive

and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed.

13.1.12.1 LIN pin

The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication.

INTERRUPT

CONTROL

WAKE-UP

MODULE

High-voltage

Shutdown

High-side

Interrupt

LIN

Wake-up

MOD1:2

LSR0:1

LINPE

VS1

LIN – DRIVER

LDVS

Slope and Slew Rate Control

Overcurrent Shutdown (interrupt maskable)

Overtemperature Shutdown (interrupt maskable)

RXONLY

RXSHORT

TXDOM

LINOT

LINOC

30K

LIN

TXD

RXD

SLOPE

CONTROL

LGND

WAKE-UP

FILTER

RECEIVER

Figure 39. LIN interface

13.1.12.2 Slew rate selection

The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew

rate can be adapted with the bits LSR1:0 in the LIN control register (LINCR). The initial slew rate is optimized for 20 kBit/s.

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13.1.12.3 LIN pull-up disable in stop and sleep mode

To improve performance and for safe behavior in case of LIN bus short to ground or LIN bus leakage during Low-power mode the internal

pull-up resistor on the LIN pin can be disconnected by clearing the LINPE bit in the MCR. The bit LINPE also changes the bus wake-up

threshold (V_BUSWU). In case of a LIN bus short to GND, this feature reduces the current consumption in Stop and Sleep modes.

13.1.12.4 Overcurrent shutdown (LIN interrupt)

The output low-side FET is protected against overcurrent conditions. In case of an overcurrent condition (e.g. LIN bus short to V_BAT), the

transmitter does not shut down. The bit LINOC in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register

(IMR) an Interrupt IRQ is generated.

13.1.12.5 Overtemperature shutdown (LIN interrupt)

The output low-side FET is protected against overtemperature conditions. In case of an overtemperature condition, the transmitter is shut

down and the bit LINOT in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register (IMR) an Interrupt IRQ

is generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. A read of the LIN status register

(LINSR) with the TXD pin re-enables the transmitter.

13.1.12.6 RXD short-circuit detection (LIN interrupt)

The LIN transceiver has a short-circuit detection for the RXD output pin. In case of an short-circuit condition, either 5.0 V or ground, the

bit RXSHORT in the LIN status register (LINSR) is set and the transmitter is shutdown. If the bit LINM is set in the interrupt mask register

(IMR) an interrupt IRQ is generated. The transmitter is automatically re-enabled once the condition is gone (transition on RXD) and TXD

is high. A read of the LIN status register (LINSR) without the RXD pin short-circuit condition clears the bit RXSHORT.

13.1.12.7 TXD Dominant Detection (LIN interrupt)

The LIN transceiver monitors the TXD input pin to detect stuck in dominant (0 V) condition. In case of a stuck condition (TXD pin 0V for

more than 1 second (typ.)) the transmitter is shut down and the bit TXDOM in the LIN status register (LINSR) is set. If the bit LINM is set

in the interrupt mask register (IMR) an interrupt IRQ is generated. The transmitter is automatically re-enabled once TXD is high. A read

of the LIN status register (LINSR) with the TXD pin is high clears the bit TXDOM.

13.1.12.8 LIN dominant voltage level selection

The LIN dominant voltage level can be selected by the bit LDVS in the LIN control register (LINCR).

13.1.12.9 LIN receiver operation only

While in Normal mode the activation of the RXONLY bit disables the LIN TX driver. In the case of a LIN error condition this bit is

automatically set. If a Low-power mode is selected with this bit set, the LIN wake-up functionality is disabled, then, in Stop mode, the RXD

pin reflects the state of the LIN bus.

13.1.12.10Stop mode and wake-up feature

During Stop mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Stop mode sequence

the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in the recessive state. The receiver

is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than t_PROPWLfollowed by a rising edge

generates a wake-up interrupt and is reported in the ISR. Also see Figure 32.

13.1.12.11Sleep mode and wake-up feature

During Sleep mode operation the transmitter of the physical layer is disabled. If the bit LIN-PU was set in the Sleep mode sequence, the

internal pull-up resistor is disconnected from V_SUPand a small current source keeps the LIN pin in recessive state. The receiver is still

active to be able to detect wake-up events on the LIN bus line. A dominant level longer than t_PROPWLfollowed by a rising edge generates

a system wake-up (Reset) and is reported in the ISR. Also see Figure 31.

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13.2 Logic commands and registers

13.2.1 SPI and configuration

The SPI creates the communication link between a microcontroller (master) and the 33910. The interface consists of four pins (see

Figure 40):

•

CS—Chip Select

MOSI—Master-Out Slave-In

MISO—Master-In Slave-Out

SCLK—Serial Clock

A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0)

and the slave replies with three system status bits and one not defined bit (VMS,LINS,HSS,n.d.) + 4 bits of status information (S3:S0).

CS

Register Write Data

MOSI

MISO

A3

A2

A1

A0

C3

C2

C1

S1

C0

S0

Register Read Data

VMS LINS HSS S3 S2

–

SCLK

Read Data Latch

Write Data Latch

Rising Edge of SCLK

Change MISO/MISO Output

Falling Edge of SCLK

Sample MISO/MISO Input

Figure 40. SPI protocol

During the inactive phase of the CS (HIGH), the new data transfer is prepared. The falling edge of the CS indicates the start of a new data

transfer and puts the MISO in the low-impedance state and latches the analog status data (Register read data). With the rising edge of

the SPI clock (SCLK), the data is moved to MISO/MOSI pins. With the falling edge of the SPI clock (SCLK) the data is sampled by the

receiver. The data transfer is only valid if exactly eight sample clock edges are present during the active (low) phase of CS.

The rising edge of the chip select CS indicates the end of the transfer and latches the write data (MOSI) into the register. The CS high

forces MISO to the high-impedance state. Register reset values are described along with the reset condition. Reset condition is the

condition causing the bit to be set to its reset value. The main reset conditions are:

- Power-On Reset (POR): level at which the logic is reset and BATFAIL flag sets.

- Reset mode

- Reset done by the RST pin (ext_reset)

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13.3 SPI register overview

.

Table 36. System Status Register

BIT

Adress(A3:A0)

Register Name / Read/Write Information

7

6

5

4

$0 - $F

SYSSR - System Status Register

R

VMS

LINS

HSS

-

Table 9 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.

Table 37. SPI register overview

BIT

Adress(A3:A0)

Register Name / Read/Write Information

3

2

1

0

MCR - Mode Control Register

VSR - Voltage Status Register

WUCR - Wake-up Control Register

WUSR - Wake-up Status Register

LINCR - LIN Control Register

LINSR - LIN Status Register

W

R

HVSE

VSOV

-

LINPE

VSUV

-

MOD2

VDDOT

-

MOD1

BATFAIL

L1WE

L1

$0

$1

$2

$3

$4

$5

$6

$7

R

W

R

-

R

-

L1

W

R

LDVS

RXSHORT

PWMHS2

HS2OP

RXONLY

TXDOM

PWMHS1

HS2CL

WD2

LSR1

LINOT

HS2

LSR0

LINOC

HS1

LINSR - LIN Status Register

R

HSCR - High-side Control Register

HSSR - High-side Status Register

W

R

HS1OP

WD1

CYST1

WDOFF

MX1

HS1CL

WD0

R

TIMCR - Timing Control Register

W

CS/WD

$A

CYST2

WDERR

MX2

CYST0

WDWO

MX0

WDSR - Watchdog Status Register

AMUXCR - Analog Multiplexer Control Register

CFR - Configuration Register

R

WDTO

L1DS

HVDD

HSM

$B

$C

$D

W

R

CYSX8

-

IMR - Interrupt Mask Register

LINM

ISR1

VMM

$E

$F

ISR - Interrupt Source Register

ISR3

ISR2

ISR0

ISR - Interrupt Source Register

R

ISR3

ISR2

ISR0

Note: Address $8 and $9 are reserved and must not be used.

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13.3.1 Register definitions

13.3.1.1 System status register - SYSSR

The system status register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It

summarizes the status of the voltage status register (VSR), LIN status register (LINSR) and the HSSR.

Table 38. System Status Register

S7

S6

S5

S4

Read

VMS

LINS

HSS

–.

13.3.1.1.1 VMS - voltage monitor status

This read-only bit indicates one or more bits in the voltage status register (VSR) are set.

1 = Voltage Monitor bit set

0 = None

BATFAIL

VDDOT

VMS

VSUV

VSOV

Figure 41. Voltage monitor status

13.3.1.1.2 LINS - LIN status

This read-only bit indicates one or more bits in the LIN status register (LINSR) are set.

1 = LIN Status bit set

0 = None

LINOC

LINOT

LINS

TXDOM

RXSHORT

Figure 42. LIN status

13.3.1.1.3 HSS - high-side switch status

This read-only bit indicates one or more bits in the HSSR are set.

1 = High-side Status bit set

0 = None

HS1CL

HS1OP

HSS

HS2CL

HS2OP

Figure 43. High-side status

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13.3.1.2 Mode control register - MCR

The MCR allows to switch between the operation modes and to configure the 33910. Writing the MCR returns the voltage status register

(VSR).

Table 39. Mode control register - $0

C3

C2

C1

C0

Write

HVSE

1

LINPE

1

MOD2

MOD1

Reset Value

Reset Condition

-

POR

13.3.1.2.1 HVSE - high-voltage shutdown enable

This write-only bit enables/disables automatic shutdown of the high-side and the low-side drivers during a high-voltage VSOV condition.

1 = automatic shutdown enabled

0 = automatic shutdown disabled

13.3.1.2.2 LINPE - LIN pull-up enable

This write-only bit enables/disables the 30 kΩ LIN pull-up resistor in Stop and Sleep modes. This bit also controls the LIN bus wake-up

threshold.

1 = LIN pull-up resistor enabled

0 = LIN pull-up resistor disabled

13.3.1.2.3 MOD2, MOD1 - mode control bits

These write-only bits select the Operating mode and allow to clear the watchdog in accordance with Table 38 Mode Control Bits.

Table 40. Mode control bits

MOD2

MOD1

Description

0

1

0

1

0

1

Normal Mode

Stop Mode

Sleep Mode

Normal Mode + watchdog Clear

13.3.1.3 Voltage status register - VSR

Returns the status of the several voltage monitors. This register is also returned when writing to the MCR.

Table 41. Voltage status register - $0/$1

S3

S2

S1

S0

Read

VSOV

VSUV

VDDOT

BATFAIL

13.3.1.3.1 VSOV - V

overvoltage

SUP

This read-only bit indicates an overvoltage condition on the VS1 pin.

1 = Overvoltage condition.

0 = Normal condition.

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13.3.1.3.2 VSUV - V

undervoltage

SUP

This read-only bit indicates an undervoltage condition on the VS1 pin.

1 = Undervoltage condition.

0 = Normal condition.

13.3.1.3.3 VDDOT - main voltage regulator overtemperature warning

This read-only bit indicates the main voltage regulator temperature reached the overtemperature prewarning threshold.

1 = Overtemperature prewarning

0 = Normal

13.3.1.3.4 BATFAIL - battery fail flag

This read-only bit is set during power-up and indicates the 33910 had a power on reset (POR). Any access to the MCR or voltage status

register (VSR) clears the BATFAIL flag.

1 = POR Reset has occurred

0 = POR Reset has not occurred

13.3.1.4 Wake-up control register - WUCR

This register is used to control the digital wake-up input. Writing the wake-up control register (WUCR) returns the wake-up status register

(WUSR).

Table 42. Wake-up Control Register - $2

C3

C2

C1

C0

Write

0

1

0

1

0

1

L1WE

1

Reset Value

Reset Condition

POR, Reset mode or ext_reset

13.3.1.4.1 L1WE - wake-up input enable

This write-only bit enables/disables the L1 input. In Stop and Sleep mode the L1WE bit activates the L1 input for wake-up. If the L1 input

is selected on the analog multiplexer, the L1WE is masked to 0.

1 = Wake-up Input enabled.

0 = Wake-up Input disabled.

13.3.1.5 Wake-up status register - WUSR

This register is used to monitor the digital wake-up inputs and also returned when writing to the wake-up control register (WUCR).

Table 43. Wake-up Status Register - $2/$3

S3

S2

S1

S0

Read

-

L1

13.3.1.5.1 L1 - wake-up input

This read-only bit indicates the status of the L1 input. If the L1 input is not enabled then the wake-up status returns 0. After a wake-up

form Stop or Sleep mode this bit also allows to verify the L1 input has caused the wake-up, by first reading the interrupt status register

(ISR) and then reading the wake-up status register (WUSR).

1 = L1 Wake-up.

0 = L1 Wake-up disabled or selected as analog input.

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13.3.1.6 LIN control register - LINCR

This register controls the LIN physical interface block. Writing the LIN control register (LINCR) returns the LIN status register (LINSR).

Table 44. LIN control register - $4

C3

C2

C1

C0

Write

LDVS

0

RXONLY

0

LSR1

0

LSR0

0

Reset Value

POR, Reset mode,

ext_reset or LIN

failure gone*

POR,Resetmode

or ext_reset

Reset Condition

POR

* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag resets automatically when the failure is gone.

13.3.1.6.1 LDVS - LIN dominant voltage select

This write-only bit controls the LIN Dominant voltage:

1 = LIN Dominant Voltage = V_{LIN_DOM_1}(1.7 V typ)

0 = LIN Dominant Voltage = V_{LIN_DOM_0}(1.1 V typ)

13.3.1.6.2 RXONLY - LIN receiver operation only

This write-only bit controls the behavior of the LIN transmitter. In Normal mode the activation of the RXONLY bit disables the LIN

transmitter. In case of a LIN error condition, this bit is automatically set. In Stop mode, this bit disables the LIN wake-up functionality and

the RXD pin reflects the state of the LIN bus.

1 = only LIN receiver active (Normal mode) or LIN wake-up disabled (Stop mode)

0 = LIN fully enabled

13.3.1.6.3 LSRx - LIN slew rate

This write-only bit controls the LIN driver slew rate in accordance with Table 45.

Table 45. LIN slew rate control

LSR1

LSR0

Description

0

1

0

1

0

1

Normal Slew Rate (up to 20 kb/s)

Slow Slew Rate (up to 10 kb/s)

Fast Slew Rate (up to 100 kb/s)

Reserved

13.3.1.7 LIN status register - LINSR

This register returns the status of the LIN physical interface block and is also returned when writing to the LIN control register (LINCR).

Table 46. LIN status register - $4/$5

S3

S2

S1

S0

Read

RXSHORT

TXDOM

LINOT

LINOC

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13.3.1.7.1 RXSHORT - RXD pin short-circuit

This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The short-circuit delay must be

8.0 µs worst case to be detected and to shutdown the driver. To clear this bit, it must be read after the condition is gone (transition detected

on RXD pin). The LIN driver is automatically re-enabled once the condition is gone.

1 = RXD short-circuit condition.

0 = None.

13.3.1.7.2 TXDOM - TXD permanent dominant

This read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LIN

transmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second typical value. To clear this bit,

it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes High.

1 = TXD stuck at dominant fault detected.

0 = None.

13.3.1.7.3 LINOT - LIN driver overtemperature shutdown

This read-only bit signals the LIN transceiver was shutdown due to overtemperature. The transmitter is automatically re-enabled after the

overtemperature condition is gone and TXD is high. The LINOT bit is cleared after SPI read once the condition is gone.

1 = LIN overtemperature shutdown

0 = None

13.3.1.7.4 LINOC - LIN driver overcurrent shutdown

This read-only bit signals an overcurrent condition occurred on the LIN pin. The LIN driver is not shutdown but an IRQ is generated. To

clear this bit, it must be read after the condition is gone.

1 = LIN overcurrent shutdown

0 = None

13.3.1.8 High-side control register - HSCR

This register controls the operation of the high-side drivers. Writing to this register returns the High-side Status Register (HSSR).

Table 47. High-side control register - $6

C3

C2

C1

C0

Write

PWMHS2 PWMHS1

HS2

0

HS1

0

Reset Value

0

POR, Reset mode, ext_reset, HSx

overtemp or (VSOV & HVSE)

Reset Condition

POR

13.3.1.8.1 PWMHSx - PWM input control enable

This write-only bit enables/disables the PWMIN input pin to control the high-side switch. The high-side switch must be enabled (HSx bit).

1 = PWMIN input controls HS1 output.

0 = HSx is controlled only by SPI.

13.3.1.8.2 HSx - high-side switch control

This write-only bit enables/disables the high-side switch.

1 = HSx switch on.

0 = HSx switch off.

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13.3.1.9 High-side status register - HSSR

This register returns the status of the high-side switch and is also returned when writing to the HSCR.

Table 48. High-side Status Register - $6/$7

S3

S2

S1

S0

Read

HS2OP

HS2CL

HS1OP

HS1CL

13.3.1.9.1 High-side thermal shutdown

A thermal shutdown of the high-side drivers is indicated by setting the HSxOP and HSxCL bits simultaneously.

13.3.1.9.2 HSxOP - high-side switch open load detection

This read-only bit signals the high-side switch is conducting current below a certain threshold indicating possible load disconnection.

1 = HSx Open Load detected (or thermal shutdown)

0 = Normal

13.3.1.9.3 HSxCL - high-side current limitation

This read-only bit indicates the high-side switch is operating in current Limitation mode.

1 = HSx in current limitation (or thermal shutdown)

0 = Normal

13.3.1.10 Timing control register - TIMCR

This register is a double purpose register which allows to configure the watchdog and the cyclic sense periods. Writing to the TIMCR also

returns the WDSR.

Table 49. Timing control register - $A

C3

C2

C1

C0

WD2

CYST2

0

WD1

CYST1

0

WD0

CYST0

0

Write

CS/WD

Reset Value

-

Reset Condition

POR

13.3.1.10.1 CS/WD - cyclic sense or watchdog prescaler select

This write-only bit selects which prescaler is being written to, the cyclic sense prescaler or the watchdog prescaler.

1 = Cyclic Sense Prescaler selected

0 = Watchdog Prescaler select

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13.3.1.10.2 WDx - watchdog prescaler

This write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 50.

This configuration is valid only if windowing watchdog is active.

Table 50. Watchdog prescaler

WD2

WD1

WD0

Prescaler Divider

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

6

8

10

12

14

13.3.1.10.3 CYSTx - cyclic sense period prescaler select

This write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the configuration register (CFR) (See

Configuration register - CFR on page 92). This option is only active if the high-side switch is enabled when entering in Stop or Sleep mode.

Otherwise a timed wake-up is performed after the period shown in Table 51.

Table 51. Cyclic sense interval

CYSX8 ⁽¹²⁶⁾CYST2

CYST1

CYST0

Interval

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Cyclic Sense

20 ms

40 ms

60 ms

80 ms

100 ms

120 ms

140 ms

160 ms

320 ms

480 ms

640 ms

800 ms

960 ms

1120 ms

Notes

126. bit CYSX8 is located in configuration register (CFR)

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13.3.1.11 Watchdog status register

This register returns the watchdog status information and is also returned when writing to the TIMCR.

Table 52. Watchdog status register - $A/$B

S3

S2

S1

S0

Read

WDTO

WDERR

WDOFF

WDWO

13.3.1.11.1 WDTO - watchdog timeout

This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the watchdog within the window

closed. Any access to this register or the TIMCR clears the WDTO bit.

1 = Last reset caused by watchdog timeout

0 = None

13.3.1.11.2 WDERR - watchdog error

This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision

timebase. The windowing function is disabled.

1 = WDCONF pin resistor missing

0 = WDCONF pin resistor not floating

13.3.1.11.3 WDOFF - watchdog off

This read-only bit signals the watchdog pin connected to GND and therefore disabled. If watchdog timeouts are disabled, the device

automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming the Flash memory.

1 = Watchdog is disabled

0 = Watchdog is enabled

13.3.1.11.4 WDWO - watchdog window open

This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case

WDERR is High.

1 = Watchdog window open

0 = Watchdog window closed

13.3.1.12 Analog multiplexer control register - MUXCR

This register controls the analog multiplexer and selects the divider ration for the L1 input divider.

Table 53. Analog multiplexer control register -$C

C3

C2

C1

C0

Write

L1DS

1

MX2

0

MX1

0

MX0

0

Reset Value

Reset Condition

POR

POR, Reset mode or ext_reset

13.3.1.12.1 L1DS - L1 analog input divider select

This write-only bit selects the resistor divider for the L1 analog input. Voltage is internally clamped to VDD.

0 = L1 Analog divider: 1

1 = L1 Analog divider: 3.6 (typ.)

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13.3.1.13 MXx - analog multiplexer input select

These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 54. When disabled or when in Stop

or Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption.

Table 54. Analog multiplexer channel select

MX2

MX1

MX0

Meaning

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Disabled

Reserved

Die Temperature Sensor

VSENSE input

L1 input

Reserved

13.3.1.14 Configuration register - CFR

This register controls the cyclic sense timing multiplier.

Table 55. Configuration Register - $D

C3

C2

C1

C0

Write

0

CYSX8

0

Reset Value

POR, Reset mode

or ext_reset

Reset Condition

POR

13.3.1.14.1 HVDD - hall sensor supply enable

This write-only bit enables/disables the state of the hall sensor supply.

1 = HVDD on

0 = HVDD off

13.3.1.14.2 CYSX8 - cyclic sense timing x eight

This write-only bit influences the Cyclic Sense period as shown in Table 51.

1 = Multiplier enabled

0 = None

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13.3.1.15 Interrupt mask register - IMR

This register allow to mask some of interrupt sources. The respective flags within the ISR continues to work, but does not generate

interrupts to the MCU. The 5.0 V Regulator overtemperature prewarning interrupt and undervoltage (VSUV) interrupts can not be masked

and always causes an interrupt. Writing to the interrupt mask register (IMR) returns the ISR.

Table 56. Interrupt mask register - $E

C3

C2

C1

C0

Write

HSM

1

-.

1

LINM

1

VMM

1

Reset Value

Reset Condition

POR

13.3.1.15.1 HSM - high-side interrupt mask

This write-only bit enables/disables interrupts generated in the high-side block.

1 = HS Interrupts Enabled

0 = HS Interrupts Disabled

13.3.1.15.2 LINM - LIN interrupts mask

This write-only bit enables/disables interrupts generated in the LIN block.

1 = LIN Interrupts Enabled

0 = LIN Interrupts Disabled

13.3.1.15.3 VMM - voltage monitor interrupt mask

This write-only bit enables/disables interrupts generated in the voltage monitor block. The only maskable interrupt in the voltage monitor

block is the V_SUPovervoltage interrupt.

1 = Interrupts Enabled

0 = Interrupts Disabled

13.3.1.16 Interrupt source register - ISR

This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges

the interrupt and leads IRQ pin to high, if there are no other pending interrupts. If there are pending interrupts, IRQ is driven high for 10 µs

and then be driven low again. This register is also returned when writing to the interrupt mask register (IMR).

Table 57. Interrupt source register - $E/$F

S3

S2

S1

S0

Read

ISR3

ISR2

ISR1

ISR0

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13.3.1.16.1 ISRx - interrupt source register

These read-only bits indicate the interrupt source are described in Table 58. If no interrupt is pending than all bits are 0. If more than one

interrupt is pending, the interrupt sources are handled sequentially multiplex.

Table 58. Interrupt sources

Interrupt source

ISR3 ISR2 ISR1 ISR0

Priority

none maskable

maskable

0

1

0

1

0

1

no interrupt

L1 wake-up from Stop mode

HS interrupt (Overtemperature)

Reserved

none

-

highest

LIN interrupt (RXSHORT, TXDOM, LIN OT, LIN

OC) or LIN wake-up

0

1

0

Voltage monitor interrupt (Low-voltage and VDD

overtemperature)

0

1

0

1

0

Voltage monitor interrupt (High-voltage)

Forced wake-up

-

lowest

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14 Typical applications

The 33910 can be configured in several applications. The figure below shows the 33910 in the typical slave node application.

V

BAT

D1

C2

C1

VDD

IRQ

Interrupt

Control Module

LVI, HVI, HTI, OCI

Voltage Regulator

5V Output Module

C5

C4

C3

AGND

HVDD

Hall Sensor Supply

VDD

Reset

Control Module

LVR, HVR, HTR, WD,

RST

IRQ

RST

Window

R1

Watchdog Module

PWMIN

TIMER

High Side Control

Module

HS1

HS2

MISO

MOSI

SCLK

CS

Chip Temp Sense Module

VBAT Sense Module

SPI

&

CONTROL

SPI

VSENSE

MCU

R2

L1

Analog Input Module

ADOUT0

A/D

Wake Up Module

Digital Input Module

RXD

TXD

LIN Physical Layer

SCI

A/D

LIN

C6

Typical Component Values:

C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 220 pF

R1 = 10 kΩ; R2 = 20 kΩ-200 kΩ

Recommended Configuration of the not Connected Pins (NC):

R7

Pin 15, 16, 17, 19, 20, 21, 22 = GND

Pin 11 = open (floating)

Pin 28 = this pin is not internally connected and may be used for PCB routing

optimization.

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95

15 Packaging

15.1 Package dimensions

Important For the most current revision of the package, visit www.nxp.com and select Documentation, then under Available

Documentation column select Packaging Information.

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16 Revision history

Revision

Date

5/2007

Description of changes

1.0

•

Initial Release

•

Several textual corrections

Page 11: “Analog Output offset Ratio” changed to “Analog Output offset” +/-22mV

Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5

Page 12: Common mode input impedance corrected to 75kΩ

Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release

2.0

9/2007

3.0

4.0

9/2007

2/2008

•

Revision number incremented at engineering request.

Changed Functional Block Diagram on page 24.

•

Datasheet updated according to the Pass1.2 silicon version electrical parameters

Add Maximum Rating on I_{BUS_NO_GND}parameter

Added L1, Temperature Sense Analog Output Voltage per characterization, Internal Chip Temperature Sense

Gain per characterization at three temperatures. See Figure 16, Temperature sense gain, VSENSE Input

Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization, and VSENSE Output Related Offset

per characterization parameters

•

Added Temperature sense gain section

5.0

11/2008

Minor corrections to ESD Capability, ⁽¹⁹⁾, Cyclic Sense ON Time from Stop and Sleep Mode, LIN bus pin

(LIN), Serial data clock pin (SCLK), Master out slave in pin (MOSI), Master in slave out pin (MISO), Digital/

analog pin (L1), Normal request mode, Sleep mode, LIN overtemperature shutdown/TXD stuck at dominant/

RXD short-circuit, Fault detection management conditions, Lin physical layer, LIN interface, Overtemperature

shutdown (LIN interrupt), LIN receiver operation only, SPI protocol, L1 - wake-up input 1, LIN control register

- LINCR, and RXSHORT - RXD pin short-circuit

•

Updated Freescale form and style

6.0

7.0

2/2009

3/2009

Added explanation for pins Not Connected (NC).

•

Changed VBAT_SHIFT and GND_SHIFT maximum from 10% to 11.5% for both parameters on page 13.

Combined Complete Data sheet for Part Numbers MC33910BAC and MC34910BAC to the back of this data

8.0

9.0

3/2010

sheet.

•

Changed ESD Voltage for Machine Model from ±200 to ±150

Added note ⁽⁷⁰⁾to Table 26

9/2015

7/2016

•

Updated to NXP document form and style

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99

Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

NXP.com

Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or

Document Number: MC33910

Rev. 9.0

7/2016


型号：	MC34910BAC,557
厂家：	NXP
描述：	Buffer/Inverter Based Peripheral Driver, 0.11A, PQFP32 驱动接口集成电路
文件：	总100页 (文件大小：2084K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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