MC34VR500VAES [NXP]
Multi-output DC/DC regulator for QorIQ LS1/T1 family of communications processors;
| 型号： | MC34VR500VAES |
| 厂家： | 
NXP |
| 描述： | Multi-output DC/DC regulator for QorIQ LS1/T1 family of communications processors |
| 文件： | 总92页 (文件大小：2550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC34VR500
Rev. 11, 4/2020
NXP Semiconductors
Technical Data
Multi-output DC/DC regulator for
QorIQ LS1/T1 family of
34VR500
communications processors
The 34VR500 is a high performance, highly integrated, multi-output,
SMARTMOS, DC/DC regulator solution, with integrated power MOSFETs
ideally suited for the LS1/T1 family of communication processors. Integrating
four switching and five linear regulators, the 34VR500 provides power to the
complete system, including the processor, DDR memory, and system
peripherals.
Power Management
Features:
ES SUFFIX (WF-TYPE)
98ASA00589D
56 QFN-EP WF8X8
• Four buck converters:
• SW1: 4.5 A
• SW2: 2.0 A
• SW3: 2.5 A
Applications:
• Internet of things (IoT) gateway
• Mobile wireless router
• MFP printer
• Network attached storage
• Automatic teller machine
• SW4: 1.0 A, (VTT tracking regulator)
• Five general purpose linear regulators
• DDR termination reference voltage (DDR3L and DDR4)
• Programmable low-power modes
• I2C control of all the regulators
• Power Control Logic with processor interface and event detection
LS102X
VDD
TA_BB_VDD
VDDC
VR500
SW1
SW2
OVDD1/2
LDO2
LDO4
L1VDD
OVDD
GVDD
3.3 VIN BUS
LDO5
SW3
DDR3
VTT
SW4
REFOUT
HDMI
LDO1
LDO3
Ethernet
Figure 1. 34VR500 simplified application diagram
© NXP B.V. 2020.
Table of Contents
1
2
3
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3 34VR500 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.4 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4
5
6
7
8
9
34VR500
2
NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided
on the web. To determine the orderable part numbers for this device, go to http://www.nxp.com and perform a part number search for the
following device numbers.
Table 1. Orderable part variations
Temperature
Part number
Package
SW4 VTT mode
Processor
Reference design
DDR memory
Notes
(T )
A
LS1021A IOT
Gateway
TWR-LS1021A
MC34VR500V1ES
Enabled
DDR3L (VTT = 0.675 V)
N/A
LS1020/21/22A
MC34VR500V2ES
MC34VR500V3ES
Disabled
Enabled
DDR4 (VTT = 0.6 V)
LS1043ARDB
T1023RDB
MC34VR500V4ES
Enabled
LS1043/23A
T1023/13
-40 °C to +105 °C 56 QFN 8x8 mm
MC34VR500V5ES
MC34VR500V6ES
MC34VR500V7ES
MC34VR500V8ES
MC34VR500V9ES
Enabled
Enabled
Enabled
Disabled
Disabled
DDR3L (VTT = 0.675 V)
(1)(2)
LS1024A
LS1020/21/22A
LS1046A
DDR4 (VTT = 0.6 V)
LS1046ARDB-PA
LS1028A-RDB
LS1028
LS1043/23A
T1023/13
LS1043ARDB
T1023RDB
MC34VR500VAES
Enabled
Disabled
DDR4 (VTT = 0.6 V)
N/A
MC34VR500VBES
Notes
LX2160
1.
2.
For tape and reel, add an R2 suffix to the part number.
See Table 8 for the start-up configuration.
34VR500
NXP Semiconductors
3
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
VR500
FB1
SW1 Buck
Regulator
4500 mA
VLDOIN1
LDO1
PVIN1
LX1
LDO1
250 mA
LDO2
100 mA
LDO2
VLDOIN23
LDO3
FB2
SW2 Buck
Regulator
2000 mA
PVIN2
LX2
LDO3
350 mA
LDO4
100 mA
LDO4
VLDOIN45
LDO5
FB3
SW3 Buck
Regulator
2500 mA
PVIN3
LX3
LDO5
200 mA
Buck
FB4
Regulator
Reference
Generation
SW4 Buck
Regulator
1000 mA
LDO
Reference
Generation
PVIN4
LX4
EPAD
VBG
VBIAS
Main and Standby
Bandgap
REFOUT
REFIN
VCCI2C
Clocks and
Resets
I2C Interface
Main State Machine
SCL
SDA
VHALF
VDIG Regulator
(Internal Use
Only)
VDIG
VCC
VCC Regulator
(Internal Use
Only)
SGND4
Figure 2. 34VR500 simplified internal block diagram
34VR500
4
NXP Semiconductors
PIN CONNECTIONS
3
Pin connections
3.1
Pinout diagram
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
2
DNC
INTB
DNC
42
41
40
39
38
LDO5
VLDOIN45
LDO4
FB3
3
PORB
STBY
ICTEST1
DNC
4
5
6
37 PVIN3
36 LX3
7
PVIN1
LX1
EP
8
35
34
33
32
31
30
29
LX3
9
PVIN3
DNC
LX1
10
11
12
13
14
PVIN1
LX1
SGND3
REFOUT
REFIN
VHALF
PVIN1
FB1
SGND1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Figure 3. 34VR500 pinout diagram
3.2
Pin definitions
Table 2. 34VR500 Pin Definitions
Pin
function
Pin number
Pin name
Max. rating
Type
Definition
1
INTB
DNC
O
3.6 V
—
Digital
Open drain interrupt signal to processor
2, 6, 16, 33,
42, 44, 45, 46
—
Reserved Leave floating
3
4
PORB
STBY
O
I
3.6 V
3.6 V
Digital
Digital
Open drain reset output to processor.
Standby input signal from processor
Digital/
Analog
5
ICTEST1
I
7.5 V
Reserved pin. Connect to GND in application.
34VR500
NXP Semiconductors
5
PIN CONNECTIONS
Table 2. 34VR500 Pin Definitions (continued)
Pin
Pin number
Pin name
Max. rating
Type
Definition
function
Input to SW1 regulator. Bypass with at least a 4.7 μF ceramic capacitor and
a 0.1 μF decoupling capacitor as close to the pin as possible.
7, 10, 12
8, 9, 11
13
PVIN1 (3)
LX1 (3)
I
O
4.8 V
4.8 V
3.6 V
-
Analog
Analog
Analog
GND
SW1 switching node connection
Output voltage feedback for SW1. Route this trace separately from the high
current path and terminate at the output capacitance.
FB1 (3)
I
14
SGND1
SGND2
GND
GND
Signal ground for SW1 regulator. Connect to ground plane directly.
Signal ground for SW2 and SW4 regulators. Connect to ground plane
directly.
15
-
GND
Input supply for LDO1. Bypass with a 1.0 μF decoupling capacitor as close
17
18
19
VLDOIN1
LDO1
I
O
I
3.6 V
2.5 V
3.6 V
Analog
Analog
Analog
to the pin as possible.
LDO1 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
Output voltage feedback for SW4. Route this trace separately from the high
current path and terminate at the output capacitance.
FB4 (3)
Input to SW4 regulator. Bypass with at least a 4.7μF ceramic capacitor and
a 0.1 μF decoupling capacitor as close to the pin as possible.
20
PVIN4 (3)
I
4.8 V
Analog
21
22
LX4 (3)
LX2 (3)
O
O
4.8 V
4.8 V
Analog
Analog
Regulator 4 switching node connection
Regulator 2 switching node connection
Input to SW2 regulator. Connect pins 23 and 24 together and bypass with at
least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close
to these pins as possible.
23, 24
PVIN2 (3)
I
4.8 V
Analog
Output voltage feedback for SW2. Route this trace separately from the high
current path and terminate at the output capacitance.
25
26
27
FB2 (3)
LDO2
I
O
I
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
LDO2 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
Input supply for LDO2 and LDO3. Bypass with a 1.0 μF decoupling capacitor
as close to the pin as possible.
VLDOIN23
28
29
LDO3
O
I
3.6 V
3.6 V
Analog
Analog
LDO3 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
VHALF
Half supply reference for DDR reference.
REFOUT regulator input. Bypass with at least 1.0 μF decoupling capacitor
as close to the pin as possible.
30
REFIN
I
3.6 V
Analog
31
32
REFOUT
SGND3
O
3.6 V
-
Analog
GND
REFOUT regulator output
GND
Ground reference for the SW3 regulator. Connect directly to ground plane.
Input to SW3 regulator. Bypass with at least a 4.7 μF ceramic capacitor and
a 0.1 μF decoupling capacitor as close to the pin as possible.
34, 37
35, 36
38
PVIN3 (3)
LX3 (3)
I
O
I
4.8 V
4.8 V
3.6 V
3.6 V
4.8 V
Analog
Analog
Analog
Analog
Analog
Regulator SW3 switching node connection
Output voltage feedback for SW3. Route this trace separately from the high
current path and terminate at the output capacitance.
FB3 (3)
39
LDO4
O
I
LDO4 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
Input supply for LDO4 and LDO5. Bypass with a 1.0 μF decoupling capacitor
as close to the pin as possible.
40
VLDOIN45
43
41
VBIAS
LDO5
I
1.8 V
3.6 V
Analog
Analog
Bypass the pin with a 0.47 μF capacitor.
O
LDO5 regulator output. By pass with a 2.2 μF ceramic output capacitor.
Digital/
Analog
47
ICTEST2
I
7.5 V
Reserved pin. Connect to GND in application.
48
49
SGND4
VCC
GND
O
-
GND
Ground for the main band gap regulator. Connect directly to ground plane.
Analog Core supply
3.6 V
Analog
34VR500
6
NXP Semiconductors
PIN CONNECTIONS
Table 2. 34VR500 Pin Definitions (continued)
Pin
Pin number
Pin name
Max. rating
Type
Definition
function
50
51
52
53
54
55
VIN
VDIG
VBG
I
O
O
I/O
I
4.8 V
1.5 V
1.5 V
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
Digital
Digital
Analog
Main chip supply
Digital Core supply
Main band gap reference. Bypass with 0.22uF capacitor.
I2C data line (Open drain)
SDA
SCL
I2C clock
VCCI2C
I
Supply for I2C bus. Bypass with 0.1 μF ceramic capacitor
Enable input. Connect to the processor. Pull-up via an 8.0 kΩ to 100 kΩ to
56
EN
EP
I
3.6 V
-
Digital
GND
VBIAS if required
Expose pad. Functions as ground return for buck regulators. Tie this pad to
the inner and external ground planes through vias to allow effective thermal
dissipation.
-
GND
Notes
3.
Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be
connected to the VIN pin with a 0.1 μF bypass capacitor.
34VR500
NXP Semiconductors
7
GENERAL PRODUCT CHARACTERISTICS
4
General product characteristics
4.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol
Description
Value
Unit
Notes
Electrical ratings
V
Main input supply voltage
-0.3 to 4.8
V
V
IN
ESD Ratings
Human Body Model
Charge Device Model
(4)
V
±2000
±500
ESD
Notes
4.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model
(CDM), Robotic (CZAP = 4.0 pF).
4.2
Thermal characteristics
Table 4. Thermal ratings
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Thermal ratings
TA
TJ
Ambient Operating Temperature Range
Operating Junction Temperature Range
-40
-40
-65
–
105
125
°C
°C
°C
°C
(5)
TST
Storage Temperature Range
150
(6) (7)
TPPRT
Peak Package Reflow Temperature
Note 7
QFN56 Thermal resistance and package dissipation ratings
Junction to Ambient
Natural Convection
Four layer board (2s2p)
Eight layer board (2s6p)
(8) (9) (10)
(8) (10)
RθJA
°C/W
°C/W
–
–
28
15
Junction to Ambient (at 200 ft/min)
RθJMA
Four layer board (2s2p)
–
–
–
22
10
(11)
(12)
RθJB
Junction to Board
°C/W
°C/W
RΘJCBOTTOM
Junction to Case Bottom
1.2
34VR500
8
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 4. Thermal ratings (continued)
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Junction to Package Top
(12)
ΨJT
–
2.0
°C/W
Natural Convection
Notes
5.
6.
7.
Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 5 for
thermal protection features.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
8.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
Per JEDEC JESD51-6 with the board horizontal.
9.
10.
11.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
12.
13.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
4.2.1 Power dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the
thermal management and to avoid overheating, the 34VR500 provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds
specified in Table 5 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry will shut down the 34VR500. This thermal protection will act above
the thermal protection threshold listed in Table 5. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured
such that this protection is not tripped under normal conditions.
Table 5. Thermal protection thresholds
Parameter
Thermal 110 °C Threshold (THERM110)
Min.
Typ.
Max.
Units
Notes
100
110
115
120
2.0
110
120
125
130
–
120
130
135
140
4.0
°C
°C
°C
°C
°C
°C
Thermal 120 °C Threshold (THERM120)
Thermal 125 °C Threshold (THERM125)
Thermal 130 °C Threshold (THERM130)
Thermal Warning Hysteresis
Thermal Protection Threshold
130
140
150
34VR500
NXP Semiconductors
9
GENERAL PRODUCT CHARACTERISTICS
4.3
Electrical characteristics
4.3.1 I/O specifications
Table 6. General PMIC static characteristics.
TA = -40 to 105 °C, VVIN = 2.8 to 4.5 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V 4.0%, typical external component values and full load
current range, unless otherwise noted.
Pin Name
Parameter
Load Condition
Min.
Max.
Unit
Notes
VIL
VIH
VOL
VOH
VIL
–
0.0
0.8 *VVBIAS
0.0
0.2 *VVBIAS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
EN
–
3.6
0.4
-2.0 mA
PORB
SCL
Open Drain
0.7* VVIN
0.0
VVIN
–
0.2 * VVCCI2C
3.6
VIH
VIL
–
0.8 * VVCCI2C
0.0
–
0.2 * VVCCI2C
3.6
VIH
VOL
VOH
VOL
VOH
VIL
–
-2.0 mA
Open Drain
-2.0 mA
Open Drain
–
0.8 * VVCCI2C
0.0
SDA
0.4
0.7 * VVCCI2C
0.0
VVCCI2C
0.4
INTB
0.7* VVIN
0.0
VVIN
0.2 *VVBIAS
3.6
STBY
VIH
–
0.8 *VVBIAS
4.3.2 Current consumption
Table 7. Current consumption summary
TA = -40 to 105 °C, (See Table 3), VVIN = 3.6 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V 4.0%, typical external component values, unless
otherwise noted. Typical values are characterized at VVIN = 3.6 V, VVCCI2C = 3.3 V, and 25 °C, unless otherwise noted.
Mode
34VR500 conditions
System conditions
Typ.
Max.
Unit
Notes
Wake-up from EN active
32 k RC on
All other blocks off
(14) (15)
Off
PMIC able to wake-up
17
25
μA
VIN ≥ UVDET
Wake-up from EN active
Trimmed reference active
SW3 PFM
Trimmed 16 MHz RC off
32 k RC on
(15)
Sleep
DDR memories in self refresh
122
250
μA
REFOUT disabled
34VR500
10
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 7. Current consumption summary (continued)
TA = -40 to 105 °C, (See Table 3), VVIN = 3.6 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V 4.0%, typical external component values, unless
otherwise noted. Typical values are characterized at VVIN = 3.6 V, VVCCI2C = 3.3 V, and 25 °C, unless otherwise noted.
Mode
34VR500 conditions
System conditions
Typ.
Max.
Unit
Notes
SW1 in PFM
SW2 in PFM
SW3 in PFM
SW4 in PFM
Trimmed 16 MHz RC enabled
Trimmed reference active
LDO1 - 5 enabled
REFOUT enabled
Processor enabled in low power mode. All
rails powered on except boost
(load = 0 mA)
(15)
Standby
297
550
μA
Notes
14.
When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
15.
For PFM operation (as defined in Table 23).
34VR500
NXP Semiconductors
11
GENERAL DESCRIPTION
5
General description
The 34VR500 is a high performance, highly integrated, multi-output, DC/DC regulator solution, with integrated power MOSFETs ideally
suited for the LS1/T1 family of communication processors.
5.1
Features
This section summarizes the 34VR500 features.
• Input voltage range: 2.8 V to 4.5 V
• Buck regulators
• Four independent outputs
• SW1, 4.5 A; 0.625 V to 1.875 V
• SW2, 2.0 A; 0.625 V to 3.3 V
• SW3, 2.5 A; 0.625 V to 3.3 V
• SW4, 1.0 A; operates in VTT mode for DDR termination at 50 % of SW3 for 34VR500V1, 34VR500V3, 34VR500V4,
34VR500V5, 34VR500V6, 34VR500V7, 34VR500VA and 0.625 V to 1.975 V for 34VR500V2, 34VR500V8, 34VR500V9
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable soft start
• Programmable PWM switching frequency
• Programmable OCP with fault interrupt
• LDOs
• Five general purpose LDOs
• LDO1, 0.80 V to 1.55 V, 250 mA
• LDO2, 1.8 V to 3.3 V, 100 mA
• LDO3, 1.8 V to 3.3 V, 350 mA
• LDO4, 1.8 V to 3.3 V, 100 mA
• LDO5, 1.8 V to 3.3 V, 200 mA
• Soft start
• DDR memory reference voltage
• REFOUT, 10 mA
• 16 MHz internal master clock
• I2C interface
• User programmable Standby, Sleep, and OFF modes
34VR500
12
NXP Semiconductors
GENERAL DESCRIPTION
5.2
Functional block diagram
MC34VR500 Functional Block Diagram
Start-up Configuration
Power Generation
(Factory programmable)
Vo1
Vo4
SW1
(0.625 - 1.875 V)
4.5A
SW2
(0.625 – 3.3 V)
2.0A
Vo2
Voltage
Phasing and Frequency Selection
Sequence and Timing
SW4
(0.625 - 1.975 V)
1.0A
SW3
(0.625 – 3.3 V)
2.5A
Vo3
VTToption
Logic and Control
LDO1
(0.8 - 1.55 V)
250 mA
LDO2
(1.8 - 3.3 V)
100 mA
Parallel MCU I nterf ace
Regulator Control
I2C Communication & Registers
LDO3
(1.8 – 3.3 V)
350 mA
LDO4
(1.8 - 3.3 V)
100 mA
Fault Detection & Protection
Thermal
LDO5
(1.8 - 3.3 V)
200 mA
Current Limit
Short-circuit
Figure 4. 34VR500 functional block diagram
5.3
Functional description
5.3.1 Power generation
The 34VR500 PMIC features four buck regulators, five general purpose LDOs, and a DDR voltage reference to supply voltages for the
processor, memory, and peripheral devices.
Depending on the system power path configuration, the five general purpose LDO regulators can be directly supplied from the main input
supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific REFOUT
voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination
5.3.2 Control logic
The 34VR500 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including
interrupt and reset. Startup voltage and sequence are internally programed. After power up, the regulator voltages can be changed via
I2C. The 34VR500 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor.
34VR500
NXP Semiconductors
13
GENERAL DESCRIPTION
5.3.2.1
Interface signals
EN
EN is an input signal to the IC that generates a turn-on event. Refer to section Turn on events for more details.
STBY
STBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode.
STBY can be configured as active high or active low using the STBYINV bit. Refer to the section Standby mode for more details.
PORB
PORB is an open-drain, active low output. In its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up
sequence is enabled; refer to Figure 8 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an
indicator that all supplies have been enabled; it is only asserted for a turn-off event.
INTB
INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is de-
asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
34VR500
14
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6
Functional block requirements and behaviors
6.1
Start-up
The 34VR500 starts up from the internal configuration, which is hard-coded into the device. However, the 34VR500 can be controlled
through the I2C port after the Start-up sequence. It is also possible to modify the contents of the Internal Registers via the bus I2C to modify
the start up parameters (see section Start sequence creation).
6.1.1 Device start-up configuration
Table 8 shows the internal configuration for the 34VR500V1, 34VR500V2, 34VR500V3, 34VR500V4, 34VR500V5, 34VR500V6,
34VR500V7, 34VR500V8, 34VR500V9, 34VR500VA, 34VR500VB.
Table 8. Start-up configuration
Registers
34VR500V1 34VR500V2 34VR500V3 34VR500V4 34VR500V5 34VR500V6 34VR500V7 34VR500V8 34VR500V9 34VR500VA 34VR500VB
2
0x08
Default I C Address
1.8 V
1
2.5 V
2
2.5 V
4
2.5 V
5
2.5 V
2
LDO2_VOLT
LDO2_SEQ
LDO3_VOLT
LDO3_SEQ
LDO4_VOLT
LDO4_SEQ
LDO5_VOLT
LDO5_SEQ
SW1_VOLT
SW1_SEQ
1.8 V
1
1.8 V
1
2.5 V
2
1.8 V
2
1.8 V
1
3.3 V
2
2.5 V
2.5 V
2
—
2.5 V
2
1
2
1.8 V
3
1
2.5 V
1
3
2.5 V
1
2
4
3.0 V
5
3
4
1.8 V
5
—
2.5 V
1
1.8 V
3
1.8 V
3
2.5 V
1
2.5 V
8
1.8 V
—
1.8 V
1
3.3 V
3
3.3 V
3
1.8 V
1
1.8 V
1
3.3 V
3
3.3 V
5
1.8 V
1
3.3 V
7
—
3.3 V
—
—
1.0 V
1.5 V
2
1.2 V
1.0 V
0.85 V
1
1.0 V
5
1.8 V
1
1.0 V
1.0 V
1.5 V
1.2 V
3
1.0 V
1.0 V
2
1.8 V
1
1.1 V
1
1.0 V
1.35 V
1
SW2_VOLT
SW2_SEQ
1.0 V
1.8 V
1
2.5 V
2
1.35 V
1
0.9 V
1
2
1.35 V
3
2
1.35 V
3
2
1.2 V
3
1.2 V
3
1.5 V
3
1.8 V
1
1.8 V
3
SW3_VOLT
SW3_SEQ
1.2 V
12
1.35 V
12
1.2 V
12
1.8 V
1
VTT
3
1.0 V
5
SW4_VOLT
SW4_SEQ
VTT
3
1.8 V
3
VTT
12
VTT
12
VTT
3
VTT
3
1.35 V
4
VTT
12
VTT
—
3
12
REFOUT_SEQ
LDO1_VOLT
LDO1_SEQ
3
3
12
3
3
—
4
12
3
1.2 V
4
1.2 V
4
1.2 V
4
1.35 V
1
1.35 V
12
1.1 V
1
1.35 V
4
—
—
1.35 V
1
1.35 V
—
—
—
PU CONFIG,
SEQ_CLK_SPEED
1.0 ms
PU CONFIG,
SWDVS_CLK
6.25 mV/μs
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
SW1 CONFIG
SW2 CONFIG
SW3 CONFIG
SW4 CONFIG
34VR500
NXP Semiconductors
15
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
UVDET
VIN
tR1
tD1
EN
tR2
tD2
LDO2,3,4,5
tR2
tD3
SW1,2
tR2
tD3
SW3,4
REFOUT
tR2
TD3
LDO1
PORB
tD4
tR3
Figure 5. Starting sequence: example for V1 and V2
Table 9. 34VR500V1 and V2 start-up sequence timing
Parameter
Description
Typ.
Unit
tD1
tR1
tD2
tR2
tD3
tD4
tR3
Turn-on delay
6.0
ms
ms
ms
ms
ms
ms
ms
(16)
Rise time of EN
Turn-on delay of first regulator
Rise time of regulators (17)
Delay between regulators
Turn-on delay of PORB
Rise time of PORB
2.5
0.2
1.0
2.0
0.2
Notes
16.
Depends on the external signal driving EN.
17.
Rise time is a function of slew rate of regulators and nominal voltage selected.
34VR500
16
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.1.2 Start sequence creation
The 34VR500 powers up based on the contents of the internal registers. Depending on certain bit settings, the internal registers are loaded
from different sources, as shown in Figure 6.
Figure 6. Starting sequence
The contents of the internal registers are initialized to zero when a valid VIN is first applied. The values that are then loaded into the internal
registers depend on the value of the TBB_POR (the initial value of TBB_POR is always “0”):
• If TBB_POR = 0 the values are loaded from the Default Sequence (this is the case always for first starting)
• If TBB_POR = 1 the values are loaded from the internal RAM. VIN must be valid to maintain the contents of the internal RAM.
To power on with the contents of the internal RAM, the following conditions must exist:
• VIN is valid
• TBB_POR = 1 and there is a valid turn-on event via the EN pin
To keep a regulator off during a start-up sequence is to set its sequence to 0. This corresponds to the XX_SEQ setting of 0x00.
For example, 0x01 corresponds to a sequence of 1, and so on.
34VR500
NXP Semiconductors
17
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 7 explains how to start from a new configuration.
First VIN Applied
34VR500
Keep EN pin in
regulators will not
turn on
low state
I2C
programming
+
Program the new
start sequence and
set TBB_POR to 1
TBB_POR = 1
Turn On event
EN pin to high
state
Create a Turn On
event via the EN pin
Start from the
Internal RAM
TBB_POR
TBB_POR = 1
TBB_POR = 0
Start from the
Default
Sequence
Figure 7. Modifying a starting sequence
Table 95 shows the portion of the register map concerning the programming of a new starting sequence.
6.2
16 MHz and 32 kHz clocks
There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within
-8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions:
• VIN < UVDET
• All regulators are in SLEEP mode
• All regulators are in PFM switching mode
A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 20 are referenced to the 32 kHz derived from the
16 MHz clock. The exceptions are the LOWVINI and ENI interrupts, which are referenced to the 32 kHz untrimmed clock.
Table 10. 16 MHz clock specifications
TA = -40 to 105 °C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V 4.0%, and typical external component values. Typical values are
characterized at VVIN = 3.6 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Operating Voltage from the VIN pin
Min.
Typ.
Max.
Units
Notes
VIN
2.8
–
4.5
V
34VR500
18
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 10. 16 MHz clock specifications
TA = -40 to 105 °C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V 4.0%, and typical external component values. Typical values are
characterized at VVIN = 3.6 V, and 25 °C, unless otherwise noted.
f16MHZ
f2MHZ
16 MHz Clock Frequency
2.0 MHz Clock Frequency
14.7
1.84
16
–
17.3
2.16
MHz
MHz
(18)
Notes
18.
2.0 MHz clock is derived from the 16 MHz clock.
6.2.1 Clock adjustment
The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By
changing the factory trim values of the 16 MHz clock, the user may add an offset as small as 3.0% of the nominal frequency. Contact a
NXP representative for detailed information on this feature.
6.3
Bias and references block description
6.3.1 Internal core voltage references
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VBG. The bandgap and the rest
of the core circuitry are supplied from VCC. Table 11 shows the main characteristics of the core circuitry.
Table 11. Core voltages electrical specifications(20)
TA = -40 to 105 °C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V 4.0%, and typical external component values. Typical values are
characterized at VVIN = 3.6 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
VDIG (digital core supply)
Output Voltage
(19)
VDIG
ON mode
OFF mode
–
–
1.5
1.3
–
–
V
VCC (Analog core supply)
Output Voltage
(19)
(19)
VCC
ON mode
OFF mode
–
–
2.775
0.0
–
–
V
VBG (bandgap / regulator reference)
VBG
Output Voltage
–
–
–
1.2
0.5
–
–
–
V
%
%
VBGACC
VBGTACC
Absolute Accuracy
Temperature Drift
0.25
Notes
19.
3.0 V < VIN < 4.5 V, no external loading on VDIG, VCC, or VBG. Extended operation down to UVDET, but no system malfunction.
For information only.
20.
6.3.1.1
External components
Table 12. External components for core voltages
Regulator
Capacitor value (μF)
VDIG
VCC
VBG
1.0
1.0
0.22
34VR500
NXP Semiconductors
19
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.3.2 REFOUT voltage reference
REFOUT is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input
voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole.
This divider then utilizes a voltage follower to drive the load.
REFIN
REFIN
CHALF1
100 nF
VHALF
_
+
CHALF2
100 nF
Discharge
REFOUT
REFOUT
CREFDDR
1.0 uf
Figure 8. REFOUT block diagram
6.3.2.1
REFOUT control register
The REFOUT voltage reference is controlled by a single bit in REFOUTCTRL register in Table 13.
Table 13. Register REFOUTCTRL - ADDR 0x6A
Name
UNUSED
Bit #
R/W Default
Description
3:0
–
R/W
–
0x00
0x00
0x00
UNUSED
Enable or disables REFOUT output voltage
0 = REFOUT Disabled
REFOUTEN
4
1 = REFOUT Enabled
UNUSED
7:5
UNUSED
External components
Table 14. REFOUT external components(21)
Capacitor
Capacitance (μF)
REFIN(22) to VHALF
VHALF to GND
REFOUT
0.1
0.1
1.0
Notes
21.
22.
Use X5R or X7R capacitors.
REFIN to GND, 1.0 μF minimum capacitance is provided by buck regulator output.
34VR500
20
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
REFOUT specifications
Table 15. REFOUT electrical characteristics
TA = -40 to 105 °C (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VREFIN = 1.5 V, VVBIAS = 1.0 V 4.0%, and typical external component
values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VREFIN = 1.5 V, and 25 °C, unless
otherwise noted.
Symbol
REFOUT
VREFIN
IREFDDR
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage Range
1.2
0.0
10.5
–
–
–
1.8
10
25
–
V
Operating Load Current Range
mA
mA
μA
IREFDDRLIM
Current Limit, IREFDDR when VREFOUT is forced to VREFIN/4
Quiescent Current
15
8.0
(23)
IREFDDRQ
Active mode – DC
Output Voltage
VREFOUT
–
–1.0
–
VREFIN/2
–
1.0
–
V
%
1.2 V < VREFIN < 1.8 V, 0.0 mA < IREFDDR < 10 mA
Output Voltage Tolerance
VREFOUTTOL
–
1.2 V < VREFIN < 1.8 V, 0.6 mA ≤ IREFDDR ≤ 10 mA
Load Regulation
VREFOUTLOR
0.40
mV/mA
1.0 mA < IREFDDR < 10 mA, 1.2 V < VREFIN < 1.8 V
Active mode – AC
Turn-on Time, Enable to 90% of end value
VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA
tONREFDDR
tOFFREFDDR
VREFOUTOSH
–
–
–
–
–
100
10
6.0
–
μs
ms
%
Turn-Off Time, Disable to 10% of initial value
VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA
–
Start-up Overshoot
1.0
5.0
VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA
Transient Load Response
VREFIN = 1.2 V, 1.8 V
VREFOUTTLR
mV
Notes
23.
When REFOUT is off there is a quiescent current of 1.5 μA typical.
34VR500
NXP Semiconductors
21
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4
Power generation
6.4.1 Modes of operation
The operation of the 34VR500 can be reduced to four states, or modes: ON, OFF, Sleep, and Standby. Figure 9 shows the state diagram
of the 34VR500, along with the conditions to enter and exit from each state.
Thermal shutdown
OFF
Sleep
EN = 1
& VIN > UVDET
EN = 0
Any SWxOMODE bits=1
EN = 0
All SWxOMODE bits= 0
EN = 0
Any SWxOMODE bits=1
EN = 1
ON
& VIN > UVDET
Thermal shudown
STANDBY asserted
STANDBY de-asserted
EN = 0
All SWxOMODE bits= 0
Thermal shutdown
Standby
Figure 9. State diagram
To complement the state diagram in Figure 9, a description of the states is provided in following sections. Note that VIN must exceed the
rising UVDET threshold to allow a power up. Refer to Table 22 for the UVDET thresholds. Additionally, the interrupt signal and INTB are
only active in Sleep, Standby, and ON states.
6.4.1.1
On mode
The 34VR500 enters the ON mode after a turn-on event. PORB is de-asserted, high, in this mode of operation.
6.4.1.2
Off mode
The 34VR500 enters the OFF mode after a turn-off event. A thermal shutdown event also forces the 34VR500 into the OFF mode. Only
VDIG is powered in this mode of operation. To exit the OFF mode, a valid turn-on event is required. PORB is asserted, LOW, in this mode.
34VR500
22
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.1.3
Standby mode
• Depending on STBY pin configuration, Standby is entered when the STBY pin is asserted. This is typically used for low-power mode
of operation.
• When STBY is de-asserted, Standby mode is exited.
A product may be designed to go into a Low-power mode after periods of inactivity. The STBY pin is provided for board level control of
going in and out of such deep sleep modes (DSM).
When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the
operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby are pre-programmed through
the I2C interface.
Note that the STBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account
the programmed input polarity as shown in Table 16. When the 34VR500 is powered up first, regulator settings for the Standby mode are
mirrored from the regulator settings for the ON mode. To change the STBY pin polarity to Active Low, set the STBYINV bit via software
first, and then change the regulator settings for Standby mode as required. For simplicity, STBY will generally be referred to as active high
throughout this document.
Table 16. STBY pin and polarity control
STBY (Pin)(25)
STBYINV (I2C bit)(26)
STBY Control (24)
0
0
1
1
0
1
0
1
0
1
1
0
Notes
24.
STBY = 0: System is not in Standby, STBY = 1: System is in Standby
The state of the STBY pin only has influence in On mode.
Bit 6 in Power Control Register (ADDR - 0x1B)
25.
26.
Since STBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the
pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and
peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into Standby
mode.
When enabled (STBYDLY = 01, 10, or 11) per Table 17, STBYDLY will delay the Standby initiated response for the entire IC, until the
STBYDLY counter expires.
An allowance should be made for three additional 32 k cycles required to synchronize the Standby event.
Table 17. STBY delay - initiated response
STBYDLY[1:0](27)
Function
00
01
10
11
No Delay
One 32 k period (default)
Two 32 k periods
Three 32 k periods
Notes
27.
Bits [5:4] in Power Control Register (ADDR - 0x1B)
34VR500
NXP Semiconductors
23
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.1.4
Sleep mode
• Depending on EN pin configuration, Sleep mode is entered when EN is de-asserted and SWxOMODE bit is set.
• To exit Sleep mode, assert the EN pin.
In the Sleep mode, the regulator will use the set point as programmed by SW1OFF[5:0] for SW1, SW2, SW3, and SW4. The activated
regulators will maintain settings for this mode and voltage until the next turn-on event. Table 18 shows the control bits in Sleep mode.
During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event.
Table 18. Regulator mode control
SWxOMODE
Off operational mode (sleep) (28)
0
1
Off
PFM
Notes
28.
For sleep mode, an activated switching regulator, should use the off mode set
point as programmed by SW1OFF[5:0] for SW1, SW2, SW3, and SW4.
6.4.2 State machine flow summary
Table 19 provides a summary matrix of the 34VR500 flow diagram to show the conditions needed to transition from one state to another.
Table 19. State machine flow summary
Next state
STATE
OFF
Sleep
Standby
ON
OFF
X
X
X
X
X
EN = 1 & VIN > UVDET
EN = 1 & VIN > UVDET
Sleep
Thermal Shutdown
Thermal Shutdown
Standby
ON
EN = 0, Any SWxOMODE = 1
EN = 0, Any SWxOMODE = 1
X
Standby de-asserted
X
EN = 0, All SWxOMODE = 0
Thermal Shutdown
Standby asserted
EN = 0, All SWxOMODE = 0
6.4.2.1
Turn on events
From OFF and Sleep modes, the PMIC is powered on by a turn ON event. VIN must be greater than UVDET for the PMIC to turn-on. When
VIN is greater than UVDET, a logic high on the EN pin is a turn ON event, when EN is high before VIN is valid, a VIN transition, from 0.0 V
to a voltage greater than UVDET, also a Turn ON event. See the State diagram, Figure 9, and the Table 19 for more details. Any regulator
enabled in the Sleep mode will remain enabled when transitioning from Sleep to ON, i.e., the regulator will not be turned OFF and then
ON again to match the start-up sequence. The following is a more detailed description of the EN configuration:
• The EN signal is high and VIN > UVDET, the PMIC will turn ON; the interrupt and sense bits, ENI and ENS respectively, will be set.
The sense bit will show the real time status of the EN pin. In this configuration, the EN input can be a mechanical switch debounced
through a programmable debouncer, ENDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press. The interrupt is
generated for both the falling and the rising edge of the EN pin. By default, a 30 ms interrupt debounce is applied to both falling and rising
edges. The falling edge debounce timing can be extended with ENDBNC[1:0] as defined in the table below. The interrupt is cleared by
software, or when cycling through the OFF mode.
34VR500
24
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 20. EN hardware debounce bit settings
Turn on
Falling edge INT
debounce (ms)
Rising edge INT
debounce (ms)
Bits
State
debounce (ms)
00
01
10
11
0.0
31.25
125
31.25
31.25
125
31.25
31.25
31.25
31.25
ENDBNC[1:0]
Notes
750
750
29.
The sense bit, ENS, is not debounced and follows the state of the EN pin.
6.4.2.2
EN pin
Turn off events
The EN pin is used to power off the 34VR500. The Off mode is entered when the EN pin is low and SWxOMODE = 0.
Thermal protection
If the die temperature surpasses a given threshold, the thermal protection circuit will power off the 34VR500 to avoid damage. A turn-on
event will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature decreases
below a given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power dissipation section for
more detailed information.
Undervoltage detection
The state machine will transition to the OFF mode when the voltage at the VIN pin drops below the UVDET undervoltage falling threshold.
6.4.3 Power tree
The 34VR500 features four buck regulators, five general purpose LDOs, and a DDR voltage reference, to supply voltages for the
application and peripheral devices. The buck regulators are supplied directly from the main input supply (VIN). The inputs to all of the buck
regulators must be tied to VIN, whether they are powered ON or OFF. The five general use LDO regulators are directly supplied from the
main input supply or from the switching regulators depending on the application requirements. Since REFOUT is intended to provide DDR
memory reference voltage, it should be supplied by any rail supplying voltage to DDR memories; the typical application recommends the
use of SW3 as the input supply for REFOUT. Refer to Table 21 for a summary of all power supplies provided by the 34VR500.
Table 21. Power tree summary
Supply
Output voltage (V)
Step size (mV)
Maximum load current (mA)
SW1
SW2
SW3
0.625 - 1.875
25
4500
2000
2500
0.625 - 1.975 / 0.8 - 3.3
0.625 - 1.975 / 0.8 - 3.3
25 / 50
25 / 50
0.5*SW3_OUT (VTT for V1, V3,
V4, V5), 0.625 - 1.975 (for V2)
SW4
1000
LDO1
LDO2
0.80 – 1.55
1.8 – 3.3
50
250
100
350
100
200
10
100
100
100
100
NA
LDO3
1.8 – 3.3
LDO4
1.8 – 3.3
LDO5
1.8 – 3.3
REFOUT
0.5*SW3_OUT
34VR500
NXP Semiconductors
25
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial
power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative
tables and text specifying each supply for information on performance metrics and operating ranges. Table 22 summarizes the UVDET
thresholds.
Table 22. UVDET threshold
UVDET threshold
VIN
Rising
Falling
3.1 V
2.65 V
VR500
LS102x
VDDCORE
SW1
VDDCORE
(0.625 to 1.875 V), 4.5 A
SW2
VDDC
VDDC
VIN
3.3 V
(0.625 to 3.3 V),
2.0 A
LDO2
(1.8 to 3.3 V),
100 mA
OVDD1/2
LDO4
(1.8 to 3.3 V),
100 mA
L1VDD
OVDD
LDO5
(1.8 to 3.3 V),
200 mA
SW3
DDR CORE
(0.625 to 3.3 V),
2.5 A
SW4
System/VTT
(0.625 to 1.975 V)
(0.5*VDDR)
1.0 A
REFOUT
0.5*VDDR, 10 mA
SW3
DDR3
VTT
LDO1
(0.80 to 1.55 V),
250 mA
Peripherals
VIN
3.3 V
LDO3
(1.8 to 3.3 V),
350 mA
Figure 10. 34VR500 typical power map
34VR500
26
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4 Buck regulators
Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.
6.4.4.1
Current limit
Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit
condition persists for more than 8.0 ms, a fault interrupt is generated.
6.4.4.2
General control
To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur
by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current
variation. Available switching modes for buck regulators are presented in Table 23.
Table 23. Switching mode description
Mode
Description
OFF
The regulator is switched off and the output voltage is discharged.
In this mode, the regulator is always in PFM mode, which is useful at light loads for
optimized efficiency.
PFM
PWM
APS
In this mode, the regulator is always in PWM mode operation regardless of load conditions.
In this mode, the regulator moves automatically between pulse skipping mode and PWM
mode depending on load conditions.
During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after
the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching
mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes.
Table 24 summarizes the Buck regulator programmability for Normal and Standby modes.
Table 24. Regulator mode control
SWxMODE[3:0]
Normal Mode
Standby Mode
SWxMODE[3:0]
Normal Mode
Standby Mode
0000
0001
0010
0011
0100
0101
0110
0111
Off
PWM
Off
Off
1000
1001
1010
1011
1100
1101
1110
1111
APS
APS
Reserved
Reserved
Reserved
APS
Reserved
Reserved
Reserved
PFM
Reserved
PFM
Reserved
Off
APS
Off
PWM
PWM
APS
PWM
PFM
PWM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate of the
output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic voltage scaling. For each regulator, the
output voltage options are the same for Normal and Standby modes.
When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected
by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage
programmed in its voltage register.
34VR500
NXP Semiconductors
27
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Any regulators whose SWxOMODE bit is set to “1” will enter Sleep mode if a EN turn-off event occurs, and any regulator whose
SWxOMODE bit is set to “0” will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage
register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose
SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state.
Any regulator whose SWxOMODE bit is set to “0” will be powered up with the same delay in the start-up sequence as when powering On
from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings.
Table 18 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point
as programmed by SWxOFF[5:0] for SW1, SW2, SW3, and SW4.
6.4.4.3
Dynamic voltage scaling
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.
1. Normal operation: The output voltage is selected by I2C bits SWx[5:0] for SW1, SW2, SW3, and SW4. A voltage transition initiated
by I2C is governed by the DVS stepping rates shown in Table 26.
2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SWxSTBY[5:0] for SW1, SW2, SW3, and SW4. Voltage transitions
initiated by a Standby event are governed by the SWxDVSSPEED[1:0] and I2C bits shown in Table 26.
3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SWxOFF[5:0] for SW1, SW2, SW3, and SW4. Voltage transitions
initiated by a turn-off event are governed by the SWxDVSSPEED[1:0] I2C bits shown in Table 26.
Table 25, Table 26, summarize the set point control and DVS time stepping applied to all regulators.
Table 25. DVS control logic for SW1, SW2, SW3, and SW4
STBY
Set Point Selected by
0
1
SWx[5:0]
SWxSTBY[5:0]
Table 26. DVS speed selection for SW1, SW2, SW3, and SW4
SWxDVSSPEED[1:0]
Function
00
01 (default)
10
25 mV step each 2.0 μs
25 mV step each 4.0 μs
25 mV step each 8.0 μs
25 mV step each 16 μs
11
The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are
determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in
PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control.
During the DVS period the overcurrent condition on the regulator should be masked.
34VR500
28
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Requested
Set Point
Output Voltage
with light Load
Internally
Controlled Steps
Example
Actual Output
Voltage
Output
Voltage
Initial
Set Point
Actual
Output Voltage
Internally
Controlled Steps
Possible
Output Voltage
Window
Request for
Higher Voltage
Request for
Lower Voltage
Voltage
Change
Request
Initiated by I2C Programming, Standby Control
Figure 11. Voltage stepping with DVS
6.4.4.4
Regulator phase clock
The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 27. By default, each regulator is initialized at 90 ° out
of phase with respect to each other. For example, SW1 is set to 0 °, SW2 is set to 90 °, SW3 is set to 180 °, and SW4 is set to 270 ° by
default at power up.
Table 27. Regulator phase clock selection
SWxPHASE[1:0] Phase of Clock Sent to Regulator (degrees)
00
01
10
11
0
90
180
270
The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 29 shows the
selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different
frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and
4.0 MHz, 180 ° are the same in terms of phasing. Table 28 shows the optimum phasing when using more than one switching frequency.
Table 28. Optimum phasing
Frequencies
Optimum phasing
1.0 MHz
2.0 MHz
0 °
180 °
1.0 MHz
4.0 MHz
0 °
180 °
2.0 MHz
4.0 MHz
0 °
180 °
1.0 MHz
2.0 MHz
4.0 MHz
0 °
90 °
90 °
34VR500
NXP Semiconductors
29
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 29. Regulator frequency configuration
SWxFREQ[1:0]
Frequency
00
01
10
11
1.0 MHz
2.0 MHz
4.0 MHz
Reserved
6.4.4.5
SW1 regulator
The SW1 is a 4.5 A regulator capable of providing an output from 0.625 to 1.875 V. Figure 12 shows a high level block diagram of the
SW1 regulator.
PVIN1
PVIN1
SW1MODE
ISENSE
CINSW1
Controller
SW1
LX1
EP
Driver
LSW1
COSW1
SW1FAULT
I2C
Interface
I2C
Internal
Compensation
Z2
FB1
Z1
VREF
EA
DAC
Figure 12. SW1 regulator block diagram
6.4.4.6
SW1 setup and control registers
SW1 output voltage is programmable from 0.625 to 1.875 V in steps of 25 mV. After power up in the default voltage, the output voltage
can be changed in the Normal, Standby and Sleep mode by writing to the SW1[5:0], SW1STBY[5:0], and SW1OFF[5:0] respectively.
Figure 30 shows the output voltage coding for these registers.
Table 30. SW1 output voltage configuration
SW1[5:0]
SW1[5:0]
Set point
SW1STBY[5:0]
SW1OFF[5:0]
SW1 output (V)
Set point
SW1STBY[5:0]
SW1OFF[5:0]
SW1 output (V)
13
14
15
16
17
18
19
20
21
001101
001110
001111
010000
010001
010010
010011
010100
010101
0.6250
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
39
40
41
42
43
44
45
46
47
100111
101000
101001
101010
101011
101100
101101
101110
101111
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
34VR500
30
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 30. SW1 output voltage configuration (continued)
SW1[5:0]
SW1[5:0]
Set point
SW1STBY[5:0]
SW1OFF[5:0]
SW1 output (V)
Set point
SW1STBY[5:0]
SW1OFF[5:0]
SW1 output (V)
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
Table 31 provides a list of registers used to configure and operate SW1 and a detailed description on each one of these register is provided
in Table 31 through Table 36.
Table 31. SW1 register summary
Register
SW1VOLT
Address
Output
0x2E
0x2F
0x30
0x31
0x32
SW1 Output voltage set point in normal operation
SW1 Output voltage set point in Standby
SW1 Output voltage set point in Sleep
SW1STBY
SW1OFF
SW1MODE
SW1CONF
SW1 Switching Mode selector register
SW1 DVS, Phase, Frequency and ILIM configuration
Table 32. Register SW1VOLT - ADDR 0x2E
Name
Bit #
R/W Default
Description
Sets the SW1 output voltage during normal operation mode. See Table 30
for all possible configurations.
SW1
UNUSED
5:0
7:6
R/W
–
0x00
0x00
UNUSED
Table 33. Register SW1STBY - ADDR 0x2F
Name
SW1STBY
Bit #
R/W Default
Description
Sets the SW1 output voltage during Standby mode. See Table 30 for all
possible configurations.
5:0
7:6
R/W
–
0x00
0x00
UNUSED
UNUSED
34VR500
NXP Semiconductors
31
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 34. Register SW1OFF - ADDR 0x30
Name
SW1OFF
UNUSED
Bit #
R/W Default
Description
Sets the SW1 output voltage during Sleep mode. See Table 30 for all
possible configurations.
5:0
7:6
R/W
–
0x00
0x00
UNUSED
Table 35. Register SW1MODE - ADDR 0x31
Name
SW1MODE
Bit #
R/W Default
Description
Sets the SW1 switching operation mode. See Table 23 for all possible
configurations.
3:0
4
R/W
–
0x08
0x00
UNUSED
UNUSED
Set status of SW1 when in Sleep mode
SW1OMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
Table 36. Register SW1CONF - ADDR 0x32
Name
Bit #
R/W
Default
Description
SW1 current limit level selection
SW1ILIM
0
R/W
0x00
0 = High level current limit
1 = Low level current limit
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
Unused
SW1FREQ
3:2
5:4
7:6
SW1 switching frequency selector. See Table 29.
SW1 Phase clock selection. See Table 27.
SW1 DVS speed selection. See Table 26.
SW1PHASE
SW1DVSSPEED
6.4.4.7
SW1 external components
Table 37. SW1 external component recommendations
Components
Description
SW1input capacitor
Component
(30)
CINSW1
3 x 4.7 μF
3 x 0.1 μF
(30)
CIN1HF
SW1decoupling input capacitor
SW1 output capacitor
SW1 inductor
(30)
COSW1
7 x 22 μF
LSW1
0.68 μH, DCR = 10 mΩ, ISAT = 9.0 A
Notes
30.
Use X5R or X7R capacitors.
34VR500
32
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.8
SW1 specifications
Table 38. SW1 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, V
= 1.2 V, I
= 100 mA,
SW1
A
IN
PVIN1
SW1
V
V
= 1.0 V 4.0%, typical external component values, f
= 2.0 MHz, unless otherwise noted. Typical values are characterized at
VBIAS
SW1
= V
= 3.6 V, V
= 1.2 V, I
= 100 mA, and 25 °C, unless otherwise noted.
IN
PVIN1
SW1
SW1
Symbol
Switch mode supply SW1
Parameter
Min.
Typ.
Max.
Unit
Notes
VPVIN1
VSW1
Operating Input Voltage
Nominal Output Voltage
Output Voltage Accuracy
2.8
–
–
4.5
–
V
V
Table 30
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1 < 4.5 A
0.625 V ≤ VSW1 ≤ 1.450 V
1.475 V ≤ VSW1 ≤ 1.875 V
-25
-3.0
–
–
25
3.0
mV
%
VSW1ACC
•
PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1 < 150 mA
-65
-45
-3.0
–
–
–
65
45
3.0
mV
mV
%
0.625 V < VSW1 < 0.675 V
0.7 V < VSW1 < 0.85 V
0.875 V < VSW1 < 1.875 V
Rated Output Load Current,
ISW1
–
–
4500
mA
2.8 V < VIN < 4.5 V, 0.625 V < VSW1 < 1.875 V
Current Limiter Peak Current Detection
•
Current through Inductor
SW1ILIM = 0
ISW1LIM
7.1
5.3
10.5
7.9
13.7
10.3
A
SW1ILIM = 1
Start-up Overshoot
VSW1
ISW1 = 0 mA
–
–
–
–
66
mV
µs
DVS clk = 25 mV/4 μs, VIN = VPVIN1 = 4.5 V, VSW1 = 1.875 V
Turn-on Time, Enable to 90% of end value
tONSW1
500
ISW1 = 0 mA, DVS clk = 25 mV/4.0 μs, VIN = VPVIN1 = 4.5 V,
V
SW1 = 1.875 V
Switching Frequency
SW1FREQ[1:0] = 00
SW1FREQ[1:0] = 01
SW1FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW1
MHz
Efficiency
•
VIN = 3.6 V, fSW1 = 2.0 MHz, LSW1 = 1.0 μH
–
–
–
–
–
–
77
82
86
84
80
68
–
–
–
–
–
–
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 850 mA
APS, PWM, 1.2 V, 1275 mA
APS, PWM, 1.2 V, 2125 mA
APS, PWM, 1.2 V, 4500 mA
ηSW1
%
ΔVSW1
VSW1LIR
VSW1LOR
Output Ripple
–
–
–
5.0
–
–
mV
mV
mV
Line Regulation (APS, PWM)
DC Load Regulation (APS, PWM)
Transient Load Regulation
20
20
–
•
Transient load = 0 to 2.25 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW1LOTR
mV
–
–
–
–
50
50
34VR500
NXP Semiconductors
33
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 38. SW1 electrical characteristics (continued)
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, V
= 1.2 V, I
= 100 mA,
SW1
A
IN
PVIN1
SW1
V
V
= 1.0 V 4.0%, typical external component values, f
= 2.0 MHz, unless otherwise noted. Typical values are characterized at
VBIAS
SW1
= V
= 3.6 V, V
= 1.2 V, I
= 100 mA, and 25 °C, unless otherwise noted.
IN
PVIN1
SW1
SW1
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW1 (continued)
Quiescent Current
ISW1Q
PFM Mode
APS Mode
–
–
18
145
–
–
µA
RSW1DIS
Discharge Resistance
–
–
600
60
–
Ω
SW1 P-MOSFET RDS(on)
VPVIN1 = 3.3 V
RONSW1P
77
mΩ
SW1 N-MOSFET RDS(on)
VPVIN1 = 3.3 V
RONSW1N
–
80
101
mΩ
100
90
80
70
60
50
40
30
20
10
0
2MHz, 1.8V, PWM
1MHz, 1.8V, PWM
100
1000
Load Current (mA)
SW1 Efficiency Waveform: VIN = 3.3 V; VOUT = 1.8 V
10000
SW1 Efficiency Waveform: VIN = 3.6 V; VOUT = 1.2 V
SW1 Efficiency Waveform: VIN = 3.6 V; VOUT = 1.2 V
Figure 13. SW1 efficiency waveforms
34VR500
34
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 14. Load transient response – SW1 (APS)
6.4.4.9
SW2
SW2 is a 2.0 A rated buck regulator. Table 23 describes the modes, and Table 24 show the options for the SWxMODE[3:0] bits.
Figure 15 shows the block diagram and the external component connections for SW2 regulator.
PVIN2
PVIN2
SW2MODE
ISENSE
CINSW2
Controller
SW2
LX2
EP
Driver
LSW2
COSW2
SW2FAULT
I2C
Interface
Internal
I2C
Compensation
Z2
FB2
Z1
VREF
EA
DAC
Figure 15. SW2 block diagram
34VR500
NXP Semiconductors
35
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.10 SW2 setup and control registers
SW2 output voltage is programmable from 0.625 V to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal
operation. Its value is determined by the default configuration. Therefore, once SW2[6] is set to "0", the output is limited to the lower output
voltages from 0.625 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. Likewise, once bit SW2[6] is set to "1", the
output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV increments, as determined by bits
SW2[5:0].
In order to optimize the performance of the regulator, it is recommended only voltages from 2.000 V to 3.300 V be used in the high range,
and the lower range be used for voltages from 0.625 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW2[5:0], SW2STBY[5:0]
and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] are copied into bits SW2STBY[6], and SW2OFF[6] bits.
Therefore, the output voltage range remains the same in all three operating modes. Table 39 shows the output voltage coding valid for
SW2.
Table 39. SW2 output voltage configuration
Low output voltage range(31)
High output voltage range
Set Point
SW2[6:0]
SW2 Output
Set Point
SW2[6:0]
SW2 Output
0
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.6250
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
0.8000
0.8500
0.9000
0.9500
1.0000
1.0500
1.1000
1.1500
1.2000
1.2500
1.3000
1.3500
1.4000
1.4500
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
2.1000
2.1500
2.2000
2.2500
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
34VR500
36
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 39. SW2 output voltage configuration(continued)
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
94
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
2.3000
2.3500
95
96
2.4000
97
2.4500
98
2.5000
99
2.5500
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
2.6000
2.6500
2.7000
2.7500
2.8000
2.8500
2.9000
2.9500
3.0000
3.0500
3.1000
3.1500
3.2000
3.2500
3.3000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes
31.
For voltages less than 2.0 V, only use set points 9 to 63.
2
Setup and control of SW2 is done through I C registers listed i n Table 40, and a detailed description of each one of the registers is
provided in Tables 41 to Table 45.
34VR500
NXP Semiconductors
37
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 40. SW2 register summary
Register
SW2VOLT
Address
Description
0x35
0x36
0x37
0x38
0x39
Output voltage set point on normal operation
Output voltage set point on Standby
Output voltage set point on Sleep
SW2STBY
SW2OFF
SW2MODE
SW2CONF
Switching Mode selector register
DVS, Phase, Frequency, and ILIM configuration
Table 41. Register SW2VOLT - ADDR 0x35
Name
Bit #
R/W Default
Description
Sets the SW2 output voltage during normal operation
mode. See Table 39 for all possible configurations.
SW2
SW2
5:0
R/W
0x00
Sets the operating output voltage range for SW2. Set
by OTP. See Table 39 for all possible configurations.
6
7
R
–
0x00
0X00
UNUSED
UNUSED
Table 42. Register SW2STBY - ADDR 0x36
Name
SW2STBY
Bit #
R/W Default
Description
Sets the SW2 output voltage during Standby mode.
See Table 39 for all possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW2 on
Standby mode. This bit inherits the value configured
on bit SW2[6] by OTP. See Table 39 for all possible
configurations.
SW2STBY
UNUSED
6
7
R
–
0x00
0X00
UNUSED
Table 43. Register SW2OFF - ADDR 0x37
Name
SW2OFF
Bit #
R/W Default
Description
Sets the SW2 output voltage during Sleep mode. See
Table 39 for all possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW2 on
Sleep mode. This bit inherits the value configured on
bit SW2[6] by OTP. See Table 39 for all possible
configurations.
SW2OFF
UNUSED
6
7
R
–
0x00
0X00
UNUSED
Table 44. Register SW2MODE - ADDR 0x38
Name
SW2MODE
Bit #
R/W Default
Description
Sets the SW2 switching operation mode.
See Table 23 for all possible configurations.
3:0
4
R/W
–
0x08
0x00
UNUSED
UNUSED
Set status of SW2 when in Sleep mode
SW2OMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
34VR500
38
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 45. Register SW2CONF - ADDR 0x39
Name
Bit #
R/W Default
Description
SW2 current limit level selection
SW2ILIM
0
R/W
0x00
0 = High level current limit
1 = Low level current limit
UNUSED
1
R/W
R/W
0x00
0x00
Unused
SW2 switching frequency selector.
See Table 29.
SW2FREQ
3:2
SW2 Phase clock selection.
See Table 27.
SW2PHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW2 DVS speed selection.
See Table 28.
SW2DVSSPEED
6.4.4.11 SW2 external components
Table 46. SW2 external component recommendations
Components
Description
SW2 Input capacitor
Values
(32)
CINSW2
4.7 μF
0.1 μF
(32)
CIN2HF
SW2 Decoupling input capacitor
SW2 Output capacitor
(32)
COSW2
3 x 22 μF
1.5 μH
LSW2
SW2 Inductor
DCR = 50 mΩ
ISAT = 2.6 A
Notes
32.
Use X5R or X7R capacitors.
6.4.4.12 SW2 specifications
Table 47. SW2 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, I
= 100 mA, V
= 1.0 V 4.0%, typical
VBIAS
A
IN
PVIN2
SW2
external component values, f
= 2.0 MHz, unless otherwise noted. Typical values are characterized at V = V = 3.6 V,
SW2
IN
PVIN2
I
= 100 mA, and 25 °C, unless otherwise noted.
SW2
Symbol
Switch mode supply SW2
VPVIN2 Operating Input Voltage
VSW2
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
–
–
4.5
–
V
V
Nominal Output Voltage
Output Voltage Accuracy
Table 39
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 2.0 A
-25
-3.0
-6.0
–
–
–
25
3.0
6.0
mV
%
%
0.625 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
VSW2ACC
•
PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA
-65
-45
-3.0
-3.0
–
–
–
–
65
45
3.0
3.0
mV
mV
%
0.625 V < VSW2 < 0.675 V
0.7 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
%
34VR500
NXP Semiconductors
39
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 47. SW2 electrical characteristics (continued)
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, I
= 100 mA, V
= 1.0 V 4.0%, typical
VBIAS
A
IN
PVIN2
SW2
external component values, f
= 2.0 MHz, unless otherwise noted. Typical values are characterized at V = V = 3.6 V,
SW2
IN
PVIN2
I
= 100 mA, and 25 °C, unless otherwise noted.
SW2
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Rated Output Load Current
ISW2
mA
(33)
2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V
–
–
2000
Current Limiter Peak Current Detection
•
Current through Inductor
SW2ILIM = 0
SW2ILIM = 1
ISW2LIM
A
2.8
2.1
4.0
3.0
5.2
3.9
Start-up Overshoot
VSW2OSH
–
–
–
–
66
mV
µs
ISW2 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN2 = 4.5 V
Turn-ON Time, Enable to 90% of end value
tONSW2
500
ISW2 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN2 = 4.5 V
Switching Frequency
SW2FREQ[1:0] = 00
SW2FREQ[1:0] = 01
SW2FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW2
MHz
Notes
33.
The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).
34VR500
40
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 47. SW2 electrical characteristics (continued)
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, I
= 100 mA, V
= 1.0 V 4.0%, typical
VBIAS
A
IN
PVIN2
SW2
external component values, f
= 2.0 MHz, unless otherwise noted. Typical values are characterized at V = V = 3.6 V,
SW2
IN
PVIN2
I
= 100 mA, and 25 °C, unless otherwise noted.
SW2
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW2 (continued)
Efficiency
•
VIN = 2.8 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
–
77
–
APS, PWM, 1.0 V, 1000 mA
•
V
IN = 4.5V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
–
–
–
68
68
76
–
–
–
PFM, 1.0 V, 50 mA
APS, 1.0 V, 1.0 mA
APS, 1.0 V, 1000 mA
VIN = 3.6V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
ηSW2
%
•
–
–
–
–
–
–
94
95
96
94
92
86
–
–
–
–
–
–
PFM, 3.15 V, 1.0 mA
PFM, 3.15 V, 50 mA
APS, PWM, 3.15 V, 400 mA
APS, PWM, 3.15 V, 600 mA
APS, PWM, 3.15 V, 1000 mA
APS, PWM, 3.15 V, 2000 mA
ΔVSW2
VSW2LIR
VSW2LOR
Output Ripple
–
–
–
5.0
–
–
mV
mV
mV
Line Regulation (APS, PWM)
DC Load Regulation (APS, PWM)
Transient Load Regulation
20
20
–
•
Transient load = 0.0 mA to 0.5 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW2LOTR
mV
–
–
–
–
50
50
Quiescent Current
PFM Mode
APS Mode (Low output voltage settings)
APS Mode (High output voltage settings)
–
–
–
23
145
305
–
–
–
ISW2Q
µA
SW2 P-MOSFET RDS(on)
at VIN = VPVIN2 = 3.3 V
RONSW2P
–
190
209
mΩ
SW2 N-MOSFET RDS(on)
at VIN = VPVIN2 = 3.3 V
RONSW2N
RSW2DIS
–
–
212
600
255
–
mΩ
Discharge Resistance
Ω
34VR500
NXP Semiconductors
41
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW2 Efficiency Waveform: VIN = 3.6V; VOUT = 1.8V
Figure 16. SW2 efficiency waveforms
Figure 17. Load transient response – SW2 (PWM)
6.4.4.13 SW3
SW3 is a 2.5 A regulator capable of providing an output from 0.625 V to 3.3 V. Figure 18 shows a high level block diagram of the SW3
regulator.
34VR500
42
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
PVIN3
PVIN3
SW3MODE
ISENSE
CINSW3
Controller
SW3
LX3
EP
Driver
LSW3
COSW3
SW3FAULT
I2C
Interface
I2C
Internal
Compensation
Z2
FB3
Z1
VREF
EA
DAC
Figure 18. SW3 regulator block diagram
6.4.4.14 SW3 setup and control registers
SW3 output voltage is programmable from 0.625 V to 3.300 V; however, bit SW3 [6] in register SW3VOLT is read-only during normal
operation. Its value is determined by the default configuration. Therefore, once SW3 [6] is set to “0”, the output is limited to the lower output
voltages from 0.625 V to 1.975 V with 25 mV increments, as determined by bits SW3[5:0]. Likewise, once bit SW3[6] is set to "1", the
output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV increments, as determined by bits
SW3[5:0].
In order to optimize the performance of the regulator, it is recommended only voltages from 2.00 V to 3.300 V be used in the high range
and the lower range be used for voltages from 0.625 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW3[5:0], SW3STBY[5:0],
and SW3OFF[5:0] bits respectively; however, the initial state of the SW3[6] bit is copied into the SW3STBY[6] and SW3OFF[6] bits.
Therefore, the output voltage range remains the same on all three operating modes. Table 48 shows the output voltage coding valid for
SW3. Table 48 shows the output voltage coding valid for SW3.
Table 48. SW3 output voltage configuration
Low output voltage range(34)
High output voltage range
SW3[6:0]
Set point
SW3[6:0]
SW3 output
Set point
SW3 output
0
1
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.6250
64
65
66
67
68
69
70
71
72
73
74
75
76
77
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
0.8000
0.8500
0.9000
0.9500
1.0000
1.0500
1.1000
1.1500
1.2000
1.2500
1.3000
1.3500
1.4000
1.4500
2
3
4
5
6
7
8
9
10
11
12
13
0.6500
0.6750
0.7000
0.7250
34VR500
NXP Semiconductors
43
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 48. SW3 output voltage configuration (continued)
Low output voltage range(34)
High output voltage range
SW3[6:0]
Set point
SW3[6:0]
SW3 output
Set point
SW3 output
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
78
79
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
2.1000
2.1500
2.2000
2.2500
2.3000
2.3500
2.4000
2.4500
2.5000
2.5500
2.6000
2.6500
2.7000
2.7500
2.8000
2.8500
2.9000
2.9500
3.0000
3.0500
3.1000
3.1500
3.2000
3.2500
3.3000
Reserved
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
34VR500
44
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 48. SW3 output voltage configuration (continued)
Low output voltage range(34)
High output voltage range
Set point
SW3[6:0]
SW3 output
Set point
SW3[6:0]
SW3 output
52
53
54
55
56
57
58
59
60
61
62
63
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
116
117
118
119
120
121
122
123
124
125
126
127
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes
34.
For voltages less than 2.0 V, only use set points 9 to 63.
Table 49 provides a list of registers used to configure and operate SW3. A detailed description on each of these register is provided on
Tables 49 through Table 54.
Table 49. SW3 register summary
Register
SW3VOLT
Address
Output
0x3C
0x3D
0x3E
0x3F
0x40
SW3 Output voltage set point on normal operation
SW3 Output voltage set point on Standby
SW3 Output voltage set point on Sleep
SW3STBY
SW3OFF
SW3MODE
SW3CONF
SW3 Switching mode selector register
SW3 DVS, phase, frequency and ILIM configuration
Table 50. Register SW3VOLT - ADDR 0x3C
Name
Bit #
R/W Default
Description
Sets the SW3 output voltage, during normal operation mode. See
Table 48 for all possible configurations.
SW3
SW3
5:0
R/W
0x00
Sets the operating output voltage range for SW3. Set by OTP. See
Table 48 for all possible configurations.
6
7
R
–
0x00
0x00
UNUSED
UNUSED
Table 51. Register SW3STBY - ADDR 0x3D
Name
SW3STBY
Bit #
R/W Default
Description
Sets the SW3 output voltage, during Standby mode. See Table 48 for all
possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW3 on Standby mode. This
bit inherits the value configured on bit SW3[6] by OTP. See Table 48 for
all possible configurations.
SW3
6
7
R
–
0x00
0x00
UNUSED
UNUSED
34VR500
NXP Semiconductors
45
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 52. Register SW3OFF - ADDR 0x3E
Name
SW3OFF
Bit #
R/W Default
Description
Sets the SW3 output voltage during Sleep mode. See Table 48 for all
possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW3 on Sleep mode. This bit
inherits the value configured on bit SW3[6] by OTP. See Table 48 for all
possible configurations.
SW3
6
7
R
–
0x00
0x00
UNUSED
UNUSED
Table 53. Register SW3MODE - ADDR 0x3F
Name
SW3MODE
Bit #
R/W Default
Description
Sets the SW3 switching operation mode.
See Table 23 for all possible configurations.
3:0
4
R/W
–
0x08
0x00
UNUSED
UNUSED
Set status of SW3 when in Sleep mode.
SW3OMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
Table 54. Register SW3CONF - ADDR 0x40
Name
Bit #
R/W Default
Description
SW3 current limit level selection
0 = High level current limit
1 = Low level current limit
SW3ILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
Unused
SW3FREQ
3:2
5:4
7:6
SW3 switching frequency selector. See Table 29.
SW3 Phase clock selection. See Table 27.
SW3 DVS speed selection. See Table 28.
SW3PHASE
SW3DVSSPEED
6.4.4.15 SW3 external components
Table 55. SW3 external component requirements
Components
Description
SW3 input capacitor
SW3
(35)
CINSW3
2 x 4.7 μF
3 x 22 μF
2 x 0.1 μF
(35)
COSW3
CIN3HF
SW3 output capacitor
(35)
SW3 decoupling input capacitor
1.5 μH
LSW3
SW3 inductor
DCR = 25 mΩ
ISAT = 5.0 A
Notes
35.
Use X5R or X7R capacitors.
34VR500
46
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.16 SW3 specifications
Table 56. SW3 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, V
= 1.5 V, I
= 100 mA,
A
IN
PVIN3
SW3
SW3
V
V
= 1.0 V 4.0%, typical external component values, f
= 2.0 MHz. Typical values are characterized at V = V
= 3.6 V,
VBIAS
SW3
IN
PVIN3
= 1.5 V, I
= 100 mA, and 25 °C, unless otherwise noted.
SW3
SW3
Symbol
Switch mode supply SW3
VPVIN3 Operating Input Voltage
VSW3
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
-
–
4.5
-
V
V
Nominal Output Voltage
Output Voltage Accuracy
Table 48
•
PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3 < 2.5 A
-25
-3.0
-6.0
–
–
–
25
3.0
6.0
mV
%
%
0.625 V < VSW3 < 0.85 V
0.875 V < VSW3 < 1.975 V
2.0 V < VSW3 < 3.3 V
PFM, steady state (2.8 V < VIN < 4.5 V, 0 < ISW3 < 50 mA)
VSW3ACC
•
-65
-45
-45
-3.0
–
–
–
–
65
45
45
3.0
mV
mV
mV
%
0.625 V < VSW3 < 0.675 V
0.7 V < VSW3 < 0.85 V
0.875 V < VSW3 < 1.975 V
2.0 V < VSW3 < 3.3 V
Rated Output Load Current
(36)
•
2.8 V < VIN < 4.5 V, 0.625 V < VSW3 < 3.3 V
PWM, APS mode
ISW3
mA
A
–
–
2500
Current Limiter Peak Current Detection
•
Current through inductor
SW3ILIM = 0
ISW3LIM
3.5
2.7
5.0
3.8
6.5
4.9
SW3ILIM = 1
Start-up Overshoot
VSW3OSH
–
–
–
–
66
mV
µs
ISW3 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN3 = 4.5 V
Turn-on Time
tONSW3
Enable to 90% of end value
500
ISW3 = 0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN3 = 4.5 V
Switching Frequency
SW3FREQ[1:0] = 00
SW3FREQ[1:0] = 01
SW3FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW3
MHz
Notes
36.
The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW3 - VSW3) = ISW3* (DCR of inductor +RONSW3xP + PCB trace resistance).
34VR500
NXP Semiconductors
47
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 56. SW3 electrical characteristics (continued)
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, V
= 1.5 V, I
= 100 mA,
A
IN
PVIN3
SW3
SW3
V
V
= 1.0 V 4.0%, typical external component values, f
= 2.0 MHz. Typical values are characterized at V = V
= 3.6 V,
VBIAS
SW3
IN
PVIN3
= 1.5 V, I
= 100 mA, and 25 °C, unless otherwise noted.
SW3
SW3
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW3 (continued)
Efficiency
•
fSW3 = 2.0 MHz, LSW3 1.0 μH
–
–
–
–
–
–
84
85
85
84
80
74
–
–
–
–
–
–
PFM, 1.5 V, 1.0 mA
PFM, 1.5 V, 50 mA
APS, PWM 1.5 V, 500 mA
APS, PWM 1.5 V, 750 mA
APS, PWM 1.5 V, 1250 mA
APS, PWM 1.5 V, 2500 mA
ηSW3
%
ΔVSW3
VSW3LIR
VSW3LOR
Output Ripple
–
–
–
5.0
–
–
mV
mV
mV
Line Regulation (APS, PWM)
DC Load Regulation (APS, PWM)
Transient Load Regulation
20
20
–
•
Transient Load = 0.0 mA to 1.25 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW3LOTR
mV
–
–
–
–
50
50
Quiescent Current
PFM Mode
ISW3Q
–
–
22
300
–
–
µA
APS Mode
SW3 P-MOSFET RDSON
at VIN = VPVIN3 = 3.3 V
RONSW3P
–
mΩ
108
123
SW3 N-MOSFET RDSON
at VIN = VPVIN3 = 3.3 V
RONSW3N
RSW3DIS
–
–
mΩ
129
600
163
–
Discharge Resistance
Ω
Figure 19. SW3 efficiency waveforms
34VR500
48
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 20. Load transient response – SW3 (PWM)
6.4.4.17 SW4
SW4 operates by default in VTT mode (for the 34VR500V1, V3, V4, V5, V6, V7) and it's not possible to change this configuration and
modify the output voltage after the Start-up sequence. SW4 operates in non VTT mode for the 34VR500V2 and it is possible to change
2
the output voltage by the I C bus.
SW4 is a 1.0 A rated buck regulator capable of operating in two modes. In Regulator mode, it operates as a normal buck regulator with a
programmable output between 0.625 and 1.975 V. It is capable of operating in the three available switching modes: PFM, APS, and PWM,
described on Table 23 and configured by the SW4MODE[3:0] bits, as shown in Table 24.
If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage will track the
output voltage of SW3, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The minimum output
voltage for SW4 in VTT mode is 0.6 V
Figure 21 shows the block diagram and the external component connections for the SW4 regulator.
PVIN4
PVIN4
SW4MODE
ISENSE
CINSW4
Controller
SW4
LX4
EP
Driver
LSW4
COSW4
SW4FAULT
I2C
Interface
Internal
I2C
Compensation
Z2
FB4
Z1
VREF
EA
DAC
Figure 21. SW4 block diagram
34VR500
NXP Semiconductors
49
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.18 SW4 setup and control registers
In Regulator mode, the SW4 output voltage is programmable from 0.625 to 1.975 V.
The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW4[5:0], SW4STBY[5:0],
and SW4OFF[5:0] bits, respectively. Table 57 shows the output voltage coding valid for SW4.
Table 57. SW4 output voltage configuration
Set Point
SW4[5:0]
SW4 Output
Set Point
SW4[5:0]
SW4 Output
9
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
0.6250
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
2
Full setup and control of SW4 is done through the I C registers listed on Table 58, and a detailed description of each one of the registers
is provided in Tables 59 to Table 63.
34VR500
50
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 58. SW4 register summary
Register
SW4VOLT
Address
Description
0x4A
0x4B
0x4C
0x4D
0x4E
Output voltage set point on normal operation
SW4STBY
SW4OFF
Output voltage set point on Standby
Output voltage set point on Sleep
SW4MODE
SW4CONF
Switching mode selector register
DVS, phase, frequency and ILIM configuration
Table 59. Register SW4VOLT - ADDR 0x4A
Name
Bit #
R/W Default
Description
Sets the SW4 output voltage during normal operation mode. See Table 57
for all possible configurations.
SW4
UNUSED
5:0
7
R/W
–
0x00
0x00
UNUSED
Table 60. Register SW4STBY - ADDR 0x4B
Name
SW4STBY
UNUSED
Bit #
R/W Default
Description
Sets the SW4 output voltage during Standby mode. See Table 57 for all
possible configurations.
5:0
7
R/W
–
0x00
0x00
UNUSED
Table 61. Register SW4OFF - ADDR 0x4C
Name
SW4OFF
UNUSED
Bit #
R/W Default
Description
Sets the SW4 output voltage during Sleep mode. See Table 57 for all
possible configurations.
5:0
7
R/W
–
0x00
0x00
UNUSED
Table 62. Register SW4MODE - ADDR 0x4D
Name
SW4MODE
Bit #
R/W Default
Description
Sets the SW4 switching operation mode. See Table 23 for all possible
configurations.
3:0
4
R/W
–
0x08
0x00
UNUSED
UNUSED
Set status of SW4 when in Sleep mode
SW4OMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
34VR500
NXP Semiconductors
51
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 63. Register SW4CONF - ADDR 0x4E
Name
Bit #
R/W Default
Description
SW4 current limit level selection
SW4ILIM
0
R/W
0x00
0 = High level Current limit
1 = Low level Current limit
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
Unused
SW4FREQ
3:2
5:4
7:6
SW4 switching frequency selector. See Table 29.
SW4 Phase clock selection. See Table 27.
SW4 DVS speed selection. See Table 28.
SW4PHASE
SW4DVSSPEED
6.4.4.19 SW4 external components
Table 64. SW4 external component recommendations
Components
Description
SW4 Input capacitor
Values
(37)
CINSW4
4.7 μF
0.1 μF
(37)
CIN4HF
SW4 Decoupling input capacitor
SW4 Output capacitor
(37)
COSW4
3 x 22 μF
1.5 μH
LSW4
SW4 Inductor
DCR = 50 mΩ
ISAT = 2.6 A
Notes
37.
Use X5R or X7R capacitors.
6.4.4.20 SW4 specifications
Table 65. SW4 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, V
= 1.8 V, I
= 100 mA,
A
IN
PVIN4
SW4
SW4
V
V
= 1.0 V 4.0%, typical external component values, f
= 2.0 MHz, unless otherwise noted. Typical values are characterized at
VBIAS
SW4
= V
= 3.6 V, V
= 1.8 V, I
= 100 mA, and 25 °C, unless otherwise noted.
IN
PVIN4
SW4
SW4
Symbol
Switch mode supply SW4
Parameter
Min.
Typ.
Max.
Unit
Notes
VPVIN4
Operating Input Voltage
2.8
–
4.5
V
V
Nominal Output Voltage
Normal operation
VTT Mode
VSW4
–
–
Table 57
VSW3/2
–
–
Output Voltage Accuracy
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A
0.625 V < VSW4 < 0.85 V
0.875 V < VSW4 < 1.975 V
-25
-3.0
–
–
25
3.0
mV
%
•
PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA
VSW4ACC
-65
-45
-45
–
–
–
65
45
45
mV
mV
mV
0.625 V < VSW4 < 0.675 V
0.7 V < VSW4 < 0.85 V
0.875 V < VSW4 < 1.975 V
-40
–
–
–
40
mV
mA
•
VTT Mode, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A
Rated Output Load Current
ISW4
1000
2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 1.975 V
34VR500
52
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 65. SW4 electrical characteristics (continued)
All parameters are specified at T = -40 to 105 °C (See Table 3), V = V
= 3.6 V, V
= 1.8 V, I
= 100 mA,
A
IN
PVIN4
SW4
SW4
V
V
= 1.0 V 4.0%, typical external component values, f
= 2.0 MHz, unless otherwise noted. Typical values are characterized at
VBIAS
SW4
= V
= 3.6 V, V
= 1.8 V, I
= 100 mA, and 25 °C, unless otherwise noted.
IN
PVIN4
SW4
SW4
Symbol
Switch mode supply SW4 (continued)
Parameter
Min.
Typ.
Max.
Unit
Notes
Current Limiter Peak Current Detection
Current through inductor
SW4ILIM = 0
ISW4LIM
A
1.4
1.0
2.0
1.5
3.0
2.4
SW4ILIM = 1
Start-up Overshoot
VSW4OSH
–
–
–
–
66
mV
µs
ISW4 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN4 = 4.5 V
Turn-on Time
tONSW4
Enable to 90% of end value
500
ISW4 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN4 = 4.5 V
Switching Frequency
SW4FREQ[1:0] = 00
SW4FREQ[1:0] = 01
SW4FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW4
MHz
Efficiency
•
fSW4 = 2.0 MHz, LSW4 = 1.0 μH
–
–
–
–
–
81
78
87
88
83
–
–
–
–
–
PFM, 1.8 V, 1.0 mA
PFM, 1.8 V, 50 mA
APS, PWM 1.8 V, 200 mA
APS, PWM 1.8 V, 500 mA
APS, PWM 1.8 V, 1000 mA
ηSW4
%
–
–
–
78
76
66
–
–
–
PWM 0.75 V, 200 mA
PWM 0.75 V, 500 mA
PWM 0.75 V, 1000 mA
ΔVSW4
VSW4LIR
VSW4LOR
Output Ripple
–
–
–
5.0
–
–
mV
mV
mV
Line Regulation (APS, PWM)
DC Load Regulation (APS, PWM)
Transient Load Regulation
20
20
–
•
Transient Load = 0.0 mA to 500 mA, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW4LOTR
–
–
–
–
mV
50
50
Quiescent Current
PFM Mode
ISW4Q
–
–
22
145
–
–
µA
APS Mode
SW4 P-MOSFET RDSON
at VIN = VPVIN4 = 3.3 V
RONSW4P
–
236
274
mΩ
SW4 N-MOSFET RDSON
at VIN = VPVIN4 = 3.3 V
RONSW4N
RSW4DIS
–
–
293
600
378
–
mΩ
Discharge Resistance
Ω
34VR500
NXP Semiconductors
53
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 22. SW4 efficiency waveforms
Figure 23. Load transient response – SW4 (PWM)
6.4.5 LDO regulators description
This section describes the LDO regulators provided by the 34VR500. All regulators use the main bandgap as reference. Refer to Bias and
references block description section for further information on the internal reference voltages.
A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest
bias currents may be attained by forcing the part into its Low Power mode by setting the LDOxLPWR bit. The use of this bit is only
recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded.
When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when PORB is low.
34VR500
54
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VLDOINx
VLDOINx
VREF
_
+
LDOx
LDOxLPWR
LDOx
LDOx
I2C
Interface
CLDOx
LDOx
Discharge
Figure 24. General LDO block diagram
6.4.5.1
Transient response waveforms
Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 25. Note that the transient
line and load response refers to the overshoot, or undershoot only, excluding the DC shift.
34VR500
NXP Semiconductors
55
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
IMAX
ILOAD
IMAX/10
1.0 us
1.0 us
Transient Load Stimulus
IL = IMAX/10
IL = IMAX
Overshoot
VOUT
Undershoot
VOUT Transient Load Response
VINx_INITIAL
VINx
VINx_FINAL
10 us
10 us
Transient Line Stimulus
VINx_FINAL
VINx_INITIAL
Overshoot
VOUT
Undershoot
VOUT Transient Line Response
Figure 25. Transient waveforms
34VR500
56
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.2
Short-circuit protection
All general purpose LDOs have short-circuit protection capability. The Short-circuit Protection (SCP) system includes debounced fault
condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product
damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its LDOxEN bit, while at the same time, an interrupt
LDOxFAULTI will be generated to flag the fault to the system processor. The LDOxFAULTI interrupt is maskable through the
LDOxFAULTM mask bit.
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators will not automatically be disabled upon a
short-circuit detection. However, the current limiter will continue to limit the output current of the regulator. By default, the REGSCPEN is
not set; therefore, at start-up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, LDOxFAULTI, will
be generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 66 for SCP behavior configuration.
Table 66. Short-circuit behavior
REGSCPEN[0]
Short-circuit Behavior
0
1
Current limit
Shutdown
6.4.5.3
LDO regulator control
Each LDO is fully controlled through its respective LDOxCTL register. This register enables the user to set the LDO output voltage
according to Table 67 for LDO1 and uses the voltage set point on Table 68 for LDO2 through LDO5.
Table 67. LDO1 output voltage configuration
Set point
LDO1[3:0]
LDO1 output (V)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.800
0.850
0.900
0.950
1.000
1.050
1.100
1.150
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 68. LDO2/3/4/5 output voltage configuration
Set point
LDOx[3:0]
LDOx output (V)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as
2
programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I C bits for this. Table 69
presents a summary of all valid combinations of the control bits on LDOxCTL register and the expected behavior of the LDO output.
Table 69. LDO control
LDOxEN
LDOxLPWR
LDOxSTBY
STANDBY(38)
LDOxOUT
0
1
1
1
1
1
X
0
1
X
0
1
X
0
0
1
1
1
X
X
X
0
Off
On
Low Power
On
1
Off
1
Low Power
Notes
38.
STANDBY refers to a Standby event as described earlier.
For more detail information, Table 70 through Table 74 provide a description of all registers necessary to operate all five general purpose
LDO regulators.
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Table 70. Register LDO1CTL - ADDR 0x6D
Name
Bit #
R/W Default
Description
LDO1
3:0
R/W
–
0x80
0x00
Sets LDO1 output voltage. See Table 67 for all possible configurations.
Enables or Disables LDO1 output
LDO1EN
4
0 = OFF
1 = ON
LDO1STBY
LDO1LPWR
UNUSED
5
6
7
R/W
R/W
–
0x00
0x00
0x00
Set LDO1 output state when in Standby. Refer to Table 69.
Enable Low Power Mode for LDO1. Refer to Table 69.
UNUSED
Table 71. Register LDO2CTL - ADDR 0x6E
Name
Bit #
R/W Default
Description
LDO2
3:0
R/W
–
0x80
0x00
Sets LDO2 output voltage. See Table 68 for all possible configurations.
Enables or Disables LDO2 output
LDO2EN
4
0 = OFF
1 = ON
LDO2STBY
LDO2LPWR
UNUSED
5
6
7
R/W
R/W
–
0x00
0x00
0x00
Set LDO2 output state when in Standby. Refer to Table 69.
Enable Low Power Mode for LDO2. Refer to Table 69.
UNUSED
Table 72. Register LDO3CTL - ADDR 0x6F
Name
Bit #
R/W Default
Description
LDO3
3:0
R/W
0x80
Sets LDO3 output voltage. See Table 68 for all possible configurations.
Enables or Disables LDO3 output
LDO3EN
4
–
0x00
0 = OFF
1 = ON
LDO3STBY
LDO3LPWR
UNUSED
5
6
7
R/W
R/W
–
0x00
0x00
0x00
Set LDO3 output state when in Standby. Refer to Table 69.
Enable Low Power Mode for LDO3. Refer to Table 69.
UNUSED
Table 73. Register LDO4CTL - ADDR 0x70
Name
Bit #
R/W Default
Description
LDO4
3:0
R/W
0x80
Sets LDO4 output voltage. See Table 68 for all possible configurations.
Enables or Disables LDO4 output
LDO4EN
4
–
0x00
0 = OFF
1 = ON
LDO4STBY
LDO4LPWR
UNUSED
5
6
7
R/W
R/W
–
0x00
0x00
0x00
Set LDO4 output state when in Standby. Refer to Table 69.
Enable Low Power Mode for LDO4. Refer to Table 69.
UNUSED
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 74. Register LDO5CTL - ADDR 0x71
Name
Bit #
R/W Default
Description
LDO5
3:0
R/W
–
0x80
0x00
Sets LDO5 output voltage. See Table 68 for all possible configurations.
Enables or Disables LDO5 output
LDO5EN
4
0 = OFF
1 = ON
LDO5STBY
LDO5LPWR
UNUSED
5
6
7
R/W
R/W
–
0x00
0x00
0x00
Set LDO5 output state when in Standby. Refer to Table 69.
Enable Low Power Mode for LDO5. Refer to Table 69.
UNUSED
6.4.5.4
External components
Table 75 lists the typical component values for the general purpose LDO regulators.
Table 75. LDO external components
Regulator
Output capacitor (μF)(39)
LDO1
LDO2
LDO3
LDO4
LDO5
4.7
2.2
4.7
2.2
2.2
Notes
39.
Use X5R/X7R ceramic capacitors.
6.4.5.5
LDO specifications
LDO1
6.4.5.5.1
Table 76. LDO1 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.0 V, VLDO1[3:0] = 1111, I = 10 mA,
LDO1
A
IN
LDOIN1
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.0 V, LDO1[3:0] = 1111, I
= 10 mA and 25 °C, unless otherwise noted.
LDOIN1
LDO1
Symbol
LDO1
VLDOIN1
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
Nominal Output Voltage
Operating Load Current
1.75
–
–
Table 67
–
3.40
–
V
V
LDO1NOM
ILDO1
0.0
250
mA
LDO1 active mode - DC
Output Voltage Tolerance
VLDO1TOL
1.75 V <VLDOIN1 < 3.4 V, 0.0 mA < ILDO1 < 250 mA
LDO1[3:0] = 0000 to 1111
-3.0
–
–
3.0
–
%
Load Regulation
VLDO1LOR
(VLDO1 at ILDO1 = 250 mA) - (VLDO1 at ILDO2 = 0.0 mA)
For any 1.75 V <VLDOIN1 < 3.4 V
0.05
0.50
mV/mA
mV/V
Line Regulation
VLDO1LIR
(VLDO1 at VLDOIN1 = 3.4 V) - (VLDO1 at VLDOIN1 = 1.75 V)
For any 0.0 mA < ILDO1 < 250 mA
–
–
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Table 76. LDO1 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.0 V, VLDO1[3:0] = 1111, I = 10 mA,
LDO1
A
IN
LDOIN1
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.0 V, LDO1[3:0] = 1111, I
= 10 mA and 25 °C, unless otherwise noted.
LDOIN1
LDO1
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
LDO1 active mode - DC (continued)
Current Limit
ILDO1LIM
mA
mA
ILDO1 when LDO1 is forced to LDO1NOM/2
305
290
–
417
–
510
500
–
Overcurrent Protection Threshold
ILDO1OCP
ILDO1 required to cause the SCP function to disable LDO when
REGSCPEN = 1
Quiescent Current
ILDO1Q
No load, Change in IVIN and IVLDOIN1
When LDO1 enabled
16
μA
LDO1 AC and transient
PSRR
•
ILDO1 = 187.5 mA, 20 Hz to 20 kHz
(40)
PSRRLDO1
dB
50
37
60
45
–
–
LDO1[3:0] = 0000 - 1101
LDO1[3:0] = 1110, 1111
Output Noise Density
•
VLDOIN1 = 1.75 V, ILDO1 = 187.5 mA
NOISELDO1
–
–
–
-108
-118
-124
-100
-108
-112
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-On Slew Rate
•
10% to 90% of end value
•
1.75 V ≤ VLDOIN1 ≤ 3.4 V, ILDO1 = 0.0 mA
LDO1[3:0] = 0000 to 0111
LDO1[3:0] = 1000 to 1111
SLWRLDO1
mV/μs
μs
–
–
–
–
12.5
16.5
Turn-On Time
Enable to 90% of end value, VLDOIN1 = 1.75 V, 3.4 V
ILDO1 = 0.0 mA
tONLDO1
60
–
500
Turn-Off Time
tOFFLDO1
Disable to 10% of initial value, VLDOIN1 = 1.75 V
ILDO1 = 0.0 mA
–
–
–
10
ms
%
Start-up Overshoot
LDO1OSHT
1.0
2.0
VLDOIN1 = 1.75 V, 3.4 V, ILDO1 = 0.0 mA
Transient Load Response
VLDOIN1 = 1.75 V, 3.4 V
VLDO1LOTR
ILDO1 = 25 to 250 mA in 1.0 μs
Peak of overshoot or undershoot of LDO1 with respect to final value
Refer to Figure 25
–
–
–
3.0
8.0
%
Transient Line Response
ILDO1 = 187.5 mA
VLDOIN1INITIAL = 1.75 V to VLDOIN1 = 2.25 V for
LDO1[3:0] = 0000 to 1101
VLDO1LITR
5.0
mV
VLDOIN1INITIAL = VLDO1+0.3 V to VLDOIN1FINAL = VLDO1+0.8 V for
LDO1[3:0] = 1110, 1111
Refer to Figure 25
Notes
40.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.5.2
LDO2
Table 77. LDO2 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, VLDO2[3:0] = 1111, I = 10 mA,
LDO2
A
IN
LDOIN23
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO2[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN23
LDO2
Symbol
LDO2
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
1.8 V ≤ LDO2NOM ≤ 2.5 V
2.6 V ≤ LDO2NOM ≤ 3.3 V
2.8
LDO2NOM
0.250
(41)
VLDOIN23
–
–
3.6
3.6
V
+
LDO2NOM
ILDO2
Nominal Output Voltage
Operating Load Current
–
Table 68
–
–
V
0.0
100
mA
LDO2 DC
Output Voltage Tolerance
VLDOIN23MIN < VLDOIN23 < 3.6 V
0.0 mA < ILDO2 < 100 mA
LDO2[3:0] = 0000 to 1111
VLDO2TOL
-3.0
–
–
3.0
–
%
Load Regulation
VLDO2LOR
(VLDO2 at ILDO2 = 100 mA) - (VLDO2 at ILDO2 = 0.0 mA)
For any VLDOIN23MIN < VLDOIN23 < 3.6 V
0.07
mV/mA
Line Regulation
VLDO2LIR
ILDO2LIM
ILDO2OCP
(VLDO2 at VLDOIN23 = 3.6 V) - (VLDO2 at VLDOIN23MIN
For any 0.0 mA < ILDO2 < 100 mA
)
–
0.8
167
–
–
mV/V
mA
Current Limit
127
120
200
200
ILDO2 when LDO2 is forced to LDO2NOM/2
Overcurrent Protection Threshold
mA
ILDO2 required to cause the SCP function to disable LDO when
REGSCPEN = 1
Quiescent Current
ILDO2Q
No load, Change in IVIN and IVLDOIN23
When LDO2 enabled
–
13
–
μA
LDO2 AC and transient
PSRR
•
ILDO2 = 75 mA, 20 Hz to 20 kHz
(42)
PSRRLDO2
dB
35
55
40
60
–
–
LDO2[3:0] = 0000 - 1110, VLDOIN23 = VLDOIN23MIN + 100 mV
LDO2[3:0] = 0000 - 1000, VLDOIN23 = LDO2NOM + 1.0 V
Output Noise Density
•
VLDOIN23 = VLDOIN23MIN, ILDO2 = 75 mA
NOISELDO2
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-On Slew Rate
•
10% to 90% of end value
•
VLDOIN23MIN ≤ VLDOIN23 ≤ 3.6 V, ILDO2 = 0.0 mA
SLWRLDO2
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
LDO2[3:0] = 0000 to 0011
LDO2[3:0] = 0100 to 0111
LDO2[3:0] = 1000 to 1011
LDO2[3:0] = 1100 to 1111
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Table 77. LDO2 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, VLDO2[3:0] = 1111, I = 10 mA,
LDO2
A
IN
LDOIN23
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO2[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN23
LDO2
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
LDO2 AC and transient (continued)
Turn-On Time
tONLDO2
Enable to 90% of end value, VLDOIN23 = VLDOIN23MIN, 3.6 V
ILDO2 = 0.0 mA
60
–
500
μs
Turn-Off Time
tOFFLDO2
Disable to 10% of initial value, VLDOIN23 = VLDOIN23MIN
ILDO2 = 0.0 mA
–
–
–
10
ms
%
Start-up Overshoot
LDO2OSHT
1.0
2.0
VLDOIN23 = VLDOIN23MIN, 3.6 V, ILDO2 = 0.0 mA
Transient Load Response
VLDOIN23 = VLDOIN23MIN, 3.6 V
ILDO2 = 10 to 100 mA in 1.0μs
Peak of overshoot or undershoot of LDO2 with respect to final
value. Refer to Figure 25
VLDO2LOTR
–
–
3.0
8.0
%
Transient Line Response
ILDO2 = 75 mA
VLDOIN23INITIAL = 2.8 V to VLDOIN23FINAL = 3.3 V for
LDO2[3:0] = 0000 to 0111
VLDO2LITR
–
5.0
mV
V
LDOIN23INITIAL = VLDO2+0.3 V to VLDOIN23FINAL = VLDO2+0.8 V for
LDO2[3:0] = 1000 to 1010
LDOIN23INITIAL = VLDO2+0.25 V to VLDOIN23FINAL = 3.6 V for
V
LDO2[3:0] = 1011 to 1111
Refer to Figure 25
Notes
41.
When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
42.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VLDOIN23MIN refers to the minimum allowed input voltage for a particular output voltage.
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.5.3
LDO3
Table 78. LDO3 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, LDO3[3:0] = 1111, I = 10 mA,
LDO3
A
IN
LDOIN23
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO3[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN23
LDO3
Symbol
LDO3
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
2.8
LDO3NOM
0.250
(43)
VLDOIN23
1.8 V ≤ LDO3NOM ≤ 2.5 V
2.6 V ≤ LDO3NOM ≤ 3.3 V
–
–
3.6
3.6
V
+
LDO3NOM
ILDO3
Nominal Output Voltage
Operating Load Current
–
Table 68
–
–
V
0.0
350
mA
LDO3 DC
Output Voltage Tolerance
VLDOIN23MIN < VLDOIN23 < 3.6 V
0.0 mA < ILDO3 < 350 mA
LDO3[3:0] = 0000 to 1111
VLDO3TOL
-3.0
–
–
3.0
–
%
Load Regulation
VLDO3LOR
(VLDO3 at ILDO3 = 350 mA) - (VLDO3 at ILDO3 = 0.0 mA)
For any VLDOIN23MIN < VLDOIN23 < 3.6 V
0.07
mV/mA
Line Regulation
VLDO3LIR
ILDO3LIM
ILDO3OCP
(VLDO3 at 3.6 V) - (VLDO3 at VLDOIN23MIN
For any 0.0 mA < ILDO3 < 350 mA
)
–
0.80
584.5
–
–
mV/V
mA
Current Limit
435
420
700
700
ILDO3 when LDO3 is forced to LDO3NOM/2
Overcurrent Protection Threshold
mA
ILDO3 required to cause the SCP function to disable LDO when
REGSCPEN = 1
Quiescent Current
ILDO3Q
No load, Change in IVIN and IVLDOIN23
When LDO3 enabled
–
13
–
μA
LDO3 AC and transient
PSRR
•
ILDO3 = 262.5 mA, 20 Hz to 20 kHz
(44)
PSRRLDO3
dB
35
55
40
60
–
–
LDO3[3:0] = 0000 - 1110, VLDOIN23 = VLDOIN23MIN + 100 mV
LDO3[3:0] = 0000 - 1000, VLDOIN23 = LDO3NOM + 1.0 V
Output Noise Density
•
VLDOIN23 = VLDOIN23MIN, ILDO3 = 262.5 mA
NOISELDO3
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-On Slew Rate
•
10% to 90% of end value
•
VLDOIN23MIN ≤ VLDOIN23 ≤ 3.6 V, ILDO3 = 0.0 mA
SLWRLDO3
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
LDO3[3:0] = 0000 to 0011
LDO3[3:0] = 0100 to 0111
LDO3[3:0] = 1000 to 1011
LDO3[3:0] = 1100 to 1111
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Table 78. LDO3 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, LDO3[3:0] = 1111, I = 10 mA,
LDO3
A
IN
LDOIN23
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO3[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN23
LDO3
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
LDO3 AC and transient (continued)
Turn-On Time
tONLDO3
Enable to 90% of end value, VLDOIN23 = VLDOIN23MIN, 3.6 V
ILDO3 = 0.0 mA
60
–
500
μs
Turn-Off Time
tOFFLDO3
Disable to 10% of initial value, VLDOIN23 = VLDOIN23MIN
ILDO3 = 0.0 mA
–
–
–
10
ms
%
Start-up Overshoot
LDO3OSHT
1.0
2.0
VLDOIN23 = VLDOIN23MIN, 3.6 V, ILDO3 = 0.0 mA
Transient Load Response
VLDOIN23 = VLDOIN23MIN, 3.6 V
ILDO3 = 35 to 350 mA in 1.0 μs
Peak of overshoot or undershoot of LDO3 with respect to final
value. Refer to Figure 25
VLDO3LOTR
–
–
3.0
8.0
%
Transient Line Response
ILDO3 = 262.5 mA
VLDOIN23INITIAL = 2.8 V to VLDOIN23FINAL = 3.3 V for
LDO3[3:0] = 0000 to 0111
VLDO3LITR
–
5.0
mV
V
LDOIN23INITIAL = VLDO3+0.3 V to VLDOIN23FINAL = VLDO3+0.8 V
for LDO3[3:0] = 1000 to 1010
LDOIN23INITIAL = VLDO3+0.25 V to VLDOIN23FINAL = 3.6 V for
V
LDO3[3:0] = 1011 to 1111
Refer to Figure 25
Notes
43.
When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
44.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VLDOIN23MIN refers to the minimum allowed input voltage for a particular output voltage.
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65
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.5.4
LDO4
Table 79. LDO4 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, LDO4[3:0] = 1111, I = 10 mA,
LDO4
A
IN
LDOIN45
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO4[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN45
LDO4
Symbol
LDO4
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
–
–
4.5
4.5
2.8
LDO4NOM
0.250
(45)
VLDOIN45
1.8 V ≤ LDO4NOM ≤ 2.5 V
2.6 V ≤ LDO4NOM ≤ 3.3 V
V
+
LDO4NOM
ILDO4
Nominal Output Voltage
Operating Load Current
–
Table 68
–
–
V
0.0
100
mA
LDO4 active mode – DC
Output Voltage Tolerance
VLDO4TOL
VLDOIN45MIN < VLDOIN45 < 4.5 V
0.0 mA < ILDO4 < 100 mA, LDO4[3:0] = 0000 to 1111
-3.0
–
–
3.0
–
%
Load Regulation
VLDO4LOR
(VLDO4 at ILDO4 = 100 mA) - (VLDO4 at ILDO4 = 0.0 mA)
For any VLDOIN45MIN < VLDOIN45 < 4.5 mV
0.10
mV/mA
Line Regulation
VLDO4LIR
ILDO4LIM
ILDO4OCP
(VLDO4 at VLDOIN45 = 4.5 V) - (VLDO4 at VLDOIN45MIN
For any 0.0 mA < ILDO4 < 100 mA
)
–
0.50
167
–
–
mV/V
mA
Current Limit
122
120
200
200
ILDO4 when LDO4 is forced to LDO4NOM/2
Overcurrent Protection threshold
mA
ILDO4 required to cause the SCP function to disable LDO when
REGSCPEN = 1
Quiescent Current
ILDO4Q
No load, Change in IVIN and IVLDOIN45
When LDO4 enabled
–
13
–
μA
LDO4 AC and transient
PSRR
•
ILDO4 = 75 mA, 20 Hz to 20 kHz
(46)
PSRRLDO4
dB
35
52
40
60
–
–
LDO4[3:0] = 0000 - 1111, VLDOIN45 = VLDOIN45MIN + 100 mV
LDO4[3:0] = 0000 - 1111, VLDOIN45 = LDO4NOM + 1.0 V
Output Noise Density
•
VLDOIN45 = VLDOIN45MIN, ILDO4 = 75 mA
NOISELDO4
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-On Slew Rate
•
10% to 90% of end value
•
VLDOIN45MIN ≤ VLDOIN45 ≤ 4.5 mV, ILDO4 = 0.0 mA
SLWRLDO4
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
LDO4[3:0] = 0000 to 0011
LDO4[3:0] = 0100 to 0111
LDO4[3:0] = 1000 to 1011
LDO4[3:0] = 1100 to 1111
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66
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 79. LDO4 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, LDO4[3:0] = 1111, I = 10 mA,
LDO4
A
IN
LDOIN45
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO4[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN45
LDO4
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
LDO4 active mode – DC (continued)
Turn-On Time
tONLDO4
Enable to 90% of end value, VLDOIN45 = VLDOIN45MIN, 4.5 V
ILDO4 = 0.0 mA
60
–
500
μs
Turn-Off Time
tOFFLDO4
Disable to 10% of initial value, VLDOIN45 = VLDOIN45MIN
ILDO4 = 0.0 mA
–
–
–
10
ms
%
Start-Up Overshoot
LDO4OSHT
1.0
2.0
VLDOIN45 = VLDOIN45MIN, 4.5 V, ILDO4 = 0.0 mA
Transient Load Response
VLDOIN45 = VLDOIN45MIN, 4.5 V
ILDO4 = 10 to 100 mA in 1.0 μs
Peak of overshoot or undershoot of LDO4 with respect to final
value.
VLDO4LOTR
–
–
3.0
8.0
%
Refer to Figure 25
Transient Line Response
ILDO4 = 75 mA
VLDOIN45INITIAL = 2.8 V to VLDOIN45FINAL = 3.3 V for
LDO4[3:0] = 0000 to 0111
VLDO4LITR
-
5.0
mV
VLDOIN45INITIAL = VLDO4+0.3 V to VLDOIN45FINAL = VLDO4+0.8 V
for LDO4[3:0] = 1000 to 1111
Refer to Figure 25
Notes
45.
When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
46.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VLDOIN45MIN refers to the minimum allowed input voltage for a particular output voltage.
34VR500
NXP Semiconductors
67
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.5.5
LDO5
Table 80. LDO5 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, LDO5[3:0] = 1111, I = 10 mA,
LDO5
A
IN
LDOIN45
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO5[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN45
LDO5
Symbol
LDO5
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
1.8 V ≤ LDO5NOM ≤ 2.5 V
2.6 V ≤ LDO5NOM ≤ 3.3 V
2.8
LDO5NOM
0.250
–
–
4.5
4.5
(47)
VLDOIN45
V
+
LDO5NOM
ILDO5
Nominal Output Voltage
Operating Load Current
–
Table 68
–
–
V
0.0
200
mA
LDO5 DC
Output Voltage Tolerance
VLDO5TOL
VLDOIN45MIN < VLDOIN45 < 4.5 V, 0.0 mA < ILDO5 < 200 mA
LDO5[3:0] = 0000 to 1111
-3.0
–
–
3.0
–
%
Load Regulation
VLDO5LOR
(VLDO5 at ILDO5 = 200 mA) - (VLDO5 at ILDO5 = 0.0 mA)
For any VLDOIN45MIN < VLDOIN45 < 4.5 V
0.10
0.50
333
mV/mA
Line Regulation
VLDO5LIR
ILDO5LIM
ILDO5OCP
ILDO5Q
(VLDO5 at VLDOIN45 = 4.5 V) - (VLDO5 at VLDOIN45MIN
For any 0.0 mA < ILDO5 < 200 mA
)
–
–
mV/V
mA
Current Limit
ILDO5 when LDO5 is forced to LDO5NOM/2
232
475
Over Current Protection Threshold
mA
ILDO5 required to cause the SCP function to disable LDO when
REGSCPEN = 1
220
–
–
475
–
Quiescent Current
13
μA
No load, Change in IVIN and IVLDOIN45, When LDO5 enabled
LDO5 AC and transient
PSRR
•
ILDO5 = 150 mA, 20 Hz to 20 kHz
(48)
PSRRLDO5
dB
35
52
40
60
–
–
LDO5[3:0] = 0000 - 1111, VLDOIN45 = VLDOIN45MIN + 100 mV
LDO5[3:0] = 0000 - 1111, VLDOIN45 = LDO5NOM + 1.0 V
Output Noise Density
•
VLDOIN45 = VLDOIN45MIN, ILDO5 = 150 mA
NOISELDO5
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-On Slew Rate
•
10% to 90% of end value
•
VLDOIN45MIN ≤ VLDOIN45 ≤ 4.5 V. ILDO5 = 0.0 mA
SLWRLDO5
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
LDO5[3:0] = 0000 to 0011
LDO5[3:0] = 0100 to 0111
LDO5[3:0] = 1000 to 1011
LDO5[3:0] = 1100 to 1111
34VR500
68
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 80. LDO5 electrical characteristics
All parameters are specified at T = -40 to 105 °C (See Table 3), V = 3.6 V, V
= 3.6 V, LDO5[3:0] = 1111, I = 10 mA,
LDO5
A
IN
LDOIN45
V
V
= 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at V = 3.6 V,
VBIAS
IN
= 3.6 V, LDO5[3:0] = 1111, I
= 10 mA, and 25 °C, unless otherwise noted.
LDOIN45
LDO5
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
LDO5 AC and transient (continued)
Turn-On Time
tONLDO5
Enable to 90% of end value, VLDOIN45 = VLDOIN45MIN, 4.5 V
ILDO5 = 0.0 mA
60
–
500
μs
Turn-Off Time
tOFFLDO5
Disable to 10% of initial value, VLDOIN45 = VLDOIN45MIN
ILDO5 = 0.0 mA
–
–
–
10
ms
%
Start-Up Overshoot
LDO5OSHT
1.0
2.0
VLDOIN45 = VLDOIN45MIN, 4.5 V, ILDO5 = 0 mA
Transient Load Response
VLDOIN45 = VLDOIN45MIN, 4.5 V
ILDO5 = 20 to 200 mA in 1.0 μs
Peak of overshoot or undershoot of LDO5 with respect to final
value. Refer to Figure 25
VLDO5LOTR
–
–
–
3.0
8.0
%
Transient Line Response
ILDO5 = 150 mA
VLDOIN45INITIAL = 2.8 V to VLDOIN45FINAL = 3.3 V for
LDO5[3:0] = 0000 to 0111
VLDO5LITR
5.0
mV
V
LDOIN45INITIAL = VLDO5+0.3 V to VLDOIN45FINAL = VLDO5+0.8 V for
LDO5[3:0] = 1000 to 1111
Refer to Figure 25
Notes
47.
When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
48.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VLDOIN45 refers to the minimum allowed input voltage for a particular output voltage.
2
6.5
Control interface I C block description
2
2
The 34VR500 contains an I C interface port which allows access by a processor, or any I C master, to the register set. Via these registers,
the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.
The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL
and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be
2
accomplished by reducing the drive strength of the I C master via software. It is recommended to use a drive strength of 80 Ω or higher
to increase the edge times. Alternatively, this can be accomplished by using small capacitors from SCL and SDA to ground. For example,
use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of 4.8 kΩ.
2
6.5.1 I C device ID
I C interface protocol requires a device ID for addressing the target IC on a multi-device bus. The I C address is set to 0x08.
2
2
34VR500
NXP Semiconductors
69
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.2 I2C operation
2
The I C mode of the interface is implemented generally following the Fast mode definition which supports up to 400 kbits/s operation
(exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.)
2
The I C interface is configured as "Slave".
2
Timing diagrams, electrical specifications, and further details can be found in the I C specification, which is available for download at:
http://www.nxp.com/documents/user_manual/UM10204.pdf
2
I C read operations are performed in byte increments separated by an ACK. Read operations begin with the MSB and each byte is sent
out unless a STOP command or NACK is received prior to completion.
2
The 34VR500 only supports single-byte I C transactions for read and write. The host initiates and terminates all communication. The host
sends a master command packet after driving the start condition. The device responds to the host if the master command packet contains
the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from
the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.
The 34VR500 uses the "repeated start" operation for reads, as shown in Figure 27.
Figure 26. Data transfer on the I2C bus
Figure 27. Read operation
6.5.3 Interrupt handling
The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving
the INTB pin low.
Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt
can be cleared by writing a “1” to the appropriate bit in the Interrupt Status register; this will also cause the INTB pin to go high. If there
are multiple interrupt bits set the INTB pin will remain low until all are either masked or cleared. If a new interrupt occurs while the processor
clears an existing interrupt bit, the INTB pin will remain low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB
pin will not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for
status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts
are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the INTB pin
will go low after unmasking.
34VR500
70
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are
read only, and not latched or clearable. Interrupts generated by external events are debounced; therefore, the event needs to be stable
throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT
summary Table 81. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.5.4 Interrupt bit summary
Table 81 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer to
the related chapters.
Table 81. Interrupt, mask and sense bits
Interrupt
Mask
LOWVINM
Sense
LOWVINS
Purpose
Trigger
Debounce time (ms)
Low Input Voltage Detect
Sense is 1 if below 2.80 V threshold
LOWVINI
H to L
3.9(49)
Enable on button event
Sense is 1 if EN is high
H to L
L to H
31.25(49)
31.25
ENI
ENM
ENS
Thermal 110 °C threshold
Sense is 1 if above threshold
THERM110
THERM120
THERM125
THERM130
SW1FAULTI
SW2FAULTI
SW3FAULTI
SW4FAULTI
LDO1FAULTI
LDO2FAULTI
LDO3FAULTI
LDO4FAULTI
THERM110M
THERM120M
THERM125M
THERM130M
SW1FAULTM
SW2FAULTM
SW3FAULTM
SW4FAULTM
LDO1FAULTM
LDO2FAULTM
LDO3FAULTM
LDO4FAULTM
LDO5FAULTM
THERM110S
THERM120S
THERM125S
THERM130S
SW1FAULTS
SW2FAULTS
SW3FAULTS
SW4FAULTS
LDO1FAULTS
LDO2FAULTS
LDO3FAULTS
LDO4FAULTS
LDO5FAULTS
Dual
Dual
3.9
3.9
3.9
3.9
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Thermal 120 °C threshold
Sense is 1 if above threshold
Thermal 125 °C threshold
Sense is 1 if above threshold
Dual
Thermal 130 °C threshold
Sense is 1 if above threshold
Dual
Regulator 1 overcurrent limit
Sense is 1 if above current limit
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Regulator 2 overcurrent limit
Sense is 1 if above current limit
Regulator 3 overcurrent limit
Sense is 1 if above current limit
Regulator 4 overcurrent limit
Sense is 1 if above current limit
LDO1 overcurrent limit
Sense is 1 if above current limit
LDO2 overcurrent limit
Sense is 1 if above current limit
LDO3 overcurrent limit
Sense is 1 if above current limit
LDO4 overcurrent limit
Sense is 1 if above current limit
LDO5 overcurrent limit
Sense is 1 if above current limit
LDO5FAULTI
Notes
49.
Debounce timing for the falling edge can be extended with ENDBNC[1:0].
A full description of all interrupt, mask, and sense registers is provided in Tables 82 to 90.
34VR500
NXP Semiconductors
71
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 82. Register INTSTAT0 - ADDR 0x05
Name
Bit #
R/W
Default
Description
Power on interrupt bit
ENI
0
1
2
3
4
5
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
0
0
0
0
0
0
LOWVINI
Low-voltage interrupt bit
THERM110I
THERM120I
THERM125I
THERM130I
110 °C Thermal interrupt bit
120 °C Thermal interrupt bit
125 °C Thermal interrupt bit
130 °C Thermal interrupt bit
Table 83. Register INTMASK0 - ADDR 0x06
Name
Bit #
R/W
Default
Description
ENM
0
1
2
3
4
5
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
1
1
1
1
1
1
Power on interrupt mask bit
LOWVINM
Low-voltage interrupt mask bit
110 °C Thermal interrupt mask bit
120 °C Thermal interrupt mask bit
125 °C Thermal interrupt mask bit
130 °C Thermal interrupt mask bit
THERM110M
THERM120M
THERM125M
THERM130M
Table 84. Register INTSENSE0 - ADDR 0x07
Name
Bit #
R/W
Default
Description
Enable on sense bit
0 = EN low
ENS
0
R
0
1 = EN high
Low voltage sense bit
0 = VIN > 2.8 V
LOWVINS
1
2
3
4
5
R
R
R
R
R
0
0
0
0
0
1 = VIN ≤ 2.8 V
110 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
THERM110S
THERM120S
THERM125S
THERM130S
120 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
125 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
130 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
Table 85. Register INTSTAT1 - ADDR 0x08
Name
SW1FAULTI
Bit #
R/W
Default
Description
2:0
3
R/W1C
R/W1C
R/W1C
R/W1C
0
0
0
0
SW1 Overcurrent interrupt bit
SW2 Overcurrent interrupt bit
SW3 Overcurrent interrupt bit
SW4 Overcurrent interrupt bit
SW2FAULTI
SW3FAULTI
SW4FAULTI
5:4
6
34VR500
72
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 86. Register INTMASK1 - ADDR 0x09
Name
Bit #
R/W
Default
Description
SW1FAULTM
SW2FAULTM
SW3FAULTM
SW4FAULTM
2:0
3
R/W
R/W
R/W
R/W
1
1
1
1
SW1 Overcurrent interrupt mask bit
SW2 Overcurrent interrupt mask bit
SW3 Overcurrent interrupt mask bit
SW4 Overcurrent interrupt mask bit
5:4
6
Table 87. Register INTSENSE1 - ADDR 0x0A
Name
Bit #
R/W
Default
Description
SW1 Overcurrent sense bit
0 = Normal operation
SW1FAULTS
2:0
R
0
1 = Above current limit
SW2 Overcurrent sense bit
0 = Normal operation
SW2FAULTS
SW3FAULTS
SW4FAULTS
3
5:4
6
R
R
R
0
0
0
1 = Above current limit
SW3 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW4 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
Table 88. Register INTSTAT4 - ADDR 0x11
Name
Bit #
R/W
Default
Description
LDO1FAULTI
LDO2FAULTI
LDO3FAULTI
LDO4FAULTI
LDO5FAULTI
1
2
3
4
5
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
0
0
0
0
0
LDO1 Overcurrent interrupt bit
LDO2 Overcurrent interrupt bit
LDO3 Overcurrent interrupt bit
LDO4 Overcurrent interrupt bit
LDO5 Overcurrent interrupt bit
Table 89. Register INTMASK4 - ADDR 0x12
Name
Bit #
R/W
Default
Description
LDO1FAULTM
LDO2FAULTM
LDO3FAULTM
LDO4FAULTM
LDO5FAULTM
1
2
3
4
5
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
LDO1 Overcurrent interrupt mask bit
LDO2 Overcurrent interrupt mask bit
LDO3 Overcurrent interrupt mask bit
LDO4 Overcurrent interrupt mask bit
LDO5 Overcurrent interrupt mask bit
34VR500
NXP Semiconductors
73
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 90. Register INTSENSE4 - ADDR 0x13
Name
Bit #
R/W
Default
Description
LDO1 Overcurrent sense bit
0 = Normal operation
LDO1FAULTS
1
R
0
1 = Above current limit
LDO2 Overcurrent sense bit
0 = Normal operation
LDO2FAULTS
LDO3FAULTS
LDO4FAULTS
LDO5FAULTS
2
3
4
5
R
R
R
R
0
0
0
0
1 = Above current limit
LDO3 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
LDO4 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
LDO5 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
6.5.5 Specific registers
6.5.5.1
IC and version identification
The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 91 to 93.
Table 91. Register DEVICEID - ADDR 0x00
Name
DEVICEID
Bit #
R/W
Default
Description
Die version.
0100 = 34VR500
3:0
R
0x00
Table 92. Register SILICON REV- ADDR 0x03
Name
Bit #
R/W
Default
Description
Represents the metal mask revision
Pass 0.0 = 0000
METAL_LAYER_REV
3:0
R
0x00
.
.
Pass 0.15 = 1111
Represents the full mask revision
Pass 1.0 = 0001
FULL_LAYER_REV
7:4
R
0x01
.
.
Pass 15.0 = 1111
Table 93. Register FABID - ADDR 0x04
Name
Bit #
R/W
Default
Description
Allows for characterizing different options within
the same reticule
FIN
1:0
3:2
R
R
0x00
0x00
FAB
Represents the wafer manufacturing facility
34VR500
74
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.6 Register bitmap
The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can
be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,
the functional registers are the same, but the extended registers are different. To access the Functional page from one of the extended
pages, no write to the page register is necessary.
Registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will have no effect.
The contents of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit.
Bit #: The bit location in the register (7-0)
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Bits reset by VCOREDIG_PORB
Bits reset by EN or loaded default
Bits reset by DIGRESETB
Bits reset by PORB
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
Default: The value after reset, as noted in the Default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
2
• “X” corresponds to Read / Write bits that are initialized at start-up. Bits are subsequently I C modifiable, when their reset has been
released. “X” may also refer to bits that may have other dependencies. For example, some bits may depend on the version of the
IC, or a value from an analog block, for instance the sense bits for the interrupts.
6.5.6.1
Register map
Table 94. Functional page
BITS[7:0]
Add Register name R/W
Default
7
–
0
6
–
0
5
–
0
4
–
1
3
2
1
0
DEVICE ID [3:0]
00
DeviceID
R
8'b0001_0000
0
1
0
0
FULL_LAYER_REV[3:0]
METAL_LAYER_REV[3:0]
03
04
05
06
07
SILICONREVID
FABID
R
R
8'b0001_0000
8'b0000_0000
0
0
0
1
–
0
0
0
0
0
0
–
–
–
FAB[1:0]
FIN[1:0]
0
0
0
0
0
0
ENI
0
–
–
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
INTSTAT0
INTMASK0
INTSENSE0
RW1C 8'b0000_0000
0
0
0
0
0
0
0
–
–
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
ENM
1
R/W
R
8'b0011_1111
8'b00xx_xxxx
0
RSVD
0
0
RSVD
0
1
1
1
1
1
THERM130S
x
THERM125S
x
THERM120S
x
THERM110S
x
LOWVINS
x
ENS
x
34VR500
NXP Semiconductors
75
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 94. Functional page (continued)
BITS[7:0]
Add Register name R/W
Default
7
–
0
–
0
–
0
6
5
0
1
x
4
0
1
x
3
2
0
1
x
1
0
0
1
x
SW4FAULTI
SW3FAULTI
SW3FAULTM
SW3FAULTS
SW2FAULTI
SW1FAULTI
08
09
0A
INTSTAT1
INTMASK1
INTSENSE1
RW1C 8'b0000_0000
0
0
0
SW4FAULTM
SW2FAULTM
SW1FAULTM
R/W
R
8'b0111_1111
8'b0xxx_xxxx
1
1
1
SW4FAULTS
x
SW2FAULTS
x
SW1FAULTS
x
–
0
–
0
LDO5FAULTI
0
LDO4FAULTI
0
LDO3FAULTI
0
LDO2FAULTI
0
LDO1FAULTI
0
–
0
11
12
INTSTAT4
INTMASK4
RW1C 8'b0000_0000
LDO5
FAULTM
LDO4
FAULTM
LDO3
FAULTM
LDO2
FAULTM
LDO1
FAULTM
–
0
–
0
–
0
–
0
–
1
–
x
R/W
R
8'b0011_1111
8'b00xx_xxxx
1
1
1
1
1
LDO5
FAULTS
LDO4
FAULTS
LDO3
FAULTS
LDO2
FAULTS
LDO1
FAULTS
13
1B
INTSENSE4
PWRCTL
x
x
x
x
x
REGSCPEN
0
STANDBYINV
0
STBYDLY[1:0]
ENDBNC[1:0]
ENRSTEN
0
RESTARTEN
0
R/W
8'b0001_0000
0
1
0
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
SW1[5:0]
2E
2F
30
31
32
SW1VOLT
SW1STBY
SW1OFF
R/W
R/W
R/W
R/W
R/W
8'b00xx_xxxx
8'b00xx_xxxx
8'b00xx_xxxx
8'b0000_1000
8'bxx00_xx00
x
x
x
x
x
x
x
1
x
x
x
x
0
x
x
x
x
x
x
x
SW1STBY[5:0]
SW1OFF[5:0]
x
x
–
0
SW1OMODE
0
SW1MODE[3:0]
SW1MODE
SW1CONF
0
0
SW1ILIM
0
SW1DVSSPEED[1:0]
SW1PHASE[1:0]
SW1FREQ[1:0]
–
x
x
0
0
0
–
0
–
0
–
0
–
0
SW2[6:0]
35
36
37
38
39
SW2VOLT
SW2STBY
SW2OFF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx01_xx00
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
SW2STBY[6:0]
x
SW2OFF[6:0]
x
x
–
0
x
x
–
0
SW2OMODE
0
SW2MODE[3:0]
SW2MODE
SW2CONF
1
0
0
SW2ILIM
0
SW2DVSSPEED[1:0]
SW2PHASE[1:0]
SW2FREQ[1:0]
–
x
x
0
1
x
0
34VR500
76
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 94. Functional page (continued)
BITS[7:0]
Add Register name R/W
Default
7
6
5
4
3
2
1
0
–
0
–
0
–
0
SW3[6:0]
3C
3D
3E
3F
40
SW3AVOLT
SW3ASTBY
SW3AOFF
SW3MODE
SW3CONF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx10_xx00
x
x
x
0
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
SW3STBY[6:0]
x
SW3OFF[6:0]
x
x
x
–
0
SW3OMODE
0
SW3MODE[3:0]
0
1
0
0
SW3ILIM
0
SW3DVSSPEED[1:0]
SW3PHASE[1:0]
SW3FREQ[1:0]
–
x
x
1
0
x
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
SW4[5:0]
4A
4B
4C
4D
4E
SW4VOLT
SW4STBY
SW4OFF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx11_xx00
x
x
x
x
x
x
x
1
x
x
x
x
x
x
x
x
SW4STBY[5:0]
SW4OFF[5:0]
x
x
0
x
x
x
–
0
SW4OMODE
0
SW4MODE[3:0]
SW4MODE
SW4CONF
0
0
SW4ILIM
0
SW4DVSSPEED[1:0]
SW4PHASE[1:0]
SW4FREQ[1:0]
–
x
x
1
1
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
–
REFOUTEN
–
0
–
0
–
0
–
0
6A
6D
6E
6F
70
71
7F
REFOUTCRTRL
LDO1CTL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b000x_0000
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b0000_0000
0
0
x
LDO1LPWR
LDO1STBY
LDO1EN
LDO1[3:0]
LDO2[3:0]
LDO3[3:0]
LDO4[3:0]
LDO5[3:0]
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
LDO2LPWR
LDO2STBY
LDO2EN
LDO2CTL
0
0
x
LDO3LPWR
LDO3STBY
LDO3EN
LDO3CTL
0
0
x
LDO4LPWR
LDO4STBY
LDO4EN
LDO4CTL
0
0
x
LDO5EN
x
LDO5LPWR
LDO5STBY
LDO5CTL
0
–
0
0
–
0
PAGE[4:0]
x
Page Register
x
34VR500
NXP Semiconductors
77
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 95. Extended page 1: internal RAM
BITS[7:0]
Address Register name TYPE
Default
7
–
0
–
0
–
0
6
–
0
5
4
3
2
1
x
x
0
x
x
x
SW1_VOLT[5:0]
x
A8
A9
AA
SW1 VOLT
SW1 SEQ
R/W
R/W
R/W
8'b00xx_xxxx
8'b000x_xxxx
8'b0000_00xx
x
x
x
SW1_SEQ[4:0]
0
–
0
0
–
0
x
–
0
x
–
0
x
–
0
SW1_FREQ[1:0]
SW1 CONFIG
x
–
0
–
0
–
0
SW2_VOLT[6:0]
x
AC
AD
AE
SW2 VOLT
SW2 SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_00xx
x
–
0
–
0
x
x
x
x
x
x
x
x
SW2_SEQ[4:0]
0
–
0
x
–
0
x
–
0
x
–
0
SW2_FREQ[1:0]
SW2 CONFIG
x
–
0
–
0
–
0
SW3A_VOLT[6:0]
x
B0
B1
B2
SW3 VOLT
SW3 SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_xxxx
x
–
0
–
0
x
x
x
x
x
x
x
x
SW3_SEQ[4:0]
x
0
–
0
x
–
0
x
x
SW3_CONFIG[1:0]
SW3_FREQ[1:0]
SW3 CONFIG
x
x
–
0
–
0
–
0
–
0
–
0
–
0
SW4_VOLT[5:0]
B8
B9
BA
SW4 VOLT
SW4 SEQ
R/W
R/W
R/W
8'b00xx_xxxx
8'b000x_xxxx
8'b000x_xxxx
x
–
0
–
0
x
x
x
x
x
x
x
x
SW4_SEQ[4:0]
x
VTT
x
x
–
x
x
–
x
SW4_FREQ[1:0]
SW4 CONFIG
x
–
0
–
0
–
0
REFOUT_SEQ[4:0]
0
C4
REFOUT SEQ
R/W
8'b000x_x0xx
x
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
LDO1_VOLT[3:0]
CC
CD
LDO1 VOLT
LDO1 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
LDO1_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
LDO2_VOLT[3:0]
D0
LDO2 VOLT
R/W
8'b0000_xxxx
x
x
x
x
34VR500
78
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 95. Extended page 1: internal RAM (continued)
BITS[7:0]
Address Register name TYPE
Default
7
–
0
6
–
0
5
–
0
4
3
2
1
0
LDO2_SEQ[4:0]
x
D1
LDO2 SEQ
R/W
8'b000x_xxxx
x
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
LDO3_VOLT[3:0]
D4
D5
LDO3 VOLT
LDO3 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
LDO3_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
LDO4_VOLT[3:0]
D8
D9
LDO4 VOLT
LDO4 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
LDO4_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
LDO5_VOLT[3:0]
DC
DD
LDO5 VOLT
LDO5 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
LDO5_SEQ[4:0]
x
x
x
PWRON_
CFG1
–
–
–
SWDVS_CLK1[1:0]
SEQ_CLK_SPEED1[1:0]
E0
PU CONFIG1
R/W
R/W
8'b000x_xxxx
8'b0000_00x0
0
0
RSVD
RSVD
–
0
x
x
x
x
RSVD
RSVD
–
x
–
TBB_POR
–
–
–
–
E4
E8
TBB_POR
0
–
0
RSVD
RSVD
RSVD
RSVD
RSVD
PG_EN
0
–
0
–
0
–
0
–
0
PWRGD EN
R/W/M 8'b0000_000x
0
x
34VR500
NXP Semiconductors
79
TYPICAL APPLICATIONS
7
Typical applications
7.1
Introduction
Figure 28 provides a typical application diagram of the 34VR500 PMIC together with its functional components. For details on component
references and additional components such as filters, refer to the individual sections.
7.1.1 Application diagram
VLDOIN1
1.0uF
FB1
SW1 Output
VR500
3 x 4.7 uF
+3 x 0.1 uF
Vin
PVIN1
LX1
SW1
4500 mA
Buck
O/P
Drive
0.68uH
4.7uF
LDO1
250mA
LDO1
7 x22 uF
VLDOIN23
1.0uF
2.2uF
LDO2
100mA
LDO2
LDO3
SW2 Output
1.5uH
LX2
LDO3
350mA
SW2
2000 mA
Buck
O/P
Drive
PVIN2
4.7uF
3 x 22 uF
4.7 uF
+0.1 uF
Vin
VLDOIN45
FB2
Core Control logic
1.0uF
2.2uF
LDO4
100mA
LDO4
LDO5
Initialization State Machine
FB3
SW3 Output
3 x 22 uF
LDO5
200mA
2 x 4.7 uF
Vin
+2 x 0.1 uF
2.2uF
SW3
2500 mA
Buck
PVIN3
LX3
O/P
Drive
1.5uH
Supplies
Control
VCCI2C
VCCI2C
CONTROL
FB4
I2C
Interface
SW4 Output
3 x 22 uF
4.7 uF
+0.1 uF
Vin
SW4
1000 mA
Buck
PVIN4
LX4
SCL
SDA
O/P
Drive
1.5uH
To
MCU
DVS CONTROL
DVS Control
I2C
Register
map
1uF
Trim-In-Package
VDIG
VBG
VCC
220nF
1uF
Reference
Generation
Clocks and
resets
SGND4
VBIAS
0.47uF
1uF
Clocks
32kHz and 16MHz
REFOUT
REFIN
VSW3
Package Pin Legend
Output Pin
Input Pin
100nF
VHALF
Bi-directional Pin
100nF
VSW2
VSW2
VSW2
To/From
AP
Figure 28. Typical application schematic
34VR500
80
NXP Semiconductors
TYPICAL APPLICATIONS
7.1.2 Application instructions
Table 96 provides a complete list of the recommended components on a full featured system using the 34VR500 device. Critical
components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may
be used.
7.2
Bill of materials
Table 96. Bill of materials (50)
Schematic
Assy
opt
Item Qty
Value
Description
Part number
Manufacturer
Component/pin
label
Freescale components
1
1
Power management IC
4 x 4 x 2.1
34VR500
Freescale
BUCK, SW1 - (0.625-1.875 V), 4.5 A
2
1
0.60 μH
XAL4020-601ME
Coilcraft
Output Inductor
ISAT = 10.4 A for 30% drop,
DCRMAX = 10.45 mΩ
3
4
5
6
3
3
22 μF
4.7 μF
0.1 μF
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
BUCK, SW2 - (0.625-3.3 V), 2.0 A
3.9 x 3.9 x 1.1
6
1
1.5 μH
LPS4012-152MR
Coilcraft
Output Inductor
ISAT = 2.6 A for 10% drop,
DCRMAX = 70 mΩ
7
8
9
2
1
1
22 μF
4.7 μF
0.1 μF
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
BUCK, SW3 - (0.625-3.3 V), 2.5 A
4 x 4 x 2.1
10
1
1.5 μH
XFL4020-152ME
Coilcraft
Output Inductor
ISAT = 7.0 A for 10% drop,
DCRMAX = 21.45 mΩ
4.3 x 4.3 x 1.4
ISAT = 2.9 A for 10% drop,
DCRMAX = 78 mΩ
Output Inductor
(Alternate)
11
12
–
–
1.5 μH
1.0 μH
LPS4014_152ML
Coilcraft
Toko
4 x 4 x 1.2
ISAT = 6.2 A, DCR = 37 mΩ
Output inductor
(Alternate)
FDSD0412-H-1R0M
13
14
15
4
2
1
22 μF
4.7 μF
0.1 μF
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
34VR500
NXP Semiconductors
81
TYPICAL APPLICATIONS
Table 96. Bill of materials (50) (continued)
Schematic
Assy
opt
Item Qty
Value
Description
Part number
Manufacturer
Component/pin
label
BUCK, SW4 - (0.625-1.975 V), 1.0 A
3.9 x 3.9 x 1.1
16
1
1.5 μH
LPS4012-152MR
Coilcraft
Output Inductor
ISAT = 2.6 A for 10% drop,
DCRMAX = 70 mΩ
17
18
19
2
1
1
22 μF
4.7 μF
0.1 μF
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
LDO, LDO1 - (0.80-1.55), 250 mA
20
1
4.7 μF
6.3 V X5R 0402
6.3 V X5R 0402
6.3 V X5R 0402
6.3 V X5R 0402
6.3 V X5R 0402
C0402X5R6R3-
Venkel
Output capacitance
Output capacitance
Output capacitance
Output capacitance
Output capacitance
LDO, LDO2 - (1.80-3.30), 100 mA
21
1
2.2 μF
C0402C225M9PACTU Kemet
LDO, LDO3 - (1.80-3.30), 350 mA
22
1
4.7 μF
C0402X5R6R3-
Venkel
LDO, LDO4 - (1.80-3.30), 100 mA
23
1
2.2 μF
C0402C225M9PACTU Kemet
C0402C225M9PACTU Kemet
CC0402KRX5R6BB105 Yageo America
LDO, LDO5 - (1.80-3.30), 200 mA
24
1
2.2 μF
Reference, REFOUT - (0.60-0.90V), 10 mA
25
26
1
2
1.0 μF
0.1 μF
10 V X5R 0402
10 V X5R 0402
Output capacitance
VHALF, REFIN
C0402C104K8PAC
Kemet
Internal references, VDIG, VBG, VCC
27
28
29
1
1
1
1.0 μF
1.0 μF
0.22 μF
10 V X5R 0402
10 V X5R 0402
10 V X5R 0402
CC0402KRX5R6BB105 Yageo America
CC0402KRX5R6BB105 Yageo America
GRM155R61A224KE1 Murata
VDIG
VCC
VBG
Miscellaneous
30
31
32
33
34
35
1
1
1
1
1
1
0.1 μF
1.0 μF
100 kΩ
100 kΩ
100 kΩ
100 kΩ
10 V X5R 0402
10 V X5R 0402
1/16 W 0402
1/16 W 0402
1/16 W 0402
1/16 W 0402
CD402C104K8PAC
Kemet
VCCI2C
VIN
CC0402KRX5R6BB105 Yageo America
RK73H1ETTP1003F
RK73H1ETTP1003F
RK73H1ETTP1003F
RK73H1ETTP1003F
KOA SPEER
KOA SPEER
KOA SPEER
KOA SPEER
EN
PORB
STBY
INTB
Notes
50.
Freescale does not assume liability, endorse, or warrant components from external manufacturers are referenced in circuit drawings or tables.
While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
Do not populate
51.
52.
Critical components. For critical components, it is vital to use the manufacturer listed.
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TYPICAL APPLICATIONS
7.3
34VR500 layout guidelines
7.3.1 General board recommendations
1. It is recommended to use an eight layer board stack-up arranged as follows:
• High current signal
• GND
• Signal
• Power
• Power
• Signal
• GND
• High current signal
2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area.
3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.
7.3.2 Component placement
It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output
capacitors.
7.3.3 General routing requirements
1. Some recommended things to keep in mind for manufacturability:
• Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
• Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils
2. Care must be taken with FBx pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or
high power signals, like the ones on the PVINx, SWx, and LXx pins. They could be also shielded.
3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power
planes shield these traces).
4. Avoid coupling traces between important signal/low noise supplies (like VBG, VCC, VDIG) from any switching node (i.e. LX1, LX2,
LX3, and LX4).
5. Make sure that all components related to a specific block are referenced to the corresponding ground.
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TYPICAL APPLICATIONS
7.3.4 Parallel routing requirements
2
1. I C signal routing
• CLK is the fastest signal of the system, so it must be given special care.
• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them
with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.
Figure 29. Recommended shielding for critical signals
• These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
• Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good practice
is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
7.3.5 Switching regulator layout recommendations
1. Per design, the switching regulators in 34VR500 are designed to operate with only one input bulk capacitor. However, it is
recommended to add a high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor
should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
2. Make high-current ripple traces low-inductance (short, high W/L ratio).
3. Make high-current traces wide or copper islands.
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TYPICAL APPLICATIONS
VIN
PVINx
CIN_HF
CIN
SWx
LXx
Driver Controller
L
COUT
FBx
Compensation
Figure 30. Generic buck regulator architecture
Figure 31. Layout example for buck regulators
7.4
Thermal information
7.4.1 Rating data
The thermal rating data of the packages has been simulated with the results listed in Table 4.
Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol R
or θJA (Theta-JA) strictly for
θJA
junction-to-ambient thermal resistance on a 1s test board in natural convection environment. R
or θJMA (Theta-JMA) will be used for
θJMA
both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and
2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used.
The JEDEC standards can be consulted at http://www.jedec.org.
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TYPICAL APPLICATIONS
7.4.2 Estimation of junction temperature
An estimation of the chip junction temperature T can be obtained from the equation:
J
T = T + (R
x P )
D
J
A
θJA
with:
T = Ambient temperature for the package in °C
A
RθJA = Junction to ambient thermal resistance in °C/W
P = Power dissipation in the package in W
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board R
and the value obtained on a four
θJA
layer board R
. Actual application PCBs show a performance close to the simulated four layer board value although this may be
θJMA
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature T is estimated using the following equation
J
T = T + (R
x P ) with
D
J
B
θJB
T = Board temperature at the package perimeter in °C
B
R
= Junction to board thermal resistance in °C/W
θJB
P = Power dissipation in the package in W
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
See Functional block requirements and behaviors for more details on thermal management.
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NXP Semiconductors
PACKAGING
8
Packaging
8.1
Packaging dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number. See the Thermal characteristics section for specific thermal characteristics
for each package.
Table 97. Package drawing information
Package
Suffix
Package outline drawing number
56 QFN 8x8 mm - 0.5 mm pitch.
WF-Type (wettable flank)
ES
98ASA00589D
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PACKAGING
34VR500
88
NXP Semiconductors
PACKAGING
34VR500
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89
REVISION HISTORY
9
Revision history
Revision
Date
Description of changes
•
Initial release
1.0
5/2014
•
•
•
•
•
•
SW2, SW3, and SW4 voltage range modification
Table 6.1.2 added to explain how to change the start sequence.
Table 95 added
Added PC34VR500V2ES to the Orderable part Table 1
Update the 98A number
2.0
3.0
8/2014
1/2015
Added Bill of Materials
•
•
Updated Table 1 (corrected a typo)
Updated values for VSW2ACC in Table 47
•
•
Updated values for VSW3ACC in Table 56
Updated values for VSW4ACC in Table 65
•
•
Updated package outline (changed 98ASA00379D to 98ASA00589D)
Added optimized value for the buck regulator external components
•
•
•
•
•
Added MC34VR500V3ES, MC34VR500V4ES, MC34VR500V5ES to the Orderable Part Variations Table
Added SW1, SW2, SW3, SW4 transient load plots
Added SW1, SW2 efficiency plots
Updated Control interface I2C block description, I2C device ID, and I2C operation sections
Updated SW2 rated current to 2.0 A
4.0
5.0
7/2015
1/2017
•
•
•
•
Updated document to NXP form and style
Added MC34VR500V6ES, MC34VR500V7ES, and MC34VR500V8ES to Table 1
Updated Table 8 and added the new part numbers to 5.1 Features, page 12, and 6.4.4.17 SW4, page 49
Updated Figure 16
•
Updated voltage values under “Four independent outputs” for SW2 and SW3 from “0.625 V to 1.975 V” to
“0.625V to 3.3V” in Section 5.1
•
•
•
•
•
•
•
Updated Figure 4 in Section 5.2, to reflect revised voltage values for SW2 and SW3
Updated voltage values for SW2 and SW3 in Table 21 from “0.625 - 1.975” to “0.625 - 1.975 / 0.8 - 3.3”
Updated Step size values for SW2 and SW3 from “25” to “25 / 50” in Table 21
Updated SW2 and SW3 voltage from “1.975 V” to “3.3” V in Figure 10
Updated Section 6.4.4.10 and Table 39
Updated Table 41, Table 42 and Table 43, adding two rows to the bottom of each table
Updated Table 47, as follows:
•
•
•
•
Added high voltage range values “2.0 V < VSW2 < 3.3 V”, “-6.0” and “6.0” in the first bullet of Parameter,
Min and Max columns for VSW2ACC
Added high voltage range values “2.0 V < VSW2 < 3.3 V”, “-3.0” and “3.0” in the second bullet of Parameter,
Min and Max columns for VSW2ACC
Updated the parameter value for VSW2 from “2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 1.975 V” to “2.8 V < VIN
< 4.5 V, 0.625 V < VSW2 < 3.3 V”
Added third bullet under Parameter along with associated Typ values for ηSW2
•
•
•
•
Updated Section 6.4.4.13, revising “1.975 V” to “3.3 V”
6.0
1/2018
Updated the first paragraph of Section 6.4.4.14 and the content of Table 48
Updated Table 50, Table 51 and Table 52, adding two rows to the bottom of each table
Updated Table 56 as follows:
•
•
•
Added high voltage range values “2.0 V < VSW3 < 3.3 V”, “-6.0” and “6.0” in the first bullet of Parameter,
Min and Max columns for VSW3ACC
Added high voltage range values “2.0 V < VSW2 < 3.3 V”, “-3.0” and “3.0” in the second bullet of Parameter,
Min and Max columns for VSW3ACC
Updated the parameter value for VSW3 from “2.8 V < VIN < 4.5 V, 0.625 V < VSW3 < 1.975 V” to “2.8 V < VIN
< 4.5 V, 0.625 V < VSW3 < 3.3 V”
•
•
Removed “single/dual phase” from “PWM, APS mode single/dual phase”
Removed “PWN, APS mode independent (per phase)” from the parameter value for ISW3 and removed the
associated Max value
•
Removed “x” after “SW3” in the note at the bottom of the table.
•
•
Updated Table 94 as follows:
Remove the values for Bit 6 for addresses 35, 36, 37, 3C, 3D, 3E, AC and B0
Updated bold text before item 6 for SW2 and bold text before item 7 for SW3 from “(0.625-1.975 V)” to “(0.625-
3.3 V)” in Table 96.
•
34VR500
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NXP Semiconductors
REVISION HISTORY
Revision
Date
Description of changes
•
•
•
Added MC34VR500V9ES to Table 1
Added 34VR500V9 to “Four independent outputs” for SW4 in Section 5.1 Features, page 12
Updated Table 8
7.0
5/2018
•
•
Added MC34VR500VAES to Table 1
Added configuration for 34VR500VA to Table 8
8.0
9.0
10
8/2018
1/2019
3/2020
•
•
Added MC34VR500VBES to Table 1
Added configuration for 34VR500VB to Table 8
•
•
Changed document status from Advance Information to Technical Data
Updated Features list on page 1 as per CIN 202003004I (deleted “Auto qualified AEC Q100 grade 2”)
•
Updated start-up configuration for 34VR500VB in Table 8
•
•
•
LDO3_SEQ - replaced 3 by 2
SW2_VOLT - replaced 1.8 V by 0.9 V
SW3_VOLT - replaced 0.9 V by 1.8 V
11
4/2020
34VR500
NXP Semiconductors
91
Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to any
products herein.
How to Reach Us:
Home Page:
NXP.com
Web Support:
http://www.nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,
and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the
following address:
http://www.nxp.com/terms-of-use.html.
NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or
service names are the property of their respective owners. All rights reserved.
© NXP B.V. 2020.
Document Number: MC34VR500
Rev. 11
4/2020
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