MC35XS3500HFKR2_技术文档

Document Number: MC35XS3500

Rev. 8.0, 8/2013

Freescale Semiconductor

Technical Data

Smart Rear Corner Light Switch

(Penta 35 mOhm)

35XS3500

The 35XS3500 is designed for low-voltage automotive and

industrial lighting applications. Its five low R_DS(ON)MOSFETs (five

35 m) can control the high sides of five separate resistive loads

(bulbs and LEDs).

HIGH SIDE SWITCH

Programming, control and diagnostics are accomplished using a

16-bit SPI interface (3.3 V or 5.0 V). Each output has its own pulse-

width modulation (PWM) control via the SPI. The 35XS3500 has

highly sophisticated failure mode handling to provide high availability

of the outputs. Its multiphase control and output edge shaping

improves electromagnetic compatibility (EMC) behavior.

The 35XS3500 is packaged in a power-enhanced 12 x 12 mm

nonleaded PQFN package with exposed tabs.

Bottom View

Features

FK SUFFIX

98ART10511D

24-PIN PQFN

PB FREE

• Penta 35 m high side switches

• 16-bit SPI communication interface with daisy chain capability

• Current sense output with SPI-programmable multiplex switch

and board temperature feedback

• Digital diagnosis feature

• PWM module with multiphase feature including prescaler

• LEDs control including accurate current sensing and low duty-

cycle capability

ORDERING INFORMATION

Device

(For Tape and Reel,

Add R2 Suffix)

Temperature

Package

Range (T )

• Fully protected switches

A

• Over-current shutdown detection

• Power net and reverse polarity protection

• Low-power mode

MC35XS3500HFK

-40 to 125 °C

24 PQFN

* MC35XS3500DHFK

• Fail-safe mode functions including autorestart feature

• External smart power switch control including current recopy

* Recommended for all new designs

12V

5.0V

12V

35XS3500

VCC

VBAT

LIMP

FLASHER

STOP

CP

OUT1

Watchdog

OUT2

IGN

RST

CLOCK

CS

OUT3

OUT4

MCU

OUT5

S0

FETIN

FETOUT

SI

SCLK

CSNS

Smart

Switch

GND

Figure 1. 35XS3500 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

DEVICE VARIATIONS

Table 1. MC35XS3500 Device Variations

Part Number

Package

Temp.

Comment

MC35XS3500HFK

MC35XS3500DHFK

Initial release

D version is more robust against V_BATinterrupt

24 PQFN

-40 to 125 °C

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

INTERNAL BLOCK DIAGRAM

VCC

VBAT

CP

Charge

Pump

OV/UV/POR

detections

V_CCfailure

detection

Internal

Regulator

R

UP

CS

SO

SI

Gate Drive

drain/gate clamp

SCLK

Logic

LED Control

R_DWN

OUT1

Over-current

Detection

CLOCK

LIMP

STOP

Open Load

Detection

FLASHER

IGN

Over-temperature

Detection

RST

OUT1

OUT2

OUT3

R_DWN

OUT3

OUT4

OUT5

Over-temperature

Prewarning

OUT4

OUT5

Selectable Output Current

Recopy (Analog MUX)

FETIN

CSNS

Current Recopy

Synchronization

Temperature

Feedback

VCC

Driver for External

MOSFET

FETOUT

GND

Figure 2. 35XS3500 Simplified Internal Block Diagram

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

13 12 11 10

9

8

7

6

5

4

3

2

1

CP

16

17

24

CSNS

GND

23

14

GND

OUT5

18

22

OUT1

15

VBAT

19

20

21

OUT2

OUT4

OUT3

Figure 3. 35XS3500 Pin Connections (Transparent Package Top View)

Table 2. 35XS3500 Pin Definitions

Functional descriptions these pins can be found in the Functional Description section beginning on page 20.

Pin Name Pin Function

Formal Name

Definition

1

2

Input

External FET Input

FETIN

IGN

This pin is the current sense recopy of the external MOSFET.

Ignition Input

(Active High)

This input wakes the device. It also controls outputs 1 and 2 in case of

Fail mode activation. This pin has a passive internal pull-down.

3

RST

Input

Reset

This input wakes the device. It is also used to initialize the device

configuration and fault registers through the SPI. This pin has a passive

internal pull-down.

4

5

FLASHER

CLOCK

Input

Flasher Input

(Active High)

This input wakes the device. This pin has a passive internal pull-down.

Clock Input

This pin state depends on RST logic level.

As long as RST input pin is set to logic [0], this pin is pulled up in order to

report wake event. Otherwise, the PWM frequency and timing are

generated from this digital clock input by the PWM module.

This pin has a passive internal pull-down.

6

7

8

LIMP

STOP

CS

Input

Limp Home Input

(Active High)

The Fail mode can be activated by this digital input. This pin has an active

internal pull-down current source.

Stop Light Input

(Active High)

This input wakes the device. This pin has a passive internal pull-down.

Chip Select

(Active Low)

When this signal is high, SPI signals are ignored. Asserting this pin low

starts a SPI transaction. The transaction is signaled as completed when

this signal returns high. This pin has a passive internal pull-up resistance.

9

SCLK

Input

SPI Clock Input

This input pin is connected to the master microcontroller providing the

required bit shift clock for SPI communication. This pin has a passive

internal pull-down resistance.

35XS3500

Analog Integrated Circuit Device Data

4

Freescale Semiconductor

PIN CONNECTIONS

Table 2. 35XS3500 Pin Definitions (continued)

Functional descriptions these pins can be found in the Functional Description section beginning on page 20.

Pin Name Pin Function

Formal Name

Definition

10

SI

Input

Master-Out Slave-In

This data input is sampled on the positive edge of the SCLK. This pin has

a passive internal pull-down resistance.

11

12

VCC

SO

Input

Logic Supply

SPI Logic power supply.

Output

Master-In Slave-Out

SPI data sent to the MCU by this pin. This data output changes on the

negative edge of SCLK, and when CS is high. This pin is high-impedance.

13

FETOUT

Output

External FET Gate

This pin controls an external SMART MOSFET by logic level. This output

called OUT6.

If OUT6 is not used in the application, this output pin is set to logic high

when the current sense output becomes valid when CSNS sync SPI bit is

set to logic [1].

This pin is the ground for the logic and analog circuitry of the device.⁽¹⁾

Power supply pin.

14, 17, 23

GND

Ground

15

16

VBAT

CP

Input

Battery Input

Charge Pump

Output

This pin is the connection for an external tank capacitor (for internal use

only).

18

19

20

21

22

OUT5

OUT4

OUT3

OUT2

OUT1

Output

Output 5

Output 4

Output 3

Output 2

Output 1

Protected 35 m high side power output to the load.

24

CSNS

Output

Current Sense Output

This pin is used to output a current proportional to OUT1:OUT5, FETin

current, and it is used externally to generate a ground-referenced voltage

for the microcontroller to monitor output current. Moreover, this pin can

report a voltage proportional to the temperature on the GND flag.

OUT1:OUT5, FETin current sensing and Temperature feedback choice is

SPI programmable.

Notes

1. The pins 14, 17, and 23 must be shorted on the board.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating

Symbol

Value

Unit

ELECTRICAL RATINGS

V

Over-voltage Test Range

BAT

28

40

Maximum Operation Voltage

Load Dump (400 ms) at 25 °C

V

Reverse Polarity Voltage Range

2.0 Min at 25 °C

BAT

-18

V

-0.3 to 5.5

V

VCC Supply Voltage

CC

V

Output Voltage

OUT

40

Positive

-16

Negative (ground disconnected)

I

±1.0

mA

Digital Input Current in Clamping Mode (SI, SCLK, CS, IGN, FLASHER,

STOP, LIMP)

IN

I

+10

-1.0

FETIN Input Current

FETIN

V_SO

E

-0.3 to V +0.3

CC

V

SO and FETOUT Output Voltage

30

mJ

Outputs clamp energy using single pulse method (L = 2.0 mH; R = 0 ;

VBAT = 14 V at 150 °C initial)

ESD Voltage⁽²⁾

V

ESD

±2000

±8000

±750

Human Body Model (HBM) OUT[1:5], VPWR, and GND

Charge Device Model (CDM)

Corner Pins (1,13,19,21)

±500

All Other Pins (2-12, 14-18, 20, 22-24)

THERMAL RATINGS

°C

Operating Temperature

Ambient

T

-40 to 125

-40 to 150

A

Junction

T

J

Peak Package Reflow Temperature During Reflow^{(3), (4)}

Storage Temperature

T_PPRT

T_STG

Note 4

°C

-55 to 150

THERMAL RESISTANCE

Thermal Resistance, Junction to Case⁽⁵⁾

Notes

R

1.0

C/W

JC



2. ESD testing is performed in accordance with the Human Body Model (HBM) (C

Model.

= 100 pF, R

= 1500 ) and the Charge Device

ZAP

3. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

4. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

5. Typical value is guaranteed per design.

35XS3500

Analog Integrated Circuit Device Data

6

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUT (VBAT, VCC)

V_BAT

V

Battery Supply Voltage Range

Full Performance and Short-circuit

Extended Voltage Range⁽⁶⁾

7.0

6.0

–

20

28

V_BATUV

5.0

27.5

40

5.5

30

–

6.0

32.5

48

V

Battery Supply Under-voltage (UV flag is set ON)

V

Battery Voltage Clamp (OV flag is set ON)

Battery Voltage Clamp

BATCLAMP_OV

V

BATCLAMP

Battery Supply Power on Reset⁽⁹⁾

If V_BAT< 5.5 V, V_BAT= V_CC

V_BATPOR1

V_BATPOR2

2.0

–

3.0

4.0

If V_BAT< 5.5 V, V_BAT= 0

VBAT Supply Current at 25 °C and V_BAT=12 V and V_CC= 5.0 V

I_BATSLEEP1

I_BATSLEEP2

I_BAT

Sleep State Current, Outputs Open

Sleep State Current, Outputs Grounded

Normal Mode, IGN = 5.0 V, RST = 5.0 V, Outputs Open

–

0.5

10

5.0

20

A

mA

V_CC

3.0

2.2

–

5.5

2.8

V

Digital Voltage Range, Full Performance

Digital Supply Under-voltage (V_CCFailure)

V_CCUV

2.5

I_CCSLEEP

A

Sleep Current Consumption on V

Output OFF

at 25 °C and V

12 V

BAT =

CC

–

0.2

5.0

I_CC

mA

Supply Current Consumption on V

and V

12 V

BAT =

CC

–

2.6

5.0

No SPI

3.0 MHz SPI Communication

LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, STOP)

Input High Logic Level⁽⁷⁾

V

2.0

–

V

IH

Input Low Logic Level⁽⁷⁾

V

0.8

2.2

IL

V

1.0

Ignition Threshold Level (IGN, FLASHER, STOP and RST)

IGN

TH

V

Input Clamp Voltage (IGN, FLASHER, LIMP, STOP, CS, SCLK, SI, RST)

I = 1.0 mA

CL_POS

V

7.5

–

13

V

Input Forward Voltage (IGN, FLASHER, LIMP, STOP, CS, SCLK, SI, RST)

I = 1.0 mA

CL_NEG

V

-2.0

100

–

-0.3

400

Input Passive Pull-up Resistance on CS pin⁽⁸⁾

R

200

k

UP

R

100

200

500

Input Passive Pull-down Resistance on SI, SCLK, FLASHER, IGN, FOG,

CLOCK, LIMP and RST pins⁽⁸⁾

DWN

V_SOH

V

SO High-state Output Voltage

I_OH= 1.0 mA

CC

0.8

0.95

–

V_CLOCKH

V_CC

CLOCK Output Voltage reporting wake-up event (I_CLOCK=1.0 mA)

Notes

6. In extended mode, the functionality is guaranteed but not the electrical parameters.

7. Valid for RST, SI, SCLK, CLOCK, FLASHER, STOP, and LIMP pins.

8. Valid for the following input voltage range: VCC = -0.3 to +0.3 V.

9. Please refer to Loss of VBAT section for more details.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, STOP) (CONTINUED)

V_SOL

V

SO Low-state Output Voltage

I_OL= -1.6 mA

–

0.2

0.0

0.4

1.0

I_SOLEAK

A

SO Tri-state Leakage Current

CS > 0.7 V

-1.0

CC

I_CSNSLEAK

CSNS Tri-state Leakage Current

VCC = 5.5 V, CSNS = 4.5 V

VCC = 5.0 V, CSNS = 5.5 V

VCC = 5.0 V, CSNS = 3.0 V

-5.0

-10

0.0

1.0

-1.0

V

5.0

6.0

7.0

V

Current Sense Output Clamp Voltage

I_CSNS< 10.0 mA

CSNS

OUTPUT (OUT 1:5)

I

A

Output Leakage Current in OFF state

Sleep mode, Outputs Grounded

Normal mode, Outputs Grounded

OUTLEAK

–

0

2.0

25

20

V

Output Negative Clamp Voltage

I_OUT= -500 mA, Outputs OFF

OUT

-22

–

-16

Current Sense Output Precision⁽¹⁰⁾

I /I

%

CS CS

Full-Scale Range (FSR) for LED Control bit = 0

-14

-15

-17

-22

-

14

15

17

22

0.75 FSR

0.50 FSR

0.25 FSR 

0.10 FSR

Full-Scale Range (FSR) for LED Control bit = 1

0.187 FSR = 0.75 FSR_LED

0.125 FSR = 0.50 FSR_LED

0.062 FSR = 0.25 FSR_LED

0.025 FSR = 0.10 FSR_LED

-13

-20

-30

-

13

20

30

%

Current Sense Output Precision

-6.0

-

6.0

Over-temperature Range [-40;125 °C], V_BATRange [10 V-16 V] and FSR

Range [25%-100%], calculated with one calibration point (Taken at 25 °C,

VBAT = 13.5 V and 50% FSR)⁽¹²⁾

–

Current Sense Output Precision with one calibration point (50% FSR_LED

_{BAT =}13.5 at 25 °C⁽¹²⁾

,

V

Temperature Drift of Current Sense Output⁽¹¹⁾

I /T

ppm/

°C

CS

–

±280

±400

V_BAT= 13.5 V, I_OUT= 2.8 A reference taken at T_A= 25 °C

Notes

10. 10 V < V_BAT< 16 V. (I_CS/I_{CS =}(measured I_CS- targeted I_CS)/ targeted I_CSwith targeted I_CS= 5.0 mA

11. Based on statistical data. Not production tested. I_CS/T = [(measured at I_CSat T₁- measured at I_CSat T₂) measured at I_CSat room]/

(T_{1 -}T₂)

12. Based on statistical analysis covering 99.74% of parts.

35XS3500

Analog Integrated Circuit Device Data

8

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

OUTPUT (OUT 1:5) (CONTINUED)

Symbol

Min

Typ

Max

Unit

Minimum Output Current Reported in CSNS for OUT[1-5]⁽¹³⁾

I

mA

35MIN(CSNS)

65

40

–

10 V VBAT 16 V

Minimum Output Current Reported in CSNS for OUT[1-5] in LED Mode⁽¹³⁾

I

35MIN(CSNS) LED

10 V VBAT 16 V

T

155

110

175

125

195

140

°C

Over-temperature Shutdown

OTS

Thermal Prewarning⁽¹⁴⁾

Output Voltage Threshold

TAIL LIGHT (OUT1)

T

OTSWARN

V

0.475

0.5

0.525

V_BAT

OUT_TH

R

m

Output Drain-to-Source ON Resistance (I

2.8 A, T = 25 °C)

A

DS(ON)

OUT =

–

35

55

V

= 13.5 V

= 7.0 V

BAT

R

m

Output Drain-to-Source ON Resistance (I_OUT= 2.8 A, V_{BAT =}13.5 V, 

= 150 °C)⁽¹⁴⁾

DS(ON)

–

59.5

70

T

A

Reverse Output ON Resistance (I_OUT= -2.8 A, V_{BAT =}-12 V, T = 25 °C)⁽¹⁵⁾

A

SD(ON)

TAIL LIGHT (OUT1)

R

m

Output Drain-to-Source ON Resistance (I

Control = 1

1.5 A, T = 25 °C) for LED

A

DS(ON)25_LED

OUT =

–

70

V

= 13.5 V

= 7.0 V

110

BAT

R_{DS(ON)150_LED}

m

Output Drain-to-Source ON Resistance (I

= 150 °C) for LED Control = 1

1.5 A, V

= 13.5 V,

BAT

–

119

T

A

I

28.0

30.2

35.0

36.0

43.5

41.8

A

High Over-current Shutdown Threshold 1

OCHI1

V

_{BAT =}16 V, T = -40 °C

A

29.4

28.3

35.0

33.8

40.6

39.3

_{BAT =}16 V, T = 25 °C

A

₌16 V, T = 125 °C

BAT

A

I

12.3

5.7

15.4

7.2

18.5

8.9

A

High Over-current Shutdown Threshold 2

Low Over-current Shutdown Threshold

OCHI2

I

OCLO

Open Load Current Threshold in ON State⁽¹⁶⁾

Open Load Current Threshold in ON State with LED⁽¹⁷⁾

- 0.5 V

I

0.05

0.2

0.5

OL

I

mA

OLLED

4.0

–

10

20

–

V

OL = BAT

Current Sense Full-scale Range⁽¹⁸⁾

Notes

I

6.0

A

CS FSR

13. Output current value computed after leakage current removal (open load condition)

14. Parameter guaranteed by design; however it is not production tested.

15. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V_BAT

.

16. OLLED1, bit D0 in SI data is set to [0]

17. OLLED1, bit D0 in SI data is set to [1]

18. For a typical value of I_{CS FSR,}I_{CSNS =}5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

TAIL LIGHT (OUT1) (CONTINUED)

Symbol

Min

Typ

Max

Unit

Current Sense Full-scale Range ⁽¹⁹⁾depending on LED Control = 1

I

–

1.6

–

A

CS FSR_LED

R_SC1(OUT1)

Severe Short-circuit Impedance Range ⁽¹⁹⁾

350

m

LICENSE LIGHT (OUT2)

R

m

Output Drain-to-Source ON Resistance (I

2.8 A, T = 25 °C)

A

DS(ON)

OUT =

–

35

55

V

= 13.5 V

= 7.0 V

BAT

R

Output Drain-to-Source ON Resistance (I_OUT= -2.8 A, V_{BAT =}-13.5 V,

= 25 °C)⁽²⁰⁾

DS(ON)

–

59.5

70

T

A

Reverse Output ON Resistance (I_OUT= 2.8 A, V_{BAT =}12 V, T = 150 °C)⁽²¹⁾

R

m

SD(ON)

A

R

Output Drain-to-Source ON Resistance (I

Control = 1

=1.5 A, T = 25 °C) for LED

A

DS(ON)25_LED

OUT

–

70

V

= 13.5 V

= 7.0 V

110

BAT

R_{DS(ON)150_LED}

m

Output Drain-to-Source ON Resistance (I

1.5 A, V

= 13.5 V,

BAT

OUT =

–

119

T

= 150 °C) for LED Control = 1

A

I

28.0

30.2

35.0

36.0

43.5

41.8

A

High Over-current Shutdown Threshold 1

OCHI1

V

_{BAT =}16 V, T = -40 °C

A

29.4

28.3

35.0

33.8

40.6

39.3

_{BAT =}16 V, T = 25 °C

A

_{BAT =}16 V, T = 125 °C

A

I

12.3

5.7

15.4

7.2

18.5

8.9

A

High Over-current Shutdown Threshold 2

Low Over-current Shutdown Threshold

OCHI2

I

OCLO

Open Load Current Threshold in ON State⁽²²⁾

Open Load Current Threshold in ON State with LED⁽²³⁾

- 0.5 V

I

0.05

0.2

0.5

OL

I

mA

OLLED

4.0

–

10

6.0

1.6

–

20

–

V

OL = BAT

Current Sense Full-Scale Range⁽²⁴⁾

I

A

CS FSR

Current Sense Full-Scale Range⁽²⁰⁾depending on LED Control = 1

I

–

CS FSR_LED

R_SC1(OUT2)

Severe short-circuit impedance range⁽²⁰⁾

350

–

m

Notes

19. Output current value computed after leakage current removal (open load condition)

20. Parameter guaranteed by design; however, it is not production tested.

21. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V

.

BAT

22. OLLED2, bit D0 in SI data is set to [0]

23. OLLED2, bit D0 in SI data is set to [1]

24. For typical value of I

, I

= 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.

CS FSR CSNS

35XS3500

Analog Integrated Circuit Device Data

10

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TAIL LIGHT (OUT3)

Output Drain-to-Source ON Resistance (I

R

m

2.8 A, T = 25 °C)

DS(ON)25

OUT =

A

–

35

55

V

= 13.5 V

= 7.0 V

BAT

R

m

Output Drain-to-Source ON Resistance (I_OUT= 2.8 A, V_{BAT =}13.5 V,

= 150 °C)⁽²⁵⁾

DS(ON)150

–

59.5

70

T

A

R

Reverse Source-to-Drain ON Resistance (I_OUT= -2.8 A, V_{BAT =}-12 V,

= 25 °C)⁽²⁶⁾

SD(ON)25

T

A

R

Output Drain-to-Source ON Resistance (I

Control = 1

1.5 A, T = 25 °C) for LED

A

DS(ON)25_LED

OUT =

–

70

V

= 13.5 V

= 7.0 V

110

BAT

R_{DS(ON)150_LED}

m

Output Drain-to-Source ON Resistance (I

= 150 °C) for LED Control = 1

1.5 A, V

= 13.5 V,

BAT

OUT =

–

119

T

A

I

28.0

30.2

35.0

36.0

43.5

41.8

A

High Over Current Shutdown Threshold 1

OCHI1

V

₌16 V, T = -40 °C

A

BAT

29.4

28.3

35.0

33.8

40.6

39.3

_{BAT =}16 V, T = 25 °C

A

_{BAT =}16 V, T = 125 °C

A

I

12.3

5.7

15.4

7.2

18.5

8.9

A

High Over-current Shutdown Threshold 2

Low Over-current Shutdown Threshold

OCHI2

I

OCLO

Open Load Current Threshold in ON State⁽²⁷⁾

I

0.05

0.2

0.5

OL

Open Load Current Threshold in ON State with LED⁽²⁸⁾

- 0.5 V

I

mA

OLLED

4.0

–

10

6.0

1.6

–

20

–

V

OL = BAT

Current Sense Full-scale Range⁽²⁹⁾

I

A

CS FSR

Current Sense Full-scale Range⁽²⁵⁾depending on LED Control = 1

Severe short-circuit impedance range⁽²⁵⁾

I

–

CS FSR_LED

R_SC1(OUT3)

350

–

m

Notes

25. Parameter guaranteed by design; however, it is not production tested.

26. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V

.

BAT

27. OLLED3, bit D2 in SI data is set to [0]

28. OLLED3, bit D2 in SI data is set to [1]

29. For a typical value of I_{CS FSR,}I_{CSNS =}5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

STOP LIGHT (OUT4)

Output Drain-to-Source ON Resistance (I

R

m

2.8 A, T = 25 °C)

DS(ON)25

OUT =

A

–

35

55

V

= 13.5 V

= 7.0 V

BAT

R

m

Output Drain-to-Source ON Resistance (I_OUT= 2.8 A, V_{BAT =}13.5 V,

= 150 °C)⁽³⁰⁾

DS(ON)150

–

59.5

T

A

R

Output Drain-to-Source ON Resistance (I

Control = 1

1.5 A, T = 25 °C) for LED

A

DS(ON)25_LED

OUT =

–

70

V

= 13.5 V

= 7.0 V

BAT

110

R_{DS(ON)150_LED}

m

A

Output Drain-to-Source ON Resistance (I

=1.5 A, V

= 13.5 V,

BAT

OUT

–

119

70

T

= 150 °C) for LED Control = 1

A

R

Reverse Source-to-Drain ON Resistance (I_OUT= -2.8 A, V_{BAT =}-12 V,

= 25 °C)⁽³¹⁾

DS(ON)25

T

A

I

28.0

30.2

35.0

36.0

43.5

41.8

High Over-current Shutdown Threshold 1

OCHI1

V

₌16 V, T = -40 °C

A

BAT

29.4

28.3

35.0

33.8

40.6

39.3

_{BAT =}16 V, T = 25 °C

A

_{BAT =}16 V, T = 125 °C

A

I

12.3

5.7

15.4

7.2

18.5

8.9

A

High Over-current Shutdown Threshold 2

Low Over-current Shutdown Threshold

OCHI2

I

OCLO

Open Load Current Threshold in ON State⁽³²⁾

I

0.05

0.2

0.5

OL

Open Load Current Threshold in ON State with LED⁽³³⁾

I

mA

OLLED

4.0

–

10

6.0

1.6

20

–

V

- 0.5 V

OL = BAT

Current Sense Full-scale Range⁽³⁴⁾

I

A

CS FSR

Current Sense Full-scale Range⁽³⁰⁾depending on LED Control = 1

Severe Short-circuit Impedance Range⁽³⁰⁾

I

–

CS FSR_LED

R_SC1(OUT4)

350

m

Notes

30. Parameter guaranteed by design; however, it is not production tested.

31. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V

.

BAT

32. OLLED3, bit D2 in SI data is set to [0]

33. OLLED3, bit D2 in SI data is set to [1]

34. For a typical value of I_{CS FSR,}I_{CSNS =}5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.

35XS3500

Analog Integrated Circuit Device Data

12

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

FLASHER (OUT5)

Output Drain-to-Source ON Resistance (I

R

m

2.8 A, T = 25 °C)

DS(ON)25

OUT =

A

–

35

55

V

= 13.5 V

= 7.0 V

BAT

R

m

Output Drain-to-Source ON Resistance (I_OUT= 2.8 A, V_{BAT =}13.5 V,

= 150 °C)⁽³⁵⁾

DS(ON)150

–

59.5

70

T

A

R

Reverse Source-to-Drain ON Resistance (I_OUT= -2.8 A, V_{BAT =}-12 V,

= 25 °C)⁽³⁶⁾

SD(ON)25

T

A

R

Output Drain-to-Source ON Resistance (I

Control = 1

=1.5 A, T = 25 °C) for LED

A

DS(ON)25_LED

OUT

–

70

V

= 13.5 V

= 7.0 V

BAT

110

R_{DS(ON)150_LED}

m

Output Drain-to-Source ON Resistance (I

1.5 A, V

= 13.5 V,

BAT

OUT =

–

119

T

= 150 °C) for LED Control = 1

A

I

28.0

30.2

35.0

36.0

43.5

41.8

A

High Over-current Shutdown Threshold 1

OCHI1

V

₌16 V, T = -40 °C

A

BAT

29.4

28.3

35.0

33.8

40.6

39.3

_{BAT =}16 V, T = 25 °C

A

_{BAT =}16 V, T = 125 °C

A

I

12.3

5.7

15.4

7.2

18.5

8.9

A

High Over-current Shutdown Threshold 2

Low Over-current Shutdown Threshold

OCHI2

I

OCLO

Open Load Current Threshold in ON State⁽³⁷⁾

Open Load Current Threshold in ON State with LED⁽³⁸⁾

- 0.5 V

I

0.05

0.2

0.5

OL

I

mA

OLLED

4.0

–

10

6.0

1.6

–

20

–

V

OL = BAT

Current Sense Full-scale Range⁽³⁹⁾

I

A

CS FSR

Current Sense Full-scale Range⁽³⁵⁾depending on LED Control = 1

Severe Short-circuit Impedance Range⁽³⁵⁾

I

–

CS FSR_LED

R_SC1(OUT5)

350

–

m

Notes

35. Parameter guaranteed by design; however, it is not production tested.

36. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V

.

BAT

37. OLLED3, bit D2 in SI data is set to [0]

38. OLLED3, bit D2 in SI data is set to [1]

39. For a typical value of I_{CS FSR,}I_{CSNS =}5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 3.0 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPARE (FETOUT, FETIN)

V

0.8

–

V_CC

V

FETOUT Output High Level at I = 1.0 mA

FETOUT Output Low Level at I = 1.0 mA

FETIN Input Full Scale Range Current

FETIN Input Clamp Voltage

H MAX

V

0.2

5.0

–

0.4

–

H MIN

I

–

mA

V

FETIN

V

5.3

7.0

CLIN

V

Drop Voltage between FETIN and CSNS for MUX[2:0] = 110

DRIN

0.0

–

0.4

I

5 mA, 5.5 V > CSNS > 0.0 V

FETIN =

I_FETINLEAK

A

FETIN Leakage Current when external current switch sense is enabled

-1.0

–

5.0

1.0

4.5 V > V

3.0 V > V

> 0 V, 5.5 V > VCC > 4.5 V, CSNS open

> 0 V, 4.5 V > VCC > 0, CSNS open

FETIN

TEMPERATURE OF GND FLAG

V

920

1025

11.3

1140

11.7

mV

Analog Temperature Feedback at T_A= 25 °C with 5.0 k > R_CSNS> 500 

T_FEED

Analog Temperature Feedback Derating with 5.0 k > R_CSNS> 500 ⁽⁴⁰⁾

V

10.9

mV/ °C

DT_FEED

Analog Temperature Feedback Precision⁽⁴⁰⁾

V

-15

–

15

°C

DT_ACC

Analog Temperature Feedback Precision with calibration point at 25 °C⁽⁴⁰⁾

V

-5.0

5.0

DT_ACC_CAL

Notes

40. Parameter guaranteed by design; however, it is not production tested.

35XS3500

Analog Integrated Circuit Device Data

14

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.5 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

POWER OUTPUTS TIMING (OUT1:5)

Symbol

Min

Typ

Max

Unit

Current Sense Valid Time on resistive load only⁽⁴¹⁾

s

t_CSNS(VAL)

–

90

45

150

75

SR bit = 0

SR bit = 1

s

t_CSNS(SYNC)

Current Sense Synchronization Time on FETOUT

SR bit = 0

SR bit = 1

–

130

70

185

110

30

Current Sense Settling Time on resistive load only⁽⁴¹⁾

Driver Output Positive Slew Rate (30% to 70% at V

10

s

t_CSNS(SET)

SR

R

V/s

= 14 V)

BAT

0.10

0.20

0.25

0.40

0.56

0.80

SR bit = 0, I

SR bit = 1, I

= 2.8 A

= 0.7 A

OUT

SR

F

V/s

Driver Output Negative Slew Rate (70% to 30% at V

BAT

0.10

0.20

0.25

0.40

0.56

0.80

SR bit = 0, I

SR bit = 1, I

= 2.8 A

= 0.7 A

OUT

SR

Driver Output Matching Slew Rate (SR_R/SR_F)(70% to 30% at V

at 25 °C)

= 14 V

BAT

0.8

1.0

1.2

s

t_DLYON

Driver Output Turn-ON Delay (SPI ON Command [No PWM, CS Positive

Edge] to Output = 50% V at V = 14 V)

BAT

50

25

–

120

65

SR bit = 0, I

= 2.8 A

OUT

SR bit = 1, I

= 0.7 A

OUT

t_DLYOFF

Driver Output Turn-OFF Delay (SPI OFF command [CS Positive Edge] to

Output = 50% V

at V

14 V)

BAT

OUT

BAT =

50

25

–

120

65

SR bit = 0, I

SR bit = 1, I

= 2.8 A

= 0.7 A

t_RF

Driver Output Matching Time (t_DLY(ON)- t_DLY(OFF)) at Output = 50% V

BAT

with V

= 14 V, f

= 240 Hz, 

= 50%, at 25 °C

BAT

PWM

-40

-23

–

20

SR bit = 0, I

SR bit = 1, I

= 2.8 A for OUT1/2/3/4/5

= 0.7 A for OUT1/2/3/4/5

OUT

7.0

Notes

41. Not production tested.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.5 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

PWM MODULE

Nominal PWM Frequency Range⁽⁴⁴⁾

Clock Input Frequency Range

f

30

–

400

Hz

PWM

f

7.68

4.0

–

51.2

96

kHz

%

CLK

Output PWM Duty Cycle maximum range for 11 V<V_BAT<18 V^{(42), (44)}

Output PWM Duty Cycle linear range for 11 V<V_BAT<18 V^{(43), (44)}

PWM_MAX

PWM_LIN

PWM_DIAG

5.5

–

96

%

Output PWM Duty Cycle range for full diagnostic for 11 V<VBAT<18 V⁽⁴⁵⁾

200 Hz Output PWM frequency

5.5

11

–

96

90

400 Hz Output PWM frequency

WATCHDOG TIMING

t

50

–

75

100

30

ms

Watchdog Timeout (SPI Failure)

WDTO

I/O PLAUSIBILITY CHECK TIMING

7.0

s

t_SD

Fault Shutdown Delay Time (from Over-temperature or OCHI1 or OHCI2 or

OCLO Fault Detection to Output = 50%V_BATwithout round shaping feature

for turn off)

Under-voltage Deglitch Time⁽⁴⁶⁾

0.8

1.25

2.0

s

t_UV

t₁

7.0

52.5

3.5

10

75

13.5

97.5

6.5

ms

High Over-current Threshold Time 1

t₂

High Over-current Threshold Time 2

Autorestart Period

75

t_AUTORST

t_{OCSH_AUTO}

5.0

10.0

150

Autorestart Over-current Shutdown Delay Time

Limp Home Input pin Deglicher Time

t

7.0

13.0

195

LIMP

Cyclic Open Load Detection Timing with LED⁽⁴⁷⁾

Flasher Toggle Timeout

105

t_OLLED

t

1.4

1.0

100

2.3

2.0

200

3.0

4.0

400

s

FLASHER

t

Ignition Toggle Timeout

IGNITION

s

t_STOP

Stop Toggle Timeout

f

kHz

Clock Input Low Frequency Detection Range

Clock Input High Frequency Detection Range

Notes

LCLK DET

f

HCLK DET

42. The PWM ratio is measured at V_OUT= 50% of V_BATin nominal range of frequency. It is possible to put the device fully on (PWM duty

cycle = 100%) and fully off (PWN duty cycle = 0%). Between 4%-96%, OCLO_1,2, OCLO and open load are available in ON state. See

Input Timing Switching Characteristics on page 18.

43. Linear range is defined by output duty cycle to SPI duty cycle configuration +/- LSB. For values outside the linear duty cycle range, a

calibration curve is available.

44. Not production tested.

45. Full diagnostic corresponds to the availability of the following features: output current sensing, output status and openload detection.

Not production tested.

46. This time is measured from the V_BAT(UV)level to the fault reporting. Parameter guaranteed in testmode.

47. OLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 9, Serial Input Address

and Configuration Bit Map.

35XS3500

Analog Integrated Circuit Device Data

16

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.5 V  V_CC 5.5 V, 7.0 V  V_BAT 20 V, -40C  T_A 125C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25C under nominal conditions, unless otherwise noted.

Characteristic

SPI INTERFACE CHARACTERISTICS

Symbol

Min

Typ

Max

Unit

f_SPI

t_CS

–

3.0

1.0

MHz

us

Maximum Frequency of SPI Operation

Rising Edge of CS to Falling Edge of CS (Required Setup Time)⁽⁴⁸⁾

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)⁽⁴⁸⁾

Required High State Duration of SCLK (Required Setup Time)⁽⁴⁸⁾

Required Low State Duration of SCLK (Required Setup Time)⁽⁴⁸⁾

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)⁽⁴⁸⁾

SI to Falling Edge of SCLK (Required Setup Time)⁽⁴⁹⁾

t_LEAD

t_WSCLKH

t_WSCLKl

t_LAG

–

500

167

83

ns

–

50

25

t_SISU

Falling Edge of SCLK to SI (Required Setup Time)⁽⁴⁹⁾

t_SIHOLD

t_RSO

83

SO Rise Time

C_L= 80 pF

–

25

50

t_FSO

ns

SO Fall Time

C_L= 80 pF

–

25

–

50

SI, CS, SCLK, Incoming Signal Rise Time⁽⁵⁰⁾

SI, CS, SCLK, Incoming Signal Fall Time⁽⁵⁰⁾

Time from Falling Edge of CS to SO Low-impedance⁽⁵¹⁾

t_RSI

t_FSI

t_SO(EN)

t_SO(DIS)

ns

–

50

145

Time from Rising Edge of CS to SO High-impedance⁽⁵²⁾

65

Notes

48. Maximum setup time required for the 35XS3500 is the minimum guaranteed time needed from the microcontroller.

49. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

50. Time required for output status data to be available for use at SO. 1.0 kon pull-up on CS.

51. Time required for output status data to be terminated at SO. 1.0 kon pull-up on CS.

52. Time required to obtain valid data out from SO following the rise of SCLK.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

VIL

V_IL

TwRSTB

t_CS

t_ENBL

TCSB

TENBL

VIH

V_IH

90% V

0.7VDD

CC

CCSB

10.07%VDVD

CC

VIL

V_IL

t_RSI

Tt_WwS_SC_CL_LK_Kh_H

TrSI

tTlead

LEAD

t_LAG

Tlag

VIH

V_IH

90% V_CC

0.7VDD

SCLK

10% V_CC

0.2VDD

VIL

V_IL

t_STS_I(SIs_Uu₎

t

TwSCLKl

WSCLKL

TfSI

t_FSI

t

TSI(hold)

SI(HOLD)

VIH

V_IH

900.7%VDVD

CC

Don’t Care

Valid

SI

01.02V%DDV_CC

V

VIL

IL

Figure 4. Input Timing Switching Characteristics

t_RSI

t_FSI

TrSI

TfSI

VOH

V_OH

2.0 V

3.5V

50%

SCLK

1.0V

0.8 V

VOL

V_OL

t_SO(EN)

TdlyLH

0.210V%DDV_CC

VOH

V_OH

90% V

0.7 VD_CD_C

SO

VOL

V_OL

Low-to-High

Low to High

TrSO

t_RSO

T

t_V^V_A^A_L^L_I^ID_D

TfSO

t_FSO

SO

V_OH

VOH

90% V

0.7 VDD_CC

High to Low

High-to-Low

0.2VDD

10% V_CC

VOL

V_OL

TdlyHL

t_SO(DIS)

Figure 5. SCLK Waveform and Valid SO Data Delay Time

35XS3500

Analog Integrated Circuit Device Data

18

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

CS

High logic level

Low logic level

Time

V_OUT[1:5]

V

PWR

R

PWM

50%V

PWR

Time

t_DLY(OFF)

t_DLY(ON)

V_OUT[1:5]

70% V

PWR

SR_F

SR_R

30% V

PWR

Time

Figure 6. Output Slew Rate and Time Delays

CS

High logic level

Low logic level

Time

I_OUT[1:5]

I

MAX

t_DLY(OFF)

t_DLY(ON)

t_CSNS(VAL)

t_CSNS(SET)

I_CSNS

Time

V_FETOUT

t_CSNS(SYNC)

High logic level

with CSNS sync bit = 1

Low logic level

Time

Figure 7. Current Sensing Time Delays

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 35XS3500 is designed for low-voltage automotive and

industrial lighting applications. Its five low R_DS(ON)MOSFETs

resistive loads (bulbs). Programming, control, and

diagnostics are accomplished using a 16-bit SPI interface.

(five 35 m) can control the high sides of five separate

FUNCTIONAL PIN DESCRIPTION

The amplitude of the input current is divided by four while

the frequency is four times the original one. The two following

pictures illustrate the behavior.

Supply Voltage (VBAT)

The VBAT pin of the 35XS3500 is the power supply of the

device. In addition to its supply function, this tab contributes

to the thermal behavior of the device by conducting the heat

from the switching MOSFETs to the printed circuit board.

Ch.1

Ch.2

Ch.3

Ch.4

Supply Voltage (VCC)

This is an external voltage input pin used to supply the SPI

digital portion of the circuit and the gate driver of the external

SMART MOSFET.

Total

Ground (GND)

0°

90°

180°

270°

0°

This pin is the ground of the device.

Clock Input (CLOCK) and PWM Module

When the part is in Normal Mode (RST=1), the PWM

frequency and timing are generated from the rising edge of

clock input by the PWM module. The clock input frequency is

the selectable factor 2⁷= 128 or 2⁸= 256 of the PWM

Ch.1

Ch.2

Ch.3

Ch.4

frequency per output, depending PR bit value.

The OUT1:6 can be controlled in the range of 4% to 96%

with a resolution of 7 bits of duty cycle (bits D[6:0]).

Total

The following table describes the PWM resolution.

0°

90°

180°

270°

0°

On/Off(Bit

D7)

Duty cycle (7 bits

resolution)

Output state

The synchronization of the switching phases between

different corner light IC is provided by a SPI command in

combination with the CS input. The bit in the SPI is called

PWM sync (initialization register).

0

1

X

OFF

0000000

0000001

0000010

1111111

PWM (1/128 duty cycle)

PWM (2/128 duty cycle)

PWM (3/128 duty cycle)

fully ON

In Normal mode, No PWM feature (100% duty cycle) is

provided in the following instances:

• with the following SPI configuration: D7:D0=FF.

• In case of clock input signal failure (out of f_PWM), the

outputs state depends on the D7 bit value (D7=1+ON)

in Normal mode.

Table 6. PWM Resolution

The timing includes four programmable PWM switching

phases (0°, 90°, 180°, and 270°) to improve overall EMC

behavior of the light module.

In Fail mode. The outputs state depends on the IGN,

STOP and Flasher pins.

If RST=0, this pin reports the wake-up event for wake=1

when VBAT and VCC are in operational voltage range.

35XS3500

Analog Integrated Circuit Device Data

20

Freescale Semiconductor

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Limp Home (LIMP)

FETOUT Output (FETOUT)

This output pin is used to control an external MOSFET

The Limp Home mode of the component can be activated

by this digital input port. The signal is “high active”, meaning

the Fail mode can be activated by a logic high signal at the

input.

(OUT6).

The high level of the FETOUT Output is VCC if V_BATand

V_CCare available in case of FETOUT is controlled ON.

Ignition Input (IGN)

FETOUT is not protected in case of a short-circuit or

under-voltage on V_BAT

.

The Ignition input wakes the device. It also controls the

Fail Home mode activation. The signal is “high active”,

meaning the component is active in case of a logic high at the

input.

In case of a reverse battery, OUT6 is OFF.

FETIN Input (FETIN)

This input pin gives the current recopy of the external

MOSFET. It can be routed on the CSNS output by a SPI

command.

Flasher Input (FLASHER)

The Flasher input wakes the device. It also controls the

Fail mode activation. The signal is “high active”, meaning the

component is active in case of a logic high at the input.

SPI Protocol Description

The SPI interface has a full-duplex, three-wire

synchronous data transfer with four I/O lines associated with

it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),

and Chip Select (CS).

Reset Input (RST)

This input wakes the device when the RST pin is at

logic [1]. It is also used to initialize the device configuration

and the SPI fault registers when the signal is low. All SI/SO

registers described in Table 9 and Table are reset. The fault

management is not affected by RST (see Figure 2).

The SI/SO pins of the 35XS3500 device follow a first-in,

first-out (D15 to D0) protocol, with both input and output

words transferring the most significant bit (MSB) first. All

inputs are compatible with 5.0 V CMOS logic levels supplied

Current Sense Output (CSNS)

by V_CC

.

The current sense output pin is an analog current output or

a voltage proportional to the temperature on the GND flag.

The routing to the common resistor is SPI programmable.

The SPI lines perform the following functions:

Serial Clock (SCLK)

This current sense monitoring may be synchronized in

case of the OUT6 is not used. So, the current sense

monitoring can be synchronized with a rising edge on the

FETOUT pin (t_CSNS(SYNC)) if CSNS sync SPI bit is set to logic

The SCLK pin clocks the internal shift registers of the

35XS3500 device. The SI pin accepts data into the input shift

register on the falling edge of the SCLK signal, while the SO

pin shifts data information out of the SO line driver on the

rising edge of the SCLK signal. It is important that the SCLK

pin be in a logic low state whenever CS makes any transition.

For this reason, it is recommended that the SCLK pin be in a

logic [0] whenever the device is not accessed (CS logic [1]

state). SCLK has a passive pull-down, R_DWN. When CS is

[1]. Connection of the FETOUT pin to a MCU input pin allows

the MCU to sample the CSNS pin during a valid time-slot.

Since this falling edge is generated at the end of this timeslot,

upon a switch-off command, this feature may be used to

implement maximum current control.

logic [1], signals at the SCLK and SI pins are ignored and SO

is tri-stated (high-impedance) (see Figure 8).

Charge Pump (CP)

An external capacitor is connected between this pin and

the VBAT pin. It is used as a tank for the internal charge

pump. Its typical value is 100 nF ±20%, 25 V maximum.

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

CS

CSB

CS

SCLK

SI

D15

D14

D13

D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SO

OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

Notes

NOTES: 1. RSTB is in a logic H state during the above operation.

1. D15:D0 relate to the most recent ordered entry of data into the device.

device.

2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC

3

2. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.

device.

OD0 OD1 OD2

and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC

Figure 8. Single 16-Bit Word SPI Communication

Serial Input (SI)

Chip Select (CS)

The SI pin is a serial interface command data input pin.

Each SI bit is read on the falling edge of SCLK. A 16-bit

stream of serial data is required on the SI pin, starting with

The CS pin enables communication with the master

device. When this pin is in a logic [0] state, the device is

capable of transferring information to, and receiving

D15 to D0. SI has a passive pull-down, R_DOWN

.

information from, the master device. The 35XS3500 device

latches in data from the Input Shift registers to the addressed

registers on the rising edge of CS. The device transfers

status information from the power output to the Shift register

on the falling edge of CS. The SO output driver is enabled

when CS is logic [0]. CS should transition from a logic [1] to a

logic [0] state only when SCLK is a logic [0]. CS has a

Serial Output (SO)

The SO data pin is a tri-state output from the shift register.

The SO pin remains in a high-impedance state until the CS

pin is put into a logic [0] state. The SO data is capable of

reporting the status of the output, the device configuration,

and the state of the key inputs. The SO pin changes state on

the rising edge of SCLK and reads out on the falling edge of

SCLK.

passive pull-up, R_UP

.

STOP Input (STOP)

The STOP input wakes the device. It also controls the Fail

mode activation. The signal is “high active“, meaning the

component is active in case of a logic high at the input.

35XS3500

Analog Integrated Circuit Device Data

22

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

The following figure describes the PWM, outputs and over-

current behavior in Normal mode.

Sleep Mode

The Sleep mode is the default mode of the 35XS3500.

This is the state of the device after first applying battery

voltage (V_BAT) and prior to any I/O transitions. This is also the

D7 bit

state of the device when IGN, RST, FLASHER, and STOP

are logic [0]. In the Sleep mode, the output and all internal

circuitry are OFF to minimize current draw. In addition, all

SPI-configurable features of the device are reset. The

35XS3500 will transit to two modes (Normal and Fail)

depending on wake and fail signals (see Table 18).

D0-D6 bits

Output

Over-current

The transition to the other modes is according to the

following signals:

• Wake = IGN or IGN_ON or FLASHER or

FLASHER_ON or STOP or STOP_ON or RST

• Fail = VCC fail or SPI fail or External limp

Fail Mode

The 35XS3500 is in Fail mode when:

• Wake = 1

Normal Mode

• Fail = 1

The 35XS3500 is in Normal mode when:

In Fail mode:

• The outputs are under control of the external pins (see

Table 6).

• The outputs are fully protected in case of overload,

over-temperature and under-voltage (on B_VATor on

V_CC).

• Wake = 1

• Fail = 0

In Normal operating mode the power outputs are under full

control of the SPI as follows:

• The outputs 1 to 6, including multiphase timing, and

selectable slew-rate, are controlled by the

programmable PWM module.

• The output 4 is activated directly by the STOP external

pin in case the STOP_en bit is set to a logic [1].

• The outputs 1 to 5 are switched OFF in case of under-

voltage on VBAT.

• The SPI reports continuously the content of address 11,

disregard to previous requested output data word.

• Neither digital diagnosis feature (SPI) nor analog

current sense are available.

• In case of overload (OCHI2 or OCLO) conditions or

under-voltage on VBAT, the outputs are under control

of the autorestart feature.

• The outputs 1 to 5 are protected by the selectable over-

current double window and over-temperature shutdown

circuit.

• In case of a serious overload condition (OCHI1 or OT)

the corresponding output is latched OFF until a new

wake-up event (wake = 0 then 1)

• The digital diagnosis feature transfers status of the

smart outputs via the SPI.

• The analog current sense output (current recopy

feature) can be rerouted by the SPI.

IGN_ON

1.4 sec min

IGN (external)

• The outputs can be configured to control LED loads:

R_DS(ON)is increased by a factor of 2 and the current

recopy ratio is scaled by a factor of 4.

OUT[1,2]

• The SPI reports NM=1 in this mode.

Over-current

Table 7. Limp Home Output State

Output 1

Tail Light

Output 2

License Light

Output 3

Rear Drive Light

Output 4

Stop Light

Output 5

Flasher

External Switch

Rear Fog Light

IGN Pin

OFF

STOP Pin

FLASHER Pin

OFF

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

The Autorestart is not limited in time.

Autorestart Strategy

The autorestart circuitry is used to supervise the outputs

and reactivate high side switches in case of overload or

under-voltage failure conditions, and provide a high

availability of the outputs.

Transition Fail to Normal Mode

To leave the Fail mode, the fail condition must be removed

(fail=0). The microcontroller has to toggle the SPI D10 bit (0

to 1) to reset to the watchdog bit; the other bits are not

considered. The previous latched faults are reset by the

transition into Normal mode.

This autorestart is available in Fail mode when no

supervising intelligence of the microcontroller is available.

Autorestart is activated in case of an overload condition

(OCHI2 or OCLO) or under-voltage condition on VBAT (Table

9, Over-current window in case of Autorestart).

Transition Normal to Fail Mode

To leave the Normal mode, a fail condition must occur

(fail=1). The previous latched faults are reset by the transition

into Fail mode.

The autorestart switches ON the outputs. During the ON

state of the switch OCHI1, the window is enabled for

tochi_Auto, then after the output is protected by OCLO.

If the SI is shorted to VCC, the device transmits to Fail

Safe mode until the WD bit toggles through the SPI (from [0]

to [1]).

Output current

All settings are according to predefined values (all bits set

to logic [0]).

OCHI1

START-UP SEQUENCE

The 35XS3500 enters into Normal mode after start-up if

the following sequence is provided:

OCLO or UV fault

• V_BATand V_CCpower supplies must be above their

under-voltage thresholds (Sleep mode).

• Generate a wake-up event (wake=1) from 0 to 1 on

RST. The device switches to Normal mode.

• Apply the PWM clock after a maximum of 200 s (min.

50 s).

• Send a SPI command to the device status register to

clear the clock fail flag and enable the PWM module to

start.

OCLO

tochi_auto

time

Auto period

Figure 9. Over-current window in case of Autorestart

In case of OCHI1 or OT, the switch is latched OFF until

wake up (wake=0, then 1).

If the correct startup sequence is not provided, the PWM

function is not guaranteed.

In case of OCLO or under-voltage, the output switch is

OFF. After the autorestart period (75 ms) is turned ON again.

Figure 10 describes the wake-up block diagram.

POWER OFF MODE

In case an under-voltage occurred in Fail mode, it will be

latched and delatched after the auto restart period

(t_AUTORST).

The 35XS3500 is in Power OFF mode when the battery

voltage is below V_BATPOR[1,2]thresholds. For more details,

please refer to Loss of VBAT paragraph.

35XS3500

Analog Integrated Circuit Device Data

24

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

(fail=0) and (wake=1)

Sleep

(wake=0)

(wake=1) and (fail=1) *

(wake=0)

V_{BAT <}V_BATPOR[1,2]

V_{BAT >}V_BATPOR[1,2]

V_{BAT <}V_BATPOR[1,2]

Power OFF

V_{BAT <}V_BATPOR[1,2]

Normal

Fail

(fail=0) and (wake=1)

(fail=1) and (wake=1)

Notes:

* only available in case of V_CCfail condition

wake=(RST=1) OR (IGN_ON=1) OR (Flasher_ON=1) OR (Stop_ON=1)

fail=(V_CC_fail=1) OR (SPI_fail=1) OR (ext_limp=1)

Figure 10. Operating Modes State Machine

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

VBAT

wake

VBAT

VCC

Wake-up bar

Internal

regulator

IGN

IGN_ON

Deglitcher

Dig2.5V

Flasher_ON

FLASHER

Deglitcher

Oscillator

Fog_ON

FOG

Fault

management

PWM freq

detector

Deglitcher

SPI registers

PWM module

VCC fail

OR

SPI fail

External

Limp

reset

RST

Fail

VCC

OR

CLOCK

UVF

1.4 sec min

external

external_ON

external: IGN, FLASHER, FOG

external_ON: IGN_ON, FLASHER_ON, FOG_ON

Figure 11. Wake-up Block Diagram

35XS3500

Analog Integrated Circuit Device Data

26

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS



Serial Input Communication

Table 8. SI Message Bit Assignment

SPI communication compliant to 3.3 and 5.0 V is

Bit Sig SI Msg Bit

Message Bit Description

Register address bits.

accomplished using 16-bit messages. A message is

transmitted by the master starting with the MSB, D15, and

ending with the LSB, D0. Each incoming command message

on the SI pin can be interpreted using the bit assignment

described in Table 8. The 5 bits D15:D11, called register

address bits, are used to select the command register. Bit

D10 is the watchdog bit. The remaining 10 bits, D9:D0, are

used to configure and control the output and its protection

features. Multiple messages can be transmitted in

MSB

D15:D11

D10

Watchdog in: toggled to satisfy watchdog

requirements.

LSB

D9:D0

Used to configure inputs, outputs, device

protection features, and SO status content.

succession to accommodate those applications where daisy

chaining is desirable or to confirm transmitted data as long as

the messages are all multiples of 16 bits. Any attempt made

to latch in a message that is not 16 bits will be ignored.

Device Register Addressing

The register addresses (D15:D11) and the impact of the

serial input registers on device operation are described in this

section. Table 9 summarizes the content of the SI registers.

All SPI registers are reset (all bits equal 0) in case of RST

equals 0 or fail mode (Fail=1).

Table 9. Serial Input Address and Configuration Bit Map

SI Address

SI Data

SI Register

D1 D1 D1 D1 D1

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

5

4

3

2

1

Initializatio

n

PWM

sync

0

WD

0

STOPen

LED

0

MUX2

MUX1

MUX0

SOA1

SOA0

LED

Config OL

0

1

WD

OLLED5 OLLED4 OLLED3 OLLED2 OLLED1

Control Control

2

Control5 Control4 Control3

1

Config

Prescaler

0

1

0

1

WD

0

1

PR1

SR1

0

PR2

SR2

0

PR3

0

PR4

SR4

PR5

SR5

PR6

0

Config SR

SR3

0

Config

CSNS

sync

NO_OC NO_OC NO_OC NO_OC NO_OC

HI5

HI4

HI3

HI2

HI1

Control

OUT1

0

1

0

1

0

1

0

1

0

1

0

1

WD Phase2 Phase1

ONoff

PWM6 PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

Control

OUT2

PWM4

PWM3

PWM2

PWM1

PWM0

Control

OUT3

Control

OUT4

Control

OUT5

Control

External

Switch

0

1

0

WD Phase2 Phase1

ONoff

PWM6 PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 9. Serial Input Address and Configuration Bit Map

RESET

X

0

Note: testmode address used only by FSL is D[15:11]=01111 with RST voltage higher than 8.0 V typ.

The watchdog timeout is specified by the t

ADDRESS 00000—Initialization

WDTO

parameter. As long as the WD bit (D10) of an incoming SPI

message is toggled within the minimum watchdog timeout

period (WDTO), the device will operate normally. If an

internal watchdog timeout occurs before the WD bit is

toggled, the device will revert to Fail mode. All registers are

cleared. To exit the Fail mode, send valid SPI communication

with WD bit = 1.

The Initialization register is used to read the various

statuses, choose one of the six outputs current recopy,

enable the STOP pin, and synchronize the switching phases

between different corner light devices. The register bits D1

and D0 determine the content of the 16 bits of SO data.

(Refer to the section entitled Serial Output Communication

(Device Status Return Data)) Bits D9:D2 are described in

Table .

Table 10. Initialization Register

SI Address

SI Data

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

PWM

sync

0

WD

0

STOPen

0

MUX2 MUX1 MUX0 SOA1 SOA0

x = Don’t care

D6 (PWM sync) = 0, No synchronization

D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense

D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense

D4, D3, D2 (MUX2, MUX1, MUX0) = 010,current sense

D6 (PWM sync) = 1, Synchronization on CSB positive edge

D7 (STOPen) = 0, STOP pin does not control the output 4.

D7 (STOPen) = 1, STOP pin controls the output 4.

D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense

D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense

D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense

D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current sense

D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog

feedback

ADDRESS 00001—Configuration OL

ADDRESS 00010—CONFIGURATION PRESCALER

AND SR

The Configuration OL register is used to enable the open

load detection for LEDs in Normal mode (OLLEDn in Table 9)

and to active the LED Control.

Two configuration registers are available at this address.

The Configuration Prescaler when D9 bit is set to logic [0] and

Configuration SR when D9 bit is set to logic [1].

When bit D0 is set to logic [1], the open load detection

circuit for LED is activated for output 1. When bit D0 is set to

logic [0], open load detection circuit for standard bulbs is

activated for output 1.

The Configuration Prescaler register is used to enable the

PWM clock prescaler per output. When the corresponding

PR bit is set to logic [1], the clock prescaler (reference clock

divided by 2) is activated for the dedicated output.

When bit D5 is set to logic [1], the LED Control is activated

for output 1.

The SR Prescaler register is used to increase the output

slew-rate by a factor of 2. When the corresponding SR bit is

set to logic [1], the output switching time is divided by 2 for the

dedicated output.

35XS3500

Analog Integrated Circuit Device Data

28

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

ADDRESS 00011—CONFIGURATION CSNS

ADDRESS 01101—Control OUT5

The Configuration Current Sense register is used

todisable the high over-current shutdown phase (OCHI1 and

OCHI2 dynamic levels) in order to activate immediately the

current sense analog feedback.

Same description as OUT1.

ADDRESS 01110—Control External Switch

Same description as OUT1.

When bit D9 is set to logic [1], the current sense

synchronization signal is reported on FETOUT output pin.

ADDRESS 01111 —Test Mode

When the corresponding NO_OCHI bit is set to logic [1],

the output is only protected with OCLO level. And the current

sense is immediately available if it is selected through SPI, as

described in Figures 13. The NO_OCHI bit per output is

automatically reset at each corresponding ON off bit

transition from logic [1] to [0] and in case of over-temperature

or over-current fault. All NO_OCHI bits are also reset in case

of under-voltage fault detection.

This register is reserved for test and is not available with

the SPI during normal operation.

Serial Output Communication (Device Status

Return Data)

When the CS pin is pulled low, the output register is

loaded. Meanwhile, the data clocks out the MSB first as the

new message data is clocked into the SI pin. The first 16 bits

of data clocking out of the SO, and following a CS transition,

is dependant upon the previously written SPI word (SOA1

and SOA0 defined in the last SPI initialization word).

ADDRESS 01001—Control OUT1

Bits D9 and D8 control the switching phases as shown in

Table 11.

Any bits clocked out of the SO pin after the first 16 will be

representative of the initial message bits clocked into the SI

pin, since the CS pin first transitioned to a logic [0]. This

feature is useful for daisy chaining devices.

Table 11. Switching Phases

D9:D8

00

PWM Phase

0°

01

90°

A valid message length is determined following a CS

transition of logic [0] to logic [1]. If the message length is

valid, the data is latched into the appropriate registers. A valid

message length is a multiple of 16 bits. At this time, the SO

pin is tri-stated and the fault status register is now able to

accept new fault status information.

10

180°

270°

11

Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF

with bit D7 at logic [0]. This register allows the master to

control the duty cycle and the switching phases of OUT1. The

duty cycle resolution is given by bits D6:D0.

The output status register correctly reflects the status of

the Initialization-selected register data at the time that the CS

is pulled to a logic [0] during SPI communication and/or for

the period of time since the last valid SPI communication,

with the following exceptions:

D7 = 0, D6:D0 = XX output OFF.

D7 = 1, D6:D0 = 00 output ON during 1/128.

• The previous SPI communication was determined to be

invalid. In this case, the status will be reported as

though the invalid SPI communication never occurred.

• Battery transients below 6.0 V, resulting in an under-

voltage shutdown of the outputs, may result in incorrect

data loaded into the SPI register, except the UVF fault

reporting (OD13).

D7 = 1, D6:D0 = 1 A output ON during 27/128 on PWM

period.

D7 = 1, D6:D0 = 7 F output continuous ON (no PWM).

ADDRESS 01010—Control OUT2

Same description as OUT1.

Serial Output Bit Assignment

ADDRESS 011111—Control OUT3

The contents of bits OD15:OD0 depend on bits D1:D0

from the most recent initialization command SOA[1:0] (refer

to Table 12), as explained in the paragraphs that follow.

Same description as OUT1.

ADDRESS 01100—Control OUT4

The register bits are reset by a read operation and also if

the fault is removed.

Same description as OUT1.

Table 12 summarizes the SO register content. Bit OD10

reflects Normal mode (NM).

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 12. Serial Output Bit Map Description

SI Data

Status/

Mode

SO SO OD1 OD1

OD1

2

OD1

0

OD13

OD11

OD9 OD8 OD7 OD6 OD5 OD4

OD3

OD2

OD1 OD0

A1 A0

5

4

Output

Status

0

1

0

1

0

UVF OTW OTS NM OL5 OVL5 OL4 OVL4 OL3 OVL3 OL2

UVF OTW OTS NM OC5 OTS5 OC4 OTS4 OC3 OTS3 OC2

OVL2

OL1 OVL1

Overloa

d Status

0

1

0

OTS2

OC1 OTS1

CLOC

K fail

Device

Status

UVF OTW OTS NM

0

OV STOP IGN_ FLAS RC

STOP FLASHER IGN

OUT3

0

_ON

ON HER_

ON

OUT5

0

OUT4

OUT2 OUT1

Output

Status

1

0

1

0

X

Reset

X

0

1

0

Previous Address SOA[1:0]=00

If the previous two LSBs are 00, bits OD15:OD0 reflect the

output status (Table 13).

Table 13. Output Status

OD15 OD14 OD13 OD12 OD11 OD10

UVF OTW OTS NM

OD9

OD8

OD7

OD6

OVL4

OD5

OD4

OD3

OD2

OD1

OD0

0

OL5

OVL5

OL4

OL3

OVL3

OL2

OVL2

OL1

OVL1

OD13 (UVF) = Under-voltage Flag on V_BAT

OD9, OD7, OD5, OD3, OD1 (OL5, OL4, OL3, OL2, OL1) = Open Load

Flag at Outputs 5 through 1, respectively.

OD12 (OTW) = Over-temperature Prewarning Flag

OD11 (OTS) = Over-temperature Flag for all outputs

OD10 (NM) = Normal mode

OD8, OD6, OD4, OD2, OD0 (OVL5, OVL4, OVL3, OVL2,

OVL1) = Overload Flag for Outputs 5 through 1, respectively.This

corresponds to over-temperature or OCHI or OCLO faults.

Note

A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].

OVL=OCHI1+OCHI2+OCLO

Previous Address SOA[1:0]=01

If the previous two LSBs are 01, bits OD15:OD0 reflect

reflect the temperature status (Table 14).

Table 14. Overload Status

OD15 OD14 OD13 OD12 OD11 OD10

UVF OTW OTS NM

OD9

OD8

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

0

1

OC5

OTS5

OC4

OTS4

OC3

OTS3

OC2

OTS2

OC1

OTS1

OD13 (UVF) = Under-voltage Flag on V_BAT

OD9, OD7, OD5, OD3, OD1 (OC5, OC4, OC3, OC2, OC1) = High

Over-current Shutdown Flag for Outputs 5 through 1, respectively

OD12 (OTW) = Over-temperature Prewarning Flag

OD11 (OTS) = Over-temperature Flag for all outputs

OD10 (NM) = Normal mode

OD8, OD6, OD4, OD2, OD0 (OTS5, OTS4, OTS3, OTS2,

OTS1) = Over-temperature Flag for Outputs 5 through 1, respectively

Note

A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].

OC=OCHI1+OCHI2

Previous Address SOA[1:0]=10

If the previous two LSBs are 01, bits OD15:OD0 reflect the

status of the 35XS3500 (Table 15).

35XS3500

Analog Integrated Circuit Device Data

30

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 15. Device Status

OD15 OD14 OD13 OD12 OD11 OD10

UVF OTW OTS NM

OD9

OD8

OD7

STOP_ IGN_ON FLASH

ON ER_ON

OD6

OD5

OD4

OD3

OD2

OD1

OD0

STOP FLASH

ER pin

1

0

OV

RC

IGN pin CLOCK

fail

OD13 (UVF) = Under-voltage Flag on V_BAT

OD6 = Indicates the state of internal IGN_ON signal

OD5 = Indicates the state of internal FLASHER_ON signal

OD12 (OTW) = Over-temperature Prewarning Flag

OD11 (OTS) = Over-temperature Flag for all outputs

OD10 (NM) = Normal mode

OD4 (RC) = Logic [0] indicates a Front Corner Light Switch. Logic [1]

indicates a Rear Corner Light Switch

OD3 (STOP pin) = Indicates the STOP pin state in real time

OD2 (FLASHER pin) = Indicates the FLASHER pin state in real time

OD1 (IGN pin) = Indicates the IGN pin state in real time

OD0 (CLOCK fail) = Logic [1], which indicates a clock failure

OD8 (Over-voltage) = Over-voltage Flag on V_BATin real time

OD7 = Indicates the state of internal STOP_ON signal, as described

in Figures 11

Previous Address SOA[1:0]=11

If the previous two LSBs are 11, bits OD15:OD0 reflect the

status of the 35XS3500 (Table 15).

Table 16. Output Status

OD15 OD14 OD13 OD12 OD11 OD10

UVF OTW OTS NM

OD9

OD8

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

OUT1

OUT4

OUT3

1

0

X

OUT5

OUT2

OD3 (OUT4) = Logic [0] indicates the OUT4 voltage is lower than

_{OUT_TH}. Logic [1] indicates the OUT4 voltage is higher than V_{OUT_TH}

OD13 (UVF) = Under-voltage Flag on V_BAT

V

OD12 (OTW) = Over-temperature Prewarning Flag

OD11 (OTS) = Over-temperature Flag for all outputs

OD10 (NM) = Normal mode

OD2 (OUT3) = Logic [0] indicates the OUT3 voltage is lower than

_{OUT_TH}. Logic [1] indicates the OUT3 voltage is higher than V_{OUT_TH}

V

OD1 (OUT2) = Logic [0] indicates the OUT2 voltage is lower than

_{OUT_TH}. Logic [1] indicates the OUT2 voltage is higher than V_{OUT_TH}

OD4 (OUT5) = Logic [0] indicates the OUT5 voltage is lower than

_{OUT_TH}. Logic [1] indicates the OUT5 voltage is higher than

V

OD0 (OUT1) = Logic [0] indicates the OUT5 voltage is lower than

V_{OUT_TH}

V

_{OUT_TH}. Logic [1] indicates the OUT1 voltage is higher than V_{OUT_TH}

latched and reported via the SPI. To delatch the fault and be

able to turn the outputs ON again, the failure condition must

be removed (T< 175 °C typically) and:

Protection and Diagnosis

Output Protection Features

• if the device was in Normal mode, the output

corresponding register (bit D7) must be rewritten. 

Application of the complete OCHI window

(OCHI1+OCHI2 during t2) depends on toggling or not

toggling D7 bit.

• if the device was in Fail mode, the corresponding output

is locked until device restart: wake up from Sleep mode

The 35XS3500 provides the following protection features:

• Protection against transients on V_BATsupply line (per

ISO 7637)

• Active clamp, including protection against negative

transients on output line

• Over-temperature

or V_BATPOR1

.

• Severe and resistive over-current

• Open Load during ON state

The SPI fault report (OTS bit) is removed after a read

operation.

These protections are provided for each output (OUT1:5).

Over-current detections

Over-temperature detection

The 35XS3500 provides intelligent over-current shutdown

(see Figure 12) in order to protect the internal power

transistors and the harness in the event of overload (fuse

characteristic).

The 35XS3500 provides over-temperature shutdown for

each output (OUT1:OUT5). It can occur when the output pin

is in the ON or OFF state. An over-temperature fault condition

results in turning OFF the corresponding output. The fault is

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

• if the device was in Normal mode: the output

corresponding register (bit D7) must be rewritten D7=1.

Application of complete OCHI window depends on

toggling or not toggling D7 bit.

• if the device was in Fail mode, the failure is locked until

restart of the device: wake-up from Sleep mode or

Output current

OCHI1

V_BATPOR1

.

For OCHI2 and OCLO:

OCHI2

OCLO

• if the device was in Normal mode: the output

corresponding register (bit D7) must be rewritten D7=1.

Application of complete OCHI window depends on

toggling or not toggling D7 bit.

• if the device was in Fail mode, autorestart is activated.

The device autorestart feature provides a fixed duty

cycle and fixed period with OCHI1 window.

autorestart feature resets OCHI2 or OCLO fault after

corresponding Autorestart period.

t1

time

t2

Figure 12. Double Over-current Window in Normal Mode

OCHI (I_OCHI1and then I_OCHI2) is only activated after

The SPI fault reports are removed after a read operation:

- OC bit=(OCHI1) or (OCHI2) fault

toggling the D7 bit in Normal mode. During the output

switching, the severe short-circuit condition provided on the

module connector is reported as an OCHI fault. In Fail mode,

the control of OCHI window is provided by the toggles:

IGN_ON, Flasher_ON. The current thresholds (I_OCHI1, I_OCHI2

- OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault

Over-voltage detection and active clamp

and I_OCLO) and the time (t₁and t₂) are fixed numbers for each

driver. After t_2,the OCLO current threshold is set to protect in

steady state. t₁and t₂times are compared to “on” state

duration (t_ON) of the output. In case of the output is controlled

in PWM mode during the inrush period, the t_ONcorresponds

The 35XS3500 provides an active gate clamp circuit, in

order to limit the maximum drain to source voltage.

In case of overload on an output, the corresponding switch

(OUT[1 to 5]) is turned off which leads to a high voltage at

VBAT, with an inductive V_BATline. The maximum VBAT

to the sum of each “on” state duration in order to expand

dynamically the transient over-current profile.

voltage is limited at V_BATCLAMPby active clamp circuitry

through the load. In case of open load condition, the positive

transient pulses (ISO 7637 pulse 2 and inductive battery line)

shall be handled by the application.

In case of an overload (OCHI1 or OCHI2 or OCLO

detection), the corresponding output is disabled immediately.

The fault is latched and the status is reported via the SPI. To

delatch the fault, the failure condition must be removed and:

Figures 13 and 14 describe the faults management in

Normal mode and Fail mode.

For OCHI1:

35XS3500

Analog Integrated Circuit Device Data

32

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

(OCHI2=1) or (OT=1) or (UV=1) or (D7=0)

Note: t1 and t2 please refer to Figure 12.

t₁<t_ON<t₂and (NO_OCHI=0)

without fault

(OCHI1=1) or (OT=1) or (UV=1) or (D7=0)

D7=0 then 1 without fault

and (NO_OCHI=0)

t_ON=t₁without fault

t_ON=t₂without fault

OCHI2

OFF

(rewrite D7=1) and

(t_ON<t₁) without fault and

(NO_OCHI=0)

(NO_OCHI=1) without fault

OCHI1

(NO_OCHI=1) without fault

OCLO

t_ON<t₁and (NO_OCHI=0) without fault

t_ON>t₁without fault and (rewrite D7=1) and (NO_OCHI=0)

(t_ON>t₂) and (rewrite D7=1) without fault

D7=0 then 1 without fault and (NO_OCHI=1)

(OCLO=1) or (OT=1) or (UV=1) or (D7=0)

Figure 13. Faults Management in Normal Mode (for OUT[1:5] only)

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

(OT=1) or

(OCHI1=1)

(external_ON=0)

OFF-latched

State

(OT=1)

(external_ON=0)

(external_ON=1)

(OT=1)

(t>t_OCHI1) and (autorestart=0)

(t>t_OCHI2) and (autorestart=0)

OFF

out: OFF

autorestart=0

OCHI2

out: external

OCHI1

out: external

OCLO

out: external

(t>t_{OCHI1_AUTO}) and (autorestart=1)

(UV=1)

and

(external_on=1)

(t>t_autorestart) and (UV*=0)

(UV=1) or (OCHI2=1)

(UV=1)

(OCLO=1) or

(UV=1)

OFF Autorestart

out: OFF

autorestart=1

(external_ON=0)

1.4 sec min

external

external_ON

external: IGN, Flasher, Stop

external_ON: IGN_ON, Flasher_ON, Stop_ON

Note: * See Autorestart strategy chapter.

Figure 14. Faults Management in Fail Mode (for OUT[1:5] only)

Current Sense

DIAGNOSIS

Open Load

The 35XS3500 diagnosis for load current (OUT1:6) is

done using the current sense (CSNS) pin connected to an

external resistor. The CSNS resistance value is defined in

function to VCC voltage value. It is recommended to use

resistor 500  < R_CSNS< 5.0 k. Typical value is 1.0 k for

The 35XS3500 provides open load detection for each

output (OUT1:OUT5) when the output pin is in the ON state.

Open load detection levels can be chosen by the SPI to

detect a standard bulb or LEDs (OLLED bit). Open load for

LEDs only is detected during each regular switch-off state or

periodically each t_OLLED(fully-on, D[6:0] = 7F). To detect

5.0 V application. The routing of the current sense sources is

SPI programmable (MUX[2,0] bits).

The current recopy feature for OUT1:5 is disabled during

a high over-current shutdown phase (t₂) and is only enabled

OLLED in fully on state, the output must be on at least t_OLLED.

When an open load has been detected, the output stays ON.

during low over-current shutdown thresholds. The current

recopy output delivers current only during ON time of the

output switch without overshoot (aperiodic settling).

To delatch the diagnosis, the condition should be removed

and a SPI read operation is needed (OL bit). In case of a

Power on Reset on VBAT, the fault will be reset.

The current recopy is not active in Fail mode.

35XS3500

Analog Integrated Circuit Device Data

34

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

With a calibration strategy, the output current sensing

precision can be improved significantly. One calibration point

at 25 °C for 50% of FSR allows removing part to part

contribution. So, the calibrated part precision goes down to 

+/-6.0% over [20% - 75%] output current FSR, over voltage

range (10 to 16 V) and temperature range (-40 to 125 °C).

The board temperature feedback is not active in Fail

mode.

With a calibration strategy, the temperature monitoring

precision can be improved. So, one calibration point at 25 °C

allows removing part to part contribution, as presented in

Figure 17.

With dedicated calibration points, the current recopy

allows diagnosing lamp damage in paralleling operations, like

as flasher topology. The Figure 15 summaries test results

covering 99.74% of parts (device ageing not included) for

Standard lamps and LEDs.

typ

2.5

min

max

2

1.5

1

0.5

0

-40

-20

0

20

40

60

80

100

120

140

160

180

Board temperature (°C)

Figure 17. Analog Temperature Precision with

Calibration Strategy

Output Status

The 35XS3500 provides the state of OUT1:OUT5 outputs

in real time through SPI. The OUT bit is set to logic [1] when

the corresponding output voltage is closed to half of battery.

This bit allows synchronizing current sense and diagnosing

short-circuit between OUT and VBAT pins.

Orange = LED mode

Blue = lamp mode (default mode)

Figure 15. Current Sense Precision with Calibration

Strategy

Temperature Prewarning

Board Temperature Feedback

The 35XS3500 provides a temperature prewarning

reported via the SPI (OTW bit) in Normal mode. The

information is latched. To delatch, a read SPI command is

needed. In case of a Power on Reset, the fault will be reset.

The 35XS3500 provides a voltage proportional to the

temperature on the GND flag. This analog feedback is

available in CSNS output pin for MUX[2,0] bits set to “111”,

as described in Figure 16.

External Pin Status

The 35XS3500 provides the status of the FLASHER, IGN,

STOP, and CLOCK pins via the SPI in real time and in

Normal mode.

typ

2.5

min

max

Failure Handling Strategy

2

1.5

1

A highly sophisticated failure handling strategy enables

light functionality even in case of failures inside the

component or the light module. Components are protected

against:

•

Reverse Polarity

Loss of Supply Lines

Fatal Mistreatment of Logic I/O Pins

0.5

0

-40

-20

0

20

40

60

80

100

120

140

160

180

Board temperature (°C)

Figure 16. Analog Temperature Precision

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

provided for RST is set to logic [1]. The SPI pull-up and

pull-down current resistors are available. This fault

condition can be diagnosed with UVF fault in OD13

reporting bit. The previous device configuration is

Reverse Polarity Protection on V

BAT

In case of a permanently reverse polarity operation, the

output transistors are turned ON (R_SD) to prevent thermal

overloads and no protections are available.

maintained. No current is conducted from V_CCto V_BAT

.

An external diode on VCC is necessary in order to not to

destroy the 35XS3500 in cases of reverse polarity.

Loss of V (Digital Logic Supply Line)

CC

During loss a of V_CC(V_CC< V_CCUV) and with wake=1, the

In case of negative transients on the VBAT line (per

ISO 7637), the VCC line is still operating, while the VBAT line

35XS3500 is switched automatically into Fail mode (no

deglich time). The external SMART MOSFET is OFF. All SPI

registers are reset and must be reprogrammed when V_CC

is negative. Without loads on OUT1:5 terminal, an external

clamp between V_BATand GND is mandatory to avoid

goes above V_CCUV. The device will transit in OFF mode if

exceeding maximum rating. The maximum external clamp

voltage shall be between the reverse battery condition and 

-20 V.

VBAT < V_BATPOR2

.

LOSS OF V AND V

Therefore, the device is protected against latch-up with or

without load on OUT outputs.

CC

BAT

If the external V_BATand V_CCsupplies are disconnected (or

not within specification: (V_CCand V_BAT) < V_BATPOR1), all SPI

Loss of Supply Lines

register contents are reset with default values corresponding

to all SPI bits are set to logic [0] and all latched faults are also

reset.

The 35XS3500 is protected against the loss of any supply

line. The detection of the supply line failure is provided inside

the device itself.

Loss of Ground (GND)

Loss of V

BAT

During a loss of ground, the 35XS3500 cannot operate the

loads (the outputs (1:5) are switched OFF), but is not

destroyed by the operating condition. Current limit resistors in

the digital input lines protect the digital supply against

excessive current (1.0 kohm typical). The state of the

external smart power switch controlled by FETOUT is not

guaranteed, and the state of the external smart MOS is

defined with an external termination resistor.

During an under-voltage of V_BAT

(V_BATPOR1<V_BAT<V_BATUV) and with an active device

(wake=1), the outputs [1-5] are switched off immediately. No

current path exists from V_BATto V_CC. The external MOSFET

(OUT6) can be controlled by the SPI if V_CCremains and is

above to V_CCUV. The fault is reported to the UVF bit (OD13).

To delatch the fault, the under-voltage condition should be

removed and:

Fatal Mistreatment of Logic I/O Pins

• the bit D7 must be rewritten to a logic [1] in Normal

mode. Application of the OCHI window depends on

toggling or not toggling the D7 bit. When the fault is

delatched, the 35XS3500 returns to the configuration it

was just before the failure.

The digital I/Os are protected against fatal mistreatment

by a signal plausibility check according to Table 17.

Table 17. Logic I/O Plausibility Check

• if the device was in Fail mode, the fault will be delatched

periodically by the Autorestart feature.

Input/Output

LIMP

Signal Check Strategy

Debounce for 10 ms

In case of V_BAT<V_BATPOR1(Power OFF state), the

(PWM) CLOCK

Frequency range

(bandpass filter)

behavior depends on V_CC

:

• all latched faults are reset if V_CC< V_CCUV

,

SPI (MOSI, SCLK, CS)

WD, D10 bit internal toggle

• all latched faults are maintained under V_CCin nominal

conditions. In case V_BATis disconnected, OUT[1:5]

outputs are OFF. OUT6 output state depends on the

previous SPI configuration. The SPI configuration,

reporting (if V_BATwas previously in the nominal voltage

range for at least 35 sec), and daisy-chain features are

In case the LIMP input is set to a logic [1] for a delay longer

than 10 ms typical, the 35XS3500 is switched into Fail mode.

In case of a (PWM) Clock failure, no PWM feature is

provided, and the bit D7 defines the outputs state. In case of

a SPI failure, the 35XS3500 is switched into Fail mode

(Figure 18)

35XS3500

Analog Integrated Circuit Device Data

36

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

.

1

0

WD Bit D10

timeout

D10 is toggled after

the window watch-

75ms window watchdog

Fail Mode activation

Figure 18. Watchdog Window

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

TYPICAL APPLICATIONS

Figure 19 shows full vehicle light functionality, including fog lights, battery redundancy concept, light substitution mode, and

Limp Home mode.

MOSI, MISO, SCLK

CP

CS

CLOCK

CS

100nF

10XS3535

CLOCK

VBAT

VCC

RST

IGN

RST

VBAT

VCC

Smart Corner

Light Switch

(Front Left)

Smart Corner

Light Switch

(Front Right)

IGN

LIMP

FLASHER

FOG

CSNS

100nF

VBAT

VCC

CP

CS

35XS3500

CLOCK

35XS3500

CLOCK

VBAT

VCC

RST

IGN

RST

IGN

Smart Corner

Light Switch

(Rear Right)

Smart Corner

Light Switch

(Rear Left)

LIMP

FLASHER

STOP

CSNS

STOP

CSNS

Microcontroller

Watchdog

V

WD

CC

(5.0V)

Flasher

V

Ignition

Stop Light

V

BAT

Figure 19. Typical Application

35XS3500

Analog Integrated Circuit Device Data

38

Freescale Semiconductor

TYPICAL APPLICATIONS

EMC & EMI PERFORMANCES

The 35XS3500 will be compliant to CISPR25 Class5 in

Standby mode with 22 nF decoupling capacitor on OUT[1:5].

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

39

PACKAGING

PACKAGING DIMENSIONS

PACKAGING

PACKAGING DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ART10511D

listed below. Dimension shown are provided for reference ONLY.

FK SUFFIX

24-PIN PQFN

98ART10511D

ISSUE 0

35XS3500

Analog Integrated Circuit Device Data

40

Freescale Semiconductor

PACKAGING

PACKAGING DIMENSIONS

FK SUFFIX

24-PIN PQFN

98ART10511D

ISSUE 0

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

41

PACKAGING

PACKAGING DIMENSIONS

FK SUFFIX

24-PIN PQFN

98ART10511D

ISSUE 0

35XS3500

Analog Integrated Circuit Device Data

42

Freescale Semiconductor

PACKAGING

PACKAGING DIMENSIONS

FK SUFFIX

24-PIN PQFN

98ART10511D

ISSUE 0

35XS3500

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

REVISION HISTORY

Revision

1.0

Date

Description of Changes

•

Initial Release

5/2010

•

Changed PN to MC35XS3500PNA

Changed classification to Advance Information

Added Minimum Output Current Reported in CSNS for OUT[1-5]⁽¹³⁾to Table 3.

Added Minimum Output Current Reported in CSNS for OUT[1-5] in LED Mode⁽¹³⁾to Table 3.

Added Note: Output current value computed after leakage current removal (open load condition) to

Table 3.

2.0

7/20101

•

3.0

9/2010

•

Added Under-voltage Deglitch Time parameter.

4.0

5.0

5/2011

4/2012

•

Added Orderable Part Number PC35XS3500HFK

Corrected errors in Table 12 and Table 15

•

Removed MC35XS3500PNA

6.0

6/2012

Updated PC35XS3500HFK to MC35XS3500HFK

Added ⁽⁴⁾

Updated Under-voltage Deglitch Time t_UVparameter in Table 5, Dynamic Electrical Characteristics

on page 15

•

Updated Freescale form and style

Added “if V_BATwas previously in the nominal voltage range for at least 35 sec” to Loss of V_BAT

Section.

Added MC35XS3500DHFK to the ordering information.

7.0

8.0

12/2012

8/2013

•

Changed CSNS condition for CSNS Tri-state Leakage Current

Changed Driver Output Matching Time (t_DLY(ON)- t_DLY(OFF)) at Output = 50% V_BATwith

V_BAT= 14 V, _fPWM= 240 Hz, _PWM= 50%, at 25 °C

•

Corrected conditions for FETIN Leakage Current when external current switch sense is enabled

35XS3500

Analog Integrated Circuit Device Data

44

Freescale Semiconductor

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There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based

on the information in this document.

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and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance

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Document Number: MC35XS3500

Rev. 8.0

8/2013


型号：	MC35XS3500HFKR2
厂家：	NXP
描述：	BUF OR INV BASED PRPHL DRVR 驱动接口集成电路驱动器
文件：	总45页 (文件大小：870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC35XS3500HFKR2 [NXP]

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