MC56F8013MFAE_技术文档

56F8013/56F8011

Data Sheet

Technical Data

56F8000

16-bit Digital Signal Controllers

MC56F8013

Rev. 12

05/2008

freescale.com

Document Revision History

Version History

Rev. 0

Description of Change

Initial release.

Rev. 1

Updates to Part 10, Specifications,

Table 10-1, added maximum clamp current, per pin

Table 10-12, clarified variation over temperature table and graph

Table 10-16, added LIN slave timing

Rev. 2

Rev. 3

Added alternate pins to Figure 11-1 and Table 11-1.

Corrected ADC offering on page 3, clarified Section 1.4.1, corrected bit selects in Timer

Channel 3 Input (TC3_INP) bit 9, Section 6.3.1.7, and simplified notes in Table 10-9.

Rev. 4

Added clarification on sync inputs in Section 1.4.1, added voltage difference specification to

Table 10-1 and Table 10-4, deleted formula for Ambient Operating Temperature in

Table 10-4, also a note for pin group 3 to Table 10-1, corrected Table 8-1, error in Port C

peripheral function configuration, removed text from notes in Table 10-9 that referred to

multiple flash blocks - this family has one flash block. Added RoHs and “pb-free” language to

back cover.

Rev. 5

Updates to Section 10

Table 10-5, corrected max values for ADC Input Current High and Low; corrected typ value

for pull-up disabled Digital Input Current Low (a)

Table 10-6, corrected typ and added max values for Standby > Stop and Powerdown modes

Table 10-7, corrected min value for Low-Voltage Interrupt for 3.3V

Table 10-11, corrected typ and max values and units for PLL lock time

Table 10-12, corrected typ values for Relaxation Oscillator output frequency and variation

over temperature (also increased temp range to 150 degreesC) and added variation over

temperature from 0—105 degreesC

Updated Figure 10-5

Table 10-19, updated max values for Integral Non-Linearity full input signal range, Negative

Differential Non-Linearity, ADC internal clock, Offset Voltage Internal Ref, Gain Error and

Offset Voltage External Ref; updated typ values for Negative Differential Non-Linearity, Offset

Voltage Internal Ref, Gain Error and Offset Voltage External Ref; added new min values and

corrected typ values for Signal-to-noise ratio, Total Harmonic Distortion, Spurious Free

Dynamic Range, Signal-to-noise plus distortion, Effective Number of Bits

Rev. 6

Rev. 7

Added details to Section 1. Clarified language in State During Reset column in Table 2-3;

corrected flash data retention temperature in Table 10-4; moved input current high/low

toTable 10-19 and location of footnotes in Table 10-5; reorganized Table 10-19; clarified title

of Figure 10-1.

Added information on automotive device for 56F8013.

Added information on 56F8011device; edited to indicate differences in 56F8013 and 56F8011

devices.

Updated values for V_EI3.3and V_EI2.5in Table 10-7.

Deleted values for input and output voltage in Table 10-8.

Added row for MC56F8013MFAE in Table 10-12.

56F8013/56F8011 Data Sheet, Rev. 12

2

Freescale Semiconductor

Document Revision History (Continued)

Version History

Rev. 8

Description of Change

• In Table 10-4, added an entry for flash data retention with less than 100 program/erase

cycles (minimum 20 years).

• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.

• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode

from 400kHz to 200kHz.

Rev. 9

In Table 10-19, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.

Rev. 10

Added the following note to the description of the TMS signal in Table 2-3:

Note: Always tie the TMS pin to V_DDthrough a 2.2K resistor.

Rev. 11

Removed “Preliminary” and made changes throughout the book, including changes in the

following sections:

• Feature additions to Section 1.1.4

• Deleted Section 1.4.1

• Table 2-3

• Added diagram in Section 3.5.1

• Added paragraph to Section 5.3

• Deleted Section 5.5, “Operating Modes”

• Added features to Section 6.2

• Section 6.3.8.1 and Section 6.3.8.2

• Deleted note from Section 6.3.8.3

• Clarifications to Section 6.3 register descriptions

• Removed paragraph from Section 6.4

Rev. 12

• Revised Section 7, Security Features.

• Updated temperature information in Table 10-1 and Table 10-4.

• Fixed miscellaneous errors.

Please see http://www.freescale.com for the most current data sheet revision.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

3

56F8013/56F8011 General Description

Note: Features in italics describe the 56F8011 device.

• Up to 32 MIPS at 32MHz core frequency

• One Serial Peripheral Interface (SPI)

• One 16-bit Quad Timer

• DSP and MCU functionality in a unified,

C-efficient architecture

2

• One Inter-Integrated Circuit (I C) Port

• Computer Operating Properly (COP)/Watchdog

• On-Chip Relaxation Oscillator

• 56F8013 device offers 16KB Program Flash

56F8011 device offers 12KB Program Flash

• 56F8013 device offers 4KB Unified Data/Program

• Integrated Power-On Reset and Low-Voltage Interrupt

Module

RAM

56F8011 device offers 2KB Unified Data/Program

RAM

• JTAG/Enhanced On-Chip Emulation (OnCE™) for

unobtrusive, real-time debugging

• One 6-channel PWM module

• Two 3-channel 12-bit ADCs

• Up to 26 GPIO lines

• 32-pin LQFP Package

• One Serial Communication Interface (SCI) with LIN

slave functionality

V

SSA

CAP

DD

SS

DDA

RESET

4

2

JTAG/EOnCE

Port or

GPIOD

Digital Reg

Low-Voltage

Supervisor

Analog Reg

PWM

or Timer Port

or GPIOA

7

PWM Outputs

16-Bit

56800E Core

Data ALU

Program Controller

and Hardware

Looping Unit

Address

Generation Unit

Bit

Manipulation

Unit

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

PAB

PDB

CDBR

CDBW

3

AD0

AD1

ADC

or

GPIOC

Memory

R/W Control

XDB2

XAB1

XAB2

Program Memory

8K x 16 Flash

6K x 16 Flash

System Bus

Control

PAB

Unified Data /

Program RAM

4KB

PDB

CDBR

CDBW

2KB

IPBus Bridge (IPBB)

Timer or

GPIOB

2

SCI

P

O

R

System

Integration

Module

SPI or I C

Interrupt

Controller

COP/

Watchdog

2

O

S

C

Clock

Generator*

or I C

or GPIOB

or Timer

or GPIOB

*Includes On-Chip

Relaxation Oscillator

4

2

56F8013/56F8011 Block Diagram

56F8013/56F8011 Data Sheet, Rev. 12

4

Freescale Semiconductor

56F8013/56F8011 Data Sheet Table of Contents

Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 6

Part 8: General Purpose Input/Output

1.1. 56F8013/56F8011 Features . . . . . . . . . . . . . 6

1.2. 56F8013/56F8011 Description . . . . . . . . . . . 8

1.3. Award-Winning Development Environment . 9

1.4. Architecture Block Diagram . . . . . . . . . . . . . 9

1.5. Synchronize ADC with PWM . . . . . . . . . . . . 9

1.6. Multiple Frequency PWM . . . . . . . . . . . . . . . 9

1.7. Product Documentation . . . . . . . . . . . . . . . 13

1.8. Data Sheet Conventions. . . . . . . . . . . . . . . 13

(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 86

8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . . 88

Part 9: Joint Test Action Group (JTAG). . . 93

9.1. 56F8013/56F8011 Information. . . . . . . . . . . 93

Part 10: Specifications. . . . . . . . . . . . . . . . . 93

10.1. General Characteristics . . . . . . . . . . . . . . . 93

10.2. DC Electrical Characteristics . . . . . . . . . . . 97

10.3. AC Electrical Characteristics . . . . . . . . . . . 99

10.4. Flash Memory Characteristics . . . . . . . . . 100

10.5. External Clock Operation Timing . . . . . . . 101

10.6. Phase Locked Loop Timing . . . . . . . . . . . 101

10.7. Relaxation Oscillator Timing. . . . . . . . . . . 102

10.8. Reset, Stop, Wait, Mode Select, and

Part 2: Signal/Connection Descriptions . . 14

2.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2. 56F8013/56F8011 Signal Pins . . . . . . . . . . 18

Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 26

3.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 28

3.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 29

Interrupt Timing . . . . . . . . . . . . . . . . . . . . 103

10.9. Serial Peripheral Interface (SPI) Timing. . 105

10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 108

10.11. Serial Communication Interface (SCI)

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.12. Inter-Integrated Circuit Interface (I2C)

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.13. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 112

10.14. Analog-to-Digital Converter (ADC)

Parameters . . . . . . . . . . . . . . . . . . . . . . . 114

10.15. Equivalent Circuit for ADC Inputs. . . . . . 115

10.16. Power Consumption . . . . . . . . . . . . . . . . 116

Part 4: Memory Map . . . . . . . . . . . . . . . . . . 29

4.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2. Interrupt Vector Table. . . . . . . . . . . . . . . . . 29

4.3. Program Map . . . . . . . . . . . . . . . . . . . . . . . 31

4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.5. EOnCE Memory Map . . . . . . . . . . . . . . . . . 34

4.6. Peripheral Memory Mapped Registers . . . . 35

Part 5: Interrupt Controller (ITCN) . . . . . . . 44

5.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3. Functional Description . . . . . . . . . . . . . . . . 44

5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 47

5.5. Register Descriptions . . . . . . . . . . . . . . . . . 48

5.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Part 11: Packaging. . . . . . . . . . . . . . . . . . . 118

11.1. 56F8013/56F8011 Package and Pin-Out

Information. . . . . . . . . . . . . . . . . . . . . . . . 118

Part 12: Design Considerations . . . . . . . . 121

12.1. Thermal Design Considerations . . . . . . . . 121

12.2. Electrical Design Considerations . . . . . . . 122

Part 6: System Integration Module (SIM). . 64

6.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 64

6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.3. Register Descriptions . . . . . . . . . . . . . . . . . 66

6.4. Clock Generation Overview . . . . . . . . . . . . 79

6.5. Power-Down Modes . . . . . . . . . . . . . . . . . . 79

6.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.7. Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Part 13: Ordering Information. . . . . . . . . . 124

Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 124

Part 7: Security Features . . . . . . . . . . . . . . 84

7.1. Operation with Security Enabled . . . . . . . . 84

7.2. Flash Access Lock and Unlock Mechanisms 85

7.3. Product Analysis. . . . . . . . . . . . . . . . . . . . . 86

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

5

Part 1 Overview

1.1 56F8013/56F8011 Features

1.1.1

Digital Signal Controller Core

•

Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

Four 36-bit accumulators, including extension bits

32-bit arithmetic and logic multi-bit shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses

Four internal data buses

Instruction set supports both DSP and controller functions

Controller-style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time

debugging

1.1.2

Differences Between Devices

Table 1-1 outlines the key differences between the 56F8013 and 56F8011 devices.

Table 1-1 Device Differences

Feature

56F8013

56F8011

Program Flash

16KB

4KB

12KB

2KB

Unified Data/Program RAM

1.1.3

Memory

•

Dual Harvard architecture permits as many as three simultaneous accesses to program and data

memory

•

Flash security and protection that prevent unauthorized users from gaining access to the internal

Flash

On-chip memory:

— 16KB of Program Flash (56F8013 device)

12KB of Program Flash (56F8011 device)

— 4KB of Unified Data/Program RAM (56F8013 device)

2KB of Unified Data/Program RAM (56F8011 device)

•

EEPROM emulation capability using Flash

56F8013/56F8011 Data Sheet, Rev. 12

6

Freescale Semiconductor

56F8013/56F8011 Features

1.1.4

Peripheral Circuits for 56F8013/56F8011

•

One multi-function six-output Pulse Width Modulator (PWM) module

— Up to 96MHz PWM operating clock

— 15 bits of resolution

— Center-aligned and Edge-aligned PWM signal mode

— Four programmable fault inputs with programmable digital filter

— Double-buffered PWM registers

— Each complementary PWM signal pair can output different switching frequency by selecting

PWM generation sources from:

– PWM generator

– External GPIO

– Internal timers

– ADC conversion result of over/under limits:

– When the conversion result is greater than high limit, deactivate PWM signal

– When the conversion result is less than low limit, activate the PWM signal

Two independent 12-bit Analog-to-Digital Converters (ADCs)

— 2 x 3 channel inputs

•

— Supports both simultaneous and sequential conversions

— ADC conversions can be synchronized by both PWM and timer modules

— Sampling rate up to 2.67MSPS

— 8-word result buffer registers

— ADC Smart Power Management (Auto-standby, auto-powerdown)

One 16-bit multi-purpose Quad Timer module (TMR)

— Up to 96MHz operating clock

— Four independent 16-bit counter/timers with cascading capability

— Each timer has capture and compare capability

— Up to 12 operating modes

One Serial Communication Interface (SCI) with LIN Slave functionality

— Full-duplex or single-wire operation

— Two receiver wake-up methods:

•

– Idle line

– Address mark

One Serial Peripheral Interface (SPI)

— Full-duplex operation

— Master and slave modes

— Programmable Length Transactions (2 to 16 bits)

2

•

One Inter-Integrated Circuit (I C) port

— Operates up to 400kbps

— Supports both master and slave operation

Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

7

•

Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance

Integrated Power-On Reset and Low-Voltage Interrupt Module

Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals

Clock Sources:

— On-chip relaxation oscillator

— External clock source

•

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

JTAG/EOnCE debug programming interface for real-time debugging

1.1.5

Energy Information

•

Fabricated in high-density CMOS with 5V tolerance

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

ADC smart power management

Each peripheral can be individually disabled to save power

1.2 56F8013/56F8011 Description

The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).

It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller

with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8013/56F8011 is well-suited for many

applications. The 56F8013/56F8011 includes many peripherals that are especially useful for industrial

control, motion control, home appliances, general purpose inverters, smart sensors, fire and security

systems, switched mode power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8013/56F8011 supports program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. The 56F8013/56F8011 also offers up to 26

General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8013 Digital Signal Controller includes 16KB of Program Flash and 4KB of Unified

Data/Program RAM. The 56F8011 Digital Signal Controller includes 12KB of Program Flash and 2KB

of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in

pages. Program Flash page erase size is 512 Bytes (256 Words).

2

A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I C, Quad Timer—supports various

applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals

can also be used as General Purpose Input/Outputs (GPIOs).

56F8013/56F8011 Data Sheet, Rev. 12

8

Freescale Semiconductor

Award-Winning Development Environment

1.3 Award-Winning Development Environment

TM

Processor Expert

(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use

component-based software application creation with an expert knowledge system.

The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and

development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs

create a complete, scalable tools solution for easy, fast, and efficient development.

1.4 Architecture Block Diagram

The 56F8013/56F8011’s architecture is shown in Figure 1-1, Figure 1-2, and Figure 1-3. Figure 1-1

illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and

the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and

control blocks connected to the IPBus Bridge. Figure 1-3 details how the device’s I/O pins are muxed.

The figures do not show the on-board regulator and power and ground signals. Please see Part 2,

Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals.

1.5 Synchronize ADC with PWM

ADC conversion can be synchronized with PWM module via Quad Timer channel 2 and 3 if needed.

Internally, the PWM synch signal, which is generated at every PWM reload, can be connected to the timer

channel 3 input and the timer channel 2 and 3 outputs are connected to ADC sync inputs. Timer channel

3 output is connected to SYNC0 and Timer channel 2 is connected to SYNC1. The setting is controlled by

TC3_INP bit in the SIM Control Register; see Section 6.3.1.

SYNC0 is the master ADC sync input is used to trigger both ADCA and ADCB in sequence and parallel

mode. SYNC1 is used to trigger ADCB in parallel independent mode, while SYNC0 is used to trigger

ADCA. See 56F801X Peripheral Reference Manual for additional information.

1.6 Multiple Frequency PWM

When both PWM channels of a complementary pair in software control mode and software control bits

are set to 1, each complementary PWM signal pair—PWM 0 and 1; PWM 2 and 3; PWM 4 and 5—can

select a PWM source of one of following sources that enables each PWM pair to output different frequency

PWM signal.

•

External GPIO input:

— GPIOB2 input can be used to drive PWM 0 and 1

— GPIOB3 input can be used to drive PWM 2 and 3

— GPIOB4 input can be used to drive PWM 4 and 5

•

Quad Timer output:

— Timer0 output can be used to drive PWM 0 and 1

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

9

— Timer2 output can be used to drive PWM 2 and 3

— Timer3 output can be used to drive PWM 4 and 5

•

ADC conversion result:

— Signal of Over/Under limit of ADC sample 0 can be used to drive PWM 0 and 1

— Signal of Over/Under limit of ADC sample 1 can be used to drive PWM 2 and 3

— Signal of Over/Under limit of ADC sample 2 can be used to drive PWM 4 and 5

DSP56800E Core

Program Control Unit

ALU1

ALU2

Address

Generation

Unit

PC

LA

LA2

Instruction

Decoder

R0

R1

(AGU)

HWS0

HWS1

FIRA

R2

R3

Interrupt

Unit

Program

Memory

M01

N3

OMR

R4

R5

N

SR

LC

LC2

Looping

Unit

SP

FISR

XAB1

XAB2

PAB

Data /

Program

RAM

PDB

CDBW

CDBR

XDB2

A2

B2

C2

D2

A1

B1

C1

D1

Y1

Y0

X0

A0

B0

C0

D0

Bit-

Manipulation

Unit

IPBUS

Interface

Y

Data

Enhanced

OnCE™

Arithmetic

Logic Unit

(ALU)

JTAG TAP

MAC and ALU

Multi-Bit Shifter

Figure 1-1 56800E Core Block Diagram

56F8013/56F8011 Data Sheet, Rev. 12

10

Freescale Semiconductor

Multiple Frequency PWM

To/From IPBus Bridge

CLKGEN

(ROSC / PLL /

CLKIN)

Interrupt

Controller

Low-Voltage Interrupt

POR & LVI

System POR

RESET / GPIOA7

8

GPIO A

GPIO B

GPIO C

GPIO D

GPIOAn

GPIOBn

GPIOCn

6

4

SIM

GPIODn

COP Reset

COP

IPBus

(Continues on Figure 1-3)

Figure 1-2 Peripheral Subsystem

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

11

(Continued from Figure 1-2)

To/From IPBus Bridge

PWM0 - 3

4

PWM0 - 3

2

PWM4, 5

Fault1, 2

Fault0

GPIOA0 - 3

PWM

2

PWM4, 5

Fault1, 2

T2, 3

Output Controls

Fault3

GPIOA4 - 5

GPIOA6

Reload

Pulse

2

3

2

Fault0

Fault3

from ADC

2

T3i

T2/3

T1

GPIOB5

GPIOB4

Timer

T0

T2o, T3o

T0

I²C is muxed with both SPI and SCI.

T2 and T3 are muxed with SPI and PWM.

CLKO

2

TXD, RXD

SDA, SCL

2

SCI

I²C

GPIOB6 - 7

GPIOB0 - 1

GPIOB2 - 3

SCLK, SS

2

SPI

MISO, MOSI

T2, 3

3

to PWM

3

ANA0, 1, 3

ANA2

Sync0, Over/Under

Sync1 Limits

ANA0, 1, 3

ANA2

ANB2

GPIOC0, 1, 3

V_REFH, V_REFL

ADC

ANB2

V

_REFH, V_REFL

2

3

ANB0, 1, 3

GPIOC2, 6

ANB0, 1, 3

GPIOC4, 5, 7

IPBus

Figure 1-3 56F8013/56F8011 Peripheral I/O Pin-Out

56F8013/56F8011 Data Sheet, Rev. 12

12

Freescale Semiconductor

Product Documentation

1.7 Product Documentation

The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8013

or 56F8011. Documentation is available from local Freescale distributors, Freescale Semiconductor sales

offices, Freescale Literature Distribution Centers, or online at:

http://www.freescale.com

Table 1-2 56F8013/56F8011 Chip Documentation

Topic

DSP56800E

Description

Order Number

DSP56800ERM

Detailed description of the 56800E family architecture,

16-bit Digital Signal Controller core processor, and the

instruction set

Reference Manual

56F801X Peripheral

Reference Manual

Detailed description of peripherals of the 56F801X

family of devices

MC56F8000RM

56F801XBLUG

MC56F8013

56F801X Serial

Bootloader User Guide

Detailed description of the Serial Bootloader in the

56F801x family of devices

56F8013/56F8011

Technical Data Sheet

Electrical and timing specifications, pin descriptions,

and package descriptions (this document)

Errata

Details any chip issues that might be present

MC56F8013E

MC56F8011E

1.8 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted”

“deasserted”

Examples:

A high true (active high) signal is high or a low true (active low) signal is low.

A high true (active high) signal is low or a low true (active low) signal is high.

Voltage¹

Signal/Symbol

Logic State

True

Signal State

Asserted

V_IL/V_OL

False

Deasserted

Asserted

V_IH/V_OH

V_IL/V_OL

True

False

Deasserted

1. Values for V , V , V , and V are defined by individual product specifications.

IL

OL

IH

OH

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

13

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8013/56F8011 are organized into functional groups, as detailed in

Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or

signals present on a pin, sorted by pin number.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins

Power (V_DDor V_DDA

)

2

3

Ground (V_SSor V_SSA

)

Supply Capacitors

Reset

1

7

Pulse Width Modulator (PWM) Ports¹

Serial Peripheral Interface (SPI) Ports²

Analog-to-Digital Converter (ADC) Ports

4

6

2

Timer Module Ports³

Serial Communications Interface (SCI) Ports⁴

2

4

JTAG/Enhanced On-Chip Emulation (EOnCE)

1. Pins in this section can function as Timer and GPIO.

2

2. Pins in this section can function as Timer, I C, and GPIO.

3. Pins can function as PWM and GPIO.

2

4. Pins in this section can function as I C and GPIO.

56F8013/56F8011 Data Sheet, Rev. 12

14

Freescale Semiconductor

Introduction

Table 2-2 56F8013/56F8011 Pins

Peripherals:

LQFP

Pin #

Name

Quad Power &

Timer Ground

Signal Name

GPIO I2C SCI

SPI

ADC

PWM

JTAG

Misc.

1

2

3

4

GPIOB6 GPIOB6, RXD,

B6 SDA RXD

CLKIN

SDA, CLKIN

GPIOB1 GPIOB1, SS,

B1 SDA

B7 SCL TXD

B5

SS

SDA

GPIOB7 GPIOB7, TXD,

SCL

GPIOB5 GPIOB5, T1,

FAULT3

T1

FAULT3

5

6

7

ANB0

ANB1

ANB2

ANB0, GPIOC4

ANB1, GPIOC5

C4

C5

C6

ANB0

ANB1

ANB2, V_REFL

GPIOC6

,

ANB2,

V_REFL

8

9

VDDA

VSSA

ANA2

V_DDA

V_SSA

V_DDA

V_SSA

10

ANA2, V_REFH

GPIOC2

,

C2

ANA2,

V_REFH

11

12

13

ANA1

ANA0

ANA1, GPIOC1

ANA0, GPIOC0

C1

C0

ANA1

ANA0

VSS_IO V_SS

V_SS

14

15

16

TCK

TCK, GPIOD2

D2

A7

B3

TCK

RESET RESET, GPIOA7

RESET

GPIOB3 GPIOB3, MOSI,

MOSI

MISO

T3

T2

T3

17

GPIOB2 GPIOB2, MISO,

B2

T2

18

19

GPIOA6 GPIOA6, FAULT0 A6

FAULT0

GPIOB4 GPIOB4, T0,

B4

T0

T3

CLKO

20

21

22

GPIOA5 GPIOA5, PWM5,

A5

PWM5,

FAULT2

FAULT2, T3

GPIOB0 GPIOB0, SCLK,

B0 SCL

SCLK

SCL

GPIOA4 GPIOA4, PWM4,

A4

PWM4,

T2

FAULT1, T2

FAULT1

23

24

GPIOA2 GPIOA2, PWM2

GPIOA3 GPIOA3, PWM3

A2

A3

PWM2

PWM3

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

15

Table 2-2 56F8013/56F8011 Pins (Continued)

Peripherals:

LQFP

Pin #

Name

Quad Power &

Timer Ground

Signal Name

GPIO I2C SCI

SPI

ADC

PWM

JTAG

Misc.

25

26

27

VCAP

VDD

V_CAP

V_DD

V_CAP

V_DD

V_SS

VSS_IO V_SS

28

29

30

31

32

GPIOA1 GPIOA1, PWM1

GPIOA0 GPIOA0, PWM0

A1

A0

D0

D3

D1

PWM1

PWM0

TDI

TDI, GPIOD0

TMS, GPIOD3

TDO, GPIOD1

TDI

TMS

TDO

TMS

TDO

56F8013/56F8011 Data Sheet, Rev. 12

16

Freescale Semiconductor

Introduction

V_DD

V_SS

Power

Ground

Power

1

2

V_DDA

1

V_SSA

Ground

56F8013 /

56F8011

GPIOB0 (SCLK, SCL)

GPIOB1 (SS, SDA)

Other

Supply

Ports

1

SPI Port or

V_CAP

I²C Port or

Timer Port

or GPIO

1

GPIOB2 (MISO, T2)

GPIOB3 (MOSI, T3)

1

GPIOB6 (RXD, SDA, CLKIN)

GPIOB7 (TXD, SCL)

SCI Port or

I²C Port or

GPIO

GPIOA0 - 2 (PWM0 - 2)

GPIOA3 (PWM3)

1

3

1

PWM Port or

Timer Port or

GPIO

GPIOA4 (PWM4, FAULT1, T2)

GPIOA5 (PWM5, FAULT2, T3)

GPIOA6 (FAULT0)

1

RESET

RESET (GPIOA7)

1

ANA0 - 1 (GPIOC0 - 1)

ANA2 (V_REFH, GPIOC2)

2

1

GPIOB4 (T0, CLKO)

GPIOB5 (T1, FAULT3)

Timer Port

or GPIO

ADC Port or

GPIO

1

ANB0 - 1 (GPIOC4 - 5)

ANB2 (V_REFL, GPIOC6)

2

1

TCK (GPIOD2)

1

TMS (GPIOD3)

TDI (GPIOD0)

TDO (GPIOD1)

JTAG/

EOnCE Port

or GPIO

1

Figure 2-1 56F8013/56F8011 Signals Identified by Functional Group

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

17

2.2 56F8013/56F8011 Signal Pins

After reset, each pin is configured for its primary function (listed first). Any alternate functionality must

be programmed.

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

V_DD

V_SS

26

13

27

8

Supply

I/O Power — This pin supplies 3.3V power to the chip I/O interface.

V_SS— These pins provide ground for chip logic and I/O drivers.

V_SS

V_DDA

Supply

ADC Power — This pin supplies 3.3V power to the ADC modules. It

must be connected to a clean analog power supply.

V_SSA

9

ADC Analog Ground — This pin supplies an analog ground to the

ADC modules.

V_CAP

25

V_CAP— Connect a 2.2 μF or greater bypass capacitor between this

pin and VSS_IO, which is required by the internal voltage regulator

for proper chip operation. See Section 10.2.1.

GPIOB6

1

Input/

Input with Port B GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(RXD)

Input

Receive Data — SCI receive data input.

(SDA¹)

Serial Data — This pin serves as the I²C serial data line.

Input/

Output

Input

(CLKIN)

Clock Input — This pin serves as an optional external clock input.

After reset, the default state is GPIOB6. The alternative peripheral

functionality is controlled via the SIM (See Section 6.3.8) and the

CLKMODE bit of the OCCS Oscillator Control Register.

1. This signal is also brought out on the GPIOB1 pin.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

18

Freescale Semiconductor

56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB7

3

Input/

Input with Port B GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(TXD)

Output

Transmit Data — SCI transmit data output or transmit / receive in

single wire operation.

(SCL²)

Serial Clock — This pin serves as the I²C serial clock.

Input/

Output

After reset, the default state is GPIOB7. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

2. This signal is also brought out on the GPIOB0 pin.

RESET

15

Input

Input with Reset — This input is a direct hardware reset on the processor.

internal

pull-up

enabled

When RESET is asserted low, the chip is initialized and placed in the

reset state. A Schmitt trigger input is used for noise immunity. The

internal reset signal will be deasserted synchronous with the internal

clocks after a fixed number of internal clocks.

(GPIOA7)

Input/Open

Drain

Output

Port A GPIO — This GPIO pin can be individually programmed as

an input or open drain output pin. Note that RESET functionality is

disabled in this mode and the chip can only be reset via POR, COP

reset, or software reset.

After reset, the default state is RESET.

GPIOB4

19

Input/

Input with Port B GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(T0)

Input/

T0 — Timer, Channel 0

Output

(CLKO)

Output

Clock Output — This is a buffered clock signal. Using the

SIM_CLKO Select Register (SIM_CLKOSR), this pin can be

programmed as any of the following: disabled (logic 0), CLK_MSTR

(system clock), IPBus clock, or oscillator output. See Section 6.3.7.

After reset, the default state is GPIOB4. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

19

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB5

4

Input/

Input with Port B GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(T1)

Input/

T1 — Timer, Channel 1

Output

(FAULT3)

Input

FAULT3 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

After reset, the default state is GPIOB5. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

TCK

14

Input with Test Clock Input — This input pin provides a gated clock to

internal

pull-up

enabled

synchronize the test logic and shift serial data to the JTAG/EOnCE

port. The pin is connected internally to a pull-up resistor. A Schmitt

trigger input is used for noise immunity.

(GPIOD2)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TCK.

TMS

31

Input

Input with Test Mode Select Input — This input pin is used to sequence the

internal

pull-up

JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

enabled

(GPIOD3)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TMS.

Note: Always tie the TMS pin to V_DDthrough a 2.2K resistor if this pin

is configured as TMS.

TDI

30

Input

Input with Test Data Input — This input pin provides a serial input data stream

internal

pull-up

to the JTAG/EOnCE port. It is sampled on the rising edge of TCK

and has an on-chip pull-up resistor.

enabled

(GPIOD0)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TDI.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

20

Freescale Semiconductor

56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

TDO

32

Output

Test Data Output — This tri-stateable output pin provides a serial

output data stream from the JTAG/EOnCE port. It is driven in the

shift-IR and shift-DR controller states, and changes on the falling

edge of TCK.

(GPIOD1)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TDO.

GPIOB0

(SCLK)

21

Input/

Output

Input with Port B GPIO — This GPIO pin can be individually programmed as

internal

pull-up

an input or output pin.

enabled

Input/

Output

SPI Serial Clock — In the master mode, this pin serves as an

output, clocking slaved listeners. In slave mode, this pin serves as

the data clock input. A Schmitt trigger input is used for noise

immunity.

(SCL³)

Serial Data — This pin serves as the I²C serial clock.

Input/

Output

After reset, the default state is GPIOB0. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

3. This signal is also brought out on the GPIOB7 pin.

GPIOB1

2

Input/

Input with Port B GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(SS)

Input

SPI Slave Select — SS is used in slave mode to indicate to the SPI

module that the current transfer is to be received.

(SDA⁴)

Serial Clock — This pin serves as the I²C serial data line.

Input/

Output

After reset, the default state is GPIOB1. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

4. This signal is also brought out on the GPIOB6 pin.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

21

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB2

17

Input/

Input with Port B GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(MISO)

Input/

Output

SPI Master In/Slave Out — This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a

slave device is placed in the high-impedance state if the slave device

is not selected. The slave device places data on the MISO line a

half-cycle before the clock edge the master device uses to latch the

data.

(T2⁵)

Input/

Output

T2 — Timer, Channel 2

After reset, the default state is GPIOB2. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

5. This signal is also brought out on the GPIOA4 pin.

GPIOB3

16

Input/

Input with Port B GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(MOSI)

Input/

Output

SPI Master Out/Slave In— This serial data pin is an output from a

master device and an input to a slave device. The master device

places data on the MOSI line a half-cycle before the clock edge the

slave device uses to latch the data.

(T3⁶)

Input/

Output

T3 — Timer, Channel 3

After reset, the default state is GPIOB3. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

6. This signal is also brought out on the GPIOA5 pin.

GPIOA0

29

Input/

Input with Port A GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(PWM0)

Output

PWM0 — This is one of the six PWM output pins.

After reset, the default state is GPIOA0.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

22

Freescale Semiconductor

56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOA1

(PWM1)

GPIOA2

(PWM2)

GPIOA3

(PWM3)

GPIOA4

28

23

24

22

Input/

Output

Input with Port A GPIO — This GPIO pin can be individually programmed as

internal

pull-up

an input or output pin.

enabled

Output

PWM1 — This is one of the six PWM output pins.

After reset, the default state is GPIOA1.

Input/

Output

Input with Port A GPIO — This GPIO pin can be individually programmed as

internal

pull-up

an input or output pin.

enabled

Output

PWM2 — This is one of the six PWM output pins.

After reset, the default state is GPIOA2.

Input/

Output

Input with Port A GPIO — This GPIO pin can be individually programmed as

internal

pull-up

an input or output pin.

enabled

Output

PWM3 — This is one of the six PWM output pins.

After reset, the default state is GPIOA3.

Input/

Input with Port A GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(PWM4)

Output

Input

PWM4 — This is one of the six PWM output pins.

(FAULT1)

Fault1 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

(T2⁷)

Input/

Output

T2 — Timer, Channel 2

After reset, the default state is GPIOA4. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

7. This signal is also brought out on the GPIOB2 pin.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

23

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOA5

20

Input/

Input with Port A GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(PWM5)

Output

Input

PWM5 — This is one of the six PWM output pins.

(FAULT2)

Fault2 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

(T3⁸)

Input/

Output

T3 — Timer, Channel 3

After reset, the default state is GPIOA5. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

8. This signal is also brought out on the GPIOB3 pin.

GPIOA6

18

Input/

Input with Port A GPIO — This GPIO pin can be individually programmed as

Output

internal

pull-up

an input or output pin.

enabled

(FAULT0)

Input

Fault0 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

After reset, the default state is GPIOA6.

ANA0

12

11

Analog

Input

ANA0 — Analog input to ADC A, channel 0

(GPIOC0)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is ANA0.

ANA1

Input

Analog

Input

ANA1 — Analog input to ADC A, channel 1

(GPIOC1)

Input/

Port C GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is ANA1.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

24

Freescale Semiconductor

56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

ANA2

10

Input

Analog

Input

ANA2 — Analog input to ADC A, channel 2

(V_REFH

)

Input

V_REFH— Analog reference voltage high

Input/

Output

(GPIOC2)

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is ANA2.

ANB0

5

6

7

Input

Analog

Input

ANB0 — Analog input to ADC B, channel 0

(GPIOC4)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is ANB0.

ANB1

Input

Analog

Input

ANB1 — Analog input to ADC B, channel 1

(GPIOC5)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is ANB1.

ANB2

Input

Analog

Input

ANB2 — Analog input to ADC B, channel 2

(V_REFL

)

V_REFL— Analog reference voltage low. This should normally be

connected to a low-noise V_SS

.

Input/

Output

(GPIOC6)

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is ANB2.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

25

Part 3 OCCS

3.1 Overview

This module provides the system clock, which is used to generate the various chip clocks. This module

also produces the oscillator clock plus the ADC clock and high-speed peripheral clock.

The on-chip clock synthesis module allows product design using an internal relaxation oscillator to run

56F801X family parts at user-selectable frequencies up to 32MHz.

3.2 Features

The On-Chip Clock Synthesis (OCCS) module interfaces to the oscillator and PLL. The OCCS module

features:

•

Internal relaxation oscillator

Ability to power down the internal relaxation oscillator

Ability to put the internal relaxation oscillator into a standby mode

3-bit postscaler provides control for the PLL output

Ability to power down the internal PLL

Provides 2X system clock, which operates at twice the system clock, to the System Integration Model (SIM)

that is used to generate the various device clocks

•

Provides 3X system clock, which operates at three times the system clock, to PWM and Timer

Safety shutdown feature is available in the event that the PLL reference clock is lost

Can be driven from an external clock source

The clock generation module provides the programming interface for both the PLL and internal relaxation

oscillator.

3.3 Operating Modes

In 56F801X family parts, either an internal oscillator or an external frequency source can be used to

provide a reference clock to the SIM.

The 2X system clock source output from the OCCS can be described by one of the following equations:

2X system frequency = oscillator frequency

2X system frequency = (oscillator frequency X 8) / (postscaler)

where:

postscaler = 1, 2, 4, 8, 16, or 32 PLL output divider

The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle

in the system clock output.

56F8013/56F8011 Data Sheet, Rev. 12

26

Freescale Semiconductor

Operating Modes

The 56F801X family parts’ on-chip clock synthesis module has the following registers:

•

Control Register (OCCS_CR)

Divide-by Register (OCCS_DB)

Status Register (OCCS_SR)

Shutdown Register (OCCS_SHUTDN)

Oscillator Control Register (OCCS_OCTRL)

For more information on these registers, please refer to the 56F801X Peripheral Reference Manual.

3.3.1

External Clock Source

The recommended method of connecting an external clock is illustrated in Figure 3-1. The external clock

source is connected to GPIOB6 / RXD / SDA / CLKIN.

56F8013/56F8011

GPIOB6 / RXD / SDA / CLKIN

External Clock

Figure 3-1 Connecting an External Clock Signal using GPIOB6 / RXD / SDA / CLKIN

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

27

3.4 Block Diagram

Figure 3-2 provides a block diagram which shows how the 56F8013/56F8011 creates its internal clock,

using the relaxation oscillator as an 8MHz clock reference for the PLL.

TRIM[9:0]

Relaxation

OSC

ROSB

ROPD

Bus Interface and

Control

Bus

Interface

GPIOB6 / RXD

MUX

PRECS

MSTR_OSC

SYS_CLK_x2

source to the SIM

(64MHz max)

FOUT

Postscaler

÷ 3

÷ 2

PLL

X 24

(÷ 1, 2, 4, 8, 16, 32)

ZSRC

PLLCOD

HS PERF CLK

(96MHz max)

Postscaler

(÷ 1, 2, 4, 8, 16, 32)

LCK

Lock

Detector

Loss of

Reference

Clock

Loss of Reference Clock Interrupt

Detector

Figure 3-2 OCCS Block Diagram with Relaxation Oscillator

56F8013/56F8011 Data Sheet, Rev. 12

28

Freescale Semiconductor

Pin Descriptions

3.5 Pin Descriptions

3.5.1

External Reference (GPIOB6 / RXD / SDA / CLKIN)

After reset, the internal relaxation oscillator is selected as the clock source for the chip. The user then has

the option of switching to an external clock reference if desired by enabling the PRECS bit in the OCCS

Oscillator Control register.

Part 4 Memory Map

4.1 Introduction

The 56F8013/56F8011 device is a 16-bit motor-control chip based on the 56800E core. It uses a

Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is

used in both spaces and Flash memory is used only in Program space.

This section provides memory maps for:

•

Program Address Space, including the Interrupt Vector Table

Data Address Space, including the EOnCE Memory and Peripheral Memory Maps

On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are

identified in the “Use Restrictions” column of Table 4-1.

Table 4-1 Chip Memory Configurations

On-Chip Memory

56F8013

56F8011

Use Restrictions

Program Flash

(PFLASH)

8k x 16

6k x 16

Erase / Program via Flash interface unit and word writes to CDBW

Unified RAM (ram)

2k x 16

1k x 16

Usable by both the Program and Data memory spaces

4.2 Interrupt Vector Table

Table 4-2 provides the 56F8013/56F8011’s reset and interrupt priority structure, including on-chip

peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts

lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing

some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For

a selected priority level, the lowest vector number has the highest priority.

The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.5.6

for the reset value of the VBA.

By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the

interrupt vector table. In these instances, the first two locations in the vector table must contain branch or

JMP instructions. All other entries must contain JSR instructions.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

29

1

Table 4-2 Interrupt Vector Table Contents

Vector

Number

Priority

Level

Vector Base

Address +

Peripheral

Interrupt Function

Reserved for Reset Overlay²

core

P:$00

core

P:$02

P:$04

P:$06

P:$08

P:$0A

P:$0C

P:$0E

P:$10

P:$12

P:$14

P:$16

P:$18

P:$1A

Reserved for COP Reset Overlay

Illegal Instruction

2

3

4

5

6

7

8

9

3

SW Interrupt 3

HW Stack Overflow

Misaligned Long Word Access

EOnCE Step Counter

EOnCE Breakpoint Unit 0

EOnCE Trace Buffer

EOnCE Transmit Register Empty

EOnCE Receive Register Full

SW Interrupt 2

1-3

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33, 34

35

1

SW Interrupt 1

0

SW Interrupt 0

Reserved

PS

0-2

P:$20

P:$22

P:$24

P:$26

P:$28

Power Sense

OCCS

FM

PLL Lock, Loss of Clock Reference Interrupt

FM Access Error Interrupt

FM Command Complete

FM Command, data and address Buffers Empty

Reserved

FM

GPIOD

GPIOC

GPIOB

GPIOA

SPI

0-2

P:$2C

P:$2E

P:$30

P:$32

P:$34

P:$36

P:$38

P:$3A

P:$3C

P:$3E

P:$40

GPIOD

GPIOC

GPIOB

GPIOA

SPI Receiver Full / Error

SPI Transmitter Empty

SCI Transmitter Empty

SCI Transmitter Idle

SCI Reserved

SPI

SCI

SCI Receiver Error

SCI Receiver Full

SCI

Reserved

I²C

0-2

P:$46

Timer

36

37

0-2

P:$48

P:$4A

Timer Channel 0

Timer Channel 1

(Continues next page)

56F8013/56F8011 Data Sheet, Rev. 12

30

Freescale Semiconductor

Program Map

1

Table 4-2 Interrupt Vector Table Contents (Continued)

Vector

Number

Priority

Level

Vector Base

Address +

Peripheral

Interrupt Function

Timer

ADC

38

0-2

P:$4C

P:$4E

P:$50

P:$52

P:$54

P:$56

P:$58

P:$5A

Timer Channel 2

Timer Channel 3

39

40

41

42

43

44

45

0-2

-1

ADCA Conversion Complete

ADCB Conversion Complete

ADC Zero Crossing or Limit Error

Reload PWM

ADC

PWM

SWILP

PWM Fault

SW Interrupt Low Priority

1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced

from the vector table, providing only 19 bits of address.

2. If the VBA is set to the reset value, the first two locations of the vector table will overlay the chip reset addresses.

4.3 Program Map

The Program Memory map is shown in Table 4-3.

1

Table 4-3 Program Memory Map for 56F8013

Begin/End Address

Memory Allocation

P: $FF FFFF

P: $00 8800

RESERVED

On-Chip RAM²

4KB

P: $00 87FF

P: $00 8000

P: $00 7FFF

P: $00 2000

RESERVED

P: $00 1FFF

P: $00 0000

Internal Program Flash

16KB

Cop Reset Address = $00 0002

Boot Location = $00 0000

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Data space starting at address X: $00 0000;

see Figure 4-1.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

31

1

Table 4-4 Program Memory Map for 56F8011

Begin/End Address

Memory Allocation

P: $1F FFFF

P: $00 8400

RESERVED

On-Chip RAM²

2KB

P: $00 83FF

P: $00 8000

P: $00 7FFF

P: $00 2000

RESERVED

P: $00 1FFF

P: $00 0800

Internal Program Flash

12KB

Cop Reset Address = $00 0802

Boot Location = $00 0800

P: $00 07FF

P: $00 0000

RESERVED

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Data space starting at address X: $00 0000;

see Figure 4-1.

4.4 Data Map

1

Table 4-5 Data Memory Map for 56F8013

Begin/End Address

Memory Allocation

X:$FF FFFF

X:$FF FF00

EOnCE

256 locations allocated

X:$FF FEFF

X:$01 0000

RESERVED

X:$00 FFFF

X:$00 F000

On-Chip Peripherals

4096 locations allocated

X:$00 EFFF

X:$00 8800

RESERVED

X:$00 EFFF

X:$00 0800

X:$00 7FFF

X:$00 0040

On-Chip Data RAM²

4KB

X:$00 07FF

X:$00 0000

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Program space starting at P: $00 8000; see

Figure 4-1.

56F8013/56F8011 Data Sheet, Rev. 12

32

Freescale Semiconductor

Data Map

1

Table 4-6 Data Memory Map for 56F8011

Begin/End Address

Memory Allocation

X:$FF FFFF

X:$FF FF00

EOnCE

256 locations allocated

X:$FF FEFF

X:$01 0000

RESERVED

X:$00 FFFF

X:$00 F000

On-Chip Peripherals

4096 locations allocated

X:$00 EFFF

X:$00 0400

RESERVED

On-Chip Data RAM²

2KB

X:$00 03FF

X:$00 0000

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Program space starting at P: $00 8000; see

Figure 4-1.

Program

Data

EOnCE

Reserved

RAM

Peripherals

Reserved

RAM

Reserved

Dual Port RAM

Flash

Figure 4-1 Dual Port RAM

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

33

4.5 EOnCE Memory Map

Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.

Table 4-7 EOnCE Memory Map

Address

X:$FF FFFF

Register Acronym

Register Name

OTX1 / ORX1

Transmit Register Upper Word

Receive Register Upper Word

X:$FF FFFE

OTX / ORX (32 bits)

Transmit Register

Receive Register

X:$FF FFFD

X:$FF FFFC

X:$FF FFFB - X:$FF FFA1

X:$FF FFA0

X:$FF FF9F

X:$FF FF9E

X:$FF FF9D

X:$FF FF9C

X:$FF FF9B

X:$FF FF9A

X:$FF FF99

OTXRXSR

OCLSR

Transmit and Receive Status and Control Register

Core Lock / Unlock Status Register

Reserved

OCR

Control Register

Instruction Step Counter

OSCNTR (24 bits)

OSR

Instruction Step Counter

Status Register

OBASE

Peripheral Base Address Register

Trace Buffer Control Register

Trace Buffer Pointer Register

Trace Buffer Register Stages

OTBCR

OTBPR

X:$FF FF98

OTB (21 - 24 bits/stage) Trace Buffer Register Stages

Breakpoint Unit Control Register

X:$FF FF97

X:$FF FF96

OBCR (24 bits)

OBAR1 (24 bits)

OBAR2 (32 bits)

OBMSK (32 bits)

OBCNTR

Breakpoint Unit Control Register

Breakpoint Unit Address Register 1

Breakpoint Unit Address Register 2

Breakpoint Unit Mask Register 2

Reserved

X:$FF FF95

X:$FF FF94

X:$FF FF93

X:$FF FF92

X:$FF FF91

X:$FF FF90

X:$FF FF8F

X:$FF FF8E

X:$FF FF8D

X:$FF FF8C

X:$FF FF8B

X:$FF FF8A

X:$FF FF89 - X:$FF FF00

EOnCE Breakpoint Unit Counter

Reserved

OESCR

External Signal Control Register

Reserved

56F8013/56F8011 Data Sheet, Rev. 12

34

Freescale Semiconductor

Peripheral Memory Mapped Registers

4.6 Peripheral Memory Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may

be accessed with the same addressing modes used for ordinary Data memory, except all peripheral

registers should be read/written using word accesses only.

Table 4-8 summarizes base addresses for the set of peripherals on the 56F8013/56F8011 device.

Peripherals are listed in order of the base address.

The following tables list all of the peripheral registers required to control or access the peripherals.

Table 4-8 Data Memory Peripheral Base Address Map Summary

Peripheral

Prefix

Base Address

Table Number

Timer

PWM

ITCN

ADC

SCI

TMRn

PWM

ITCN

ADC

SCI

X:$00 F000

X:$00 F040

X:$00 F060

X:$00 F080

X:$00 F0B0

X:$00 F0C0

X:$00 F0D0

4-9

4-10

4-11

4-12

4-13

4-14

4-15

SPI

I²C

I2C

COP

X:$00 F0E0

X:$00 F0F0

X:$00 F100

X:$00 F110

X:$00 F120

X:$00 F130

X:$00 F140

X:$00 F160

X:$00 F400

4-16

4-17

4-18

4-19

4-20

4-21

4-22

4-23

4-24

CLK, PLL, OSC, TEST

GPIO Port A

GPIO Port B

GPIO Port C

GPIO Port D

SIM

OCCS

GPIOA

GPIOB

GPIOC

GPIOD

SIM

Power Supervisor

FM

PS

FM

Table 4-9 Quad Timer Registers Address Map

(TMR_BASE = $00 F000)

Register Acronym

Address Offset

Register Description

Compare Register 1

TMR0_COMP1

TMR0_COMP2

TMR0_CAPT

TMR0_LOAD

TMR0_HOLD

TMR0_CNTR

TMR0_CTRL

TMR0_SCTRL

TMR0_CMPLD1

$0

$1

$2

$3

$4

$5

$6

$7

$8

Compare Register 2

Capture Register

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

35

Table 4-9 Quad Timer Registers Address Map (Continued)

(TMR_BASE = $00 F000)

Register Acronym

Address Offset

Register Description

Comparator Load Register 2

TMR0_CMPLD2

TMR0_CSCTRL

$9

$A

Comparator Status and Control Register

Reserved

TMR1_COMP1

TMR1_COMP2

TMR1_CAPT

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

Compare Register 1

Compare Register 2

Capture Register

TMR1_LOAD

TMR1_HOLD

TMR1_CNTR

TMR1_CTRL

Load Register

Hold Register

Counter Register

Control Register

TMR1_SCTRL

TMR1_CMPLD1

TMR1_CMPLD2

TMR1_CSCTRL

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Reserved

TMR2_COMP1

TMR2_COMP2

TMR2_CAPT

$20

$21

$22

$23

$24

$25

$26

$27

$28

$29

$2A

Compare Register 1

Compare Register 2

Capture Register

TMR2_LOAD

TMR2_HOLD

TMR2_CNTR

TMR2_CTRL

Load Register

Hold Register

Counter Register

Control Register

TMR2_SCTRL

TMR2_CMPLD1

TMR2_CMPLD2

TMR2_CSCTRL

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Reserved

TMR3_COMP1

TMR3_COMP2

TMR3_CAPT

$30

$31

$32

$33

$34

$35

$36

$37

$38

$39

$3A

Compare Register 1

Compare Register 2

Capture Register

TMR3_LOAD

TMR3_HOLD

TMR3_CNTR

TMR3_CTRL

Load Register

Hold Register

Counter Register

Control Register

TMR3_SCTRL

TMR3_CMPLD1

TMR3_CMPLD2

TMR3_CSCTRL

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

56F8013/56F8011 Data Sheet, Rev. 12

36

Freescale Semiconductor

Peripheral Memory Mapped Registers

Table 4-10 Pulse Width Modulator Registers Address Map

(PWM_BASE = $00 F040)

Register Acronym

Address Offset

$0

Register Description

PWM_CTRL

PWM_FCTRL

PWM_FLTACK

PWM_OUT

Control Register

$1

$2

Fault Control Register

Fault Status Acknowledge Register

Output Control Register

Counter Register

$3

PWM_CNTR

PWM_CMOD

PWM_VAL0

PWM_VAL1

PWM_VAL2

PWM_VAL3

PWM_VAL4

PWM_VAL5

PWM_DTIM0

PWM_DTIM1

PWM_DMAP1

PWM_DMAP2

PWM_CNFG

PWM_CCTRL

PWM_PORT

PWM_ICCTRL

PWM_SCTRL

$4

$5

Counter Modulo Register

Value Register 0

$6

$7

Value Register 1

$8

Value Register 2

$9

Value Register 3

$A

$B

$C

$D

$E

$F

Value Register 4

Value Register 5

Dead Time Register 0

Dead Time Register 1

Disable Mapping Register 1

Disable Mapping Register 2

Configure Register

$10

$11

$12

$13

$14

Channel Control Register

Port Register

Internal Correction Control Register

Source Control Register

Table 4-11 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F060)

Register Acronym

Address Offset

Register Description

Interrupt Priority Register 0

ITCN_IPR0

ITCN_IPR1

ITCN_IPR2

ITCN_IPR3

ITCN_IPR4

ITCN_VBA

ITCN_FIM0

ITCN_FIVAL0

ITCN_FIVAH0

ITCN_FIM1

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

Interrupt Priority Register 1

Interrupt Priority Register 2

Interrupt Priority Register 3

Interrupt Priority Register 4

Vector Base Address Register

Fast Interrupt Match 0 Register

Fast Interrupt Vector Address Low 0 Register

Fast Interrupt Vector Address High 0 Register

Fast Interrupt Match 1 Register

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

37

Table 4-11 Interrupt Control Registers Address Map (Continued)

(ITCN_BASE = $00 F060)

Register Acronym

Address Offset

Register Description

ITCN_FIVAL1

ITCN_FIVAH1

ITCN_IRQP0

ITCN_IRQP1

ITCN_IRQP2

$A

$B

$C

$D

$E

Fast Interrupt Vector Address Low 1 Register

Fast Interrupt Vector Address High 1 Register

IRQ Pending Register 0

IRQ Pending Register 1

IRQ Pending Register 2

Reserved

ITCN_ICTRL

$12

Interrupt Control Register

Reserved

Table 4-12 Analog-to-Digital Converter Registers Address Map

(ADC_BASE = $00 F080)

Register Acronym

Address Offset

Register Description

Control Register 1

ADC_CTRL1

ADC_CTRL2

ADC_ZXCTRL

ADC_CLIST 1

ADC_CLIST 2

ADC_SDIS

$0

$1

Control Register 2

$2

Zero Crossing Control Register

Channel List Register 1

Channel List Register 2

Sample Disable Register

Status Register

$3

$4

$5

ADC_STAT

$6

ADC_LIMSTAT

ADC_ZXSTAT

ADC_RSLT0

ADC_RSLT1

ADC_RSLT2

ADC_RSLT3

ADC_RSLT4

ADC_RSLT5

ADC_RSLT6

ADC_RSLT7

ADC_LOLIM0

ADC_LOLIM1

ADC_LOLIM2

ADC_LOLIM3

ADC_LOLIM4

ADC_LOLIM5

ADC_LOLIM6

ADC_LOLIM7

$7

Limit Status Register

Zero Crossing Status Register

Result Register 0

$8

$9

$A

Result Register 1

$B

Result Register 2

$C

$D

$E

Result Register 3

Result Register 4

Result Register 5

$F

Result Register 6

$10

$11

$12

$13

$14

$15

$16

$17

$18

Result Register 7

Low Limit Register 0

Low Limit Register 1

Low Limit Register 2

Low Limit Register 3

Low Limit Register 4

Low Limit Register 5

Low Limit Register 6

Low Limit Register 7

56F8013/56F8011 Data Sheet, Rev. 12

38

Freescale Semiconductor

Peripheral Memory Mapped Registers

Table 4-12 Analog-to-Digital Converter Registers Address Map (Continued)

(ADC_BASE = $00 F080)

Register Acronym

Address Offset

$19

Register Description

High Limit Register 0

ADC_HILIM0

ADC_HILIM1

ADC_HILIM2

ADC_HILIM3

ADC_HILIM4

ADC_HILIM5

ADC_HILIM6

ADC_HILIM7

ADC_OFFST0

ADC_OFFST1

ADC_OFFST2

ADC_OFFST3

ADC_OFFST4

ADC_OFFST5

ADC_OFFST6

ADC_OFFST7

ADC_PWR

$1A

$1B

$1C

$1D

$1E

$1F

$20

$21

$22

$23

$24

$25

$26

$27

$28

$29

$2A

High Limit Register 1

High Limit Register 2

High Limit Register 3

High Limit Register 4

High Limit Register 5

High Limit Register 6

High Limit Register 7

Offset Register 0

Offset Register 1

Offset Register 2

Offset Register 3

Offset Register 4

Offset Register 5

Offset Register 6

Offset Register 7

Power Control Register

Voltage Reference Register

Reserved

ADC_VREF

Table 4-13 Serial Communication Interface Registers Address Map

(SCI_BASE = $00 F0B0)

Register Acronym

Address Offset

Register Description

Baud Rate Register

SCI_RATE

SCI_CTRL1

SCI_CTRL2

SCI_STAT

SCI_DATA

$0

$1

$2

$3

$4

Control Register 1

Control Register 2

Status Register

Data Register

Table 4-14 Serial Peripheral Interface Registers Address Map

(SPI_BASE = $00 F0C0)

Register Acronym

Address Offset

Register Description

Status and Control Register

SPI_SCTRL

SPI_DSCTRL

SPI_DRCV

SPI_DXMIT

$0

$1

$2

$3

Data Size and ControlRegister

Data Receive Register

Data Transmit Register

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

39

2

Table 4-15 I C Registers Address Map

(I2C_BASE = $00 F0D0)

Register Acronym

Address Offset

Register Description

I2C_ADDR

I2C_FDIV

I2C_CTRL

I2C_STAT

I2C_DATA

I2C_NFILT

$0

$1

$2

$3

$4

$5

Address Register

Frequency Divider Register

Control Register

Status Register

Data I/O Register

Noise Filter Register

Table 4-16 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F0E0)

Register Acronym

Address Offset

Register Description

COP_CTRL

COP_TOUT

COP_CNTR

$0

$1

$2

Control Register

Time-Out Register

Counter Register

Table 4-17 Clock Generation Module Registers Address Map

(OCCS_BASE = $00 F0F0)

Register Acronym

Address Offset

Register Description

OCCS_CTRL

OCCS_DIVBY

OCCS_STAT

$0

$1

$2

Control Register

Divide-By Register

Status Register

Reserved

OCCS_SHUTDN

OCCS_OCTRL

$4

$5

Shutdown Register

Oscillator Control Register

56F8013/56F8011 Data Sheet, Rev. 12

40

Freescale Semiconductor

Peripheral Memory Mapped Registers

Table 4-18 GPIOA Registers Address Map

(GPIOA_BASE = $00 F100)

Address Offset

Register Description

Register Acronym

GPIOA_PUPEN

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Pull-up Enable Register

GPIOA_DATA

GPIOA_DDIR

Data Register

Data Direction Register

GPIOA_PEREN

GPIOA_IASSRT

GPIOA_IEN

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

GPIOA_IEPOL

GPIOA_IPEND

GPIOA_IEDGE

GPIOA_PPOUTM

GPIOA_RDATA

GPIOA_DRIVE

Interrupt Edge Polarity Register

Interrupt Pending Register

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Register

Drive Strength Control Register

Table 4-19 GPIOB Registers Address Map

(GPIOB_BASE = $00 F110)

Register Acronym

Address Offset

Register Description

GPIOB_PUPEN

GPIOB_DATA

GPIOB_DDIR

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Pull-up Enable Register

Data Register

Data Direction Register

GPIOB_PEREN

GPIOB_IASSRT

GPIOB_IEN

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

Interrupt Edge Polarity Register

Interrupt Pending Register

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Register

GPIOB_IEPOL

GPIOB_IPEND

GPIOB_IEDGE

GPIOB_PPOUTM

GPIOB_RDATA

GPIOB_DRIVE

Drive Strength Control Register

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

41

Table 4-20 GPIOC Registers Address Map

(GPIOC_BASE = $00 F120)

Register Acronym

Address Offset

Register Description

GPIOC_PUPEN

GPIOC_DATA

GPIOC_DDIR

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Pull-up Enable Register

Data Register

Data Direction Register

GPIOC_PEREN

GPIOC_IASSRT

GPIOC_IEN

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

Interrupt Edge Polarity Register

Interrupt Pending Register

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Register

GPIOC_IEPOL

GPIOC_IPEND

GPIOC_IEDGE

GPIOC_PPOUTM

GPIOC_RDATA

GPIOC_DRIVE

Drive Strength Control Register

Table 4-21 GPIOD Registers Address Map

(GPIOD_BASE = $00 F130)

Register Acronym

Address Offset

Register Description

GPIOD_PUPEN

GPIOD_DATA

GPIOD_DDIR

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Pull-up Enable Register

Data Register

Data Direction Register

GPIOD_PEREN

GPIOD_IASSRT

GPIOD_IEN

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

Interrupt Edge Polarity Register

Interrupt Pending Register

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Register

GPIOD_IEPOL

GPIOD_IPEND

GPIOD_IEDGE

GPIOD_PPOUTM

GPIOD_RDATA

GPIOD_DRIVE

Drive Strength Control Register

56F8013/56F8011 Data Sheet, Rev. 12

42

Freescale Semiconductor

Peripheral Memory Mapped Registers

Table 4-22 System Integration Module Registers Address Map

(SIM_BASE = $00 F140)

Register Acronym

Address Offset

Register Description

SIM_CTRL

SIM_RSTAT

SIM_SWC0

SIM_SWC1

SIM_SWC2

SIM_SWC3

SIM_MSHID

SIM_LSHID

SIM_PWR

$0

$1

$2

$3

$4

$5

$6

$7

$8

Control Register

Reset Status Register

Software Control Register 0

Software Control Register 1

Software Control Register 2

Software Control Register 3

Most Significant Half JTAG ID

Least Significant Half JTAG ID

Power Control Register

Reserved

SIM_CLKOUT

SIM_GPS

$A

$B

$C

$D

$E

Clock Out Select Register

GPIO Peripheral Select Register

Peripheral Clock Enable Register

I/O Short Address Location High Register

I/O Short Address Location Low Register

SIM_PCE

SIM_IOSAHI

SIM_IOSALO

Table 4-23 Power Supervisor Registers Address Map

(PS_BASE = $00 F160)

Register Acronym

Address Offset

Register Description

PS_CTRL

PS_STAT

$0

$1

Control Register

Status Register

Table 4-24 Flash Module Registers Address Map

(FM_BASE = $00 F400)

Register Acronym

Address Offset

Register Description

Clock Divider Register

FM_CLKDIV

FM_CNFG

$0

$1

Configuration Register

Reserved

$2

FM_SECHI

FM_SECLO

$3

Security High Half Register

Security Low Half Register

Reserved

$4

$5 - $9

$10

FM_PROT

Protection Register

Reserved

$11 - $12

$13

FM_USTAT

User Status Register

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

43

Table 4-24 Flash Module Registers Address Map (Continued)

(FM_BASE = $00 F400)

Register Acronym

Address Offset

Register Description

Command Register

FM_CMD

$14

$15

$16

$17

$18

$19

$1A

$1B

Reserved

FM_DATA

Data Buffer Register

Reserved

FM_OPT1

Optional Data 1 Register

Reserved

FM_TSTSIG

$1D

Test Array Signature Register

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to

signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in

order to service this interrupt.

5.2 Features

The ITCN module design includes these distinctive features:

•

Programmable priority levels for each IRQ

Two programmable Fast Interrupts

Notification to SIM module to restart clocks out of Wait and Stop modes

Ability to drive initial address on the address bus after reset

For further information, see Table 4-2, Interrupt Vector Table Contents.

5.3 Functional Description

The Interrupt Controller contains registers that allow each of the 46 interrupt sources to be set to one of

four priority levels (excluding certain interrupts that are of fixed priority). All of the interrupt requests of

a given level are priority encoded to determine the lowest numerical value of the active interrupt requests

for that level. Within a given priority level, number 0 is the highest priority and number 45 is the lowest.

During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN can wake

up the core and restart system clocks by signaling a pending IRQ to the System Integration Module (SIM)

to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to

56F8013/56F8011 Data Sheet, Rev. 12

44

Freescale Semiconductor

Functional Description

entering the Wait or Stop mode.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

45

5.3.1

Normal Interrupt Handling

Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest

priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base

Address (VBA) and the vector number to determine the vector address, generating an offset into the vector

table for each interrupt.

5.3.2

Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be

serviced. The following table defines the nesting requirements for each priority level.

Table 5-1 Interrupt Mask Bit Definition

Exceptions Permitted

Exceptions Masked

SR[9]

SR[8]

0

1

0

1

0

1

Priorities 0, 1, 2, 3

Priorities 1, 2, 3

Priorities 2, 3

Priority 3

None

Priority 0

Priorities 0, 1

Priorities 0, 1, 2

5.3.3

Fast Interrupt Handling

Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes

Fast Interrupts before the core does.

A Fast Interrupt is defined (to the ITCN) by:

1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers

2. Setting the FIMn register to the appropriate vector number

3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt

When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a

match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector

address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an

offset from the VBA.

The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts

its Fast Interrupt handling.

56F8013/56F8011 Data Sheet, Rev. 12

46

Freescale Semiconductor

Block Diagram

5.4 Block Diagram

any0

Priority

Level

Level 0

46 -> 6

Priority

Encoder

6

2 -> 4

INT0

Decode

INT

VAB

IPIC

CONTROL

any3

IACK

SR[9:8]

Level 3

Priority

Level

46 -> 6

Priority

PIC_EN

6

Encoder

2 -> 4

Decode

INT45

Figure 5-1 Interrupt Controller Block Diagram

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

47

5.5 Register Descriptions

A register address is the sum of a base address and an address offset. The base address is defined at the

system level and the address offset is defined at the module level. The ITCN module has 16 registers.

Table 5-2 ITCN Register Summary

(ITCN_BASE = $00 F060)

Register

Acronym

Base Address +

Register Name

Section Location

IPR0

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

$C

$D

$E

Interrupt Priority Register 0

5.5.1

5.5.2

IPR1

Interrupt Priority Register 1

Interrupt Priority Register 2

Interrupt Priority Register 3

Interrupt Priority Register 4

Vector Base Address Register

Fast Interrupt Match 0 Register

Fast Interrupt 0 Vector Address Low Register

Fast Interrupt 0 Vector Address High 0 Register

Fast Interrupt Match 1 Register

Fast Interrupt 1 Vector Address Low Register

Fast Interrupt 1 Vector Address High Register

IRQ Pending Register 0

IPR2

5.5.3

IPR3

5.5.4

IPR4

5.5.5

VBA

5.5.6

FIM0

5.5.7

FIVAL0

FIVAH0

FIM1

5.5.8

5.5.9

5.5.10

5.5.11

5.5.12

5.5.13

5.5.14

5.5.15

FIVAL1

FIVAH1

IRQP0

IRQP1

IRQP2

IRQ Pending Register 1

IRQ Pending Register 2

Reserved

ICTRL

$12

Interrupt Control Register

5.5.16

Reserved

56F8013/56F8011 Data Sheet, Rev. 12

48

Freescale Semiconductor

Register Descriptions

Add.

Offset

Register

Name

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

W

R

0

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

$C

$D

$E

IPR0

IPR1

LVI IPL

RX_REG IPL TX_REG IPL TRBUF IPL

BKPT_U IPL

FM_ERR IPL

SPI_RCV IPL

STPCNT IPL

PLL IPL

0

GPIOB IPL

GPIOC IPL

GPIOD IPL

FM_CBE IPL FM_CC IPL

W

R

0

SCI_RCV

IPL

SCI_RERR

IPL

SCI_XMIT

IPL

SPI_XMIT

IPL

IPR2

SCI_TIDLIPL

TMR_1 IPL

GPIOA IPL

W

R

0

ADCA_CC

IPL

I2C_ADDR

IPL

IPR3

TMR_3 IPL

TMR_2 IPL

TMR_0 IPL

W

R

0

ADC_ZC_LE

IPL

IPR4

PWM_F IPL PWM_RL IPL

ADCB_CC IPL

W

R

VBA

VECTOR_BASE_ADDRESS

W

R

0

FIM0

FAST INTERRUPT 0

W

R

FIVAL0

FIVAH0

FIM1

FAST INTERRUPT 0 VECTOR ADDRESS LOW

W

R

0

FAST INTERRUPT 0 VECTOR

ADDRESS HIGH

W

R

FAST INTERRUPT 1

W

R

FIVAL1

FIVAH1

IRQP0

IRQP1

IRQP2

FAST INTERRUPT 1 VECTOR ADDRESS LOW

W

R

0

FAST INTERRUPT 1 VECTOR

ADDRESS HIGH

W

R

PENDING[16:2]

1

W

R

PENDING[32:17]

W

R

1

PENDING[45:33]

W

Reserved

ICTRL

R

INT

IPIC

VAB

1

0

INT_

DIS

$12

W

Reserved

= Reserved

Figure 5-2 ITCN Register Map Summary

5.5.1

Interrupt Priority Register 0 (IPR0)

Base + $0

15

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

Read

Write

LVI IPL

RX_REG IPL TX_REG IPL

TRBUF IPL

BKPT_U IPL STPCNT IPL

0

RESET

Figure 5-3 Interrupt Priority Register 0 (IPR0)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

49

5.5.1.1

LVI IPL—Bits 15–14

This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities

0 through 2 and is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.1.2

Reserved—Bits 13–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.1.3

EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)— Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.5.1.4

EOnCE Transmit Register Empty Interrupt Priority Level

(TX_REG IPL)— Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.5.1.5

EOnCE Trace Buffer Interrupt Priority Level

(TRBUF IPL)— Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.5.1.6

EOnCE Breakpoint Unit Interrupt Priority Level

(BKPT_U IPL)— Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

56F8013/56F8011 Data Sheet, Rev. 12

50

Freescale Semiconductor

Register Descriptions

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.5.1.7

EOnCE Step Counter Interrupt Priority Level

(STPCNT IPL)— Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.5.2

Interrupt Priority Register 1 (IPR1)

Base + $1

Read

15

14

13

12

11

10

9

0

8

0

7

6

5

4

3

2

1

0

GPIOB IPL

GPIOC IPL

GPIOD IPL

FM_CBE IPL

FM_CC IPL

FM_ERR IPL

PLL IPL

Write

0

RESET

Figure 5-4 Interrupt Priority Register 1 (IPR1)

GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 15–14

5.5.2.1

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.2.2

GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

51

5.5.2.3

GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.2.4

Reserved—Bits 9–8

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.2.5

FM Command, Data, Address Buffers Empty Interrupt Priority Level

(FM_CBE IPL)—Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.2.6

FM Command Complete Priority Level (FM_CC IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.2.7

FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8013/56F8011 Data Sheet, Rev. 12

52

Freescale Semiconductor

Register Descriptions

5.5.2.8

PLL Loss of Reference or Change in Lock Status Interrupt Priority Level

(PLL IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.3

Interrupt Priority Register 2 (IPR2)

Base + $2

Read

15

14

13

12

11

0

10

0

9

8

7

6

5

4

3

2

1

0

SCI_RERR

IPL

SCI_RCV IPL

SCI_TIDL IPL SCI_XMIT IPL SPI_XMIT IPL SPI_RCV IPL

GPIOA IPL

Write

0

RESET

Figure 5-5 Interrupt Priority Register 2 (IPR2)

5.5.3.1

SCI Receiver Full Interrupt Priority Level (SCI_RCV IPL)—

Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.3.2

SCI Receiver Error Interrupt Priority Level (SCI_RERR IPL)—

Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.3.3

Reserved—Bits 11–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

53

5.5.3.4

SCI Transmitter Idle Interrupt Priority Level (SCI_TIDL IPL)—

Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.3.5

SCI Transmitter Empty Interrupt Priority Level (SCI_XMIT IPL)—

Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.3.6

SPI Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)—

Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.3.7

SPI Receiver Full Interrupt Priority Level (SPI_RCV IPL)—

Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8013/56F8011 Data Sheet, Rev. 12

54

Freescale Semiconductor

Register Descriptions

5.5.3.8

GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.4

Interrupt Priority Register 3 (IPR3)

Base + $3

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

0

2

0

1

0

I2C_ADDR

IPL

ADCA_CC IPL TMR_3 IPL

TMR_2 IPL

TMR_1 IPL

TMR_0 IPL

Write

0

RESET

Figure 5-6 Interrupt Priority Register 3 (IPR3)

5.5.4.1

ADCA Conversion Complete Interrupt Priority Level

(ADCA_CC IPL)—Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.4.2

Timer Channel 3 Interrupt Priority Level (TMR_3 IPL)—Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.4.3

Timer Channel 2 Interrupt Priority Level (TMR_2 IPL)—Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

55

5.5.4.4

Timer Channel 1 Interrupt Priority Level (TMR_1 IPL)—Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.4.5

Timer Channel 0 Interrupt Priority Level (TMR_0 IPL)—Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

2

5.5.4.6

I C Address Detect Interrupt Priority Level (I2C_ADDR IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.4.7

Reserved—Bits 3–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.5

Interrupt Priority Register 4 (IPR4)

Base + $4

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

6

5

4

3

2

1

0

ADC_ZC_LE

IPL

ADCB_CC

IPL

PWM_F IPL PWM_RL IPL

Write

0

RESET

Figure 5-7 Interrupt Priority Register 4 (IPR4)

Reserved—Bits 15–8

5.5.5.1

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

56F8013/56F8011 Data Sheet, Rev. 12

56

Freescale Semiconductor

Register Descriptions

5.5.5.2

PWM Fault Interrupt Priority Level (PWM_F IPL)—

Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.5.3

Reload PWM Interrupt Priority Level (PWM_RL IPL)—

Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.5.4

ADC Zero Crossing or Limit Error Interrupt Priority Level

(ADC_ZC_LE IPL)— Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.5.5.5

ADCB Conversion Complete Interrupt Priority Level

(ADCB_CC IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

57

5.5.6

Vector Base Address Register (VBA)

Base + $5

Read

15

0

14

0

13

12

11

10

9

8

7

6

5

4

0

3

0

2

0

1

0

VECTOR_BASE_ADDRESS

Write

RESET¹

0

1. The 56F8013 resets to a value of 0x0000. This corresponds to reset addresses of 0x000000.

The 56F8011 resets to a value of 0x0010. This corresponds to reset addresses of 0x000800.

Figure 5-8 Vector Base Address Register (VBA)

5.5.6.1

Reserved—Bits 15–14

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.6.2

Vector Address Bus (VAB) Bits 13—0

The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits

are determined based on the highest priority interrupt and are then appended onto VBA before presenting

the full VAB to the Core.

5.5.7

Fast Interrupt Match 0 Register (FIM0)

Base + $6

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

FAST INTERRUPT 0

Write

0

RESET

Figure 5-9 Fast Interrupt Match 0 Register (FIM0)

5.5.7.1

Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.7.2

Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority

level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.

Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to

the vector table.

56F8013/56F8011 Data Sheet, Rev. 12

58

Freescale Semiconductor

Register Descriptions

5.5.8

Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Base + $7

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

1

0

FAST INTERRUPT 0 VECTOR ADDRESS LOW

Write

RESET

0

Figure 5-10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0

5.5.8.1

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.5.9

Fast Interrupt 0 Vector Address High Register (FIVAH0)

Base + $8

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

3

2

1

0

FAST INTERRUPT 0 VECTOR

ADDRESS HIGH

Write

RESET

0

Figure 5-11 Fast Interrupt 0 Vector Address High Register (FIVAH0)

Reserved—Bits 15–5

5.5.9.1

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.9.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.5.10 Fast Interrupt 1 Match Register (FIM1)

Base + $9

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

FAST INTERRUPT 1

Write

0

RESET

Figure 5-12 Fast Interrupt 1 Match Register (FIM1)

5.5.10.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.10.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

59

Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority

level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt.

Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to

the vector table.

5.5.11 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Base + $A

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

1

0

FAST INTERRUPT 1 VECTOR ADDRESS LOW

Write

0

RESET

Figure 5-13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

5.5.11.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1

to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.5.12 Fast Interrupt 1 Vector Address High (FIVAH1)

Base + $B

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

FAST INTERRUPT 1 VECTOR

ADDRESS HIGH

Write

0

RESET

Figure 5-14 Fast Interrupt 1 Vector Address High Register (FIVAH1)

5.5.12.1 Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.12.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1

to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.5.13 IRQ Pending Register 0 (IRQP0)

Base + $C

Read

15

14

13

12

11

10

9

8

7

6

1

5

1

4

1

3

1

2

1

0

1

PENDING[16:2]

Write

RESET

1

Figure 5-15 IRQ Pending Register 0 (IRQP0)

56F8013/56F8011 Data Sheet, Rev. 12

60

Freescale Semiconductor

Register Descriptions

5.5.13.1 IRQ Pending (PENDING)—Bits 15–1

This register combines with IRQP1 and IRQP2 to represent the pending IRQs for interrupt vector numbers

2 through 45.

•

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.5.13.2 Reserved—Bit 0

This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.5.14 IRQ Pending Register 1 (IRQP1)

Base + $D

Read

15

14

13

12

11

10

9

8

7

6

1

5

1

4

1

3

1

2

1

0

1

PENDING[32:17]

Write

1

RESET

Figure 5-16 IRQ Pending Register 1 (IRQP1)

5.5.14.1 IRQ Pending (PENDING)—Bits 32–17

This register combines with IRQP0 and IRQP2 to represent the pending IRQs for interrupt vector numbers

2 through 45.

•

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.5.15 IRQ Pending Register 2 (IRQP2)

Base + $E

Read

15

1

14

1

13

1

12

11

10

9

8

1

7

6

5

4

1

3

1

2

1

0

1

PENDING[45:33]

Write

1

RESET

Figure 5-17 IRQ Pending Register 2 (IRQP2)

5.5.15.1 IRQ Pending (PENDING)—Bits 45–33

This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers

2 through 45.

•

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

61

5.5.16 Interrupt Control Register (ICTRL)

$Base + $12

Read

15

14

13

12

11

10

9

8

7

0

6

0

5

4

1

3

1

2

1

0

INT

IPIC

VAB

INT_

DIS

Write

RESET

0

1

0

Figure 5-18 Interrupt Control Register (ICTRL)

5.5.16.1 Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

•

0 = No interrupt is being sent to the 56800E core

1 = An interrupt is being sent to the 56800E core

5.5.16.2 Interrupt Priority Level (IPIC)—Bits 14–13

These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E

core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being

sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service

routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

•

00 = Required nested exception priority levels are 0, 1, 2, or 3

01 = Required nested exception priority levels are 1, 2, or 3

10 = Required nested exception priority levels are 2 or 3

11 = Required nested exception priority level is 3

Table 5-3 Interrupt Priority Encoding

Current Interrupt

Priority Level

Required Nested

Exception Priority

IPIC_VALUE[1:0]

00

01

10

11

No interrupt or SWILP

Priority 0

Priorities 0, 1, 2, 3

Priorities 1, 2, 3

Priorities 2, 3

Priority 3

Priority 1

Priority 2 or 3

5.5.16.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6

This read-only field shows the vector number (VAB[6:0]) used at the time the last IRQ was taken. In the

case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when

the 56800E core jumps to a new interrupt service routine.

56F8013/56F8011 Data Sheet, Rev. 12

62

Freescale Semiconductor

Resets

Note:

Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

5.5.16.4 Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.

•

0 = Normal operation (default)

1 = All interrupts disabled

5.5.16.5 Reserved—Bits 4–2

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.5.16.6 Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6 Resets

5.6.1

General

Table 5-4 Reset Summary

Source

Characteristics

Reset

Priority

Core Reset

RST

Core reset from the SIM

5.6.2

Description of Reset Operation

Reset Handshake Timing

5.6.2.1

The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is

asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET

is released. The general timing is shown in Figure 5-19.

RES

CLK

RESET_VECTOR_ADR

VAB

PAB

READ_ADR

Figure 5-19 Reset Interface

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

63

5.6.3

ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,

except the core IRQs with fixed priorities:

•

Illegal Instruction

SW Interrupt 3

HW Stack Overflow

Misaligned Long Word Access

SW Interrupt 2

SW Interrupt 1

SW Interrupt 0

SW Interrupt LP

These interrupts are enabled at their fixed priority levels.

Part 6 System Integration Module (SIM)

6.1 Introduction

The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls

distribution of resets and clocks and provides a number of control features. The System Integration Module

is responsible for the following functions:

•

Reset sequencing

Clock control & distribution

Stop/Wait control

System status registers

Registers for software access to the JTAG ID of the chip

Test registers

Power control

I/O pad multiplexing

These are discussed in more detail in the sections that follow.

56F8013/56F8011 Data Sheet, Rev. 12

64

Freescale Semiconductor

Features

6.2 Features

The SIM has the following features:

•

Reset sequencing

Core and peripheral clock control and distribution

Stop/Wait mode control

System status

Power control

Control I/O multiplexing

System bus clocks with pipeline hold-off support

System clocks for non-pipelined interfaces

Peripheral clocks for Quad Timer and PWM with high-speed (3X) option

Power-saving clock gating for peripherals

Three power modes (Run, Wait, Stop) to control power utilization

— Stop mode shuts down the 56800E core, system clock, and peripheral clock

— Wait mode shuts down the 56800E core and unnecessary system clock operation

— Run mode supports full part operation

•

Controls, with write protection, the enable/disable of 56800E core WAIT and STOP instructions

Controls, with write protection, the enable/disable of Large Regulator Standby mode

Controls to route functional signals to selected peripherals and I/O pads

Controls deassertion sequence of internal resets

Software-initiated reset

Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control

Timer channel Stop mode clocking controls

SCI Stop mode clocking control to support LIN Sleep mode stop recovery

Short addressing location control

Registers for containing the JTAG ID of the chip

Controls output to CLKO pin

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

65

6.3 Register Descriptions

Table 6-1 SIM Registers (SIM_BASE = $00 F140)

Address Offset

Address Acronym

Register Name

Control Register

Section Location

Base + $0

Base + $1

Base + $2

Base + $3

Base + $4

Base + $5

Base + $6

Base + $7

Base + $8

SIM_CTRL

SIM_RSTAT

SIM_SWC0

SIM_SWC1

SIM_SWC2

SIM_SWC3

SIM_MSHID

SIM_LSHID

SIM_PWR

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

Reset Status Register

Software Control Register 0

Software Control Register 1

Software Control Register 2

Software Control Register 3

Most Significant Half of JTAG ID

Least Significant Half of JTAG ID

Power Control Register

Reserved

Base + $A

Base + $B

Base + $C

Base + $D

Base + $E

SIM_CLKOUT

SIM_GPS

CLKO Select Register

6.3.7

6.3.8

GPIO Peripheral Select Register

Peripheral Clock Enable Register

I/O Short Address Location High Register

I/O Short Address Location Low Register

SIM_PCE

6.3.9

SIM_IOSAHI

SIM_IOSALO

6.3.10

56F8013/56F8011 Data Sheet, Rev. 12

66

Freescale Semiconductor

Register Descriptions

Add.

Address

Offset Acronym

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

W

R

0

SIM_

CTRL

TC3_ TC2_ TC1_ TC0_

SCI_

SD

TC3_

INP

ONCE SW

EBL0 RST

STOP_

DISABLE

WAIT_

DISABLE

$0

SD

0

SD

0

SD

0

SD

0

SIM_

$1

SWR COPR EXTR POR

RSTAT

W

R

$2

$3

$4

$5

$6

$7

$8

SIM_SWC0

SIM_SWC1

SIM_SWC2

SIM_SWC3

SIM_MSHID

SIM_LSHID

Software Control Data 0

Software Control Data 1

Software Control Data 2

Software Control Data 3

W

R

W

R

W

R

W

R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

W

R

W

R

SIM_PWR

Reserved

LRSTDBY

W

R

W

R

0

SIM_

CLKOUT

CLK

DIS

$A

$B

$C

PWM3 PWM2 PWM1 PWM0

CLKOSEL

CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_

B7

SIM_GPS

SIM_PCE

TCR

PCR

0

CFG_A5

CFG_A4

0

B6

B5

B4

B3

B2

B1

B0

W

R

0

I2C

0

ADC

0

TMR

0

SCI

0

SPI

0

PWM

W

R

0

1

0

$D SIM_IOSAHI

$E SIM_IOSALO

ISAL[23:22]

W

R

ISAL[21:6]

W

0

= Read as 0

= Reserved

= Read as 1

= Reserved

Figure 6-1 SIM Register Map Summary

6.3.1

SIM Control Register (SIM_CTRL)

Base + $0

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TC3_ TC2_ TC1_ TC0_ SCI_

SD

TC3_

INP

ONCE SW

EBL

STOP_

DISABLE

WAIT_

DISABLE

SD

RST

Write

RESET

0

Figure 6-2 SIM Control Register (SIM_CTRL)

6.3.1.1

Timer Channel 3 Stop Disable (TC3_SD)—Bit 15

This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode.

•

0 = Timer Channel 3 disabled in Stop mode

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

67

•

1 = Timer Channel 3 enabled in Stop mode

6.3.1.2

Timer Channel 2 Stop Disable (TC2_SD)—Bit 14

This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode.

•

0 = Timer Channel 2 disabled in Stop mode

1 = Timer Channel 2 enabled in Stop mode

6.3.1.3

Timer Channel 1 Stop Disable (TC1_SD)—Bit 13

This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode.

•

0 = Timer Channel 1 disabled in Stop mode

1 = Timer Channel 1 enabled in Stop mode

6.3.1.4

Timer Channel 0 Stop Disable (TC0_SD)—Bit 12

This bit enables the operation of the Timer Channel 0 peripheral clock in Stop mode.

•

0 = Timer Channel 0 disabled in Stop mode

1 = Timer Channel 0 enabled in Stop mode

6.3.1.5

SCI Stop Disable (SCI_SD)—Bit 11

This bit enables the operation of the SCI peripheral clock in Stop mode. This is recommended for use in

LIN mode so that the SCI can generate interrupts and recover from Stop mode while the LIN interface is

in Sleep mode and using Stop mode to reduce power consumption.

•

0 = SCI disabled in Stop mode

1 = SCI enabled in Stop mode

6.3.1.6

Reserved—Bit 10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.1.7

Timer Channel 3 Input (TC3_INP)—Bit 9

This bit selects the input of Timer Channel 3 to be from the PWM Sync signal or GPIO pin.

•

1 = Timer Channel 3 Input from PWM sync signal

0 = Timer Channel 3 Input controlled by SIM_GPS register CFG_B3 and CFG_A5 fields

6.3.1.8

Reserved—Bits 8–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.1.9

OnCE Enable (ONCEEBL)—Bit 5

•

0 = OnCE clock to 56800E core enabled when core TAP is enabled

1 = OnCE clock to 56800E core is always enabled

6.3.1.10 Software Reset (SWRST)—Bit 4

Writing 1 to this field will cause the part to reset.

56F8013/56F8011 Data Sheet, Rev. 12

68

Freescale Semiconductor

Register Descriptions

6.3.1.11 Stop Disable (STOP_DISABLE[1:0])—Bits 3–2

•

00 = Stop mode will be entered when the 56800E core executes a STOP instruction

01 = The 56800E STOP instruction will not cause entry into Stop mode

10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the

STOP_DISABLE field is write-protected until the next reset

•

11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is

write-protected until the next reset

6.3.1.12 Wait Disable (WAIT_DISABLE[1:0])—Bits 1–0

•

00 = Wait mode will be entered when the 56800E core executes a WAIT instruction

01 = The 56800E WAIT instruction will not cause entry into Wait mode

10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the

WAIT_DISABLE field is write-protected until the next reset

•

11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is

write-protected until the next reset

6.3.2

SIM Reset Status Register (SIM_RSTAT)

This register is updated upon any system reset and indicates the cause of the most recent reset. It also

controls whether the COP reset vector or regular reset vector in the vector table is used. This register is

asynchronously reset during Power-On Reset (see power supervisor module) and subsequently is

synchronously updated based on the level of the external reset, software reset, or cop reset inputs. Only

one source will ever be indicated. In the event that multiple reset sources assert simultaneously, the

highest-precedence source will be indicated. The precedence from highest to lowest is POR, EXTR,

COPR, and SWR. While POR is always set during a Power-On Reset, EXTR will become set if the

external reset pin is asserted or remains asserted after the Power-On Reset (POR) has deasserted.

Base + $1

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SWR COPR

EXTR POR

Write

0

RESET

Figure 6-3 SIM Reset Status Register (SIM_RSTAT)

6.3.2.1

Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing.

6.3.2.2

Software Reset (SWR)—Bit 5

When set, this bit indicates that the previous system reset occurred as a result of a software reset (written

1 to SWRST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also

occurred.

6.3.2.3

COP Reset (COPR)—Bit 4

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

69

(COP) timer. It will not be set if an external or POR reset also occurred. If COPR is set as code starts

executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.4

External Reset (EXTR)—Bit 3

When set, this bit indicates that the previous system reset was caused by an external reset. It will only be

set if the external reset pin was asserted or remained asserted after the Power-On Reset deasserted.

6.3.2.5

Power-On Reset (POR)—Bit 2

This bit is set during a Power-On Reset.

6.3.2.6

Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.3

SIM Software Control Registers (SIM_SWC0, SIM_SWC1,

SIM_SWC2, and SIM_SWC3)

Only SIM_SWC0 is shown in this section. SIM_SWC1, SIM_SWC2, and SIM_SWC3 are identical in

functionality.

Base + $2

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Software Control Data 0

Write

0

RESET

Figure 6-4 SIM Software Control Register 0 (SIM_SWC0)

Software Control Data 0 (FIELD)—Bits 15–0

6.3.3.1

This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is

intended for use by a software developer to contain data that will be unaffected by the other reset sources

(RESET pin, software reset, and COP reset).

6.3.4

Most Significant Half of JTAG ID (SIM_MSHID)

This read-only register displays the most significant half of the JTAG ID for the chip. This register reads

$01F2.

Base + $6

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

Write

0

1

0

1

0

RESET

Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)

56F8013/56F8011 Data Sheet, Rev. 12

70

Freescale Semiconductor

Register Descriptions

6.3.5

Least Significant Half of JTAG ID (SIM_LSHID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register reads

$401D.

Base + $7

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

Write

RESET

0

1

0

1

0

1

Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)

6.3.6

SIM Power Control Register (SIM_PWR)

This register controls the Standby mode of the large regulator. The large regulator derives the core digital

logic power supply from the IO power supply. In some circumstances, the large regulator may be put in a

reduced-power Standby mode without interfering with part operation. Refer to the overview of

power-down modes and the overview of clock generation for more information on the use of large

regulator standby.

Base + $8

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LRSTDBY

Write

0

RESET

Figure 6-7 SIM Power Control Register (SIM_PWR)

6.3.6.1

Reserved—Bits 15–2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.6.2

Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0

This bit controls the pull-up resistors on the IRQA pin.

•

00 = Large regulator is in Normal mode

01 = Large regulator is in Standby (reduced-power) mode

10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset

11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset

NOTE:

Standby mode can be used when device operates below 200KHz with PLL shut

down.

6.3.7

CLKO Select Register (SIM_CLKOUT)

The CLKO select register can be used to multiplex out selected clocks generated inside the clock

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

71

generation and SIM modules. All functionality is for test purposes only and is subject to

unspecified latencies. Glitches may be produced when the clock is enabled or switched.

The lower four bits of the GPIO A register can function as GPIO, PWM, or as additional clock output

signals. GPIO has priority and is enabled/disabled via the GPIOA_PEREN. If GPIOA[3:0] are

programmed to operate as peripheral outputs, then the choice between PWM and additional clock outputs

is done here in the CLKOUT. The default state is for the peripheral function of GPIOA[3:0] to be

programmed as PWM. This can be changed by altering PWM3 through PWM0.

Base + $A

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

CLKOSEL

0

1

0

CLK

DIS

PWM3 PWM2 PWM1 PWM0

Write

0

1

0

RESET

Figure 6-8 CLKO Select Register (SIM_CLKOUT)

6.3.7.1

Reserved—Bits 15–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.7.2

PWM3—Bit 9

•

0 = Peripheral output function of GPIOA[3] is defined to be PWM3

1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock

6.3.7.3

PWM2—Bit 8

•

0 = Peripheral output function of GPIOA[2] is defined to be PWM2

1 = Peripheral output function of GPIOA[2] is defined to be the system clock

6.3.7.4

PWM1—Bit 7

•

0 = Peripheral output function of GPIOA[1] is defined to be PWM1

1 = Peripheral output function of GPIOA[1] is defined to be two times the rate of the system clock

6.3.7.5

PWM0—Bit 6

•

0 = Peripheral output function of GPIOA[0] is defined to be PWM0

1 = Peripheral output function of GPIOA[0] is defined to be three times the rate of the system clock

6.3.7.6

Clockout Disable (CLKDIS)—Bit 5

•

0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL

1 = CLKOUT is 0

6.3.7.7

Clockout Select (CLKOSEL)—Bits 4–0

Selects clock to be muxed out on the CLKO pin.

•

00000 = Reserved for factory test—Continuous system clock

56F8013/56F8011 Data Sheet, Rev. 12

72

Freescale Semiconductor

Register Descriptions

•

01001 = Reserved for factory test—OCCS MSTR OSC clock

01011 = Reserved for factory test—ADC clock

01100 = Reserved for factory test—JTAG TCLK

01101 = Reserved for factory test—Continuous peripheral clock

01110 = Reserved for factory test—Continuous inverted peripheral clock

01111 = Reserved for factory test—Continuous high-speed peripheral clock

6.3.8

SIM GPIO Peripheral Select Register (SIM_GPS)

All of the peripheral pins on the 56F8013/56F8011 share their Input/Output (I/O) with GPIO ports. To

select peripheral or GPIO control, program corresponding bit in the GPIOx_PEREN register in GPIO

module. See the 56F801x Peripheral Reference Manual for detail. In some cases, there are two possible

peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS

register is used to determine which peripheral has control when the corresponding I/O pin is configured in

peripheral mode.

As shown in Figure 6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which

pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when

PEREN = 1.

GPIOB_PEREN Register

GPIO Controlled

0

1

I/O Pad Control

SIM_GPS Register

0

1

Quad Timer Controlled

SCI Controlled

Figure 6-9 Overall Control of Pads Using SIM_GPS Control

Base + $B

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_

B7

TCR PCR

CFG_A5

CFG_A4

B6

B5

B4

B3

B2

B1

B0

Write

0

RESET

Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

73

6.3.8.1

Quad Timer Clock Rate (TCR)—Bit 15

This bit selects the clock speed for the Quad Timermodule.

•

0 = Quad Timer module clock rate equals system clock rate, to a maximum 32MHz (default)

1 = Quad Timer module clock rate equals three times system clock rate, to a maximum 96MHz

Note: This bit should only be changed while the TMR module’s clock is disabled. See Section 6.3.9.

Note: High-speed clocking is only available when the PLL is being used.

Note: If the PWM sync signal pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section

6.3.1.7), then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

6.3.8.2

PWM Clock Rate (PCR)—Bit 14

This bit selects the clock speed for the PWM module.

•

0 = PWM module clock rate equals system clock rate, to a maximum 32MHz (default)

1 = PWM module clock rate equals three times system clock rate, to a maximum 96MHz

Note: This bit should only be changed while the PWM module’s clock is disabled. See Section 6.3.9.

Note: High-speed clocking is only available when the PLL is being used.

Note: If the PWM sync signal is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7),

then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

Table 6-2 Allowable Quad Timer and PWM Clock Rates

when Using PWM Reload Pulse

Quad Timer

1X

3X

Clock Speed

1X

3X

OK

NO

OK

PWM

6.3.8.3

Reserved—Bits 13–12

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.8.4

Configure GPIOB7 (CFG_B7)—Bit 11

This bit selects the alternate function for GPIOB7.

•

0 = TXD — SCI Transmit Data (default)

1 = SCL — I2C Serial Clock

6.3.8.5

Configure GPIOB6 (CFG_B6)—Bit 10

This bit selects the alternate function for GPIOB6.

56F8013/56F8011 Data Sheet, Rev. 12

74

Freescale Semiconductor

Register Descriptions

•

0 = RXD — SCI Receive Data(default)

1 = SDA — I2C Serial Data

Note: The PRECS bit in the OCCS Oscillator Control register can enable this pin as the

source clock to the chip. In this mode, make sure that no on-chip peripheral (including the

GPIO) is driving this pin.

6.3.8.6

Configure GPIOB5 (CFG_B5)—Bit 9

This bit selects the alternate function for GPIOB5.

•

0 = T1 — Timer Channel 1 input/output(default)

1 = FAULT3 — PWM FAULT3 Input

6.3.8.7

Configure GPIOB4 (CFG_B4)—Bit 8

This bit selects the alternate function for GPIOB4.

•

0 = T0 — Timer Channel 0 input/output (default)

1 = CLKO — Clock Output

6.3.8.8

Configure GPIOB3 (CFG_B3)—Bit 7

This bit selects the alternate function for GPIOB3.

•

0 = MOSI — SPI Master Out/Slave In (default)

1 = T3 — Time Channel 3 input/output

6.3.8.9

Configure GPIOB2 (CFG_B2)—Bit 6

This bit selects the alternate function for GPIOB2.

•

0 = MISO — SPI Master In/Slave Out (default)

1 = T2 — Timer Channel 2 input/output

6.3.8.10 Configure GPIOB1 (CFG_B1)—Bit 5

This bit selects the alternate function for GPIOB1.

•

0 = SS — SPI Slave Select(default)

1 = SDA— I2C Serial Data

6.3.8.11 Configure GPIOB0 (CFG_B0)—Bit 4

This bit selects the alternate function for GPIOB0.

•

0 = SCLK — SPI Serial Clock (default)

1 = SCL — I2C Serial Clock

6.3.8.12 Configure GPIOA5[1:0] (CFG_A5)—Bits 3–2

These bits select the alternate function for GPIOA5.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

75

•

00 = PWM5 — PWM5 Output (default)

01 = PWM5 — PWM5 Output

10 = FAULT2 — PWM FAULT2 Input

11 = T3 — Timer Channel 3 input/output

6.3.8.13 Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0

These bits select the alternate function for GPIOA4.

•

00 = PWM4 — PWM4 Output (default)

01 = PWM4 — PWM4 Output

10 = FAULT1— PWM FAULT1 Input

11 = T2 — Timer Channel 2 input/output

NOTE:

Take care when programming the following CFG_* signals so as not to connect

two different I/O pins to the same peripheral input. For example, do not set

CFG_B7 to select SCL and also set CFG_B0 to select SCL. If this occurs for an

output signal, then the signal will be routed to two I/O pins. For input signals, the

values on the two I/O pins will be ORed together before reaching the peripheral.

6.3.9

Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power

savings feature. The clocks can be individually controlled for each peripheral on the chip. The

corresponding peripheral should itself be disabled while its clock is shut off.

Base + $C

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

I2C

ADC

TMR

SCI

SPI

PWM

Write

0

RESET

Figure 6-11 Peripheral Clock Enable Register (SIM_PCE)

I C Clock Enable (I2C)—Bit 15

2

6.3.9.1

•

0 = The clock is not provided to the I2C module(the 12C module is disabled)

1 = Clocks to the I²C module are enabled

•

6.3.9.2

Reserved—Bit 14

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.3

Analog-to-Digital Converter IPBus Clock Enable (ADC)—Bit 13

•

0 = The clock is not provided to the ADC module (the ADC module is disabled)

1 = Clocks to the ADC module are enabled

56F8013/56F8011 Data Sheet, Rev. 12

76

Freescale Semiconductor

Register Descriptions

6.3.9.4

Reserved—Bits 12–7

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.5

Timer Clock Enable (TMR)—Bit 6

•

0 = The clock is not provided to the Quad Timer module(the Quad Timer module is disabled)

1 = Clocks to the Quad Timer module are enabled

6.3.9.6

Reserved—Bit 5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.7

SCI Clock Enable (SCI)—Bit 4

•

0 = The clock is not provided to the SCI module (the SCI module is disabled)

1 = Clocks to the SCI module are enabled

6.3.9.8

Reserved—Bit 3

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.9

SPI Clock Enable (SPI)—Bit 2

•

0 = The clock is not provided to the SPI module (the SPI module is disabled)

1 = Clocks to the SPI module are enabled

6.3.9.10 Reserved—Bit 1

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.9.11 PWM Clock Enable (PWM)—Bit 0

•

0 = The clock is not provided to the PWM module (the PWM module is disabled)

1 = Clocks to the PWM module are enabled

6.3.10 I/O Short Address Location Register (SIM_IOSAHI and

SIM_IOSALO)

The I/O Short Address Location registers are used to specify the memory referenced via the I/O short

address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;

the upper address bits are not directly controllable. This register set allows limited control of the full

address, as shown in Figure 6-12.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

77

Instruction Portion

“Hard Coded” Address Portion

6 Bits from I/O Short Address Mode Instruction

16 Bits from SIM_IOSALO Register

2 bits from SIM_IOSAHI Register

Full 24-Bit for Short I/O Address

Figure 6-12 I/O Short Address Determination

With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral

registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register

to its previous contents prior to returning from interrupt.

Note:

The default value of this register set points to the EOnCE registers.

The pipeline delay between setting this register set and using short I/O addressing with the new value

is five instruction cycles.

Base + $D

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ISAL[23:22]

Write

0

1

RESET

Figure 6-13 I/O Short Address Location High Register (SIM_IOSAHI)

6.3.10.1 Reserved—Bits 15—2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.10.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0

This field represents the upper two address bits of the “hard coded” I/O short address.

56F8013/56F8011 Data Sheet, Rev. 12

78

Freescale Semiconductor

Clock Generation Overview

Base + $E

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ISAL[21:6]

Write

1

RESET

Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)

6.3.10.3 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.4 Clock Generation Overview

The SIM uses master clocks, 2X system clock at a maximum of 64MHz, from the OCCS module to

produce the peripheral and system (core and memory) clocks at a maximum of 32MHz. It divides the

master clock by two and gates it with appropriate power mode and clock gating controls. The high speed

peripheral clock from OCCS operates at three times the system clock for PWM and Quad Timer module

at a maximum of 96MHz.

The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either

an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). The

relaxation oscillator can be operated at full speed (8MHz), standby speed (200kHz), or powered down. An

8MHz clock can be multiplied to 192 MHz using the PLL and postscaled to provide a variety of high speed

clock rates. Either the postscaled PLL output or input clock of PLL signal can be selected to produce the

master clocks to the SIM. When the PLL is not selected, the high speed peripheral clock is disabled and

the 2X system clock is input clock from either internal relaxation oscillator or external clock source.

In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables

(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible

control of clocking and power utilization. The SIM’s clock enable controls can be used to disable

individual clocks when not needed. The clock rate controls enable the high speed clocking option for the

Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral

User Manual for further details.

6.5 Power-Down Modes

The 56F8013/56F8011 operates in one of five Power-Down modes, as shown in Table 6-3.

Table 6-3 Clock Operation in Power-Down Modes

Mode

Core Clocks

Peripheral Clocks

Description

Device is fully functional

Run

Core and memory

clocks disabled

Peripheral clocks

enabled

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

79

Table 6-3 Clock Operation in Power-Down Modes (Continued)

Mode

Core Clocks

Peripheral Clocks

Description

Wait

Core and memory

clocks disabled

Peripheral clocks

enabled

Core executes WAIT instruction to enter this

mode.

Typically used for power-conscious applications.

Possible recoveries from Wait mode to Run

mode are:

1. Any interrupt

2. Executing a Debug mode entry command

during the 56800E core JTAG interface

2. Any reset (POR, external, software, COP)

Stop

Master clock generation in the OCCS

remains operational, but the SIM disables

the generation of system and peripheral

clocks.

Core executes STOP instruction to enter this

mode. Possible recoveries from Stop mode to

Run mode are:

1. Interrupt from Timer channels that have been

configured to operate in Stop mode (TCx_SD)

2. Interrupt for SCI configured to operate in Stop

mode (SCI_SD)

3. Low-voltage interrupt

4. Executing a Debug mode entry command

using the 56800E core JTAG interface

5. Any reset (POR, external, software, COP)

Standby

The OCCS generates the 2X system clock The user configures the OCCS and SIM to select

at a reduced frequency (200kHz). The PLL the relaxation oscillator clock source (PRECS),

and high speed peripheral clocks are

disabled and the high-speed peripheral

option is not available. System and

peripheral clocks operate at 100kHz.

shut down the PLL (PLLPD), put the relaxation

oscillator in Standby mode (ROSB), and put the

large regulator in Standby (LRSTDBY). The part

is fully operational, but operating at a minimum

frequency and power configuration. Recovery

requires reversing the sequence used to enter

this mode (allowing for PLL lock time).

Power-Down

Master clock generation in the OCCS is

completely shut down. All system and

peripheral clocks are disabled.

The user configures the OCCS and SIM to enter

Standby mode as shown in the previous

description, followed by powering down the

oscillator (ROPD). The only possible recoveries

from this mode are:

1. External Reset

2. Power-On Reset

The power modes provide additional means to disable clock domains, configure the voltage regulator, and

configure clock generation to manage power utilization, as shown in Table 6-3. Run, Wait, and Stop

modes provide means of enabling/disabling the peripheral and/or core clocking as a group. Stop disable

controls are provided for selected peripherals in the control register so that these peripheral clocks can

optionally continue to operate in Stop mode and generate interrupts which will return the part from Stop

to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is

possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.

A 200kHz clock external clock can optionally be used in Standby mode to produce the required Standby

100kHz system bus rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully

disables the part and minimizes its power utilization but is only recoverable via reset.

When the PLL is not selected and the system bus is operating at around 100kHz, the large regulator can

be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.

56F8013/56F8011 Data Sheet, Rev. 12

80

Freescale Semiconductor

Resets

1

All peripherals, except the COP/watchdog timer, run at the system clock (peripheral bus) frequency ,

which is the same as the main processor frequency in this architecture. The COP timer runs at

MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz. The only exception is

the Quad Timer and PWM, which can be configured to operate at three times the system bus rate using

TCR and PCR controls, provided the PLL is active and selected.

6.6 Resets

The SIM supports four sources of reset, as shown in Figure 6-15. The two asynchronous sources are the

external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset,

which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, and the COP

reset. The SIM uses these to generate resets for the internal logic. These are outlined in Table 6-4. The

first column lists the four primary resets which are calculated. The JTAG circuitry is reset by the Power-On

Reset. Columns two through five indicate which reset sources trigger these reset signals. The last column

provides additional detail.

Table 6-4 Primary System Resets

Reset Sources

Reset Signal

POR

External

Software

COP

Comments

EXTENDED_POR

X

Stretched version of POR. Relevant 64

Relaxation Oscillator Clock cycles after

POR deasserts.

CLKGEN_RST

PERIP_RST

CORE_RST

X

Released 32 Relaxation Oscillator Clock

cycles after all reset sources have

released.

Releases 32 Relaxation Oscillator Clock

cycles after the CLKGEN_RST is

released.

Releases 32 SYS_CLK periods after

PERIP_RST is released.

Figure 6-15 provides a graphic illustration of the details in Table 6-4. Note that the POR_Delay blocks

use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this

phase of reset.

1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

81

EXTENDED_POR

JTAG

POR

pulse shaper

Power-On

Reset

Memory

(active

low)

Subsystem

Delay 64

MSTR_OSC

Clocks

CLKGEN_RST

OCCS

COMBINED_RST

External

RESET IN

(active

PERIP_RST

Delay 32

MSTR_OSC

Clocks

RESET

Peripherals

low)

pulse shaper

Delay 32

COP

(active

low)

sys clocks

SW Reset

56800E

pulse shaper

Delay 32

sys clocks

pulse shaper

Delay blocks assert immediately and

deassert only after the programmed

number of clock cycles.

CORE_RST

Figure 6-15 Sources of RESET Functional Diagram (Test modes not included)

POR resets are extended 64 MSTR_OSC clocks to stabilize the power supply. All resets are subsequently

extended for an additional 32 MSTR_OSC clocks and 64 system clocks as the various internal reset

controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset

from when power comes on to when code is running is 28μS. An external reset generation chip may also

be used. Resets may be asserted asynchronously, but they are always released internally on a rising edge

of the system clock.

56F8013/56F8011 Data Sheet, Rev. 12

82

Freescale Semiconductor

Clocks

6.7 Clocks

The memory, peripheral and core clocks all operate at the same frequency (32MHz max) with the

exception of the Quad Timer and PWM peripheral clocks, which have the option (using TCR and PCR) to

operate three times faster. The SIM is responsible for stalling individual clocks as a response to various

hold-off requests, low power modes, and other configuration parameters. The SIM has access to the

following signals from the OCCS module:

MSTR_OSC

This comes from the input clock source mux of the OCCS. It is the output of the

relaxation oscillator or the external clock source, depending on PRECS. It is not

guaranteed to be at 50% duty cycle (+ or - 10% can probably be assumed for design

purposes). This clock runs continuously, even during resetm and is used for reset

generation.

HS_PERF

The PLL multiplies the MSTR_OSC by 24, to a maximum of 192MHz. The ZSRC

field in OCCS selects the active source to be the PLL. This is divided by 2 and

postscaled to produce this maximum 96MHz clock. It is used without further division

to produce the high-speed (3x system bus rate) variants of the Quad Timer and PWM

peripheral clocks. This clock is disabled when ZSRC is selecting MSTR_OSC.

SYS_CLK_x2

The PLL can multiply the MSTR_OSC by 24, to a maximum of 192MHz. When the

PLL is selected by the OCCS ZSRC field, the PLL is divided by three and postscaled

to produce this maximum 64MHz clock. When MSTR_OSC is selected by the OCCS

ZSRC field, MSTR_OSC feeds SYS_CLK_x2 directly. The SIM takes this clock and

divides it by two to generate all the normal (1x system bus rate) peripheral and system

clocks.

While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks,

the ADC standby and conversion clocks are generated by a direct interface between the ADC and the

OCCS module.

Figure 6-16 illustrates clock relationships to one another and to the various resets as the device comes out

of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external

reset, COP and Software reset). In the 56F8013/56F8011 architecture, this signal will be stretched by the

SIM for a period of time (up to 96 MSTR_OSC clock cycles, depending upon the status of the POR) to

create the clock generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST

synchronously with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is

delayed 32 SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then

delayed by 32 SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be

released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is

necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E

core becoming active.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

83

Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles

for combined reset extension

RST

MSTR_OSC

Switch on falling OSC_CLK

96 MSTR_OSC cycles

CKGEN_RST

SYS_CLK_x2

SYS_CLK

SYS_CLK_D

SYS_CLK_DIV2

32 SYS_CLK cycles delay

Switch on falling SYS_CLK

PERIP_RST

CORE_RST

Switch on falling SYS_CLK

32 SYS_CLK cycles delay

Figure 6-16 Timing Relationships of Reset Signal to Clocks

6.8 Interrupts

The SIM generates no interrupts.

Part 7 Security Features

The 56F8013/56F8011 offers security features intended to prevent unauthorized users from reading the

contents of the flash memory (FM) array. The 56F8013/56F8011’s flash security consists of several

hardware interlocks that prevent unauthorized users from gaining access to the flash array.

After flash security is set, an authorized user is still able to access on-chip memory if the user purposely

includes a subroutine to read and transfer the contents of internal memory via serial communication

peripherals, as this code would defeat the purpose of security.

7.1 Operation with Security Enabled

After the user has programmed the flash with his application code, the 56F8013/56F8011 can be secured

by programming a security word ($E70A) into program memory location $00 1FF7. This nonvolatile word

will keep the device secured through reset and through power-down of the device. Refer to the flash

56F8013/56F8011 Data Sheet, Rev. 12

84

Freescale Semiconductor

Flash Access Lock and Unlock Mechanisms

memory chapter in MC56F8000RM, the 56F8000 Peripheral Reference Manual for details. When flash

security mode is enabled, the 56F8013/56F8011 will disable the core EOnCE debug capabilities. Normal

program execution is otherwise unaffected.

7.2 Flash Access Lock and Unlock Mechanisms

There are several methods that effectively lock or unlock the on-chip flash.

7.2.1

Disabling EOnCE Access

On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for

the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE

port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active

and provides the chip’s boundary scan capability and access to the ID register, but proper implementation

of flash security will block any attempt to access the internal flash memory via the EOnCE port when

security is enabled.

7.2.2

Flash Lockout Recovery Using JTAG

If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash

contents, including the configuration field, thus disabling security (the protection register is cleared). This

does not compromise security, as the entire contents of the user’s secured code stored in flash are erased

before security is disabled on the device on the next reset or power-up sequence.

To start the lockout recovery sequence via JTAG, the JTAG public instruction

(LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register.

Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock

divider value must be shifted into the corresponding 7-bit data register. After the data register has been

updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout

sequence to commence. The controller must remain in this state until the erase sequence has completed.

Refer to MC56F8000RM, the 56F8000 Peripheral Reference Manual, for more details, or contact

Freescale.

Note:

Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller

and the device to return to normal unsecured operation. Power-on reset will also reset both.

7.2.3

Flash Lockout Recovery Using CodeWarrior

CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by

Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory configuration

file. The command Unlock_Flash_on_Connect1 in the .cfg file accomplishes the same task as using the

Debug menu.

This lockout recovery mechanism also includes the complete erasure of the internal flash contents,

including the configuration field, thus disabling security (the protection register is cleared).

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

85

7.2.4

Flash Lockout Recovery Without Mass Erase

The user can un-secure a secured device by programming the word $0000 into program memory location

$00 1FF7. After completing the programming, both the JTAG TAP controller and the device must be

reset in order to return to normal unsecured operation. Power-on reset will also reset both.

The user is responsible for directing the device to invoke the flash programming subroutine to reprogram

the word $0000 into program memory location $00 1FF7. This is done by, for example, toggling a specific

pin, or by downloading a user-defined key through serial interfaces.

Note:

Flash contents can only be programmed for 1s to 0s.

7.3 Product Analysis

The recommended method of unsecuring a secured device for product analysis of field failures is via the

method suggested in Section 7.2.4. The customer would need to supply Technical Support with the details

of the protocol to access the subroutines in flash. An alternative method for performing analysis on a

secured device would be to mass-erase and reprogram the flash with the original code, but also either

modify the security word or else not program the security word.

Part 8 General Purpose Input/Output (GPIO)

8.1 Introduction

This section is intended to supplement the GPIO information found in the 56F801X Peripheral User

Manual and contains only chip-specific information. This information supercedes the generic information

in the 56F801X Peripheral User Manual.

8.2 Configuration

There are four GPIO ports defined on the 56F8013/56F8011. The width of each port, the associated

peripheral and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown

in Table 8-2.

56F8013/56F8011 Data Sheet, Rev. 12

86

Freescale Semiconductor

Configuration

Table 8-1 GPIO Ports Configuration

Available Pins in

56F8013/56F8011

GPIO Port

Peripheral Function

PWM, Reset

Reset Function

GPIO, except GPIOA7

A

B

C

8

6

SPI, SCI, Timer

GPIO

ADC (GPIOC3 and GPIOC7 are not

bonded out on the 56F8013/56F8011)

Analog

JTAG

D

4

Table 8-2 GPIO External Signals Map

Pins in shaded rows are not available in 56F8013/56F8011

LQFP

Package Pin

Notes

GPIO Function Peripheral Function

GPIOA0

GPIOA1

GPIOA2

GPIOA3

GPIOA4

PWM0

29

28

23

24

22

Defaults to A0

Defaults toA1

Defaults to A2

Defaults to A3

PWM1

PWM2

PWM3

PWM4 / FAULT1 / T2

SIM register SIM_GPS is used to select

between PWM4, FAULT1, and T2

Defaults to A4

GPIOA5

PWM5 / FAULT2 / T3

20

SIM register SIM_GPS is used to select

between PWM5, FAULT2, and T3

Defaults to A5

GPIOA6

GPIOA7

GPIOB0

FAULT0

18

15

21

Defaults to A6

RESET

Defaults to RESET

SCLK / SCL

SIM register SIM_GPS is used to select

between SCLK and SCL

Defaults to B0

GPIOB1

GPIOB2

SS / SDA

MISO / T2

2

SIM register SIM_GPS is used to select

between SS and SDA

Defaults to B1

17

SIM register SIM_GPS is used to select

between MISO and T2

Defaults to B2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

87

Table 8-2 GPIO External Signals Map (Continued)

Pins in shaded rows are not available in 56F8013/56F8011

LQFP

Package Pin

Notes

GPIO Function Peripheral Function

GPIOB3

GPIOB4

GPIOB5

GPIOB6

MOSI / T3

16

SIM register SIM_GPS is used to select

between MOSI and T3

Defaults to B3

T0 / CLKO

19

4

SIM register SIM_GPS is used to select

between T0 and CLKO

Defaults to B4

T1 / FAULT3

RXD / SDA / CLKIN

SIM register SIM_GPS is used to select

between T1 and FAULT3

Defaults to B5

1

SIM register SIM_GPS is used to select

between RXD and SDA. CLKIN

functionality is enabled using the PLL

Control Register within the OCCS block.

Defaults to B6

GPIOB7

TXD / SCL

3

SIM register SIM_GPS is used to select

between TXD and SCL

Defaults to B7

GPIOC0

GPIOC1

GPIOC2

ANA0

12

11

10

Defaults to ANA0

Defaults to ANA1

Defaults to ANA2

ANA1

ANA2 / V_REFH

GPIOC3

ANA3

Not bonded out in 56F8013/56F8011

Defaults to ANA3

GPIOC4

GPIOC5

GPIOC6

ANB0

5

6

7

Defaults to ANB0

Defaults to ANB1

Defaults to ANB2

ANB1

ANB2 / V_REFL

GPIOC7

ANB3

Not bonded out in 56F8013/56F8011

Defaults to ANB3

GPIOD0

GPIOD1

GPIOD2

GPIOD3

TDI

30

32

14

31

Defaults to TDI

Defaults to TDO

Defaults to TCK

Defaults to TMS

TDO

TCK

TMS

8.3 Reset Values

Tables 4-18 through 4-21 detail registers for the 56F8013/56F8011; Figures 8-1 through 8-4 summarize

register maps and reset values.

56F8013/56F8011 Data Sheet, Rev. 12

88

Freescale Semiconductor

Reset Values

Add.

Offset

Register Acronym

GPIOA_PUPEN

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

6

5

4

3

2

1

0

R

W

PU

D

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

RS

0

1

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

R

W

GPIOA_DATA

GPIOA_DDIR

RS

0

R

W

DD

PE

IA

RS

0

R

W

GPIOA_PEREN

GPIOA_IASSRT

GPIOA_IEN

RS

0

R

W

RS

0

R

W

IEN

RS

0

R

W

IEPOL

GPIOA_IEPOL

GPIOA_IPEND

GPIOA_IEDGE

GPIOA_PPOUTM

GPIOA_RDATA

GPIOA_DRIVE

RS

0

R

W

IPR

IES

RS

0

1

0

1

R

W

RS

0

R

W

OEN

RS

0

R

W

RAW DATA

RS

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

R

W

DRIVE

RS

0

R

W

Read as 0

Reserved

Reset

RS

Figure 8-1 GPIOA Register Map Summary

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

89

Add.

Offset

Register Acronym

GPIOB_PUPEN

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

6

5

4

3

2

1

0

R

W

PU

D

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

RS

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

X

0

1

R

W

GPIOB_DATA

GPIOB_DDIR

RS

0

1

0

1

X

0

R

W

DD

PE

IA

RS

0

R

W

GPIOB_PEREN

GPIOB_IASSRT

GPIOB_IEN

RS

0

R

W

RS

0

R

W

IEN

RS

0

R

W

IEPOL

GPIOB_IEPOL

GPIOB_IPEND

GPIOB_IEDGE

GPIOB_PPOUTM

GPIOB_RDATA

GPIOB_DRIVE

RS

0

R

W

IPR

IES

RS

0

1

0

1

R

W

RS

0

R

W

OEN

RS

0

R

W

RAW DATA

RS

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

R

W

DRIVE

RS

0

R

W

Read as 0

Reserved

Reset

RS

Figure 8-2 GPIOB Register Map Summary

56F8013/56F8011 Data Sheet, Rev. 12

90

Freescale Semiconductor

Reset Values

Add.

Offset

Register Acronym

GPIOC_PUPEN

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

6

5

4

3

2

1

0

R

W

PU

D

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

RS

0

1

0

1

0

1

X

0

1

0

1

0

1

X

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

X

0

1

0

1

0

1

X

0

R

W

GPIOC_DATA

GPIOC_DDIR

RS

0

R

W

DD

PE

IA

RS

0

R

W

GPIOC_PEREN

GPIOC_IASSRT

GPIOC_IEN

RS

0

R

W

RS

0

R

W

IEN

RS

0

R

W

IEPOL

GPIOC_IEPOL

GPIOC_IPEND

GPIOC_IEDGE

GPIOC_PPOUTM

GPIOC_RDATA

GPIOC_DRIVE

RS

0

R

W

IPR

IES

RS

0

1

0

1

R

W

RS

0

R

W

OEN

RS

0

R

W

RAW DATA

RS

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

R

W

DRIVE

RS

0

R

W

Read as 0

Reserved

Reset

RS

Figure 8-3 GPIOC Register Map Summary

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

91

Add.

Offset

Register Acronym

GPIOD_PUPEN

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

1

0

R

W

PU

D

$0

$1

$2

$3

$4

$5

RS

0

1

R

W

GPIOD_DATA

GPIOD_DDIR

GPIOD_PEREN

GPIOD_IASSRT

GPIOD_IEN

RS

0

1

0

1

0

1

0

1

0

R

W

DD

PE

RS

0

R

W

RS

0

R

W

IA

RS

0

R

W

IEN

RS

0

R

W

IEPOL

$6

GPIOD_IEPOL

RS

0

1

X

0

1

X

0

R

W

IPR

IES

$7

$8

$9

$A

$B

GPIOD_IPEND

GPIOD_IEDGE

GPIOD_PPOUTM

GPIOD_RDATA

GPIOD_DRIVE

RS

0

1

0

1

R

W

RS

0

R

W

OEN

RS

0

R

W

RAW DATA

RS

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

R

W

DRIVE

RS

0

R

W

Read as 0

Reserved

Reset

RS

56F8013/56F8011 Data Sheet, Rev. 12

92

Freescale Semiconductor

56F8013/56F8011 Information

Figure 8-4 GPIOD Register Map Summary

Part 9 Joint Test Action Group (JTAG)

9.1 56F8013/56F8011 Information

Please contact your Freescale sales representative or authorized distributor for device/package-specific

BSDL information.

The TRST pin is not available in this package. The pin is tied to V in the package.

DD

The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high

for five rising edges of TCK, as described in the 56F801X Peripheral User Manual.

Part 10 Specifications

10.1 General Characteristics

The 56F8013/56F8011 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital

inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process

technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture

of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and

5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the

power savings of 3.3V I/O levels, combined with the ability to receive 5V levels without damage.

Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum

is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to

the device.

Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to

125ºC ambient temperature over the following supply ranges:

V

= V

= 0V, V = V

= 3.0–3.6V, CL < 50pF, f = 32MHz

SS

SSA

DD

DDA OP

Note: The 56F8011 device is specified to meet Industrial requirements only.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

93

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

Table 10-1 Absolute Maximum Ratings

(V_SS= 0V, V_SSA= 0V)

Characteristic

Supply Voltage Range

Symbol

V_DD

Notes

Min

-0.3

- 0.3

-

Max

4.0

0.3

6.0

4.0

-20

Unit

V

Analog Supply Voltage Range

ADC High Voltage Reference

Voltage difference V_DDto V_DDA

Voltage difference V_SSto V_SSA

Input Voltage Range (Digital inputs)

V_DDA

V_REFH

ΔV_DD

ΔV_SS

V_IN

V

Pin Groups 1, 2

Pin Group 3

V

Input Voltage Range (ADC inputs)¹

Input clamp current, per pin (V_IN< 0)²

V_INA

V

V_IC

mA

Output clamp current, per pin (V_O< 0)²

V_OC

-

-20

4.0

mA

V

Output Voltage Range

Pin Group 1

V_OUT

-0.3

(Normal Push-Pull mode)

Output Voltage Range

(Open Drain mode)

Pin Groups 1, 2

V_OUTOD

-0.3

6.0

V

Ambient Temperature (Automotive)

Ambient Temperature (Industrial)

Junction Temperature (Automotive)

Junction Temperature (Industrial)

Storage Temperature (Automotive)

Storage Temperature (Industrial)

T_A

-40

-55

125

105

150

125

150

°C

T_J

T_STG

1. Pin Group 3 can tolerate 6V for less than 5 seconds when they are configured as ADC inputs or during reset. Pin Group 3 can

tolerate 6V if they are configured as GPIO.

2. Continuous input current per pin is -2 mA

56F8013/56F8011 Data Sheet, Rev. 12

94

Freescale Semiconductor

General Characteristics

Default Mode

Pin Group 1: GPIO, TDI, TDO, TMS, TCK

Pin Group 2: RESET, GPIOA7

Pin Group 3: ADC Analog Inputs

10.1.1 ElectroStatic Discharge (ESD) Model

Table 10-2 56F8013/56F8011 ESD Protection

Characteristic

Min

Typ

Max

Unit

ESD for Human Body Model (HBM)

ESD for Machine Model (MM)

2000

200

—

V

ESD for Charge Device Model (CDM)

750

6

Table 10-3 LQFP Package Thermal Characteristics

Value

(LQFP)

Characteristic

Comments

Symbol

Unit

Notes

Junction to ambient

Natural convection

Single layer board

(1s)

R_θJA

74

50

°C/W

1,2

1,3

Junction to ambient

Natural convection

Four layer board

(2s2p)

R_θJMA

Junction to ambient

(@200 ft/min)

Single layer board

(1s)

R_θJMA

67

46

°C/W

1,3

Junction to ambient

(@200 ft/min)

Four layer board

(2s2p)

R_θJMA

Junction to board

R_θJB

R_θJC

Ψ_JT

23

20

4

°C/W

4

5

6

Junction to case

Junction to package top

Natural Convection

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESC51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the

top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per

JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

7. See Section 12.1 for more details on thermal design considerations.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

95

Table 10-4 Recommended Operating Conditions

(V

= 0V, V

= 0V, V = 0V )

REFL

SSA

SS

Characteristic

Supply voltage

Symbol

V_DD

Notes

Min

3

Typ

3.3

—

0

Max

3.6

Unit

V

ADC Supply voltage

V_DDA

3

3.6

V

ADC High Voltage Reference

Voltage difference V_DDto V_DDA

Voltage difference V_SSto V_SSA

V_REFH

ΔV_DD

3

V_DDA

0.1

V

-0.1

V

ΔV_SS

0

0.1

V

Device Clock Frequency

Using relaxation oscillator

Using external clock source

FSYSCLK

—

MHz

8

0

32

Input Voltage High (digital inputs)

Input Voltage Low (digital inputs)

Output Source Current High (at V_OHmin.)

V_IH

V_IL

I_OH

Pin Groups 1, 2

2

—

5.5

0.8

V

-0.3

mA

Pin Group 1

—

-4

-8

When programmed for low drive strength

When programmed for high drive strength

Output Source Current Low (at V_OLmax.)

I_OL

mA

°C

Pin Groups 1, 2

—

4

8

When programmed for low drive strength

When programmed for high drive strength

Ambient Operating Temperature

(Automotive)

125

T

-40

—

A

Ambient Operating Temperature (Industrial)

105

—

°C

T

-40

—

A

Flash Endurance

(Program Erase Cycles)

N_F

T_A= -40°C to

105°C

10,000

Cycles

Flash Data Retention

T_R

T_J<= 85°C avg

15

20

—

Years

Flash Data Retention with <100

Program/Erase Cycles

t_FLRET

Note: Total chip source or sink current cannot exceed 50mA

Default Mode

Pin Group 1: GPIO, TDI, TDO, TMS, TCK

Pin Group 2: RESET, GPIOA7

Pin Group 3: ADC analog inputs

56F8013/56F8011 Data Sheet, Rev. 12

96

Freescale Semiconductor

DC Electrical Characteristics

10.2 DC Electrical Characteristics

Table 10-5 DC Electrical Characteristics

At Recommended Operating Conditions

Test

Unit

Characteristic

Output Voltage High

Symbol

Notes

Min

Typ

Max

Conditions

V_OH

V_OL

I_IH

Pin Group 1

Pin Groups 1, 2

2.4

—

0

—

0.4

V

I_OH= I_OHmax

I_OL= I_OLmax

Output Voltage Low

Digital Input Current High

pull-up enabled or disabled¹

—

+/- 2.5

μA

V_IN= 2.4V to

5.5V

Digital Input Current Low

pull-up enabled

pull-up disabled¹

I_IL

Pin Groups 1, 2

μA

V_IN= 0V

-15

—

-30

0

-60

+/- 2.5

Output Current

High Impedance State¹

I_OZ

Pin Groups 1, 2

—

0

+/- 2.5

V_OUT= 2.4V to

5.5V or 0V

Schmitt Trigger Input Hysteresis

Input Capacitance

V_HYS

C_IN

—

0.35

10

—

V

—

pF

Output Capacitance

C_OUT

10

1. See Figure 10-1

Default Mode

Pin Group 1: GPIO, TDI, TDO, TMS, TCK

Pin Group 2: RESET, GPIOA7

Pin Group 3: ADC Analog Inputs

2.0

0.0

- 2.0

- 4.0

- 6.0

- 8.0

- 10.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Volt

Figure 10-1 I /I vs. V (Typical; Pull-Up Disabled)

IN OZ

IN

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

97

Table 10-6 Current Consumption per Power Supply Pin (Typical)

Typical @ 3.3V, 25°C

Maximum@ 3.6V, 25°C

Mode

Conditions

1

I_DDA

I_DD

RUN

32MHz Device Clock

42mA

13.5mA

—

Relaxation Oscillator on

PLL powered on

Continuous MAC instructions with fetches from

Program Flash

All peripheral modules enabled. Quad Timer and

PWM using 1x Clock

ADC powered on and clocked

WAIT

STOP

32MHz Device Clock

Relaxation Oscillator on

PLL powered on

Processor Core in WAIT state

All Peripheral modules enabled. Quad Timer and

PWM using 1x Clock

17mA

0μA

—

ADC powered off

4MHz Device Clock

Relaxation Oscillator on

PLL powered off

Processor Core in STOP state

All peripheral module and core clocks are off

ADC powered off

5mA

0μA

—

STANDBY > 100KHz Device Clock

STOP

430μA

550μA

400μA

1μA

Relaxation Oscillator in Standby mode

PLL powered off

Processor Core in STOP state

All peripheral module and core clocks are off

ADC powered off

Voltage regulator in Standby mode

POWER-

DOWN

Device Clock is off

Relaxation Oscillator powered off

PLL powered off

300μA

0μA

1μA

Processor Core in STOP state

All peripheral module and core clocks are off

ADC powered off

Voltage Regulator in Standby mode

1. No Output Switching

All ports configured as inputs

All inputs Low

No DC Loads

56F8013/56F8011 Data Sheet, Rev. 12

98

Freescale Semiconductor

AC Electrical Characteristics

Table 10-7 Power-On Reset Low-Voltage Parameters

Typ

2.7

Max

—

Unit

V

Min

2.58

—

Characteristic

Symbol

V_EI3.3

V_E12.5

V_EIH

Low-Voltage Interrupt for 3.3V supply¹

Low-Voltage Interrupt for 2.5V supply²

2.15

50

—

V

Low-Voltage Interrupt Recovery Hysteresis

—

mV

V

Power-On Reset³

POR

—

1.8

1.9

1. When V drops below V

, an interrupt is generated.

DD

EI3.3

2. When V drops below V

, an interrupt is generated.

DD

EI32.5

3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While

power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V

1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is

typically 100mV less than V during ramp-up until 2.5V is reached, at which time it self-regulates.

DD

10.2.1 Voltage Regulator Specifications

The 56F8013/56F8011 have two on-chip regulators. One supplies the PLL and relaxation oscillator. It has

no external pins and therefore has no external characteristics which must be guaranteed (other than proper

operation of the device). The second regulator supplies approximately 2.5V to the 56F8013/56F8011’s

core logic. This regulator requires an external 2.2μF, or greater, capacitor for proper operation. Ceramic

and tantalum capacitors tend to provide better performance tolerances. The output voltage can be

measured directly on the V

pin. The specifications for this regulator are shown in Table 10-8.

CAP

Table 10-8. Regulator Parameters

Characteristic

Short Circuit Current

Symbol

I_SS

Min

—

Typical

450

Max

650

30

Unit

mA

Short Circuit Tolerance

T_RSC

—

Minutes

(output shorted to ground)

10.3 AC Electrical Characteristics

Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,

propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured

between the 10% and 90% points, as shown in Figure 10-2.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

99

Low

V_IL

High

V_IH

90%

50%

10%

Input Signal

Midpoint1

Fall Time

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Rise Time

Figure 10-2 Input Signal Measurement References

Figure 10-3 shows the definitions of the following signal states:

•

Active state, when a bus or signal is driven, and enters a low impedance state

Tri-stated, when a bus or signal is placed in a high impedance state

Data Valid state, when a signal level has reached V_OLor V_OH

•

Data Invalid state, when a signal level is in transition between V_OLand V_OH

Data2 Valid

Data2

Data1 Valid

Data1

Data3 Valid

Data3

Data

Tri-stated

Data Invalid State

Data Active

Figure 10-3 Signal States

10.4 Flash Memory Characteristics

Table 10-9 Flash Timing Parameters

Characteristic

Symbol

Tprog

Terase

Tme

Min

20

Typ

—

Max

40

Unit

μs

Program time¹

Erase time ²

20

—

ms

Mass erase time

100

—

1. There is additional overhead which is part of the programming sequence. See the 56F801X Peripheral User Manual

for details.

2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory.

56F8013/56F8011 Data Sheet, Rev. 12

100

Freescale Semiconductor

External Clock Operation Timing

10.5 External Clock Operation Timing

1

Table 10-10 External Clock Operation Timing Requirements

Characteristic

Symbol

f_osc

Min

4

Typ

8

Max

8

Unit

MHz

ns

Frequency of operation (external clock driver)²

Clock Pulse Width³

t_PW

6.25

—

3

External Clock Input Rise Time⁴

t_rise

ns

External Clock Input Fall Time⁵

t_fall

—

3

ns

1. Parameters listed are guaranteed by design.

2. See Figure 10-4 for details on using the recommended connection of an external clock driver.

3. The high or low pulse width must be no smaller than 6.25ns or the chip may not function.

4. External clock input rise time is measured from 10% to 90%.

5. External clock input fall time is measured from 90% to 10%.

V_IH

External

Clock

90%

50%

10%

90%

50%

10%

V_IL

t_fall

t_rise

t_PW

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Figure 10-4 External Clock Timing

10.6 Phase Locked Loop Timing

Table 10-11 PLL Timing

Characteristic

Symbol

Min

Typ

Max

Unit

Internal reference relaxation oscillator frequency for

the PLL

f_rosc

—

8

—

MHz

PLL output frequency¹(24 x reference frequency)

f_op

t_lock

—

192

40

—

MHz

µs

PLL lock time²

100

Cycle-to-cycle jitter

t_jitterpll

350

ps

1. The core system clock will operate at 1/6 of the PLL output frequency.

2. This is the time required after the PLL is enabled to ensure reliable operation.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

101

10.7 Relaxation Oscillator Timing

Table 10-12 Relaxation Oscillator Timing

Characteristic

Symbol

Minimum

Typical

Maximum

Unit

Relaxation Oscillator output frequency

f_op

—

Normal Mode¹

Standby Mode

8.05

200

MHz

kHz

Relaxation Oscillator stabilization time²

t_roscs

—

1

3

µs

ps

Cycle-to-cycle jitter. This is measured on the

CLKO signal (programmed prescaler_clock)

t_jitterrosc

400

over 264 clocks³

Minimum tuning step size

Maximum tuning step size

.08

40

%

Variation over temperature –40°C to 150°C⁴

Variation over temperature 0°C to 105°C⁴

+1.0 to –1.5 +3.0 to –3.0

0 to +1 +2.0 to –2.0

+1.0 to -1.5 +3.0 to –4.5

%

Variation over temperature –40°C to 150°C⁴

(MC56F8013MFAE)

1. Output frequency after factory trim.

2. This is the time required from standby to normal mode transition.

3. J is required to meet SCI requirements.

A

4. See Figure 10-5.

56F8013/56F8011 Data Sheet, Rev. 12

102

Freescale Semiconductor

Reset, Stop, Wait, Mode Select, and Interrupt Timing

8.16

8.08

8

7.92

7.84

-50

-25

0

25

50

75

100

125

150

175

Degrees C (Junction)

Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Factory Trim

10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Note: All the address and data buses described here are internal.

1,2

Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Characteristic

Symbol

t_RA

Typical Min

Typical Max

Unit

ns

See Figure

10-6

Minimum RESET Assertion Duration

Minimum GPIO pin Assertion for Interrupt

4T

—

t_IW

2T

96T_OSC+ 64T

—

97T_OSC+ 65T

6T

ns

RESET deassertion to First Address Fetch³

t_RDA

t_IF

ns

Delay from Interrupt Assertion to Fetch of first

instruction (exiting Stop)

ns

1. In the formulas, T = clock cycle and T

= oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At 8MHz

osc

(used during Reset and Stop modes), T = 125ns.

2. Parameters listed are guaranteed by design.

3. During Power-On Reset, it is possible to use the 56F8013/56F8011 internal reset stretching circuitry to extend this period to

2^21T.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

103

GPIO pin

(Input)

T_IW

Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)

56F8013/56F8011 Data Sheet, Rev. 12

104

Freescale Semiconductor

Serial Peripheral Interface (SPI) Timing

10.9 Serial Peripheral Interface (SPI) Timing

1

Table 10-14 SPI Timing

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

Master

Slave

t_C

10-7, 10-8,

10-9, 10-10

125

62.5

—

ns

Enable lead time

Master

Slave

t_ELD

t_ELG

t_CH

t_CL

10-10

—

31

—

ns

Enable lag time

Master

Slave

—

125

—

ns

Clock (SCK) high time

Master

Slave

10-7, 10-8,

10-9, 10-10

50

31

—

ns

Clock (SCK) low time

Master

Slave

10-10

50

31

—

ns

Data set-up time required for inputs

Master

Slave

t_DS

t_DH

t_A

10-7, 10-8,

10-9, 10-10

20

0

—

ns

Data hold time required for inputs

Master

Slave

10-7, 10-8,

10-9, 10-10

0

2

—

ns

Access time (time to data active from

high-impedance state)

Slave

10-10

4.8

3.7

15

ns

Disable time (hold time to high-impedance state)

Slave

t_D

15.2

Data Valid for outputs

Master

Slave (after enable edge)

t_DV

10-7, 10-8,

10-9, 10-10

—

4.5

20.4

ns

Data invalid

Master

Slave

t_DI

t_R

t_F

10-7, 10-8,

10-9, 10-10

0

—

ns

Rise time

Master

Slave

10-7, 10-8,

10-9, 10-10

—

11.5

10.0

ns

Fall time

Master

Slave

10-7, 10-8,

10-9, 10-10

—

9.7

9.0

ns

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

105

1. Parameters listed are guaranteed by design.

1

SS

(Input)

SS is held High on master

t_C

t_R

t_F

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_F

t_R

t_CL

SCLK (CPOL = 1)

(Output)

t_DH

t_CH

t_DS

MISO

MSB in

t_DI

Bits 14–1

LSB in

t_DI(ref)

(Input)

t_DV

Bits 14–1

MOSI

(Output)

Master MSB out

t_F

Master LSB out

t_R

Figure 10-7 SPI Master Timing (CPHA = 0)

56F8013/56F8011 Data Sheet, Rev. 12

106

Freescale Semiconductor

Serial Peripheral Interface (SPI) Timing

SS

(Input)

SS is held High on master

t_F

t_C

t_R

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_F

t_CL

SCLK (CPOL = 1)

(Output)

t_CH

t_DS

t_R

t_DH

MISO

MSB in

t_DI

Bits 14–1

LSB in

t_DI(ref)

(Input)

t_DV(ref)

t_DV

Bits 14– 1

MOSI

(Output)

Master MSB out

t_F

Master LSB out

t_R

Figure 10-8 SPI Master Timing (CPHA = 1)

SS

(Input)

t_C

t_F

t_ELG

t_CL

t_R

SCLK (CPOL = 0)

(Input)

t_CH

t_ELD

t_CL

SCLK (CPOL = 1)

(Input)

t_CH

t_F

t_A

t_R

t_D

MISO

(Output)

Slave MSB out

Bits 14–1

t_DV

Slave LSB out

t_DS

t_DI

t_DH

MOSI

(Input)

MSB in

Bits 14–1

LSB in

Figure 10-9 SPI Slave Timing (CPHA = 0)

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

107

SS

(Input)

t_F

t_C

t_R

t_CL

SCLK (CPOL = 0)

(Input)

t_CH

t_ELG

t_ELD

t_CL

SCLK (CPOL = 1)

(Input)

t_DV

t_CH

t_R

t_D

t_A

t_F

MISO

Slave MSB out

MSB in

Bits 14–1

t_DV

Slave LSB out

(Output)

t_DS

t_DI

t_DH

MOSI

(Input)

Bits 14–1

LSB in

Figure 10-10 SPI Slave Timing (CPHA = 1)

10.10 Quad Timer Timing

1, 2

Table 10-15 Timer Timing

Characteristic

Timer input period

Symbol

P_IN

Min

2T + 6

1T + 3

125

Max

—

Unit

ns

See Figure

10-11

Timer input high / low period

Timer output period

P_INHL

P_OUT

—

ns

10-11

—

ns

10-11

Timer output high / low period

P_OUTHL

50

—

ns

10-11

1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns.

2. Parameters listed are guaranteed by design.

56F8013/56F8011 Data Sheet, Rev. 12

108

Freescale Semiconductor

Quad Timer Timing

Timer Inputs

P_INHL

P_IN

Timer Outputs

P_OUTHL

P_OUT

Figure 10-11 Timer Timing

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

109

10.11 Serial Communication Interface (SCI) Timing

1

Table 10-16 SCI Timing

Characteristic

Symbol

Min

—

Max

Unit

See Figure

—

Baud Rate²

BR

(f_MAX/16)

Mbps

RXD³Pulse Width

TXD⁴Pulse Width

RXD_PW

TXD_PW

0.965/BR

1.04/BR

ns

10-12

0.965/BR

10-13

LIN Slave Mode

Deviation of slave node clock from

nominal clock rate before

synchronization

F_{TOL_UNSYNCH}

F_{TOL_SYNCH}

T_BREAK

-14

-2

14

2

%

Deviation of slave node clock relative

to the master node clock after

synchronization

Minimum break character length

13

11

Master

node bit

periods

Slavenode

bit periods

1. Parameters listed are guaranteed by design.

2. f is the frequency of operation of the system clock in MHz, which is 32MHz for the 56F8013/56F8011 devices.

MAX

3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

RXD

Receive

data pin

RXD_PW

(Input)

Figure 10-12 RXD Pulse Width

TXD

Receive

data pin

TXD_PW

(Input)

Figure 10-13 TXD Pulse Width

56F8013/56F8011 Data Sheet, Rev. 12

110

Freescale Semiconductor

Inter-Integrated Circuit Interface (I2C) Timing

2

10.12 Inter-Integrated Circuit Interface (I C) Timing

2

Table 10-17 I C Timing

Standard Mode

Minimum Maximum

Fast Mode

Characteristic

Symbol

Unit

Minimum

Maximum

SCL Clock Frequency

f_SCL

0

100

0

400

kHz

Hold time (repeated )

START condition. After

this period, the first clock

pulse is generated.

t_{HD; STA}

4.0

0.6

μs

LOW period of the SCL

clock

t_LOW

4.7

4.0

4.7

1.25

0.6

μs

HIGH period of the SCL

clock

t_HIGH

Set-up time for a repeated

START condition

t_{SU; STA}

0.6

Data hold time for I²C bus

devices

0¹

3.45²

0¹

0.9²

t_{HD; DAT}

100³

Data set-up time

t_{SU; DAT}

t_r

250

ns

4

Rise time of both SDA and

SCL signals

1000

300

2 +0.1C_b

Fall time of both SDA and

SCL signals

t_f

ns

μs

2 +0.1C_b

0.6

Set-up time for STOP

condition

t_{SU; STO}

4.0

4.7

Bus free time between

STOP and START

condition

t_BUF

1.3

0.0

Pulse width of spikes that

must be suppressed by

the input filter

t_SP

N/A

50

ns

1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V min of the SCL

IH

signal) to bridge the undefined region of the falling edge of SCL.

2. The maximum t

has only to be met if the device does not stretch the LOW period (t

) of the SCL signal.

HD; DAT

LOW

2

3. A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement t

> = 250ns

SU; DAT

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.

If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

2

t

+ t

= 1000 + 250 = 1250ns (according to the Standard mode I C bus specification) before the SCL line is

rmax

SU; DAT

released.

4. C = total capacitance of the one bus line in pF.

b

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

111

SDA

SCL

t

SU; DAT

t

SP

t

BUF

HD; STA

LOW

t

SU; STA

HD; STA

SU; STO

S

BR

P

S

t

HIGH

HD; DAT

2

Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I C Bus

10.13 JTAG Timing

Table 10-18 JTAG Timing

Characteristic

Symbol

Min

DC

50

5

Max

Unit

MHz

ns

See Figure

10-15

TCK frequency of operation¹

TCK clock pulse width

f_OP

SYS_CLK/8

t_PW

t_DS

t_DH

t_DV

t_TS

—

30

10-15

TMS, TDI data set-up time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

ns

10-16

5

ns

10-16

—

ns

10-16

ns

10-16

1. TCK frequency of operation must be less than 1/8 the processor rate.

1/f_OP

t_PW

V_IH

V_M

TCK

(Input)

V_IL

V_M= V_IL+ (V_IH– V_IL)/2

Figure 10-15 Test Clock Input Timing Diagram

56F8013/56F8011 Data Sheet, Rev. 12

112

Freescale Semiconductor

JTAG Timing

TCK

(Input)

t_DS

t_DH

TDI

TMS

Input Data Valid

(Input)

t_DV

TDO

(Output)

Output Data Valid

t_TS

TDO

(Output)

Figure 10-16 Test Access Port Timing Diagram

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

113

10.14 Analog-to-Digital Converter (ADC) Parameters

1

Table 10-19 ADC Parameters

Parameter

DC Specifications

Symbol

Min

Typ

Max

Unit

Resolution

R_ES

f_ADIC

R_AD

12

0.1

—

6

12

5.33

V_REFH

13

Bits

MHz

V

ADC internal clock

Conversion range

V_REFL

—

ADC power-up time²

t_AICcycles³

t_ADPU

Recovery from auto standby

t_REC

t_ADC

t_ADS

—

0

6

1

Conversion time

Sample time

Accuracy

—

Integral non-linearity⁴

(Full input signal range)

LSB⁵

INL

—

+/- 3

+/- 5

+/- 1

Differential non-linearity

DNL

+/- .6

Monotonicity

GUARANTEED

+/- 4

Offset Voltage Internal Ref

V_OFFSET

E_GAIN

—

+/- 9

+/- 12

mV

—

Offset Voltage External Ref

Gain Error (transfer gain)

+/- 6

.998 to 1.002

1.01 to .99

ADC Inputs⁶(Pin Group 3)

Input voltage (external reference)

V_ADIN

I_IA

V_REFL

V_SSA

—

V_REFH

V_DDA

+/- 2

—

V

Input voltage (internal reference)

—

Input leakage⁷

V_REFHcurrent

0

μA

I_VREFH

I_ADI

—

0

μA

Input injection current⁸, per pin

Input capacitance

—

3

mA

pF

C_ADI

X_IN

—

See Figure 10-17

—

Input impedance

—

Ohms

AC Specifications

Signal-to-noise ratio

SNR

THD

60

61

58

—

65

64

66

62

dB

Total Harmonic Distortion

Spurious Free Dynamic Range

Signal-to-noise plus distortion

Effective Number Of Bits

SFDR

SINAD

ENOB

dB

10.0

Bits

1. All measurements were made at V = 3.3V, V

= 3.3V, and V = ground

REFL

DD

REFH

2. Includes power-up of ADC and V

3. ADC clock cycles

REF

4. INL measured from V = V

to V = V

IN REFH

IN

REFL

56F8013/56F8011 Data Sheet, Rev. 12

114

Freescale Semiconductor

Equivalent Circuit for ADC Inputs

5. LSB = Least Significant Bit = 0.806mV

6. Pin groups are detailed following Table 10-1.

7. For device S56F8013MFA00E, input leakage current is ± 1μA.

8. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the

ADC.

10.15 Equivalent Circuit for ADC Inputs

Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed

at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and

hold circuit moves to (V

-V

)/2, while the other charges to the analog input voltage. When the

REFH REFL

switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended

analog input is switched to a differential voltage centered about (V -V )/2. The switches switch

REFH REFL

on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there

are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into

the S/H output voltage, as S1 provides isolation during the charge-sharing phase.

One aspect of this circuit is that there is an on-going input current, which is a function of the analog input

voltage, V

and the ADC clock frequency.

REF

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

115

C1

: Singled Ended Mode

2 X C1 : Differential Mode

Equivalent Circuit for A/D Loading

S1

channel mux

equiv resistance

100 Ohms

ADC Input

125 Ohm

ESD Resistor

S1

C1

S/H

(V_REFHx- V_REFLx) / 2

1

2

3

S1

1.

2.

Parasitic capacitance due to package, pin-to-pin and pin-to-package

base coupling; 1.8pF

Parasitic capacitance due to the chip bond pad, ESD protection devices

and signal routing; 2.04pF

8 pF noise damping capacitor

C1 = 1.4 pF

S2

C1

: Singled Ended Mode

2 X C1 : Differential Mode

3.

4.

5.

S1 and S2 switch phases are non-overlapping and operate at the ADC

clock frequency

S1

S2

1

6. Equivalent input impedance, when the input is selected =

+100ohm+125ohm

( ADC Clock Rate)×1.4×10⁻¹²

Figure 10-17 Equivalent Circuit for A/D Loading

10.16 Power Consumption

See Section 10.1 for a list of IDD requirements for the 56F8013/56F8011. This section provides additional

detail which can be used to optimize power consumption for a given application.

Power consumption is given by the following equation:

Total power = A: internal [static component]

+B: internal [state-dependent component]

+C: internal [dynamic component]

+D: external [dynamic component]

+E: external [static]

A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,

Please see http://www.freescale.com for the most current mechanical drawing.

PLL, and voltage references. These sources operate independently of processor state or operating

56F8013/56F8011 Data Sheet, Rev. 12

116

Freescale Semiconductor

Power Consumption

frequency.

B, the internal [state-dependent component], reflects the supply current required by certain on-chip

resources only when those resources are in use. These include RAM, Flash memory and the ADCs.

2

C, the internal [dynamic component], is classic C*V *F CMOS power dissipation corresponding to the

56800E core and standard cell logic.

D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading

2

on the external pins of the chip. This is also commonly described as C*V *F, although simulations on two

of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero

Y-intercept.

Table 10-20 I/O Loading Coefficients at 10MHz

Intercept

Slope

8mA drive

4mA drive

1.3

0.11mW / pF

1.15mW

Power due to capacitive loading on output pins is (first order) a function of the capacitive load and

frequency at which the outputs change. Table 10-20 provides coefficients for calculating power dissipated

in the I/O cells as a function of capacitive load. In these cases:

TotalPower = Σ((Intercept + Slope*Cload)*frequency/10MHz)

where:

•

Summation is performed over all output pins with capacitive loads

TotalPower is expressed in mW

Cload is expressed in pF

Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found

to be fairly low when averaged over a period of time.

E, the external [static component], reflects the effects of placing resistive loads on the outputs of the

2

device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V = 0.5

for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving

10mA into LEDs, then P = 8*.5*.01 = 40mW.

In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,

as it is assumed to be negligible.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

117

Part 11 Packaging

11.1 56F8013/56F8011 Package and Pin-Out Information

This section contains package and pin-out information for the 56F8013/56F8011. These devices come in

a 32-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the 32-pin

LQFP, Figure 11-2 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out

for the 32-pin LQFP.

ORIENTATION

MARK

GPIOA3/PWM3

GPIOB6/RXD/SDA/CLKIN

GPIOB1/SS/SDA

PIN 25

GPIOA2/PWM2

PIN 1

GPIOB7/TXD/SCL

GPIOA4/PWM4/FAULT1/T2

GPIOB0/SCLK/SCL

GPIOB5/T1/FAULT3

ANB0/GPIOC4

ANB1/GPIOC5

GPIOA5/PWM5/FAULT2/T3

GPIOB4/T0/CLKO

ANB2/V_REFL/GPIOC6

GPIOA6/FAULT0

GPIOB2/MISO/T2

PIN 17

PIN 9

V_DDA

Note: Alternate signals are in italic

Figure 11-1 Top View, 56F8013/56F8011 32-Pin LQFP Package

56F8013/56F8011 Data Sheet, Rev. 12

118

Freescale Semiconductor

56F8013/56F8011 Package and Pin-Out Information

1

Table 11-1 56F8013/56F8011 32-Pin LQFP Package Identification by Pin Number

No.

Signal Name

V_SSA

Signal Name

V_CAP

1

2

GPIOB6

RXD,SDA,CLKIN

9

17

18

GPIOB2

MISO,T2

25

26

GPIOB1

10

ANA2

GPIOA6

V_DD

SS,SDA

V_REFH,GPIOC2

FAULT0

3

4

5

6

7

GPIOB7

TXD,SCL

11

12

13

14

15

ANA1

GPIOC1

19

20

21

22

23

GPIOB4

T0,CLKO

27

28

30

31

V_SS

GPIOB5

T1,FAULT3

ANA0

GPIOC0

GPIOA5

PWM5,FAULT2,T3

GPIOA1

PWM1

ANB0

GPIOC4

V_SS

GPIOB0

SCLK,SCL

GPIOA0

PWM0

ANB1

GPIOC5

TCK

GPIOD2

GPIOA4

PWM4,FAULT1,T2

TDI

GPIOD0

ANB2

RESET

GPIOA2

TMS

V_REFL,GPIOC6

GPIOA7

PWM2

GPIOD3

8

V_DDA

16

GPIOB3

24

GPIOA3

32

TDO

MOSI,T3

PWM3

GPIOD1

1.Alternate signals are in iltalic

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

119

4X

A

A1

0.20 (0.008) AB T–U

Z

32

25

1

–U–

V

–T–

B

AE

P

B1

DETAIL Y

–Z–

V1

17

8

DETAIL Y

9

4X

0.20 (0.008) AC T–U

Z

9

NOTES:

S1

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

S

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –AB– IS LOCATED AT BOTTOM

OF LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED

AT DATUM PLANE –AB–.

DETAIL AD

G

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –AC–.

–AB–

–AC–

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –AB–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

SEATING

PLANE

0.10 (0.004) AC

BASE

METAL

N

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

F

D

^8XM

MILLIMETERS

MIN MAX

7.000 BSC

3.500 BSC

7.000 BSC

3.500 BSC

INCHES

MIN MAX

0.276 BSC

0.138 BSC

0.276 BSC

0.138 BSC

R

J

DIM

A

A1

B

B1

C

D

E

F

G

H

J

SECTION AE–AE

E

C

1.400

1.600

0.450

1.450

0.400

0.055

0.063

0.018

0.057

0.016

0.300

1.350

0.300

0.012

0.053

0.012

W

0.800 BSC

0.031 BSC

Q

H

K

X

0.050

0.090

0.500

0.150

0.200

0.700

0.002

0.004

0.020

0.006

0.008

0.028

K

M

N

P

12 REF

DETAIL AD

0.090

0.160

0.004

0.006

0.400 BSC

0.016 BSC

Q

R

1

5

1

5

0.150

0.250

0.006

0.010

S

9.000 BSC

0.354 BSC

S1

V

V1

W

X

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

0.177 BSC

0.354 BSC

0.177 BSC

0.008 REF

0.039 REF

Figure 11-2 56F8013/56F8011 32-Pin LQFP Mechanical Information

56F8013/56F8011 Data Sheet, Rev. 12

120

Freescale Semiconductor

Thermal Design Considerations

Part 12 Design Considerations

12.1 Thermal Design Considerations

An estimation of the chip junction temperature, T , can be obtained from the equation:

J

T = T + (R

x P )

D

J

A

θJΑ

where:

o

T

R

= Ambient temperature for the package ( C)

A

o

= Junction-to-ambient thermal resistance ( C/W)

θJΑ

P

= Power dissipation in the package (W)

D

The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy

estimation of thermal performance. Unfortunately, there are two values in common usage: the value

determined on a single-layer board and the value obtained on a board with two planes. For packages such

as the PBGA, these values can be different by a factor of two. Which value is closer to the application

depends on the power dissipated by other components on the board. The value obtained on a single layer

board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the

internal planes is usually appropriate if the board has low-power dissipation and the components are well

separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance:

R

= R

+ R

θJA

θJC θCA

where:

R

= Package junction-to-ambient thermal resistance (°C/W)

= Package junction-to-case thermal resistance (°C/W)

= Package case-to-ambient thermal resistance (°C/W)

θJA

θJC

θCA

R

is device related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case to ambient thermal resistance, R

. For instance, the user can change the size of the heat

θCA

sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit

board, or change the thermal dissipation on the printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the

Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a

JT

measurement of the temperature at the top center of the package case using the following equation:

T = T + (Ψ x P )

J

T

JT

D

where:

o

T

Ψ

= Thermocouple temperature on top of package ( C)

= Thermal characterization parameter ( C/W)

T

o

JT

P

= Power dissipation in package (W)

D

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

121

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

12.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation of the 56F8013/56F8011:

•

Provide a low-impedance path from the board power supply to each V_DDpin on the 56F8013/56F8011 and

from the board ground to each V_SS(GND) pin

•

The minimum bypass requirement is to place 0.01–0.1μF capacitors positioned as close as possible to the

package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of

the V_DD/V_SSpairs, including V_DDA/V_SSA.Ceramic and tantalum capacitors tend to provide better

tolerances.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_DDand V_SS(GND)

pins are as short as possible

56F8013/56F8011 Data Sheet, Rev. 12

122

Freescale Semiconductor

Electrical Design Considerations

•

Bypass the V_DDand V_SSwith approximately 100μF, plus the number of 0.1μF ceramic capacitors

•

PCB trace lengths should be minimal for high-frequency signals

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the V_DDand V_SScircuits.

•

Take special care to minimize noise levels on the V_REF, V_DDAand V_SSApins

Using separate power planes for V_DDand V_DDAand separate ground planes for V_SSand V_SSAis

recommended. Connect the separate analog and digital power and ground planes as close as possible to

power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is

advisable to connect a small inductor or ferrite bead in serial with both V_DDAand V_SSAtraces.

•

It is highly desirable to physically separate analog components from noisy digital components by ground

planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog

ground trace around an analog signal trace to isolate it from digital traces.

Because the Flash memory is programmed through the JTAG/EOnCE port, SPI, SCI or I²C, the designer

should provide an interface to this port if in-circuit Flash programming is desired.

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

123

Part 13 Ordering Information

Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

Table 13-1 56F8013/56F8011 Ordering Information

Ambient

Temperature

Range

Supply

Voltage

Count

Frequency

(MHz)

Part

Package Type

Order Number

Low-Profile Quad Flat Pack (LQFP)

MC56F8013

MC56F8011

3.0–3.6 V

32

–40° to + 125°C

–40° to + 105°C

MC56F8013MFAE*

S568013MFA00E*

MC56F8013VFAE*

MC56F8011VFAE*

*This package is RoHS compliant.

Part 14 Appendix

Register acronyms are revised from previous device data sheets to provide a cleaner register description.

A cross reference to legacy and revised acronyms are provided in the following table.

Peripheral Reference Manual

Data Sheet

Memory Address

Start End

Processor

Expert

Acronym

New

Legacy

Module

Register Name

New Acronym

Legacy Acronym

Acronym

ADC Control Register 1

CTRL1

CTRL2

ZXCTRL

CLIST1

CLIST2

SDIS

ADCR1

ADCR2

ADC_CTRL1

ADC_CTRL2

ADC_ZXCTRL

ADC_CLIST1

ADC_CLIST2

ADC_SDIS

ADC_ADCR1

ADC_ADCR2

ADC_ADCR1

ADC_ADCR2

0xF080

Control Register 2

0xF081

0xF082

Zero Crossing Control Register

ADZCC

ADC_ADZCC

Channel List Register 1

Channel List Register 2

Sample Disable Register

Status Register

ADLST1

ADC_ADLST1

ADC_ADLST2

ADC_ADSDIS

ADC_ADLST1

ADC_ADLST2

ADC_ADSDIS

ADC_ADSTAT

ADC_ADLSTAT

ADC_ADZCSTAT

ADC_ADRSLT0-7

ADC_ADLLMT0-7

0xF083

ADLST2

0xF084

ADSDIS

0xF085

STAT

ADSTAT

ADC_STAT

ADC_ADSTAT

ADC_ADLSTAT

ADC_ADZCSTAT

ADC_ADRSLT0-7

ADC_ADLLMT0-7

ADC_ADHLMT0-7

ADC_ADOFS0-7

ADC_ADPOWER

ADC_ADCAL

0xF086

Limit Status Register

LIMSTAT

ZXSTAT

RSLT0-7

LOLIM0-7

HILIM0-7

OFFST0-7

PWR

ADLSTAT

ADZCSTAT

ADRSLT0-7

ADLLMT0-7

ADHLMT0-7

ADOFS0-7

ADPOWER

ADCAL

ADC_LIMSTAT

ADC_ZXSTAT

ADC_RSLT0-7

ADC_LOLIM0-7

ADC_HILIM0-7

ADC_OFFST0-7

ADC_PWR

0xF087

Zero Crossing Status Register

Result Registers 0-7

0xF088

0xF089 0XF090

0XF091 0XF098

Low Limit Registers 0-7

High Limit Registers 0-7

Offset Registers 0-7

ADC_ADHLMT0-7 0XF099 0XF0A0

ADC_ADOFS0-7

ADC_ADPOWER

ADC_CAL

0XF0A1 0XF0A8

0XF0A9

Power Control Register

Voltage Reference Register

CAL

ADC_VREF

0XF0AA

COP Control Register

CTRL

TOUT

CNTR

COPCTL

COPTO

COP_CTRL

COP_TOUT

COP_CNTR

COPCTL

COPTO

COPCTL

COPTO

0XF0E0

0XF0E1

0XF0E2

Time-Out Register

Counter Register

COPCTR

2

Address Register

ADDR

FDIV

IBAD

IBFD

IBCR

I2C_ADDR

I2C_FDIV

I2C_CTRL

I2C_IBAD

I2C_IBFD

I2C_IBCR

IBAD

IBFD

IBCR

0xF0D0

0xF0D1

0xF0D2

I C

Frequency Divider Register

Control Register

CTRL

56F8013/56F8011 Data Sheet, Rev. 12

124

Freescale Semiconductor

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

RoHS-compliant and/or Pb-free versions of Freescale products have the

functionality and electrical characteristics of their non-RoHS-compliant

and/or non-Pb-free counterparts. For further information, see

http://www.freescale.com or contact your Freescale sales representative.

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

For information on Freescale’s Environmental Products program, go to

http://www.freescale.com/epp.

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064, Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080

Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Freescale Semiconductor does

not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized

for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other

application in which the failure of the Freescale Semiconductor product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Freescale

Semiconductor and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Freescale Semiconductor was negligent

regarding the design or manufacture of the part.

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,

Inc. All other product or service names are the property of their respective owners.

This product incorporates SuperFlash® technology licensed from SST.

MC56F8013

Rev. 12

05/2008


型号：	MC56F8013MFAE
厂家：	NXP
描述：	16-bit DSC, 56800E core, 16KB Flash, 32MHz, QFP 32 时钟 PC 微控制器外围集成电路
文件：	总126页 (文件大小：1057K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC56F8013MFAE [NXP]

相关型号：

MC56F8013PB

MC56F8013VFAE

MC56F8013VFAE

MC56F8013VFAER2

MC56F8014

MC56F8014E

MC56F8014MFAE

MC56F8014VFAE

MC56F8023

MC56F8023VLC

MC56F8025

MC56F8025E