MC56F82348MLH_技术文档

Document Number MC56F82348MLH

Rev. 2, 07/2020

NXP Semiconductors

Data Sheet: Technical Data

MC56F82348MLH

MC56F82348

Supports MC56F82348MLH

Features

• Communication interfaces

– Up to two high-speed queued SCI (QSCI) modules

with LIN slave functionality

– Up to two queued SPI (QSPI) modules

– One I2C/SMBus port

– One Modular/Scalable Controller Area Network

(MSCAN) module

• This family of digital signal controllers (DSCs) is

based on the 32-bit 56800EX core. Each device

combines, on a single chip, the processing power of a

DSP and the functionality of an MCU with a flexible

set of peripherals to support many target applications:

– Industrial control

– Home appliances

• Timers

– Smart sensors

– Wireless charging

– One 16-bit quad timer (1 x 4 16-bit timer)

– Two Periodic Interval Timers (PITs)

– Power distribution systems

– Motor control (ACIM, BLDC, PMSM, SR, stepper)

– Photovoltaic systems

– Circuit breaker

– Medical device/equipment

• Security and integrity

– Cyclic Redundancy Check (CRC) generator

– Windowed Computer operating properly (COP)

watchdog

– External Watchdog Monitor (EWM)

– Instrumentation

• Clocks

• DSC based on 32-bit 56800EX core

– Up to 50 MIPS at 50 MHz core frequency

– DSP and MCU functionality in a unified, C-efficient

architecture

– Two on-chip relaxation oscillators: 8 MHz (400 kHz

at standby mode) and 200 kHz

– Crystal / resonator oscillator

• System

• On-chip memory

– DMA controller

– Up to 64 KB flash memory

– Integrated power-on reset (POR) and low-voltage

interrupt (LVI) and brown-out reset module

– Inter-module crossbar connection

– JTAG/enhanced on-chip emulation (EOnCE) for

unobtrusive, real-time debugging

– Up to 8 KB data/program RAM

– On-chip flash memory and RAM can be mapped

into both program and data memory spaces

• Analog

– Two high-speed, 8-channel, 12-bit ADCs with

dynamic x1, x2, and x4 programmable amplifier

– Four analog comparators with integrated 6-bit DAC

references

• Operating characteristics

– Single supply: 3.0 V to 3.6 V

– 5 V–tolerant I/O (except for RESETB pin which is a

3.3 V pin only)

– Up to two 12-bit digital-to-analog converters (DAC)

• 64-pin LQFP package

• One FlexPWM module with up to 8 PWM outputs

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1

Overview............................................................................................3

7.2 Moisture handling ratings........................................................28

7.3 ESD handling ratings.............................................................. 28

7.4 Voltage and current operating ratings..................................... 29

General............................................................................................... 30

8.1 General characteristics............................................................ 30

8.2 AC electrical characteristics....................................................31

8.3 Nonswitching electrical specifications....................................32

8.4 Switching specifications..........................................................38

8.5 Thermal specifications............................................................ 39

Peripheral operating requirements and behaviors..............................40

9.1 Core modules...........................................................................40

9.2 System modules.......................................................................41

9.3 Clock modules.........................................................................42

9.4 Memories and memory interfaces...........................................44

9.5 Analog..................................................................................... 46

9.6 Timer....................................................................................... 51

9.7 Communication interfaces.......................................................52

1.1 MC56F82348MLH Product Features......................................3

1.2 56800EX 32-bit Digital Signal Controller (DSC) core...........3

1.3 Operation Parameters.............................................................. 4

1.4 On-Chip Memory and Memory Protection............................. 5

1.5 Interrupt Controller................................................................. 5

1.6 Peripheral highlights............................................................... 6

1.7 Block diagrams........................................................................11

MC56F82348MLH signal and pin descriptions.................................14

Signal groups......................................................................................22

Ordering parts.....................................................................................22

4.1 Determining valid orderable parts...........................................22

Part identification...............................................................................23

5.1 Description.............................................................................. 23

5.2 Format..................................................................................... 23

5.3 Fields....................................................................................... 23

Terminology and guidelines...............................................................23

6.1 Definition: Operating requirement..........................................23

6.2 Definition: Operating behavior............................................... 24

6.3 Definition: Attribute................................................................24

6.4 Definition: Rating....................................................................25

6.5 Result of exceeding a rating....................................................25

6.6 Relationship between ratings and operating requirements......25

6.7 Guidelines for ratings and operating requirements................. 26

6.8 Definition: Typical value........................................................ 26

6.9 Typical value conditions......................................................... 27

Ratings................................................................................................28

7.1 Thermal handling ratings........................................................ 28

8

2

3

4

9

5

6

10 Design Considerations....................................................................... 58

10.1 Thermal design considerations................................................58

10.2 Electrical design considerations..............................................60

10.3 Power-on Reset design considerations....................................61

11 Obtaining package dimensions.......................................................... 63

12 Pinout................................................................................................. 63

12.1 Signal Multiplexing and Pin Assignments..............................63

12.2 Pinout diagrams.......................................................................65

13 Product documentation.......................................................................66

14 Revision History.................................................................................67

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Overview

1 Overview

1.1 MC56F82348MLH Product Features

The following table highlights features that differ among members of the family. Features

not listed are shared in common by all members of the family.

Table 1. MC56F82348MLH features

MC56F82348MLH

Core frequency (MHz)

Flash memory (KB)

RAM (KB)

50

64

8

Windowed Computer Operating Properly (WCOP)

Periodic Interrupt Timer (PIT)

Cyclic Redundancy Check (CRC)

Timer (TMR)

1

4

12-bit Cyclic ADC channels

PWMA with input capture:

High-resolution channels

Standard channels

12-bit DAC

2x8

1x8

0

2

DMA

Yes

Analog Comparators (CMP)

QSCI

4

2

QSPI

2

I2C/SMBus

1

MSCAN

1

54

GPIO

Package pin count

64 LQFP

1.2 56800EX 32-bit Digital Signal Controller (DSC) core

• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual

Harvard architecture:

• Three internal address buses

• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data

bus, and one 16-bit instruction bus

• 32-bit data accesses

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Overview

• Supports concurrent instruction fetches in the same cycle, and dual data accesses

in the same cycle

• 20 addressing modes

• As many as 50 million instructions per second (MIPS) at 50 MHz core frequency

• 162 basic instructions

• Instruction set supports both fractional arithmetic and integer arithmetic

• 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,

plus addition, subtraction, and logical operations

• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator

(MAC) with dual parallel moves

• 32-bit arithmetic and logic multi-bit shifter

• Four 36-bit accumulators, including extension bits

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Bit reverse address mode, which effectively supports DSP and Fast Fourier

Transform algorithms

• Full shadowing of the register stack for zero-overhead context saves and restores:

nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,

N, N3, M01)

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions enable compact code

• Enhanced bit manipulation instruction set

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack, with the stack's depth limited only by

memory

• Priority level setting for interrupt levels

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging

that is independent of processor speed

1.3 Operation Parameters

• Up to 50 MHz operation

• Operation ambient temperature:

-40 ^oC to 125^oC

• Single 3.3 V power supply

• Supply range: V_DD- V_SS= 2.7 V to 3.6 V, V_DDA- V_SSA= 2.7 V to 3.6 V

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Overview

1.4 On-Chip Memory and Memory Protection

• Dual Harvard architecture permits as many as three simultaneous accesses to

program and data memory

• Internal flash memory with security and protection to prevent unauthorized access

• Memory resource protection (MRP) unit to protect supervisor programs and

resources from user programs

• Programming code can reside in flash memory during flash programming

• The dual-port RAM controller supports concurrent instruction fetches and data

accesses, or dual data accesses by the core.

• Concurrent accesses provide increased performance.

• The data and instruction arrive at the core in the same cycle, reducing latency.

• On-chip memory

• Up to 32 KB program/data flash memory

• Up to4 KB dual port data/program RAM

1.5 Interrupt Controller

• Five interrupt priority levels

• Three user-programmable priority levels for each interrupt source: level 0, level

1, level 2

• Unmaskable level 3 interrupts include illegal instruction, hardware stack

overflow, misaligned data access, SWI3 instruction

• Interrupt level 3 is highest priority and non-maskable. Its sources include:

• Illegal instructions

• Hardware stack overflow

• SWI instruction

• EOnce interrupts

• Misaligned data accesses

• Lowest-priority software interrupt: level LP

• Support for nested interrupts, so that a higher priority level interrupt request can

interrupt lower priority interrupt subroutine

• Masking of interrupt priority level is managed by the 56800EX core

• Two programmable fast interrupts that can be assigned to any interrupt source

• Notification to System Integration Module (SIM) to restart clock when in wait and

stop states

• Ability to relocate interrupt vector table

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Peripheral highlights

1.6 Peripheral highlights

1.6.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)

• Up to 100 MHz operation clock with PWM Resolution as fine as 10 ns

• PWM module contains four identical submodules, with two outputs per submodule

• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs

• PWM outputs can be configured as complementary output pairs or independent

outputs

• Dedicated time-base counter with period and frequency control per submodule

• Independent top and bottom deadtime insertion for each complementary pair

• Independent control of both edges of each PWM output

• Enhanced input capture and output compare functionality on each input:

• Channels not used for PWM generation can be used for buffered output compare

functions.

• Channels not used for PWM generation can be used for input capture functions.

• Enhanced dual edge capture functionality

• Synchronization of submodule to external hardware (or other PWM) is supported.

• Double-buffered PWM registers

• Integral reload rates from 1 to 16

• Half-cycle reload capability

• Multiple output trigger events can be generated per PWM cycle via hardware.

• Support for double-switching PWM outputs

• Up to eight fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity

• Individual software control of each PWM output

• All outputs can be programmed to change simultaneously via a FORCE_OUT event.

• Option to supply the source for each complementary PWM signal pair from any of

the following:

• Crossbar module outputs

• External ADC input, taking into account values set in ADC high and low limit

registers

1.6.2 12-bit Analog-to-Digital Converter (Cyclic type)

• Two independent 12-bit analog-to-digital converters (ADCs):

• 2 x 5-channel external inputs

• Built-in x1, x2, x4 programmable gain pre-amplifier

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Peripheral highlights

• Maximum ADC clock frequency up to 10 MHz, having period as low as 100 ns

• Single conversion time of 10 ADC clock cycles

• Additional conversion time of 8 ADC clock cycles

• Support of analog inputs for single-ended and differential (including unipolar

differential) conversions

• Sequential and parallel scan modes. Parallel mode includes simultaneous and

independent scan modes.

• First 8 samples of each ADC have offset, limit and zero-crossing calculation

supported

• ADC conversions can be synchronized by any module connected to the internal

crossbar module, such as PWM, timer, GPIO, and comparator modules.

• Support for hardware-triggering and software-triggering conversions

• Support for a multi-triggering mode with a programmable number of conversions on

each trigger

• Each ADC has ability to scan and store up to 8 conversion results.

• Current injection protection

1.6.3 Inter-Module Crossbar and AND-OR-INVERT logic

• Provides generalized connections between and among on-chip peripherals: ADCs,

12-bit DAC, comparators, quad-timers, eFlexPWMs, EWM, and select I/O pins

• User-defined input/output pins for all modules connected to the crossbar

• DMA request and interrupt generation from the crossbar

• Write-once protection for all registers

• AND-OR-INVERT function provides a universal Boolean function generator that

uses a four-term sum-of-products expression, with each product term containing true

or complement values of the four selected inputs (A, B, C, D).

1.6.4 Comparator

• Full rail-to-rail comparison range

• Support for high and low speed modes

• Selectable input source includes external pins and internal DACs

• Programmable output polarity

• 6-bit programmable DAC as a voltage reference per comparator

• Three programmable hysteresis levels

• Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output

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Peripheral highlights

1.6.5 12-bit Digital-to-Analog Converter

• 12-bit resolution

• Powerdown mode

• Automatic mode allows the DAC to automatically generate pre-programmed output

waveforms, including square, triangle, and sawtooth waveforms (for applications like

slope compensation)

• Programmable period, update rate, and range

• Output can be routed to an internal comparator, or optionally to an off-chip

destination

1.6.6 Quad Timer

• Four 16-bit up/down counters, with a programmable prescaler for each counter

• Operation modes: edge count, gated count, signed count, capture, compare, PWM,

signal shot, single pulse, pulse string, cascaded, quadrature decode

• Programmable input filter

• Counting start can be synchronized across counters

• Up to 100 MHz operation clock

1.6.7 Queued Serial Communications Interface (QSCI) modules

• Operating clock can be up to two times the CPU operating frequency

• Four-word-deep FIFOs available on both transmit and receive buffers

• Standard mark/space non-return-to-zero (NRZ) format

• 16-bit integer and 3-bit fractional baud rate selection

• Full-duplex or single-wire operation

• Programmable 8-bit or 9-bit data format

• Error detection capability

• Two receiver wakeup methods:

• Idle line

• Address mark

• 1/16 bit-time noise detection

• Up to 6.25 Mbit/s baud rate at 100 MHz operation clock

1.6.8 Queued Serial Peripheral Interface (QSPI) modules

• Maximum 12.5 Mbit/s baud rate

• Selectable baud rate clock sources for low baud rate communication

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Peripheral highlights

• Baud rate as low as the maximum Baud rate / 4096

• Full-duplex operation

• Master and slave modes

• Double-buffered operation with separate transmit and receive registers

• Four-word-deep FIFOs available on transmit and receive buffers

• Programmable length transmissions (2 bits to 16 bits)

• Programmable transmit and receive shift order (MSB as first bit transmitted)

1.6.9 Inter-Integrated Circuit (I2C)/System Management Bus (SMBus)

modules

• Compatible with I2C bus standard

• Support for System Management Bus (SMBus) specification, version 2

• Multi-master operation

• General call recognition

• 10-bit address extension

• Start/Repeat and Stop indication flags

• Support for dual slave addresses or configuration of a range of slave addresses

• Programmable glitch input filter with option to clock up to 100 MHz

1.6.10 Modular/Scalable Controller Area Network (MSCAN) Module

• Clock source from PLL or oscillator.

• Implementation of the CAN protocol Version 2.0 A/B

• Standard and extended data frames

• 0-to-8 bytes data length

• Programmable bit rate up to 1 Mbit/s

• Support for remote frames

• Individual Rx Mask Registers per Message Buffer

• Internal timer for time-stamping of received and transmitted messages

• Listen-only mode capability

• Programmable loopback mode supporting self-test operation

• Programmable transmission priority scheme: lowest ID, lowest buffer number, or

highest priority

• Low power modes, with programmable wakeup on bus activity

1.6.11 Windowed Computer Operating Properly (COP) watchdog

• Programmable windowed timeout period

• Support for operation in all power modes: run mode, wait mode, stop mode

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Peripheral highlights

• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is

detected

• Selectable reference clock source in support of EN60730 and IEC61508

• Selectable clock sources:

• External crystal oscillator / external clock source

• On-chip low-power 200 kHz oscillator

• System bus (IPBus up to 50 MHz)

• 8 MHz / 400 kHz ROSC

• Support for interrupt triggered when the counter reaches the timeout value

1.6.12 External Watchdog Monitor (EWM)

• Monitors external circuit as well as the software flow

• Programmable timeout period

• Interrupt capability prior to timeout

• Independent output (EWM_OUT_b) that places external circuit (but not CPU and

peripheral) in a safe mode when EWM timeout occurs

• Selectable reference clock source in support of EN60730 and IEC61508

• Wait mode and Stop mode operation is not supported.

• Selectable clock sources:

• External crystal oscillator / external clock source

• On-chip low-power 200 kHz oscillator

• System bus (IPBus up to 50 MHz)

• 8 MHz / 400 kHz ROSC

1.6.13 Power supervisor

• Power-on reset (POR) is released after VDD > 2.7 V during supply is ramped up;

CPU, peripherals, and JTAG/EOnCE controllers exit RESET state

• Brownout reset (V_DD< 2.0 V)

• Critical warn low-voltage interrupt (LVI 2.2 V)

• Peripheral low-voltage warning interrupt (LVI 2.7 V)

1.6.14 Phase-locked loop

• Wide programmable output frequency: 200 MHz to 400 MHz

• Input reference clock frequency: 8 MHz to 16 MHz

• Detection of loss of lock and loss of reference clock

• Ability to power down

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Clock sources

1.6.15 Clock sources

1.6.15.1 On-chip oscillators

• Tunable 8 MHz relaxation oscillator with 400 kHz at standby mode (divide-by-two

output)

• 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT

1.6.15.2 Crystal oscillator (MC56F82316 only)

• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic

resonator

• Operating frequency: 4–16 MHz

1.6.16 Cyclic Redundancy Check (CRC) Generator

• Hardware CRC generator circuit with 16-bit shift register

• High-speed hardware CRC calculation

• Programmable initial seed value

• CRC16-CCITT compliancy with x¹⁶+ x¹²+ x⁵+ 1 polynomial

• Error detection for all single, double, odd, and most multibit errors

• Option to transpose input data or output data (CRC result) bitwise, which is required

for certain CRC standards

1.6.17 General Purpose I/O (GPIO)

• 5 V tolerance (except RESET_B )

• Individual control of peripheral mode or GPIO mode for each pin

• Programmable push-pull or open drain output

• Configurable pullup or pulldown on all input pins

• All pins (except JTAG, RESET_B ) default to be GPIO inputs

• 2 mA / 9 mA capability

• Controllable output slew rate

1.7 Block diagrams

The 56800EX core is based on a modified dual Harvard-style architecture, consisting of

three execution units operating in parallel, and allowing as many as six operations per

instruction cycle. The MCU-style programming model and optimized instruction set

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Clock sources

enable straightforward generation of efficient and compact code for the DSP and control

functions. The instruction set is also efficient for C compilers, to enable rapid

development of optimized control applications.

The device's basic architecture appears in Figure 1 and Figure 2. Figure 1 shows how the

56800EX system buses communicate with internal memories, and the IPBus interface

and the internal connections among the units of the 56800EX core. Figure 2 shows the

peripherals and control blocks connected to the IPBus bridge. See the specific device’s

Reference Manual for details.

DSP56800EX Core

Program Control Unit

ALU1

ALU2

Address

Generation

Unit

PC

LA

LA2

HWS0

HWS1

FIRA

Instruction

Decoder

R0

R1

(AGU)

R2

Interrupt

Unit

Program

Memory

M01

N3

R3

OMR

R4

SR

LC

LC2

R5

Looping

Unit

N

SP

FISR

XAB1

XAB2

PAB

Data/

Program

RAM

PDB

CDBW

CDBR

XDB2

A2

B2

C2

D2

A1

B1

C1

D1

Y1

Y0

X0

A0

B0

C0

D0

Bit-

Manipulation

Unit

IPBus

Interface

Data

Y

Enhanced

OnCE™

Arithmetic

Logic Unit

(ALU)

JTAG TAP

MAC and ALU Multi-Bit Shifter

Figure 1. 56800EX basic block diagram

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Clock sources

JTAG

Program Bus

Core Data Bus

EOnCE

56800EX CPU

Program

Controller

(PC)

Address

Generation

Unit (AGU)

Program/Data Flash

Up to 32KB

4

Secondary Data Bus

Arithmetic

Logic Unit

(ALU)

Bit

Manipulation

Unit

Data/Program RAM

Up to 6KB

DMA Controller

Interrupt Controller

Crystal OSC

Internal

8 MHz

Internal

200 kHz

Windowed

Watchdog (WCOP)

Power Management

Controller (PMC)

System Integration

Module (SIM)

Periodic Interrupt

Timer (PIT) 0, 1

CRC

PLL

Peripheral Bus

QSCI

0,1

I2C

0

QSPI

0

Quad Timer

eFlexPWM

EWM

Inter Module connection

Inter-Module

Crossbar B

AND-OR-INV

Logic

GPIO & Peripheral MUX

Inter-Module

Crossbar A

Package

Pins

DACB

12bit

Comparators with

6bit DAC A,B,C

ADC B

12bit

DACA

12bit

ADC A

12bit

Peripheral Bus

Figure 2. System diagram

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MC56F82348MLH signal and pin descriptions

2 MC56F82348MLH signal and pin descriptions

After reset, each pin is configured for its primary function (listed first). Any alternative

functionality, shown in parentheses, must be programmed through the GPIO module

peripheral enable registers (GPIOx_PER) and the SIM module GPIO peripheral select

(GPSx) registers. All GPIO ports can be individually programmed as an input or output

(using bit manipulation).

• PWMA_FAULT0, PWMA_FAULT1, and similar signals are inputs used to disable

selected PWMA outputs, in cases where the fault conditions originate off-chip.

Table 2. Signal descriptions

Signal Name

V_DD

64

LQFP

Type

Supply

State During

Reset

Signal Description

29

Supply

I/O Power — Supplies 3.3 V power to the chip I/O interface.

44

60

30

43

61

22

V_SS

Supply

I/O Ground — Provide ground for the device I/O interface.

V_DDA

V_SSA

V_CAP

Supply

Analog Power — Supplies 3.3 V power to the analog modules. It

must be connected to a clean analog power supply.

23

Analog Ground — Supplies an analog ground to the analog modules.

It must be connected to a clean power supply.

26

57

On-chip

regulator

output

On-chip

regulator

output

Connect a 2.2 µF or greater bypass capacitor between this pin and

V_SSto stabilize the core voltage regulator output required for proper

device operation.

TDI

64

Input

Input, internal Test Data Input — It is sampled on the rising edge of TCK and has

pullup

an internal pullup resistor. After reset, the default state is TDI.

enabled

(GPIOD0)

TDO

Input/

Output

GPIO Port D0

62

Output

Test Data Output — It is driven in the shift-IR and shift-DR controller

states, and it changes on the falling edge of TCK. After reset, the

default state is TDO

(GPIOD1)

Input/

GPIO Port D1

Output

TCK

1

Input

Input, internal Test Clock Input — The pin is connected internally to a pullup

pullup

enabled

resistor. A Schmitt-trigger input is used for noise immunity. After

reset, the default state is TCK

(GPIOD2)

Input/

GPIO Port D2

Output

TMS

63

Input

Input, internal Test Mode Select Input — It is sampled on the rising edge of TCK

pullup

enabled

and has an internal pullup resistor. After reset, the default state is

TMS.

Table continues on the next page...

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MC56F82348MLH signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name

64

LQFP

Type

State During

Reset

Signal Description

NOTE: Always tie the TMS pin to V_DDthrough a 2.2 kΩ resistor if

need to keep on-board debug capability. Otherwise, directly

tie to V_DD

.

(GPIOD3)

Input/

GPIO Port D3

Output

RESET or

RESETB

2

Input

Input, internal Reset — A direct hardware reset on the processor. When RESET is

pullup

asserted low, the device is initialized and placed in the reset state. A

Schmitt-trigger input is used for noise immunity. The internal reset

signal is deasserted synchronous with the internal clocks after a

fixed number of internal clocks. After reset, the default state is

RESET. Recommended a capacitor of up to 0.1 µF for filtering noise.

enabled

(GPIOD4)

Input/

Opendrain

Output

GPIO Port D4 RESET functionality is disabled in this mode and the

device can be reset only through POR, COP reset, or software reset.

GPIOA0

13

Input/

Input, internal GPIO Port A0

Output

pullup

enabled

(ANA0&CMPA_I

N3)

Input

ANA0 is analog input to channel 0 of ADCA; CMPA_IN3 is positive

input 3 of analog comparator A. After reset, the default state is

GPIOA0.

(CMPC_O)

Output

Analog comparator C output

GPIOA1

14

15

16

Input/

Output

Input, internal GPIO Port A1: After reset, the default state is GPIOA1.

pullup

enabled

(ANA1&CMPA_I

N0)

Input

ANA1 is analog input to channel 1 of ADCA; CMPA_IN0 is negative

input 0 of analog comparator A. When used as an analog input, the

signal goes to ANA1 and CMPA_IN0. The ADC control register

configures this input as ANA1 or CMPA_IN0.

GPIOA2

Input/

Output

Input, internal GPIO Port A2: After reset, the default state is GPIOA2.

pullup

enabled

(ANA2&VREFH

A&CMPA_IN1)

Input

ANA2 is analog input to channel 2 of ADCA; VREFHA is analog

reference high of ADCA; CMPA_IN1 is negative input 1 of analog

comparator A. When used as an analog input, the signal goes to

both ANA2, VREFHA, and CMPA_IN1.

GPIOA3

Input/

Output

Input, internal GPIO Port A3: After reset, the default state is GPIOA3.

pullup

enabled

(ANA3&VREFL

A&CMPA_IN2)

Input

ANA3 is analog input to channel 3 of ADCA; VREFLA is analog

reference low of ADCA; CMPA_IN2 is negative input 2 of analog

comparator A.

GPIOA4

12

11

Input/

Output

Input, internal GPIO Port A4: After reset, the default state is GPIOA4.

pullup

enabled

(ANA4&CMPD_I

N0)

Input

ANA4 is Analog input to channel 4 of ADCA; CMPD_IN0 is input 0 to

comparator D.

GPIOA5

Input/

Output

Input, internal GPIO Port A5: After reset, the default state is GPIOA5.

pullup

enabled

(ANA5&CMPD_I

N1)

Input

ANA5 is analog input to channel 5 of ADCA; ANC9 is analog input to

channel 9 of ADCC; CMPD_IN1 is negative input 1 of analog

comparator D.

Table continues on the next page...

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15

MC56F82348MLH signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name

GPIOA6

64

LQFP

Type

State During

Reset

Signal Description

10

Input/

Output

Input

Input, internal GPIO Port A6: After reset, the default state is GPIOA6.

pullup

enabled

(ANA6&CMPD_I

N2)

ANA6 is analog input to channel 5 of ADCA; CMPD_IN2 is negative

input 2 of analog comparator D.

GPIOA7

9

Input/

Input, internal GPIO Port A7: After reset, the default state is GPIOA7.

Output

pullup

enabled

(ANA7&CMPD_I

N3)

Input

ANA7 is analog input to channel 7 of ADCA; CMPD_IN3 is negative

input 3 of analog comparator D.

GPIOB0

24

Input/

Output

Input, internal GPIO Port B0: After reset, the default state is GPIOB0.

pullup

enabled

(ANB0&CMPB_I

N3)

Input

ANB0 is analog input to channel 0 of ADCB; CMPB_IN3 is positive

input 3 of analog comparator B. When used as an analog input, the

signal goes to ANB0 and CMPB_IN3. The ADC control register

configures this input as ANB0.

GPIOB1

25

Input/

Output

Input, internal GPIO Port B1: After reset, the default state is GPIOB1.

pullup

enabled

(ANB1&CMPB_I

N0)

Input

ANB1 is analog input to channel 1 of ADCB; CMPB_IN0 is negative

input 0 of analog comparator B. When used as an analog input, the

signal goes to ANB1 and CMPB_IN0. The ADC control register

configures this input as ANB1.

DACB_O

Analog

Output

12-bit digital-to-analog output

GPIOB2

27

28

Input/

Output

Input, internal GPIO Port B2: After reset, the default state is GPIOB2.

pullup

enabled

(ANB2&VERFH

B&CMPC_IN3)

Input

ANB2 is analog input to channel 2 of ADCB; VREFHB is analog

reference high of ADCB; CMPC_IN3 is positive input 3 of analog

comparator C. When used as an analog input, the signal goes to

both ANB2 and CMPC_IN3.

GPIOB3

Input/

Output

Input, internal GPIO Port B3: After reset, the default state is GPIOB3.

pullup

enabled

(ANB3&VREFL

B&CMPC_IN0)

Input

ANB3 is analog input to channel 3 of ADCB; VREFLB is analog

reference low of ADCB; CMPC_IN0 is negative input 0 of analog

comparator C.

GPIOB4

21

20

19

Input/

Output

Input, internal GPIO Port B4: After reset, the default state is GPIOB4.

pullup

enabled

(ANB4&CMPC_I

N1)

Input

ANB4 is analog input to channel 4 of ADCB; CMPC_IN1 is negative

input 1 of analog comparator C.

GPIOB5

Input/

Output

Input, internal GPIO Port B5: After reset, the default state is GPIOB5.

pullup

enabled

(ANB5&CMPC_I

N2)

Input

ANB5 is analog input to channel 5 of ADCB; CMPC_IN2 is negative

input 2 of analog comparator C.

GPIOB6

Input/

Output

Input, internal GPIO Port B6: After reset, the default state is GPIOB6.

pullup

enabled

(ANB6&CMPB_I

N1)

Input

ANB6 is analog input to channel 6 of ADCB; CMPB_IN1 is negative

input 1 of analog comparator B.

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MC56F82348MLH signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name

GPIOB7

64

LQFP

Type

State During

Reset

Signal Description

17

Input/

Output

Input

Input, internal GPIO Port B7: After reset, the default state is GPIOB7.

pullup

enabled

(ANB7&CMPB_I

N2)

ANB7 is analog input to channel 7 of ADCB; CMPB_IN2 is negative

input 2 of analog comparator B.

GPIOC0

3

Input/

Output

Input, internal GPIO Port C0: After reset, the default state is GPIOC0.

pullup

enabled

(EXTAL)

Analog

Input

The external crystal oscillator input (EXTAL) connects the internal

crystal oscillator input to an external crystal or ceramic resonator.

(CLKIN0)

Input

External clock input 0¹

GPIOC1

4

5

Input/

Output

Input, internal GPIO Port C1: After reset, the default state is GPIOC1.

pullup

enabled

(XTAL)

Input

The external crystal oscillator output (XTAL) connects the internal

crystal oscillator output to an external crystal or ceramic resonator.

GPIOC2

Input/

Output

Input, internal GPIO Port C2: After reset, the default state is GPIOC2.

pullup

enabled

(TXD0)

Output

Input

SCI0 transmit data output or transmit/receive in single wire operation

(XB_OUT11)

(XB_IN2)

(CLKO0)

Crossbar module output 11

Crossbar module input 2

Output

Buffered clock output 0: the clock source is selected by clockout

select (CLKOSEL) bits in the clock output select register (CLKOUT)

of the SIM.

GPIOC3

7

Input/

Output

Input, internal GPIO Port C3: After reset, the default state is GPIOC3.

pullup

enabled

(TA0)

Input/

Quad timer module A channel 0 input/output

Output

(CMPA_O)

(RXD0)

Output

Input

Analog comparator A output

SCI0 receive data input

External clock input 1

(CLKIN1)

GPIOC4

Input

8

Input/

Output

Input, internal GPIO Port C4: After reset, the default state is GPIOC4.

pullup

enabled

(TA1)

Input/

Quad timer module A channel 1 input/output

Output

(CMPB_O)

(XB_IN6)

Output

Input

Analog comparator B output

Crossbar module input 6

(EWM_OUT_B)

GPIOC5

Output

External Watchdog Module output

18

31

Input/

Output

Input, internal GPIO Port C5: After reset, the default state is GPIOC5.

pullup

enabled

(DACA_O)

Analog

Output

12-bit digital-to-analog output

(XB_IN7)

Input

Crossbar module input 7

GPIOC6

Input/

Output

Input, internal GPIO Port C6: After reset, the default state is GPIOC6.

pullup

enabled

(TA2)

Input/

Quad timer module A channel 2 input/output

Output

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MC56F82348MLH signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name

64

LQFP

Type

State During

Reset

Signal Description

(XB_IN3)

Input

Crossbar module input 3

(CMP_REF)

Analog

Input

Positive input 3 of analog comparator A and B and C.

(SS0_B)

GPIOC7

(SS0_B)

Input/

Output

In slave mode, SS0_B indicates to the SPI module 0 that the current

transfer is to be received.

32

Input/

Output

Input, internal GPIO Port C7: After reset, the default state is GPIOC7.

pullup enable

Input/

Output

In slave mode, SS0_B indicates to the SPI module 0 that the current

transfer is to be received.

(TXD0)

Output

Input

SCI0 transmit data output or transmit/receive in single wire operation

Crossbar module input 8

(XB_IN8)

GPIOC8

33

Input/

Output

Input, internal GPIO Port C8: After reset, the default state is GPIOC8.

pullup

enabled

(MISO0)

Input/

Master in/slave out for SPI0 — In master mode, MISO0 pin is the

Output

data input. In slave mode, MISO0 pin is the data output. The MISO

line of a slave device is placed in the high-impedance state if the

slave device is not selected.

(RXD0)

Input

SCI0 receive data input

Crossbar module input 9

Crossbar module output 6

(XB_IN9)

(XB_OUT6)

GPIOC9

Input

Output

34

Input/

Output

Input, internal GPIO Port C9: After reset, the default state is GPIOC9.

pullup

enabled

(SCLK0)

Input/

SPI0 serial clock. In master mode, SCLK0 pin is an output, clocking

Output

slaved listeners. In slave mode, SCLK0 pin is the data clock input.

(XB_IN4)

(TXD0)

Input

Crossbar module input 4

Output

SCI0 transmit data output or transmit/receive in single wire operation

Crossbar module output 8

(XB_OUT8)

GPIOC10

35

Input/

Output

Input, internal GPIO Port C10: After reset, the default state is GPIOC10.

pullup

enabled

(MOSI0)

Input/

Master out/slave in for SPI0 — In master mode, MOSI0 pin is the

Output

data output. In slave mode, MOSI0 pin is the data input.

(XB_IN5)

(MISO0)

Input

Crossbar module input 4

Input/

Output

Master in/slave out for SPI0 — In master mode, MISO0 pin is the

data input. In slave mode, MISO0 pin is the data output. The MISO

line of a slave device is placed in the high-impedance state if the

slave device is not selected.

(XB_OUT9)

Output

Crossbar module output 9

GPIOC11

37

Input/

Output

Input, internal GPIO Port C11: After reset, the default state is GPIOC11.

pullup

enabled

(CANTX)

(SCL0)

Open-drain

Output

CAN transmit data output

Input/

I²C0 serial clock

Open-drain

Output

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MC56F82348MLH signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name

(TXD1)

64

LQFP

Type

State During

Reset

Signal Description

Output

SCI1 transmit data output or transmit/receive in single wire operation

GPIOC12

38

Input/

Output

Input, internal GPIO Port C12: After reset, the default state is GPIOC12.

pullup

enabled

(CANRX)

(SDA0)

Input

CAN receive data input

I²C0 serial data line

Input/

Open-drain

Output

(RXD1)

Input

SCI1 receive data input

GPIOC13

49

55

Input/

Output

Input, internal GPIO Port C13: After reset, the default state is GPIOC13.

pullup

enabled

(TA3)

Input/

Output

Quad timer module A channel 3 input/output

(XB_IN6)

Input

Crossbar module input 6

(EWM_OUT_B)

GPIOC14

Output

External Watchdog Module output

Input/

Output

Input, internal GPIO Port C14: After reset, the default state is GPIOC14.

pullup

enabled

(SDA0)

Input/

I²C0 serial data line

Opendrain

Output

(XB_OUT4)

(PWM_FAULT4)

GPIOC15

Output

Input

Crossbar module output 4

Disable PWMA output 4

56

Input/

Output

Input, internal GPIO Port C15: After reset, the default state is GPIOC15.

pullup

enabled

(SCL0)

Input/

I²C0 serial clock

Open-drain

Output

(XB_OUT5)

(PWM_FAULT5)

GPIOE0

Output

Input

Crossbar module output 5

Disable PWMA output 5

45

46

47

48

Input/

Output

Input, internal GPIO Port E0: After reset, the default state is GPIOE0.

pullup

enabled

(PWM_0B)

GPIOE1

Input/

Output

PWM module A (NanoEdge), submodule 0, output B or input capture

B

Input/

Output

Input, internal GPIO Port E1: After reset, the default state is GPIOE1.

pullup

enabled

(PWM_0A)

GPIOE2

Input/

Output

PWM module A (NanoEdge), submodule 0, output A or input capture

A

Input/

Output

Input, internal GPIO Port E2: After reset, the default state is GPIOE2.

pullup

enabled

(PWMA_1B)

GPIOE3

Input/

Output

PWM module A (NanoEdge), submodule 1, output B or input capture

B

Input/

Output

Input, internal GPIO Port E3: After reset, the default state is GPIOE3.

pullup

enabled

(PWMA_1A)

Input/

PWM module A (NanoEdge), submodule 1, output A or input capture

Output

A

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MC56F82348MLH signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name

GPIOE4

64

LQFP

Type

State During

Reset

Signal Description

51

Input/

Output

Input, internal GPIO Port E4: After reset, the default state is GPIOE4.

pullup

enabled

(PWMA_2B)

Input/

PWM module A (NanoEdge), submodule 2, output B or input capture

Output

B

(XB_IN2)

Input

Crossbar module input 2

GPIOE5

52

53

54

36

Input/

Output

Input, internal GPIO Port E5: After reset, the default state is GPIOE5.

pullup

enabled

(PWMA_2A)

Input/

Output

PWM module A (NanoEdge), submodule 2, output A or input capture

A

(XB_IN3)

Input

Crossbar module input 3

GPIOE6

Input/

Output

Input, internal GPIO Port E6: After reset, the default state is GPIOE6.

pullup

enabled

(PWMA_3B)

Input/

Output

PWM module A (NanoEdge), submodule 3, output B or input capture

B

(XB_IN4)

Input

Crossbar module input 4

GPIOE7

Input/

Output

Input, internal GPIO Port E7: After reset, the default state is GPIOE7.

pullup

enabled

(PWMA_3A)

Input/

Output

PWM module A (NanoEdge), submodule 3, output A or input capture

A

(XB_IN5)

Input

Crossbar module input 5

GPIOF0

Input/

Output

Input, internal GPIO Port F0: After reset, the default state is GPIOF0.

pullup

enabled

(XB_IN6)

(SCLK1)

Input

Crossbar module input 6

Input/

Output

SPI1 serial clock — In master mode, SCLK1 pin is an output,

clocking slaved listeners. In slave mode, SCLK1 pin is the data clock

input 0.

GPIOF1

50

Input/

Output

Input, internal GPIO Port F1: After reset, the default state is GPIOF1.

pullup

enabled

(CLKO1)

Output

Buffered clock output 1: the clock source is selected by clockout

select (CLKOSEL) bits in the clock output select register (CLKOUT)

of the SIM.

(XB_IN7)

(CMPD_O)

GPIOF2

Input

Crossbar module input 7

Output

Analog comparator D output

39

Input/

Output

Input, internal GPIO Port F2: After reset, the default state is GPIOF2.

pullup

enabled

(SCL0)

Input/

Open-

drain

I²C0 serial clock

Output

(XB_OUT6)

(MISO1)

Output

Crossbar module output 6

Input/

Output

Master in/slave out for SPI1 —In master mode, MISO1 pin is the

data input. In slave mode, MISO1 pin is the data output. The MISO

line of a slave device is placed in the high-impedance state if the

slave device is not selected.

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MC56F82348MLH signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name

GPIOF3

64

LQFP

Type

State During

Reset

Signal Description

40

Input/

Output

Input, internal GPIO Port F3: After reset, the default state is GPIOF3.

pullup

enabled

(SDA0)

Input/

I²C0 serial data line

Open-drain

Output

(XB_OUT7)

(MOSI1)

Output

Crossbar module output 7

Input/

Output

Master out/slave in for SPI1— In master mode, MOSI1 pin is the

data output. In slave mode, MOSI1 pin is the data input.

GPIOF4

41

Input/

Output

Input, internal GPIO Port F4: After reset, the default state is GPIOF4.

pullup

enabled

(TXD1)

Output

SCI1 transmit data output or transmit/receive in single wire operation

(XB_OUT8)

(PWMA_0X)

Crossbar module output 8

Input/

Output

PWM module A (NanoEdge), submodule 0, output X or input capture

X

(PWMA_FAULT

6)

Input

Disable PWMA output 6

GPIOF5

42

Input/

Output

Input, internal GPIO Port F5: After reset, the default state is GPIOF5.

pullup

enabled

(RXD1)

Input

SCI1 receive data input

(XB_OUT9)

(PWMA_1X)

Output

Crossbar module output 9

Input/

Output

PWM module A (NanoEdge), submodule 1, output X or input capture

X

(PWMA_FAULT

7)

Input

Disable PWMA output 7

GPIOF6

58

59

Input/

Output

Input, internal GPIO Port F6: After reset, the default state is GPIOF6.

pullup

enabled

(PWMA_3X)

Input/

Output

PWM module A (NanoEdge), submodule 3, output X or input capture

X

(XB_IN2)

Input

Crossbar module input 2

GPIOF7

Input/

Output

Input, internal GPIO Port F7: After reset, the default state is GPIOF7.

pullup

enabled

(CMPC_O)

(SS1_B)

Output

Analog comparator C output

Input/

Output

In slave mode, SS1_B indicates to the SPI1 module that the current

transfer is to be received.

(XB_IN3)

Input

Crossbar module input 3

GPIOF8

6

Input/

Input, internal GPIO Port F8: After reset, the default state is GPIOF8.

Output

pullup

enabled

(RXD0)

Input

SCI0 receive data input

(XB_OUT10)

(CMPD_O)

(PWMA_2X)

Output

Crossbar module output 10

Analog comparator D output

PWM module A (NanoEdge), submodule 2, output X or input capture

X

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Signal groups

1. If CLKIN is selected as the device’s external clock input, then both the GPS_C0 bit (in GPS1) and the EXT_SEL bit (in

OCCS oscillator control register (OSCTL)) must be set. Also, the crystal oscillator should be powered down.

3 Signal groups

The input and output signals of the MC56F82348MLH are organized into functional

groups, as detailed in Table 3.

Table 3. Functional Group Pin Allocations

Functional Group

Number of

Pins in

64LQFP

Power Inputs (V_DD, V_DDA), Power output( V_CAP

)

6

4

Ground (V_SS, V_SSA

)

Reset

1

eFlexPWM with NanoEdge ports not including fault pins (for 56F827xx)

eFlexPWM without NanoEdge ports not including fault pins

Queued Serial Peripheral Interface (QSPI0 and QSPI1) ports

Queued Serial Communications Interface (QSCI0 and QSCI1) ports

Inter-Integrated Circuit Interface (I²C0) ports

12-bit Analog-to-Digital Converter inputs

8

4

9

10

6

16

17/5

2

Analog Comparator inputs/outputs

12-bit Digital-to-Analog output

Quad Timer Module (TMRA and TMRB) ports

Controller Area Network (MSCAN)

4

2

Inter-Module Crossbar inputs/outputs

17/11

2/2

4

Clock inputs/outputs

JTAG / Enhanced On-Chip Emulation (EOnCE)

4 Ordering parts

4.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to nxp.com and perform a part number search for the

following device numbers: MC56F82

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NXP Semiconductors

Part identification

5 Part identification

5.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

5.2 Format

Part numbers for this device have the following format: Q 56F8 2 C F P T PP N

5.3 Fields

This table lists the possible values for each field in the part number (not all combinations

are valid):

Field

Description

Values

Q

Qualification status

• MC = Fully qualified, general market flow

• PC = Prequalification

56F8

DSC family with flash memory and DSP56800/

DSP56800E/DSP56800EX core

• 56F8

2

DSC subfamily

• 2

C

F

Maximum CPU frequency (MHz)

Primary program flash memory size

Pin count

• 3 = 50 MHz

• 4 = 64 KB

• 8 = 64

P

T

Temperature range (°C)

Package identifier

• M = –40 to 125

• LH = 64LQFP

PP

N

Packaging type

• R = Tape and reel

• (Blank) = Trays

6 Terminology and guidelines

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Terminology and guidelines

6.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical

characteristic that you must guarantee during operation to avoid incorrect operation and

possibly decreasing the useful life of the chip.

6.1.1 Example

This is an example of an operating requirement:

Symbol

Description

Min.

Max.

Unit

V_DD

1.0 V core supply

voltage

0.9

1.1

V

6.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of values

for a technical characteristic that are guaranteed during operation if you meet the

operating requirements and any other specified conditions.

6.2.1 Example

This is an example of an operating behavior:

Symbol

Description

Min.

Max.

Unit

I_WP

Digital I/O weak pullup/ 10

pulldown current

130

µA

6.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are

guaranteed, regardless of whether you meet the operating requirements.

6.3.1 Example

This is an example of an attribute:

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NXP Semiconductors

Terminology and guidelines

Symbol

Description

Min.

Max.

Unit

CIN_D

Input capacitance:

digital pins

—

7

pF

6.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded,

may cause permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

6.4.1 Example

This is an example of an operating rating:

Symbol

Description

Min.

Max.

Unit

V_DD

1.0 V core supply

voltage

–0.3

1.2

V

6.5 Result of exceeding a rating

40

30

The likelihood of permanent chip failure increases rapidly as

soon as a characteristic begins to exceed one of its operating ratings.

20

10

0

Operating rating

Measured characteristic

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25

Terminology and guidelines

6.6 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

6.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

6.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Given the typical manufacturing process, is representative of that characteristic

during operation when you meet the typical-value conditions or other specified

conditions

Typical values are provided as design guidelines and are neither tested nor guaranteed.

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NXP Semiconductors

Terminology and guidelines

6.8.1 Example 1

This is an example of an operating behavior that includes a typical value:

Symbol

Description

Min.

Typ.

Max.

Unit

I_WP

Digital I/O weak

pullup/pulldown

current

10

70

130

µA

6.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and

temperature conditions:

5000

4500

4000

T_J

3500

150 °C

3000

105 °C

2500

25 °C

2000

–40 °C

1500

1000

500

0

0.90

0.95

1.00

1.05

1.10

V_DD(V)

6.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

3.3 V supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

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27

Ratings

7 Ratings

7.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

7.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

7.3 ESD handling ratings

Although damage from electrostatic discharge (ESD) is much less common on these

devices than on early CMOS circuits, use normal handling precautions to avoid exposure

to static discharge. Qualification tests are performed to ensure that these devices can

withstand exposure to reasonable levels of static without suffering any permanent

damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification. During the

device qualification ESD stresses were performed for the human body model (HBM), the

machine model (MM), and the charge device model (CDM).

All latch-up testing is in conformity with AEC-Q100 Stress Test Qualification.

A device is defined as a failure if after exposure to ESD pulses, the device no longer

meets the device specification. Complete DC parametric and functional testing is

performed as per the applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

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Ratings

Table 4. ESD/Latch-up Protection

Characteristic¹

Min

–2000

–200

–500

–100

Max

+2000

+200

+500

+100

Unit

ESD for Human Body Model (HBM)

ESD for Machine Model (MM)

V

ESD for Charge Device Model (CDM)

V

Latch-up current at TA= 85°C (I_LAT

)

mA

1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions

unless otherwise noted.

7.4 Voltage and current operating ratings

Absolute maximum ratings are stress ratings only, and functional operation at the

maxima is not guaranteed. Stress beyond the limits specified in Table 5 may affect device

reliability or cause permanent damage to the device.

NOTE

If the voltage difference between VDD and VDDA or VSS and

VSSA is too large, then the device can malfunction or be

permanently damaged. The restrictions are:

• At all times, it is recommended that the voltage

difference of VDD - VSS be within +/-200 mV of the

voltage difference of VDDA - VSSA, including power

ramp up and ramp down; see additional requirements in

Table 6. Failure to do this recommendation may result in a

harmful leakage current through the substrate, between the

VDD/VSS and VDDA/VSSA pad cells. This harmful

leakage current could prevent the device from operating

after power up.

• At all times, to avoid permanent damage to the part, the

voltage difference between VDD and VDDA must

absolutely be limited to 0.3 V; see Table 5.

• At all times, to avoid permanent damage to the part, the

voltage difference between VSS and VSSA must

absolutely be limited to 0.3 V; see Table 5.

Table 5. Absolute Maximum Ratings (V_SS= 0 V, V_SSA= 0 V)

Characteristic

Supply Voltage Range

Analog Supply Voltage Range

Symbol

V_DD

Notes

Min

-0.3

Max

4.0

Unit

V

V_DDA

4.0

V

Table continues on the next page...

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General

Table 5. Absolute Maximum Ratings (V_SS= 0 V, V_SSA= 0 V) (continued)

Characteristic

Symbol

V_REFHx

ΔV_DD

ΔV_SS

V_IN

Notes

Min

-0.3

-0.4

-0.3

—

Max

4.0

0.3

5.5

4.0

-5.0

20.0

25

Unit

V

ADC High Voltage Reference

Voltage difference V_DDto V_DDA

Voltage difference V_SSto V_SSA

Digital Input Voltage Range

V

Pin Group 1

Pin Group 2

Pin Group 4

Pin Group 3

V

RESET Input Voltage Range

Oscillator Input Voltage Range

Analog Input Voltage Range

V_{IN_RESET}

V_OSC

V_INA

V

Input clamp current, per pin (V_IN< V_SS- 0.3 V),

Output clamp current, per pin

V_IC

mA

V_OC

—

Contiguous pin DC injection current—regional limit sum

of 16 contiguous pins

I_ICont

-25

Output Voltage Range (normal push-pull mode)

Output Voltage Range (open drain mode)

RESET Output Voltage Range

V_OUT

Pin Group 1, 2

Pin Group 1

Pin Group 2

-0.3

4.0

5.5

4.0

V

V_OUTOD

V_{OUTOD_RE}

SET

DAC Output Voltage Range

Ambient Temperature

V_{OUT_DAC}

Pin Group 5

M temperature

-0.3

-40

-55

4.0

125

135

150

V

T_A

T_j

°C

Junction Temperature

Storage Temperature Range (Extended Industrial)

T_STG

8 General

8.1 General characteristics

The device is fabricated in high-density, low-power CMOS with 5 V–tolerant TTL-

compatible digital inputs, except 3.3 V for RESET . The term “5 V–tolerant” refers to the

capability of an I/O pin, built on a 3.3 V–compatible process technology, to withstand a

voltage up to 5.5 V without damaging the device.

5 V–tolerant I/O is desirable because many systems have a mixture of devices designed

for 3.3 V and 5 V power supplies. In such systems, a bus may carry both 3.3 V– and 5 V–

compatible I/O voltage levels . This 5 V–tolerant capability therefore offers the power

savings of 3.3 V I/O levels combined with the ability to receive 5 V levels without

damage.

Absolute maximum ratings in Table 5 are stress ratings only, and functional operation at

the maximum is not guaranteed. Stress beyond these ratings may affect device reliability

or cause permanent damage to the device.

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NXP Semiconductors

General

Unless otherwise stated, all specifications within this chapter apply to the temperature

range specified in Table 5 over the following supply ranges: V_SS=V_SSA=0V,

V_DD=V_DDA=3.0V to 3.6V, CL≤50 pF, f_OP=50MHz.

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields. However,

normal precautions are advised to avoid application of any

voltages higher than maximum-rated voltages to this high-

impedance circuit. Reliability of operation is enhanced if

unused inputs are tied to an appropriate voltage level.

8.2 AC electrical characteristics

Tests are conducted using the input levels specified in the section "Voltage and current

operating behaviors". Unless otherwise specified, propagation delays are measured from

the 50% to the 50% point, and rise and fall times are measured between the 10% and 90%

points, as shown in Figure 3.

Low

High

V

IH

90%

50%

10%

Midpoint1

Fall Time

Input Signal

V

IL

Rise Time

The midpoint is V + (V – V )/2.

IL

IH

IL

Figure 3. Input signal measurement references

Figure 4 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state

• Tri-stated, when a bus or signal is placed in a high impedance state

• Data Valid state, when a signal level has reached V_OLor V_OH

• Data Invalid state, when a signal level is in transition between V_OLand V_OH

Data1 Valid

Data1

Data2 Valid

Data2

Data3 Valid

Data3

Data

Data Invalid State

Tri-stated

Data Active

Figure 4. Signal states

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General

8.3 Nonswitching electrical specifications

8.3.1 Voltage and current operating requirements

This section includes information about recommended operating conditions.

NOTE

Recommended V_DDramp rate is less than 200 ms.

Table 6. Recommended Operating Conditions (V_REFLx=0V, V_SSA=0V, V_SS=0V)

Characteristic

Symbol

V_DD, V_DDA

V_REFHA

V_REFHB

ΔVDD

ΔVSS

Notes¹

Min

2.7

Typ

Max

3.6

Unit

V

Supply voltage

3.3

ADC (Cyclic) Reference Voltage High

V_DDA-0.6

V_DDA

V

Voltage difference V_DDto V_DDA

Voltage difference V_SSto V_SSA

Input Voltage High (digital inputs)

RESET Input Voltage High

-0.1

0

0.1

V

-0.1

V_IH

Pin Group 1

Pin Group 2

0.7 x V_DD

5.5

V_{IH_RESET}

V_IL

—

V_DD

Input Voltage Low (digital inputs)

Oscillator Input Voltage High

XTAL driven by an external clock source

Oscillator Input Voltage Low

Pin Groups 1, 2

Pin Group 4

0.3 x V_DD

V_DD+ 0.3

V_IHOSC

2.0

V_ILOSC

I_OH

Pin Group 4

-0.3

0.8

V

Output Source Current High (at V_OHmin.)

• Programmed for low drive strength

Pin Group 1

—

-2

-9

mA

• Programmed for high drive strength

Output Source Current Low (at V_OLmax.)^{2, 3}

• Programmed for low drive strength

I_OL

Pin Groups 1, 2

—

2

9

mA

• Programmed for high drive strength

1. Default Mode

• Pin Group 1: GPIO, TDI, TDO, TMS, TCK

• Pin Group 2: RESET

• Pin Group 3: ADC and Comparator Analog Inputs

• Pin Group 4: XTAL, EXTAL

• Pin Group 5: DAC analog output

2. When ambient temperature is below 105°C, total IO sink current and total IO source current are limited to 75 mA each

When ambient temperature is above 105°C, total IO sink current and total IO source current are limited to 36 mA combined

3. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive

injection currents of 16 contiguous pins—is 25 mA.

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General

8.3.2 LVD and POR operating requirements

Table 7. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters

Characteristic

Symbol

POR

Min

Typ

2.0

Max

Unit

V

POR Assert Voltage¹

POR Release Voltage²

LVI_2p7 Threshold Voltage

LVI_2p2 Threshold Voltage

POR

2.7

V

2.73

2.23

V

1. During 3.3-volt V_DDpower supply ramp down

2. During 3.3-volt V_DDpower supply ramp up (gated by LVI_2p7)

8.3.3 Voltage and current operating behaviors

The following table provides information about power supply requirements and I/O pin

characteristics.

Table 8. DC Electrical Characteristics at Recommended Operating Conditions

Characteristic

Output Voltage High

Output Voltage Low

Symbol

V_OH

Notes ¹

Min

V_DD- 0.5

—

Typ

—

Max

—

Unit

V

Test Conditions

I_OH= I_OHmax

Pin Group 1

V_OL

Pin Groups

1, 2

—

0.5

V

I_OL= I_OLmax

Digital Input Current High

I_IH

Pin Group 1

Pin Group 2

—

0

+/- 2.5

µA

V_IN= 2.4 V to 5.5 V

V_IN= 2.4 V to V_DD

pull-up enabled or

disabled

Comparator Input Current

High

I_IHC

I_IHOSC

I_IL

Pin Group 3

—

0

+/- 2

µA

V_IN= V_DDA

V_IN= 0V

Oscillator Input Current

High

Digital Input Current Low

Pin Groups

1, 2

—

0

+/- 0.5

2, 3

pull-up disabled

Internal Pull-Up

Resistance

R_Pull-Up

R_Pull-Down

I_ILC

20

—

0

50

kΩ

µA

V

—

Internal Pull-Down

Resistance

—

V_IN= 0V

Comparator Input Current

Low

Pin Group 3

Pin Group 5

—

+/- 2

Oscillator Input Current

Low

I_ILOSC

—

0

+/- 2

V_IN= 0V

DAC Output Voltage

Range

V_DAC

Typically

V_SSA

—

Typically

V_DDA-

R_LD= 3 kΩ || C_LD= 400 pF

+

40mV

Output Current ^{2, 3}

I_OZ

Pin Groups

1, 2

—

0

+/- 1

µA

—

High Impedance State

Table continues on the next page...

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General

Table 8. DC Electrical Characteristics at Recommended Operating Conditions (continued)

Characteristic

Symbol

Notes ¹

Min

Typ

Max

Unit

Test Conditions

Schmitt Trigger Input

Hysteresis

V_HYS

Pin Groups 0.06 × V_DD

1, 2

—

V

—

1. Default Mode

• Pin Group 1: GPIO, TDI, TDO, TMS, TCK

• Pin Group 2: RESET

• Pin Group 3: ADC and Comparator Analog Inputs

• Pin Group 4: XTAL, EXTAL

• Pin Group 5: DAC

2. See the following figure "I_IN/I_OZvs. V_IN(typical; pull-up disabled) (design simulation)" .

3. To minimize the excessive leakage ( > 1 μA) current from digital pin, input signal should NOT stay between 1.1 V and 0.9

× V_DDfor prolonged time.

V (volt)

Figure 5. I_IN/I_OZvs. V_IN(typical; pull-up disabled) (design simulation)

8.3.4 Power mode transition operating behaviors

Parameters listed are guaranteed by design.

NOTE

All address and data buses described here are internal.

Table 9. Reset, stop, wait, and interrupt timing

Characteristic

Symbol

Typical Min

Typical

Max

Unit

See

Figure

Minimum RESET Assertion Duration

t_RA

16

—

ns

—

Table continues on the next page...

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General

Table 9. Reset, stop, wait, and interrupt timing (continued)

Characteristic

Symbol

Typical Min

Typical

Max

Unit

See

Figure

RESET deassertion to First Address Fetch

t_RDA

t_IF

865 x T_OSC+ 8 x T

361.3

ns

—

Delay from Interrupt Assertion to Fetch of first

instruction (exiting Stop)

570.9

NOTE

In Table 9, T = system clock cycle and T_OSC= oscillator clock

cycle. For an operating frequency of 50MHz, T=20 ns. At 4

MHz (used coming out of reset and stop modes), T=250 ns.

Table 10. Power mode transition behavior

Symbol

Description

Min

Max

Unit

Notes

T_POR

After a POR event, the amount of delay from when V_DDreaches

2.7 V to when the first instruction executes (over the operating

temperature range).

199

225

µs

STOP mode to RUN mode

LPS mode to LPRUN mode

VLPS mode to VLPRUN mode

WAIT mode to RUN mode

6.81

240.9

1424

0.570

237.2

1413

µs

810

1459

0.620

810

LPWAIT mode to LPRUN mode

VLPWAIT mode to VLPRUN mode

1

2

1500

1. CPU clock = 200 KHz and 8 MHz IRC on standby. Exit by an interrupt on PORTC GPIO.

2. Using 64 KHz external clock; CPU Clock = 32KHz. Exit by an interrupt on PortC GPIO.

8.3.5 Power consumption operating behaviors

Table 11. Current Consumption (mA)

Mode

Maximum

Frequency

Conditions¹

Typical at

3.3 V, 25°C

Maximum

at 3.6V,

125°C

1

I_DD

I_DDAI_DD

9.9

I_DDA

RUN

50 MHz

• 50 MHz Core and Peripheral clock

• Regulators are in full regulation

• Relaxation Oscillator on

27.6

43.5 14.0

• PLL powered on

• Continuous MAC instructions with fetches from Program

Flash

• All peripheral modules enabled. TMRs and SCIs using 1X

peripheral clock

• NanoEdge within eFlexPWM using 2X peripheral clock

Table continues on the next page...

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35

General

Table 11. Current Consumption (mA) (continued)

Mode

Maximum

Frequency

Conditions¹

Typical at

3.3 V, 25°C

Maximum

at 3.6V,

125°C

1

I_DD

I_DDAI_DD

I_DDA

• ADC/DAC (only one 12-bit DAC and all 6-bit DACs)

powered on and clocked

• Comparator powered on

WAIT

50 MHz

• 50 MHz Core and Peripheral clock

• Regulators are in full regulation

• Relaxation Oscillator on

24.0

—

41.3

—

• PLL powered on

• Processor Core in WAIT state

• All Peripheral modules enabled.

• TMRs and SCIs using 1X Clock

• NanoEdge within PWMA using 2X clock

• ADC/DAC (single 12-bit DAC, all 6-bit DACs), Comparator

powered off

STOP

4 MHz

2 MHz

• 4 MHz Device Clock

• Regulators are in full regulation

• Relaxation Oscillator on

6.3

—

19.4

13.0

—

• PLL powered off

• Processor Core in STOP state

• All peripheral module and core clocks are off

• ADC/DAC/Comparator powered off

LPRUN

(LsRUN)

• 200 kHz Device Clock from Relaxation Oscillator's (ROSC) 2.8

low speed clock

3.1

4.0

• ROSC in standby mode

• Regulators are in standby

• PLL disabled

• Repeat NOP instructions

• All peripheral modules enabled, except NanoEdge and

cyclic ADCs. One 12-bit DAC and all 6-bit DACs enabled. ²

• Simple loop with running from platform instruction buffer

LPWAIT

(LsWAIT)

2 MHz

• 200 kHz Device Clock from Relaxation Oscillator's (ROSC) 2.7

low speed clock

• ROSC in standby mode

• Regulators are in standby

• PLL disabled

• All peripheral modules enabled, except NanoEdge and

cyclic ADCs. One 12-bit DAC and all 6-bit DACs enabled.²

• Processor core in wait mode

3.1

13.0

12.0

10.0

4.0

LPSTOP

(LsSTOP)

2 MHz

• 200 kHz Device Clock from Relaxation Oscillator's (ROSC) 1.2

low speed clock

• ROSC in standby mode

• Regulators are in standby

• PLL disabled

—

• Only PITs and COP enabled; other peripheral modules

disabled and clocks gated off²

• Processor core in stop mode

VLPRUN

200 kHz

• 32 kHz Device Clock

0.7

—

• Clocked by a 32 kHz external clock source

• Oscillator in power down

• All ROSCs disabled

• Large regulator is in standby

Table continues on the next page...

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NXP Semiconductors

General

Table 11. Current Consumption (mA) (continued)

Mode

Maximum

Frequency

Conditions¹

Typical at

3.3 V, 25°C

Maximum

at 3.6V,

125°C

1

I_DD

I_DDAI_DD

I_DDA

• Small regulator is disabled

• PLL disabled

• Repeat NOP instructions

• All peripheral modules, except COP and EWM, disabled

and clocks gated off

• Simple loop running from platform instruction buffer

VLPWAIT

200 kHz

• 32 kHz Device Clock

0.7

—

10.0

—

• Clocked by a 32 kHz external clock source

• Oscillator in power down

• All ROSCs disabled

• Large regulator is in standby

• Small regulator is disabled

• PLL disabled

• All peripheral modules, except COP, disabled and clocks

gated off

• Processor core in wait mode

VLPSTOP

200 kHz

• 32 kHz Device Clock

0.7

—

10.0

—

• Clocked by a 32 kHz external clock source

• Oscillator in power down

• All ROSCs disabled

• Large regulator is in standby.

• Small regulator is disabled.

• PLL disabled

• All peripheral modules, except COP, disabled and clocks

gated off

• Processor core in stop mode

1. No output switching, all ports configured as inputs, all inputs low, no DC loads.

2. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 500 kHz due to

the fixed frequency ratio of 1:2 between the CPU clock and the flash clock when running with 2 MHz external clock input

and CPU running at 1 MHz.

8.3.6 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com.

2. Perform a keyword search for “EMC design.”

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General

8.3.7 Capacitance attributes

Table 12. Capacitance attributes

Description

Symbol

C_IN

Min.

—

Typ.

10

Max.

—

Unit

pF

Input capacitance

Output capacitance

C_OUT

—

10

—

pF

8.4 Switching specifications

8.4.1 Device clock specifications

Table 13. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Notes

Normal run mode

f_SYSCLK

Device (system and core) clock frequency

• using relaxation oscillator

0.001

0

50

MHz

• using external clock source

f_BUS

Bus clock

—

8.4.2 General switching timing

Table 14. Switching timing

Symbol Description

GPIO pin interrupt pulse width¹

Min

Max

Unit

Notes

1.5

IP Bus

Clock

Cycles

2

Synchronous path

Port rise and fall time (high drive strength), slew disabled,

2.7V ≤ V_DD≤ 3.6V

5.5

1.5

8.2

3.2

15.1

6.8

ns

3

4

3

4

Port rise and fall time (high drive strength), slew enabled,

2.7V ≤ V_DD≤ 3.6V

Port rise and fall time (low drive strength), slew disabled, 2.7V

≤ V_DD≤ 3.6V

17.8

9.2

Port rise and fall time (low drive strength), slew enabled, 2.7V

≤ V_DD≤ 3.6V

1. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming

GPIOn_IPOLR and GPIOn_IENR.

2. The greater synchronous and asynchronous timing must be met.

3. 75 pF load

4. 15 pF load

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8.5 Thermal specifications

8.5.1 Thermal operating requirements

Table 15. Thermal operating requirements

Symbol

T_J

Description

Min

–40

Max

135

125

Unit

Die junction temperature

Ambient temperature

°C

T_A

8.5.2 Thermal attributes

This section provides information about operating temperature range, power dissipation,

and package thermal resistance. Power dissipation on I/O pins is usually small compared

to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-

determined rather than being controlled by the MCU design. To account for P_I/Oin power

calculations, determine the difference between actual pin voltage and V_SSor V_DDand

multiply by the pin current for each I/O pin. Except in cases of unusually high pin current

(heavy loads), the difference between pin voltage and V_SSor V_DDis very small.

See Thermal design considerations for more detail on thermal design considerations.

Board type

Symbol

Description

64 LQFP

Unit

Notes

Single-layer (1s)

R_θJA

Thermal

64

46

52

39

28

°C/W

,

resistance, junction

to ambient (natural

convection)

Four-layer (2s2p)

Single-layer (1s)

Four-layer (2s2p)

—

R_θJA

Thermal

1,

resistance, junction

to ambient (natural

convection)

R_θJMA

R_θJB

Thermal

1,2

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

resistance, junction

to board

Table continues on the next page...

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Peripheral operating requirements and behaviors

Board type

Symbol

Description

64 LQFP

Unit

Notes

—

R_θJC

Thermal

resistance, junction

to case

15

3

°C/W

Ψ_JT

Thermal

characterization

parameter, junction

to package top

outside center

(natural

convection)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions

—Forced Convection (Moving Air) with the board horizontal.

9 Peripheral operating requirements and behaviors

9.1 Core modules

9.1.1 JTAG timing

Table 16. JTAG timing

Characteristic

Symbol

Min

Max

Unit

See

Figure

TCK frequency of operation

TCK clock pulse width

f_OP

t_PW

t_DS

t_DH

t_DV

t_TS

DC

50

5

SYS_CLK/ 8

MHz

ns

Figure 6

Figure 7

—

30

TMS, TDI data set-up time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

ns

5

ns

—

ns

1/f

OP

t

PW

V

IH

V

M

TCK

(Input)

IL

V

= V + (V – V )/2

IL IH IL

M

Figure 6. Test clock input timing diagram

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TCK

(Input)

t

DH

DS

TDI

TMS

Input Data Valid

(Input)

t

DV

TDO

(Output)

Output Data Valid

t

TS

TDO

(Output)

Figure 7. Test access port timing diagram

9.2 System modules

9.2.1 Voltage regulator specifications

The voltage regulator supplies approximately 1.2 V to the device's core logic. For proper

operations, the voltage regulator requires a minimum external 2.2 µF capacitor on each

V_CAPpin with total capacitors on all V_CAPpins at a minimum of 4.4µF. Ceramic and

tantalum capacitors tend to provide better performance tolerances. The output voltage can

be measured directly on the V_CAPpin. The specifications for this regulator are shown in

Table 17.

Table 17. Regulator 1.2 V parameters

Characteristic

Output Voltage ¹

Short Circuit Current ²

Symbol

V_CAP

I_SS

Min

—

Typ

1.22

600

—

Max

—

Unit

V

—

mA

Short Circuit Tolerance (V_CAPshorted to ground)

T_RSC

—

30

minute

1. Value is after trim

2. Guaranteed by design

Table 18. Bandgap electrical specifications

Characteristic

Reference Voltage (after trim)

Symbol

Min

Typ

Max

Unit

V_REF

—

1.21¹

—

V

1. Typical value is trimmed at 25℃. There could be 50 mV variation due to temperature change.

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System modules

9.3 Clock modules

9.3.1 External clock operation timing

Parameters listed are guaranteed by design.

Table 19. External clock operation timing requirements

Characteristic

Symbol

f_osc

Min

Typ

Max

Unit

MHz

ns

Frequency of operation (external clock driver)¹

Clock pulse width²

—

50

t_PW

8

External clock input rise time³

External clock input fall time⁴

t_rise

—

1

ns

t_fall

1

—

ns

Input high voltage overdrive by an external clock

Input low voltage overdrive by an external clock

V_ih

0.85×V_DD

—

V

V_il

0.3×V_DD

V

1. See the "External clock timing" figure for details on using the recommended connection of an external clock driver.

2. The chip may not function if the high or low pulse width is smaller than 6.25 ns.

3. External clock input rise time is measured from 10% to 90%.

4. External clock input fall time is measured from 90% to 10%.

V

IH

External

Clock

90%

50%

10%

90%

50%

10%

t

V

IL

t

fall

rise

t

PW

Note: The midpoint is V + (V – V )/2.

IL

IH

IL

Figure 8. External clock timing

9.3.2 Phase-Locked Loop timing

Table 20. Phase-Locked Loop timing

Characteristic

PLL input reference frequency¹

PLL output frequency²

Symbol

f_ref

Min

8

Typ

8

Max

Unit

MHz

µs

16

400

73.2

60

f_op

200

35.5

40

—

PLL lock time³

t_plls

Allowed Duty Cycle of input reference

t_dc

50

%

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.

The PLL is optimized for 8 MHz input.

2. The frequency of the core system clock cannot exceed 50 MHz. If the NanoEdge PWM is available, the PLL output must

be set to 400 MHz.

3. This is the time required after the PLL is enabled to ensure reliable operation.

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9.3.3 External crystal or resonator requirement

Table 21. Crystal or resonator requirement

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation

f_XOSC

4

8

16

MHz

9.3.4 RC Oscillator Timing

Table 22. RC Oscillator Electrical Specifications

Characteristic

Symbol

Min

Typ

Max

Unit

8 MHz Output Frequency¹

Run Mode

0°C to 105°C

7.84

7.76

7.60

248

8

8.16

8.24

8.32

562

MHz

kHz

-40°C to 105°C

-40°C to 125°C

-40°C to 105°C

-40°C to 125°C

8

Standby Mode (IRC

trimmed @ 8 MHz)

405

198

702

kHz

8 MHz Frequency Variation over 25°C

RUN Mode

0°C to 105°C

1.5

2

3

%

-40°C to 105°C

-40°C to 125°C

-5 to +4

200 kHz Output Frequency²

RUN Mode

-40°C to 105°C

-40°C to 125°C

194

192

200

206

208

kHz

200 kHz Output Frequency Variation over 25°C

RUN Mode

0°C to 85°C

1.5

0.12

10

2

3

%

µs

%

-40°C to 105°C

-40°C to 125°C

8 MHz output³

200 kHz output⁴

4

Stabilization Time

Output Duty Cycle

tstab

-

48

50

52

1. Frequency after factory trim

2. Frequency after factory trim

3. Standby to run mode transition

4. Power down to run mode transition

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Figure 9. RC Oscillator Temperature Variation (Typical) After Trim (Preliminary)

9.4 Memories and memory interfaces

9.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

9.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are

active and do not include command overhead.

Table 23. NVM program/erase timing specifications

Symbol Description

t_hvpgm4Longword Program high-voltage time

Min.

Typ.

Max.

Unit

Notes

—

7.5

18

μs

—

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Table 23. NVM program/erase timing specifications (continued)

Symbol Description

Min.

—

Typ.

13

Max.

113

Unit

Notes

t_hversscrSector Erase high-voltage time

ms

t_hversall

Erase All high-voltage time

—

52

452

1

1. Maximum time based on expectations at cycling end-of-life.

9.4.1.2 Flash timing specifications — commands

Table 24. Flash command timing specifications

Symbol Description

Min.

—

Typ.

—

Max.

60

Unit

μs

Notes

t_rd1sec1kRead 1s Section execution time (flash sector)

1

t_pgmchk

t_rdrsrc

t_pgm4

Program Check execution time

Read Resource execution time

Program Longword execution time

Erase Flash Sector execution time

Read 1s All Blocks execution time

Read Once execution time

—

45

μs

—

30

μs

65

14

—

145

114

0.9

25

μs

—

t_ersscr

t_rd1all

ms

μs

1

t_rdonce

—

t_pgmonceProgram Once execution time

65

70

—

μs

—

2

t_ersall

Erase All Blocks execution time

575

30

ms

μs

t_vfykey

Verify Backdoor Access Key execution time

1

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

9.4.1.3 Flash high voltage current behaviors

Table 25. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

mA

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

mA

9.4.1.4 Reliability specifications

Table 26. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

—

20

100

50 K

10 K

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1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant

25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering

Bulletin EB619.

9.5 Analog

9.5.1 12-bit Cyclic Analog-to-Digital Converter (ADC) Parameters

Table 27. 12-bit ADC Electrical Specifications

Characteristic

Symbol

Min

Typ

Max

Unit

Recommended Operating Conditions

Supply Voltage

VDDA

Vrefhx

f_ADCCLK

R_AD

3

3.3

3.6

VDDA

10

V

VREFH (in external reference mode)

ADC Conversion Clock

Conversion Range

VDDA-0.6

0.1

MHz

V

V_REFH– V_REFL

V_REFH

Fully Differential

– (V_REFH– V_REFL

V_REFL

)

Single Ended/Unipolar

Input Voltage Range (per input)

External Reference

V_ADIN

V

V_REFL

0

V_REFH

V_DDA

Internal Reference

Timing and Power

Conversion Time

t_ADC

8

ADC Clock

Cycles

ADC Power-Up Time (from adc_pdn)

t_ADPU

13

ADC Clock

Cycles

ADC RUN Current (per ADC block)

I_ADRUN

1.8

0.1

mA

µA

ADC Powerdown Current (adc_pdn

enabled)

I_ADPWRDWN

V_REFHCurrent (in external mode)

Accuracy (DC or Absolute)

Integral non-Linearity

Differential non-Linearity

Monotonicity

I_VREFH

190

225

µA

INL

+/- 1.5

+/- 0.5

+/- 2.5

+/- 0.8

LSB

DNL

GUARANTEED

Offset

V_OFFSET

mV

+/- 8

Fully Differential

+/- 12

Single Ended/Unipolar

Gain Error

E_GAIN

0.996 to1.004 0.990 to 1.010

AC Specifications

Signal to Noise Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range

SNR

THD

66

75

77

dB

SFDR

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Table 27. 12-bit ADC Electrical Specifications (continued)

Characteristic

Symbol

SINAD

ENOB

Min

Typ

66

Max

Unit

dB

Signal to Noise plus Distortion

Effective Number of Bits

Gain = 1x (Fully Differential/Unipolar)

Gain = 2x (Fully Differential/Unipolar)

Gain = 4x (Fully Differential/Unipolar)

Gain = 1x (Single Ended)

Gain = 2x (Single Ended)

Gain = 4x (Single Ended)

Variation across channels

ADC Inputs

—

bits

10.6

—

10.3

10.6

10.4

10.2

0.1

Input Leakage Current

I_IN

1

nA

mV/°C

V

Temperature sensor slope

Temperature sensor voltage at 25 °C

Disturbance

T_SLOPE

V_TEMP25

1.3

0.82

Input Injection Current

I_INJ

+/-3

mA

dB

pF

Channel to Channel Crosstalk

Memory Crosstalk

ISOXTLK

MEMXTLK

C_ADI

-82

-71

Input Capacitance

4.8

Sampling Capacitor

9.5.1.1 Equivalent circuit for ADC inputs

The following figure shows the ADC input circuit during sample and hold. S1 and S2 are

always opened/closed at non-overlapping phases, and both S1 and S2 are dependent on

the ADC clock frequency. The following equation gives equivalent input impedance

when the input is selected.

1

100 ohm

+

ohm

50

+

-12

(ADC ClockRate) x 4.8x10

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C1

Channel Mux

equivalent resistance

100Ohms

S1

50  ESD

Resistor

Analog Input

C1

S1

S/H

1

2

S1

S2

(V_REFHx- V_REFLx) / 2

C1

1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =

1.8pF

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal

routing = 2.04pF

3. S1 and S2 switch phases are non-overlapping and depend on the ADC clock

frequency

S1

S2

Figure 10. Equivalent circuit for A/D loading

9.5.2 12-bit Digital-to-Analog Converter (DAC) parameters

Table 28. DAC parameters

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

DC Specifications

Resolution

12

—

12

1

12

bits

µs

Settling time

At output load

RLD = 3 kΩ

CLD = 400 pF

Power-up time

Time from release of PWRDWN

signal until DACOUT signal is valid

t_DAPU

—

11

µs

Accuracy

INL

Integral non-linearity

Range of input digital words:

410 to 3891 ($19A - $F33)

5% to 95% of full range

+/- 3

+/- 4

LSB

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Table 28. DAC parameters (continued)

Parameter

Conditions/Comments

Range of input digital words:

410 to 3891 ($19A - $F33)

5% to 95% of full range

Symbol

Min

Typ

Max

Unit

Differential non-linearity

DNL

—

+/- 0.8

+/- 0.9

LSB

Monotonicity

Offset error

> 6 sigma monotonicity,

< 3.4 ppm non-monotonicity

Range of input digital words:

410 to 3891 ($19A - $F33)

5% to 95% of full range

guaranteed

+/- 25

—

V_OFFSET

—

+ /- 47

+/- 1.5

mV

Gain error

Range of input digital words: 410 to

3891 ($19A - $F33) 5% to 95% of

full range

E_GAIN

+/- 0.5

—

%

V

DAC Output

Output voltage range Within 40 mV of either V_SSAor V_DDA

V_OUT

V_SSA

0.04 V

+

V_DDA- 0.04

V

AC Specifications

SNR

Signal-to-noise ratio

—

85

—

dB

Spurious free dynamic

range

SFDR

-72

Effective number of bits

ENOB

—

11

—

bits

9.5.3 CMP and 6-bit DAC electrical specifications

Table 29. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

2.7

—

Typ.

—

Max.

3.6

—

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

300

36

μA

V

—

V_SS

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis

• CR0[HYSTCTR] = 00¹

—

mV

V_H

—

5

13

48

mV

• CR0[HYSTCTR] = 01

25

55

80

• CR0[HYSTCTR] = 10²

105

148

• CR0[HYSTCTR] = 11²

V_CMPOh

V_CMPOl

t_DHS

Output high

Output low

V_DD– 0.5

—

25

—

0.5

50

V

—

Propagation delay, high-speed mode (EN=1,

PMODE=1)

ns

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Table 29. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

t_DLS

Propagation delay, low-speed mode (EN=1,

PMODE=0)³

—

60

200

ns

Analog comparator initialization delay⁴

—

40

7

—

μs

μA

V

I_DAC6b

6-bit DAC current adder (enabled)

6-bit DAC reference inputs, Vin1 and Vin2

V_DDA

—

V_DD

There are two reference input options selectable (via

VRSEL control bit). The reference options must fall

within this range.

INL

6-bit DAC integral non-linearity

6-bit DAC differential non-linearity

–0.5

–0.3

—

0.5

0.3

LSB⁵

LSB

DNL

1. Measured with input voltage range limited to 0 to V_DD

2. Measured with input voltage range limited to 0.7≤Vin≤V_DD-0.8

3. Input voltage range: 0.1V_DD≤Vin≤0.9V_DD,step = 100mV, across all temperature. Does not include PCB and PAD delay.

4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,

VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.

5. 1 LSB = V_reference/64

0.08

0.07

0.06

HYSTCTR

Setting

0.05

00

0.04

01

10

11

0.03

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 11. Typical hysteresis vs. Vin level (V_DD= 3.3 V, PMODE = 0)

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Timer

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 12. Typical hysteresis vs. Vin level (V_DD= 3.3 V, PMODE = 1)

9.6 Timer

9.6.1 Quad Timer timing

Parameters listed are guaranteed by design.

Table 30. Timer timing

Characteristic

Timer input period

Symbol

P_IN

Min¹

2T + 10

1T + 5

2T-2

Max

—

Unit

ns

See Figure

Figure 13

Timer input high/low period

Timer output period

P_INHL

P_OUT

—

ns

—

ns

Timer output high/low period

P_OUTHL

1T-2

—

ns

1. T = clock cycle. For 50 MHz operation, T = 20 ns.

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Timer

Timer Inputs

P

INHL

P

IN

Timer Outputs

P

OUTHL

P

OUT

Figure 13. Timer timing

9.7 Communication interfaces

9.7.1 Queued Serial Peripheral Interface (SPI) timing

Parameters listed are guaranteed by design.

Table 31. SPI timing

Characteristic

Cycle time

Master

Symbol

Min

Max

Unit

See Figure

Figure 14

Figure 15

Figure 16

Figure 17

t_C

60

—

ns

Slave

Enable lead time

Master

t_ELD

t_ELG

t_CH

—

ns

20

Slave

Enable lag time

Master

Figure 17

—

ns

20

Slave

Clock (SCK) high time

Master

Figure 14

Figure 15

Figure 16

Figure 17

—

ns

Slave

Clock (SCK) low time

t_CL

28

—

ns

Master

Slave

Data set-up time required for inputs

Master

t_DS

Figure 14

Figure 15

20

—

ns

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Timer

Table 31. SPI timing (continued)

Characteristic

Symbol

Min

Max

Unit

See Figure

Slave

1

—

ns

Figure 16

Figure 17

Figure 14

Data hold time required for inputs

t_DH

1

3

—

ns

Master

Slave

Figure 15

Figure 16

Figure 17

Access time (time to data active

from high-impedance state)

t_A

5

—

ns

Slave

Disable time (hold time to high-

impedance state)

t_D

Figure 17

Slave

Data valid for outputs

Master

t_DV

Figure 14

Figure 15

Figure 16

Figure 17

Figure 14

Figure 15

Figure 16

Figure 17

Figure 14

Figure 15

Figure 16

Figure 17

Figure 14

Figure 15

Figure 16

Figure 17

—

ns

Slave (after enable edge)

Data invalid

Master

t_DI

t_R

t_F

0

—

ns

Slave

Rise time

Master

Slave

—

1

ns

Fall time

Master

Slave

—

1

ns

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Timer

SS

(Input)

SS is held high on master

t

C

t

R

t

F

t

CL

SCLK (CPOL = 0)

(Output)

t

CH

t

F

t

R

t

CL

SCLK (CPOL = 1)

(Output)

t

DH

CH

t

DS

MISO

(Input)

MSB in

t

Bits 14–1

LSB in

t (ref)

DI

t

DI

DV

MOSI

(Output)

Master MSB out

Bits 14–1

Master LSB out

t

R

F

Figure 14. SPI master timing (CPHA = 0)

SS

(Input)

SS is held High on master

t

C

t

F

t

R

t

CL

SCLK (CPOL = 0)

(Output)

t

CH

t

F

t

CL

SCLK (CPOL = 1)

(Output)

t

CH

t

DS

t

R

t

DH

MISO

(Input)

MSB in

t

Bits 14–1

LSB in

t

(ref)

DI

t

DV

t (ref)

DV

DI

MOSI

(Output)

Master MSB out

Bits 14– 1

Master LSB out

t

R

F

Figure 15. SPI master timing (CPHA = 1)

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Timer

SS

(Input)

t

C

t

F

t

ELG

t

CL

t

R

SCLK (CPOL = 0)

(Input)

t

CH

t

ELD

t

CL

SCLK (CPOL = 1)

(Input)

t

CH

t

F

t

A

R

t

D

MISO

(Output)

Slave MSB out

Bits 14–1

Slave LSB out

t

DS

DV

t

DI

t

DH

MOSI

(Input)

MSB in

Bits 14–1

LSB in

Figure 16. SPI slave timing (CPHA = 0)

SS

(Input)

t

F

t

C

t

R

t

CL

SCLK (CPOL = 0)

(Input)

t

CH

t

ELG

t

ELD

t

CL

SCLK (CPOL = 1)

(Input)

t

DV

CH

t

R

t

D

t

A

F

MISO

(Output)

Slave MSB out

Bits 14–1

Slave LSB out

t

DV

DS

t

DI

t

DH

MOSI

(Input)

MSB in

Bits 14–1

LSB in

Figure 17. SPI slave timing (CPHA = 1)

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Timer

9.7.2 Queued Serial Communication Interface (SCI) timing

Parameters listed are guaranteed by design.

Table 32. SCI timing

Characteristic

Baud rate¹

Symbol

BR

Min

—

Max

Unit

Mbit/s

μs

See Figure

—

(f_MAX/16)

1.04/BR

RXD pulse width

TXD pulse width

RXD_PW

TXD_PW

0.965/BR

Figure 18

Figure 19

μs

LIN Slave Mode

Deviation of slave node clock from nominal F_{TOL_UNSYNCH}

clock rate before synchronization

-14

14

2

%

—

Deviation of slave node clock relative to

the master node clock after

synchronization

F_{TOL_SYNCH}

-2

Minimum break character length

T_BREAK

13

11

—

Master

node bit

periods

—

Slave node

bit periods

1. f_MAXis the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.)50 MHz.

RXD

SCI receive

data pin

RXD

PW

(Input)

Figure 18. RXD pulse width

TXD

SCI transmit

data pin

TXD

PW

(output)

Figure 19. TXD pulse width

9.7.3 Modular/Scalable Controller Area Network (MSCAN)

Table 33. MSCAN Timing Parameters

Characteristic

Baud Rate

Symbol

BR_CAN

Min

—

5

Max

1

Unit

Mbit/s

µs

CAN Wakeup dominant pulse filtered

CAN Wakeup dominant pulse pass

T_WAKEUP

1.5

—

µs

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Timer

CAN_RX

CAN receive

data pin

T

WAKEUP

(Input)

Figure 20. Bus Wake-up Detection

NOTE

CAN wakeup is not supported when ROSC_8M is in standby

mode.

9.7.4 Inter-Integrated Circuit Interface (I²C) timing

Table 34. I ²C timing

Characteristic

Symbol

Standard Mode

Minimum Maximum

100

Fast Mode

Unit

Minimum

Maximum

400

SCL Clock Frequency

f_SCL

0

kHz

µs

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD; STA

4

—

0.6

—

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

4

—

1.3

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

Data hold time for I²C bus devices

t_HD; DAT

t_SU; DAT

t_r

0

3.45

—

0

100²

0.9¹

—

µs

ns

Data set-up time

250

—

3,

Rise time of SDA and SCL signals

1000

20 +0.1C_b

300

4

Fall time of SDA and SCL signals

Set-up time for STOP condition

t_f

—

300

20 +0.1C_b

300

ns

4

t_SU; STO

t_BUF

4

—

0.6

1.3

—

µs

Bus free time between STOP and

START condition

4.7

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

0

50

ns

1. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL

lines.

2. The maximum t_HD; DAT must be met only if the device does not stretch the LOW period (t_LOW) of the SCL signal.

3. A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement t_{SU; DAT}≥ 250 ns must

then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax+ t_{SU; DAT}

= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is released.

4. C_b= total capacitance of the one bus line in pF.

MC56F82348, Rev. 2, 07/2020

NXP Semiconductors

57

Design Considerations

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

S

SR

P

S

t_{HD; DAT}

t_HIGH

Figure 21. Timing definition for fast and standard mode devices on the I²C bus

10 Design Considerations

10.1 Thermal design considerations

An estimate of the chip junction temperature (T_J) can be obtained from the equation:

T_J= T_A+ (R_ΘJA× P_D)

where

T_A= Ambient temperature for the package (°C)

R_ΘJA= Junction-to-ambient thermal resistance (°C/W)

P_D= Power dissipation in the package (W).

The junction-to-ambient thermal resistance is an industry-standard value that provides a

quick and easy estimation of thermal performance. Unfortunately, there are two values in

common usage: the value determined on a single-layer board and the value obtained on a

board with two planes. For packages such as the PBGA, these values can be different by

a factor of two. Which T_Jvalue is closer to the application depends on the power

dissipated by other components on the board.

• The T_Jvalue obtained on a single layer board is appropriate for a tightly packed

printed circuit board.

• The T_Jvalue obtained on a board with the internal planes is usually appropriate if the

board has low-power dissipation and if the components are well separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-

case thermal resistance and a case-to-ambient thermal resistance:

R_ΘJA= R_ΘJC+ R_ΘCA

where

MC56F82348, Rev. 2, 07/2020

58

NXP Semiconductors

Design Considerations

R_ΘJA= Package junction-to-ambient thermal resistance (°C/W)

R_ΘJC= Package junction-to-case thermal resistance (°C/W)

R_ΘCA= Package case-to-ambient thermal resistance (°C/W).

R_ΘJCis device related and cannot be adjusted. You control the thermal environment to

change the case to ambient thermal resistance, R_ΘCA. For instance, you can change the

size of the heat sink, the air flow around the device, the interface material, the mounting

arrangement on printed circuit board, or change the thermal dissipation on the printed

circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat

sinks are not used, the thermal characterization parameter (Ψ_JT) can be used to

determine the junction temperature with a measurement of the temperature at the top

center of the package case using the following equation:

T_J= T_T+ (Ψ_JT× P_D)

where

T_T= Thermocouple temperature on top of package (°C/W)

Ψ_JT= hermal characterization parameter (°C/W)

P_D= Power dissipation in package (W).

The thermal characterization parameter is measured per JESD51–2 specification using a

40-gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over

about 1 mm of wire extending from the junction. The thermocouple wire is placed flat

against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

To determine the junction temperature of the device in the application when heat

sinks are used, the junction temperature is determined from a thermocouple inserted at

the interface between the case of the package and the interface material. A clearance slot

or hole is normally required in the heat sink. Minimizing the size of the clearance is

important to minimize the change in thermal performance caused by removing part of the

thermal interface to the heat sink. Because of the experimental difficulties with this

technique, many engineers measure the heat sink temperature and then back-calculate the

case temperature using a separate measurement of the thermal resistance of the interface.

From this case temperature, the junction temperature is determined from the junction-to-

case thermal resistance.

MC56F82348, Rev. 2, 07/2020

NXP Semiconductors

59

Design Considerations

10.2 Electrical design considerations

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields. However,

take normal precautions to avoid application of any voltages

higher than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation of the device:

• Provide a low-impedance path from the board power supply to each V_DDpin on the

device and from the board ground to each V_SS(GND) pin.

• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as

near as possible to the package supply pins. The recommended bypass configuration

is to place one bypass capacitor on each of the V_DD/V_SSpairs, including V_DDA/V_SSA

Ceramic and tantalum capacitors tend to provide better tolerances.

.

• Ensure that capacitor leads and associated printed circuit traces that connect to the

chip V_DDand V_SS(GND) pins are as short as possible.

• Bypass the V_DDand V_SSwith approximately 100 µF, plus the number of 0.1 µF

ceramic capacitors.

• PCB trace lengths should be minimal for high-frequency signals.

• Consider all device loads as well as parasitic capacitance due to PCB traces when

calculating capacitance. This is especially critical in systems with higher capacitive

loads that could create higher transient currents in the V_DDand V_SScircuits.

• Take special care to minimize noise levels on the V_REF, V_DDA, and V_SSApins.

• Using separate power planes for V_DDand V_DDAand separate ground planes for V_SS

and V_SSAare recommended. Connect the separate analog and digital power and

ground planes as near as possible to power supply outputs. If an analog circuit and

digital circuit are powered by the same power supply, then connect a small inductor

or ferrite bead in serial with V_DDA. Traces of V_SSand V_SSAshould be shorted

together.

• Physically separate analog components from noisy digital components by ground

planes. Do not place an analog trace in parallel with digital traces. Place an analog

ground trace around an analog signal trace to isolate it from digital traces.

• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,

or I²C, the designer should provide an interface to this port if in-circuit flash

programming is desired.

• If desired, connect an external RC circuit to the RESET pin. The resistor value

should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of

0.1 µF–4.7 µF.

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60

NXP Semiconductors

Design Considerations

• Configuring the RESET pin to GPIO output in normal operation in a high-noise

environment may help to improve the performance of noise transient immunity.

• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a

reset state during normal operation if JTAG converter is not present. Furthermore,

configure TMS, TDI, TDO and TCK to GPIO if operation environment is very noisy.

• During reset and after reset but before I/O initialization, all the GPIO pins are at tri-

state.

• To eliminate PCB trace impedance effect, each ADC input should have a no less than

33 pF 10Ω RC filter.

10.3 Power-on Reset design considerations

10.3.1 Improper power-up sequence between VDD/VSS and VDDA/

VSSA:

It is recommended that VDD be kept within 100 mV of VDDA at all times, including

power ramp-up and ramp-down. Failure to keep VDD within 100 mV of VDDA may

cause a leakage current through the substrate, between the VDD and VDDA pad cells.

This leakage current could prevent operation of the device after it powers up. The voltage

difference between VDD and VDDA must be limited to below 0.3 V at all times, to avoid

permanent damage to the part (See Table 5). Also see Table 6.

10.3.2 Unnecessary protection circuit:

In many circuit designs, it is a general practice to add external clamping diodes on each

analog input pin; see diode D1 and D2 in Figure 22, to prevent the surge voltage from

damaging the analog input.

MC56F82348, Rev. 2, 07/2020

NXP Semiconductors

61

Design Considerations

Reg3

DC

Reg1

DC

3.3V

12V

200V ~300V

+

DC

C4

C2

C3

C5

C6

Reg2

DC

C1

R6

R5

R4

VDD

VDDA

MC56F8xxxx

ADC_IN

R2

D1

D2

R1

C7

C8

R3

RESET

VSS

+

D1 and D2 are unnecessary,

because all analog

VSSA

inputs already have the

internal current injection

protection circuit.

Figure 22. Protection Circuit Example

This device uses the 5V tolerance I/O. When the pin is configured to digital input, it can

accept 5V input. See Table 5. When the pin is configured to analog input, the internal

integrated current injection protection circuit is enabled. The current injection protection

circuit performs the same functions as external clamp diode D1 and D2 in Figure 22. As

long as the source or sink current for each analog pin is less than 3 mA, then there is no

damage to the device. See Table 27. Therefore, D1 and D2 clamping diodes are not

recommended to be used.

10.3.3 Heavy capacitive load on power supply output:

In some applications, the low cost DC/DC converter may not regulate the output voltage

well before it reaches the regulation point, which is roughly around 2.5V to 2.7V.

However, the device might exit power-on reset at around 2.3V. If the initialization code

enables the PLL to run the DSC at full speed right after reset, then the high current will

be pulled by DSC from the supply, which can cause the supply voltage to drop below the

operation voltage; see the captured graph (Figure 23). This can cause the DSC fail to start

up.

MC56F82348, Rev. 2, 07/2020

62

NXP Semiconductors

Obtaining package dimensions

Figure 23. Supply Voltage Drop

A recommended initialization sequence during power-up is:

1. After POR is released, run a few hundred NOP instructions from the internal

relaxation oscillator; this gives time for the supply voltage to stabilize.

2. Configure the peripherals (except the ADC) to the desired settings; the ADC should

stay in low power mode.

3. Power up the PLL.

4. After the PLL locks, switch the clock from PLL prescale to postscale.

5. Configure the ADC.

11 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing's document number:

Drawing for package

Document number to be used

64-pin LQFP

98ASS23234W

12 Pinout

MC56F82348, Rev. 2, 07/2020

NXP Semiconductors

63

Pinout

12.1 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The SIM's GPS registers are responsible

for selecting which ALT functionality is available on most pins.

NOTE

• The RESETB pin is a 3.3 V pin only.

• If the GPIOC1 pin is used as GPIO, the XOSC should be

powered down.

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

LQFP

1

TCK

GPIOD2

GPIOD4

EXTAL

XTAL

TXD0

RXD0

TA0

2

RESETB

GPIOC0

GPIOC1

GPIOC2

GPIOF8

GPIOC3

GPIOC4

GPIOA7

GPIOA6

GPIOA5

GPIOA4

GPIOA0

GPIOA1

GPIOA2

GPIOA3

GPIOB7

GPIOC5

GPIOB6

GPIOB5

GPIOB4

VDDA

RESETB

GPIOC0

GPIOC1

GPIOC2

GPIOF8

GPIOC3

GPIOC4

GPIOA7

GPIOA6

GPIOA5

GPIOA4

GPIOA0

GPIOA1

GPIOA2

GPIOA3

GPIOB7

GPIOC5

GPIOB6

GPIOB5

GPIOB4

VDDA

3

CLKIN0

4

5

XB_OUT11

XB_OUT10

CMPA_O

XB_IN2

CLKO0

6

PWM_2X

CLKIN1

7

RXD0

8

TA1

CMPB_O

XB_IN6

EWM_OUT_B

9

ANA7

ANA6

ANA5

ANA4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

ANA0&CMPA_IN3

ANA1&CMPA_IN0

ANA2&VREFHA&CMPA_IN1

ANA3&VREFLA&CMPA_IN2

ANB7&CMPB_IN2

DACA_O

CMPC_O

XB_IN7

ANB6&CMPB_IN1

ANB5&CMPC_IN2

ANB4&CMPC_IN1

VSSA

GPIOB0

GPIOB1

VCAP

GPIOB0

GPIOB1

VCAP

ANB0&CMPB_IN3

ANB1&CMPB_IN0

DACB_O

GPIOB2

GPIOB3

VDD

GPIOB2

GPIOB3

VDD

ANB2&VERFHB&CMPC_IN3

ANB3&VREFLB&CMPC_IN0

VSS

GPIOC6

TA2

XB_IN3

CMP_REF

SS0_B

MC56F82348, Rev. 2, 07/2020

64

NXP Semiconductors

Pinout

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

LQFP

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

GPIOC7

GPIOC8

GPIOC9

GPIOC10

GPIOF0

GPIOC11

GPIOC12

GPIOF2

GPIOF3

GPIOF4

GPIOF5

VSS

GPIOC7

GPIOC8

GPIOC9

GPIOC10

GPIOF0

GPIOC11

GPIOC12

GPIOF2

GPIOF3

GPIOF4

GPIOF5

VSS

SS0_B

MISO0

SCLK0

MOSI0

XB_IN6

TXD0

XB_IN8

XB_IN9

TXD0

RXD0

XB_OUT6

XB_OUT8

XB_OUT9

XB_IN4

XB_IN5

MISO0

SCL0

TXD1

RXD1

SDA0

SCL0

SDA0

TXD1

RXD1

XB_OUT6

XB_OUT7

XB_OUT8

XB_OUT9

PWM_0X

PWM_1X

PWM_FAULT6

PWM_FAULT7

VDD

GPIOE0

GPIOE1

GPIOE2

GPIOE3

GPIOC13

GPIOF1

GPIOE4

GPIOE5

GPIOE6

GPIOE7

GPIOC14

GPIOC15

VCAP

GPIOE0

GPIOE1

GPIOE2

GPIOE3

GPIOC13

GPIOF1

GPIOE4

GPIOE5

GPIOE6

GPIOE7

GPIOC14

GPIOC15

VCAP

PWM_0B

PWM_0A

PWM_1B

PWM_1A

TA3

XB_IN6

XB_IN7

XB_IN2

XB_IN3

XB_IN4

XB_IN5

XB_OUT4

XB_OUT5

EWM_OUT_B

CLKO1

PWM_2B

PWM_2A

PWM_3B

PWM_3A

SDA0

PWM_FAULT4

PWM_FAULT5

SCL0

GPIOF6

GPIOF7

VDD

GPIOF6

GPIOF7

VDD

PWM_3X

CMPC_O

XB_IN2

XB_IN3

VSS

TDO

GPIOD1

GPIOD3

GPIOD0

TMS

TDI

12.2 Pinout diagrams

The following diagrams show pinouts for the packages. For each pin, the diagrams show

the default function. However, many signals may be multiplexed onto a single pin.

MC56F82348, Rev. 2, 07/2020

NXP Semiconductors

65

Product documentation

TCK

RESETB

GPIOC0

GPIOC1

GPIOC2

GPIOF8

GPIOC3

GPIOC4

GPIOA7

GPIOA6

GPIOA5

GPIOA4

GPIOA0

GPIOA1

GPIOA2

GPIOA3

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

GPIOE3

GPIOE2

GPIOE1

GPIOE0

VDD

2

3

4

5

6

VSS

7

GPIOF5

GPIOF4

GPIOF3

GPIOF2

GPIOC12

GPIOC11

GPIOF0

GPIOC10

GPIOC9

GPIOC8

8

9

10

11

12

13

14

15

16

Figure 24. 64-pin LQFP

NOTE

The RESETB pin is a 3.3 V pin only.

13 Product documentation

The documents listed in Table 35 are required for a complete description and proper

design with the device. Documentation is available from local NXP distributors, NXP

sales offices, or online at nxp.com.

Table 35. Device documentation

Topic

Description

Document Number

DSP56800E/DSP56800EX

Reference Manual

Detailed description of the 56800EX family architecture, 32-bit

digital signal controller core processor, and the instruction set

DSP56800ERM

Reference Manual

Detailed functional description and programming model

MC56F827XXRM

Table continues on the next page...

MC56F82348, Rev. 2, 07/2020

66

NXP Semiconductors

Revision History

Table 35. Device documentation (continued)

Topic

Description

Document Number

MC56F82348MLH Data Sheet

Electrical and timing specifications, pin descriptions, and

package information (this document)

MC56F82348

MC56F82xxx Errata

Details any chip issues that might be present

MC56F82xxx_Errata

14 Revision History

The following table summarizes changes to this document since the release of the

previous version.

Table 36. Revision History

Rev. No.

Date

Substantial Changes

1

1.1

2

10/2013

11/2013

07/2020

First public release

In Table 2, added DACB_O signal description

Some updates, for a new public release.

• Some clarifications in sections "12-bit Analog-to-Digital Converter (Cyclic type)",

"Queued Serial Peripheral Interface (QSPI) modules", "Power supervisor" and

"Electrical design considerations".

• Added new sections "External Watchdog Monitor (EWM)" and "Power-on Reset design

considerations".

• Minor update in the table "Signal descriptions".

• Some updates in sections "Voltage and current operating ratings", "Voltage and current

operating requirements", "Voltage and current operating behaviors", the tables "12-bit

ADC Electrical Specifications" and "SCI timing".

MC56F82348, Rev. 2, 07/2020

NXP Semiconductors

67

Information in this document is provided solely to enable system and software implementers to use

NXP products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits based on the information in this document. NXP reserves the right to

make changes without further notice to any products herein.

How to Reach Us:

Home Page:

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Web Support:

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particular purpose, nor does NXP assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets

and/or specifications can and do vary in different applications, and actual performance may vary over

time. All operating parameters, including "typicals," must be validated for each customer application

by customer's technical experts. NXP does not convey any license under its patent rights nor the

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found at the following address: nxp.com/SalesTermsandConditions.

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vulnerabilities. Customers are responsible for the design and operation of their applications and

products to reduce the effect of these vulnerabilities on customer's applications and products, and

NXP accepts no liability for any vulnerability that is discovered. Customers should implement

appropriate design and operating safeguards to minimize the risks associated with their applications

and products.

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Document Number MC56F82348MLH

Revision 2, 07/2020


型号：	MC56F82348MLH
厂家：	NXP
描述：	This family of digital signal controllers (DSCs) is based on the 32-bit 56800EX core.
文件：	总68页 (文件大小：1106K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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