MC56F84550VLFR [NXP]
32-bit DSC, 56800EX core, 96KB Flash, 80MHz, QFP 48;型号: | MC56F84550VLFR |
厂家: | NXP |
描述: | 32-bit DSC, 56800EX core, 96KB Flash, 80MHz, QFP 48 时钟 微控制器 外围集成电路 |
文件: | 总79页 (文件大小:1263K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: MC56F8455X
Rev. 3, 06/2014
Freescale Semiconductor
Data Sheet: Technical Data
MC56F8455X
MC56F8455X / MC56F8454X
Supports the 56F84553VLH,
56F84550VLF, 56F84543VLH,
56F84540VLF
Features
Analog
•
•
•
This family of digital signal controllers (DSCs) is
based on the 32-bit 56800EX core. Each device
combines, on a single chip, the processing power of a
DSP and the functionality of an MCU with a flexible
set of peripherals to support many target applications:
– Industrial control
– Two high-speed, 8-channel, 12-bit ADCs with
dynamic x2, x4 programmable amplifier
– One 20-channel, 16-bit ADC
– Up to four analog comparators with integrated 6-bit
DAC references
•
– One 12-bit DAC
– Home appliances
– Smart sensors
– Fire and security systems
– Switched-mode power supply and power
management
– Uninterruptible Power Supply (UPS)
– Solar and wind power generator
– Power metering
– Motor control (ACIM, BLDC, PMSM, SR, stepper)
– Handheld power tools
PWMs and timers
– One eFlexPWM module with up to 9 PWM outputs,
including 8 channels with high resolution NanoEdge
placement
– Two 16-bit quad timer (2 x 4 16-bit timers)
– Two Periodic Interval Timers (PITs)
– Two Programmable Delay Blocks (PDBs)
Communication interfaces
– Two high-speed queued SCI (QSCI) modules with
LIN slave functionality
– Two queued SPI (QSPI) modules
– Two SMBus-compatible I2C ports
– One flexible controller area network (FlexCAN)
module
– Circuit breaker
– Medical device/equipment
– Instrumentation
– Lighting
DSC based on 32-bit 56800EX core
– Up to 80 MIPS at 80 MHz core frequency
– DSP and MCU functionality in a unified, C-efficient
architecture
•
•
Security and integrity
•
•
•
– Cyclic Redundancy Check (CRC) generator
– Computer operating properly (COP) watchdog
– External Watchdog Monitor (EWM)
On-chip memory
– Up to 128 KB (96 KB + 32 KB) flash memory,
including up to 32 KB FlexNVM
Clocks
– Two on-chip relaxation oscillators: 8 MHz (400 kHz
at standby mode) and 32 kHz
– Crystal / resonator oscillator
– Up to 16 KB RAM
– Up to 2 KB FlexRAM with EEE capability
– 80 MHz program execution from both internal flash
memory and RAM
– On-chip flash memory and RAM can be mapped
into both program and data memory spaces
System
– DMA controller
– Integrated power-on reset (POR) and low-voltage
interrupt (LVI) and brown-out reset module
– Inter-module crossbar connection
– JTAG/enhanced on-chip emulation (EOnCE) for
unobtrusive, real-time debugging
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2014 Freescale Semiconductor, Inc.
Operating characteristics
– Single supply: 3.0 V to 3.6 V
– 5 V–tolerant I/O (except RESETB pin)
•
•
LQFP packages:
– 48-pin
– 64-pin
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
2
Freescale Semiconductor, Inc.
Table of Contents
1
Overview.................................................................................4
7
Ratings....................................................................................33
1.1 MC56F844xx/5xx/7xx product family............................4
1.2 56800EX 32-bit Digital Signal Controller (DSC) core....5
1.3 Operation parameters...................................................6
1.4 On-chip memory and memory protection......................6
1.5 Interrupt Controller........................................................7
1.6 Peripheral highlights......................................................7
1.7 Block diagrams..............................................................13
MC56F8455x signal and pin descriptions...............................16
Signal groups..........................................................................26
Ordering parts.........................................................................27
4.1 Determining valid orderable parts.................................27
Part identification.....................................................................27
5.1 Description....................................................................27
5.2 Format...........................................................................27
5.3 Fields.............................................................................28
5.4 Example........................................................................28
Terminology and guidelines....................................................28
6.1 Definition: Operating requirement.................................28
6.2 Definition: Operating behavior.......................................29
6.3 Definition: Attribute........................................................29
6.4 Definition: Rating...........................................................30
6.5 Result of exceeding a rating..........................................30
6.6 Relationship between ratings and operating
7.1 Thermal handling ratings...............................................33
7.2 Moisture handling ratings..............................................33
7.3 ESD handling ratings.....................................................33
7.4 Voltage and current operating ratings...........................34
General...................................................................................35
8.1 General characteristics..................................................35
8.2 AC electrical characteristics..........................................35
8.3 Nonswitching electrical specifications...........................36
8.4 Switching specifications................................................42
8.5 Thermal specifications...................................................43
Peripheral operating requirements and behaviors..................44
9.1 Core modules................................................................44
9.2 System modules............................................................46
9.3 Clock modules...............................................................46
9.4 Memories and memory interfaces.................................49
9.5 Analog...........................................................................52
9.6 PWMs and timers..........................................................61
9.7 Communication interfaces.............................................62
8
2
3
4
9
5
6
10 Design Considerations............................................................68
10.1 Thermal design considerations.....................................68
10.2 Electrical design considerations....................................70
11 Obtaining package dimensions...............................................71
12 Pinout......................................................................................72
12.1 Signal Multiplexing and Pin Assignments......................72
12.2 Pinout diagrams............................................................74
13 Product documentation...........................................................77
14 Revision history.......................................................................77
requirements.................................................................30
6.7 Guidelines for ratings and operating requirements.......31
6.8 Definition: Typical value................................................31
6.9 Typical value conditions................................................32
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
3
Overview
1 Overview
1.1 MC56F844xx/5xx/7xx product family
The following table lists major features, including features that differ among members of
the family. Features not listed are shared by all members of the family.
Table 1. 56F844xx/5xx/7xx family
Part
MC56F84
Number
789 786 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441
Core freq. 100 100 100 100 100 80
(MHz)
80
80
80
80
80
80
80
60
60
60
60
60
Flash
memory
(KB)
256 256 128 128 128 96
96
64
64 256 256 128 128 128 96
96
64
64
FlevNVM/ 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2
FlexRAM
(KB)
Total flash 288 288 160 160 160 128 128 96
96 288 288 160 160 160 128 128 96
96
memory
(KB)1
RAM (KB) 32
32
24
24
24
16
16
8
8
32
32
24
24
24
16
16
8
8
Memory
resource
protection
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
External
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Watchdog
12-bit
2x8 2x8 2x8 2x8 2x8 2x8 2x5 2x8 2x5 2x8 2x8 2x8 2x8 2x8 2x8 2x5 2x8 2x5
Cyclic ADC
Channels
(ADCA and
ADCB)
12-bit
300 300 300 300 300 300 300 300 300 600 600 600 600 600 600 600 600 600
Cyclic ADC ns
Conversion
time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(ADCA and
ADCB)
16-bit SAR 16
ADC (with
Temperatu
re Sensor)
channels
10
16
10
8
8
̶
8
̶
16
10
16
10
̶
8
̶
8
̶
(ADCC)
PWMA
High-res
channels
8
8
8
8
8
8
6
8
6
0
0
0
0
0
0
0
0
0
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
4
Freescale Semiconductor, Inc.
Overview
Table 1. 56F844xx/5xx/7xx family (continued)
Part
MC56F84
Number
789 786 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441
PWMA Std
channels
4
1
4
1
1
1
0
1
0
12
12
12
12
9
9
6
9
6
PWMA
Input
12
9
12
9
9
9
6
9
6
12
12
12
12
9
9
6
9
6
capture
channels
PWMB Std 12
channels
9 2
7
12
12
9 2
7
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
12
12
9 2
7
12
12
9 2
7
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
PWMB
Input
12
capture
channels
12-bit DAC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
̶
̶
1
1
̶
̶
̶
̶
Quad
1
1
1
1
1
1
Decoder
DMA
CMP
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
4
3
3
2
1
4
3
2
2
1
4
3
3
2
1
4
3
2
2
1
4
2
4
2
3
2
4
2
3
2
1
2
1
4
3
3
2
1
4
3
2
2
1
4
3
3
2
1
4
3
2
2
1
4
2
4
2
3
2
4
2
3
2
QSCI
QSPI
1
1
1
1
1
1
1
1
1
I2C/SMBus
FlexCAN
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
0
0
LQFP
100 80 100 80
64
64
48
64
48 100 80 100 80
64
64
48
64
48
package
pin count
1. This total includes FlexNVM and assumes no FlexNVM is used with FlexRAM for EEPROM.
2. The outputs of PWMB_3A and PWM_3B are available through the on-chip inter-module crossbar.
1.2 56800EX 32-bit Digital Signal Controller (DSC) core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
• As many as 80 million instructions per second (MIPS) at 80 MHz core frequency
• 162 basic instructions
• Instruction set supports both fractional arithmetic and integer arithmetic
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
5
Overview
• 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
• 32-bit arithmetic and logic multi-bit shifter
• Four 36-bit accumulators, including extension bits
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
• Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions enable compact code
• Enhanced bit manipulation instruction set
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack, with the stack's depth limited only by
memory
• Priority level setting for interrupt levels
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
that is independent of processor speed
1.3 Operation parameters
• Up to 80 MHz operation at -40 °C to 105 °C ambient temperature
• Single 3.3 V power supply
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
1.4 On-chip memory and memory protection
• Modified dual Harvard architecture permits as many as three simultaneous accesses
to program and data memory
• Internal flash memory with security and protection to prevent unauthorized access
• Memory resource protection (MRP) unit to protect supervisor programs and
resources from user programs
• Programming code can reside in flash memory during flash programming
• The dual-ported RAM controller supports concurrent instruction fetches and data
accesses, or dual data accesses, by the DSC core.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
6
Freescale Semiconductor, Inc.
Peripheral highlights
• Concurrent accesses provide increased performance.
• The data and instruction arrive at the core in the same cycle, reducing latency.
• On-chip memory
• Up to 144 KW program/data flash memory, including FlexNVM
• Up to 16 KW dual port data/program RAM
• Up to 16 KW FlexNVM, which can be used as additional program or data flash
memory
• Up to 1 KW FlexRAM, which can be configured as enhanced EEPROM (used in
conjunction with FlexNVM) or used as additional RAM
1.5 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
1.6 Peripheral highlights
1.6.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)
• One PWM module contains 4 identical submodules, with up to 3 outputs per
submodule, and up to 80 MHz PWM operating clock
• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
7
Peripheral highlights
• PWMA with NanoEdge high resolution
• Fractional delay for enhanced resolution of the PWM period and edge placement
• Arbitrary PWM edge placement
• 390 ps PWM frequency and duty-cycle resolution when NanoEdge functionality
is enabled.
• Fractional clock digital dithering: 5-bit digital fractional clock accumulation for
enhanced resolution of PWM period and edge placement, which is effectively
equivalent to 390 ps resolution in the overall accumulative period.
• PWM outputs can be configured as complementary output pairs or independent
outputs
• Dedicated time-base counter with period and frequency control per submodule
• Independent top and bottom deadtime insertion for each complementary pair
• Independent control of both edges of each PWM output
• Enhanced input capture and output compare functionality on each input:
• Channels not used for PWM generation can be used for buffered output compare
functions.
• Channels not used for PWM generation can be used for input capture functions.
• Enhanced dual edge capture functionality
• Synchronization of submodule to external hardware (or other PWM) is supported.
• Double-buffered PWM registers
• Integral reload rates from 1 to 16
• Half-cycle reload capability
• Multiple output trigger events can be generated per PWM cycle via hardware.
• Support for double-switching PWM outputs
• Up to eight fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Individual software control of each PWM output
• All outputs can be programmed to change simultaneously via a FORCE_OUT event.
• PWMX pin can optionally output a third PWM signal from each submodule
• Option to supply the source for each complementary PWM signal pair from any of
the following:
• Crossbar module outputs
• External ADC input, taking into account values set in ADC high and low limit
registers
1.6.2 12-bit Analog-to-Digital Converter (Cyclic type)
• Two independent 12-bit analog-to-digital converters (ADCs):
• 2 x 8-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
8
Freescale Semiconductor, Inc.
Peripheral highlights
• Maximum ADC clock frequency up to 20 MHz, having period as low as a 50-ns
• Single conversion time of 8.5 ADC clock cycles
• Additional conversion time of 6 ADC clock cycles
• Support of analog inputs for single-ended and differential conversions
• Sequential, parallel, and independent scan mode
• First 8 samples have offset, limit and zero-crossing calculation supported
• ADC conversions can be synchronized by any module connected to the internal
crossbar module, such as PWM, timer, GPIO, and comparator modules.
• Support for simultaneous triggering and software-triggering conversions
• Support for a multi-triggering mode with a programmable number of conversions on
each trigger
• Each ADC has ability to scan and store up to 8 conversion results.
• Current injection protection
1.6.3 Inter-Module Crossbar and AND-OR-INVERT logic
• Provides generalized connections between and among on-chip peripherals: ADCs,
12-bit DAC, comparators, quad-timers, eFlexPWMs, PDBs, EWM, and select I/O
pins
• User-defined input/output pins for all modules connected to the crossbar
• DMA request and interrupt generation from the crossbar
• Write-once protection for all registers
• AND-OR-INVERT function provides a universal Boolean function generator that
uses a four-term sum-of-products expression, with each product term containing true
or complement values of the four selected inputs (A, B, C, D).
1.6.4 Comparator
• Full rail-to-rail comparison range
• Support for high and low speed modes
• Selectable input source includes external pins and internal DACs
• Programmable output polarity
• 6-bit programmable DAC as a voltage reference per comparator
• Three programmable hysteresis levels
• Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output
1.6.5 12-bit Digital-to-Analog Converter
• 12-bit resolution
• Powerdown mode
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
9
Peripheral highlights
• Automatic mode allows the DAC to automatically generate pre-programmed output
waveforms, including square, triangle, and sawtooth waveforms (for applications like
slope compensation)
• Programmable period, update rate, and range
• Output can be routed to an internal comparator, ADC, or optionally to an off-chip
destination
1.6.6 Quad Timer
• Four 16-bit up/down counters, with a programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM,
signal shot, single pulse, pulse string, cascaded, quadrature decode
• Programmable input filter
• Counting start can be synchronized across counters
1.6.7 Queued Serial Communications Interface (QSCI) modules
• Operating clock can be up to two times the CPU operating frequency
• Four-word-deep FIFOs available on both transmit and receive buffers
• Standard mark/space non-return-to-zero (NRZ) format
• 13-bit integer and 3-bit fractional baud rate selection
• Full-duplex or single-wire operation
• Programmable 8-bit or 9-bit data format
• Error detection capability
• Two receiver wakeup methods:
• Idle line
• Address mark
• 1/16 bit-time noise detection
1.6.8 Queued Serial Peripheral Interface (QSPI) modules
• Maximum 25 Mbit/s baud rate
• Selectable baud rate clock sources for low baud rate communication
• Baud rate as low as Baudrate_Freq_in / 8192
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four-word-deep FIFOs available on transmit and receive buffers
• Programmable length transmissions (2 bits to 16 bits)
• Programmable transmit and receive shift order (MSB as first bit transmitted)
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
10
Freescale Semiconductor, Inc.
Peripheral highlights
1.6.9 Inter-Integrated Circuit (I2C)/System Management Bus (SMBus)
modules
• Compatible with I2C bus standard
• Support for System Management Bus (SMBus) specification, version 2
• Multi-master operation
• General call recognition
• 10-bit address extension
• Start/Repeat and Stop indication flags
• Support for dual slave addresses or configuration of a range of slave addresses
• Programmable glitch input filter
1.6.10 Flex Controller Area Network (FlexCAN) module
• Clock source from PLL or XOSC/CLKIN
• Implementation of CAN protocol Version 2.0 A/B
• Standard and extended data frames
• Data length of 0 to 8 bytes
• Programmable bit rate up to 1 Mbps
• Support for remote frames
• Sixteen Message Buffers: each Message Buffer can be configured as receive or
transmit, and supports standard and extended messages
• Individual Rx Mask Registers per Message Buffer
• Internal timer for time-stamping of received and transmitted messages
• Listen-only mode capability
• Programmable loopback mode, supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Global network time, synchronized by a specific message
• Low power modes, with programmable wakeup on bus activity
1.6.11 Computer Operating Properly (COP) watchdog
• Programmable timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator/external clock source
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
11
Clock sources
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 80 MHz)
• 8 MHz / 400 kHz ROSC
• Support for interrupt triggered when the counter reaches the timeout value
1.6.12 Power supervisor
• Power-on reset (POR) to reset CPU, peripherals, and JTAG/EOnCE controllers (VDD
> 2.1 V)
• Brownout reset (VDD < 1.9 V)
• Critical warn low-voltage interrupt (LVI2.0)
• Peripheral low-voltage interrupt (LVI2.7)
1.6.13 Phase-locked loop
• Wide programmable output frequency: 240 MHz to 400 MHz
• Input reference clock frequency: 8 MHz to 16 MHz
• Detection of loss of lock and loss of reference clock
• Ability to power down
1.6.14 Clock sources
1.6.14.1 On-chip oscillators
• Tunable 8 MHz relaxation oscillator with 400 kHz at standby mode (divide-by-two
output)
• 32 kHz low frequency clock as secondary clock source for COP, EWM, PIT
1.6.14.2 Crystal oscillator
• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic
resonator
• Operating frequency: 4–16 MHz
1.6.15 Cyclic Redundancy Check (CRC) generator
• Hardware 16/32-bit CRC generator
• High-speed hardware CRC calculation
• Programmable initial seed value
• Programmable 16/32-bit polynomial
• Error detection for all single, double, odd, and most multi-bit errors
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
12
Freescale Semiconductor, Inc.
Clock sources
• Option to transpose input data or output data (CRC result) bitwise or bytewise,1
which is required for certain CRC standards
• Option for inversion of final CRC result
1.6.16 General Purpose I/O (GPIO)
• 5 V tolerance (except RESETB pin)
• Individual control of peripheral mode or GPIO mode for each pin
• Programmable push-pull or open drain output
• Configurable pullup or pulldown on all input pins
• All pins (except JTAG and RESETB) default to be GPIO inputs
• 2 mA / 9 mA source/sink capability
• Controllable output slew rate
1.7 Block diagrams
The 56800EX core is based on a modified dual Harvard-style architecture, consisting of
three execution units operating in parallel, and allowing as many as six operations per
instruction cycle. The MCU-style programming model and optimized instruction set
enable straightforward generation of efficient and compact code for the DSP and control
functions. The instruction set is also efficient for C compilers, to enable rapid
development of optimized control applications.
The device's basic architecture appears in Figure 1 and Figure 2. Figure 1 shows how the
56800EX system buses communicate with internal memories, and the IPBus interface
and the internal connections among the units of the 56800EX core. Figure 2 shows the
peripherals and control blocks connected to the IPBus bridge. See the specific device’s
Reference Manual for details.
1. A bytewise transposition is not possible when accessing the CRC data register via 8-bit accesses. In this case, user
software must perform the bytewise transposition.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
13
Clock sources
DSP56800EX Core
Program Control Unit
ALU1
ALU2
Address
Generation
Unit
PC
LA
LA2
HWS0
HWS1
FIRA
Instruction
Decoder
R0
R1
(AGU)
R2
Interrupt
Unit
Program
Memory
M01
N3
R3
OMR
R4
SR
LC
LC2
R5
Looping
Unit
N
SP
FISR
XAB1
XAB2
PAB
Data/
Program
RAM
PDB
CDBW
CDBR
XDB2
A2
B2
C2
D2
A1
B1
C1
D1
Y1
Y0
X0
A0
B0
C0
D0
Bit-
Manipulation
Unit
IPBus
Interface
Data
Y
Enhanced
OnCE™
Arithmetic
Logic Unit
(ALU)
JTAG TAP
MAC and ALU Multi-Bit Shifter
Figure 1. 56800EX basic block diagram
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
14
Freescale Semiconductor, Inc.
Clock sources
JTAG
Program Bus
Core Data Bus
EOnCE
Program/Data Flash
56800EX CPU
Up to 96KB
Program
Controller
(PC)
Address
Generation
Unit (AGU)
Data Flash
32KB
FlexRAM
4
Secondary Data Bus
Arithmetic
Logic Unit
(ALU)
Bit
Manipulation
Unit
2KB
Data/Program RAM
Up to 16KB
DMA Controller
Interrupt Controller
Crystal OSC
Power Management
Controller (PMC)
Internal 8 MHz
Watchdog (COP)
Internal 32 kHz
PLL
System Integration
Module (SIM)
Periodic Interrupt
Timer (PIT) 0, 1
CRC
Peripheral Bus
QSCI
0, 1
Quad Timer eFlexPWM A
I2C
0, 1
QSPI
0
FlexCAN
A & B
NanoEdge
Inter Module CrossbarInputs
Inter Module Crossbar Outputs
Inter-Module
Crossbar B
AND-OR-INV
Logic
GPIO & Peripheral MUX
Inter-Module
Crossbar A
Inter Module Crossbar Outputs
Inter Module Crossbar Inputs
Package
Pins
ADC C
16-bit
Comparators With
6-bit DAC A,B,C,D
ADC B
12-bit
DAC
12-bit
ADC A
12-bit
PDB
0, 1
EWM
Peripheral Bus
Figure 2. System diagram
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
15
MC56F8455x signal and pin descriptions
2 MC56F8455x signal and pin descriptions
After reset, each pin is configured for its primary function (listed first). Any alternative
functionality, shown in parentheses, must be programmed through the GPIO module
peripheral enable registers (GPIO_x_PER) and the SIM module GPIO peripheral select
(GPSx) registers. All GPIO ports can be individually programmed as an input or output
(using bit manipulation).
• There are 2 PWM modules: PWMA, PWMB. Each PWM module has 4 submodules:
PWMA has PWMA_0, PWMA_1, PWMA_2, PWMA_3; PWMB has PWMB_0,
PWMB_1, PWMB_2, PWMB_3. Each PWM module's submodules have 3 pins (A,
B, X) each, with the syntax for the pins being PWMA_0A, PWMA_0B, PWMA_0X,
and PWMA_1A, PWMA_1B, PWMA_1X, and so on. Each submodule pin can be
configured as a PWM output or as a capture input.
• EWM_OUT_B is the output of the External Watchdog Module (EWM), and is active
low (denoted by the "_B" part of the syntax).
For the MC56F8455X products, which use 48-pin LQFP and 64-pin LQFP packages:
Table 2. Signal descriptions
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
VDD
VDD
VDD
VSS
VSS
VSS
VDDA
29
-
Supply
Supply
I/O Power — Supplies 3.3 V power to the chip I/
O interface.
44
60
30
43
61
22
32
44
22
31
45
15
Supply
Supply
I/O Ground — Provide ground for the device I/O
interface.
Supply
Supply
Supply
Supply
Analog Power — Supplies 3.3 V power to the
analog modules. It must be connected to a clean
analog power supply.
VSSA
23
16
Analog Ground — Supplies an analog ground to
the analog modules. It must be connected to a
clean power supply.
VCAP
VCAP
26
57
19
43
On-chip
regulator
output
On-chip
regulator
output
Connect a 2.2uF or greater bypass capacitor
between this pin and VSS to stabilize the core
voltage regulator output required for proper
device operation. V<sub>CAP</sub> is used to
observe core voltage.
voltage
voltage
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
16
Freescale Semiconductor, Inc.
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
TDI
64
48
Input
Input,
internal
pullup
Test Data Input — Provides a serial input data
stream to the JTAG/EOnCE port. It is sampled
on the rising edge of TCK and has an internal
pullup resistor. After reset, the default state is
TDI.
enabled
(GPIOD0)
Input/Output Input,
internal
GPIO Port D0
pullup
enabled
TDO
62
46
Output
Output
Test Data Output — This tri-stateable pin
provides a serial output data stream from the
JTAG/EOnCE port. It is driven in the shift-IR and
shift-DR controller states, and it changes on the
falling edge of TCK. After reset, the default state
is TDO.
(GPIOD1)
Input/Output Input,
internal
GPIO Port D1
pullup
enabled
TCK
1
1
Input
Input,
internal
pullup
Test Clock Input — This input pin provides a
gated clock to synchronize the test logic and
shift serial data to the JTAG/EOnCE port. The
pin is connected internally to a pullup resistor. A
Schmitt-trigger input is used for noise immunity.
After reset, the default state is TCK.
enabled
(GPIOD2)
Input/Output Input,
internal
GPIO Port D2
pullup
enabled
TMS
63
47
Input
Input,
internal
pullup
Test Mode Select Input — Used to sequence
the JTAG TAP controller state machine. It is
sampled on the rising edge of TCK and has an
internal pullup resistor. After reset, the default
state is TMS.
enabled
NOTE: Always tie the TMS pin to VDD through
a 2.2K resistor, if needed to keep an
on-board debug capability. Otherwise,
tie the TMS pin directly to VDD
.
(GPIOD3)
Input/Output Input,
internal
GPIO Port D2
pullup
enabled
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
17
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
RESET or RESETB
2
2
Input
Input,
internal
pullup
Reset — A direct hardware reset on the
processor. When RESET is asserted low, the
device is initialized and placed in the reset state.
A Schmitt-trigger input is used for noise
enabled
(This pin is immunity. The internal reset signal is deasserted
3.3V only.)
synchronously with the internal clocks after a
fixed number of internal clocks. After reset, the
default state is RESET. To filter noise on the
RESETB pin, install a capacitor (up to 0.1 uF)
on it.
(GPIOD4)
Input/ Open- Input,
drain Output internal
pullup
GPIO Port D4 RESET functionality is disabled in
this mode and the device can be reset only
through Power-On Reset (POR), COP reset, or
software reset.
enabled
GPIOA0
13
9
Input/Output Input
GPIO Port A0: After reset, the default state is
GPIOA0.
(ANA0&CMPA_IN3)
Input
ANA0 is input to channel 0 of ADCA; CMPA_IN3
is input 3 of analog comparator A. When used
as an analog input, the signal goes to both
places (ANA0 and CMPA_IN3), but the glitch on
this pin during ADC sampling may interfere with
other analog inputs shared on this pin.
(CMPC_O)
Output
Analog comparator C output
GPIOA1
14
10
Input/Output Input
GPIO Port A1: After reset, the default state is
GPIOA1.
(ANA1&CMPA_IN0)
Input
ANA1 is input to channel 1 of ADCA; CMPA_IN0
is input 0 of analog comparator A. When used
as an analog input, the signal goes to both
places (ANA1 and CMPA_IN0), but the glitch on
this pin during ADC sampling may interfere with
other analog inputs shared on this pin.
GPIOA2
15
11
Input/Output Input
Input
GPIO Port A2: After reset, the default state is
GPIOA2.
(ANA2&VREFHA&
CMPA_IN1)
ANA2 is input to channel 2 of ADCA; VREFHA
is the reference high of ADCA; CMPA_IN1 is
input 1 of analog comparator A. When used as
an analog input, the signal goes to both places
(ANA2 and CMPA_IN1), but the glitch on this
pin during ADC sampling may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANA2 or
VREFHA using the ADCA control register.
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
18
Freescale Semiconductor, Inc.
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOA3
16
12
Input/Output Input
GPIO Port A3: After reset, the default state is
GPIOA3.
(ANA3&VREFLA&
CMPA_IN2)
Input
ANA3 is input to channel 3 of ADCA; VREFLA is
the reference low of ADCA; CMPA_IN2 is input
2 of analog comparator A. When used as an
analog input, the signal goes to both places
(ANA3 and CMPA_IN2), but the glitch on this
pin during ADC sampling may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANA3 or
VREFLA using the ADCA control register.
GPIOA4
12
8
Input/Output Input
Input
GPIO Port A4: After reset, the default state is
GPIOA4.
(ANA4&ANC8&CMPD_IN0
)
ANA4 is input to channel 4 of ADCA; ANC8 is
input to channel 8 of ADCC; CMPD_IN0 is input
0 to comparator D. When used as an analog
input, the signal goes to all three places (ANA4
and ANC8 and CMPA_IN0), but the glitchon this
pin during ADC sampling may interfere with
other analog inputs shared on this pin.
GPIOA5
11
10
9
-
-
-
Input/Output Input
Input
GPIO Port A5: After reset, the default state is
GPIOA5.
(ANA5&ANC9)
ANA5 is input to channel 5 of ADCA; ANC9 is
input to channel 9 of ADCC. When used as an
analog input, the signal goes to both places
(ANA5 and ANC9), but the glitch on this pin
during ADC sampling may interfere with other
analog inputs shared on this pin.
GPIOA6
Input/ Output Input
Input
GPIO Port A6: After reset, the default state is
GPIOA6.
(ANA6&ANC10)
ANA6 is input to channel 5 of ADCA; ANC10 is
input to channel 10 of ADCC. When used as an
analog input, the signal goes to both places
(ANA6 and ANC10), but the glitch on this pin
during ADC sampling may interfere with other
analog inputs shared on this pin.
GPIOA7
Input/Output Input
Input
GPIO Port A7: After reset, the default state is
GPIOA7.
(ANA7&ANC11)
ANA7 is input to channel 7 of ADCA; ANC11 is
input to channel 11 of ADCC. When used as an
analog input, the signal goes to both places
(ANA7 and ANC11), but the glitch on this pin
during ADC sampling may interfere with other
analog inputs shared on this pin.
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
19
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOB0
24
17
Input/Output Input
GPIO Port B0: After reset, the default state is
GPIOB0.
(ANB0&CMPB_IN3)
Input
ANB0 is input to channel 0 of ADCB; CMPB_IN3
is input 3 of analog comparator B. When used
as an analog input, the signal goes to both
places (ANB0 and CMPB_IN3), but the glitch on
this pin during ADC sampling may interfere with
other analog inputs shared on this pin.
GPIOB1
25
18
Input/ Output Input
Input
GPIO Port B1: After reset, the default state is
GPIOB1.
(ANB1&CMPB_IN0)
ANB1 is input to channel 1 of ADCB; CMPB_IN0
is input 0 of analog comparator B. When used
as an analog input, the signal goes to both
places (ANB1 and CMPB_IN0), but the glitch on
this pin during ADC sampling may interfere with
other analog inputs shared on this pin.
GPIOB2
27
20
Input/ Output Input
Input
GPIO Port B2: After reset, the default state is
GPIOB2.
(ANB2&VREFHB&CMPC_
IN3)
ANB2 is input to channel 2 of ADCB; VREFHB
is the reference high of ADCB; CMPC_IN3 is
input 3 of analog comparator C. When used as
an analog input, the signal goes to both places
(ANB2 and CMPC_IN3), but the glitch during
ADC sampling on this pin may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANB2 or
VREFHB using the ADCB control register.
GPIOB3
28
21
Input/ Output Input
Input
GPIO Port B3: After reset, the default state is
GPIOB3.
(ANB3&VREFLB&CMPC_I
N0)
ANB3 is input to channel 3 of ADCB; VREFLB is
the reference low of ADCB; CMPC_IN0 is input
0 of analog comparator C. When used as an
analog input, the signal goes to both places
(ANB3 and CMPC_IN0), but the glitch during
ADC sampling on this pin may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANB3 or
VREFLB using the ADCB control register.
GPIOB4
21
14
Input/ Output Input
Input
GPIO Port B4: After reset, the default state is
GPIOB4.
(ANB4&ANC12&CMPC_IN
1)
ANB4 is input to channel 4 of ADCB; ANC12 is
input to channel 12 of ADCC; CMPC_IN1 is
input 1 of analog comparator C. When used as
an analog input, the signal goes to all three
places (ANB4 and ANC12 and CMPC_IN1), but
the glitch during ADC sampling on this pin may
interfere with other analog inputs shared on this
pin.
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
20
Freescale Semiconductor, Inc.
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOB5
20
-
-
-
Input/ Output Input
GPIO Port B5: After reset, the default state is
GPIOB5.
(ANB5&ANC13&CMPC_IN
2)
Input
ANB5 is input to channel 5 of ADCB; ANC13 is
input to channel 13 of ADCC; CMPC_IN2 is
input 2 of analog comparator C. When used as
an analog input, the signal goes to all three
places (ANB5 and ANC13 and CMPC_IN2), but
the glitch during ADC sampling on this pin may
interfere with other analog inputs shared on this
pin.
GPIOB6
19
Input/ Output Input
Input
GPIO Port B6: After reset, the default state is
GPIOB6.
(ANB6&ANC14&CMPB_IN
1)
ANB6 is input to channel 6 of ADCB; ANC14 is
input to channel 14 of ADCC; CMPB_IN1 is
input 1 of analog comparator B. When used as
an analog input, the signal goes to all three
places (ANB6 and ANC14 and CMPB_IN1), but
the glitch during ADC sampling on this pin may
interfere with other analog inputs shared on this
pin.
GPIOB7
17
Input/ Output Input
Input
GPIO Port B7: After reset, the default state is
GPIOB7.
(ANB7&ANC15&CMPB_IN
2)
ANB7 is input to channel 7 of ADCB; ANC15 is
input to channel 15 of ADCC; CMPB_IN2 is
input 2 of analog comparator B. When used as
an analog input, the signal goes to all three
places (ANB7 and ANC15 and CMPB_IN2), but
the glitch during ADC sampling on this pin may
interfere with other analog inputs shared on this
pin.
GPIOC0
3
4
3
4
Input/Output Input
Analog Input
GPIO Port C0: After reset, the default state is
GPIOC0.
EXTAL
The external crystal oscillator input (EXTAL)
connects the internal crystal oscillator input to
an external crystal or ceramic resonator.
External clock input 0.2
CLKIN0
Input
GPIOC1
Input/Output Input
GPIO Port C1: After reset, the default state is
GPIOC1.
(XTAL)
Analog
Output
The external crystal oscillator output (XTAL)
connects the internal crystal oscillator output to
an external crystal or ceramic resonator.
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
21
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOC2
5
5
Input/Output Input
GPIO Port C2: After reset, the default state is
GPIOC2.
(TXD0)
Output
SCI0 transmit data output or transmit/receive in
single-wire operation
(TB0)
Input/Output
Input
Quad timer module B channel 0 input/output
Crossbar module input 2
(XB_IN2)
(CLKO0)
Output
Buffered clock output 0: the clock source is
selected by clockout select (CLKOSEL) bits in
the clock output select register (CLKOUT) of the
SIM.
GPIOC3
7
8
6
7
Input/ Output Input
GPIO Port C3: After reset, the default state is
GPIOC3.
(TA0)
Input/ Output
Output
Quad timer module A channel 0 input/output
Analog comparator A output
SCI0 receive data input
(CMPA_O)
(RXD0)
Input
(CLKIN1)
GPIOC4
Input
External clock input 1
Input/ Output Input
GPIO Port C4: After reset, the default state is
GPIOC4.
(TA1)
Input/ Output
Output
Quad timer module A channel 1 input/output
Analog comparator B output
(CMPB_O)
(XB_IN8)
(EWM_OUT_B)
GPIOC5
Input
Crossbar module input 8
Output
External Watchdog Module output
18
31
13
23
Input/ Output Input
GPIO Port C5: After reset, the default state is
GPIOC5.
(DACO)
Analog
Output
12-bit digital-to-analog output
(XB_IN7)
Input
Crossbar module input 7
GPIOC6
Input/ Output Input,
GPIO Port C6: After reset, the default state is
GPIOC6.
(TA2)
Input/ Output
Input
Quad timer module A channel 2 input/output
Crossbar module input 3
(XB_IN3)
(CMP_REF)
Analog Input
Positive input 5 of analog comparator A and B
and C and D. Note: MC56F84550 and
MC56F84540 do not have CMPD.
GPIOC7
32
24
Input/ Output Input
Input/ Output
GPIO Port C7: After reset, the default state is
GPIOC7.
(SS0_B)
In slave mode, SS0_B indicates to the SPI
module 0 that the current transfer is to be
received.
(TXD0)
Output
SCI0 transmit data output or transmit/receive in
single-wire operation
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
22
Freescale Semiconductor, Inc.
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOC8
33
25
Input/Output Input
GPIO Port C8: After reset, the default state is
GPIOC8.
(MISO0)
Input/Output
Master in/slave out for SPI0 —In master mode,
MISO0 pin is the data input. In slave mode,
MISO0 pin is the data output. The MISO line of
a slave device is placed in the high-impedance
state if the slave device is not selected.
(RXD0)
Input
SCI0 receive data input
Crossbar module input 9
(XB_IN9)
GPIOC9
Input
34
35
26
27
Input/ Output Input
GPIO Port C9: After reset, the default state is
GPIOC9.
(SCK0)
Input/ Output
SPI0 serial clock. In master mode, SCK0 pin is
an output, clocking slaved listeners. In slave
mode, SCK0 pin is the data clock input.
(XB_IN4)
Input
Crossbar module input 4
GPIOC10
Input/ Output Input
GPIO Port C10: After reset, the default state is
GPIOC10.
(MOSI0)
Input/ Output
Master out/slave in for SPI0 — In master mode,
MOSI0 pin is the data output. In slave mode,
MOSI0 pin is the data input.
(XB_IN5)
(MISO0)
Input
Crossbar module input 5
Input/ Output
Master in/slave out for SPI0 — In master mode,
MISO0 pin is the data input. In slave mode,
MISO0 pin is the data output. The MISO line of
a slave device is placed in the high-impedance
state if the slave device is not selected.
GPIOC11
(CANTX)
(SCL1)
37
29
Input/Output Input
GPIO Port C11: After reset, the default state is
GPIOC11.
Open-drain
Output
CAN transmit data output
Input/ Open-
drain Output
I2C1 serial clock
(TXD1)
Output
SCI1 transmit data output or transmit/receive in
single wire operation
GPIOC12
38
30
Input/ Output Input
GPIO Port C12: After reset, the default state is
GPIOC12.
(CANRX)
(SDA1)
Input
CAN receive data input
I2C1 serial data line
Input/ Open-
drain Output
(RXD1)
Input
SCI1 receive data input
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
23
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOC13
49
37
Input/ Output Input,
GPIO Port C13: After reset, the default state is
GPIOC13.
(TA3)
Input/ Output
Input
Quad timer module A channel 3 input/output
Crossbar module input 6
(XB_IN6)
(EWM_OUT_B)
GPIOC14
Output
External Watchdog Module output
55
56
41
42
Input/ Output Input
GPIO Port C14: After reset, the default state is
GPIOC14.
I2C0 serial data line
(SDA0)
Input/ Open-
drain Output
(XB_OUT4)
Input
Crossbar module output 4
GPIOC15
Input/ Output Input
GPIO Port C15: After reset, the default state is
GPIOC15.
(SCL0)
Input/ Open-
drain Output
I2C0 serial clock
(XB_OUT5)
Input
Crossbar module output 5
GPIOE0
45
46
47
48
51
33
34
35
38
39
Input/ Output Input
GPIO Port E0: After reset, the default state is
GPIOE0.
PWMA_0B
GPIOE1
Input/ Output
PWM module A (NanoEdge), submodule 0,
output B or input capture B
Input/ Output Input
Input/ Output
GPIO Port E1: After reset, the default state is
GPIOE1.
(PWMA_0A)
GPIOE2
PWM module A (NanoEdge), submodule 0,
output A or input capture A
Input/ Output Input
Input/ Output
GPIO Port E2: After reset, the default state is
GPIOE2.
(PWMA_1B)
GPIOE3
PWM module A (NanoEdge), submodule 1,
output B or input capture B
Input/ Output Input
Input/ Output
GPIO Port E3: After reset, the default state is
GPIOE3.
(PWMA_1A)
GPIOE4
PWM module A (NanoEdge), submodule 1,
output A or input capture A
Input/ Output Input
Input/ Output
GPIO Port E4: After reset, the default state is
GPIOE4.
(PWMA_2B)
PWM module A (NanoEdge), submodule 2,
output B or input capture B
(XB_IN2)
Input
Crossbar module input 2
GPIOE5
52
40
Input/ Output Input
GPIO Port E5: After reset, the default state is
GPIOE5.
(PWMA_2A)
(XB_IN3)
Input/ Output
Input
PWM module A (NanoEdge), submodule 2,
output A or input capture A
Crossbar module input 3
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
24
Freescale Semiconductor, Inc.
MC56F8455x signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOE6
53
-
Input/ Output Input
GPIO Port E6: After reset, the default state is
GPIOE6.
(PWMA_3B)
Input/ Output
PWM module A (NanoEdge), submodule 3,
output B or input capture B
(XB_IN4)
Input
Crossbar module input 4
(PWMB_2B)
Input/ Output
PWM module B, submodule 2, output B or input
capture B
GPIOE7
54
-
Input/ Output Input
Input/ Output
GPIO Port E7: After reset, the default state is
GPIOE7.
(PWMA_3A)
PWM module A, submodule 3, output A or input
capture A
(XB_IN5)
Input
Crossbar module input 5
(PWMB_2A)
Input/ Output
PWM module B, submodule 2, output A or input
capture A
GPIOF0
36
50
28
38
Input/ Output Input
GPIO Port F0: After reset, the default state is
GPIOF0.
(XB_IN6)
(TB2)
Input
Crossbar module input 6
Input/ Output
Input/ Output Input
Quad timer module B Channel 2 input/output
GPIOF1
GPIO Port F1: After reset, the default state is
GPIOF1.
(CLKO1)
Output
Buffered clock output 1: the clock source is
selected by clockout select (CLKOSEL) bits in
the clock output select register (CLKOUT) of the
SIM.
(XB_IN7)
(CMPD_O)
GPIOF2
Input
Crossbar module input 7
Output
Analog comparator D output
39
40
41
-
-
-
Input/ Output Input
GPIO Port F2: After reset, the default state is
GPIOF2.
I2C1 serial clock
(SCL1)
Input/ Open-
drain Output
(XB_OUT6)
Output
Crossbar module output 6
GPIOF3
Input/ Output Input
GPIO Port F3: After reset, the default state is
GPIOF3.
I2C1 serial data line
(SDA1)
Input/ Open-
drain Output
(XB_OUT7)
Output
Crossbar module output 7
GPIOF4
Input/ Output Input
GPIO Port F4: After reset, the default state is
GPIOF4.
(TXD1)
Output
Output
SCI1 transmit data output or transmit/receive in
single wire operation
(XB_OUT8)
Crossbar module output 8
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
25
Signal groups
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
48
LQFP
Type
State
During
Reset1
Signal Description
GPIOF5
42
-
-
Input/ Output Input
GPIO Port F5: After reset, the default state is
GPIOF5.
(RXD1)
Output
SCI1 receive data input
(XB_OUT9)
GPIOF6
Output
Crossbar module output 9
58
Input/ Output Input
GPIO Port F6: After reset, the default state is
GPIOF6.
(TB2)
Input/ Output
Input/ Output
Quad timer module B Channel 2 input/output
(PWMA_3X)
PWM module A, submodule 3, output X or input
capture X
(PWMB_3X)
Input/ Output
PWM module B, submodule 3, output X or input
capture X
(XB_IN2)
Input
Crossbar module input 2
GPIOF7
59
-
-
Input/ Output Input
GPIO Port F7: After reset, the default state is
GPIOF7.
(TB3)
Input/ Output
Output
Quad timer module B Channel 3 input/output
Analog comparator C output
(CMPC_O)
(XB_IN3)
GPIOF8
Input
Crossbar module input 3
6
Input/ Output
GPIO Port F8: After reset, the default state is
GPIOF8.
(RXD0)
(TB1)
Input
SCI0 receive data input
Input/ Output
Output
Quad timer module B Channel 1 input/output
Analog comparator D output
(CMPD_O)
1. For all GPIO except GPIOD0 - GPIOD4, input only after reset (internal pullup and pull-down are disabled).
2. If CLKIN is selected as the device’s external clock input, then both the GPS_C0 bit (in GPS1) and the EXT_SEL bit (in
OCCS oscillator control register (OSCTL)) must be set. Also, the crystal oscillator should be powered down.
3 Signal groups
The input and output signals of the MC56F84xxx are organized into functional groups, as
listed in Table 3. Note that some package sizes may not be available for your specific
product. See MC56F844xx/5xx/7xx product family.
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins
64 LQFP 80 LQFP 100 LQFP
48 LQFP
Power Inputs (VDD, VDDA), Power Outputs (VCAP
)
5
4
1
6
6
5
1
6
6
1
Ground (VSS, VSSA
Reset
)
4
1
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
26
Freescale Semiconductor, Inc.
Ordering parts
Table 3. Functional Group Pin Allocations
(continued)
Functional Group
Number of Pins
48 LQFP
64 LQFP
80 LQFP 100 LQFP
eFlexPWM with NanoEdge ports, not including fault pins
6
5
8
5
N/A
8
N/A
15
15
6
Queued Serial Peripheral Interface (QSPI) ports
Queued Serial Communications Interface (QSCI) ports
Inter-Integrated Circuit (I2C) interface ports
12-bit Analog-to-Digital Converter (Cyclic ADC) inputs
16-bit Analog-to-Digital Converter (SAR ADC) inputs
Analog Comparator inputs/outputs
6
9
9
4
6
6
10
2
16
8
16
10
13/6
1
16
16
16/6
1
10/4
1
13/6
1
12-bit Digital-to-Analog output
Quad Timer Module (TMR) ports
6
9
11
2
13
2
Controller Area Network (FlexCAN)
2
2
Inter-Module Crossbar inputs/outputs
12/2
2/2
4
16/6
2/2
4
19/17
2/3
4
25/19
2/3
4
Clock inputs/outputs
JTAG / Enhanced On-Chip Emulation (EOnCE)
4 Ordering parts
4.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: MC56F84
5 Part identification
5.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
27
Terminology and guidelines
5.2 Format
Part numbers for this device have the following format: Q 56F8 4 C F P T PP N
5.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• MC = Fully qualified, general market flow
• PC = Prequalification
56F8
DSC family with flash memory and DSP56800/
DSP56800E/DSP56800EX core
• 56F8
4
DSC subfamily
• 4
C
Maximum CPU frequency (MHz)
• 4 = 60 MHz
• 5 = 80 MHz
• 7 = 100 MHz
F
P
Primary program flash memory size
Pin count
• 4 = 64 KB
• 5 = 96 KB
• 6 = 128 KB
• 8 = 256 KB
• 0 and 1 = 48
• 2 and 3 = 64
• 4, 5, and 6 = 80
• 7, 8, and 9 = 100
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LF = 48LQFP
• LH = 64LQFP
• LK = 80LQFP
• LL = 100LQFP
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
5.4 Example
This is an example part number: MC56F84789VLL
6 Terminology and guidelines
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
28
Freescale Semiconductor, Inc.
Terminology and guidelines
6.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
6.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
6.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
6.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
6.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
6.3.1 Example
This is an example of an attribute:
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
29
Terminology and guidelines
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
6.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
6.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
6.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
30
Freescale Semiconductor, Inc.
Terminology and guidelines
6.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
6.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
6.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
31
Terminology and guidelines
6.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
6.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
6.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
32
Freescale Semiconductor, Inc.
Ratings
7 Ratings
7.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.3 ESD handling ratings
Although damage from electrostatic discharge (ESD) is much less common on these
devices than on early CMOS circuits, use normal handling precautions to avoid exposure
to static discharge. Qualification tests are performed to ensure that these devices can
withstand exposure to reasonable levels of static without suffering any permanent
damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification. During the
device qualification ESD stresses were performed for the human body model (HBM), the
machine model (MM), and the charge device model (CDM).
All latch-up testing is in conformity with AEC-Q100 Stress Test Qualification.
A device is defined as a failure if after exposure to ESD pulses, the device no longer
meets the device specification. Complete DC parametric and functional testing is
performed as per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
33
Ratings
Table 4. ESD/Latch-up Protection
Characteristic1
Min
–2000
–200
–500
–100
Max
+2000
+200
+500
+100
Unit
V
ESD for Human Body Model (HBM)
ESD for Machine Model (MM)
V
ESD for Charge Device Model (CDM)
V
Latch-up current at TA= 85°C (ILAT
)
mA
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
unless otherwise noted.
7.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in Table 5 may affect device
reliability or cause permanent damage to the device.
Table 5. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V)
Characteristic
Supply Voltage Range
Symbol
VDD
Notes1
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.4
-0.3
—
Max
4.0
4.0
4.0
0.3
0.3
5.5
4.0
4.0
4.0
-5.0
20.0
25
Unit
V
Analog Supply Voltage Range
ADC High Voltage Reference
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Digital Input Voltage Range
VDDA
VREFHx
ΔVDD
ΔVSS
VIN
V
V
V
V
Pin Group 1
Pin Group 2
Pin Group 4
Pin Group 3
V
RESET Input Voltage Range
Oscillator Input Voltage Range
Analog Input Voltage Range
Input clamp current, per pin (VIN < VSS - 0.3 V)2, 3
Output clamp current, per pin4
VIN_RESET
VOSC
VINA
V
V
V
VIC
mA
mA
mA
VOC
—
Contiguous pin DC injection current—regional limit sum
of 16 contiguous pins
IICont
-25
Output Voltage Range (normal push-pull mode)
Output Voltage Range (open drain mode)
RESET Output Voltage Range
VOUT
Pin Group 1, 2
Pin Group 1
Pin Group 2
-0.3
-0.3
-0.3
4.0
5.5
4.0
V
V
V
VOUTOD
VOUTOD_RE
SET
DAC Output Voltage Range
VOUT_DAC
Pin Group 5
-0.3
-40
-40
-55
4.0
105
125
150
V
Ambient Temperature Industrial
Junction Temperature
TA
Tj
°C
°C
°C
Storage Temperature Range (Extended Industrial)
TSTG
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
34
Freescale Semiconductor, Inc.
General
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. Continuous clamp current
3. All 5 volt tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode
connection to VDD. If VIN greater than VDIO_MIN (= VSS–0.3 V) is observed, then there is no need to provide current
limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required.
4. I/O is configured as push-pull mode.
8 General
8.1 General characteristics
The device is fabricated in high-density, low-power CMOS with 5 V–tolerant TTL-
compatible digital inputs, except for the RESET pin which is 3.3V only. The term “5 V–
tolerant” refers to the capability of an I/O pin, built on a 3.3 V–compatible process
technology, to withstand a voltage up to 5.5 V without damaging the device.
5 V–tolerant I/O is desirable because many systems have a mixture of devices designed
for 3.3 V and 5 V power supplies. In such systems, a bus may carry both 3.3 V– and 5 V–
compatible I/O voltage levels (a standard 3.3 V I/O is designed to receive a maximum
voltage of 3.3 V 10ꢀ during normal operation without causing damage). This 5 V–
tolerant capability therefore offers the power savings of 3.3 V I/O levels combined with
the ability to receive 5 V levels without damage.
Absolute maximum ratings in Table 5 are stress ratings only, and functional operation at
the maximum is not guaranteed. Stress beyond these ratings may affect device reliability
or cause permanent damage to the device.
Unless otherwise stated, all specifications within this chapter apply over the temperature
range of -40°C to 105°C ambient temperature over the following supply ranges:
VSS=VSSA=0V, VDD=VDDA=3.0V to 3.6V, CL≤50 pF, fOP=80MHz.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this high-
impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
35
General
8.2 AC electrical characteristics
Tests are conducted using the input levels specified in Table 8. Unless otherwise
specified, propagation delays are measured from the 50ꢀ to the 50ꢀ point, and rise and
fall times are measured between the 10ꢀ and 90ꢀ points, as shown in Figure 3.
Low
High
V
IH
90%
50%
10%
Midpoint1
Fall Time
Input Signal
V
IL
Rise Time
The midpoint is V + (V – V )/2.
IL
IH
IL
Figure 3. Input signal measurement references
Figure 4 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid
Data1
Data2 Valid
Data2
Data3 Valid
Data3
Data
Data Invalid State
Tri-stated
Data Active
Data Active
Figure 4. Signal states
8.3 Nonswitching electrical specifications
8.3.1 Voltage and current operating requirements
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is between 1 ms and 200 ms.
Table 6. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V)
Characteristic
Symbol
Notes1
Min
Typ
Max
Unit
Supply voltage2
VDD, VDDA
2.7
3.3
3.6
V
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
36
Freescale Semiconductor, Inc.
General
Table 6. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V) (continued)
Characteristic
Symbol
VREFHA
VREFHB
VREFHC
ΔVDD
ΔVSS
VIH
Notes1
Min
Typ
Max
Unit
ADC (Cyclic) Reference Voltage High
3.0
VDDA
V
ADC (SAR) Reference Voltage High
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Input Voltage High (digital inputs)
RESET Voltage High
2.0
-0.1
VDDA
0.1
V
V
V
V
V
V
V
0
0
-0.1
0.1
Pin Group 1
Pin Group 2
0.7 x VDD
0.7 x VDD
5.5
VIH_RESET
VIL
—
VDD
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
XTAL driven by an external clock source
Oscillator Input Voltage Low
Output Source Current High (at VOH min.)3, 4
• Programmed for low drive strength
Pin Groups 1, 2
Pin Group 4
0.35 x VDD
VDD + 0.3
VIHOSC
2.0
VILOSC
IOH
Pin Group 4
-0.3
0.8
V
Pin Group 1
Pin Group 1
—
—
-2
-9
mA
• Programmed for high drive strength
Output Source Current Low (at VOL max.)3, 4
• Programmed for low drive strength
IOL
Pin Groups 1, 2
Pin Groups 1, 2
—
—
2
9
mA
• Programmed for high drive strength
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. ADC (Cyclic) specifications are not guaranteed when VDDA is below 3.0 V.
3.
4. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive
injection currents of 16 contiguous pins—is 25 mA.
8.3.2 LVD and POR operating requirements
Table 7. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR)
Parameters
Characteristic
Symbol
POR
Min
Typ
2.0
Max
Unit
POR Assert Voltage1
POR Release Voltage2
LVI_2p7 Threshold Voltage
LVI_2p2 Threshold Voltage
V
V
V
V
POR
2.7
2.73
2.23
1. During 3.3-volt VDD power supply ramp down
2. During 3.3-volt VDD power supply ramp up (gated by LVI_2p7)
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
37
General
8.3.3 Voltage and current operating behaviors
The following table provides information about power supply requirements and I/O pin
characteristics.
Table 8. DC Electrical Characteristics at Recommended Operating
Conditions
Characteristic
Output Voltage High
Output Voltage Low
Symbol
VOH
Notes1
Min
VDD - 0.5
—
Typ
—
Max
—
Unit
V
Test Conditions
IOH = IOHmax
Pin Group 1
VOL
Pin Groups
1, 2
—
0.5
V
IOL = IOLmax
Digital Input Current High
IIH
Pin Group 1
Pin Group 2
—
0
+/- 2.5
µA
VIN = 2.4 V to 5.5 V
VIN = 2.4 V to VDD
pull-up enabled or
disabled
Comparator Input Current
High
IIHC
IIHOSC
RPull-Up
RPull-Down
IILC
Pin Group 3
Pin Group 3
—
—
0
0
+/- 2
+/- 2
50
µA
µA
kΩ
kΩ
µA
µA
V
VIN = VDDA
Oscillator Input Current
High
VIN = VDDA
Internal Pull-Up
Resistance
20
—
—
0
—
Internal Pull-Down
Resistance
20
50
—
VIN = 0V
Comparator Input Current
Low
Pin Group 3
Pin Group 3
Pin Group 5
—
+/- 2
+/- 2
Typically
Oscillator Input Current
Low
IILOSC
VDAC
—
0
VIN = 0V
DAC Output Voltage
Range
Typically
VSSA
—
RLD = 3 kΩ || CLD = 400 pF
+
VDDA -
40mV
40mV
Output Current1
IOZ
Pin Groups
1, 2
—
0
+/- 1
µA
V
—
—
High Impedance State
Schmitt Trigger Input
Hysteresis
VHYS
Pin Groups 0.06 x VDD
1, 2
—
—
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC
8.3.4 Power mode operating behaviors
Parameters listed are guaranteed by design.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
38
Freescale Semiconductor, Inc.
General
NOTE
To filter noise on the RESETB pin, install a capacitor (up to 0.1
uF) on it.
Table 9. Reset, stop, wait, and interrupt timing
Characteristic
Symbol
Typical Min
Typical
Max
Unit
See
Figure
Minimum RESET Assertion Duration
tRA
tRDA
tIF
161
865 x TOSC + 8 x T
361.3
—
ns
ns
ns
—
—
—
RESET deassertion to First Address Fetch
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
570.9
1. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion
must be greater than 21 ns.
NOTE
In the Table 9, T = system clock cycle and TOSC = oscillator
clock cycle. For an operating frequency of 80MHz, T=12.5ns.
At 4MHz (used coming out of reset and stop modes), T=250ns.
Table 10. Power-On-Reset mode transition times
Symbol
Description
Min
Max
Unit
Notes
TPOR
After a POR event, the amount of delay from when VDD
reaches 2.7V to when the first instruction executes (over the
operating temperature range).
199
225
us
LPS mode to LPRUN mode
VLPS mode to VLPRUN mode
STOP mode to RUN mode
240
1424
6.79
551
1500
7.29
0.650
1500
554
us
us
us
us
us
us
4
5
3
2
5
4
WAIT mode to RUN mode
0.570
1413
237.2
VLPWAIT mode to VLPRUN mode
LPWAIT mode to LPRUN mode
1. Normal boot (FTFL_OPT[LPBOOT]=1)
2. Clock configuration: CPU clock = 80 MHz, bus clock = 80 MHz, flash clock = 20
MHz
3. Clock configuration: CPU clock = 4 MHz, system clock source is 8 MHz IRC
4. CPU Clock = 200 kHz and 8 Mhz IRC in standby mode
5. Clock configuration: Using 64 kHz external clock source, CPU Clock = 32 kHz
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
39
General
8.3.5 Power consumption operating behaviors
Table 11. Current Consumption
Mode
Maximum Conditions
Frequency
Typical at 3.3 V, Maximum at 3.6
25°C
V, 105°C
1
1
IDD
IDDA
IDD
IDDA
RUN
80 MHz
• 80 MHz Device Clock
36.9 mA 16.2 mA 63.8 mA 26 mA
• Regulators are in full regulation
• Relaxation Oscillator on
• PLL powered on
• Continuous MAC instructions with fetches from
Program Flash
• All peripheral modules enabled.
• TMRs and SCIs using 1X Clock
• NanoEdge within PWMA using 1X clock
• ADC/DAC powered on and clocked at 5 MHz2
• Comparator powered on
WAIT
80 MHz
• 80 MHz Device Clock
32.8 mA 13.52 μA 57.3 mA 45 μA
• Regulators are in full regulation
• Relaxation Oscillator on
• PLL powered on
• Processor Core in WAIT state
• All Peripheral modules enabled.
• TMRs and SCIs using 1X Clock
• NanoEdge within PWMA using 2X clock
• ADC/DAC/Comparator powered off
STOP
4 MHz
2 MHz
• 4 MHz Device Clock
• Regulators are in full regulation
• Relaxation Oscillator on
9.09 mA 13.14 μA 28.70 43.20 μA
mA
• PLL powered off
• Processor Core in STOP state
• All peripheral module and core clocks are off
• ADC/DAC/Comparator powered off
LPRUN
(LsRUN)
• 200 kHz Device Clock from Relaxation Oscillator
(ROSC)
1.85 mA 3 mA
15.76 5.15 mA
mA
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Repeat NOP instructions
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs3
• Simple loop with running from platform instruction
buffer
LPWAIT
(LsWAIT)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator
(ROSC)
1.81 mA 2.67 mA 15.58 5.15 mA
mA
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs3
• Processor core in wait mode
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
40
Freescale Semiconductor, Inc.
General
Table 11. Current Consumption (continued)
Mode
Maximum Conditions
Frequency
Typical at 3.3 V, Maximum at 3.6
25°C
V, 105°C
1
1
IDD
IDDA
IDD
IDDA
LPSTOP
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator
1.06 mA 13.10 μA 14.74
43.2 μA
(LsSTOP)
(ROSC)
mA
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Only PITs and COP enabled; other peripheral
modules disabled and clocks gated off3
• Processor core in stop mode
VLPRUN
200 kHz
• 32 kHz Device Clock
0.57 mA 12.20 μA 8.39 mA 17.40 μA
• Clocked by a 32 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• Repeat NOP instructions
• All peripheral modules, except COP and EWM,
disabled and clocks gated off
• Simple loop running from platform instruction
buffer
VLPWAIT
200 kHz
• 32 kHz Device Clock
0.56 mA 11.44 μA 8.30 mA 15.00 μA
• Clocked by a 32 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in wait mode
VLPSTOP
200 kHz
• 32 kHz Device Clock
0.56 mA 10.44 μA 8.21 mA 13.14 μA
• Clocked by a 32 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in stop mode
1. No output switching, all ports configured as inputs, all inputs low, no DC loads
2. ADC power consumption at higher frequency can be found in Table 28
3. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 250 kHz,
because of the fixed frequency ratio of 1:4 between the CPU clock and the flash clock (when using a 2 MHz external input
clock and the CPU is operating at 1 MHz).
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
41
General
8.3.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
8.3.7 Capacitance attributes
Table 12. Capacitance attributes
Description
Symbol
CIN
Min.
—
Typ.
10
Max.
—
Unit
pF
Input capacitance
Output capacitance
COUT
—
10
—
pF
8.4 Switching specifications
8.4.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYSCLK
Device (system and core) clock frequency
• using relaxation oscillator
0.001
0
80
80
80
MHz
MHz
• using external clock source
fIPBUS
IP bus clock
—
8.4.2 General switching timing
Table 14. Switching timing
Symbol Description
GPIO pin interrupt pulse width1
Min
Max
Unit
Notes
1.5
IP Bus
Clock
Cycles
2
Synchronous path
Port rise and fall time (high drive strength), Slew disabled 2.7
≤ VDD ≤ 3.6V.
5.5
1.5
15.1
6.8
ns
3
3
Port rise and fall time (high drive strength), Slew enabled 2.7
≤ VDD ≤ 3.6V.
ns
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
42
Freescale Semiconductor, Inc.
General
Table 14. Switching timing (continued)
Symbol Description
Min
Max
Unit
Notes
Port rise and fall time (low drive strength). Slew disabled . 2.7
8.2
17.8
ns
4
≤ VDD ≤ 3.6V
Port rise and fall time (low drive strength). Slew enabled . 2.7
≤ VDD ≤ 3.6V
3.2
9.2
ns
4
1. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming
GPIOn_IPOLR and GPIOn_IENR.
2. The greater synchronous and asynchronous timing must be met.
3. 75 pF load
4. 15 pF load
8.5 Thermal specifications
8.5.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
Unit
°C
Die junction temperature
Ambient temperature (extended industrial)
TA
°C
8.5.2 Thermal attributes
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To account for PI/O in power
calculations, determine the difference between actual pin voltage and VSS or VDD and
multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is very small.
See Thermal design considerations for more detail on thermal design considerations.
Board type
Symbol
Description
48 LQFP
64 LQFP
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
70
64
°C/W
1, 2
ambient (natural
convection)
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Board type
Symbol
Description
48 LQFP
64 LQFP
Unit
Notes
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
46
46
°C/W
1, 3
ambient (natural
convection)
Single-layer
(1s)
RθJMA
RθJMA
RθJB
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
57
39
23
52
39
28
°C/W
°C/W
°C/W
1,3
1,3
4
Four-layer
(2s2p)
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
—
Thermal
resistance,
junction to
board
—
—
RθJC
Thermal
resistance,
junction to case
17
3
15
3
°C/W
°C/W
5
6
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1.
2.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification.
3.
4.
5.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
6.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
9 Peripheral operating requirements and behaviors
9.1 Core modules
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
9.1.1 JTAG timing
Table 16. JTAG timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK frequency of operation
TCK clock pulse width
fOP
tPW
tDS
tDH
tDV
tTS
DC
50
5
SYS_CLK/ 16
MHz
ns
Figure 5
Figure 5
Figure 6
Figure 6
Figure 6
Figure 6
—
—
—
30
30
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
ns
5
ns
—
—
ns
ns
1/f
OP
t
t
PW
PW
V
IH
V
V
V
M
M
TCK
(Input)
IL
V
= V + (V – V )/2
IL IH IL
M
Figure 5. Test clock input timing diagram
TCK
(Input)
t
t
DH
DS
TDI
TMS
Input Data Valid
(Input)
t
DV
TDO
(Output)
Output Data Valid
t
TS
TDO
(Output)
Figure 6. Test access port timing diagram
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
45
System modules
9.2 System modules
9.2.1 Voltage regulator specifications
The voltage regulator supplies approximately 1.2 V to the MC56F84xxx’s core logic. For
proper operations, the voltage regulator requires an external 2.2 µF capacitor on each
VCAP pin. Ceramic and tantalum capacitors tend to provide better performance
tolerances. The output voltage can be measured directly on the VCAP pin. The
specifications for this regulator are shown in Table 17.
Table 17. Regulator 1.2 V parameters
Characteristic
Output Voltage1
Short Circuit Current2
Symbol
VCAP
ISS
Min
—
Typ
1.22
600
—
Max
—
Unit
V
—
—
mA
Short Circuit Tolerance (VCAP shorted to ground)
TRSC
—
30
Minutes
1. Value is after trim
2. Guaranteed by design
Table 18. Bandgap electrical specifications
Characteristic
Reference Voltage (after trim)
Symbol
Min
Typ
Max
Unit
VREF
—
1.21
—
V
9.3 Clock modules
9.3.1 External clock operation timing
Parameters listed are guaranteed by design.
Table 19. External clock operation timing requirements
Characteristic
Symbol
fosc
Min
Typ
Max
Unit
MHz
ns
Frequency of operation (external clock driver)1
Clock pulse width2
External clock input rise time3
—
—
50
tPW
8
—
trise
—
—
—
—
1
1
ns
External clock input fall time4
tfall
—
ns
Input high voltage overdrive by an external clock
Input low voltage overdrive by an external clock
Vih
0.85VDD
—
—
V
Vil
0.3VDD
V
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
46
Freescale Semiconductor, Inc.
System modules
1. See Figure 7 for detail on using the recommended connection of an external clock driver.
2. The chip may not function if the high or low pulse width is smaller than 6.25 ns.
3. External clock input rise time is measured from 10% to 90%.
4. External clock input fall time is measured from 90% to 10%.
V
IH
External
Clock
90%
50%
10%
90%
50%
10%
t
V
IL
t
fall
rise
t
t
PW
PW
Note: The midpoint is V + (V – V )/2.
IL
IH
IL
Figure 7. External clock timing
9.3.2 Phase-Locked Loop timing
Table 20. Phase-Locked Loop timing
Characteristic
PLL input reference frequency1
PLL output frequency2
Symbol
fref
Min
Typ
8
Max
Unit
MHz
MHz
µs
8
16
400
73.2
60
fop
—
PLL lock time3
tplls
35.5
40
Allowed Duty Cycle of input reference
tdc
50
%
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 80 MHz. If the NanoEdge PWM is available, the PLL output must
be set to above 320 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.
9.3.3 External crystal or resonator requirement
Table 21. Crystal or resonator requirement
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation
fXOSC
4
8
16
MHz
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
47
System modules
9.3.4 Relaxation oscillator timing
Table 22. Relaxation oscillator electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
MHz
kHz
8 MHz Output Frequency1
7.84
7.76
8
8
8.16
8.24
RUN Mode
• 0°C to 105°C
• -40°C to 105°C
266.8
402
554.3
Standby Mode (IRC trimmed @ 8 MHz)
• -40°C to 105°C
8 MHz Frequency Variation
RUN Mode
+/- 1.5
+/- 1.5
+/-2
+/-3
%
Due to temperature
• 0°C to 105°C
• -40°C to 105°C
32 kHz Output Frequency2
30.1
32
33.9
+/-4
kHz
%
RUN Mode
• -40°C to 105°C
32 kHz Output Frequency Variation
RUN Mode
+/-2.5
Due to temperature
• -40°C to 105°C
Stabilization Time
• 8 MHz output3
• 32 kHz output4
tstab
0.12
14.4
50
0.4
16.2
52
µs
%
Output Duty Cycle
48
1. Frequency after application of 8 MHz trim
2. Frequency after application of 32 kHz trim
3. Standby to run mode transition
4. Power down to run mode transition
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
48
Freescale Semiconductor, Inc.
System modules
Figure 8. Relaxation oscillator temperature variation (typical) after trim (preliminary)
9.4 Memories and memory interfaces
9.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
9.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
49
System modules
Table 23. NVM program/erase timing specifications (continued)
Symbol Description
Min.
—
Typ.
13
Max.
113
452
904
Unit
ms
Notes
thversscr Sector Erase high-voltage time
thversblk32k Erase Block high-voltage time for 32 KB
thversblk256k Erase Block high-voltage time for 256 KB
1
1
1
—
52
ms
—
104
ms
1. Maximum time based on expectations at cycling end-of-life.
9.4.1.2 Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
—
trd1blk32k
• 32 KB data flash
—
—
—
—
0.5
1.7
ms
ms
trd1blk256k
• 256 KB program flash
trd1sec1k Read 1s Section execution time (data flash
sector)
—
—
—
—
60
60
μs
μs
1
1
trd1sec2k Read 1s Section execution time (program flash
sector)
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 32 KB data flash
—
—
—
—
—
65
45
30
μs
μs
μs
1
1
tpgm4
145
—
2
tersblk32k
—
—
55
465
985
ms
ms
tersblk256k
• 256 KB program flash
122
tersscr
Erase Flash Sector execution time
Program Section execution time
• 512 B program flash
• 512 B data flash
—
14
114
ms
2
—
tpgmsec512p
tpgmsec512d
tpgmsec1kp
tpgmsec1kd
—
—
—
—
2.4
4.7
4.7
9.3
—
—
—
—
ms
ms
ms
ms
• 1 KB program flash
• 1 KB data flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
25
ms
μs
μs
ms
μs
—
1
trdonce
tpgmonce Program Once execution time
65
175
—
—
—
2
tersall
Erase All Blocks execution time
1500
30
tvfykey
Verify Backdoor Access Key execution time
Program Partition for EEPROM execution time
• 32 KB FlexNVM
1
—
tpgmpart32k
—
70
—
ms
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
50
Freescale Semiconductor, Inc.
System modules
Table 24. Flash command timing specifications (continued)
Symbol Description
Set FlexRAM Function execution time:
Min.
Typ.
Max.
Unit
Notes
—
tsetramff
tsetram8k
tsetram32k
• Control Code 0xFF
—
—
—
50
0.3
0.7
—
μs
ms
ms
• 8 KB EEPROM backup
• 32 KB EEPROM backup
0.5
1.0
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Byte-write to FlexRAM execution time:
—
teewr8b8k
teewr8b16k
teewr8b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
340
385
475
1700
1800
2000
μs
μs
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
—
—
Word-write to FlexRAM execution time:
teewr16b8k
teewr16b16k
teewr16b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
340
385
475
1700
1800
2000
μs
μs
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
—
—
Longword-write to FlexRAM execution time:
teewr32b8k
teewr32b16k
teewr32b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
545
630
810
1950
2050
2250
μs
μs
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
9.4.1.3 Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
51
System modules
9.4.1.4 Reliability specifications
Table 26. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
10 K
100
50 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
Write endurance
5
50
—
—
years
years
—
—
3
20
100
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
• EEPROM backup to FlexRAM ratio = 8192
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
20 M
100 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ 125 °C influenced by the
cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical
values assume all byte-writes to FlexRAM.
9.5 Analog
9.5.1 12-bit cyclic Analog-to-Digital Converter (ADC) parameters
Table 27. 12-bit ADC electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Recommended Operating Conditions
Supply Voltage1
Vrefh Supply Voltage2
ADC Conversion Clock3
Conversion Range
VDDA
Vrefhx
fADCCLK
RAD
2.7
3.0
3.3
3.6
VDDA
20
V
V
0.6
MHz
V
VREFL
VREFH
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
52
Freescale Semiconductor, Inc.
System modules
Table 27. 12-bit ADC electrical specifications (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Voltage Range
VADIN
V
VREFL
VSSA
VREFH
VDDA
External Reference
Internal Reference
Timing and Power
Conversion Time
tADC
tADS
tADPU
IADRUN
6
ADC Clock Cycles
ADC Clock Cycles
ADC Clock Cycles
mA
Sample Time
1
5
ADC Power-Up Time (from adc_pdn)
ADC RUN Current (per ADC block)
• at 600 kHz ADC Clock, LP mode
• ≤ 8.33 MHz ADC Clock, 00 mode
• ≤ 12.5 MHz ADC Clock, 01 mode
• ≤ 16.67 MHz ADC Clock, 10 mode
• ≤ 20 MHz ADC Clock, 11 mode
13
1
5.7
10.5
17.7
22.6
ADC Powerdown Current (adc_pdn enabled)
VREFH Current
IADPWRDWN
IVREFH
0.02
µA
µA
0.001
Accuracy (DC or Absolute)
Integral non-Linearity4
Differential non-Linearity4
Monotonicity
INL
+/- 3
+/- 5
LSB5
LSB5
DNL
+/- 0.6
+/- 0.9
Offset6
VOFFSET
LSB 4
+/- 17
+/- 20
+/- 25
• 1x gain mode
• 2x gain mode
• 4x gain mode
Gain Error (normalized)
EGAIN
0.994 to
1.004
0.990 to
1.010
AC Specifications7
Signal to Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal to Noise plus Distortion
Effective Number of Bits
ADC Inputs
SNR
THD
59
64
65
59
dB
dB
dB
dB
bits
SFDR
SINAD
ENOB
Input Leakage Current
Input Injection Current 8
Input Capacitance
IIN
IINJ
0
+/-2
+/-3
µA
mA
pF
CADI
-
Sampling Capacitor
• 1x mode
-
1.4
2.8
5.6
• 2x mode
• 4x mode
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
53
System modules
1. If the ADC’s reference is from VDDA: When VDDA is below 3.0 V, then the ADC functions, but the ADC specifications are
not guaranteed.
2. When the input is at the Vrefl level, then the resulting output will be all zeros (hex 000), plus any error contribution due to
offset and gain error. When the input is at the Vrefh level, then the output will be all ones (hex FFF), minus any error
contribution due to offset and gain error.
3. ADC clock duty cycle min/max is 45/55%
4. INL measured from VIN = VREFL to VIN = V
.
5. LSB = Least Significant Bit = 0.806 mV atR3EF.H3 V VDDA, x1 Gain Setting
6. Offset over the conversion range of 0025 to 4080, with internal/external reference.
7. Measured when converting a 1 kHz input Full Scale sine wave.
8. The current that can be injected into or sourced from an unselected ADC input, without affecting the performance of the
ADC.
9.5.1.1 Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2 are
always opened/closed at non-overlapping phases, and both S1 and S2 operate at the ADC
clock frequency. The following equation gives equivalent input impedance when the
input is selected.
1
100ohm + 125ohm
+
-12
(ADC ClockRate) x 1.4x10
C1: Single Ended Mode
2XC1: Differential Mode
Channel Mux
equivalent resistance
100Ohms
S1
125 ESD
Resistor
Analog Input
C1
C1
S1
S1
S/H
3
1
2
S1
S2
S2
(VREFHx - VREFLx ) / 2
C1: Single Ended Mode
2XC1: Differential Mode
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. 8 pF noise damping capacitor
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 (4.8pF) is normally
disconnected from the input, and is only connected to the input at sampling time.
5. S1 and S2 switch phases are non-overlapping and operate at the ADC clock
frequency
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
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Freescale Semiconductor, Inc.
System modules
S1
S2
Figure 9. Equivalent circuit for A/D loading
9.5.2 16-bit SAR ADC electrical specifications
9.5.2.1 16-bit ADC operating conditions
Table 28. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
2.7
Typ.1
Max.
3.6
Unit
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
V
mV
mV
V
—
2
Delta to VDD (VDD – VDDA
)
-100
-100
VDDA
0
+100
+100
VDDA
Delta to VSS (VSS – VSSA
Absolute
)
0
2
ADC reference
voltage high
VDDA
3
VREFL
ADC reference
voltage low
Absolute
VSSA
VSSA
VSSA
V
4
VADIN
CADIN
Input voltage
VSSA
—
—
8
VDDA
10
V
—
—
Input capacitance
• 16-bit mode
pF
• 8-bit / 10-bit / 12-bit
modes
—
4
5
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
5
Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 12-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
6
6
7
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 12-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
7
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
55
System modules
3. VREFH is internally tied to VDDA
.
4. VREFL is internally tied to VSSA
.
5. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
6. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
7. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 10. ADC input impedance equivalency diagram
9.5.2.2 16-bit ADC electrical characteristics
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
Typ.2
Max.
1.7
3.9
7.3
6.1
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC
asynchronous
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
clock source
fADACK
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 16-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
-1 to +4
0.7
—
—
0.2
-0.3 to 0.5
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
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Freescale Semiconductor, Inc.
System modules
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
—
Typ.2
Max.
—
Unit
Notes
INL
Integral non-
linearity
• 16-bit modes
• 12-bit modes
• <12-bit modes
• 12-bit modes
• <12-bit modes
7.0
LSB4
5
—
1.0
-2.7 to +1.9
-0.7 to +0.5
-5.4
—
0.5
EFS
Full-scale error
—
-4
LSB4
LSB4
VADIN
=
VDDA
—
-1.4
-1.8
5
6
EQ
Quantization
error
• 16-bit modes
• 12-bit modes
—
—
-1 to 0
—
—
0.5
ENOB
Effective number 16-bit single-ended mode
of bits
• Avg=32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg=4
12-bit single-ended mode
• Avg=32
10.8
10.2
—
—
bits
bits
• Avg=1
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16-bit single-ended mode
• Avg=32
7
7
—
-85
—
dB
12-bit single-ended mode
• Avg=32
—
-74
90
—
—
dB
dB
SFDR
Spurious free
dynamic range
16-bit single-ended mode
• Avg=32
78
12-bit single-ended mode
• Avg=32
78
—
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the
device's
voltage
and current
operating
ratings)
Temp sensor
slope
–40°C to 105°C
25°C
—
—
1.715
722
—
—
mV/°C
mV
VTEMP25 Temp sensor
voltage
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
57
System modules
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operations: the ADLPC bit should be set, the HSC bit should be clear, with 1MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz. When running 12-bit Cyclic ADC and 12-bit DAC, some
degradation of ENOB (of 16-bit SAR ADC) may occur.
7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz.
8. System Clock = 4 MHz, ADC Clock = 2 MHz, AVG = Max, Long Sampling = Max
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
Averaging of 4 samples
Averaging of 32 samples
11.00
1
2
3
4
5
6
7
8
9
10 11
12
ADC Clock Frequency (MHz)
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
9.5.3 12-bit Digital-to-Analog Converter (DAC) parameters
Table 30. DAC parameters
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
DC Specifications
Resolution
Settling time1
12
—
12
1
12
bits
µs
At output load
RLD = 3 kΩ
CLD = 400 pF
Power-up time
Time from release of PWRDWN
signal until DACOUT signal is valid
tDAPU
—
—
—
11
µs
Accuracy
INL
Integral non-linearity2
Range of input digital words:
410 to 3891 ($19A - $F33)
+/- 3
+/- 4
LSB3
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
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Freescale Semiconductor, Inc.
System modules
Table 30. DAC parameters (continued)
Parameter
Conditions/Comments
Range of input digital words:
410 to 3891 ($19A - $F33)
> 6 sigma monotonicity,
Symbol
Min
Typ
Max
Unit
Differential non-
linearity2
DNL
—
+/- 0.8
+/- 0.9
LSB3
Monotonicity
Offset error2
Gain error2
guaranteed
+/- 25
—
mV
%
< 3.4 ppm non-monotonicity
Range of input digital words:
410 to 3891 ($19A - $F33)
VOFFSET
—
—
+/- 43
Range of input digital words: 410 to
3891 ($19A - $F33)
EGAIN
+/- 0.5
+/- 1.5
DAC Output
Output voltage range Within 40 mV of either VSSA or VDDA
VOUT
VSSA
0.04 V
+
—
VDDA - 0.04
V
V
AC Specifications
SNR
Signal-to-noise ratio
—
—
85
—
—
dB
dB
Spurious free dynamic
range
SFDR
-72
Effective number of bits
ENOB
—
11
—
bits
1. Settling time is swing range from VSSA to VDDA
2. No guaranteed specification within 5% of VDDA or VSSA
3. LSB = 0.806 mV
9.5.4 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
2.7
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, high-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
13
48
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
105
148
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
—
50
—
V
V
0.5
Propagation delay, high-speed mode (EN=1,
PMODE=1)2
ns
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
59
System modules
Table 31. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
250
ns
Analog comparator initialization delay3
6-bit DAC current adder (enabled)
6-bit DAC reference inputs: Vin1,Vin2
—
—
—
7
40
—
μs
μA
V
IDAC6b
VDDA
—
VDD
There are two reference input options selectable (via
VRSEL control bit). The reference options must fall
within this range.
INL
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
–0.5
–0.3
—
—
0.5
0.3
LSB4
LSB
DNL
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Signal swing is 100 mV
3. Comparator initialization delay is defined as the time between software writes (to DACEN, VRSEL, PSEL, MSEL, VOSEL),
to change the control inputs and for the comparator output to settle to a stable level.
4. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
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Freescale Semiconductor, Inc.
PWMs and timers
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
9.6 PWMs and timers
9.6.1 Enhanced NanoEdge PWM characteristics
Table 32. NanoEdge PWM timing parameters
Characteristic
Symbol
pwmp
tpu
Min
Typ
80
Max
Unit
MHz
ps
PWM clock frequency
77.5
82.5
NanoEdge Placement (NEP) Step Size1, 2
Delay for fault input activating to PWM output deactivated
Power-up Time3
390
1
ns
25
µs
1. Reference IPbus clock of 80 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
61
PWMs and timers
9.6.2 Quad Timer timing
Parameters listed are guaranteed by design.
Table 33. Timer timing
Characteristic
Timer input period
Symbol
PIN
Min1
2T + 6
1T + 3
25
Max
—
Unit
ns
See Figure
Figure 14
Figure 14
Figure 14
Figure 14
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
12.5
—
ns
1. T = clock cycle. For 80 MHz operation, T = 12.5 ns.
Timer Inputs
P
P
INHL
INHL
P
IN
Timer Outputs
P
P
OUTHL
OUTHL
P
OUT
Figure 14. Timer timing
9.7 Communication interfaces
9.7.1 Queued Serial Peripheral Interface (SPI) timing
Parameters listed are guaranteed by design.
Table 34. SPI timing
Characteristic
Cycle time
Master
Symbol
Min
Max
Unit
See Figure
Figure 15
Figure 16
Figure 17
Figure 18
tC
45
45
—
—
ns
ns
Slave
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
62
Freescale Semiconductor, Inc.
PWMs and timers
Table 34. SPI timing (continued)
Characteristic
Enable lead time
Master
Symbol
Min
Max
Unit
See Figure
tELD
Figure 18
—
—
—
ns
ns
Slave
Enable lag time
Master
tELG
Figure 18
—
—
—
ns
ns
Slave
Clock (SCK) high time
Master
tCH
Figure 15
Figure 16
Figure 17
Figure 18
Figure 18
20
20
—
—
ns
ns
Slave
Clock (SCK) low time
tCL
20
20
—
—
ns
ns
Master
Slave
Data set-up time required for inputs
tDS
Figure 15
Figure 16
Figure 17
Figure 18
Figure 15
Figure 16
Figure 17
Figure 18
Figure 18
20
1
—
—
ns
ns
Master
Slave
Data hold time required for inputs
tDH
1
3
—
—
ns
ns
Master
Slave
Access time (time to data active
from high-impedance state)
tA
5
5
—
—
ns
ns
Slave
Disable time (hold time to high-
impedance state)
tD
Figure 18
Slave
Data valid for outputs
Master
tDV
Figure 15
Figure 16
Figure 17
Figure 18
Figure 15
Figure 16
Figure 17
Figure 18
—
—
6.25
18.7
ns
ns
Slave (after enable edge)
Data invalid
Master
tDI
0
0
—
—
ns
ns
Slave
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
63
PWMs and timers
Table 34. SPI timing (continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Figure 15
Figure 16
Figure 17
Figure 18
Figure 15
Figure 16
Figure 17
Figure 18
Rise time
Master
Slave
tR
—
—
1
1
ns
ns
Fall time
Master
Slave
tF
—
—
1
1
ns
ns
SS
(Input)
SS is held high on master
t
C
t
R
t
F
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
R
t
CL
SCLK (CPOL = 1)
(Output)
t
t
DH
CH
t
DS
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t (ref)
DI
t
DI
DV
MOSI
(Output)
Master MSB out
Bits 14–1
Master LSB out
t
t
R
F
Figure 15. SPI master timing (CPHA = 0)
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
64
Freescale Semiconductor, Inc.
PWMs and timers
SS
(Input)
SS is held High on master
t
C
t
F
t
R
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
CL
SCLK (CPOL = 1)
(Output)
t
CH
t
DS
t
R
t
DH
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t
(ref)
DI
t
DV
t (ref)
DV
DI
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
t
t
R
F
Figure 16. SPI master timing (CPHA = 1)
SS
(Input)
t
C
t
F
t
ELG
t
CL
t
R
SCLK (CPOL = 0)
(Input)
t
CH
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
CH
t
F
t
t
A
R
t
D
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DS
DV
t
t
DI
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 17. SPI slave timing (CPHA = 0)
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
65
PWMs and timers
SS
(Input)
t
F
t
C
t
R
t
CL
SCLK (CPOL = 0)
(Input)
t
CH
t
ELG
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
t
DV
CH
t
R
t
t
D
t
A
F
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DV
DS
t
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 18. SPI slave timing (CPHA = 1)
9.7.2 Queued Serial Communication Interface (SCI) timing
Parameters listed are guaranteed by design.
Table 35. SCI timing
Characteristic
Baud rate1
Symbol
BR
Min
—
Max
Unit
Mbit/s
ns
See Figure
—
(fMAX/16)
1.04/BR
1.04/BR
RXD pulse width
TXD pulse width
RXDPW
TXDPW
0.965/BR
0.965/BR
Figure 19
Figure 20
ns
LIN Slave Mode
Deviation of slave node clock from nominal FTOL_UNSYNCH
clock rate before synchronization
-14
14
2
%
%
—
—
Deviation of slave node clock relative to
the master node clock after
synchronization
FTOL_SYNCH
-2
Minimum break character length
TBREAK
13
11
—
—
Master
node bit
periods
—
—
Slave node
bit periods
1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.160 MHz
depending on part number) or 2x bus clock (max. MHz) for the devices.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
66
Freescale Semiconductor, Inc.
PWMs and timers
RXD
SCI receive
data pin
RXD
PW
(Input)
Figure 19. RXD pulse width
TXD
SCI transmit
data pin
TXD
PW
(output)
Figure 20. TXD pulse width
9.7.3 Freescale’s Scalable Controller Area Network (FlexCAN)
Table 36. FlexCAN Timing Parameters
Characteristic
Baud Rate
Symbol
BRCAN
Min
—
—
5
Max
1
Unit
Mbps
µs
CAN Wakeup dominant pulse filtered
CAN Wakeup dominant pulse pass
TWAKEUP
TWAKEUP
2
—
µs
CAN_RX
CAN receive
data pin
T
WAKEUP
(Input)
Figure 21. Bus Wake-up Detection
9.7.4 Inter-Integrated Circuit Interface (I2C) timing
Table 37. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
400
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
0.91
—
µs
ns
ns
Data set-up time
6
Rise time of SDA and SCL signals
1000
20 +0.1Cb
300
Table continues on the next page...
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
67
Design Considerations
Table 37. I 2C timing (continued)
Characteristic
Symbol
Standard Mode
Minimum Maximum
300
Fast Mode
Unit
Minimum Maximum
5
Fall time of SDA and SCL signals
Set-up time for STOP condition
tf
—
20 +0.1Cb
0.6
300
—
ns
µs
µs
tSU; STO
tBUF
4
—
—
Bus free time between STOP and
START condition
4.7
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tHD; STA
tSU; STO
S
SR
P
S
tHD; DAT
tHIGH
Figure 22. Timing definition for fast and standard mode devices on the I2C bus
10 Design Considerations
10.1 Thermal design considerations
An estimate of the chip junction temperature (TJ) can be obtained from the equation:
TJ = TA + (RΘJA x PD)
Where,
TA = Ambient temperature for the package (°C)
RΘJA = Junction-to-ambient thermal resistance (°C/W)
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
68
Freescale Semiconductor, Inc.
Design Considerations
PD = Power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry-standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single-layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which TJ value is closer to the application depends on the power
dissipated by other components on the board.
• The TJ value obtained on a single layer board is appropriate for a tightly packed
printed circuit board.
• The TJ value obtained on a board with the internal planes is usually appropriate if the
board has low-power dissipation and if the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-
case thermal resistance and a case-to-ambient thermal resistance:
RΘJA = RΘJC + RΘCA
Where,
RΘJA = Package junction-to-ambient thermal resistance (°C/W)
RΘJC = Package junction-to-case thermal resistance (°C/W)
RΘCA = Package case-to-ambient thermal resistance (°C/W)
RΘJC is device related and cannot be adjusted. You control the thermal environment to
change the case to ambient thermal resistance, RΘCA. For instance, you can change the
size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat
sinks are not used, the thermal characterization parameter (YJT) can be used to
determine the junction temperature with a measurement of the temperature at the top
center of the package case using the following equation:
TJ = TT + (ΨJT x PD)
Where,
TT = Thermocouple temperature on top of package (°C/W)
ΨJT = hermal characterization parameter (°C/W)
PD = Power dissipation in package (W)
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
69
Design Considerations
The thermal characterization parameter is measured per JESD51–2 specification using a
40-gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
To determine the junction temperature of the device in the application when heat
sinks are used, the junction temperature is determined from a thermocouple inserted at
the interface between the case of the package and the interface material. A clearance slot
or hole is normally required in the heat sink. Minimizing the size of the clearance is
important to minimize the change in thermal performance caused by removing part of the
thermal interface to the heat sink. Because of the experimental difficulties with this
technique, many engineers measure the heat sink temperature and then back-calculate the
case temperature using a separate measurement of the thermal resistance of the interface.
From this case temperature, the junction temperature is determined from the junction-to-
case thermal resistance.
10.2 Electrical design considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the device:
• Provide a low-impedance path from the board power supply to each VDD pin on the
device and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as
near as possible to the package supply pins. The recommended bypass configuration
is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA
Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the
chip VDD and VSS (GND) pins are as short as possible.
.
• Bypass the VDD and VSS with approximately 100 µF, plus the number of 0.1 µF
ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
70
Freescale Semiconductor, Inc.
Obtaining package dimensions
• Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.
• Using separate power planes for VDD and VDDA and separate ground planes for VSS
and VSSA are recommended. Connect the separate analog and digital power and
ground planes as near as possible to power supply outputs. If an analog circuit and
digital circuit are powered by the same power supply, then connect a small inductor
or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted
together.
• Physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. Place an analog
ground trace around an analog signal trace to isolate it from digital traces.
• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,
or I2C, the designer should provide an interface to this port if in-circuit flash
programming is desired.
• If desired, connect an external RC circuit to the RESET pin. The resistor value
should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of
0.22 µF–4.7 µF.
• Configuring the RESET pin to GPIO output in normal operation in a high-noise
environment may help to improve the performance of noise transient immunity.
• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a
restate during normal operation if JTAG converter is not present.
• During reset and after reset but before I/O initialization, all I/O pins are at tri-state.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than
33 pF 10Ω RC filter.
11 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
Drawing for package
48-pin LQFP
Document number to be used
98ASH00962A
64-pin LQFP
98ASS23234W
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
71
Pinout
12 Pinout
12.1 Signal Multiplexing and Pin Assignments
This section shows the signals available on each package pin and the locations of these
pins on the devices supported by this document. The SIM's GPS registers are responsible
for selecting which ALT functionality is available on most pins.
NOTE
The RESETB pin is a 3.3 V pin only.
NOTE
If the GPIOC1 pin is used as GPIO, the XOSC should be
powered down.
NOTE
PWMB signals—including PWMB_2A, PWMB_2B, and
PWMB_3X—are not available on the 64 LQFP package or the
48 LQFP package.
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP
1
2
1
2
TCK
TCK
GPIOD2
GPIOD4
EXTAL
XTAL
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOB7
GPIOC5
GPIOB6
GPIOB5
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOB7
GPIOC5
GPIOB6
GPIOB5
3
3
CLKIN0
4
4
5
5
TXD0
RXD0
TA0
TB0
XB_IN2
CMPD_O
RXD0
CLKO0
CLKIN1
6
—
6
TB1
7
CMPA_O
CMPB_O
8
7
TA1
XB_IN8
EWM_OUT_B
9
—
—
—
8
ANA7&ANC11
10
11
12
13
14
15
16
17
18
19
20
ANA6&ANC10
ANA5&ANC9
ANA4&ANC8&CMPD_IN0
ANA0&CMPA_IN3
9
CMPC_O
XB_IN7
10
11
12
—
13
—
—
ANA1&CMPA_IN0
ANA2&VREFHA&CMPA_IN1
ANA3&VREFLA&CMPA_IN2
ANB7&ANC15&CMPB_IN2
DACO
ANB6&ANC14&CMPB_IN1
ANB5&ANC13&CMPC_IN2
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
72
Freescale Semiconductor, Inc.
Pinout
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
14
15
16
17
18
19
20
21
—
22
23
24
25
26
27
28
29
30
—
—
—
—
31
32
33
34
35
36
37
38
39
40
—
—
41
42
43
—
—
44
45
GPIOB4
VDDA
GPIOB4
VDDA
ANB4&ANC12&CMPC_IN1
VSSA
VSSA
GPIOB0
GPIOB1
VCAP
GPIOB0
GPIOB1
VCAP
ANB0&CMPB_IN3
ANB1&CMPB_IN0
GPIOB2
GPIOB3
VDD
GPIOB2
GPIOB3
VDD
ANB2&VREFHB&CMPC_IN3
ANB3&VREFLB&CMPC_IN0
VSS
VSS
GPIOC6
GPIOC7
GPIOC8
GPIOC9
GPIOC10
GPIOF0
GPIOC11
GPIOC12
GPIOF2
GPIOF3
GPIOF4
GPIOF5
VSS
GPIOC6
GPIOC7
GPIOC8
GPIOC9
GPIOC10
GPIOF0
GPIOC11
GPIOC12
GPIOF2
GPIOF3
GPIOF4
GPIOF5
VSS
TA2
XB_IN3
TXD0
CMP_REF
XB_IN9
SS0_B
MISO0
SCLK0
MOSI0
XB_IN6
CANTX
CANRX
SCL1
RXD0
XB_IN4
XB_IN5
TB2
MISO0
SCLK1
TXD1
SCL1
SDA1
RXD1
XB_OUT6
XB_OUT7
XB_OUT8
XB_OUT9
SDA1
TXD1
RXD1
VDD
VDD
GPIOE0
GPIOE1
GPIOE2
GPIOE3
GPIOC13
GPIOF1
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOC14
GPIOC15
VCAP
GPIOE0
GPIOE1
GPIOE2
GPIOE3
GPIOC13
GPIOF1
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOC14
GPIOC15
VCAP
PWMA_0B
PWMA_0A
PWMA_1B
PWMA_1A
TA3
XB_IN6
XB_IN7
XB_IN2
XB_IN3
XB_IN4
XB_IN5
XB_OUT4
XB_OUT5
EWM_OUT_B
CMPD_O
CLKO1
PWMA_2B
PWMA_2A
PWMA_3B
PWMA_3A
SDA0
SCL0
GPIOF6
GPIOF7
VDD
GPIOF6
GPIOF7
VDD
TB2
TB3
PWMA_3X
CMPC_O
XB_IN2
XB_IN3
SS1_B
VSS
VSS
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
73
Pinout
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP
62
63
64
46
47
48
TDO
TMS
TDI
TDO
TMS
TDI
GPIOD1
GPIOD3
GPIOD0
12.2 Pinout diagrams
The following diagrams show pinouts for the packages. For each pin, the diagrams show
the default function. However, many signals may be multiplexed onto a single pin.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
74
Freescale Semiconductor, Inc.
Pinout
TCK
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIOE3
GPIOE2
GPIOE1
GPIOE0
VDD
2
3
4
5
6
VSS
7
GPIOF5
GPIOF4
GPIOF3
GPIOF2
GPIOC12
GPIOC11
GPIOF0
GPIOC10
GPIOC9
GPIOC8
8
9
10
11
12
13
14
15
16
Figure 23. 64-pin LQFP
NOTE
The RESETB pin is a 3.3 V pin only.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
75
Pinout
GPIOE3
GPIOE2
GPIOE1
GPIOE0
VDD
36
35
34
33
32
31
30
29
28
27
26
25
TCK
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOC3
GPIOC4
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
1
2
3
4
5
VSS
6
GPIOC12
GPIOC11
GPIOF0
GPIOC10
GPIOC9
GPIOC8
7
8
9
10
11
12
Figure 24. 48-pin LQFP
NOTE
The RESETB pin is a 3.3 V pin only.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
76
Freescale Semiconductor, Inc.
Product documentation
13 Product documentation
The documents listed in Table 38 are required for a complete description and proper
design with the device. Documentation is available from local Freescale distributors,
Freescale Semiconductor sales offices, or online at freescale.com.
Table 38. Device documentation
Topic
Description
Document Number
DSP56800E/DSP56800EX
Reference Manual
Detailed description of the 56800EX family architecture, 32-bit
digital signal controller core processor, and the instruction set
DSP56800ERM
MC56F8455x Reference Manual Detailed functional description and programming model
MC56F8455XRM
MC56F8455X
MC56F8455x Data Sheet
Electrical and timing specifications, pin descriptions, and
package information (this document)
MC56F84xxx Errata
Details any chip issues that might be present
MC56F84XXX_0N27E
14 Revision history
The following table summarizes changes to this document since the release of the
previous version.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
Freescale Semiconductor, Inc.
77
Revision history
Table 39. Revision history
Rev.
Date
06/2014 Changes include:
• Correction to "PWMs and timers" feature group on page 1
Substantial Changes
3
• Updates and corrections to "56F844xx/5xx/7xx family" table.
• In "Interrupt Controller" section, added info about Interrupt level 3.
• In "Enhanced Flex Pulse Width Modulator (eFlexPWM)" section,
• Upated PWM frequencies based on device frequency, plus updated resolution of
fractional clock digital dithering.
• Updated feature list.
• Added new section "MC56F844xx signal and pin descriptions".
• In "Signal groups" section, in "Functional Group Pin Allocations" table, made corrections to
"Functional Group Pin Allocations" table.
• In "Voltage and current operating requirements" section, added RESET voltage high to
"Recommended Operating Conditions" table.
• In "Voltage and current operating behaviors" section, in "DC Electrical Characteristics" table,
updated Digital Input Current High for Pin Group 2.
• For "Power mode transition operating behaviors" section,
• Changed the name to "Power mode operating behaviors".
• In "Reset, Stop, Wait, and Interrupt Timing" table, updated "RESET deassertion to First
Address Fetch" parameters.
• Added new table "Power-On-Reset mode transition times".
• In "Power consumption operating behaviors" section, updated mode currrent values in
"Current Consumption" table.
• In "JTAG Timing" section, changed "TCK frequency of operation" to SYS_CLK/16 from
SYS_CLK/8.
• In "System modules" section, in "Voltage regulator specifications" section, in "Regulator 1.2 V
parameters" table, updated "Short Circuit Current" parameter.
• In "Relaxation Oscillator Timing" section, updates in "Relaxation Oscillator Electrical
Specifications" table.
• In "Memories and memory interfaces" section,
• "Flash Memory Characteristics" section is now called "Flash electrical specifications"
section.
• Added new section "Flash timing specifications — program and erase", where the
"Flash Timing Parameters" table (now called "NVM program/erase timing specifications"
table, and table was updated.
• Added new section "Flash high voltage current behaviors".
• In "Analog" section, in "12-bit cyclic Analog-to-Digital Converter (ADC) parameters" section,
updated "12-bit ADC electrical specifications" table.
• In "Pinout" section, in "Signal Multiplexing and Pin Assignments" section,
• Added 3 notes.
• In pin mux table, changed SCK0 to SCLK0, SCK1 to SCLK1, updates to 64LQFP[62-64]
and 48LQFP[46-48].
• In "64-pin LQFP" figure, made updates to pins 62-64, and added a note.
• In "48-pin LQFP" figure, made updates to pins 46-48, and added a note.
• In "Product Documentation" section, in "Device Documentation" table, removed Serial
Bootloader User Guide, because it is not used for these devices.
MC56F8455X / MC56F8454X Data Sheet, Rev. 3, 06/2014.
78
Freescale Semiconductor, Inc.
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Rev. 3, 06/2014
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