MC68HRC908JL3EMDW [NXP]
MC68HRC908JL3EMDW;
| 型号： | MC68HRC908JL3EMDW |
| 厂家： | 
NXP |
| 描述： | MC68HRC908JL3EMDW |
| 文件： | 总172页 (文件大小：1006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
MC68HLC908JL3E/JK3E/JK1E
MC68HC908KL3E/KK3E
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
Data Sheet
M68HC08
Microcontrollers
MC68HC908JL3E
Rev. 3
11/2004
freescale.com
MC68HC908JL8/JK3E/JK1E
MC68HRC908JL8/JK3E/JK1E
MC68HLC908JL8/JK3E/JK1E
MC68HC908KL3E/KK3E
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
3
Revision History
Revision
Level
Page
Number(s)
Date
Description
Added appendix B for ROM parts.
159–166
167–170
153–224
Nov 2004
3
Added appendix C for ADC-less parts.
Added appendix A for low-volt devices.
Dec 2002
May 2002
2
2
Updated Monitor Mode Circuit (Figure 7-1) and Monitor Mode Entry
Requirements and Options (Table 7-1) in Monitor ROM section.
76, 77
—
First general release.
MC68HC908JL3E Family Data Sheet, Rev. 3
4
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Chapter 3 Configuration Registers (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chapter 5 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Chapter 6 Oscillator (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Chapter 9 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Chapter 10 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Chapter 11 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Chapter 12 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Chapter 13 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Chapter 14 Low Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Chapter 15 Break Module (BREAK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Chapter 17 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Chapter 18 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Appendix A MC68HLC908JL3E/JK3E/JK1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Appendix B MC68H(R)C08JL3E/JK3E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Appendix C MC68HC908KL3E/KK3E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
5
List of Chapters
MC68HC908JL3E Family Data Sheet, Rev. 3
6
Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.10 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.11 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.12 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 3
Configuration Registers (CONFIG)
3.1
3.2
3.3
3.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 4
Central Processor Unit (CPU)
4.1
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3.1
4.3.2
4.3.3
4.3.4
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
7
Table of Contents
4.3.5
4.4
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5
4.5.1
4.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6
4.7
4.8
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 5
System Integration Module (SIM)
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2
SIM Bus Clock Control and Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.3.2.1
5.3.2.2
5.3.2.3
5.3.2.4
5.3.2.5
Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.4
SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.4.1
5.4.2
5.4.3
5.5
5.5.1
Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5.1.1
5.5.1.2
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.5.3
5.5.4
5.5.5
5.6
5.6.1
5.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.7
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.7.1
5.7.2
5.7.3
MC68HC908JL3E Family Data Sheet, Rev. 3
8
Freescale Semiconductor
Chapter 6
Oscillator (OSC)
6.1
6.2
6.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RC Oscillator (MC68HRC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
X-tal Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.5
6.5.1
6.5.2
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.6
Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Chapter 7
Monitor ROM (MON)
7.1
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 8
Timer Interface Module (TIM)
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.4
8.4.1
8.4.2
8.4.3
8.4.3.1
8.4.3.2
8.4.4
8.4.4.1
8.4.4.2
8.4.4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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8.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.6
8.6.1
8.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.7
8.8
TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.9
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TIM Channel Status and Control Registers (TSC0:TSC1). . . . . . . . . . . . . . . . . . . . . . . . . . 95
TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
Chapter 9
Analog-to-Digital Converter (ADC)
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.5
9.5.1
9.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.6
9.6.1
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.7
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9.7.1
9.7.2
9.7.3
Chapter 10
Input/Output (I/O) Ports
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.2 Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.2.1
10.2.2
10.2.3
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.3 Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.3.1
10.3.2
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.4.1
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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10.4.2
10.4.3
Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Chapter 11
External Interrupt (IRQ)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.3.1
IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.4 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.5 IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Chapter 12
Keyboard Interrupt Module (KBI)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.4.1
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.5 Keyboard Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.5.1
12.5.2
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.6.1
12.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Chapter 13
Computer Operating Properly (COP)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.6 Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.7.1
13.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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Chapter 14
Low Voltage Inhibit (LVI)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.4 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.5.1
14.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 15
Break Module (BREAK)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
15.3.1
15.3.2
15.3.3
15.3.4
Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
15.4 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
15.4.1
15.4.2
15.4.3
15.4.4
Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.5.1
15.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Chapter 16
Electrical Specifications
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
16.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
16.5 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
16.6 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
16.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
16.8 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
16.9 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
16.10 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
16.11 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
16.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC68HC908JL3E Family Data Sheet, Rev. 3
12
Freescale Semiconductor
Chapter 17
Mechanical Specifications
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
17.2 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
17.3 20-Pin SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.4 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.5 28-Pin SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
17.6 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Chapter 18
Ordering Information
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Appendix A
MC68HLC908JL3E/JK3E/JK1E
A.1
A.2
A.3
A.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Oscillator Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
A.5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
A.5.1
A.5.2
A.5.3
A.5.4
A.5.5
A.5.6
A.6
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Appendix B
MC68H(R)C08JL3E/JK3E
B.1
B.2
B.3
B.4
B.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
B.6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
B.6.1
B.6.2
B.6.3
B.7
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
13
Table of Contents
Appendix C
MC68HC908KL3E/KK3E
C.1
C.2
C.3
C.4
C.5
C.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
MC68HC908JL3E Family Data Sheet, Rev. 3
14
Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68H(R)C908JL3E is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit
(CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
A list of MC68H(R)C908JL3E device variations is shown in Table 1-1.
Table 1-1. Summary of Device Variations
Device
Type
Operating
Voltage
Oscillator
Option
Pin
Count
LVI
ADC
Memory
Device
28
20
20
28
20
20
28
20
20
28
20
28
20
28
20
MC68HC908JL3E
MC68HC908JK3E
MC68HC908JK1E
MC68HRC908JL3E
MC68HRC908JK3E
MC68HRC908JK3E
MC68HLC908JL3E
MC68HLC908JK3E
MC68HLC908JK1E
MC68HC08JL3E
4,096 bytes FLASH
1,536 bytes FLASH
4,096 bytes FLASH
1,536 bytes FLASH
4,096 bytes FLASH
1,536 bytes FLASH
XTAL
RC
FLASH
3V, 5V
Yes
Yes
LowVoltage
FLASH(1)
2.2 to 5.5V
No
Yes
XTAL
XTAL
RC
MC68HC08JK3E
ROM(2)
3V, 5V
3V, 5V
Yes
Yes
Yes
No
4,096 bytes ROM
MC68HRC08JL3E
MC68HRC08JK3E
MC68HC908KL3E
MC68HC908KK3E
FLASH,
ADC-less(3)
XTAL
4,096 bytes FLASH
1. Low-voltage FLASH devices are documented in Appendix A MC68HLC908JL3E/JK3E/JK1E.
2. ROM devices are documented in Appendix B MC68H(R)C08JL3E/JK3E.
3. FLASH, ADC-less devices are documented in Appendix C MC68HC908KL3E/KK3E.
All references to the MC68H(R)C908JL3E in this data book apply equally to the MC68H(R)C908JK3E
and MC68H(R)C908JK1E, unless otherwise stated.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
15
General Description
1.2 Features
Features of the MC68H(R)C908JL3E include the following:
•
•
•
•
•
EMC enhanced version of MC68H(R)C908JL3/JK3/JK1
High-performance M68HC08 architecture
Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
Low-power design; fully static with stop and wait modes
Maximum internal bus frequency:
–
–
8-MHz at 5V operating voltage
4-MHz at 3V operating voltage
•
•
Oscillator options:
–
–
Crystal oscillator for MC68HC908JL3E/JK3E/JK1E
RC oscillator for MC68HRC908JL3E/JK3E/JK1E
User program FLASH memory with security(1) feature
–
–
4,096 bytes for MC68H(R)C908JL3E/JK3E
1,536 bytes for MC68H(R)C908JK1E
•
•
•
•
128 bytes of on-chip RAM
2-channel, 16-bit timer interface module (TIM)
12-channel, 8-bit analog-to-digital converter (ADC)
23 general purpose I/O ports for MC68H(R)C908JL3E:
–
7 keyboard interrupt with internal pull-up
(6 keyboard interrupt for MC68HC908JL3E)
10 LED drivers (sink)
–
–
2 × 25mA open-drain I/O with pull-up
•
•
15 general purpose I/O ports for MC68H(R)C908JK3E/JK1E:
–
1 keyboard interrupt with internal pull-up
(MC68HRC908JK3E/JK1E only)
4 LED drivers (sink)
2 × 25mA open-drain I/O with pull-up
10-channel ADC
–
–
–
System protection features:
–
–
–
–
Optional computer operating properly (COP) reset
Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation
Illegal opcode detection with reset
Illegal address detection with reset
•
•
•
•
Master reset pin with internal pull-up and power-on reset
IRQ1 with schmitt-trigger input and programmable pull-up
28-pin PDIP, 28-pin SOIC, and 48-pin LQFP packages for MC68H(R)C908JL3E
20-pin PDIP and 20-pin SOIC packages for MC68H(R)C908JK3E/JK1E
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908JL3E Family Data Sheet, Rev. 3
16
Freescale Semiconductor
MCU Block Diagram
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68H(R)C908JL3E.
INTERNAL BUS
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
PTA6/KBI6**¥
PTA5/KBI5**‡
PTA4/KBI4**‡
PTA3/KBI3**‡
PTA2/KBI2**‡
PTA1/KBI1**‡
PTA0/KBI0**‡
CONTROL AND STATUS REGISTERS — 64 BYTES
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
#
USER FLASH:
MC68H(R)C908JK3E/JL3E — 4,096 BYTES
MC68H(R)C908JK1E — 1,536 BYTES
USER RAM — 128 BYTES
MONITOR ROM — 960 BYTES
2-CHANNEL TIMER INTERFACE
MODULE
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
PTB1/ADC1
PTB0/ADC0
BREAK
MODULE
USER FLASH VECTOR SPACE — 48 BYTES
MC68HC908JL3E/JK3E/JK1E
OSC1
X-TAL OSCILLATOR
¥ OSC2
COMPUTER OPERATING
PROPERLY MODULE
PTD7**†‡
MC68HRC908JL3E/JK3E/JK1E
RC OSCILLATOR
PTD6**†‡
PTD5/TCH1
PTD4/TCH0
PTD3/ADC8‡
PTD2/ADC9‡
POWER-ON RESET
MODULE
SYSTEM INTEGRATION
MODULE
PTD1/ADC10
#
* RST
PTD0/ADC11
LOW-VOLTAGE INHIBIT
MODULE
EXTERNAL INTERRUPT
MODULE
* IRQ1
* Pin contains integrated pull-up device.
** Pin contains programmable pull-up device.
† 25mA open-drain if output pin.
VDD
POWER
‡ LED direct sink pin.
VSS
# Pins available on MC68H(R)C908JL3E only.
¥ Shared pin: MC68HC908JL3E/JK3E/JK1E — OSC2
ADC REFERENCE
MC68HRC908JL3E/JK3E/JK1E — RCCLK/PTA6/KBI6
Figure 1-1. MCU Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
17
General Description
1.4 Pin Assignments
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IRQ1
1
RST
PTA0/KBI0
VSS
PTA5/KBI5
PTD4/TCH0
PTD5/TCH1
PTD2/ADC9
PTA4/KBI4
PTD3/ADC8
PTB0/ADC0
PTB1/ADC1
PTD1/ADC10
PTB2/ADC2
PTB3/ADC3
PTD0/ADC11
PTB4/ADC4
2
3
OSC1
4
OSC2/RCCLK/PTA6/KBI
PTA1/KBI1
VDD
5
6
7
PTA2/KBI2
PTA3/KBI3
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTD7
8
9
10
11
12
13
14
PTD6
MC68H(R)C908JL3E
Figure 1-2. 28-Pin PDIP/SOIC Pin Assignment
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
IRQ1
RST
VSS
OSC1
PTD4/TCH0
PTD5/TCH1
PTD2/ADC9
PTD3/ADC8
PTB0/ADC0
PTB1/ADC1
PTB2/ADC2
PTB3/ADC3
PTB4/ADC4
Pins not available on 20-pin packages
OSC2/RCCLK/PTA6/KBI
VDD
PTA0/KBI0
PTA1/KBI1
PTA2/KBI2
PTA3/KBI3
PTA4/KBI4
PTA5/KBI5
PTD0/ADC11
PTD1/ADC10
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTD7
PTD6
Internal pads are unconnected.
MC68H(R)C908JK3E/JK1E
Figure 1-3. 20-Pin PDIP/SOIC Pin Assignment
MC68HC908JL3E Family Data Sheet, Rev. 3
18
Freescale Semiconductor
Pin Assignments
1
36
NC
NC
NC
NC
2
3
NC
35
34
33
32
31
30
29
28
27
26
OSC1
4
PTD2/ADC9
PTA4/KBI4
PTD3/ADC8
NC
OSC2/RCCLK/PTA6/KBI6
5
PTA1/KBI1
NC
6
MC68H(R)C908JL3E
7
VDD
8
PTB0/ADC0
PTB1/ADC1
PTD1/ADC10
NC
PTA2/KBI2
PTA3KBI3
PTB7/ADC7
NC
9
10
11
25 NC
NC 12
NC: No connection
Figure 1-4. 48-Pin LQFP Pin Assignment
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
19
General Description
1.5 Pin Functions
Description of the pin functions are provided in Table 1-2.
Table 1-2. Pin Functions
PIN NAME
VDD
PIN DESCRIPTION
IN/OUT
In
VOLTAGE LEVEL
5V or 3V
Power supply.
VSS
Power supply ground
Out
0V
RESET input, active low.
With Internal pull-up and schmitt trigger input.
RST
Input
VDD
External IRQ pin.
With software programmable internal pull-up and schmitt
trigger input.
VDD to VDD+VHI
IRQ1
Input
This pin is also used for mode entry selection.
OSC1
X-tal or RC oscillator input.
In
Analog
Analog
MC68HC908JL3E/JK3E/JK1E:
X-tal oscillator output, this is the inverting OSC1 signal.
Out
OSC2
MC68HRC908JL3E/JK3E/JK1E:
Default is RC oscillator clock output, RCCLK.
Shared with PTA6/KBI6, with programmable pull-up.
In/Out
VDD
7-bit general purpose I/O port.
In/Out
In
VDD
VDD
Shared with 7 keyboard interrupts KBI[0:6].
Each pin has programmable internal pull-up device.
PTA[0:5] have LED direct sink capability
8-bit general purpose I/O port.
PTA[0:6]
PTB[0:7]
In
VDD
In
VSS
In/Out
In
VDD
Shared with 8 ADC inputs, ADC[0:7].
Analog
VDD
8-bit general purpose I/O port.
In/Out
Input
In/Out
In
PTD[3:0] shared with 4 ADC inputs, ADC[8:11].
PTD[4:5] shared with TIM channels, TCH0 and TCH1.
PTD[2:3], PTD[6:7] have LED direct sink capability
Analog
VDD
PTD[0:7]
VSS
PTD[6:7] can be configured as 25mA open-drain output with
pull-up.
In/Out
VDD
NOTE
On the MC68H(R)C908JK3E/JK1E, the following pins are not available:
PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1.
MC68HC908JL3E Family Data Sheet, Rev. 3
20
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
•
4,096 bytes of user FLASH — MC68H(R)C908JL3E/JK3E
1,536 bytes of user FLASH — MC68H(R)C908JK1E
128 bytes of RAM
48 bytes of user-defined vectors
960 bytes of Monitor ROM
•
•
•
2.2 I/O Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have the following addresses:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
$FE00; Break Status Register, BSR
$FE01; Reset Status Register, RSR
$FE02; Reserved
$FE03; Break Flag Control Register, BFCR
$FE04; Interrupt Status Register 1, INT1
$FE05; Interrupt Status Register 2, INT2
$FE06; Interrupt Status Register 3, INT3
$FE07; Reserved
$FE08; FLASH Control Register, FLCR
$FE09; FLASH Block Protect Register, FLBPR
$FE0A; Reserved
$FE0B; Reserved
$FE0C; Break Address Register High, BRKH
$FE0D; Break Address Register Low, BRKL
$FE0E; Break Status and Control Register, BRKSCR
$FE0F; Reserved
$FFFF; COP Control Register, COPCTL
2.3 Monitor ROM
The 960 bytes at addresses $FC00–$FDFF and $FE10–$FFCF are reserved ROM addresses that
contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
21
Memory
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$007F
RESERVED
64 BYTES
$0080
↓
$00FF
RAM
128 BYTES
$0100
↓
$EBFF
UNIMPLEMENTED
60,160 BYTES
$0100
↓
$F5FF
UNIMPLEMENTED
62,720 BYTES
$EC00
↓
$FBFF
FLASH MEMORY
MC68H(R)C908JL3E/JK3E
4,096 BYTES
FLASH MEMORY
MC68H(R)C908JK1E
1,536 BYTES
$F600
↓
$FBFF
$FC00
↓
$FDFF
MONITOR ROM
512 BYTES
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
BREAK STATUS REGISTER (BSR)
RESET STATUS REGISTER (RSR)
RESERVED (UBAR)
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
INTERRUPT STATUS REGISTER 3 (INT3)
RESERVED
FLASH CONTROL REGISTER (FLCR)
FLASH BLOCK PROTECT REGISTER (FLBPR)
RESERVED
RESERVED
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOW REGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
RESERVED
$FE10
↓
$FFCF
MONITOR ROM
448 BYTES
$FFD0
↓
$FFFF
USER VECTORS
48 BYTES
Figure 2-1. Memory Map
MC68HC908JL3E Family Data Sheet, Rev. 3
22
Freescale Semiconductor
Monitor ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0000 Port A Data Register (PTA) Write:
Reset:
Unaffected by reset
PTB4 PTB3
Unaffected by reset
Read:
PTB7
PTB6
PTD6
PTB5
PTD5
PTB2
PTD2
PTB1
PTB0
$0001 Port B Data Register (PTB) Write:
Reset:
Read:
$0002
Unimplemented Write:
Read:
PTD7
0
PTD4
PTD3
PTD1
PTD0
$0003 Port D Data Register (PTD) Write:
Reset:
Unaffected by reset
Read:
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Data Direction Register A
(DDRA)
$0004
$0005
$0006
$0007
Write:
Reset:
Read:
Write:
Reset:
Read:
0
DDRB7
0
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
Data Direction Register B
(DDRB)
Unimplemented Write:
Read:
DDRD7
0
DDRD6
0
DDRD5
0
DDRD4
0
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
Write:
Reset:
Read:
$0008
↓
Unimplemented Write:
$0009
Read:
0
0
0
0
0
0
0
0
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Port D Control Register
(PDCR)
$000A
Write:
Reset:
Read:
0
0
0
0
$000B
↓
$000C
Unimplemented Write:
Read:
Port A Input Pull-up
Enable Register Write:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000D
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
$000E
↓
$0019
Read:
Write:
Unimplemented
Read:
Keyboard Status and
Control Register Write:
0
0
0
0
KEYF
0
ACKK
0
IMASKK MODEK
$001A
$001B
(KBSCR)
Reset:
0
0
KBIE6
0
0
KBIE5
0
0
KBIE4
0
0
0
KBIE1
0
0
KBIE0
0
Read:
Keyboard Interrupt
Enable Register Write:
0
KBIE3
KBIE2
(KBIER)
Reset:
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 4)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
23
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Unimplemented Write:
$001C
Read:
0
0
0
0
IRQF1
0
ACK1
0
IRQ Status and Control
IMASK1
MODE1
$001D
$001E
$001F
Register Write:
(INTSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
R
0
0
R
0
0
LVIT1
0*
0
LVIT0
0*
0
0
IRQPUD
R
R
R
Configuration Register 2
(CONFIG2)†
0
COPRS
0
0
SSREC
0
0
STOP
0
0
COPD
0
R
0
R
0
LVID
0
R
Configuration Register 1
(CONFIG1)†
0
† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.
Read:
TOF
0
0
TIM Status and Control
TOIE
TSTOP
PS2
PS1
PS0
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
Register Write:
(TSC)
0
0
TRST
0
Reset:
0
1
0
0
0
0
Read: Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TIM Counter Register
High Write:
(TCNTH)
Reset:
Read:
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TIM Counter Register
Low Write:
(TCNTL)
Reset:
Read:
0
Bit15
1
0
Bit14
1
0
Bit13
1
0
Bit12
1
0
Bit11
1
0
Bit10
1
0
Bit9
1
0
TIM Counter Modulo
Bit8
Register High Write:
(TMODH)
Reset:
Read:
1
TIM Counter Modulo
Bit7
1
Bit6
1
Bit5
1
Bit4
1
Bit3
1
Bit2
1
Bit1
1
Bit0
Register Low Write:
(TMODL)
Reset:
1
CH0MAX
0
Read: CH0F
TIM Channel 0 Status and
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
Control Register Write:
(TSC0)
0
0
Reset:
Read:
TIM Channel 0
Register High Write:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
(TCH0H)
Reset:
Indeterminate after reset
Bit4 Bit3
Indeterminate after reset
Read:
TIM Channel 0
Register Low Write:
Bit7
Bit6
Bit5
0
Bit2
Bit1
Bit0
(TCH0L)
Reset:
Read: CH1F
TIM Channel 1 Status and
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
CH1MAX
Control Register Write:
(TSC1)
0
0
0
0
Reset:
Read:
TIM Channel 1
Register High Write:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
(TCH1H)
Reset:
Indeterminate after reset
Bit4 Bit3
Read:
TIM Channel 1
Register Low Write:
Bit7
Bit6
Bit5
Bit2
Bit1
Bit0
(TCH1L)
Reset:
Indeterminate after reset
R
= Unimplemented
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 4)
MC68HC908JL3E Family Data Sheet, Rev. 3
24
Freescale Semiconductor
Monitor ROM
Addr.
$002B
↓
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Unimplemented
$003B
Read: COCO
ADC Status and Control
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
$003C
$003D
Register Write:
(ADSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADC Data Register
(ADR)
Indeterminate after reset
0
0
0
0
0
0
0
0
ADIV2
0
ADIV1
0
ADIV0
0
ADC Input Clock Register
(ADICLK)
$003E
$003F
0
0
Unimplemented Write:
Read:
SBSW
See note
0
R
R
R
R
R
R
R
0
$FE00 Break Status Register (BSR) Write:
Reset:
Note: Writing a logic 0 clears SBSW.
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
$FE01 Reset Status Register (RSR) Write:
POR:
Read:
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
Reserved Write:
Read:
Break Flag Control
BCFE
R
R
R
R
R
R
R
Register Write:
(BFCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
0
IF5
R
0
IF4
R
0
IF3
R
0
0
R
0
IF1
R
0
0
R
0
0
R
Interrupt Status Register 1
(INT1)
R
0
0
IF14
R
0
0
0
0
0
0
0
Interrupt Status Register 2
(INT2)
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
0
0
0
0
0
0
0
IF15
R
Interrupt Status Register 3
(INT3)
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
R
0
R
R
R
R
R
R
R
Reserved Write:
Read:
0
0
0
HVEN
0
MASS
0
ERASE
PGM
0
FLASH Control Register
(FLCR)
Write:
Reset:
Read:
Write:
Reset:
0
BPR7
0
0
BPR6
0
0
BPR5
0
0
BPR4
0
0
BPR1
0
BPR3
BPR2
BPR0
0
FLASH Block Protect
Register (FLBPR)
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 4)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
25
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Reserved Write:
$FE0A
↓
$FE0B
R
R
R
R
R
R
R
R
Read:
Break Address High
Bit15
0
Bit14
0
Bit13
0
Bit12
0
Bit11
0
Bit10
0
Bit9
0
Bit8
0
$FE0C
$FE0D
$FE0E
Register Write:
(BRKH)
Reset:
Read:
Break Address low
Bit7
0
Bit6
0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Register Write:
(BRKL)
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
0
0
Break Status and Control
BRKE
0
BRKA
0
Register Write:
(BRKSCR)
Reset:
0
0
0
0
0
0
Read:
Write:
Reset:
Low byte of reset vector
COP Control Register
(COPCTL)
$FFFF
Writing clears COP counter (any value)
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 4)
Table 2-1. Vector Addresses
Vector Priority
INT Flag
Address
Vector
Lowest
$FFD0
↓
—
Not Used
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
ADC Conversion Complete Vector (High)
ADC Conversion Complete Vector (Low)
Keyboard Vector (High)
IF15
IF14
Keyboard Vector (Low)
IF13
↓
—
Not Used
IF6
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
—
TIM Overflow Vector (High)
TIM Overflow Vector (Low)
TIM Channel 1 Vector (High)
TIM Channel 1 Vector (Low)
TIM Channel 0 Vector (High)
TIM Channel 0 Vector (Low)
Not Used
IF5
IF4
IF3
IF2
IF1
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
IRQ1 Vector (High)
IRQ1 Vector (Low)
SWI Vector (High)
—
—
SWI Vector (Low)
Reset Vector (High)
$FFFF
Reset Vector (Low)
Highest
MC68HC908JL3E Family Data Sheet, Rev. 3
26
Freescale Semiconductor
Random-Access Memory (RAM)
2.4 Random-Access Memory (RAM)
Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero
RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
2.5 FLASH Memory
This sub-section describes the operation of the embedded FLASH memory. The FLASH memory can be
read, programmed, and erased from a single external supply. The program and erase operations are
enabled through the use of an internal charge pump.
FLASH Memory Size
Device
Memory Address Range
(Bytes)
4,096
4,096
1,536
MC68H(R)C908JL3E
MC68H(R)C908JK3E
MC68H(R)C908JK1E
$EC00—$FBFF
$EC00—$FBFF
$F600—$FBFF
Addr.
Register Name
Bit 7
6
5
4
3
HVEN
0
2
MASS
0
1
ERASE
0
Bit 0
PGM
0
Read:
Write:
Reset:
Read:
0
0
0
0
FLASH Control Register
(FLCR)
$FE08
0
BPR7
0
0
BPR6
0
0
BPR5
0
0
BPR4
0
FLASH Block Protect
BPR3
0
BPR2
0
BPR1
0
BPR0
0
$FE09
Register Write:
(FLBPR)
Reset:
= Unimplemented
Figure 2-3. FLASH I/O Register Summary
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
27
Memory
2.6 Functional Description
The FLASH memory consists of an array of 4,096 or 1,536 bytes with an additional 48 bytes for user
vectors. The minimum size of FLASH memory that can be erased is 64 bytes (a page); and the maximum
size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and
erase operations are facilitated through control bits in the Flash Control Register (FLCR). Details for these
operations appear later in this section. The address ranges for the user memory and vectors are:
•
$EC00–$FBFF; user memory; 4,096 bytes; MC68H(R)C908JL3E/JK3E
$F600–$FBFF; user memory; 1,536 bytes;
MC68H(R)C908JK1E
•
$FFD0–$FFFF; user interrupt vectors; 48 bytes
NOTE
An erased bit reads as logic 1 and a programmed bit reads as logic 0.
A security feature prevents viewing of the FLASH contents.(1)
2.7 FLASH Control Register
The FLASH Control Register controls FLASH program and erase operations.
Address:
$FE08
Bit 7
0
6
0
5
0
4
0
3
HVEN
0
2
MASS
0
1
ERASE
0
Bit 0
PGM
0
Read:
Write:
Reset:
0
0
0
0
Figure 2-4. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or
erase operation. It can only be set if either PGM=1 or ERASE=1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or page erase operation when the
ERASE bit is set.
1 = Mass erase operation selected
0 = Page erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be
set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908JL3E Family Data Sheet, Rev. 3
28
Freescale Semiconductor
FLASH Page Erase Operation
PGM — Program Control Bit
This read/write bit configures the memory for program operation. This bit and the ERASE bit should
not be set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
2.8 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte user interrupt vectors area also
forms a page. Any page within the 4K bytes user memory area ($EC00–$FBFF) can be erased alone.
The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security
reasons. Mass erase is required to erase this page.
1. Set the ERASE bit and clear the MASS bit in the FLASH Control Register.
2. Write any data to any FLASH address within the page address range desired.
3. Wait for a time, tnvs (10µs).
4. Set the HVEN bit.
5. Wait for a time tErase (1ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh (5µs).
8. Clear the HVEN bit.
9. After time, trcv (1µs), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
2.9 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH Control Register.
2. Write any data to any FLASH location within the FLASH memory address range.
3. Wait for a time, tnvs (10µs).
4. Set the HVEN bit.
5. Wait for a time tMErase (4ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh1 (100µs).
8. Clear the HVEN bit.
9. After time, trcv (1µs), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
29
Memory
2.10 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes
starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this
step-by-step procedure to program a row of FLASH memory:
(Figure 2-5 shows a flowchart of the programming algorithm.)
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Write any data to any FLASH location within the address range of the row to be programmed.
3. Wait for a time, tnvs (10µs).
4. Set the HVEN bit.
5. Wait for a time, tpgs (5µs).
6. Write data to the byte being programmed.
7. Wait for time, tPROG (30µs).
8. Repeat step 6 and 7 until all the bytes within the row are programmed.
9. Clear the PGM bit.
10. Wait for time, tnvh (5µs).
11. Clear the HVEN bit.
12. After time, trcv (1µs), the memory can be accessed in read mode again.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
The time between each FLASH address change (step 6 to step 6), or the
time between the last FLASH addressed programmed to clearing the PGM
bit (step 6 to step 10), must not exceed the maximum programming time,
tPROG max.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
MC68HC908JL3E Family Data Sheet, Rev. 3
30
Freescale Semiconductor
FLASH Program Operation
1
2
Set PGM bit
Algorithm for programming
a row (32 bytes) of FLASH memory
Write any data to any FLASH address
within the row address range desired
3
4
5
Wait for a time, tnvs
Set HVEN bit
Wait for a time, tpgs
6
7
Write data to the FLASH address
to be programmed
Wait for a time, tPROG
Completed
Y
programming
this row?
N
9
Clear PGM bit
Wait for a time, tnvh
Clear HVEN bit
NOTE:
The time between each FLASH address change (step 6 to step 6), or
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
10
11
12
must not exceed the maximum programming
time, tPROG max.
This row program algorithm assumes the row/s
to be programmed are initially erased.
Wait for a time, trcv
End of Programming
Figure 2-5. FLASH Programming Flowchart
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
31
Memory
2.11 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect blocks of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH Block Protect Register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
operations.
2.12 FLASH Block Protect Register
The FLASH Block Protect Register is implemented as an 8-bit I/O register. The value in this register
determines the starting address of the protected range within the FLASH memory.
Address:
$FE09
Bit 7
6
BPR6
0
5
BPR5
0
4
BPR4
0
3
BPR3
0
2
BPR2
0
1
BPR1
0
Bit 0
BPR0
0
Read:
Write:
Reset:
BPR7
0
Figure 2-6. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Block Protect Register Bit 7 to Bit 0
BPR[7:1] represent bits [12:6] of a 16-bit memory address. Bits [15:13] are logic 1’s and bits [5:0] are
logic 0’s.
16-bit memory address
Start address of FLASH block protect
1 1 1
0 0 0 0 0 0
BPR[7:1]
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page
boundaries — 64 bytes) within the FLASH memory.
Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range
$00–$60
The entire FLASH memory is protected.
$62 or $63
(0110 001x)
$EC40 (1110 1100 0100 0000)
$EC80 (1110 1100 1000 0000)
$ED00 (1110 1101 0000 0000)
$64 or $65
(0110 010x)
$68 or $69
(0110 100x)
MC68HC908JL3E Family Data Sheet, Rev. 3
32
Freescale Semiconductor
FLASH Block Protect Register
BPR[7:0]
and so on...
Start of Address of Protect Range
$DE or $DF
(1101 111x)
$FBC0 (1111 1011 1100 0000)
$FFC0 (1111 1111 1100 0000)
$FE
(1111 1110)
$FF
The entire FLASH memory is not protected.
Note:
The end address of the protected range is always $FFFF.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
33
Memory
MC68HC908JL3E Family Data Sheet, Rev. 3
34
Freescale Semiconductor
Chapter 3
Configuration Registers (CONFIG)
3.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers
enables or disables the following options:
•
Stop mode recovery time (32 × 2OSCOUT cycles or
4096 × 2OSCOUT cycles)
•
•
•
STOP instruction
Computer operating properly module (COP)
COP reset period (COPRS), (213–24) × 2OSCOUT or
(218–24) × 2OSCOUT
•
•
Enable LVI circuit
Select LVI trip voltage
3.2 Functional Description
The configuration register is used in the initialization of various options. The configuration register can be
written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU it is recommended that this register be written immediately
after reset. The configuration register is located at $001E and $001F, and may be read at anytime.
NOTE
The CONFIG registers are one-time writable by the user after each reset.
Upon a reset, the CONFIG registers default to predetermined settings as
shown in Figure 3-1 and Figure 3-2.
3.3 Configuration Register 1 (CONFIG1)
Address:
$001F
Bit 7
6
5
R
0
4
LVID
0
3
R
0
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
R
0
0
R
= Reserved
Figure 3-1. Configuration Register 1 (CONFIG1)
COPRS — COP reset period selection bit
1 = COP reset cycle is (213 – 24) × 2OSCOUT
0 = COP reset cycle is (218 – 24) × 2OSCOUT
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
35
Configuration Registers (CONFIG)
LVID — Low Voltage Inhibit Disable Bit
1 = Low Voltage Inhibit disabled
0 = Low Voltage Inhibit enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 × 2OSCOUT cycles instead of a 4096 × 2OSCOUT cycle delay.
1 = Stop mode recovery after 32 × 2OSCOUT cycles
0 = Stop mode recovery after 4096 × 2OSCOUT cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
3.4 Configuration Register 2 (CONFIG2)
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
IRQPUD
0
R
R
LVIT1
LVIT0
R
R
Not
affected
Not
affected
Reset:
POR:
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
Figure 3-2. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ1 Pin Pull-up control bit
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ1 pin and VDD
LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits
Detail description of the LVI control signals is given in Chapter 14 Low Voltage Inhibit (LVI)
MC68HC908JL3E Family Data Sheet, Rev. 3
36
Freescale Semiconductor
Chapter 4
Central Processor Unit (CPU)
4.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes, and architecture.
4.2 Features
•
•
•
•
•
•
•
•
•
•
Object code fully upward-compatible with M68HC05 Family
16-bit stack pointer with stack manipulation instructions
16-bit index register with x-register manipulation instructions
8-MHz CPU internal bus frequency
64-Kbyte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
•
Low-power stop and wait modes
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
37
Central Processor Unit (CPU)
4.3 CPU Registers
Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map.
7
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
0
V
1
1
H
I
N
Z
C
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 4-1. CPU Registers
4.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 4-2. Accumulator (A)
4.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
MC68HC908JL3E Family Data Sheet, Rev. 3
38
Freescale Semiconductor
CPU Registers
Bit
15
14 13 12 11 10
9
0
8
0
7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 4-3. Index Register (H:X)
4.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 4-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address
(page 0) space. For correct operation, the stack pointer must point only to
RAM locations.
4.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
39
Central Processor Unit (CPU)
Bit
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 4-5. Program Counter (PC)
4.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe
the functions of the condition code register.
Bit 7
V
6
1
1
5
1
1
4
H
X
3
I
2
N
X
1
Z
X
Bit 0
C
Read:
Write:
Reset:
X
1
X
X = Indeterminate
Figure 4-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
MC68HC908JL3E Family Data Sheet, Rev. 3
40
Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
4.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a
description of the instructions and addressing modes and more detail about the architecture of the CPU.
4.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.5.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
•
4.5.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
41
Central Processor Unit (CPU)
4.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
4.7 Instruction Set Summary
Table 4-1 provides a summary of the M68HC08 instruction set.
4.8 Opcode Map
The opcode map is provided in Table 4-2.
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Add with Carry
A ← (A) + (M) + (C)
R R – R R R
SP1
SP2
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Add without Carry
A ← (A) + (M)
R R – R R R
SP1
SP2
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7
AF
ii
ii
2
2
MC68HC908JL3E Family Data Sheet, Rev. 3
42
Freescale Semiconductor
Opcode Map
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Logical AND
A ← (A) & (M)
0
–
–
–
–
R
R
R
R
–
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
R
R
R
C
0
b7
b0
b0
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
4
1
1
4
3
5
C
Arithmetic Shift Right
R
–
–
–
–
R
R
ff
b7
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
– REL
DIR (b0)
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25
27
rr
rr
3
3
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
BGT opr
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
–
–
–
–
–
–
–
–
–
– REL
– REL
90
92
rr
rr
3
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 +rel ? (Z) | (N ⊕ V)=0 –
3
3
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28
29
22
rr
rr
rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24
rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F
2E
rr
rr
3
3
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
43
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Bit Test
(A) & (M)
0
–
–
R
R
–
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V)=1 –
–
–
–
–
– REL
93
rr
3
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
25
23
91
2C
2B
2D
26
2A
20
rr
rr
rr
rr
rr
rr
rr
rr
rr
3
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 1
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R
BRN rel
Branch Never
PC ← (PC) + 2
– REL
21
rr
3
DIR (b0)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
R
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSET n,opr
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
MC68HC908JL3E Family Data Sheet, Rev. 3
44
Freescale Semiconductor
Opcode Map
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
–
–
–
–
–
–
–
–
–
– REL
AD
rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
31
41
51
61
71
dd rr
ii rr
ii rr
ff rr
rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IX1+
Compare and Branch if Equal
–
–
IX+
SP1
CBEQ opr,SP,rel
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
– INH
IX1
IX
3F
4F
5F
8C
6F
7F
dd
ff
3
1
1
1
3
2
4
Clear
0
–
–
0
1
CLR opr,SP
SP1
9E6F ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Compare A with M
(A) – (M)
R
–
–
R
R
R
9EE1 ff
9ED1 ee ff
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
ff
4
1
1
4
3
5
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
–
R
R
R
R
1
SP1
9E63 ff
CPHX #opr
CPHX opr
IMM
R
65
75
ii ii+1
dd
3
4
(H:X) – (M:M + 1)
R
DIR
CPX #opr
CPX opr
CPX opr
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
CPX ,X
Compare X with M
Decimal Adjust A
(X) – (M)
R
–
–
–
R
R
R
R
R
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
9EE3 ff
9ED3 ee ff
DAA
(A)10
U –
R INH
72
2
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
45
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
A ← (A)–1 or M ← (M)–1 or X ← (X)–1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
– INH
IX1
IX
SP1
3B
4B
5B
6B
7B
dd rr
rr
rr
ff rr
rr
Decrement and Branch if Not Zero
–
–
–
–
–
9E6B ff rr
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
4
1
1
4
3
5
Decrement
Divide
R
–
–
–
–
R
R
R
–
SP1
9E6A ff
A ← (H:A)/(X)
H ← Remainder
DIV
–
–
R INH
52
7
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Exclusive OR M with A
A ← (A ⊕ M)
0
–
–
–
–
R
R
R
R
–
9EE8 ff
9ED8 ee ff
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
4
1
1
4
3
5
Increment
R
–
SP1
9E6C ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
– IX2
IX1
BC
CC
DC
EC
FC
dd
2
3
4
3
2
hh ll
ee ff
ff
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
IX
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD
CD
DD
ED
FD
dd
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
hh ll
ee ff
ff
Jump to Subroutine
IX
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Load A from M
A ← (M)
0
0
–
–
–
–
R
R
R
R
–
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
–
45
55
ii jj
dd
3
4
Load H:X from M
H:X ← (M:M + 1)
DIR
MC68HC908JL3E Family Data Sheet, Rev. 3
46
Freescale Semiconductor
Opcode Map
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Load X from M
X ← (M)
0
–
–
R
R
–
SP1
SP2
9EEE ff
9EDE ee ff
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
4
1
1
4
3
5
Logical Shift Left
(Same as ASL)
C
0
R
R
–
–
–
–
R
R
R
R
b7
b0
SP1
9E68 ff
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
4
1
1
4
3
5
0
C
Logical Shift Right
0
R
ff
b7
b0
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
4
4
4
(M)Destination ← (M)Source
DIX+
IMD
IX+D
Move
0
–
–
0
–
–
R
R
–
H:X ← (H:X) + 1 (IX+D, DIX+)
MUL
Unsigned multiply
X:A ← (X) × (A)
–
–
0 INH
42
5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
Negate (Two’s Complement)
R
–
–
R
R
R
SP1
9E60 ff
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
1
3
A ← (A[3:0]:A[7:4])
62
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Inclusive OR A and M
A ← (A) | (M)
0
–
–
R
R
–
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
– INH
87
8B
89
86
2
2
2
2
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
47
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
PULH
Pull H from Stack
Pull X from Stack
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
– INH
– INH
8A
88
2
2
PULX
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
4
1
1
4
3
5
C
Rotate Left through Carry
Rotate Right through Carry
R
R
–
–
–
–
R
R
R
R
R
b7
b0
SP1
9E69 ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
4
1
1
4
3
5
C
R
ff
b7
b0
SP1
9E66 ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
R
R
R
R
R
R INH
80
81
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
–
–
–
– INH
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
A2
B2
C2
D2
E2
F2
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
IX2
IX1
A ← (A) – (M) – (C)
R
R
R
R
IX
SP1
SP2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
STA opr
DIR
EXT
IX2
– IX1
IX
B7
C7
D7
E7
F7
dd
3
4
4
3
2
4
5
hh ll
ee ff
ff
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
R
R
SP1
SP2
9EE7 ff
9ED7 ee ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
R
R
– DIR
– INH
35
8E
dd
4
1
STOP
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
–
MC68HC908JL3E Family Data Sheet, Rev. 3
48
Freescale Semiconductor
Opcode Map
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
STX opr
STX opr
DIR
EXT
IX2
– IX1
IX
BF
CF
DF
EF
FF
dd
3
4
4
3
2
4
5
hh ll
ee ff
ff
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
R
R
SP1
SP2
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Subtract
A ← (A) – (M)
R
– R R R
9EE0 ff
9ED0 ee ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
R
–
–
R
–
–
R
–
–
R
–
–
R
–
–
R INH
– INH
– INH
84
97
85
2
1
1
Transfer CCR to A
A ← (CCR)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
3
1
1
3
2
4
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
R
R
–
SP1
9E6D ff
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
49
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
A
C
Accumulator
Carry/borrow bit
n
opr
PC
Any bit
Operand (one or two bytes)
Program counter
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DD
DIR
DIX+ Direct to indexed with post increment addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
Direct to direct addressing mode
Direct addressing mode
Relative program counter offset byte
Relative program counter offset byte
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
ff
H
H
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
SP
U
V
Stack pointer
Undefined
Overflow bit
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
X
Z
Index register low byte
Zero bit
ii
Immediate operand byte
&
Logical AND
IMD
Immediate source to direct destination addressing mode
|
Logical OR
IMM Immediate addressing mode
⊕
Logical EXCLUSIVE OR
Contents of
INH
IX
IX+
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
( )
–( ) Negation (two’s complement)
#
«
←
?
Immediate value
Sign extend
Loaded with
If
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
IX2
M
N
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
:
R
—
Concatenated with
Set or cleared
Not affected
MC68HC908JL3E Family Data Sheet, Rev. 3
50
Freescale Semiconductor
Opcode Map
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
51
Central Processor Unit (CPU)
MC68HC908JL3E Family Data Sheet, Rev. 3
52
Freescale Semiconductor
Chapter 5
System Integration Module (SIM)
5.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM
is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state
controller that coordinates CPU and exception timing. The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
–
–
Stop/wait/reset/break entry and recovery
Internal clock control
•
•
Master reset control, including power-on reset (POR) and COP timeout
Interrupt control:
–
–
–
Acknowledge timing
Arbitration control timing
Vector address generation
•
•
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
Table 5-1 shows the internal signal names used in this section.
Table 5-1. Signal Name Conventions
Signal Name
Description
2OSCOUT
Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit.
The 2OSCOUT frequency divided by two. This signal is again divided by two in the SIM to
generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4)
OSCOUT
IAB
IDB
Internal address bus
Internal data bus
PORRST
IRST
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
53
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
2OSCOUT (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
÷2
VDD
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULL-UP
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
COP TIMEOUT (FROM COP MODULE)
USB RESET (FROM USB MODULE)
SIM RESET STATUS REGISTER
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 5-1. SIM Block Diagram
Addr.
Register Name
Bit 7
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
Bit 0
Read:
SBSW
NOTE
0
R
0
R
0
$FE00 Break Status Register (BSR) Write:
Reset:
Note: Writing a logic 0 clears SBSW.
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
$FE01 Reset Status Register (RSR) Write:
POR:
Read:
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
$FE02
$FE03
Reserved Write:
Reset:
Read:
Break Flag Control
Register Write:
(BFCR)
BCFE
0
R
R
R
R
R
R
R
Reset:
Figure 5-2. SIM I/O Register Summary
MC68HC908JL3E Family Data Sheet, Rev. 3
54
Freescale Semiconductor
SIM Bus Clock Control and Generation
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
R
IF5
R
0
IF4
R
0
IF3
R
0
0
R
0
IF1
R
0
0
R
0
0
R
Interrupt Status Register 1
(INT1)
$FE04
$FE05
$FE06
0
0
IF14
R
0
0
0
0
0
0
0
Interrupt Status Register 2
(INT2)
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
0
0
0
0
0
0
0
IF15
R
Interrupt Status Register 3
(INT3)
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
= Unimplemented
R
= Reserved
Figure 5-2. SIM I/O Register Summary
5.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 5-3.
From
OSCILLATOR
2OSCOUT
OSCOUT
SIM COUNTER
From
OSCILLATOR
BUS CLOCK
GENERATORS
÷ 2
SIM
Figure 5-3. SIM Clock Signals
5.2.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (2OSCOUT) divided by four.
5.2.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 2OSCOUT cycle POR time-out has completed. The RST
pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the
time-out.
5.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This
time-out is selectable as 4096 or 32 2OSCOUT cycles. (See 5.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
55
System Integration Module (SIM)
5.3 Reset and System Initialization
The MCU has these reset sources:
•
•
•
•
•
•
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in Monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 5.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the reset status register (RSR). (See 5.7 SIM Registers.)
5.3.1 External Pin Reset
The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum
of 67 2OSCOUT cycles, assuming that the POR was not the source of the reset. See Table 5-2 for details.
Figure 5-4 shows the relative timing.
Table 5-2. PIN Bit Set Timing
Reset Type
POR
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
2OSCOUT
RST
IAB
VECT H VECT L
PC
Figure 5-4. External Reset Timing
5.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(Figure 5-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR.
(See Figure 5-6 . Sources of Internal Reset.) Note that for POR resets, the SIM cycles through 4096
2OSCOUT cycles during which the SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST shown in Figure 5-5.
MC68HC908JL3E Family Data Sheet, Rev. 3
56
Freescale Semiconductor
Reset and System Initialization
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
2OSCOUT
IAB
VECTOR HIGH
Figure 5-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
LVI
Figure 5-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
5.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur.
At power-on, the following events occur:
•
•
•
•
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive 2OSCOUT.
Internal clocks to the CPU and modules are held inactive for 4096 2OSCOUT cycles to allow
stabilization of the oscillator.
•
•
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
57
System Integration Module (SIM)
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
2OSCOUT
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 5-7. POR Recovery
5.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the
RST pin for all internal reset sources.
To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at
least every (212 – 24) 2OSCOUT cycles, drives the COP counter. The COP should be serviced as soon
as possible out of reset to guarantee the maximum amount of time before the first time-out.
The COP module is disabled if the RST pin or the IRQ1 pin is held at VDD + VHI while the MCU is in monitor
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1 pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, VDD + VHI on the RST pin disables the COP module.
5.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the reset status register (RSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction
as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
5.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down
the RST pin for all internal reset sources.
MC68HC908JL3E Family Data Sheet, Rev. 3
58
Freescale Semiconductor
SIM Counter
5.3.2.5 LVI Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI
trip voltage VTRIP. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RSTB) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles
later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The
SIM actively pulls down the (RSTB) pin for all internal reset sources.
5.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of 2OSCOUT.
5.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
5.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay
of 4096 2OSCOUT cycles down to 32 2OSCOUT cycles. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).
5.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 5.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 5.3.2 Active Resets from Internal Sources for counter control
and internal reset recovery sequences.)
5.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
•
Interrupts
–
–
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
•
•
Reset
Break interrupts
5.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 5-8 flow charts the handling of system interrupts.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
59
System Integration Module (SIM)
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
YES
YES
IRQ
INTERRUPT?
NO
TIMER
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
(As many interrupts as exist on chip)
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
YES
NO
RTI
INSTRUCTION?
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
NO
Figure 5-8. Interrupt Processing
MC68HC908JL3E Family Data Sheet, Rev. 3
60
Freescale Semiconductor
Exception Control
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 5-9 shows
interrupt entry timing.
Figure 5-10 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
IDB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8]
X
A
CCR
V DATA H V DATA L OPCODE
R/W
Figure 5-9. Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
IDB
CCR
A
X
PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND
R/W
Figure 5-10. Interrupt Recovery
5.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 5-11 demonstrates what happens when two interrupts are pending. If an interrupt is
pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
61
System Integration Module (SIM)
CLI
LDA #$FF
BACKGROUND ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 5-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
5.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
5.5.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 5-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
MC68HC908JL3E Family Data Sheet, Rev. 3
62
Freescale Semiconductor
Exception Control
Vector Address
Table 5-3. Interrupt Sources
INT
Register
Flag
Mask1(1)
Priority
Source
Flag
Highest
Reset
—
—
—
—
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFE0–$FFE1
$FFDE–$FFDF
SWI Instruction
IRQ1 Pin
—
—
IRQF1
CH0F
CH1F
TOF
IMASK1
CH0IE
CH1IE
TOIE
IF1
IF3
IF4
IF5
IF14
IF15
Timer Channel 0 Interrupt
Timer Channel 1 Interrupt
Timer Overflow Interrupt
Keyboard Interrupt
KEYF
COCO
IMASKK
AIEN
Lowest
ADC Conversion Complete Interrupt
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
5.5.2.1 Interrupt Status Register 1
Address:
$FE04
Bit 7
0
6
5
IF4
R
4
IF3
R
3
0
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
IF5
R
R
R
0
R
0
R
0
0
0
0
0
0
R
= Reserved
Figure 5-12. Interrupt Status Register 1 (INT1)
IF1, IF3 to IF5 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3 and 7 — Always read 0
5.5.2.2 Interrupt Status Register 2
Address:
$FE05
Bit 7
IF14
R
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
R
= Reserved
Figure 5-13. Interrupt Status Register 2 (INT2)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
63
System Integration Module (SIM)
IF14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources shown in Table 5-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 to 6 — Always read 0
5.5.2.3 Interrupt Status Register 3
Address:
$FE06
Bit 7
0
6
5
0
4
0
3
0
2
0
1
0
Bit 0
IF15
R
Read:
Write:
Reset:
0
R
R
R
0
R
0
R
0
R
0
R
0
0
0
0
R
= Reserved
Figure 5-14. Interrupt Status Register 3 (INT3)
IF15 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 to 7 — Always read 0
5.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
5.5.4 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See Chapter 15 Break Module (BREAK).) The SIM puts the CPU into the break
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.
5.5.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
MC68HC908JL3E Family Data Sheet, Rev. 3
64
Freescale Semiconductor
Low-Power Modes
5.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
5.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 5-15 shows
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module (COP) is enabled and remains active
in wait mode.
IAB
IDB
R/W
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 5-15. Wait Mode Entry Timing
Figure 5-16 and Figure 5-17 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB $A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 5-16. Wait Recovery from Interrupt or Break
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
65
System Integration Module (SIM)
32
Cycles
32
Cycles
IAB
IDB $A6
RST
$6E0B
$A6
RSTVCTH RSTVCTL
$A6
2OSCOUT
Figure 5-17. Wait Recovery from Internal Reset
5.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in stop mode, stopping the CPU and
peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32.
This is ideal for applications using canned oscillators that do not require long start-up times from stop
mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register
(BSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 5-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
IAB
IDB
R/W
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 5-18. Stop Mode Entry Timing
MC68HC908JL3E Family Data Sheet, Rev. 3
66
Freescale Semiconductor
SIM Registers
STOP RECOVERY PERIOD
2OSCOUT
INT/BREAK
IAB
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 5-19. Stop Mode Recovery from Interrupt or Break
5.7 SIM Registers
The SIM has three memory mapped registers. Table 5-4 shows the mapping of these registers.
Table 5-4. SIM Registers
Address
$FE00
$FE01
$FE03
Register
BSR
Access Mode
User
RSR
User
BFCR
User
5.7.1 Break Status Register (BSR)
The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
Note(1)
0
R
R
R
R
R
R
R
= Reserved
1. Writing a logic zero clears SBSW.
Figure 5-20. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit
clears it.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
67
System Integration Module (SIM)
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU
LOBYTE EQU
5
6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not zero,
; then just decrement low byte.
; Else deal with high byte, too.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
5.7.2 Reset Status Register (RSR)
This register contains six flags that show the source of the last reset. Clear the SIM reset status register
by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Address:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
0
Read:
Write:
POR:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 5-21. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
MC68HC908JL3E Family Data Sheet, Rev. 3
68
Freescale Semiconductor
SIM Registers
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ1 = VDD
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
5.7.3 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear status bits while the MCU is in a
break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 5-22. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
69
System Integration Module (SIM)
MC68HC908JL3E Family Data Sheet, Rev. 3
70
Freescale Semiconductor
Chapter 6
Oscillator (OSC)
6.1 Introduction
The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator
modules are available:
•
MC68HC908JL3E/JK3E/JK1E — built-in oscillator module (X-tal) that requires an external crystal
or ceramic-resonator. This option also allows an external clock that can be driven directly into
OSC1.
•
MC68HRC908JL3E/JK3E/JK1E — built-in oscillator module (RC) that requires an external RC
connection only.
6.2 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E)
The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide
accurate clock source.
In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown
in Figure 6-1. This figure shows only the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five components:
•
•
•
•
•
Crystal, X1
Fixed capacitor, C1
Tuning capacitor, C2 (can also be a fixed capacitor)
Feedback resistor, RB
Series resistor, RS (optional)
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not
be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
6.3 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E)
The RC oscillator circuit is designed for use with external R and C to provide a clock source with tolerance
less than 10%.
In its typical configuration, the RC oscillator requires two external components, one R and one C.
Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10%
tolerance. The oscillator configuration uses two components:
•
•
CEXT
REXT
The RC connection is shown in Figure 6-2.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
71
Oscillator (OSC)
From SIM
To SIM
2OSCOUT
To SIM
OSCOUT
XTALCLK
÷ 2
SIMOSCEN
MCU
OSC1
OSC2
RB
RS*
*RS can be zero (shorted) when used with higher-frequency crystals.
Refer to manufacturer’s data.
X1
See Chapter 16 for component value requirements.
C1
C2
Figure 6-1. X-tal Oscillator External Connections
From SIM
To SIM
2OSCOUT
To SIM
OSCOUT
SIMOSCEN
Ext-RC
RCCLK
EN
÷ 2
Oscillator
0
1
PTA6
I/O
PTA6
PTA6EN
MCU
OSC1
PTA6/RCCLK (OSC2)
VDD
See Chapter 16 for component value requirements.
REXT
CEXT
Figure 6-2. RC Oscillator External Connections
MC68HC908JL3E Family Data Sheet, Rev. 3
72
Freescale Semiconductor
I/O Signals
6.4 I/O Signals
The following paragraphs describe the oscillator I/O signals.
6.4.1 Crystal Amplifier Input Pin (OSC1)
OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit.
6.4.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK)
For the X-tal oscillator device, OSC2 pin is the output of the crystal oscillator inverting amplifier.
For the RC oscillator device, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the
output of the internal RC oscillator clock, RCCLK.
Device
Oscillator
OSC2 pin function
MC68HC908JL3E/JK3E/JK1E
X-tal
Inverting OSC1
Controlled by PTA6EN bit in PTAPUER ($0D)
PTA6EN = 0: RCCLK output
MC68HRC908JL3E/JK3E/JK1E
RC
PTA6EN = 1: PTA6 I/O
6.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the X-tal
oscillator circuit or the RC-oscillator.
6.4.4 X-tal Oscillator Clock (XTALCLK)
XTALCLK is the X-tal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 6-1 shows only the logical relation of XTALCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be
unstable at start-up.
6.4.5 RC Oscillator Clock (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the
external R and C. Figure 6-2 shows only the logical relation of RCCLK to OSC1 and may not represent
the actual circuitry.
6.4.6 Oscillator Out 2 (2OSCOUT)
2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module and
is used to determine the COP cycles.
6.4.7 Oscillator Out (OSCOUT)
The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation
of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the
SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
73
Oscillator (OSC)
6.5 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
6.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. OSCOUT and 2OSCOUT continues to drive to
the SIM module.
6.5.2 Stop Mode
The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT.
6.6 Oscillator During Break Mode
The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state.
MC68HC908JL3E Family Data Sheet, Rev. 3
74
Freescale Semiconductor
Chapter 7
Monitor ROM (MON)
7.1 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM
allows complete testing of the MCU through a single-wire interface with a host computer. This mode is
also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be
achieved without use of the higher test voltage, VDD + VHI, as long as vector addresses $FFFE and
$FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
7.2 Features
Features of the monitor ROM include the following:
•
•
•
•
•
•
•
•
Normal user-mode pin functionality
One pin dedicated to serial communication between monitor ROM and host computer
Standard mark/space non-return-to-zero (NRZ) communication with host computer
Execution of code in RAM or FLASH
FLASH memory security feature(1)
FLASH memory programming interface
960 bytes monitor ROM code size
Monitor mode entry without high voltage, VDD + VHI, if reset vector is blank ($FFFE and $FFFF
contain $FF)
•
Standard monitor mode entry if high voltage, VDD + VHI, is applied to IRQ1
7.3 Functional Description
The monitor ROM receives and executes commands from a host computer. Figure 7-1 shows a example
circuit used to enter monitor mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
host-computer code in RAM while most MCU pins retain normal operating mode functions. All
communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and
multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR
configuration and requires a pull-up resistor.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
75
Monitor ROM (MON)
RST
RC CIRCUIT
VDD
0.1 µF
FOR MC68HRC908JL3E/JK3E/JK1E
SW1 MUST BE AT POSITION B
See Figure 16-1 for component
values vs. frequency.
H(R)C908JL3E
H(R)C908JK3E
H(R)C908JK1E
OSC1
VDD
OSC2
VDD
0.1 µF
VSS
EXT OSC
VDD
FOR MC68HC908JL3E/JK3E/JK1E
SW1 AT POSITION A OR B
(50% DUTY)
OSC1
OSC2
FOR MC68HRC908JL3E/JK3E/JK1E
SW1 MUST BE AT POSITION A
XTAL CIRCUIT
9.8304MHz
OSC1
OSC2
FOR MC68HC908JL3E/JK3E/JK1E
SW1 AT POSITION A OR B 20 pF
MAX232
VDD
20 pF
1
16
15
VCC
C1+
+
+
+
1 µF
1 µF
1 µF
3
4
1 µF
C1–
C2+
GND
+
VDD + VHI
A
B
2
6
SW1
10 k
V+
V–
(SEE NOTE 1)
VDD
VDD
1 k
IRQ
8.5 V
5
C2–
1 µF
10 k
+
74HC125
6
DB9
5
10
9
2
3
7
8
PTB0
74HC125
3
4
VDD
2
VDD
10 k
1
5
10 k
PTB1
PTB3
PTB2
SW2
C
D
(SEE NOTE 2)
NOTES:
1. Monitor mode entry method:
SW1: Position A — High voltage entry (VTST
)
10 k
10 k
Clock source must be EXT OSC or XTAL CIRCUIT.
Bus clock depends on SW2.
SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF)
Bus clock = OSC1 ÷ 4.
2. Affects high voltage entry to monitor mode only (SW1 at position A):
SW2: Position C — Bus clock = OSC1 ÷ 4
SW2: Position D — Bus clock = OSC1 ÷ 2
5. See Table 16-4 for VDD + VHI voltage level requirements.
Figure 7-1. Monitor Mode Circuit
MC68HC908JL3E Family Data Sheet, Rev. 3
76
Freescale Semiconductor
Functional Description
7.3.1 Entering Monitor Mode
Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR and will allow communication at 9600 baud provided one of the following sets
of conditions is met:
1. If IRQ1 = VDD + VHI:
–
–
Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL)
PTB3 = low
2. If IRQ1 = VDD + VHI:
–
–
Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL)
PTB3 = high
3. If $FFFE & $FFFF is blank (contains $FF):
–
–
Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC)
IRQ1 = VDD
Table 7-1. Monitor Mode Entry Requirements and Options
Bus
OSC1 Frequency
Comments
Frequency
2.4576MHz
(OSC1 ÷ 2)
(2)
High-voltage entry to monitor
mode.(3)
9600 baud communication on
PTB0. COP disabled.
VDD + VHI
X
X
0
1
0
0
1
1
1
1
4.9152MHz
9.8304MHz
2.4576MHz
(OSC1 ÷ 4)
VDD + VHI
Low-voltage entry to monitor
mode.(4)
9600 baud communication on
PTB0. COP disabled.
BLANK
(contain
$FF)
2.4576MHz
(OSC1 ÷ 4)
VDD
X
X
X
1
9.8304MHz
NOT
BLANK
At desired
frequency
VDD
X
X
X
X
OSC1 ÷ 4
Enters User mode.
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using VDD + VHI for monitor mode entry.
The OSC1 clock must be 50% duty cycle for this condition.
2. See Table 16-4 for VDD + VHI voltage level requirements.
3. For IRQ1 = VDD + VHI:
MC68HRC908JL3E/JK3E/JK1E — clock must be EXT OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
4. For IRQ1 = VDD
:
MC68HRC908JL3E/JK3E/JK1E — clock must be RC OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
If VDD +VHI is applied to IRQ1 and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the
bus frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with VDD +VHI applied to IRQ1
upon monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock
input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two
stage at the oscillator only if VDD +VHI is applied to IRQ1. In this event, the OSCOUT frequency is equal
to the 2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the
OSC1 signal must have a 50% duty cycle at maximum bus frequency.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
77
Monitor ROM (MON)
Entering monitor mode with VDD + VHI on IRQ1, the COP is disabled as long as VDD + VHI is applied to
either the IRQ1 or the RST. (See Chapter 5 System Integration Module (SIM) for more information on
modes of operation.)
If entering monitor mode without high voltage on IRQ1 and reset vector being blank ($FFFE and $FFFF)
(Table 7-1 condition set 3, where applied voltage is VDD), then all port B pin requirements and conditions,
including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements
when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the
state of IRQ1 or the RST.
Figure 7-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ1
= VDD. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.
POR RESET
NO
IS VECTOR
BLANK?
NORMAL USER
MODE
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
NO
POR
TRIGGERED?
YES
Figure 7-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising
edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU waits for the host to send eight security bytes. (See 7.4 Security.) After the
security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is
ready to receive a command. The break signal also provides a timing reference to allow the host to
determine the necessary baud rate.
In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors
are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware
instead of user code.
Table 7-2 is a summary of the vector differences between user mode and monitor mode.
MC68HC908JL3E Family Data Sheet, Rev. 3
78
Freescale Semiconductor
Functional Description
Table 7-2. Monitor Mode Vector Differences
Functions
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
Modes
COP
User
Monitor
Notes:
Enabled
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
$FFFC
$FEFC
$FFFD
$FEFD
Disabled(1)
1. If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register.
When the host computer has completed downloading code into the MCU RAM, the host then sends a
RUN command, which executes an RTI, which sends control to the address on the stack pointer.
7.3.2 Baud Rate
The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud
rate if entry to monitor mode is by IRQ1 = VDD + VHI. When PTB3 is high, the divide by ratio is 1024. If
the PTB3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512.
Table 7-3. Monitor Baud Rate Selection
Monitor Mode
Entry By:
Input Clock
Frequency
PTB3
Baud Rate
4.9152 MHz
9.8304 MHz
4.9152 MHz
9.8304 MHz
4.9152 MHz
0
1
9600 bps
9600 bps
4800 bps
9600 bps
4800 bps
IRQ1 = VDD + VHI
1
X
X
Blank reset vector,
IRQ1 = VDD
7.3.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
(See Figure 7-3 and Figure 7-4.)
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 7-3. Monitor Data Format
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
79
Monitor ROM (MON)
NEXT
START
BIT
START
BIT
STOP
BIT
$A5
BIT 0
BIT 0
BIT 1
BIT 1
BIT 2
BIT 2
BIT 3
BIT 3
BIT 4
BIT 4
BIT 5
BIT 5
BIT 6
BIT 6
BIT 7
BIT 7
STOP
BIT
START
BIT
NEXT
START
BIT
BREAK
Figure 7-4. Sample Monitor Waveforms
The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive
baud rates must be identical.
7.3.4 Echoing
As shown in Figure 7-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin
for error checking.
SENT TO
MONITOR
READ
READ
ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW
DATA
ECHO
RESULT
Figure 7-5. Read Transaction
Any result of a command appears after the echo of the last byte of the command.
7.3.5 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 7-6.) When the monitor receives a break
signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 7-6. Break Transaction
7.3.6 Commands
The monitor ROM uses the following commands:
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
MC68HC908JL3E Family Data Sheet, Rev. 3
80
Freescale Semiconductor
Functional Description
Table 7-4. READ (Read Memory) Command
Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Returns contents of specified address
$4A
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Table 7-5. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
Opcode
None
$49
Command Sequence
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
81
Monitor ROM (MON)
Table 7-6. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Specifies 2-byte address in high byte:low byte order
Returns contents of next two addresses
$1A
Operand
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
Table 7-7. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
Opcode
None
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
NOTE
A sequence of IREAD or IWRITE commands can sequentially access a
block of memory over the full 64-Kbyte memory map.
MC68HC908JL3E Family Data Sheet, Rev. 3
82
Freescale Semiconductor
Security
Table 7-8. READSP (Read Stack Pointer) Command
Description
Reads stack pointer
Operand
None
Data Returned
Opcode
Returns stack pointer in high byte:low byte order
$0C
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
Table 7-9. RUN (Run User Program) Command
Description
Executes RTI instruction
Operand
None
None
$28
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
7.4 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTB0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code from FLASH. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. (See Figure 7-7.)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
83
Monitor ROM (MON)
VDD
4096 + 32 OSCXCLK CYCLES
24 BUS CYCLES
RST
FROM HOST
FROM MCU
PTB0
1
4
1
1
2
4
1
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 7-7. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
MC68HC908JL3E Family Data Sheet, Rev. 3
84
Freescale Semiconductor
Chapter 8
Timer Interface Module (TIM)
8.1 Introduction
This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that
provides a timing reference with input capture, output compare, and pulse-width-modulation functions.
Figure 8-1 is a block diagram of the TIM.
8.2 Features
Features of the TIM include the following:
•
Two input capture/output compare channels
–
–
Rising-edge, falling-edge, or any-edge input capture trigger
Set, clear, or toggle output compare action
•
•
•
•
•
Buffered and unbuffered pulse width modulation (PWM) signal generation
Programmable TIM clock input with 7-frequency internal bus clock prescaler selection
Free-running or modulo up-count operation
Toggle any channel pin on overflow
TIM counter stop and reset bits
8.3 Pin Name Conventions
The TIM share two I/O pins with two port D I/O pins. The full name of the TIM I/O pins are listed in
Table 8-1. The generic pin name appear in the text that follows.
Table 8-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM Pin Names:
TCH0
TCH1
PTD4/TCH0
PTD5/TCH1
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
85
Timer Interface Module (TIM)
8.4 Functional Description
Figure 8-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels are programmable independently as input capture or output compare channels.
PRESCALER SELECT
INTERNAL
PRESCALER
BUS CLOCK
TSTOP
PS2
PS1
PS0
TRST
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
TCH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
MS0A
CH0IE
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
TCH1
INTERRUPT
LOGIC
16-BIT LATCH
MS1A
CH1IE
Figure 8-1. TIM Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 3
86
Freescale Semiconductor
Functional Description
Addr.
Register Name
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
TIM Status and Control
Register
(TSC)
TOIE
TSTOP
PS2
PS1
PS0
$0020
TRST
0
0
0
1
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TIM Counter Register High
(TCNTH)
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TIM Counter Register Low
(TCNTL)
0
Bit15
1
0
Bit14
1
0
Bit13
1
0
Bit12
1
0
Bit11
1
0
Bit10
1
0
Bit9
1
0
TIM Counter Modulo Register
High
(TMODH)
Bit8
1
TIM Counter Modulo Register
Low
(TMODL)
Bit7
Bit6
1
Bit5
1
Bit4
1
Bit3
1
Bit2
1
Bit1
1
Bit0
1
1
CH0MAX
0
Read: CH0F
TIM Channel 0 Status and
Control Register
(TSC0)
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
TIM Channel 0
Register High
(TCH0H)
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Indeterminate after reset
Bit4 Bit3
Indeterminate after reset
TIM Channel 0
Register Low
(TCH0L)
Bit7
Bit6
Bit5
0
Bit2
Bit1
Bit0
Read: CH1F
TIM Channel 1 Status and
Control Register
(TSC1)
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
CH1MAX
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
TIM Channel 1
Register High
(TCH1H)
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Indeterminate after reset
Bit4 Bit3
Indeterminate after reset
TIM Channel 1
Register Low
(TCH1L)
Bit7
Bit6
Bit5
Bit2
Bit1
Bit0
= Unimplemented
Figure 8-2. TIM I/O Register Summary
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
87
Timer Interface Module (TIM)
8.4.1 TIM Counter Prescaler
The TIM clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC)
select the TIM clock source.
8.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
8.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
8.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 8.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
•
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
•
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
8.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
MC68HC908JL3E Family Data Sheet, Rev. 3
88
Freescale Semiconductor
Functional Description
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
8.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 8-3 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM
to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIM
to set the pin if the state of the PWM pulse is logic zero.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 8-3. PWM Period and Pulse Width
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000 (see 8.9.1 TIM Status and Control Register (TSC)).
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of
an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
8.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 8.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
89
Timer Interface Module (TIM)
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
•
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
•
When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
8.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel
1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
8.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
MC68HC908JL3E Family Data Sheet, Rev. 3
90
Freescale Semiconductor
Interrupts
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 8-3.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
select bits, ELSxB:ELSxA. The output action on compare must force the output to the
complement of the pulse width level. (See Table 8-3.)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSC0)
controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. (See 8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1).)
8.5 Interrupts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
•
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE=1.
CHxF and CHxIE are in the TIM channel x status and control register.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
91
Timer Interface Module (TIM)
8.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
8.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
8.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
8.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR).)
To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero
(its default state), software can read and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on
such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero.
After the break, doing the second step clears the status bit.
8.8 I/O Signals
Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1.
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin.
8.9 I/O Registers
The following I/O registers control and monitor operation of the TIM:
•
•
•
•
•
TIM status and control register (TSC)
TIM counter registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
MC68HC908JL3E Family Data Sheet, Rev. 3
92
Freescale Semiconductor
I/O Registers
8.9.1 TIM Status and Control Register (TSC)
The TIM status and control register does the following:
•
•
•
•
•
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Address:
$0020
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 8-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a logic zero to TOF. If another TIM overflow occurs before the clearing sequence is
complete, then writing logic zero to TOF has no effect. Therefore, a TOF interrupt request cannot be
lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as logic zero. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
93
Timer Interface Module (TIM)
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 8-2 shows. Reset clears the PS[2:0] bits.
Table 8-2. Prescaler Selection
PS2
0
PS1
0
PS0
0
TIM Clock Source
Internal Bus Clock ÷ 1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Not available
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
8.9.2 TIM Counter Registers (TCNTH:TCNTL)
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address:
$0021
Bit 7
TCNTH
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
0
0
0
0
0
0
0
0
Address:
$0022
Bit 7
Bit7
TCNTL
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-5. TIM Counter Registers (TCNTH:TCNTL)
MC68HC908JL3E Family Data Sheet, Rev. 3
94
Freescale Semiconductor
I/O Registers
8.9.3 TIM Counter Modulo Registers (TMODH:TMODL)
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address:
$0023
Bit 7
TMODH
6
5
Bit13
1
4
Bit12
1
3
Bit11
1
2
Bit10
1
1
Bit9
1
Bit 0
Bit8
1
Read:
Write:
Reset:
Bit15
1
Bit14
1
Address:
$0024
Bit 7
TMODL
6
5
Bit5
1
4
Bit4
1
3
Bit3
1
2
Bit2
1
1
Bit1
1
Bit 0
Bit0
1
Read:
Write:
Reset:
Bit7
1
Bit6
1
Figure 8-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)
Each of the TIM channel status and control registers does the following:
•
•
•
•
•
•
•
•
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Address:
$0025
Bit 7
CH0F
0
TSC0
6
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read:
Write:
Reset:
CH0IE
0
0
Figure 8-7. TIM Channel Status and Control Registers (TSC0:TSC1)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
95
Timer Interface Module (TIM)
Address:
$0028
TSC1
6
Bit 7
CH1F
0
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read:
Write:
Reset:
CH1IE
0
0
0
= Unimplemented
Figure 8-7. TIM Channel Status and Control Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x
status and control register with CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing logic zero to CHxF has no effect.
Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See Table 8-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See
Table 8-3.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
MC68HC908JL3E Family Data Sheet, Rev. 3
96
Freescale Semiconductor
I/O Registers
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin. Table 8-3 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
Table 8-3. Mode, Edge, and Level Selection
MSxB
MSxA
ELSxB
ELSxA
Mode
Configuration
Pin under Port Control;
Initial Output Level High
X
0
0
0
Output
Preset
Pin under Port Control;
Initial Output Level Low
X
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
X
X
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Input
Capture
Output
Compare Clear Output on Compare
or PWM
Set Output on Compare
Buffered
Output
Compareor
Buffered
PWM
Toggle Output on Compare
Clear Output on Compare
1
X
1
1
Set Output on Compare
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic one, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As Figure 8-8 shows, the CHxMAX bit takes effect in the cycle after
it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
97
Timer Interface Module (TIM)
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
OUTPUT
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
COMPARE
CHxMAX
Figure 8-8. CHxMAX Latency
8.9.5 TIM Channel Registers (TCH0H/L:TCH1H/L)
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address:
$0026
Bit 7
TCH0H
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Reset:
Indeterminate after reset
Address:
$0027
Bit 7
TCH0L
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Reset:
Indeterminate after reset
Address:
$0029
Bit 7
TCH1H
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Reset:
Indeterminate after reset
Address:
$02A
Bit 7
TCH1L
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Indeterminate after reset
Figure 8-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
MC68HC908JL3E Family Data Sheet, Rev. 3
98
Freescale Semiconductor
Chapter 9
Analog-to-Digital Converter (ADC)
9.1 Introduction
This section describes the 12-channel, 8-bit linear successive approximation analog-to-digital converter
(ADC).
9.2 Features
Features of the ADC module include:
•
•
•
•
•
•
12 channels with multiplexed input
Linear successive approximation with monotonicity
8-bit resolution
Single or continuous conversion
Conversion complete flag or conversion complete interrupt
Selectable ADC clock
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: COCO
ADC Status and Control
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
$003C
Register Write:
(ADSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADC Data Register
(ADR)
$003D
$003E
Indeterminate after reset
0
0
0
0
0
0
0
0
ADIV2
0
ADIV1
0
ADIV0
0
ADC Input Clock Register
(ADICLK)
0
0
Figure 9-1. ADC I/O Register Summary
9.3 Functional Description
Twelve ADC channels are available for sampling external sources at pins PTB0–PTB7 and PTD0–PTD3.
An analog multiplexer allows the single ADC converter to select one of the 12 ADC channels as ADC
voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters.
The ADC resolution is 8 bits. When the conversion is completed, ADC puts the result in the ADC data
register and sets a flag or generates an interrupt. Figure 9-2 shows a block diagram of the ADC.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
99
Analog-to-Digital Converter (ADC)
INTERNAL
DATA BUS
READ DDRB/DDRD
WRITE DDRB/DDRD
DISABLE
DDRBx/DDRDx
PTBx/PTDx
RESET
WRITE PTB/PTD
READ PTB/PTD
ADCx
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC VOLTAGE IN
ADCVIN
CONVERSION
COMPLETE
CHANNEL
SELECT
INTERRUPT
LOGIC
ADCH[4:0]
ADC
(1 OF 12 CHANNELS)
ADC CLOCK
AIEN
COCO
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
ADICLK
Figure 9-2. ADC Block Diagram
9.3.1 ADC Port I/O Pins
PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O pins that are shared with the ADC channels. The
channel select bits (ADC status and control register, $003C), define which ADC channel/port pin will be
used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is
selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding
DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
MC68HC908JL3E Family Data Sheet, Rev. 3
100
Freescale Semiconductor
Interrupts
9.3.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input
voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line
linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS.
NOTE
Input voltage should not exceed the analog supply voltages.
9.3.3 Conversion Time
Fourteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on
the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC
internal clock is selected to run at 1MHz, then one conversion will take 14µs to complete. With a 1MHz
ADC internal clock the maximum sample rate is 71.43kHz.
14 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
9.3.4 Continuous Conversion
In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC
data register with new data after each conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The
COCO bit (ADC status and control register, $003C) is set after each conversion and can be cleared by
writing the ADC status and control register or reading of the ADC data register.
9.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
9.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
9.5 Low-Power Modes
The following subsections describe the ADC in low-power modes.
9.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to logic 1’s before
executing the WAIT instruction.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
101
Analog-to-Digital Converter (ADC)
9.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
9.6 I/O Signals
The ADC module has 12 channels that are shared with I/O port B and port D.
9.6.1 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module.
9.7 I/O Registers
These I/O registers control and monitor ADC operation:
•
•
•
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADICLK)
9.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register.
Address:
$003C
Bit 7
6
AIEN
0
5
ADCO
0
4
ADCH4
1
3
ADCH3
1
2
ADCH2
1
1
ADCH1
1
Bit 0
ADCH0
1
Read:
Write:
Reset:
COCO
0
= Unimplemented
Figure 9-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADC status and control register is written or whenever the
ADC data register is read. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always
be logic 0 when read.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
MC68HC908JL3E Family Data Sheet, Rev. 3
102
Freescale Semiconductor
I/O Registers
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select
bits are detailed in the following table. Care should be taken when using a port pin as both an analog
and a digital input simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows
for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to
a logic 1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 9-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Channel
Input Select
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PTD3
PTD2
PTD1
PTD0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
:
0
0
0
0
1
1
1
1
0
0
0
0
1
:
0
0
1
1
0
0
1
1
0
0
1
1
0
:
0
1
0
1
0
1
0
1
0
1
0
1
0
:
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
ADC11
0
0
0
0
0
0
0
0
0
0
0
0
Unused
(see Note 1)
:
—
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
—
—
Reserved
Unused
1
1
V
V
(see Note 2)
(see Note 2)
DDA
SSA
1
1
ADC power off
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
103
Analog-to-Digital Converter (ADC)
9.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
Indeterminate after reset
= Unimplemented
Figure 9-4. ADC Data Register (ADR)
9.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC
Address:
$003E
Bit 7
6
ADIV1
0
5
ADIV0
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ADIV2
0
0
0
0
0
0
= Unimplemented
Figure 9-5. ADC Input Clock Register (ADICLK)
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC
clock. Table 9-2 shows the available clock configurations. The ADC clock should be set to
approximately 1MHz.
Table 9-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
ADC Input Clock ÷ 1
ADC Input Clock ÷ 2
ADC Input Clock ÷ 4
ADC Input Clock ÷ 8
ADC Input Clock ÷ 16
0
0
0
1
1
X
0
1
0
1
X
0
0
0
1
X = don’t care
MC68HC908JL3E Family Data Sheet, Rev. 3
104
Freescale Semiconductor
Chapter 10
Input/Output (I/O) Ports
10.1 Introduction
Twenty three (23) bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are
programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0000 Port A Data Register (PTA) Write:
Reset:
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
Read:
PTB7
PTB6
PTD6
PTB5
PTD5
PTB2
PTD2
PTB1
PTD1
PTB0
PTD0
$0001 Port B Data Register (PTB) Write:
Reset:
Read:
$0003 Port D Data Register (PTD) Write:
Reset:
PTD7
0
Read:
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
DDRA2
DDRA1
DDRA0
Data Direction Register A
(DDRA)
$0004
$0005
$0007
Write:
Reset:
Read:
Write:
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
DDRB7
0
DDRB6
0
DDRB5
0
DDRB4
0
Data Direction Register B
(DDRB)
Reset:
Read:
Write:
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
Reset:
Read:
Write:
Reset:
Read:
0
0
0
0
0
0
0
0
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Port D Control Register
(PDCR)
$000A
$000D
0
0
0
0
0
0
0
0
Port A Input Pull-up
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Enable Register Write:
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
Figure 10-1. I/O Port Register Summary
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
105
Input/Output (I/O) Ports
Table 10-1. Port Control Register Bits Summary
Module Control
Port
Bit
DDR
Pin
Module
Register
Control Bit
KBIE0
0
1
2
3
4
5
DDRA0
DDRA1
DDRA2
DDRA3
DDRA4
DDRA5
PTA0/KBI0
PTA1/KBI1
PTA2/KBI2
PTA3/KBI3
PTA4/KBI4
PTA5/KBI5
KBIE1
KBIE2
KBI
KBIER ($001B)
KBIE3
A
KBIE4
KBIE5
OSC
KBI
PTAPUE ($000D)
KBIER ($001B)
PTA6EN
KBIE6
6
DDRA6
RCCLK/PTA6/KBI6(1)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
DDRB0
DDRB1
DDRB2
DDRB3
DDRB4
DDRB5
DDRB6
DDRB7
DDRD0
DDRD1
DDRD2
DDRD3
DDRD4
DDRD5
DDRD6
DDRD7
PTB0/ADC0
PTB1/ADC1
PTB2/ADC2
PTB3/ADC3
PTB4/ADC4
PTB5/ADC5
PTB6/ADC6
PTB7/ADC7
PTD0/ADC11
PTD1/ADC10
PTD2/ADC9
PTD3/ADC8
PTD4/TCH0
PTD5/TCH1
PTD6
B
ADC
ADSCR ($003C)
ADCH[4:0]
ADC
TIM
ADSCR ($003C)
ADCH[4:0]
D
TSC0 ($0025)
ELS0B:ELS0A
TSC1 ($0028)
ELS1B:ELS1A
—
—
—
—
—
—
PTD7
1. RCCLK/PTA6/KBI6 pin is only available on MC68HRC908JL3E/JK3E/JK1E devices (RC option);
PTAPUE register has priority control over the port pin.
RCCLK/PTA6/KBI6 is the OSC2 pin on MC68HC908JL3E/JK3E/JK1E devices (X-TAL option).
MC68HC908JL3E Family Data Sheet, Rev. 3
106
Freescale Semiconductor
Port A
10.2 Port A
Port A is an 7-bit special function port that shares all seven of its pins with the keyboard interrupt (KBI)
module (see Chapter 12 Keyboard Interrupt Module (KBI)). Each port A pin also has software configurable
pull-up device if the corresponding port pin is configured as input port. PTA0 to PTA5 has direct LED drive
capability.
NOTE
PTA0–PTA5 pins are available on MC68H(R)C908JL3E only.
PTA6 pin is available on MC68HRC908JL3E/JK3E/JK1E only.
10.2.1 Port A Data Register (PTA)
The port A data register (PTA) contains a data latch for each of the seven port A pins.
Address:
$0000
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Unaffected by Reset
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
Additional Functions:
30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up
Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Figure 10-2. Port A Data Register (PTA)
PTA[6:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBI[6:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE[6:0], in the keyboard interrupt control register (KBIER) enable
the port A pins as external interrupt pins, (see Chapter 12 Keyboard Interrupt Module (KBI)).
10.2.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic one
to a DDRA bit enables the output buffer for the corresponding port A pin; a logic zero disables the output
buffer.
Address:
$0004
Bit 7
0
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
0
Figure 10-3. Data Direction Register A (DDRA)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
107
Input/Output (I/O) Ports
DDRA[6:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[6:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 10-4 shows the port A I/O logic.
READ DDRA ($0004)
PTAPUEx
WRITE DDRA ($0004)
DDRAx
RESET
30k
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
To Keyboard Interrupt Circuit
Figure 10-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
10.2.3 Port A Input Pull-up Enable Register (PTAPUE)
The port A input pull-up enable register (PTAPUE) contains a software configurable pull-up device for
each of the seven port A pins. Each bit is individually configurable and requires the corresponding data
direction register, DDRAx be configured as input. Each pull-up device is automatically and dynamically
disabled when its corresponding DDRAx bit is configured as output.
Address:
$000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
0
0
0
Figure 10-5. Port A Input Pull-up Enable Register (PTAPUE)
PTA6EN — Enable PTA6 on OSC2
This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has
no effect for X-tal oscillator option.
1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions
0 = OSC2 pin outputs the RC oscillator clock (RCCLK)
MC68HC908JL3E Family Data Sheet, Rev. 3
108
Freescale Semiconductor
Port B
PTAPUE[6:0] — Port A Input Pull-up Enable Bits
These read/write bits are software programmable to enable pull-up devices on port A pins
1 = Corresponding port A pin configured to have internal pull-up if its DDRA bit is set to 0
0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its
DDRA bit
Table 10-2 summarizes the operation of the port A pins.
Table 10-2. Port A Pin Functions
Accesses to DDRA
Read/Write
DDRA[6:0]
Accesses to PTA
DDRA
Bit
PTAPUE Bit
PTA Bit
I/O Pin Mode
Read
Write
X(1)
X
Input, VDD
Pin
Pin
PTA[6:0](3)
PTA[6:0](3)
PTA[6:0]
(2)
1
0
X
0
0
1
Input, Hi-Z(4)
Output
DDRA[6:0]
X
DDRA[6:0]
PTA[6:0]
1. X = Don’t care.
2. I/O pin pulled to VDD by internal pull-up.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High Impedance.
10.3 Port B
Port B is an 8-bit special function port that shares all eight of its port pins with the analog-to-digital
converter (ADC) module, see Chapter 9
10.3.1 Port B Data Register (PTB)
The port B data register contains a data latch for each of the eight port B pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Reset:
Unaffected by reset
ADC4 ADC3
Alternative Function:
ADC7
ADC6
AD4C5
ADC2
ADC2
ADC0
Figure 10-6. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
ADC[7:0] — ADC channels 7 to 0
ADC[7:0] are pins used for the input channels to the analog-to-digital converter module. The channel
select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an
ADC input and overrides any control from the port I/O logic. See Chapter 9 Analog-to-Digital Converter
(ADC).
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
109
Input/Output (I/O) Ports
10.3.2 Data Direction Register B (DDRB)
Data direction register B determines whether each port B pin is an input or an output. Writing a logic one
to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output
buffer.
Address:
$0005
Bit 7
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
DDRB7
0
Figure 10-7. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
To Analog-To-Digital Converter
Figure 10-8. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 10-3 summarizes the operation of the port B pins.
Table 10-3. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
DDRB Bit
PTB Bit
I/O Pin Mode
Read
Pin
Write
0
1
X(1)
X
Input, Hi-Z(2)
Output
DDRB[7:0]
PTB[7:0](3)
DDRB[7:0]
Pin
PTB[7:0]
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
MC68HC908JL3E Family Data Sheet, Rev. 3
110
Freescale Semiconductor
Port D
10.4 Port D
Port D is an 8-bit special function port that shares two of its pins with timer interface module, (see Chapter
8) and shares four of its pins with analog-to-digital converter module (see Chapter 9). PTD6 and PTD7
each has high current drive (25mA sink) and programmable pull-up. PTD2, PTD3, PTD6 and PTD7 each
has LED driving (sink) capability.
NOTE
PTD0–PTD1 are available on MC68H(R)C908JL3E only.
10.4.1 Port D Data Register (PTD)
The port D data register contains a data latch for each of the eight port D pins.
Address:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by reset
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
Additional Functions
ADC8
TCH0
ADC9
ADC10
ADC11
TCH1
25mA sink
25mA sink
(Slow Edge) (Slow Edge)
5k pull-up 5k pull-up
Figure 10-9. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
ADC[11:8] — ADC channels 11 to 8
ADC[11:8] are pins used for the input channels to the analog-to-digital converter module. The channel
select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an
ADC input and overrides any control from the port I/O logic. See Chapter 9 Analog-to-Digital Converter
(ADC).
TCH[1:0] — Timer Channel I/O
The TCH1 and TCH0 pins are the TIM input capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTD4/TCH0 and PTD5/TCH1 pins are timer channel I/O pins
or general-purpose I/O pins. See Chapter 8 Timer Interface Module (TIM).
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
111
Input/Output (I/O) Ports
10.4.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a logic one
to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output
buffer.
Address:
$0007
Bit 7
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Read:
Write:
Reset:
DDRD7
0
Figure 10-10. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 10-11 shows the
port D I/O logic.
READ DDRD ($0007)
PTDPU[6:7]
WRITE DDRD ($0007)
DDRDx
RESET
5k
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
PTD[0:3] To Analog-To-Digital Converter
PTD[4:5] To Timer
Figure 10-11. Port D I/O Circuit
When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 10-4 summarizes the operation of the port D pins.
MC68HC908JL3E Family Data Sheet, Rev. 3
112
Freescale Semiconductor
Port D
Table 10-4. Port D Pin Functions
Accessesto
Accesses to PTD
Read Write
DDRD
Bit
DDRD
PTD Bit
I/O Pin Mode
Read/Write
DDRD[7:0]
DDRD[7:0]
0
1
X(1)
X
Input, Hi-Z(2)
Output
Pin
Pin
PTD[7:0](3)
PTD[7:0]
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
10.4.3 Port D Control Register (PDCR)
The port D control register enables/disables the pull-up resistor and slow-edge high current capability of
pins PTD6 and PTD7.
Address:
$000A
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
PTDPU6
0
Read:
Write:
Reset:
SLOWD7 SLOWD6 PTDPU7
0
0
0
0
0
0
0
Figure 10-12. Port D Control Register (PDCR)
SLOWDx — Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain, high current output (25mA sink)
of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
PTDPUx — Pull-up Enable
The PTDPU6 and PTDPU7 bits enable the 5kΩ pull-up on PTD6 and PTD7 respectively, regardless
the status of DDRDx bit.
1 = Enable 5kΩ pull-up
0 = Disable 5kΩ pull-up
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
113
Input/Output (I/O) Ports
MC68HC908JL3E Family Data Sheet, Rev. 3
114
Freescale Semiconductor
Chapter 11
External Interrupt (IRQ)
11.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
11.2 Features
Features of the IRQ module include the following:
•
•
•
•
•
•
A dedicated external interrupt pin, IRQ1
IRQ1 interrupt control bits
Hysteresis buffer
Programmable edge-only or edge and level interrupt sensitivity
Automatic interrupt acknowledge
Selectable internal pullup resistor
11.3 Functional Description
A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 11-1 shows the
structure of the IRQ module.
Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An interrupt latch remains set until one
of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the IRQ latch.
•
Software clear — Software can clear the interrupt latch by writing to the acknowledge bit in the
interrupt status and control register (INTSCR). Writing a logic one to the ACK1 bit clears the IRQ1
latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge
or falling-edge and low-level-triggered. The MODE1 bit in the INTSCR controls the triggering sensitivity
of the IRQ1 pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch,
software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set
until both of the following occur:
•
•
Vector fetch or software clear
Return of the interrupt pin to logic one
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
115
External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long
as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK1 bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See 5.5 Exception Control.)
ACK1
RESET
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQPUD
VDD
INTERNAL
IRQF1
PULLUP
DEVICE
CLR
D
Q
SYNCHRO-
NIZER
IRQ1
INTERRUPT
REQUEST
CK
IRQ1
IRQ1
FF
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 11-1. IRQ Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
0
1
IMASK1
0
Bit 0
MODE1
0
Read:
0
0
0
0
IRQF1
IRQ Status and Control
$001D
Register Write:
(INTSCR)
Reset:
ACK1
0
0
0
0
0
0
= Unimplemented
Figure 11-2. IRQ I/O Register Summary
11.3.1 IRQ1 Pin
A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software
clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and low-level-sensitive. With MODE1
set, both of the following actions must occur to clear IRQ1:
MC68HC908JL3E Family Data Sheet, Rev. 3
116
Freescale Semiconductor
IRQ Module During Break Interrupts
•
•
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the
ACK1 bit in the interrupt status and control register (INTSCR). The ACK1 bit is useful in
applications that poll the IRQ1 pin and require software to clear the IRQ1 latch. Writing to the ACK1
bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise.
Setting ACK1 does not affect subsequent transitions on the IRQ1 pin. A falling edge that occurs
after writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask bit, IMASK1, is
clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ1 pin to logic one — As long as the IRQ1 pin is at logic zero, IRQ1 remains active.
The vector fetch or software clear and the return of the IRQ1 pin to logic one may occur in any order. The
interrupt request remains pending as long as the IRQ1 pin is at logic zero. A reset will clear the latch and
the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or
software clear immediately clears the IRQ1 latch.
The IRQF1 bit in the INTSCR register can be used to check for pending interrupts. The IRQF1 bit is not
affected by the IMASK1 bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
NOTE
An internal pull-up resistor to VDD is connected to the IRQ1 pin; this can be
disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
11.4 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ1 latch can be cleared during the break
state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during
the break state. (See Chapter 5 System Integration Module (SIM).)
To allow software to clear the IRQ1 latch during a break interrupt, write a logic one to the BCFE bit. If a
latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero
(its default state), writing to the ACK1 bit in the IRQ status and control register during the break state has
no effect on the IRQ latch.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
117
External Interrupt (IRQ)
11.5 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR has the following functions:
•
•
•
•
Shows the state of the IRQ1 flag
Clears the IRQ1 latch
Masks IRQ1 and interrupt request
Controls triggering sensitivity of the IRQ1 interrupt pin
Address:
$001D
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASK1
0
Bit 0
MODE1
0
Read:
Write:
Reset:
IRQF1
ACK1
0
0
0
0
0
0
= Unimplemented
Figure 11-3. IRQ Status and Control Register (INTSCR)
IRQF1 — IRQ1 Flag
This read-only status bit is high when the IRQ1 interrupt is pending.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic one to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic zero. Reset
clears ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic one to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
POR:
IRQPUD
R
R
LVIT1
LVIT0
R
R
Not affected Not affected
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
Figure 11-4. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ1 Pin Pull-up control bit
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ1 pin and VDD
MC68HC908JL3E Family Data Sheet, Rev. 3
118
Freescale Semiconductor
Chapter 12
Keyboard Interrupt Module (KBI)
12.1 Introduction
The keyboard interrupt module (KBI) provides seven independently maskable external interrupts which
are accessible via PTA0–PTA6 pins.
12.2 Features
Features of the keyboard interrupt module include the following:
•
Seven keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard
interrupt mask
•
•
•
Software configurable pull-up device if input pin is configured as input port bit
Programmable edge-only or edge- and level- interrupt sensitivity
Exit from low-power modes
Addr.
Register Name
Bit 7
6
5
4
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status
and Control Register Write:
$001A
(KBSCR)
Reset:
0
0
0
KBIE6
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
Read:
Keyboard Interrupt
Enable Register Write:
KBIE2
0
KBIE1
0
KBIE0
0
$001B
(KBIER)
Reset:
0
= Unimplemented
Figure 12-1. KBI I/O Register Summary
12.3 I/O Pins
The seven keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins
are listed in Table 12-1. The generic pin name appear in the text that follows.
Table 12-1. Pin Name Conventions
KBI
Pin Selected for KBI Function by KBIEx
Bit in KBIER
Full MCU Pin Name
Generic Pin Name
KBI0–KBI5
KBI6
PTA0/KBI0–PTA5/KBI5
RCCLK/PTA6/KBI6(1)
KBIE0–KBIE5
KBIE6
1. RCCLK/PTA6/KBI6 pin is only available on MC68HRC908JL3E/JK3E/JK1E devices (RC option).
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
119
Keyboard Interrupt Module (KBI)
12.4 Functional Description
INTERNAL BUS
VECTOR FETCH
DECODER
KBI0
ACKK
VDD
KEYF
RESET
CLR
.
D
Q
SYNCHRONIZER
Keyboard
Interrupt
Request
KBIE0
.
CK
TO PULLUP ENABLE
.
KEYBOARD
INTERRUPT FF
IMASKK
KBI6
MODEK
KBIE6
TO PULLUP ENABLE
Figure 12-2. Keyboard Interrupt Block Diagram
Writing to the KBIE6–KBIE0 bits in the keyboard interrupt enable register independently enables or
disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also
enables its internal pull-up device irrespective of PTAPUEx bits in the port A input pull-up enable register
(see 10.2.3 Port A Input Pull-up Enable Register (PTAPUE)). A logic 0 applied to an enabled keyboard
interrupt pin latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK
bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an
interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on
one pin because another pin is still low, software can disable the latter pin while it is low.
If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as
long as any keyboard pin is low.
•
If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both
of the following actions must occur to clear a keyboard interrupt request:
•
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1
to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in
applications that poll the keyboard interrupt pins and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the vector address at locations $FFE0 and $FFE1.
•
Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
MC68HC908JL3E Family Data Sheet, Rev. 3
120
Freescale Semiconductor
Keyboard Interrupt Registers
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, disable the pull-up device, use the data direction
register to configure the pin as an input and then read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a logic 0 for software to
read the pin.
12.4.1 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore
a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction
register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
12.5 Keyboard Interrupt Registers
Two registers control the operation of the keyboard interrupt module:
•
•
Keyboard status and control register
Keyboard interrupt enable register
12.5.1 Keyboard Status and Control Register
•
•
•
•
Flags keyboard interrupt requests
Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
121
Keyboard Interrupt Module (KBI)
Address:
$001A
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
Write:
Reset:
KEYF
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 12-3. Keyboard Status and Control Register (KBSCR)
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port-A. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-A. ACKK always
reads as logic 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from
generating interrupt requests on port-A. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port-A. Reset
clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
12.5.2 Keyboard Interrupt Enable Register
The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a
keyboard interrupt pin.
Address:
$001B
Bit 7
0
6
KBIE6
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
Figure 12-4. Keyboard Interrupt Enable Register (KBIER)
KBIE6–KBIE0 — Port-A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin on port-A to latch
interrupt requests. Reset clears the keyboard interrupt enable register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
MC68HC908JL3E Family Data Sheet, Rev. 3
122
Freescale Semiconductor
Low-Power Modes
12.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
12.6.1 Wait Mode
The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
12.6.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
12.7 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE
bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default
state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during
the break state has no effect.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
123
Keyboard Interrupt Module (KBI)
MC68HC908JL3E Family Data Sheet, Rev. 3
124
Freescale Semiconductor
Chapter 13
Computer Operating Properly (COP)
13.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
CONFIG1 register.
13.2 Functional Description
Figure 13-1 shows the structure of the COP module.
SIM
2OSCOUT
SIM RESET CIRCUIT
12-BIT SIM COUNTER
RESET STATUS REGISTER
INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG1)
NOTE: See SIM section for more details.
Figure 13-1. COP Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
125
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
218 – 24 or 213 – 24 2OSCOUT cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 218 – 24 2OSCOUT cycle overflow option, a 8MHz crystal gives a COP
timeout period of 32.766 ms. Writing any value to location $FFFF before an overflow occurs prevents a
COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 × 2OSCOUT cycles and sets the COP bit in the reset status
register (RSR). (See 5.7.2 Reset Status Register (RSR).).
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
13.3 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1.
13.3.1 2OSCOUT
2OSCOUT is the oscillator output signal. 2OSCOUT frequency is equal to the crystal frequency or the
RC-oscillator frequency.
13.3.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 13.4 COP Control Register) clears the
COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns
the low byte of the reset vector.
13.3.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × 2OSCOUT cycles after
power-up.
13.3.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
13.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the SIM counter.
13.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).
(See Chapter 3 Configuration Registers (CONFIG).)
MC68HC908JL3E Family Data Sheet, Rev. 3
126
Freescale Semiconductor
COP Control Register
13.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
Address:
$001F
Bit 7
6
5
R
0
4
LVID
0
3
R
0
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
R
0
0
R
= Reserved
Figure 13-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is (213 – 24) × 2OSCOUT cycles
0 = COP timeout period is (218 – 24) × 2OSCOUT cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
13.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
Figure 13-3. COP Control Register (COPCTL)
13.5 Interrupts
The COP does not generate CPU interrupt requests.
13.6 Monitor Mode
The COP is disabled in monitor mode when VDD + VHI is present on the IRQ1 pin or on the RST pin.
13.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
127
Computer Operating Properly (COP)
13.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter in a CPU interrupt routine.
13.7.2 Stop Mode
Stop mode turns off the 2OSCOUT input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
13.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VDD + VHI is present on the RST pin.
MC68HC908JL3E Family Data Sheet, Rev. 3
128
Freescale Semiconductor
Chapter 14
Low Voltage Inhibit (LVI)
14.1 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin
and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage.
14.2 Features
Features of the LVI module include the following:
•
•
Selectable LVI trip voltage
Selectable LVI circuit disable
14.3 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module
contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to
monitor VDD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine at which VDD level the
LVI module should take actions.
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when VDD drops to below the set trip
point.
VDD
LVID
VDD > LVITRIP = 0
LVI RESET
VDD < LVITRIP = 1
LOW VDD
DETECTOR
LVIT1
LVIT0
Figure 14-1. LVI Module Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
129
Low Voltage Inhibit (LVI)
14.4 LVI Control Register (CONFIG2/CONFIG1)
The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2.
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
POR:
IRQPUD
R
R
LVIT1
LVIT0
R
R
Not affected Not affected
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-2. Configuration Register 2 (CONFIG2)
Address:
$001F
Bit 7
6
5
R
0
4
LVID
0
3
R
0
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
R
0
0
R
= Reserved
Figure 14-3. Configuration Register 1 (CONFIG1)
LVID — Low Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 — LVI Trip Voltage Selection
These two bits determine at which level of VDD the LVI module will come into action. LVIT1 and LVIT0
are cleared by a Power-On Reset only.
Trip Voltage(1)
VLVR3 (2.4V)
VLVR3 (2.4V)
LVIT1
LVIT0
Comments
0
0
1
1
0
1
0
1
For VDD=3V operation
For VDD=3V operation
For VDD=5V operation
VLVR5 (4.0V)
Reserved
1. See Chapter 16 Electrical Specifications for full parameters.
14.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power-consumption standby modes.
14.5.1 Wait Mode
The LVI module, when enabled, will continue to operate in WAIT Mode.
14.5.2 Stop Mode
The LVI module, when enabled, will continue to operate in STOP Mode.
MC68HC908JL3E Family Data Sheet, Rev. 3
130
Freescale Semiconductor
Chapter 15
Break Module (BREAK)
15.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
15.2 Features
Features of the break module include the following:
•
•
•
•
Accessible I/O registers during the break Interrupt
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts
15.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction
register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The
program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
•
Software writes a logic one to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal operation. Figure 15-1 shows the
structure of the break module.
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
CONTROL
BKPT
(TO SIM)
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 15-1. Break Module Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
131
Break Module (BREAK)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
See note
0
Bit 0
Read:
Write:
Reset:
Read:
R
R
R
R
R
R
R
Break Status Register
(BSR)
$FE00
Break Flag Control
BCFE
0
R
R
R
R
R
R
R
$FE03
$FE0C
$FE0D
$FE0E
Register Write:
(BFCR)
Reset:
Read:
Break Address High
Bit15
0
Bit14
0
Bit13
0
Bit12
0
Bit11
0
Bit10
0
Bit9
0
Bit8
0
Register Write:
(BRKH)
Reset:
Read:
Break Address low
Bit7
0
Bit6
0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Register Write:
(BRKL)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
BRKE
0
BRKA
Register Write:
(BRKSCR)
Reset:
0
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
= Unimplemented
R
= Reserved
Figure 15-2. Break I/O Register Summary
15.3.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR) and see the Break Interrupts
subsection for each module.)
15.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD
($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
15.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VDD + VHI is present on the RST pin.
MC68HC908JL3E Family Data Sheet, Rev. 3
132
Freescale Semiconductor
Break Module Registers
15.4 Break Module Registers
These registers control and monitor operation of the break module:
•
•
•
•
•
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
15.4.1 Break Status and Control Register (BRKSCR)
The break status and control register contains break module enable and status bits.
Address: $FE0E
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 15-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
zero to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a logic one to
BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break
routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
15.4.2 Break Address Registers
The break address registers contain the high and low bytes of the desired breakpoint address. Reset
clears the break address registers.
Address: $FE0C
Bit 7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Figure 15-4. Break Address Register High (BRKH)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
133
Break Module (BREAK)
Address: $FE0D
Bit 7
Bit 7
0
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
Bit 0
0
Read:
Write:
Reset:
Figure 15-5. Break Address Register Low (BRKL)
15.4.3 Break Status Register
The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
Note(1)
0
R
R
R
R
R
R
R
= Reserved
1. Writing a logic zero clears SBSW.
Figure 15-6. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. The following code is an example of this.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU
LOBYTE EQU
5
6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not zero,
; then just decrement low byte.
; Else deal with high byte, too.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
MC68HC908JL3E Family Data Sheet, Rev. 3
134
Freescale Semiconductor
Low-Power Modes
15.4.4 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear status bits while the MCU is in a
break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 15-7. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
15.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
15.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set (see 5.6 Low-Power Modes). Clear the SBSW bit by writing
logic zero to it.
15.5.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 5.7
SIM Registers.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
135
Break Module (BREAK)
MC68HC908JL3E Family Data Sheet, Rev. 3
136
Freescale Semiconductor
Chapter 16
Electrical Specifications
16.1 Introduction
This section contains electrical and timing specifications.
16.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to Sections 16.5 and 16.8 for guaranteed operating conditions.
Table 16-1. Absolute Maximum Ratings
Characteristic(1)
Supply voltage
Symbol
VDD
Value
Unit
V
–0.3 to +6.0
VIN
VSS–0.3 to VDD +0.3
VSS–0.3 to +8.5
Input voltage
V
VDD+VHI
Mode entry voltage, IRQ1 pin
V
Maximum current per pin excluding VDD
and VSS
I
±25
mA
TSTG
IMVSS
IMVDD
Storage temperature
–55 to +150
100
°C
mA
mA
Maximum current out of VSS
Maximum current into VDD
100
1. Voltages referenced to VSS
.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
137
Electrical Specifications
16.3 Functional Operating Range
Table 16-2. Operating Range
Characteristic
Operating temperature range
Operating voltage range
Symbol
Value
Unit
°C
TA
–40 to +125
–40 to +85
VDD
5 ±10%
3 ±10%
V
16.4 Thermal Characteristics
Table 16-3. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
20-pin PDIP
20-pin SOIC
28-pin PDIP
28-pin SOIC
48-pin LQFP
70
°C/W
°C/W
°C/W
°C/W
°C/W
70
70
70
80
θJA
PI/O
PD
I/O pin power dissipation
User determined
W
PD = (IDD × VDD) + PI/O
K/(TJ + 273 °C)
=
Power dissipation(1)
W
PD x (TA + 273 °C)
+ PD2 × θJA
Constant(2)
K
W/°C
°C
TJ
TA + (PD × θJA)
Average junction temperature
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known TA and measured PD.
With this value of K, PD and TJ can be determined for any value of TA.
MC68HC908JL3E Family Data Sheet, Rev. 3
138
Freescale Semiconductor
5V DC Electrical Characteristics
16.5 5V DC Electrical Characteristics
Table 16-4. DC Electrical Characteristics (5V)
Characteristic(1)
Output high voltage (ILOAD = –2.0mA)
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7
Output low voltage (ILOAD = 1.6mA)
Typ(2)
Symbol
Min
Max
Unit
VOH
VDD–0.8
—
—
V
VOL
VOL
IOL
—
—
10
—
—
16
0.4
0.5
22
V
V
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5
Output low voltage (ILOAD = 25mA)
PTD6, PTD7
LED drives (VOL = 3V)
PTA0–PTA5, PTD2, PTD3, PTD6, PTD7
mA
Input high voltage
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
VIH
VIL
0.7 × VDD
VDD
—
—
V
V
Input low voltage
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
VSS
0.3 × VDD
V
DD supply current, fOP = 4MHz
Run(3)
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
Wait(4)
—
—
10
4.5
11
5
mA
mA
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
Stop(5)
—
—
6
1
6.5
1.5
mA
mA
IDD
(–40°C to 85°C)
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
(–40°C to 125°C)
—
—
2
2
5
5
µA
µA
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
—
—
2
2
10
10
µA
µA
IIL
Digital I/O ports Hi-Z leakage current
Input current
—
—
—
—
± 10
± 1
µA
µA
IIN
COUT
CIN
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
POR rearm voltage(6)
VPOR
RPOR
0
—
—
—
100
—
mV
V/ms
V
POR rise time ramp rate(7)
Monitor mode entry voltage
0.035
VDD+VHI
1.5 × VDD
8.5
Pullup resistors(8)
PTD6, PTD7
RST, IRQ1, PTA0–PTA6
RPU1
RPU2
1.8
16
3.3
26
4.8
36
kΩ
kΩ
VLVR5
LVI reset voltage
3.6
4.0
4.4
V
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
139
Electrical Specifications
4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD
.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V.
16.6 5V Control Timing
Table 16-5. Control Timing (5V)
Characteristic(1)
Internal operating frequency(2)
RST input pulse width low(3)
Symbol
fOP
Min
—
Max
8
Unit
MHz
ns
tIRL
750
—
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
16.7 5V Oscillator Characteristics
Table 16-6. Oscillator Component Specifications (5V)
Characteristic
Crystal frequency, XTALCLK
RC oscillator frequency, RCCLK
Symbol
Min
—
2
Typ
10
Max
32
Unit
MHz
MHz
fOSCXCLK
fRCCLK
10
12
External clock
reference frequency(1)
fOSCXCLK
dc
—
32
MHz
Crystal load capacitance(2)
Crystal fixed capacitance(2)
CL
C1
—
—
—
—
—
—
2 × CL
2 × CL
10 MΩ
—
—
—
—
—
—
Crystal tuning capacitance(2)
Feedback bias resistor
C2
RB
Series resistor(2), (3)
RS
REXT
CEXT
RC oscillator external R
RC oscillator external C
See Figure 16-1
10
—
—
pF
1. No more than 10% duty cycle deviation from 50%.
2. Consult crystal vendor data sheet.
3. Not required for high frequency crystals.
MC68HC908JL3E Family Data Sheet, Rev. 3
140
Freescale Semiconductor
3V DC Electrical Characteristics
14
12
10
8
C
= 10 pF
EXT
MCU
5V @ 25°C
OSC1
6
V
DD
4
R
C
EXT
EXT
2
0
0
10
20
30
(k
40
50
Resistor, R
Ω)
EXT
Figure 16-1. RC vs. Frequency (5V @25°C)
16.8 3V DC Electrical Characteristics
Table 16-7. DC Electrical Characteristics (3V)
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
Output high voltage (ILOAD = –1.0mA)
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7
Output low voltage (ILOAD = 0.8mA)
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5
Output low voltage (ILOAD = 20mA)
PTD6, PTD7
VOH
VDD–0.4
—
—
V
VOL
VOL
IOL
—
—
3
—
—
6
0.4
0.5
10
V
V
LED drives (VOL = 1.8V)
PTA0–PTA5, PTD2, PTD3, PTD6, PTD7
mA
Input high voltage
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
VIH
VIL
0.7 × VDD
VDD
—
—
V
V
Input low voltage
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
VSS
0.3 × VDD
VDD supply current, fOP = 2MHz
Run(3)
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
Wait(4)
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
Stop(5)
—
—
3
1.5
3.5
2
mA
mA
IDD
—
—
1.5
0.2
2
0.3
mA
mA
(–40°C to 85°C)
MC68HC908JL3E/JK3E/JK1E
MC68HRC908JL3E/JK3E/JK1E
—
—
1
1
5
5
µA
µA
IIL
Digital I/O ports Hi-Z leakage current
—
—
± 10
µA
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
141
Electrical Specifications
Table 16-7. DC Electrical Characteristics (3V)
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
IIN
Input current
—
—
± 1
µA
COUT
CIN
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
POR rearm voltage(6)
VPOR
RPOR
0
—
—
—
100
—
mV
V/ms
V
POR rise time ramp rate(7)
Monitor mode entry voltage
0.035
V
DD+VHI
1.5 × VDD
8.5
Pullup resistors(8)
PTD6, PTD7
RST, IRQ1, PTA0–PTA6
RPU1
RPU2
1.8
16
3.3
26
4.8
36
kΩ
kΩ
VLVR3
LVI reset voltage
2.0
2.4
2.69
V
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD
.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V.
16.9 3V Control Timing
Table 16-8. Control Timing (3V)
Characteristic(1)
Internal operating frequency(2)
RST input pulse width low(3)
Symbol
fOP
Min
—
Max
4
Unit
MHz
µs
tIRL
1.5
—
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
mation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68HC908JL3E Family Data Sheet, Rev. 3
142
Freescale Semiconductor
3V Oscillator Characteristics
16.10 3V Oscillator Characteristics
Table 16-9. Oscillator Component Specifications (3V)
Characteristic
Crystal frequency, XTALCLK
RC oscillator frequency, RCCLK
Symbol
Min
—
2
Typ
8
Max
16
Unit
MHz
MHz
fOSCXCLK
fRCCLK
8
12
External clock
reference frequency(1)
fOSCXCLK
dc
—
16
MHz
Crystal load capacitance(2)
Crystal fixed capacitance(2)
CL
C1
—
—
—
—
—
—
2 × CL
2 × CL
10 MΩ
—
—
—
—
—
—
Crystal tuning capacitance(2)
Feedback bias resistor
C2
RB
Series resistor(2), (3)
RS
REXT
CEXT
RC oscillator external R
RC oscillator external C
See Figure 16-2
10
—
—
pF
1. No more than 10% duty cycle deviation from 50%.
2. Consult crystal vendor data sheet.
3. Not required for high frequency crystals.
14
12
10
8
C
= 10 pF
MCU
EXT
3V @ 25°C
OSC1
6
V
DD
R
C
EXT
4
EXT
2
0
0
10
20
30
(kΩ)
40
50
Resistor, R
EXT
Figure 16-2. RC vs. Frequency (3V @25°C)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
143
Electrical Specifications
16.11 Typical Supply Currents
14
12
10
8
6
MC68HC908JL3E/JK3E/JK1E
4
5.5 V
3.3 V
2
0
0
1
2
3
4
5
6
7
8
9
fOP or fBUS (MHz)
Figure 16-3. Typical Operating IDD (MC68HC908JL3E/JK3E/JK1E),
with All Modules Turned On (25 °C)
10
MC68HRC908JL3E/JK3E/JK1E
8
5.5 V
3.3 V
6
4
2
0
0
1
2
3
4
5
6
7
8
9
fOP or fBUS (MHz)
Figure 16-4. Typical Operating IDD (MC68HRC908JL3E/JK3E/JK1E),
with All Modules Turned On (25 °C)
10
MC68HC908JL3E/JK3E/JK1E
8
5.5 V
3.3 V
6
4
2
0
0
1
2
3
4
5
6
7
8
9
fOP or fBUS (MHz)
Figure 16-5. Typical Wait Mode IDD (MC68HC908JL3E/JK3E/JK1E),
with All Modules Turned Off (25 °C)
MC68HC908JL3E Family Data Sheet, Rev. 3
144
Freescale Semiconductor
ADC Characteristics
2
1.75
1.50
1.25
1
MC68HRC908JL3E/JK3E/JK1E
5.5 V
3.3 V
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
8
fOP or fBUS (MHz)
Figure 16-6. Typical Wait Mode IDD (MC68HRC908JL3E/JK3E/JK1E),
with All Modules Turned Off (25 °C)
16.12 ADC Characteristics
Table 16-10. ADC Characteristics
Characteristic
Supply voltage
Symbol
Min
Max
Unit
Comments
2.7
(VDD min)
5.5
(VDD max)
VDDAD
V
VADIN
BAD
VSS
8
VDD
8
Input voltages
Resolution
V
Bits
LSB
AAD
Absolute accuracy
± 0.5
± 1.5
Includes quantization
t
AIC = 1/fADIC, tested only
fADIC
ADC internal clock
0.5
1.048
VDD
MHz
at 1 MHz
RAD
tADPU
tADC
tADS
ZADI
FADI
CADI
VSS
16
14
5
Conversion range
Power-up time
V
tAIC cycles
tAIC cycles
tAIC cycles
Conversion time
Sample time(1)
Zero input reading(2)
Full-scale reading(3)
Input capacitance
15
—
VIN = VSS
00
FE
—
01
Hex
Hex
pF
VIN = VDD
FF
(20) 8
Not tested
Input leakage(3)
Port B/port D
—
—
± 1
µA
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
145
Electrical Specifications
16.13 Memory Characteristics
Table 16-11. Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
1.3
1
Max
—
Unit
V
V
RDR
FLASH program bus clock frequency
FLASH read bus clock frequency
—
—
MHz
(1)
32k
1
8M
—
Hz
ms
f
ead
R
(2)
FLASH page erase time
t
rase
E
(3)
rase
FLASH mass erase time
t
4
10
5
—
—
—
—
—
40
—
ms
µs
µs
µs
µs
µs
µs
ME
t
FLASH PGM/ERASE to HVEN set up time
FLASH high-voltage hold time
FLASH high-voltage hold time (mass erase)
FLASH program hold time
nvs
nvh
t
t
100
5
nvh1
t
pgs
t
FLASH program time
30
1
PROG
(4)
FLASH return to read time
t
rcv
(5)
FLASH cumulative program hv period
t
—
10k
10k
10
4
ms
HV
FLASH row erase endurance(6)
FLASH row program endurance(7)
FLASH data retention time(8)
—
—
—
—
—
—
cycles
cycles
years
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the
FLASH memory.
3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of
the FLASH memory.
4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump,
by clearing HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG × 32) ≤ tHV max.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least
this many erase / program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least
this many erase / program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum
time specified.
MC68HC908JL3E Family Data Sheet, Rev. 3
146
Freescale Semiconductor
Chapter 17
Mechanical Specifications
17.1 Introduction
This section gives the dimensions for:
•
•
•
•
•
20-pin plastic dual in-line package (case #738)
20-pin small outline integrated circuit package (case #751D)
28-pin plastic dual in-line package (case #710)
28-pin small outline integrated circuit package (case #751F)
48-pin low-profile quad flat pack (case #932)
17.2 20-Pin PDIP
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
–T–
SEATING
PLANE
K
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
N
E
G
J
K
L
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
T B
0.25 (0.010)
M
N
0
0.020
15
0.040
0
0.51
15
1.01
M
M
T A
Figure 17-1. 20-Pin PDIP (Case #738)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
147
Mechanical Specifications
17.3 20-Pin SOIC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
B
0.010 (0.25)
1
10
MILLIMETERS
INCHES
20X D
DIM MIN
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
A
B
C
D
F
12.65
7.40
2.35
0.35
0.50
0.499
0.292
0.093
0.014
0.020
M
S
S
B
0.010 (0.25)
T A
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
Figure 17-2. 20-Pin SOIC (Case #751D)
17.4 28-Pin PDIP
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
28
15
14
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
36.45
13.72
3.94
0.36
1.02
MAX
37.21
14.22
5.08
0.56
1.52
MIN
MAX
1.465
0.560
0.200
0.022
0.060
1
1.435
0.540
0.155
0.014
0.040
L
C
A
N
G
H
J
K
L
2.54 BSC
0.100 BSC
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
J
G
H
F
M
K
15.24 BSC
0.600 BSC
D
SEATING
M
N
0°
0.51
15°
1.02
0°
0.020
15°
0.040
PLANE
Figure 17-3. 28-Pin PDIP (Case #710)
MC68HC908JL3E Family Data Sheet, Rev. 3
148
Freescale Semiconductor
28-Pin SOIC
17.5 28-Pin SOIC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
-A-
ANSI Y14.5M, 1982.
15
28
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
14X P
M
M
0.010 (0.25)
B
-B-
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
1
14
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
28X D
M
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
17.80
7.40
2.35
0.35
0.41
MAX
18.05
7.60
2.65
0.49
0.90
MIN
MAX
0.711
0.299
0.104
0.019
0.035
R
X 45
0.701
0.292
0.093
0.014
0.016
C
-T-
SEATING
PLANE
F
26X G
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0°
0.32
0.29
8°
10.55
0.75
0.009
0.005
0°
0.013
0.011
8°
0.415
0.029
K
F
10.01
0.25
0.395
0.010
J
Figure 17-4. 28-Pin SOIC (Case #751F)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
149
Mechanical Specifications
17.6 48-Pin LQFP
4X
NOTES:
0.200 AB T–U
Z
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE AB IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
DETAIL Y
9
A
P
A1
48
37
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
1
36
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350.
T
U
B
V
AE
AE
B1
V1
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076.
12
25
9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
MILLIMETERS
13
24
DIM
A
MIN
MAX
Z
7.000 BSC
A1
B
B1
C
D
E
3.500 BSC
7.000 BSC
3.500 BSC
S1
T, U, Z
1.400
1.600
0.270
1.450
0.230
S
0.170
1.350
0.170
DETAIL Y
4X
F
G
0.200 AC T–U
Z
0.500 BSC
H
J
K
L
M
N
0.050
0.090
0.500
1°
0.150
0.200
0.700
5°
0.080 AC
12° REF
G
AB
AC
0.090
0.160
P
0.250 BSC
R
0.150
0.250
S
9.000 BSC
S1
V
V1
W
AA
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
AD
M°
BASE METAL
TOP & BOTTOM
R
N
J
E
C
H
F
D
M
0.080
AC T–U Z
SECTION AE–AE
W
L°
K
DETAIL AD
AA
Figure 17-5. 48-Pin LQFP (Case #932)
MC68HC908JL3E Family Data Sheet, Rev. 3
150
Freescale Semiconductor
Chapter 18
Ordering Information
18.1 Introduction
This section contains ordering numbers for the MC68H(R)C908JL3E, MC68H(R)C908JK3E, and
MC68H(R)C908JK1E.
18.2 MC Order Numbers
Table 18-1. MC Order Numbers
MC order number
Oscillator type
FLASH memory
Package
MC68HC908JL3ECFA
MC68HC908JL3EMFA
Crystal oscillator
4096 Bytes
48-pin LQFP
MC68HRC98JL3ECFA
MC68HRC98JL3EMFA
RC oscillator
MC68HC908JL3ECP
MC68HC908JL3EMP
MC68HC908JL3ECDW
MC68HC908JL3EMDW
Crystal oscillator
4096 Bytes
4096 Bytes
1536 Bytes
28-pin package
MC68HRC98JL3ECP
MC68HRC98JL3EMP
MC68HRC98JL3ECDW
MC68HRC98JL3EMDW
RC oscillator
Crystal oscillator
RC oscillator
MC68HC908JK3ECP
MC68HC908JK3EMP
MC68HC908JK3ECDW
MC68HC908JK3EMDW
MC68HRC98JK3ECP
MC68HRC98JK3EMP
MC68HRC98JK3ECDW
MC68HRC98JK3EMDW
20-pin package
MC68HC908JK1ECP
MC68HC908JK1EMP
MC68HC908JK1ECDW
MC68HC908JK1EMDW
Crystal oscillator
RC oscillator
MC68HRC98JK1ECP
MC68HRC98JK1EMP
MC68HRC98JK1ECDW
MC68HRC98JK1EMDW
Temperature: C = –40 °C to +85 °C M = –40 °C to +125 °C (available for VDD = 5V only)
Package:
P = PDIP
DW = SOIC
FA = LQFP
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
151
Ordering Information
MC68HC908JL3E Family Data Sheet, Rev. 3
152
Freescale Semiconductor
Appendix A
MC68HLC908JL3E/JK3E/JK1E
A.1 Introduction
This appendix introduces three devices, that are low-voltage versions of MC68HC908JL3E/JK3E/JK1E:
•
•
•
MC68HLC908JL3E
MC68HLC908JK3E
MC68HLC908JK1E
The entire data book apply to these low-voltage devices, with exceptions outlined in this appendix.
A.2 FLASH Memory
The FLASH memory can be read at minimum VDD of 2.2V.
Program or erase operations require a minimum VDD of 2.7V.
A.3 Low-Voltage Inhibit
There is no low-voltage inhibit circuit. Therefore, no low-voltage reset. The associated register bits are
reserved bits.
A.4 Oscillator Options
Only crystal oscillator or direct clock input is supported.
A.5 Electrical Specifications
Electrical specifications for low-voltage devices are given in the following tables.
A.5.1 Functional Operating Range
Table A-1. Operating Range
Characteristic
Operating temperature range
Operating voltage range
Symbol
Value
Unit
°C
TA
0 to +85
2.2 to 5.5
VDD
VDD
V
Operating voltage for FLASH memory program
and erase operations
2.7 to 5.5
V
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
153
A.5.2 DC Electrical Characteristics
Table A-2. DC Electrical Characteristics
Characteristic(1)
Output high voltage (ILOAD = –1.0mA)
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7
Output low voltage (ILOAD = 0.8mA)
Typ(2)
Symbol
Min
Max
Unit
VOH
VDD–0.4
—
—
V
VOL
VOL
—
—
—
—
0.4
0.5
V
V
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5
Output low voltage (ILOAD = 15mA)
PTD6, PTD7
Input high voltage
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
VIH
VIL
0.7 × VDD
VDD
—
—
V
V
Input low voltage
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
VSS
0.2 × VDD
V
DD supply current (VDD = 2.4V, fOP = 2MHz)
Run(3)
—
—
—
2
1
1
3.5
1.5
3
mA
mA
µA
IDD
Wait(4)
Stop(5) 0°C to 85°C
IIL
Digital I/O ports Hi-Z leakage current
Input current
—
—
—
—
± 10
± 1
µA
µA
IIN
COUT
CIN
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
POR rearm voltage(6)
VPOR
RPOR
0
—
—
100
—
mV
POR rise time ramp rate(7)
0.02
V/ms
Pullup resistors(8)
PTD6, PTD7
RST, IRQ1, PTA0–PTA6
RPU1
RPU2
1.8
16
3.3
26
4.8
36
kΩ
kΩ
1. VDD = 2.4 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run
IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 100 pF
on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD
5. STOP IDD measured with OSC1 grounded, no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until min-
imum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V
MC68HC908JL3E Family Data Sheet, Rev. 3
154
Freescale Semiconductor
A.5.3 Control Timing
Table A-3. Control Timing
Characteristic(1)
Symbol
fOP
tIRL
Min
—
Max
2
Unit
MHz
µs
Internal operating frequency(2)
RST input pulse width low(3)
1.5
—
1. VDD = 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
mation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
A.5.4 Oscillator Characteristics
Table A-4. Oscillator Component Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
fOSCXCLK
Crystal frequency, XTALCLK
—
—
8
MHz
External clock
reference frequency(1)
fOSCXCLK
dc
—
8
MHz
Crystal load capacitance(2)
Crystal fixed capacitance(2)
CL
C1
C2
RB
RS
—
—
—
—
—
—
—
—
—
—
—
2 × CL
2 × CL
10 MΩ
—
Crystal tuning capacitance(2)
Feedback bias resistor
Series resistor(2), (3)
1. No more than 10% duty cycle deviation from 50%
2. Consult crystal vendor data sheet
3. Not Required for high frequency crystals
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
155
A.5.5 ADC Characteristics
Table A-5. ADC Characteristics
Characteristic
Symbol
Min
Max
Unit
Comments
2.2
(VDD min)
5.5
(VDD max)
VDDAD
Supply voltage
V
VADIN
BAD
VSS
8
VDD
8
Input voltages
Resolution
V
Bits
LSB
AAD
Absolute accuracy
± 0.5
± 2
Includes quantization
tAIC = 1/fADIC, tested only
at 1 MHz
fADIC
ADC internal clock
0.5
1.048
MHz
RAD
tADPU
tADC
tADS
ZADI
FADI
CADI
VSS
14
14
5
VDD
—
Conversion range
Power-up time
V
tAIC cycles
t
AIC cycles
AIC cycles
Hex
Conversion time
Sample time(1)
Zero input reading(2)
Full-scale reading(3)
Input capacitance
15
t
—
VIN = VSS
VIN = VDD
Not tested
00
FE
—
01
FF
Hex
(20) 8
pF
Input leakage(3)
Port B/port D
—
—
± 1
µA
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908JL3E Family Data Sheet, Rev. 3
156
Freescale Semiconductor
A.5.6 Memory Characteristics
The FLASH memory can only be read at an operating voltage of 2.2 to 5.5V. Program and erase are
achieved at an operating voltage of 2.7 to 5.5V. The program and erase parameters in Table A-6 are for
VDD = 2.7 to 5.5V only.
Table A-6. Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
1.3
1
Max
—
Unit
V
V
RDR
FLASH program bus clock frequency
FLASH read bus clock frequency
—
—
MHz
(1)
32k
1
8M
—
Hz
ms
f
ead
R
(2)
FLASH page erase time
t
rase
E
(3)
rase
FLASH mass erase time
t
ME
4
10
5
—
—
—
—
—
40
—
ms
µs
µs
µs
µs
µs
µs
t
FLASH PGM/ERASE to HVEN set up time
FLASH high-voltage hold time
FLASH high-voltage hold time (mass erase)
FLASH program hold time
nvs
nvh
t
t
100
5
nvhl
t
pgs
t
FLASH program time
30
1
PROG
(4)
FLASH return to read time
t
rcv
(5)
FLASH cumulative program hv period
—
4
ms
t
HV
FLASH row erase endurance(6)
FLASH row program endurance(7)
FLASH data retention time(8)
—
10k
10k
10
—
—
—
cycles
cycles
years
—
—
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the
FLASH memory.
3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of
the FLASH memory.
4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump,
by clearing HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
t
HV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG × 32) ≤ tHV max.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least
this many erase / program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least
this many erase / program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum
time specified.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
157
A.6 MC Order Numbers
Table A-7 shows the ordering numbers for the low-voltage devices.
Table A-7. MC68HLC908JL3E/JK3E/JK1E Order Numbers
MC order number
Oscillator type
FLASH memory
Package
MC68HLC98JL3EIFA
Crystal oscillator
4096 Bytes
48-pin LQFP
MC68HLC98JL3EIP
MC68HLC98JL3EIDW
Crystal oscillator
Crystal oscillator
Crystal oscillator
4096 Bytes
4096 Bytes
1536 Bytes
28-pin package
20-pin package
MC68HLC98JK3EIP
MC68HLC98JK3EIDW
MC68HLC98JK1EIP
MC68HLC98JK1EIDW
Notes:
I = 0 °C to +85 °C
P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit package (SOIC)
FA = Low-Profile Quad Flat Pack (LQFP)
MC68HC908JL3E Family Data Sheet, Rev. 3
158
Freescale Semiconductor
Appendix B
MC68H(R)C08JL3E/JK3E
B.1 Introduction
This appendix introduces four devices, that are ROM versions of MC68H(R)C908JL3E/JK3E:
•
•
•
•
MC68HC08JL3E
MC68HC08JK3E
MC68HRC08JL3E
MC68HRC08JK3E
The entire data book apply to these ROM devices, with exceptions outlined in this appendix.
Table B-1. Summary of Device Differences
MC68H(R)C08JL3E/JK3E
4,096 bytes ROM
MC68H(R)C908JL3E/JK3E
4,096 bytes FLASH
Memory ($EC00–$FBFF)
User vectors ($FFD0–$FFFF)
48 bytes ROM
48 bytes FLASH
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Not used;
locations are reserved.
Registers at $FE08 and $FE09
$FC00–$FDFF: Not used.
$FE10–$FFCF: Used for testing
purposes only.
Monitor ROM
($FC00–$FDFF and $FE10–$FFCF)
Used for testing and FLASH
programming/erasing.
B.2 MCU Block Diagram
Figure B-1 shows the block diagram of the MC68H(R)C08JL3E/JK3E.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
159
INTERNAL BUS
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
PTA6/KBI6**¥
PTA5/KBI5**‡
PTA4/KBI4**‡
PTA3/KBI3**‡
PTA2/KBI2**‡
PTA1/KBI1**‡
PTA0/KBI0**‡
CONTROL AND STATUS REGISTERS — 64 BYTES
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
#
USER ROM:
MC68H(R)C08JK3E/JL3E — 4,096 BYTES
USER RAM — 128 BYTES
MONITOR ROM — 960 BYTES
2-CHANNEL TIMER INTERFACE
MODULE
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
PTB1/ADC1
PTB0/ADC0
BREAK
MODULE
USER ROM VECTOR SPACE — 48 BYTES
MC68HC908JL3E/JK3E
OSC1
X-TAL OSCILLATOR
¥ OSC2
COMPUTER OPERATING
PROPERLY MODULE
PTD7**†‡
PTD6**†‡
MC68HRC908JL3E/JK3E
RC OSCILLATOR
PTD5/TCH1
PTD4/TCH0
PTD3/ADC8‡
PTD2/ADC9‡
PTD1/ADC10
PTD0/ADC11
POWER-ON RESET
MODULE
SYSTEM INTEGRATION
MODULE
* RST
#
LOW-VOLTAGE INHIBIT
MODULE
EXTERNAL INTERRUPT
MODULE
* IRQ1
* Pin contains integrated pull-up device.
** Pin contains programmable pull-up device.
† 25mA open-drain if output pin.
VDD
POWER
‡ LED direct sink pin.
VSS
# Pins available on MC68H(R)C08JL3E only.
¥ Shared pin: MC68HC08JL3E/JK3E — OSC2
ADC REFERENCE
MC68HRC08JL3E/JK3E — RCCLK/PTA6/KBI6
Figure B-1. MC68H(R)C08JL3E/JK3E Block Diagram
B.3 Memory Map
The MC68H(R)C08JL3E/JK3E has 4,096 bytes of user ROM from $EC00 to $FBFF, and 48 bytes of user
ROM vectors from $FFD0 to $FFFF. On the MC68H(R)C908JL3E/JK3E, these memory locations are
FLASH memory.
Figure B-2 shows the memory map of the MC68H(R)C08JL3E/JK3E.
B.4 Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the MC68H(R)C08JL3E/JK3E.
MC68HC908JL3E Family Data Sheet, Rev. 3
160
Freescale Semiconductor
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$007F
RESERVED
64 BYTES
$0080
↓
$00FF
RAM
128 BYTES
$0100
↓
$EBFF
UNIMPLEMENTED
60,160 BYTES
$EC00
↓
$FBFF
ROM
MC68H(R)C08JL3E/JK3E
4,096 BYTES
$FC00
↓
$FDFF
MONITOR ROM
512 BYTES
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
BREAK STATUS REGISTER (BSR)
RESET STATUS REGISTER (RSR)
RESERVED (UBAR)
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
INTERRUPT STATUS REGISTER 3 (INT3)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOW REGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
RESERVED
$FE10
↓
$FFCF
MONITOR ROM
448 BYTES
$FFD0
↓
$FFFF
USER ROM VECTORS
48 BYTES
Figure B-2. MC68H(R)C08JL3E/JK3E Memory Map
On the MC68H(R)C908JL3E/JK3E, these two locations are the FLASH control register and the FLASH
block protect register respectively.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
161
B.5 Monitor ROM
The monitor program (monitor ROM: $FE10–$FFCF) on the MC68H(R)C08JL3E/JK3E is for device
testing only. $FC00–$FDFF are unused.
B.6 Electrical Specifications
Electrical specifications for the MC68H(R)C908JL3E/JK3E apply to the MC68H(R)C08JL3E/JK3E,
except for the parameters indicated below.
B.6.1 DC Electrical Characteristics
Table B-2. DC Electrical Characteristics (5V)
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
VDD supply current, fOP = 4MHz
Run(3)
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
Wait(4)
—
—
9
4.3
11
5
mA
mA
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
Stop(5)
—
—
5.5
0.8
6.5
1.5
mA
mA
IDD
(–40°C to 85°C)
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
(–40°C to 125°C)
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
—
—
1.8
1.8
5
5
µA
µA
—
—
5
5
10
10
µA
µA
Pullup resistors(6)
PTD6, PTD7
RST, IRQ1, PTA0–PTA6
RPU1
RPU2
1.8
16
4.3
31
4.8
36
kΩ
kΩ
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD
.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. RPU1 and RPU2 are measured at VDD = 5.0V.
MC68HC908JL3E Family Data Sheet, Rev. 3
162
Freescale Semiconductor
Table B-3. DC Electrical Characteristics (3V)
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
V
DD supply current, fOP = 2MHz
Run(3)
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
Wait(4)
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
Stop(5)
—
—
2.8
1.4
3.5
2
mA
mA
IDD
—
—
1.5
0.19
2
0.3
mA
mA
(–40°C to 85°C)
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
—
—
1.4
1.4
5
5
µA
µA
Pullup resistors(6)
PTD6, PTD7
RST, IRQ1, PTA0–PTA6
RPU1
RPU2
1.8
16
4.3
31
4.8
36
kΩ
kΩ
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD
.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. RPU1 and RPU2 are measured at VDD = 5.0V.
B.6.2 5V Oscillator Characteristics
Table B-4. Oscillator Component Specifications (5V)
Characteristic
RC oscillator external R
RC oscillator external C
Symbol
Min
See Figure B-3 and Figure B-4
10
Typ
Max
Unit
REXT
CEXT
—
—
pF
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
163
14
12
10
8
C
= 10 pF
EXT
MCU
5V @ 25°C
OSC1
6
V
DD
4
R
C
EXT
EXT
2
0
0
10
20
30
(k
40
50
Resistor, R
Ω)
EXT
Figure B-3. RC vs. Frequency (5V @25°C)
14
12
10
8
C
= 10 pF
EXT
MCU
3V @ 25°C
OSC1
6
V
DD
4
R
C
EXT
EXT
2
0
0
10
20
30
(k
40
50
Resistor, R
Ω)
EXT
Figure B-4. RC vs. Frequency (3V @25°C)
B.6.3 Memory Characteristics
Table B-5. Memory Characteristics
Characteristic
RAM data retention voltage
NOTES:
Symbol
Min
Max
Unit
V
1.3
—
V
RDR
Since MC68H(R)C08JL3E/JK3E is a ROM device, FLASH memory electrical characteristics do not apply.
MC68HC908JL3E Family Data Sheet, Rev. 3
164
Freescale Semiconductor
B.7 MC Order Numbers
These part numbers are generic numbers only. To place an order, ROM code must be submitted to the
ROM Processing Center (RPC).
Table B-6. MC Order Numbers
MC order number
MC68HC08JL3ECP
Oscillator Type
Package
MC68HC08JL3EMP
MC68HC08JL3ECDW
MC68HC08JL3EMDW
Crystal
28-pin package
MC68HRC08JL3ECP
MC68HRC08JL3EMP
MC68HRC08JL3ECDW
MC68HRC08JL3EMDW
RC
Crystal
RC
MC68HC08JK3ECP
MC68HC08JK3EMP
MC68HC08JK3ECDW
MC68HC08JK3EMDW
20-pin package
MC68HRC08JK3ECP
MC68HRC08JK3EMP
MC68HRC08JK3ECDW
MC68HRC08JK3EMDW
NOTES:
C = –40 °C to +85 °C
M = –40 °C to +125 °C (available for VDD = 5V only)
P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit package (SOIC)
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
165
MC68HC908JL3E Family Data Sheet, Rev. 3
166
Freescale Semiconductor
Appendix C
MC68HC908KL3E/KK3E
C.1 Introduction
This appendix introduces two devices, that are ADC-less versions of MC68HC908JL3E/JK3E:
•
•
MC68HC908KL3E
MC68HC908KK3E
The entire data book applies to these devices, with exceptions outlined in this appendix.
Table C-1. Summary of MC68HC908KL3E/KK3E and MC68HC908JL3E Differences
MC68HC908KL3E/KK3E
MC68HC908JL3E
12-channel, 8-bit.
Analog-to-Digital Converter (ADC)
—
Registers at:
$003C, $003E, and $003E
Not used;
locations are reserved.
ADC registers.
Interrupt Vector at:
$FFDE and $FFDF
Not used.
ADC interrupt vector.
20-pin PDIP (MC68HC908KK3E)
20-pin SOIC (MC68HC908KK3E)
28-pin PDIP
28-pin SOIC
—
20-pin PDIP (MC68HC908JK3E)
20-pin SOIC (MC68HC908JK3E)
28-pin PDIP
28-pin SOIC
48-pin LQFP
Available Packages
C.2 MCU Block Diagram
Figure C-1 shows the block diagram of the MC68HC908KL3E/KK3E.
C.3 Pin Assignments
Figure C-2 and Figure C-3 show the pin assignments for the MC68HC908KL3E/KK3E.
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
167
INTERNAL BUS
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
PTA5/KBI5**‡
PTA4/KBI4**‡
PTA3/KBI3**‡
PTA2/KBI2**‡
PTA1/KBI1**‡
PTA0/KBI0**‡
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH — 4,096 BYTES
#
USER RAM — 128 BYTES
MONITOR ROM — 960 BYTES
2-CHANNEL TIMER INTERFACE
MODULE
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
BREAK
MODULE
USER FLASH VECTOR SPACE — 48 BYTES
OSC1
X-TAL OSCILLATOR
OSC2
COMPUTER OPERATING
PROPERLY MODULE
PTD7**†‡
PTD6**†‡
PTD5/TCH1
PTD4/TCH0
PTD3‡
POWER-ON RESET
MODULE
PTD2‡
SYSTEM INTEGRATION
MODULE
PTD1
* RST
#
PTD0
LOW-VOLTAGE INHIBIT
MODULE
EXTERNAL INTERRUPT
MODULE
* IRQ1
* Pin contains integrated pull-up device.
** Pin contains programmable pull-up device.
† 25mA open-drain if output pin.
VDD
POWER
‡ LED direct sink pin.
VSS
# Pins available on MC68HC908KL3E only.
Figure C-1. MC68HC908KL3E/KK3E Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 3
168
Freescale Semiconductor
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IRQ1
PTA0/KBI0
VSS
1
RST
2
PTA5/KBI5
PTD4/TCH0
PTD5/TCH1
PTD2
3
OSC1
4
OSC2
5
PTA1/KBI1
VDD
PTA4
6
PTD3
7
PTA2/KBI2
PTA3/KBI3
PTB7
PTB0
8
PTB1
9
PTD1
10
11
12
13
14
PTB6
PTB2
PTB5
PTB3
PTD7
PTD0
PTD6
PTB4
MC68HC908KL3E
Figure C-2. 28-Pin PDIP/SOIC Pin Assignment
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
IRQ1
VSS
RST
PTD4/TCH0
PTD5/TCH1
PTD2
OSC1
OSC2
VDD
Pins not available on 20-pin packages
PTA0/KBI0
PTA1/KBI1
PTA2/KBI2
PTA3/KBI3
PTA4/KBI4
PTA5/KBI5
PTD0
PTD1
PTD3
PTB7
PTB6
PTB5
PTD7
PTD6
PTB0
PTB1
PTB2
PTB3
PTB4
Internal pads are unconnected.
MC68HC908KK3E
Figure C-3. 20-Pin PDIP/SOIC Pin Assignment
MC68HC908JL3E Family Data Sheet, Rev. 3
Freescale Semiconductor
169
C.4 Reserved Registers
The following registers are reserved location on the MC68HC908KL3E/KK3E.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R
R
R
R
R
R
R
R
$003C
Reserved Write:
Reset:
Read:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
$003D
$003E
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Figure C-4. Reserved Registers
C.5 Reserved Vectors
The following vectors are reserved interrupt vectors on the MC68HC908KL3E/KK3E.
Table C-2. Reserved Vectors
Vector Priority
INT Flag
Address
$FFDE
$FFDF
Vector
Reserved
Reserved
—
IF15
C.6 Order Numbers
Table C-3. MC68HC908KL3E/KK3E Order Numbers
Operating
VDD
Operating
Temperature
MC order number
Package
OSC
FLASH Memory
MC68HC908KL3ECP
MC68HC908KL3ECDW
MC68HC908KK3ECP
MC68HC908KK3ECDW
28-pin PDIP
28-pin SOIC
20-pin PDIP
20-pin SOIC
–40 to +85 °C
3V, 5V
XTAL
4096 Bytes
MC68HC908JL3E Family Data Sheet, Rev. 3
170
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MC68HC908JL3E
Rev. 3, 11/2004
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