MC68HSC05C9ACFB [NXP]
8-BIT, MROM, 4.1MHz, MICROCONTROLLER, PQFP44, QFP-44;
| 型号： | MC68HSC05C9ACFB |
| 厂家： | 
NXP |
| 描述： | 8-BIT, MROM, 4.1MHz, MICROCONTROLLER, PQFP44, QFP-44 |
| 文件： | 总160页 (文件大小：3958K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
HC05C9AGRS/D
REV. 4.0
MC68HC05C9A
MC68HCL05C9A
MC68HSC05C9A
Ge ne ra l Re le a se Sp e c ific a tion
Fe b rua ry 19, 1997
CSIC MCU De sig n Ce nte r
Austin, Te xa s
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion
© 1997
MC68HC05C9A — Rev. 4.0
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
List of Se c tions
Se c tion 1. Ge ne ra l De sc rip tion . . . . . . . . . . . . . . . . . . . 17
Se c tion 2. Me m ory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Se c tion 3. Ce ntra l Proc e ssing Unit . . . . . . . . . . . . . . . . 33
Se c tion 4. Inte rrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Se c tion 5. Re se ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Se c tion 6. Low-Powe r Mod e s . . . . . . . . . . . . . . . . . . . . 51
Se c tion 7. Inp ut/ Outp ut Ports . . . . . . . . . . . . . . . . . . . . . 53
Se c tion 8. Ca p ture / Com p a re Tim e r . . . . . . . . . . . . . . . 57
Se c tion 9. Se ria l Com m unic a tions Inte rfa c e (SCI) . . . 69
Se c tion 10. Se ria l Pe rip he ra l Inte rfa c e . . . . . . . . . . . . . 89
Se c tion 11. Instruc tion Se t . . . . . . . . . . . . . . . . . . . . . . 101
Se c tion 12. Ele c tric a l Sp e c ific a tions . . . . . . . . . . . . . . 119
Se c tion 13. Me c ha nic a l Sp e c ific a tions . . . . . . . . . . . 135
Se c tion 14. Ord e ring Inform a tion . . . . . . . . . . . . . . . . 139
MC68HC05C9A — Rev. 4.0
General Release Specification
List of Sections
For More Information On This Product,
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Freescale Semiconductor, Inc.
List of Se c tions
Ap p e nd ix A. MC68HCL05C9A . . . . . . . . . . . . . . . . . . . 141
Ap p e nd ix B. MC68HSC05C9A . . . . . . . . . . . . . . . . . . . 145
Ap p e nd ix C. Se lf-Che c k Mod e . . . . . . . . . . . . . . . . . . 153
Ap p e nd ix D. M68HC05Cx Fa m ily
Fe a ture Com p a risons . . . . . . . . . . . . . . . . . . . . . . . 157
General Release Specification
MC68HC05C9A — Rev. 4.0
List of Sections
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Ta b le of Conte nts
Se c tion 1. Ge ne ra l De sc rip tion
1.1
1.2
1.3
1.4
1.5
1.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Software-Programmable Options . . . . . . . . . . . . . . . . . . . . . . .20
Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DD SS
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
OSC1 andOSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PC0–PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PD0–PD5 and PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Se c tion 2. Me m ory
2.1
2.2
2.3
2.4
2.5
2.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Se c tion 3. Ce ntra l Proc e ssing Unit
3.1
3.2
3.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
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Ta b le of Conte nts
3.3.1
Accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . .36
3.3.2
3.3.3
3.3.4
3.3.5
Se c tion 4. Inte rrup ts
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Non-Maskable Software Interrupt (SWI). . . . . . . . . . . . . . . . . .39
External Interrupt (IRQ or Port B) . . . . . . . . . . . . . . . . . . . . . . .39
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Se c tion 5. Re se ts
5.1
5.2
5.3
5.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .46
COP Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.5
5.5.1
5.5.2
5.6
5.7
5.8
Se c tion 6. Low-Powe r Mod e s
6.1
6.2
6.3
6.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Se c tion 7. Inp ut/ Outp ut Ports
7.1
7.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
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7.3
7.4
7.5
7.6
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Se c tion 8. Ca p ture / Com p a re Tim e r
8.1
8.2
8.3
Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .60
Timer Status Register (TSR). . . . . . . . . . . . . . . . . . . . . . . .62
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .63
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .64
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . .65
Output Compare Registers (OCRH and OCRL) . . . . . . . . .66
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.3.1
8.3.2
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
8.6
Se c tion 9. Se ria l Com m unic a tions Inte rfa c e (SCI)
Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
SCI Receiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SCI Transmitter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Receiver Wakeup Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .75
Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10 Address Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.11 Receive Data In (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.12 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.13 Transmit Data Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
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9.14 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.14.1
9.14.2
9.14.3
9.14.4
9.14.5
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . .80
SCI Control Register 1 (SCCR1). . . . . . . . . . . . . . . . . . . . .80
SCI Control Register 2 (SCCR2). . . . . . . . . . . . . . . . . . . . .82
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . .84
Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . . . . .86
Se c tion 10. Se ria l Pe rip he ra l Inte rfa c e
10.1 Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
10.4.1
10.4.2
10.4.3
10.4.4
Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . .91
Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . .91
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.6.1
10.6.2
10.6.3
Serial Peripheral Control Register (SPCR) . . . . . . . . . . . . .95
Serial Peripheral Status Register (SPSR). . . . . . . . . . . . . .97
Serial Peripheral Data I/O Register (SPDR) . . . . . . . . . . . .99
Se c tion 11. Instruc tion Se t
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.4.1
11.4.2
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .106
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . .107
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11.4.3
11.4.4
11.4.5
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .108
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .110
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Se c tion 12. Ele c tric a l Sp e c ific a tions
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.2 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
12.3 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
12.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
12.5 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .124
12.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.8 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . .131
Se c tion 13. Me c ha nic a l Sp e c ific a tions
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
13.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03). . .136
13.4 42-Pin Plastic Shrink Dual In-Line (SDIP)
Package (Case 858-01). . . . . . . . . . . . . . . . . . . . . . . . . . .136
13.5 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02).137
13.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . .138
Se c tion 14. Ord e ring Inform a tion
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
14.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Ap p e nd ix A. MC68HCL05C9A
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
A.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .141
MC68HC05C9A — Rev. 4.0
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Ta b le of Conte nts
Ap p e nd ix B. MC68HSC05C9A
B. 1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
B. 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
B.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .146
B. 4 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Ap p e nd ix C. Se lf-Che c k Mod e
C.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
C.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
C.3 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
C.3.1
C.3.2
Self-Check Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Self-Check Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Ap p e nd ix D. M68HC05Cx Fa m ily
Fe a ture Com p a risons
D.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
D.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
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List of Fig ure s
Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
1-6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
40-Pin PDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .21
42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .22
44-Lead PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . .23
44-Pin QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . .24
2-1
2-2
2-3
2-4
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3-1
3-2
Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4-1
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5-1
5-2
5-3
5-4
5-5
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power-On Reset and RESET. . . . . . . . . . . . . . . . . . . . . . . .45
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
COP Reset Register (COPRST) . . . . . . . . . . . . . . . . . . . . .47
COP Control Register (COPCR) . . . . . . . . . . . . . . . . . . . . .48
6-1
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .52
7-1
7-2
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
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List of Fig ure s
Figure
Title
Page
8-1
8-2
8-3
8-4
8-5
8-6
8-7
Capture/Compare Timer Block Diagram . . . . . . . . . . . . . . .58
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .60
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .62
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .63
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .64
Input Capture Registers (ICRH and ICRL). . . . . . . . . . . . . .65
Output Compare Registers (OCRH and OCRL). . . . . . . . . .66
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
Serial Communications Interface Block Diagram. . . . . . . . .71
Rate Generator Division. . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SCI Examples of Start Bit Sampling Techniques . . . . . . . . .77
SCI Sampling Technique Used on All Bits . . . . . . . . . . . . . .77
SCI Artificial Start Following a Frame Error . . . . . . . . . . . . .79
SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . .79
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . .80
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . .81
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . .82
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . .84
Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . .86
10-1
10-2
10-3
10-4
10-5
10-6
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . .91
Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . .93
Serial Peripheral Interface Master-Slave Interconnection . .94
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . .95
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
PI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .99
12-1
12-2
Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Maximum Supply Current vs Internal
Clock Frequency, VDD = 5.5 V . . . . . . . . . . . . . . . . . . . .126
Maximum Supply Current vs Internal
12-3
Clock Frequency, VDD = 3.6 V . . . . . . . . . . . . . . . . . . . .126
TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . .128
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .129
STOP Recovery Timing Diagram. . . . . . . . . . . . . . . . . . . .129
12-4
12-5
12-6
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Figure
Title
Page
12-7
12-8
12-9
12-10
Power-On Reset Timing Diagram . . . . . . . . . . . . . . . . . . .130
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .133
SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . .134
13-1
13-2
13-3
13-4
40-Pin Plastic DIP Package (Case 711-03) . . . . . . . . . . . .136
42-Pin Plastic SDIP Package (Case 858-01). . . . . . . . . . .136
44-Lead PLCC (Case 777-02) . . . . . . . . . . . . . . . . . . . . . .137
44-Lead QFP (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . .138
C-1
Self-Check Circuit Schematic . . . . . . . . . . . . . . . . . . . . . .155
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
List of Ta b le s
Table
Title
Page
4-1
Vector Addresses for Interrupts and Resets . . . . . . . . . . . .38
COP Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5-1
9-1
9-2
Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . .86
Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10-1
SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .97
11-1
11-2
11-3
11-4
11-5
11-6
11-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .106
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .107
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . .109
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .110
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . .112
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
12-1
12-2
12-3
12-4
12-5
12-6
DC Electrical Characteristics (V = 5.0 Vdc) . . . . . . . . . .124
DD
DC Electrical Characteristics (V = 3.3 Vdc) . . . . . . . . . .125
DD
Control Timing (V = 5.0 V ±10%) . . . . . . . . . . . . . . . . . .127
DD
Control Timing (V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . .128
DD
Serial Peripheral Interface Timing (V = 5.0 Vdc) . . . . . .131
DD
Serial Peripheral Interface Timing (V = 3.3 Vdc) . . . . . .132
DD
14-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Low-Power Operating Temperature Range . . . . . . . . . . .141
A-1
A-2
A-3
A-2
Low-Power Output Voltage (V = 1.8-2.4 Vdc) . . . . . . . .142
DD
Input Pullup Current (V = 1.8–2.4 Vdc) . . . . . . . . . . . . .142
DD
Low-Power Output Voltage (V = 2.5-3.6 Vdc) . . . . . . . .142
DD
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Title
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A-5
A-6
Input Pullup Current (V = 2.5–3.6 Vdc) . . . . . . . . . . . . .142
Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . .143
DD
B-1
B-2
B-3
B-4
B-5
B-6
B-7
High-Speed Operating Temperature Range . . . . . . . . . . .146
High-Speed Supply Current . . . . . . . . . . . . . . . . . . . . . . .147
Input Pullup Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
High-Speed Control Timing (V = 4.5–5.5 Vdc) . . . . . . .148
DD
High-Speed Control Timing (V = 2.4–3.6 Vdc) . . . . . . .149
DD
High-Speed Control Timing (V = 4.5–5.5 Vdc) . . . . . . .150
DD
High-Speed SPI Timing (V = 2.4–3.6 Vdc) . . . . . . . . . .151
DD
C-1
D-1
Self-Check Circuit LED Codes . . . . . . . . . . . . . . . . . . . . .156
M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . . .158
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 1. Ge ne ra l De sc rip tion
1.1 Conte nts
1.2
1.3
1.4
1.5
Introduction...............................................................................17
Features....................................................................................18
Mask Options............................................................................18
Software-Programmable Options .............................................20
Functional Pin Descriptions ......................................................21
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10
V
and V ........................................................................24
DD SS
IRQ......................................................................................24
OSC1 andOSC2..................................................................25
RESET ................................................................................25
TCAP...................................................................................25
TCMP ..................................................................................25
PA0–PA7.............................................................................25
PB0–PB7.............................................................................25
PC0–PC7 ............................................................................26
PD0–PD5 and PD7 .............................................................26
1.2 Introd uc tion
The MC68HC05C9A HCMOS microcomputer is a member of the
M68HC05 Family. The MC68HC05C9A memory map consists of 15,936
bytes of user ROM and 352 bytes of RAM. The MC68HC05C9A includes
a serial communications interface, a serial peripheral interface, and a
16-bit capture/compare timer.
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1.3 Fe a ture s
• HC05 CPU
• Mask Programmable Interrupt Capability on Port B
• Software Programmable External Interrupt Sensitivity
• 15,936 Bytes of ROM
• 352 Bytes of RAM
• Memory Mapped Input/Output (I/O)
• 31 Bidirectional I/O Lines with High Current Sink and Source
on PC7
• Asynchronous Serial Communications Interface (SCI)
• Synchronous Serial Peripheral Interface (SPI)
• 16-Bit Capture/Compare Timer
• Computer Operating Properly (COP) Watchdog Timer and Clock
Monitor
• Power-Saving Wait and Stop Modes
• On-Chip Crystal Oscillator Connections
• Single 3.0 Volts to 5.5 Volts Power Supply Requirement
• ROM Contents Security Feature
• 40-Pin Dual In-Line (DIP), 44-Pin Plastic Leaded Chip Carrier
(PLCC), 44-Pin Quad Flat Pack (QFP), and 42-Pin Plastic Shrink
Dual In-Line (SDIP) Packages
1.4 Ma sk Op tions
Eight mask options are available to select external interrupt capability
(including an internal pullup device) on each of the port B pins.
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General Description
Mask Options
SELF-CHECK ROM — 239 BYTES
USER ROM — 15,936 BYTES
USER RAM —352 BYTES
ARITHMETIC/LOGIC
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
A
CPU CONTROL
UNIT
P
ACCUMULATOR
IRQ
M68HC05
MCU
INDEX REGISTER
RESET
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
STACK POINTER
0
0 0 0 0 0 1 1
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1 1 H I N C Z
CPU CLOCK
OSC1
OSC2
DIVIDE
INTERNAL
BY TWO
OSCILLATOR
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
INTERNAL CLOCK
COP
WATCHDOG
DIVIDE
BY FOUR
TIMER CLOCK
BAUD RATE
PD7
GENERATOR
CAPTURE/
SPI
SCI
TCAP
TCMP
PD5/SS
SS
COMPARE
TIMER
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
SCK
MOSI
MISO
TDO
RDI
V
DD
POWER
V
SS
Figure 1-1. Block Diagram
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Ge ne ra l De sc rip tion
1.5 Softwa re -Prog ra m m a b le Op tions
The option register (OR), shown in Figure 1-2, contains the
programmable bits for the following options:
• Map two different areas of memory between RAM and ROM, one
of 48 bytes and one of 128 bytes
• Edge-triggered only or edge- and level-triggered external interrupt
(IRQ pin and any port B pin configured for interrupt)
This register must be written to by user software during operation of the
microcontroller.
$3FDF
Read:
Write:
Reset:
Bit 7
RAM0
0
6
RAM1
0
5
0
4
0
3
0
2
0
1
IRQ
1
Bit 0
0
0
0
0
0
0
= Unimplemented
Figure 1-2. Option Register
RAM0 — Random Access Memory Control Bit 0
This read/write bit selects between RAM or ROM in location $0020 to
$004F. This bit can be read or written at any time.
1 = RAM selected
0 = ROM selected
RAM1— Random Access Memory Control Bit 1
This read/write bit selects between RAM or ROM in location $0100 to
$017F. This bit can be read or written at any time.
1 = RAM selected
0 = EPROM selected
IRQ — Interrupt Request
This bit selects between an edge-triggered only or edge- and level-
triggered external interrupt. This bit is set by reset, but can be cleared
by software. This bit can be written only once.
1 = Edge and level interrupt option selected
0 = Edge-only interrupt option selected
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General Description
Functional Pin Descriptions
1.6 Func tiona l Pin De sc rip tions
Figure 1-3, Figure 1-4, Figure 1-5, and Figure 1-6 show the pin
assignments for the available packages. A functional description of the
pins follows.
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
RESET
IRQ
N/C
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
V
DD
2
OSC1
OSC2
TCAP
PD7
3
4
5
6
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PC1
PC2
PC3
PC4
PC5
PC6
V
PC7
SS
Figure 1-3. 40-Pin PDIP Pin Assignments
NOTE: If MC68HC705C9A devices are to be used in the same socket, pin 3
should be tied to V .
DD
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Ge ne ra l De sc rip tion
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RESET
IRQ
N/C
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
N/C
PB4
PB5
PB6
PB7
1
V
DD
2
OSC1
OSC2
TCAP
PD7
3
4
5
6
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PC1
PC2
N/C
PC3
PC4
PC5
PC6
V
PC7
SS
Figure 1-4. 42-Pin SDIP Pin Assignments
NOTE: If MC68HC705C9A devices are to be used in the same socket, pin 3
should be tied to V .
DD
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General Description
Functional Pin Descriptions
T
6
7
D
A
A
/
N
R
R
V
O
O
T
P
6
5
4
3
2
4
3
2
1
0
1
7
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
N/C
N/C
39
38
37
36
35
34
33
32
31
30
29
8
TCMP
9
PD5/SS
PD4/SCK
PD3/MOSI
PD2MISO
PD1/TDO
PD0/RDI
PC0
10
11
12
13
14
15
16
17
PC1
PC2
Figure 1-5. 44-Lead PLCC Pin Assignments
NOTE: The 44-pin PLCC pin assignment diagram is for compatibility with the
MC68HC705C9A. However, if MC68HC705C9A devices are to be used
in the same socket, pin 3 should be tied to VDD.
For compatibility with 68HC05C4A/C8A/C12A devices in 44-pin PLCC,
tie pins 17 and 18 together, and tie pins 39 and 40 together.
For compatibility with 68HC705C8A 44-pin PLCC device, three sets of
pins should be tied together: pins 17 and 18, pins 39 and 40, and pins 3,
4, and 44.
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Ge ne ra l De sc rip tion
7
D
A
/
R
R
/
/
V
O
O
T
P
4
3
2
1
0
9
8
7
6
5
4
1
TCMP
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
33
32
31
30
29
28
27
26
25
24
23
2
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
3
4
5
6
7
8
9
PC1
10
11
PC2
PC3
Figure 1-6. 44-Pin QFP Pin Assignments
NOTE: If MC68HC705C9A devices are to be used in the same socket, pin 43
should be tied to V .
DD
1.6.1 V a nd V
DD
SS
Power is supplied to the MCU using these two pins. V is the positive
DD
supply and V is ground.
SS
1.6.2 IRQ
This interrupt pin has an option that provides two different choices of
interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt
trigger as part of its input to improve noise immunity. Refer to Section 4.
Interrupts for more detail.
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General Description
Functional Pin Descriptions
1.6.3 OSC1 a nd OSC2
These pins provide control input for an on-chip clock oscillator circuit. A
crystal or ceramic resonator connected to these pins provides a system
clock. The internal frequency is one-half the crystal frequency.
1.6.4 RESET
As an input pin, this active low RESET pin is used to reset the MCU to a
known startup state by pulling RESET low. As an output pin, the RESET
pin indicates that an internal MCU reset has occurred. The RESET pin
contains an internal Schmitt trigger as part of its input to improve noise
immunity. Refer to Section 5. Resets for more detail.
1.6.5 TCAP
This pin controls the input capture feature for the on-chip programmable
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity. Refer to Section 8. Capture/Compare
Timer for more detail.
1.6.6 TCMP
The TCMP pin provides an output for the output compare feature of the
on-chip programmable timer. Refer to Section 8. Capture/Compare
Timer for more detail.
1.6.7 PA0–PA7
These eight I/O lines comprise port A. The state of each pin is software
programmable and all port A pins are configured as inputs during reset.
Refer to Section 7. Input/Output Ports for more detail.
1.6.8 PB0–PB7
These eight I/O lines comprise port B. The state of each pin is software
programmable and all port B pins are configured as inputs during reset.
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Port B has mask option register enabled pullup devices and interrupt
capability selectable for any pin. Refer to Section 7. Input/Output Ports
for more detail.
1.6.9 PC0–PC7
These eight I/O lines comprise port C. The state of each pin is software
programmable and all port C pins are configured as inputs during reset.
PC7 has high current sink and source capability. Refer to Section 7.
Input/Output Ports for more detail.
1.6.10 PD0–PD5 a nd PD7
These seven I/O lines comprise port D. The state of each pin is software
programmable and all port D pins are configured as inputs during reset.
Refer to Section 7. Input/Output Ports for more detail.
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 2. Me m ory
2.1 Conte nts
2.2
2.3
2.4
2.5
2.6
Introduction...............................................................................27
RAM..........................................................................................27
ROM .........................................................................................29
ROM Security ...........................................................................29
I/O Registers.............................................................................29
2.2 Introd uc tion
The MCU has a 16-Kbyte memory map. The memory map consists of
registers (I/O, control and status), user RAM, user ROM, self-check
ROM, and reset and interrupt vectors as shown in Figure 2-1 and
Figure 2-2.
Two control bits in the option register ($3FDF) allow the user to switch
between RAM and ROM at any time in two special areas of the memory
map, $0020–$004F (48 bytes) and $0100-$017F (128 bytes).
2.3 RAM
The main user RAM consists of 176 bytes at $0050–$00FF. This RAM
area is always present in the memory map and includes a 64-byte stack
area. The stack pointer can access 64 bytes of RAM in the range $00FF
down to $00C0.
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Me m ory
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
PORT A DATA REGISTER
PORT B DATA REGISTER
I/O REGISTERS
32 BYTES
PORT C DATA REGISTER
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
PORT D DATA DIRECTION REGISTER
UNUSED
$001F
$0020
USER ROM
48 BYTES
RAM0 = 0
RAM
48 BYTES
RAM0 = 1
$004F
$0050
UNUSED
SPI CONTROL REGISTER
SPI STATUS REGISTER
RAM
176 BYTES
$00BF
$00C0
SPI DATA REGISTER
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
(STACK)
64 BYTES
$00FF
$0100
USER ROM
128 BYTES
RAM
128 BYTES
SCI DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
RAM1 = 0
RAM1 = 1
$017F
$0180
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER COUNTER REGISTER (HIGH)
TIMER COUNTER REGISTER (LOW)
ALTERNATE COUNTER REGISTER (HIGH)
ALTERNATE COUNTER REGISTER (LOW)
UNUSED
USER ROM
15,744 BYTES
COP RESET REGISTER
COP CONTROL REGISTER
UNUSED
$3EFF
$3F00
$3FF0
UNUSED (4 BYTES)
$3FF3
$3FF4
$3FF5
$3FF6
$3FF7
$3FF8
$3FF9
$3FFA
$3FFB
$3FFC
$3FFD
$3FFE
$3FFF
SELF-CHECK
ROM
SPI VECTOR (HIGH)
SPI VECTOR (LOW)
SCI VECTOR (HIGH)
AND VECTORS
239 BYTES
SCI VECTOR (LOW)
TIMER VECTOR (HIGH)
TIMER VECTOR (LOW)
IRQ VECTOR (HIGH)
IRQ VECTOR (LOW)
SWI VECTOR (HIGH)
SWI VECTOR (LOW)
$3FDF
$3FEF
$3FF0
OPTION REGISTER
USER ROM VECTORS
16 BYTES
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
$3FFF
Figure 2-1. Memory Map
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Memory
ROM
NOTE: Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
Two additional RAM areas are available at $0020–$004F (48 bytes) and
$0100–$017F (128 bytes) (see Figure 2-1 and Figure 2-2.) These may
be accessed at any time by setting the RAM0 and RAM1 bits,
respectively, in the option register.
Refer to 1.5 Software-Programmable Options for additional
information.
2.4 ROM
The user ROM consists of 48 bytes of page zero ROM from $0020 to
$004F, 15,872 bytes of ROM from $0100 to $3EFF, and 16 bytes of user
vectors from $3FF0 to $3FFF.
2.5 ROM Se c urity
2.6 I/ O Re g iste rs
A security feature has been incorporated into the MC68HC05C9A to
help prevent external access to the contents of the ROM in any mode of
operation.
Except for the option register, all I/O, control and status registers are
located within one 32-byte block in page zero of the address space
($0000–$001F). A summary of these registers is shown in Figure 2-2.
More detail about the contents of these registers is given in two
diagrams, each showing a block of 16 registers. Figure 2-3 shows
registers $0000 to $000F and Figure 2-4 shows registers $0010 to
$001F.
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Me m ory
Addr
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Register Name
Port A Data Register
Port B Data Register
Port C Data Register
Port D Data Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port D Data Direction Register
Unused
Unused
Serial Peripheral Control Register
Serial Peripheral Status Register
Serial Peripheral Data Register
Baud Rate Register
Serial Communications Control Register 1
Serial Communications Control Register 2
Serial Communications Status Register
Serial Communications Data Register
Timer Control Register
Timer Status Register
Input Capture Register High
Input Capture Register Low
Output Compare Register High
Output Compare Register Low
Timer Register High
Timer Register Low
Alternate Timer Register High
Alternate Timer Register Low
Unused
COP Reset Register
COP Control Register
Reserved
Figure 2-2. I/O Register Summary
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Memory
I/O Registers
ADDR
REGISTER
PORTA
ACCESS
READ:
WRITE:
READ:
WRITE:
READ:
WRITE
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
BIT 7
PA7
BIT 6
PA6
BIT 5
PA5
BIT 4
PA4
BIT 3
PA3
BIT 2
PA2
BIT 1
BIT 0
PA0
PA1
PB1
$0000
PB7
PC7
PB6
PC6
PB5
PC5
PB4
PC4
PB3
PC3
PB2
PC2
PB0
PC0
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PORTB
PORTC
PORTD
DDRA
PC1
PD7
PD5
PD4
PD3
PD2
PD1
PD0
DDRA7
DDRB7
DDRC7
DDRD7
DDRA6
DDRB6
DDRC6
DDRA5
DDRB5
DDRC5
DDRD5
DDRA4
DDRB4
DDRC4
DDRD4
DDRA3
DDRB3
DDRC3
DDRD3
DDRA2
DDRB2
DDRC2
DDRD2
DDRA1
DDRB1
DDRC1
DDRD1
DDRA0
DDRB0
DDRC0
DDRD0
DDRB
DDRC
DDRD
UNUSED
UNUSED
SPCR
SPIE
SPIF
SPE
DWOM
MSTR
MODF
CPOL
SPD3
CPHA
SPR1
SPR0
WCOL
SPSR
SPD7
SPD6
SPD5
SCP1
SPD4
SCP0
M
SPD2
SCR2
SPD1
SCR1
SPD0
SCR0
SPDR
BAUD
R8
T8
WAKE
TE
SCCR1
SCCR2
TIE
TCIE
RIE
ILIE
RE
RWU
SBK
Figure 2-3. I/O Register Map
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Me m ory
ADDR
REGISTER
ACCESS
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
READ:
WRITE:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
$0010
SCSR
SCD7
SCD6
SCD5
SCD4
0
SCD3
0
SCD2
0
SCD1
SCD0
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
SCDR
TCR
ICIE
ICF
OCIE
OCF
TOIE
TOF
IEDG
0
OLVL
0
0
0
0
TSR
BIT15
BIT7
BIT14
BIT6
BIT13
BIT5
BIT12
BIT4
BIT11
BIT3
BIT10
BIT2
BIT9
BIT1
BIT8
BIT0
ICRH
ICRL
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
OCRH
OCRL
TRH
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT9
BIT0
BIT8
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT7
BIT15
BIT7
BIT6
BIT14
BIT6
BIT5
BIT13
BIT5
BIT4
BIT12
BIT4
BIT3
BIT11
BIT3
BIT2
BIT10
BIT2
BIT1
BIT9
BIT1
BIT0
BIT8
BIT0
TRL
ATRH
ATRL
UNUSED
COPRST
COPCR
RESERVED
BIT7
0
BIT6
0
BIT5
0
BIT4
BIT3
CME
BIT2
BIT1
CM1
BIT0
CM0
COPF
COPE
Figure 2-4. I/O Register Map
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Se c tion 3. Ce ntra l Proc e ssing Unit
3.1 Conte nts
3.2
Introduction...............................................................................33
3.3
CPU Registers..........................................................................34
Accumulator (A)...................................................................35
Index Register (X) ...............................................................35
Program Counter (PC) ........................................................35
Stack Pointer (SP)...............................................................35
Condition Code Register (CCR)..........................................36
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.2 Introd uc tion
This section contains the basic programmers model and the registers
contained in the CPU.
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Ce ntra l Proc e ssing Unit
3.3 CPU Re g iste rs
The MCU contains five registers as shown in the programming model of
Figure 3-1. The interrupt stacking order is shown in Figure 3-2.
7
7
0
A
X
ACCUMULATOR
0
0
0
INDEX REGISTER
13
13
PC
1
PROGRAM COUNTER
STACK POINTER
7
0
0
0
0
0
0
1
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
0
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
STACK
1
1
1
I
N
T
E
R
R
U
P
R
E
T
U
R
N
INCREASING
MEMORY
ADDRESSES
DECREASING
MEMORY
ADDRESSES
T
PCL
UNSTACK
Figure 3-2. Interrupt Stacking Order
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Central Processing Unit
CPU Registers
3.3.1 Ac c um ula tor (A)
The accumulator is a general-purpose 8-bit register used to hold
operands and results of arithmetic calculations or data manipulations.
3.3.2 Ind e x Re g iste r (X)
The index register is an 8-bit register used for the indexed addressing
value to create an effective address. The index register may also be
used as a temporary storage area.
3.3.3 Prog ra m Counte r (PC)
The program counter is a 14-bit register that contains the address of the
next byte to be fetched.
3.3.4 Sta c k Pointe r (SP)
The stack pointer contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $0FF. The stack pointer is then
decremented as data is pushed onto the stack and incremented as data
is pulled from the stack.
When accessing memory, the eight most significant bits are permanently
set to 00000011. These eight bits are appended to the six least
significant register bits to produce an address within the range of $00FF
to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
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Ce ntra l Proc e ssing Unit
3.3.5 Cond ition Cod e Re g iste r (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the
results of the instruction just executed, and the fifth bit indicates whether
interrupts are masked. These bits can be individually tested by a
program, and specific actions can be taken as a result of their state.
Each bit is explained in the following paragraphs.
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer, SCI, SPI, and external interrupt are
masked (disabled). If an interrupt occurs while this bit is set, the
interrupt is latched and processed as soon as the interrupt bit is
cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit is also affected during bit test and branch instructions and during
shifts and rotates.
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Se c tion 4. Inte rrup ts
4.1 Conte nts
4.2
4.3
4.4
4.5
4.6
4.7
Introduction...............................................................................37
Non-Maskable Software Interrupt (SWI)...................................39
External Interrupt (IRQ or Port B) .............................................39
Timer Interrupt ..........................................................................40
SCI Interrupt .............................................................................40
SPI Interrupt..............................................................................40
4.2 Introd uc tion
The MCU can be interrupted by five different sources, four maskable
hardware interrupts, and one non-maskable software interrupt:
• External signal on the IRQ pin or port B pins
• 16-bit programmable timer
• Serial communications interface
• Serial peripheral interface
• Software interrupt instruction (SWI)
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
RTI instruction causes the register contents to be recovered from the
stack and normal processing to resume.
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
NOTE: The current instruction is the one already fetched and being operated on.
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Inte rrup ts
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If an external interrupt and a timer, SCI, or SPI interrupt are pending at
the end of an instruction execution, the external interrupt is serviced first.
The SWI is executed the same as any other instruction, regardless of the
I-bit state.
Table 4-1 shows the relative priority of all the possible interrupt sources.
Figure 4-1 shows the interrupt processing flow.
Table 4-1. Vector Addresses for Interrupts and Resets
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector
Address
Function
Source
Power-On-Reset
RESET Pin
Reset
None
None
1
$3FFE–$3FFF
COP Watchdog
Software
Interrupt
(SWI)
Same Priority
As Instruction
User Code
None
None
None
I Bit
$3FFC–$3FFD
$3FFA–$3FFB
External
Interrupt
IRQ Pin
Port B Pins
2
3
ICF Bit
OCF Bit
TOF Bit
TDRE Bit
TC Bit
ICIE Bit
OCIE Bit
TOIE Bit
Timer
Interrupts
I Bit
$3FF8–$3FF9
TCIE Bit
SCI
Interrupts
RDRF Bit
OR BIt
I Bit
I Bit
4
5
$3FF6–$3FF7
$3FF4–$3FF5
RIE Bit
ILIE Bit
SPIE
IDLE Bit
SPIF Bit
MODF Bit
SPI
Interrupts
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Interrupts
Non-Maskable Software Interrupt (SWI)
4.3 Non-Ma ska b le Softwa re Inte rrup t (SWI)
The SWI is an executable instruction and a non-maskable interrupt: It is
executed regardless of the state of the I bit in the CCR. If the I bit is zero
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched, but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $3FFC and $3FFD.
4.4 Exte rna l Inte rrup t (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $3FFA and $3FFB.
When any of the port B pullups are enabled, each pin becomes an
additional external interrupt source which is executed identically to the
IRQ pin. Port B interrupts follow the same edge/edge-level selection as
the IRQ pin. The branch instructions BIL and BIH also respond to the
port B interrupts in the same way as the IRQ pin. See 7.4 Port B.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger operation is selectable. The sensitivity is software-controlled
by the IRQ bit in the option register ($3FDF).
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse can be latched
and serviced as soon as the I bit is cleared.
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Inte rrup ts
4.5 Tim e r Inte rrup t
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $3FF8 and $3FF9.
4.6 SCI Inte rrup t
Five different SCI interrupt flags cause an SCI interrupt whenever they
are set and enabled. The interrupt flags are in the SCI status register
(SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$3FF6 and $3FF7.
4.7 SPI Inte rrup t
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$3FF4 and $3FF5.
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Interrupts
SPI Interrupt
FROM RESET
I BIT
Y
IN CCR
SET?
N
CLEAR IRQ
REQUEST
LATCH
IRQ OR PORT B
EXTERNAL
INTERRUPT
Y
Y
Y
Y
N
INTERNAL
TIMER
INTERRUPT
N
INTERNAL
SCI
INTERRUPT
N
INTERNAL
SPI
INTERRUPT
N
STACK
PC,X,A,CCR
FETCH NEXT
INSTRUCTION
SET I BIT IN
CC REGISTER
LOAD PC FROM:
SWI
Y
SWI: $3FFC-$3FFD
IRQ: $3FFA-$3FFB
TIMER: $3FF8-$3FF9
SCI: $3FF6-$3FF7
SPI: $3FF4-$3FF5
INSTRUCTION
?
N
RTI
Y
INSTRUCTION
?
N
RESTORE REGISTERS
FROM STACK:
EXECUTE
INSTRUCTION
CCR,A,X,PC
Figure 4-1. Interrupt Flowchart
MC68HC05C9A — Rev. 4.0
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Inte rrup ts
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MC68HC05C9A — Rev. 4.0
Interrupts
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Se c tion 5. Re se ts
5.1 Conte nts
5.2
5.3
5.4
Introduction...............................................................................44
Power-On Reset (POR)............................................................44
RESET Pin................................................................................45
5.5
5.5.1
5.5.2
Computer Operating Properly (COP) Reset .............................46
COP Reset Register............................................................47
COP Control Register..........................................................48
5.6
5.7
5.8
COP During Wait Mode ............................................................50
COP During Stop Mode............................................................50
Clock Monitor Reset .................................................................50
MC68HC05C9A — Rev. 4.0
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Re se ts
5.2 Introd uc tion
The MCU can be reset four ways: by the initial power-on reset function,
by an active low input to the RESET pin, by the COP, or by the clock
monitor. A reset immediately stops the operation of the instruction being
executed, initializes some control bits, and loads the program counter
with a user-defined reset vector address. Figure 5-1 is a block diagram
of the reset sources.
CLOCK MONITOR
COP WATCHDOG
V
POWER-ON RESET
DD
STOP
R
RST
TO CPU AND
SUBSYSTEMS
RESET
D
Q
RESET
LATCH
INTERNAL CLOCK
Figure 5-1. Reset Sources
5.3 Powe r-On Re se t (POR)
A power-on-reset occurs when a positive transition is detected on V .
DD
The power-on reset is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
internal processor clock cycle (t ) oscillator stabilization delay after the
cyc
oscillator becomes active. The RESET pin will output a logic zero during
the 4064-cycle delay. If the RESET pin is low after the end of this 4064-
cycle delay, the MCU will remain in the reset condition until RESET is
driven high externally.
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Resets
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Resets
RESET Pin
5.4 RESET Pin
The MCU is reset when a logic zero is applied to the RESET input for a
period of one and one-half machine cycles (t ). However, in order to
RL
differentiate between an external reset and an internal reset (generated
from the COP or clock monitor), any externally driven reset must be
active (logic zero) for at least eight t
.
CYC
t
V
VDDR
DD
2
OSC1
4064t
CYC
t
CYC
INTERNAL
1
CLOCK
INTERNAL
ADDRESS
BUS
1
NEW
PC
NEW
PC
NEW
PC
NEW
PC
3FFE
3FFF
3FFE 3FFE
3FFE
3FFE
PCH
3FFF
PCL
INTERNAL
DATA
NEW
PCH
NEW
PCL
OP
CODE
OP
CODe
1
DUMMY
DUMMY
BUS
t
RL
3
4
RESET
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only meant to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. RESET outputs VOL during 4064 power-on reset cycles.
Figure 5-2. Power-On Reset and RESET
MC68HC05C9A — Rev. 4.0
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Resets
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Re se ts
5.5 Com p ute r Op e ra ting Prop e rly (COP) Re se t
This device includes a watchdog COP feature which guards against
program run-away failures. A timeout of the computer operating properly
(COP) timer generates a COP reset. The COP watchdog is a software
error detection system that automatically times out and resets the MCU
if not cleared periodically by a program sequence.
The COP is controlled with two registers; one to reset the COP timer and
the other to enable and control COP and clock monitor functions. Figure
5-3 shows a block diagram of the COP.
CM1
CM0
INTERNAL
CPU
CLOCK
÷4
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
215
217
219
221
16 BIT TIMER SYSTEM
213
COP
÷4
÷2
÷2
÷2
÷2
÷2
÷2
COPRST
Figure 5-3. COP Block Diagram
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Resets
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Resets
Computer Operating Properly (COP) Reset
5.5.1 COP Re se t Re g iste r
This write-only register, shown in Figure 5-4, is used to reset the COP.
$001D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
= Unimplemented
Figure 5-4. COP Reset Register (COPRST)
The sequence required to reset the COP timer is as follows:
• Write $55 to the COP reset register
• Write $AA to the COP reset register
Both write operations must occur in the order listed, but any number of
instructions may be executed between the two write operations provided
that the COP does not time out between the two writes. The elapsed
time between software resets must not be greater than the COP timeout
period. If the COP should time out, a system reset will occur and the
device will be re-initialized in the same fashion as a power-on reset or
reset.
Reading this register does not return valid data.
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Re se ts
5.5.2 COP Control Re g iste r
The COP control register, shown in Figure 5-5, performs the following
functions:
• Enables clock monitor function
• Enables COP function
• Selects timeout duration of COP timer
and flags the following conditions:
• A COP timeout
• Clock monitor reset
$001E
Read:
Write:
Reset:
Bit 7
0
6
0
5
0
4
COPF
U
3
CME
0
2
COPE
0
1
CM1
0
Bit 0
CM0
0
0
0
0
= Unimplemented
U = Undetermined
Figure 5-5. COP Control Register (COPCR)
COPF — Computer Operating Properly Flag
Reading the COP control register clears COPF.
1 = COP or clock monitor reset has occurred.
0 = No COP or clock monitor reset has occurred.
CME — Clock Monitor Enable
This bit is readable any time, but may be written only once.
1 = Clock monitor enabled
0 = Clock monitor disabled
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Resets
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Resets
Computer Operating Properly (COP) Reset
COPE — COP Enable
This bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset.
1 = COP enabled
0 = COP disabled
CM1 — COP Mode Bit 1
Used in conjunction with CM0 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
CM0 — COP Mode Bit 0
Used in conjunction with CM1 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
Bits 7–5 — Not Used
These bits always read as zero.
Table 5-1. COP Timeout Period
Timeout Period
(f = 2.0 MHz)
Timeout Period
(f = 4.0 MHz)
15
CM1
CM0
f
/2 Divide By
op
osc
osc
0
0
1
1
0
1
0
1
1
4
32.77 ms
131.07 ms
524.29 ms
2.097 sec
16.38 ms
65.54 ms
262.14 ms
1.048 sec
16
64
MC68HC05C9A — Rev. 4.0
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Re se ts
5.6 COP During Wa it Mod e
The COP will continue to operate normally during wait mode. The
software must pull the device out of wait mode periodically and reset the
COP to prevent a system reset.
5.7 COP During Stop Mod e
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an IRQ is used to
exit stop mode, the COP counter will not be reset after the 4064-cycle
delay and will have that many cycles already counted when control is
returned to the program.
In the event that an inadvertent STOP instruction is executed, the COP
will not provide a reset. The clock monitor function provides protection
for this situation.
5.8 Cloc k Monitor Re se t
The clock monitor circuit can provide a system reset if the clock stops for
any reason, including stop mode. When the CME bit in the COP control
register is set, the clock monitor detects the absence of the internal bus
clock for a certain period of time. The timeout period is dependent on the
processing parameters and varies from 5 µs to 100 µs, which implies
that systems using a bus clock rate of 200 kHz or less should not use the
clock monitor.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system via the bidirectional
RESET pin for four bus cycles if the clock is slow or until the clocks
recover in the case where the clocks are absent.
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MC68HC05C9A — Rev. 4.0
Resets
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Se c tion 6. Low-Powe r Mod e s
6.1 Conte nts
6.2
6.3
6.4
Introduction...............................................................................51
Stop Mode ................................................................................51
Wait Mode.................................................................................52
6.2 Introd uc tion
6.3 Stop Mod e
This section describes the low-power modes.
The STOP instruction places the MCU in its lowest-power consumption
mode. In stop mode, the internal oscillator is turned off, halting all
internal processing, including timer operation.
During the stop mode, the TCR bits are altered to remove any pending
timer interrupt request and to disable any further timer interrupts. The
timer prescaler is cleared. The I bit in the CCR is cleared to enable
external interrupts. All other registers and memory remain unaltered. All
input/output lines remain unchanged. The processor can be brought out
of the stop mode only by an external interrupt or reset. See Figure 6-1.
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Low-Powe r Mod e s
1
OSC1
t
RL
RESET
t
LIH
2
IRQ
t
4064 t
ILCH
cyc
3
IRQ
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
3FFE
3FFE
3FFE
3FFE
3FFF
NOTES:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level and edge-sensitive mask option
RESET OR INTERRUPT
VECTOR FETCH
Figure 6-1. Stop Recovery Timing Diagram
6.4 Wa it Mod e
The WAIT instruction places the MCU in a low-power consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the timer, SCI, SPI, and the oscillator
remain active. Any interrupt or reset will cause the MCU to exit the wait
mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer, SCI, and SPI may be enabled to allow a periodic exit
from the wait mode.
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Low-Power Modes
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Se c tion 7. Inp ut/ Outp ut Ports
7.1 Conte nts
7.2
7.3
7.4
7.5
7.6
Introduction...............................................................................53
Port A........................................................................................53
Port B........................................................................................54
Port C........................................................................................55
Port D........................................................................................55
7.2 Introd uc tion
This section briefly describes the 31 I/O lines arranged as one 7-bit and
three 8-bit ports. All of these port pins are programmable as either inputs
or outputs under software control of the data direction registers.
NOTE: To avoid a glitch on the output pins, write data to the I/O port data
register before writing a one to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. The contents of the port A data
register are indeterminate at initial powerup and must be initialized by
user software. Reset does not affect the data registers, but clears the
data direction registers, thereby returning the ports to inputs. Writing a
one to a DDR bit sets the corresponding port bit to output mode. A block
diagram of the port logic is shown in Figure 7-1.
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Inp ut/ Outp ut Ports
DATA DIRECTION
REGISTER BIT
INTERNAL
LATCHED OUTPUT
HC05
CONNECTIONS
I/O
OUTPUT
PIN
DATA BIT
INPUT
REG
BIT
INPUT
I/O
Figure 7-1. Port A I/O Circuit
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001
and the data direction register (DDR) is at $0005. The contents of the
port B data register are indeterminate at initial powerup and must be
initialized by user software. Reset does not affect the data registers, but
clears the data direction registers, thereby returning the ports to inputs.
Writing a one to a DDR bit sets the corresponding port pin to output
mode. Each of the port B pins has an optional external interrupt
capability that can be enabled by mask option.
The interrupt option also enables a pullup device when the pin is
configured as an input. The edge or edge- and level-sensitivity of the
IRQ pin will also pertain to the enabled port B pins. Care needs to be
taken when using port B pins that have the pullup enabled. Before
switching from an output to an input, the data should be preconditioned
to a one to prevent an interrupt from occurring. The port B logic is shown
in Figure 7-2.
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Input/Output Ports
Port C
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002
and the data direction register (DDR) is at $0006. The contents of the
port C data register are indeterminate at initial powerup and must be
initialized by user software. Reset does not affect the data registers, but
clears the data direction registers, thereby returning the ports to inputs.
Writing a one to a DDR bit sets the corresponding port bit to output
mode. PC7 has a high current sink and source capability. Figure 7-1 is
also applicable to port C.
7.6 Port D
Port D is a 7-bit bidirectional port. Four of its pins are shared with the SPI
subsystem and two more are shared with the SCI subsystem. The port
D data register is at $0003 and the data direction register is at $0007.
The contents of the port D data register are indeterminate at initial
powerup and must be initialized by user software. During reset all seven
bits become valid input ports because the DDR bits are cleared and the
special function output drivers associated with the SCI and SPI
subsystems are disabled, thereby returning the ports to inputs. Writing a
one to a DDR bit sets the corresponding port bit to output mode.
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Inp ut/ Outp ut Ports
V
V
DD
DD
DISABLED
ENABLED
PORT B EXTERNAL INTERRUPT
MASK OPTION
READ $0005
WRITE $0005
RESET
DATA DIRECTION
REGISTER B
BIT DDRB7
U
A
T
A
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
PBX
READ $0001
EDGE ONLY
SOFTWARE CONTROLLED OPTION
EDGE AND LEVEL
V
DD
D
C
Q
Q
EXTERNAL
INTERRUPT
REQUEST
FROM OTHER
PORT B PINS
R
I BIT
(FROM CCR)
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 7-2. Port B I/O Logic
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MC68HC05C9A — Rev. 4.0
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Se c tion 8. Ca p ture / Com p a re Tim e r
8.1 Conte nt
8.2
Introduction...............................................................................57
8.3
8.3.1
8.3.2
Timer Operation........................................................................58
Input Capture.......................................................................59
Output Compare..................................................................59
8.4
Timer I/O Registers...................................................................60
Timer Control Register (TCR) .............................................60
Timer Status Register (TSR)...............................................62
Timer Registers (TRH and TRL) .........................................63
Alternate Timer Registers (ATRH and ATRL) .....................64
Input Capture Registers (ICRH and ICRL)..........................65
Output Compare Registers (OCRH and OCRL)..................66
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
8.6
Timer During Wait Mode...........................................................67
Timer During Stop Mode...........................................................67
8.2 Introd uc tion
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the capture/compare subsystem.
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Ca p ture / Com p a re Tim e r
INTERNAL BUS
INTERNAL
PROCESSOR
CLOCK
HIGH LOW
BYTE BYTE
8-BIT
BUFFER
÷4
HIGH LOW
BYTE BYTE
$16
$17
OUTPUT
COMPARE
REGISTER
HIGH
BYTE
LOW
BYTE
INPUT
CAPTURE
REGISTER
16-BIT FREE
RUNNING
COUNTER
$14
$15
$18
$19
COUNTER
ALTERNATE
REGISTER
$1A
$1B
EDGE
DETECT
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
OUTPUT
COMPARE
CIRCUIT
D
Q
CLK
OUTPUT
LEVEL
REG.
TIMER
STATUS
REG.
$13
ICF OCF TOF
C
TIMER
CONTROLRESET
REG.
$12
ICIE OCIE TOIE IEDG OLVL
OUTPUT EDGE
LEVEL INPUT
(TCMP) (TCAP)
INTERRUPT CIRCUIT
Figure 8-1. Capture/Compare Timer Block Diagram
8.3 Tim e r Op e ra tion
The core of the capture/compare timer is a 16-bit free-running counter.
The counter provides the timing reference for the input capture and
output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms
and timing delays. Software can read the value in the 16-bit free-running
counter at any time without affecting the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
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Capture/Compare Timer
Timer Operation
Because the counter is 16 bits long and preceded by a fixed divide-by-4
prescaler, the counter rolls over every 262,144 internal clock cycles.
Timer resolution with a 4-MHz crystal is 2 µs.
8.3.1 Inp ut Ca p ture
The input capture function is a means to record the time at which an
external event occurs. When the input capture circuitry detects an active
edge on the TCAP pin, it latches the contents of the timer registers into
the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the TCAP
pin. Latching values into the input capture registers at successive edges
of opposite polarity measures the pulse width of the signal.
8.3.2 Outp ut Com p a re
The output compare function is a means of generating an output signal
when the 16-bit counter reaches a selected value. Software writes the
selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of
the counter to the value written in the output compare registers. When a
match occurs, the timer transfers the programmable output level bit
(OLVL) from the timer control register to the TCMP pin.
The programmer can use the output compare register to measure time
periods, to generate timing delays, or to generate a pulse of specific
duration or a pulse train of specific frequency and duty cycle on the
TCMP pin.
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Ca p ture / Com p a re Tim e r
8.4 Tim e r I/ O Re g iste rs
The following I/O registers control and monitor timer operation:
• Timer control register (TCR)
• Timer status register (TSR)
• Timer registers (TRH and TRL)
• Alternate timer registers (ATRH and ATRL)
• Input capture registers (ICRH and ICRL)
• Output compare registers (OCRH and OCRL)
8.4.1 Tim e r Control Re g iste r (TCR)
The timer control register, shown in Figure 8-2, performs these
functions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Controls the active edge polarity of the TCAP signal
• Controls the active level of the TCMP output
$0012
Read:
Write:
Reset:
Bit 7
ICIE
0
6
OCIE
0
5
TOIE
0
4
0
3
0
2
0
1
IEDG
U
Bit 0
OLVL
0
0
0
0
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Resets clear the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
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Capture/Compare Timer
Timer I/O Registers
OCIE — Output Compare Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Resets clear the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow.
Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
OLVL — Output Level
The state of this read/write bit determines whether a logic one or logic
zero appears on the TCMP pin when a successful output compare
occurs. Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
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Ca p ture / Com p a re Tim e r
8.4.2 Tim e r Sta tus Re g iste r (TSR)
The timer status register, shown in Figure 8-3, contains flags to signal
the following conditions:
• An active signal on the TCAP pin, transferring the contents of the
timer registers to the input capture registers
• A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
• A timer roll over from $FFFF to $0000
$0012
Read:
Reset:
Bit 7
ICF
U
6
OCF
U
5
TOF
U
4
0
0
3
0
0
2
0
0
1
0
0
Bit 0
0
0
U = Undetermined
Figure 8-3. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Resets have no
effect on OCF.
TOF — Timer Overflow Flag
The TOF bit is set automatically when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.
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Timer I/O Registers
8.4.3 Tim e r Re g iste rs (TRH a nd TRL)
The timer registers, shown in Figure 8-4, contains the current high and
low bytes of the 16-bit counter. Reading TRH before reading TRL
causes TRL to be latched until TRL is read. Reading TRL after reading
the timer status register clears the timer overflow flag (TOF). Writing to
the timer registers has no effect.
TRH
$0018
Read:
Write
Bit 7
6
5
4
3
2
1
Bit 0
BIT8
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
Reset:
1
1
1
1
1
1
1
1
TRL
$0019
Bit 7
BIT7
6
5
4
3
2
1
Bit 0
BIT0
Read:
Write:
Reset:
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
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Ca p ture / Com p a re Tim e r
8.4.4 Alte rna te Tim e r Re g iste rs (ATRH a nd ATRL)
The alternate timer registers, shown in Figure 8-5, contain the current
high and low bytes of the 16-bit counter. Reading ATRH before reading
ATRL causes ATRL to be latched until ATRL is read. Reading ATRL has
no effect on the timer overflow flag (TOF). Writing to the alternate timer
registers has no effect.
ATRH
$001A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BIT8
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
1
1
1
1
1
1
1
1
ATRL
$001B
Bit 7
BIT7
6
5
4
3
2
1
Bit 0
BIT0
Read:
Write:
Reset:
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE: To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt flag in the condition code register before reading
ATRH, and clear the flag after reading ATRL.
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Timer I/O Registers
8.4.5 Inp ut Ca p ture Re g iste rs (ICRH a nd ICRL)
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the input capture registers.
Reading ICRH before reading ICRL inhibits further capture until ICRL is
read. Reading ICRL after reading the status register clears the input
capture flag (ICF). Writing to the input capture registers has no effect.
ICRH
$0014
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
BIT8
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
ICRL
$0015
Bit 7
BIT7
6
5
4
3
2
1
Bit 0
BIT0
Read:
Write:
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
RESET DOES NOT AFFECT THE INPUT CAPTURE REGISTERS
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
NOTE: To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt flag in the condition code register before reading
ICRH, and clear the flag after reading ICRL.
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Ca p ture / Com p a re Tim e r
8.4.6 Outp ut Com p a re Re g iste rs (OCRH a nd OCRL)
When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).
OCRH
$0016
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
BIT8
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
Unaffected by Reset
OCRL
$0017
Bit 7
BIT7
6
5
4
3
2
1
Bit 0
BIT0
Write:
Read:
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
Unaffected by Reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code
register.
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Capture/Compare Timer
Timer During Wait Mode
8.5 Tim e r During Wa it Mod e
The CPU clock halts during the wait mode, but the timer remains active.
If interrupts are enabled, a timer interrupt will cause the processor to exit
the wait mode.
8.6 Tim e r During Stop Mod e
In the stop mode, the timer stops counting and holds the last count value
if STOP is exited by an interrupt. If STOP is exited by RESET, the
counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is
armed. This does not set any timer flags or wake up the MCU, but if an
interrupt is used to exit stop mode, there is an active input capture flag
and data from the first valid edge that occurred during the stop mode. If
RESET is used to exit stop mode, then no input capture flag or data
remains, even if a valid input capture edge occurred.
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Ca p ture / Com p a re Tim e r
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 9. Se ria l Com m unic a tions Inte rfa c e (SCI)
9.1 Conte nt
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Introduction...............................................................................70
Features....................................................................................70
SCI Receiver Features .............................................................72
SCI Transmitter Features .........................................................72
Functional Description ..............................................................72
Data Format..............................................................................74
Receiver Wakeup Operation.....................................................75
Idle Line Wakeup......................................................................76
9.10 Address Mark Wakeup .............................................................76
9.11 Receive Data In (RDI)...............................................................76
9.12 Start Bit Detection.....................................................................78
9.13 Transmit Data Out (TDO) .........................................................80
9.14 SCI I/O Registers......................................................................80
9.14.1
9.14.2
9.14.3
9.14.4
9.14.5
SCI Data Register (SCDR)..................................................80
SCI Control Register 1 (SCCR1).........................................80
SCI Control Register 2 (SCCR2).........................................82
SCI Status Register (SCSR) ...............................................84
Baud Rate Register (BAUD)................................................86
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.2 Introd uc tion
This section describes the on-chip asynchronous serial communications
interface (SCI). The SCI allows full-duplex, asynchronous, RS232 or
RS422 serial communication between the MCU and remote devices,
including other MCUs. The transmitter and receiver of the SCI operate
independently, although they use the same baud rate generator.
9.3 Fe a ture s
Features of the SCI include:
• Standard Mark/Space Non-Return-to-Zero Format
• Full Duplex Operation
• 32 Programmable Baud Rates
• Programmable 8-Bit or 9-Bit Character Length
• Separately Enabled Transmitter and Receiver
• Two Receiver Wakeup Methods:
– Idle Line Wakeup
– Address Mark Wakeup
• Interrupt-Driven Operation Capability with Five Interrupt Flags:
– Transmitter Data Register Empty
– Transmission Complete
– Transmission Data Register Full
– Receiver Overrun
– Idle Receiver Input
• Receiver Framing Error Detection
• 1/16 Bit-Time Noise Detection
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Serial Communications Interface (SCI)
Features
INTERNAL BUS
SCI INTERRUPT
+
TRANSMIT
DATA
REGISTER
RECEIVE
DATA
REGISTER
$0011
$0011
$000F
SCCR2
&
&
&
&
TIE
TCIE
RIE
ILIE
TE
RE
SBK
RWU
7
6
5
4
3
2
1
0
TRANSMIT
DATA SHIFT
REGISTER
RECEIVE
DATA SHIFT
REGISTER
TDO
PIN
RDI
PIN
+
5
SCSR
$0010
1
7
6
4
3
2
TRDE TC RDRF IDLE
OR
NF
FE
WAKEUP
UNIT
7
TE
SBK
FLAG
CONTROL
TRANSMITTER
CONTROL
RECEIVER
CONTROL
RECEIVER
CLOCK
7
R8
6
T8
5
4
M
3
2
1
0
SCCR1
$000E
WAKE
Figure 9-1. Serial Communications Interface Block Diagram
NOTE: The serial communications data register (SCI SCDR) is controlled by the
internal R/W signal. It is the transmit data register when written to and
the receive data register when read.
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.4 SCI Re c e ive r Fe a ture s
Features of the SCI receiver include:
• Receiver Wakeup Function (Idle Line or Address Bit)
• Idle Line Detection
• Framing Error Detection
• Noise Detection
• Overrun Detection
• Receiver Data Register Full Flag
9.5 SCI Tra nsm itte r Fe a ture s
Features of the SCI transmitter include:
• Transmit Data Register Empty Flag
• Transmit Complete Flag
• Send Break
9.6 Func tiona l De sc rip tion
A block diagram of the SCI is shown in Figure 9-1. Option bits in serial
control register1 (SCCR1) select the wakeup method (WAKE bit) and
data word length (M bit) of the SCI. SCCR2 provides control bits that
individually enable the transmitter and receiver, enable system
interrupts, and provide the wakeup enable bit (RWU) and the send break
code bit (SBK). Control bits in the baud rate register (BAUD) allow the
user to select one of 32 different baud rates for the transmitter and
receiver.
Data transmission is initiated by writing to the serial communications
data register (SCDR). Provided the transmitter is enabled, data stored in
the SCDR is transferred to the transmit data shift register. This transfer
of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter
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Serial Communications Interface (SCI)
Functional Description
interrupts are enabled). The transfer of data to the transmit data shift
register is synchronized with the bit rate clock (see Figure 9-2). All data
is transmitted least significant bit first. Upon completion of data
transmission, the transmission complete flag (TC) in the SCSR is set
(provided no pending data, preamble, or break is to be sent) and an
interrupt is generated (if the transmit complete interrupt is enabled). If
the transmitter is disabled, and the data, preamble, or break (in the
transmit data shift register) has been sent, the TC bit will be set also.
This will also generate an interrupt if the transmission complete interrupt
enable bit (TCIE) is set. If the transmitter is disabled during a
transmission, the character being transmitted will be completed before
the transmitter gives up control of the TDO pin.
When SCDR is read, it contains the last data byte received, provided
that the receiver is enabled. The receive data register full flag bit (RDRF)
in the SCSR is set to indicate that a data byte has been transferred from
the input serial shift register to the SCDR; this will cause an interrupt if
the receiver interrupt is enabled. The data transfer from the input serial
shift register to the SCDR is synchronized by the receiver bit rate clock.
The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR
may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and
the IDLE bit (which detects idle line transmission) in SCSR is set. This
allows a receiver that is not in the wakeup mode to detect the end of a
message, or the preamble of a new message, or to re-synchronize with
the transmitter. A valid character must be received before the idle line
condition or the IDLE bit will not be set and idle line interrupt will not be
generated.
SCP0–SCP1
SCR0–SCR2
SCI TRANS
CLOCK (TX)
SCI PRESCALER
SELECT
SCI RATE
SELECT
CONTROL
OSC FREQ
(fOSC
SCI RECEIVE
CLOCK (RT)
BUS FREQ
(fOP
÷2
÷16
)
)
CONTROL
N
M
Figure 9-2. Rate Generator Division
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.7 Da ta Form a t
Receive data or transmit data is the serial data that is transferred to the
internal data bus from the receive data input pin (RDI) or from the
internal bus to the transmit data output pin (TDO). The non-return-to-
zero (NRZ) data format shown in Figure 9-3 is used and must meet the
following criteria:
• The idle line is brought to a logic one state prior to
transmission/reception of a character.
• A start bit (logic zero) is used to indicate the start of a frame.
• The data is transmitted and received least significant bit first.
• A stop bit (logic one) is used to indicate the end of a frame. A
frame consists of a start bit, a character of eight or nine data bits,
and a stop bit.
• A break is defined as the transmission or reception of a low (logic
zero) for at least one complete frame time.
CONTROL BIT M SELECTS
8- OR 9-BIT DATA
IDLE LINE
0
1
2
3
4
5
6
7
8
0
START
STOP
START
Figure 9-3. Data Format
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Serial Communications Interface (SCI)
Receiver Wakeup Operation
9.8 Re c e ive r Wa ke up Op e ra tion
The receiver logic hardware also supports a receiver wakeup function
which is intended for systems having more than one receiver. With this
function a transmitting device directs messages to an individual receiver
or group of receivers by passing addressing information as the initial
byte(s) of each message. The wakeup function allows receivers not
addressed to remain in a dormant state for the remainder of the
unwanted message. This eliminates any further software overhead to
service the remaining characters of the unwanted message and thus
improves system performance.
The receiver is placed in wakeup mode by setting the receiver wakeup
bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver-
related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot
become set).
NOTE: The idle line detect function is inhibited while the RWU bit is set.
Although RWU may be cleared by a software write to SCCR2, it would
be unusual to do so.
Normally, RWU is set by software and is cleared automatically in
hardware by one of these methods: idle line wakeup or address mark
wakeup.
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9.9 Id le Line Wa ke up
In idle line wakeup mode, a dormant receiver wakes up as soon as the
RDI line becomes idle. Idle is defined as a continuous logic high level on
the RDI line for 10 (or 11) full bit times. Systems using this type of
wakeup must provide at least one character time of idle between
messages to wake up sleeping receivers, but must not allow any idle
time between characters within a message.
9.10 Ad d re ss Ma rk Wa ke up
In address mark wakeup, the most significant bit (MSB) in a character is
used to indicate whether it is an address (logic one) or data (logic zero)
character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wakeup would set
the MSB of the first character of each message and leave it clear for all
other characters in the message. Idle periods may be present within
messages and no idle time is required between messages for this
wakeup method.
9.11 Re c e ive Da ta In (RDI)
Receive data is the serial data that is applied through the input line and
the SCI to the internal bus. The receiver circuitry clocks the input at a
rate equal to 16 times the baud rate. This time is referred to as the RT
rate in Figure 9-4 and as the receiver clock in Figure 9-6.
The receiver clock generator is controlled by the baud rate register;
however, the SCI is synchronized by the start bit, independent of the
transmitter.
Once a valid start bit is detected, the start bit, each data bit, and the stop
bit are sampled three times at RT intervals 8 RT, 9 RT, and 10 RT (1 RT
is the position where the bit is expected to start), as shown in Figure 9-
5. The value of the bit is determined by voting logic which takes the value
of the majority of the samples. A noise flag is set when all three samples
on a valid start bit or data bit or the stop bit do not agree.
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Serial Communications Interface (SCI)
Receive Data In (RDI)
16X INTERNAL SAMPLING CLOCK
RT CLOCK EDGES FOR ALL THREE EXAMPLES
3RT
1RT
START
2RT
4RT
5RT
6RT 7RT
IDLE
RDI
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
START
NOISE
RDI
RDI
1
0
0
1
0
0
START
NOISE
0
1
1
1
1
1
1
1
0
0
0
Figure 9-4. SCI Examples of Start Bit Sampling Techniques
PREVIOUS BIT
16RT 1RT
SAMPLES
9RT
NEXT BIT
RDI
8RT
10RT
16RT 1RT
Figure 9-5. SCI Sampling Technique Used on All Bits
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.12 Sta rt Bit De te c tion
When the input (idle) line is detected low, it is tested for three more
sample times (referred to as the start edge verification samples in
Figure 9-4). If at least two of these three verification samples detect a
logic zero, a valid start bit has been detected; otherwise, the line is
assumed to be idle. A noise flag is set if all three verification samples do
not detect a logic zero. Thus, a valid start bit could be assumed with a
set noise flag present.
If a framing error has occurred without detection of a break (10 zeros for
8-bit format or 11 zeros for 9-bit format), the circuit continues to operate
as if there actually was a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register is inverted to a
logic one, and the three logic one start qualifiers (shown in Figure 9-4)
are forced into the sample shift register during the interval when
detection of a start bit is anticipated (see Figure 9-6); therefore, the start
bit will be accepted no sooner than it is anticipated.
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data
register = $003B) produced the framing error, the start bit will not be
artificially induced and the receiver must actually detect a logic one
before the start bit can be recognized (see Figure 9-7).
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Serial Communications Interface (SCI)
Start Bit Detection
DATA
EXPECTED STOP
DATA
ARTIFICIAL EDGE
START BIT
RDI
DATA SAMPLES
a) Case 1: Receive line low during artificial edge
DATA
EXPECTED STOP
START EDGE
DATA
RDI
START BIT
DATA SAMPLES
b) Case 2: Receive line high during expected start edge
Figure 9-6. SCI Artificial Start Following a Frame Error
EXPECTED STOP
BREAK
DETECTED AS VALID START EDGE
START BIT
RDI
START
START EDGE
QUALIFIERS VERIFICATION
DATA SAMPLES
SAMPLES
Figure 9-7. SCI Start Bit Following a Break
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.13 Tra nsm it Da ta Out (TDO)
Transmit data is the serial data from the internal data bus that is applied
through the SCI to the output line. Data format is as discussed in 9.7
Data Format and shown in Figure 9-3. The transmitter generates a bit
time by using a derivative of the RT clock, thus producing a transmission
rate equal to 1/16th that of the receiver sample clock.
9.14 SCI I/ O Re g iste rs
The following I/O registers control and monitor SCI operation:
• SCI data register (SCDR)
• SCI control register 1 (SCCR1)
• SCI control register 2 (SCCR2)
• SCI status register (SCSR)
9.14.1 SCI Da ta Re g iste r (SCDR)
The SCI data register, shown in Figure 9-8, is the buffer for characters
received and for characters transmitted.
$0011
Read:
Write:
Reset:
Bit 7
BIT7
6
5
4
3
2
1
Bit 0
BIT0
BIT6
BIT55
BIT4
BIT3
BIT2
BIT1
Unaffected by Reset
Figure 9-8. SCI Data Register (SCDR)
9.14.2 SCI Control Re g iste r 1 (SCCR1)
The SCI control register 1, shown in Figure 9-9, has these functions:
• Stores ninth SCI data bit received and ninth SCI data bit
transmitted
• Controls SCI character length
• Controls SCI wakeup method
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SCI I/O Registers
$000E
Read:
Write:
Reset:
Bit 7
R8
U
6
T8
U
5
4
M
U
3
WAKE
U
2
0
1
0
Bit 0
0
0
= Unimplemented
U = Undetermined
Figure 9-9. SCI Control Register 1 (SCCR1)
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit at the same time that the
SCDR receives the other eight bits. Resets have no effect on the R8
bit.
T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that the SCDR is loaded into the transmit register.
Resets have no effect on the T8 bit.
M — Character Length
This read/write bit determines whether SCI characters are 8 bits long
or 9 bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Resets have
no effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Method
This read/write bit determines which condition wakes up the SCI: a
logic one (address mark) in the most significant bit (MSB) position of
a received character or an idle condition on the PD0/RDI pin. Resets
have no effect on the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
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9.14.3 SCI Control Re g iste r 2 (SCCR2)
SCI control register 2, shown in Figure 9-10, has these functions:
• Enables the SCI receiver and SCI receiver interrupts
• Enables the SCI transmitter and SCI transmitter interrupts
• Enables SCI receiver idle interrupts
• Enables SCI transmission complete interrupts
• Enables SCI wakeup
• Transmits SCI break characters
$000F
Read:
Write:
Reset:
Bit 7
TIE
0
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Figure 9-10. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable
This read/write bit enables SCI interrupt requests when the TDRE flag
becomes set. Resets clear the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
TCIE — Transmission Complete Interrupt Enable
This read/write bit enables SCI interrupt requests when the TC flag
becomes set. Resets clear the TCIE bit.
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receiver Interrupt Enable
This read/write bit enables SCI interrupt requests when the RDRF flag
or the OR flag becomes set. Resets clear the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
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Serial Communications Interface (SCI)
SCI I/O Registers
ILIE — Idle Line Interrupt Enable
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Resets clear the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmitter Enable
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic ones from the transmit shift register to the
PD1/TDO pin. Resets clear the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receiver Enable
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Resets clear the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of standby state.
Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic zeros. Clearing the SBK bit
stops the break codes and transmits a logic one as a start bit. Reset
clears the SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.14.4 SCI Sta tus Re g iste r (SCSR)
The SCI status register, shown in Figure 9-11, contains flags to signal
the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data SCDR complete
• Receiver input idle
• Noisy data
• Framing error
$0010
Read:
Write:
Reset:
Bit 7
TDRE
1
6
TC
1
5
RDRF
0
4
IDLE
0
3
OR
0
2
NF
0
1
FE
0
Bit 0
—
= Unimplemented
Figure 9-11. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty
This clearable, read-only flag is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic zero
to avoid an instant interrupt request when turning the transmitter on.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete
This clearable, read-only flag is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TDRE
generates an interrupt request if the TCIE bit in SCCR2 is also set.
Clear the TC bit by reading the SCSR with TC set, and then writing to
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Serial Communications Interface (SCI)
SCI I/O Registers
the SCDR. Reset sets the TC bit. Software must initialize the TC bit
to logic zero to avoid an instant interrupt request when turning the
transmitter on.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full
This clearable, read-only flag is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in the SCCR2 is also set. Clear the
RDRF bit by reading the SCSR with RDRF set and then reading the
SCDR.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle
This clearable, read-only flag is set when 10 or 11 consecutive logic
ones appear on the receiver input. IDLE generates an interrupt
request if the ILIE bit in the SCCR2 is also set. Clear the ILIE bit by
reading the SCSR with IDLE set and then reading the SCDR.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun
This clearable, read-only flag is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in the SCCR2 is also set. The data in
the shift register is lost, but the data already in the SCDR is not
affected. Clear the OR bit by reading the SCSR with OR set and then
reading the SCDR.
1 = Receive shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag
This clearable, read-only flag is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
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Se ria l Com munic a tions Inte rfa c e (SCI)
FE — Receiver Framing Error
This clearable, read-only flag is set when there is a logic zero where
a stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR flag is set and the FE flag is not set. Clear the
FE bit by reading the SCSR and then reading the SCDR.
1 = Framing error
0 = No framing error
9.14.5 Ba ud Ra te Re g iste r (BAUD)
The baud rate register, shown in Figure 9-12, selects the baud rate for
both the receiver and the transmitter.
$000D
Read:
Write:
Reset:
Bit 7
—
6
5
SCP1
0
4
SCP0
0
3
2
SCR2
U
1
SCR1
U
Bit 0
SCR0
U
—
—
= Unimplemented
U = Undetermined
Figure 9-12. Baud Rate Register (BAUD)
SCP1 — SCP0–SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Reset clears both SCP1 and SCP0.
Table 9-1. Baud Rate Generator
Clock Prescaling
SCP[1:0] Baud Rate Generator Clock
00
01
10
11
Internal Clock ÷ 1
Internal Clock ÷ 3
Internal Clock ÷ 4
Internal Clock ÷ 13
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Serial Communications Interface (SCI)
SCI I/O Registers
SCR2 — SCR0–SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in Table 9-
2. Resets have no effect on the SCR2-SCR0 bits.
Table 9-2. Baud Rate Selection
SCR[2:0]
000
SCI Baud Rate (Baud)
Prescaled Clock ÷ 1
Prescaled Clock ÷ 2
Prescaled Clock ÷ 4
Prescaled Clock ÷ 8
Prescaled Clock ÷ 16
Prescaled Clock ÷ 32
Prescaled Clock ÷ 64
Prescaled Clock ÷ 128
001
010
011
100
101
110
111
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Se ria l Com munic a tions Inte rfa c e (SCI)
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 10. Se ria l Pe rip he ra l Inte rfa c e
10.1 Conte nt
10.2 Introduction...............................................................................89
10.3 Features....................................................................................90
10.4 SPI Signal Description..............................................................90
10.4.1
10.4.2
10.4.3
10.4.4
Master In Slave Out (MISO)................................................91
Master Out Slave In (MOSI)................................................91
Serial Clock (SCK) ..............................................................92
Slave Select (SS) ................................................................92
10.5 Functional Description ..............................................................93
10.6 SPI Registers............................................................................95
10.6.1
10.6.2
10.6.3
Serial Peripheral Control Register (SPCR) .........................95
Serial Peripheral Status Register (SPSR)...........................97
Serial Peripheral Data I/O Register (SPDR)........................99
10.2 Introd uc tion
The serial peripheral interface (SPI) is an interface built into the device
which allows several MC68HC05 MCUs, or MC68HC05 MCU plus
peripheral devices, to be interconnected within a single printed circuit
board. In an SPI, separate wires are required for data and clock. In the
SPI format, the clock is not included in the data stream and must be
furnished as a separate signal. An SPI system may be configured in one
containing one master MCU and several slave MCUs, or in a system in
which an MCU is capable of being a master or a slave.
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10.3 Fe a ture s
Features include:
• Full Duplex, Four-Wire Synchronous Transfers
• Master or Slave Operation
• Bus Frequency Divided by 2 (Maximum) Master Bit Frequency
• Bus Frequency (Maximum) Slave Bit Frequency
• Four Programmable Master Bit Rates
• Programmable Clock Polarity and Phase
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Master-Master Mode Fault Protection Capability
10.4 SPI Sig na l De sc rip tion
The four basic signals (MOSI, MISO, SCK, and SS) are described in the
following paragraphs. Each signal function is described for both the
master and slave modes.
NOTE: Any SPI output line has to have its corresponding data direction register
bit set. If this bit is clear, the line is disconnected from the SPI logic and
becomes a general-purpose input line. When the SPI is enabled, any
SPI input line is forced to act as an input regardless of what is in the
corresponding data direction register bit.
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Serial Peripheral Interface
SPI Signal Description
SS
CPOL = 0
CPHA = 0
SCK
CPOL = 0
CPHA = 1
SCK
SCK
CPOL = 1
CPHA = 0
CPOL = 1
CPHA = 1
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
10.4.1 Ma ste r In Sla ve Out (MISO)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
10.4.2 Ma ste r Out Sla ve In (MOSI)
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit sent first.
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10.4.3 Se ria l Cloc k (SCK)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line a half cycle before the clock edge (SCK), in order for the slave
device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the
operation of the SPI.
10.4.4 Sla ve Se le c t (SS)
The slave select (SS) input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the
transaction.The SS line on the master must be tied high. In master
mode, if the SS pin is pulled low during a transmission, a mode fault error
flag (MODF) is set in the SPSR. In master mode the SS pin can be
selected to be a general-purpose output by writing a one in bit 5 of the
port D data direction register, thus disabling the mode fault circuit.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line
could be tied to V as long as CPHA = 1 clock modes are used.
SS
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Serial Peripheral Interface
Functional Description
10.5 Func tiona l De sc rip tion
Figure 10-2 shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the I/O operation has been
completed.
S
PD2/
MISO
M
M
SPI SHIFT REGISTER
PD3/
MOSI
S
7
6 5 4 3 2 1 0
INTERNAL DATA BUS
SPDR ($000C)
INTERNAL
CLOCK
(XTAL ÷2)
SPIE
SPE
MSTR
SPIF
WCOL
MODF
DIVIDER
SPI
CONTROL
SPI INTERRUPT REQUEST
PD5/
÷ 2 ÷ 4 ÷ 16 ÷ 32
SS
SPI
CLOCK
(MASTER)
SPI CLOCK (MASTER)
CLOCK
LOGIC
SELECT
SPI
CLOCK
(SLAVE)
PD4/
SCK
SPR1 SPR0
MSTR CPHA CPOL
7
6
5
4
3
2
1
0
SPI CONTROL REGISTER (SPCR) SPIE
SPI STATUS REGISTER (SPSR) SPIF WCOL
SPI DATA REGISTER (SPDR) BIT 7 BIT 6
SPE DWOM MSTR CPOL CPHA SPR1 SPR2 $000A
0
MODF
BIT 4
0
0
0
0
$000B
BIT 5
BIT 3
BIT 2
BIT 1
BIT 0 $000C
Figure 10-2. Serial Peripheral Interface Block Diagram
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Se ria l Pe rip he ra l Inte rfa c e
The SPI is double buffered on read, but not on write. If a write is
performed during data transfer, the transfer occurs uninterrupted, and
the write will be unsuccessful. This condition will cause the write collision
(WCOL) status bit in the SPSR to be set. After a data byte is shifted, the
SPIF flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
PD5/SS
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0
I/O PORT
SPDR ($000C)
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
Figure 10-3. Serial Peripheral Interface Master-Slave
Interconnection
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Serial Peripheral Interface
SPI Registers
10.6 SPI Re g iste rs
Three registers in the SPI provide control, status, and data storage
functions. These registers are called the serial peripheral control register
(SPCR), serial peripheral status register (SPSR), and serial peripheral
data I/O register (SPDR) and are described in the following paragraphs.
10.6.1 Se ria l Pe rip he ra l Control Re g iste r (SPCR)
The SPI control register, shown in Figure 10-4, controls these functions:
• Enables SPI interrupts
• Enables the SPI system
• Selects between standard CMOS or open drain outputs for port D
• Selects between master mode and slave mode
• Controls the clock/data relationship between master and slave
• Determines the idle level of the clock pin
$000A
Read:
Write:
Reset:
Bit 7
SPIE
0
6
SPE
0
5
DWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SPR1
U
Bit 0
SPR0
U
U = Undetermined
Figure 10-4. SPI Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
SPE — Serial Peripheral System Enable
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI system enabled
0 = SPI system disabled
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DWOM — Port D Wire-OR Mode Option
This read/write bit disables the high side driver transistors on port D
outputs so that port D outputs become open-drain drivers. DWOM
affects all seven port D pins together.
1 = Port D outputs act as open-drain outputs.
0 = Port D outputs are normal CMOS outputs.
MSTR — Master Mode Select
This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit is also used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA=1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Selects
These read/write bits select one of four master mode serial clock
rates, as shown in Table 10-1. They have no effect in the slave mode.
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SPI Registers
Table 10-1. SPI Clock
Rate Selection
SPR[1:0] SPI Clock Rate
00
01
10
11
Internal Clock ÷ 2
Internal Clock ÷ 4
Internal Clock ÷ 16
Internal Clock ÷ 32
10.6.2 Se ria l Pe rip he ra l Sta tus Re g iste r (SPSR)
The SPI status register, shown in Figure 10-5, contains flags to signal
the following conditions:
• SPI transmission complete
• Write collision
• Mode fault
SPSR
Read:
Write:
Reset:
Bit 7
6
5
0
4
3
0
2
0
1
0
Bit 0
0
SPIF
WCOL
MODF
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. SPI Status Register
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Following the initial
transfer, unless SPSR is read (with SPIF set) first, attempts to write to
SPDR are inhibited.
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WCOL — Write Collision
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is zero, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is one, a transfer is said to begin the first time SCK
becomes active while SS is low and the transfer ends when the SPIF
flag gets set. Clearing the WCOL bit is accomplished by reading the
SPSR (with WCOL set) followed by an access to SPDR.
MODF — Mode Fault
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear, and is set only when the master device has its SS pin pulled
low. Setting the MODF bit affects the internal serial peripheral
interface system in the following ways.
1. An SPI interrupt is generated if SPIE = 1.
2. The SPE bit is cleared. This disables the SPI.
3. The MSTR bit is cleared, thus forcing the device into the slave
mode.
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state during
this clearing sequence or after the MODF bit has been cleared. It is
also necessary to restore DDRD after a mode fault.
Bits 5 and 3–0 — Not Implemented
These bits always read zero.
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SPI Registers
10.6.3 Se ria l Pe rip he ra l Da ta I/ O Re g iste r (SPDR)
The serial peripheral data I/O register, shown in Figure 10-6, is used to
transmit and receive data on the serial bus. Only a write to this register
will initiate transmission/reception of another byte and this will only occur
in the master device. At the completion of transmitting a byte of data, the
SPIF status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and
places data directly into the shift register for transmission.
$000C
Read:
Write:
Reset:
Bit 7
SPD7
U
6
SPD6
U
5
SPD5
U
4
SPD4
U
3
SPD3
U
2
SPD2
U
1
SPD1
U
Bit 0
SPD0
U
U = Undetermined
Figure 10-6. PI Data Register (SPDR)
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 11. Instruc tion Se t
11.1 Conte nts
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .106
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . .107
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .108
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .110
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
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11.2 Introd uc tion
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
11.3 Ad d re ssing Mod e s
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
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11.3.1 Inhe re nt
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
11.3.2 Im m e d ia te
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
11.3.3 Dire c t
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
11.3.4 Exte nd e d
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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11.3.5 Ind e xe d , No Offse t
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
11.3.6 Ind e xe d , 8-Bit Offse t
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
11.3.7 Ind e xe d ,16-Bit Offse t
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Freescale assembler
determines the shortest form of indexed addressing.
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11.3.8 Re la tive
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
11.4 Instruc tion Typ e s
The MCU instructions fall into the following five categories:
• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions
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11.4.1 Re g iste r/ Me m ory Instruc tions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 11-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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11.4.2 Re a d -Mod ify-Write Instruc tions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 11-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Bit Clear
Mnemonic
ASL
ASR
(1)
BCLR
(1)
Bit Set
BSET
Clear Register
CLR
COM
DEC
INC
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
NEG
ROL
ROR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence be-
cause it does not write a replacement value.
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11.4.3 Jum p / Bra nc h Instruc tions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Table 11-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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11.4.4 Bit Ma nip ula tion Instruc tions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 11-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
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11.4.5 Control Instruc tions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 11-5. Control Instructions
Instruction
Clear Carry Bit
Mnemonic
CLC
CLI
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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11.5 Instruc tion Se t Sum m a ry
Table 11-6. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
M oed
H I N Z C
C
O
A
O
ii
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
dd
hh ll
ee ff
ff
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
2
3
4
5
4
3
Add without Carry
A ← (A) + (M)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
Logical AND
A ← (A) (M)
— — ↕ ↕ —
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
Arithmetic Shift Left (Same as LSL)
— — ↕ ↕ ↕
C
0
ff
b7
b7
b0
b0
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
INH
IX1
IX
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
22 rr
24 rr
3
3
3
3
3
3
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
BHS rel
Branch if Higher or Same
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Table 11-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
3
3
BIL rel
Branch if IRQ Pin Low
ii
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
dd
hh ll
ee ff
ff
Bit Test Accumulator with Memory Byte
(A) (M)
— — ↕ ↕ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
PC ← (PC) + 2 + rel ? Mn = 1
— — — — ↕
BRN rel
Branch Never
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
— — — — ↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
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Table 11-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
(A) – (M)
— — ↕ ↕ ↕
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
— — ↕ ↕
1
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
(X) – (M)
— — ↕ ↕ ↕
— — ↕ ↕ —
— — ↕ ↕ —
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory
Byte
A ← (A) (M)
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
— — ↕ ↕ —
dd
hh ll
ee ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
2
3
4
3
2
Unconditional Jump
PC ← Jump Address
— — — — —
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Table 11-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
hh ll
ee ff
ff
JSR opr
DIR
BD
CD
DD
ED
FD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
EXT
IX2
IX1
IX
Jump to Subroutine
— — — — —
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
X ← (M)
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕ ↕ —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
— — ↕ ↕ ↕
b7
b0
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
— — 0 ↕ ↕
0 — — — 0
— — ↕ ↕ ↕
— — — — —
b7
b0
ff
MUL
Unsigned Multiply
X : A ← (X) × (A)
INH
42
11
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
NOP
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) (M)
— — ↕ ↕ —
dd
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39
49
59
69
79
5
3
3
6
5
C
— — ↕ ↕ ↕
b7
b0
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Instruction Set
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Instruc tion Se t
Table 11-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
— — ↕ ↕ ↕
b7
b0
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕
INH
80
9
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— — ↕ ↕ —
— 0 — — —
— — ↕ ↕ —
STOP
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
— — ↕ ↕ ↕
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
TAX
Software Interrupt
— 1 — — —
— — — — —
INH
INH
83
97
10
2
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer Accumulator to Index Register
X ← (A)
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MC68HC05C9A — Rev. 4.0
Instruction Set
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Instruction Set
Instruction Set Summary
Table 11-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
ff
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for Negative or Zero
(M) – $00
— — ↕ ↕ —
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
A ← (X)
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR
dd
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
PCH Program counter high byte
PCL
REL
rel
rr
SP
X
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
dd rr
DIR
ee ff
EXT
ff
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
Index register
H
Z
Zero flag
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
Immediate value
Logical AND
ii
Immediate operand byte
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
:
↕
—
If
Concatenated with
Set or cleared
Not affected
N
n
Negative flag
Any bit
MC68HC05C9A — Rev. 4.0
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Instruc tion Se t
L
0
1
2
3
4
5
6
7
8
9
F
E
A
B
C
D
MS B
X
X
X
X
X
X
A
X
X
X
X
X
X
X
X
X
X
A
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
F
I
B TI
T
L
J
D
S
MJ P
S
S
CP X
A
D
AD
O
O RA
CMP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
A
4
X
4
X
4
X
4
X
4
X
4
X
4
X
5
X
4
X
4
X
4
X
4
X
3
X
6
X
4
5
4
X
5
I
E
B TI
I
T
L
S
D
S
MJ P
S
S
CP X
A
D
AD
O
O RA
CMP
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A
A
5
X
5
X
5
X
5
X
5
X
5
X
5
X
6
X
5
X
5
X
5
X
5
X
4
X
7
X
X
6
I
B TI
I
T
L
J
D
S
MJ P
S
S
CP X
A
D
AD
O
O RA
CMP
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
A
A
4
E
4
E
4
E
4
E
4
E
4
E
4
X
5
X
4
X
4
X
4
X
4
X
3
X
6
X
X
5
E
B TI
T
L
S
D
S
MJ P
S
S
CP X
A
D
AD
E
O
O RA
CMP
M
m
c
N
R
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
General Release Specification
MC68HC05C9A — Rev. 4.0
Instruction Set
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 12. Ele c tric a l Sp e c ific a tions
12.1 Conte nts
12.2 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
12.3 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
12.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
12.5 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .124
12.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.8 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . .131
MC68HC05C9A — Rev. 4.0
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Ele c tric a l Sp e c ific a tions
12.2 Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
VDD
–0.3 to +7.0
V
Supply Voltage
Input Voltage
VIN
VTST
VSS –0.3 to VDD + 0.3
VSS –0.3 to 2 x VDD + 0.3
V
Normal Operation
Self-Check Mode (IRQ Pin Only)
Current Drain Per Pin
I
25
mA
(Excluding V and V
)
SS
DD
TSTG
–65 to +150
°C
Storage Temperature Range
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 12.6 DC Electrical Characteristics for guaranteed
operating conditions.
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Electrical Specifications
Operating Temperature
12.3 Op e ra ting Te m p e ra ture
Characteristic
Symbol
Value
Unit
Operating Temperature Range
MC68HC05C9AP, FN, B, FB
MC68HC05C9ACP, CFN, CB, CFB
TL to TH
0 to +70
–40 to +85
TA
°C
12.4 The rm a l Cha ra c te ristic s
Characteristic
Symbol
Value
Unit
Thermal Resistance Plastic Dual-In-Line
(PDIP)
θJA
60
°C/W
Thermal Resistance Plastic Leaded Chip
Carrier (PLCC)
θJA
70
°C/W
θJA
θJA
95
60
°C/W
°C/W
Thermal Resistance Quad Flat Pack (QFP)
Thermal Resistance Plastic Shrink DIP (SDIP)
MC68HC05C9A — Rev. 4.0
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Ele c tric a l Sp e c ific a tions
12.5 Powe r Consid e ra tions
The average chip-junction temperature, TJ, in °C, can be obtained from:
TJ = TA + (PD × θJA) (1)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user determined)
For most applications PI/O « PINT and can be neglected.
The following is an approximate relationship between PD and TJ
(neglecting PJ):
PD = K ÷ (TJ + 273 °C)
(2)
(3)
Solving equations (1) and (2) for K gives:
2
K = PD × (TA + 273 °C) + θJA × (PD)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
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MC68HC05C9A — Rev. 4.0
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Electrical Specifications
Power Considerations
V
DD
R2
SEE TABLE
TEST
POINT
C
R1
(SEE TABLE)
(SEE TABLE)
VDD = 4.5 V
Pins
R1
R2
C
PA7–PA0
3.26 Ω
2.38 Ω
50 pF
PB7–PB0
PC7–PC0
PD5–PD0, PD7
VDD = 3.0 V
Pins
R1
R2
C
PA7–PA0
10.91 Ω
6.32 Ω
50 pF
PB7–PB0
PC7–PC0
PD5–PD0, PD7
Figure 12-1. Test Load
MC68HC05C9A — Rev. 4.0
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Ele c tric a l Sp e c ific a tions
12.6 DC Ele c tric a l Cha ra c te ristic s
(1)
Table 12-1. DC Electrical Characteristics (VDD = 5.0 Vdc)
Characteristic(2)
Symbol
Min
Typ
Max
Unit
Output Voltage
I
I
LOAD = 10.0 µA
LOAD = –10.0 µA
VOL
VOH
—
DD–0.1
—
—
0.1
—
V
V
Output High Voltage
(ILOAD = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0,
TCMP, PD7, PD0
(ILOAD = –1.6 mA) PD5–PD1
(ILOAD = –5.0 mA) PC7
VOH
VDD–0.8
—
—
—
—
—
—
V
V
V
V
DD–0.8
DD–0.8
Output Low Voltage
(ILOAD = 1.6 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD7, PD5–PD0, TCMP
VOL
—
—
—
—
0.4
0.4
(ILOAD = 10 mA) PC7
Input High Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
—
VDD
V
V
Input Low Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
0.2 × VDD
Supply Current (4.5–5.5 Vdc @ fOP = 2.1 MHz)
Run(3)
—
—
3.5
1.0
5.25
3.25
mA
mA
Wait(4)
Stop(5)
IDD
25 °C
0 to 70 °C
–40 to 85 °C
—
—
—
1.0
2.0
7.0
20.0
40.0
50.0
µA
µA
µA
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7–PB0 (Without Pullup)
PC7–PC0, PD7, PD5–PD0
IOZ
—
1.0
10
µA
Input Current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
Input Pullup Current(6)
PB7–PB0 (With Pullup)
IIN
IIN
—
5
0.5
—
1
µA
µA
60
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
COUT
CIN
—
—
—
—
12
8
pF
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85 °C, unless otherwise noted
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD
all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is
affected linearly by the OSC2 capacitance.
,
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V,
V
IH = VDD–0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
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Electrical Specifications
DC Electrical Characteristics
(1)
Table 12-2. DC Electrical Characteristics (VDD = 3.3 Vdc)
Characteristic(2)
Symbol
Min
Typ
Max
Unit
Output Voltage
I
I
LOAD = 10.0 µA
LOAD = –10.0 µA
VOL
VOH
—
DD–0.1
—
—
0.1
—
V
V
Output High Voltage
(ILOAD = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
TCMP, PD7, PD0
(ILOAD = –0.4 mA) PD5–PD1
(ILOAD = –1.5 mA) PC7
VOH
VDD–0.3
—
—
—
—
—
—
V
V
V
V
DD–0.3
DD–0.3
Output Low Voltage
(ILOAD = 0.4mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD7, PD5–PD0, TCMP
VOL
—
—
—
—
0.3
0.3
(ILOAD = 6 mA) PC7
Input High Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
—
VDD
V
V
Input Low Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
0.2 × VDD
Supply Current (3.0–3.6 Vdc @ fOP = 1.0MHz)
Run(3)
—
—
1.0
500
1.6
900
mA
µA
Wait(4)
Stop(5)
IDD
25°C
0 to 70 °C
–40 to 85 °C
—
—
—
1.0
1.0
2.5
8
16
20
µA
µA
µA
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7–PB0 (Without Pullup)
PC7–PC0, PD7, PD5–PD0
IOZ
—
1.0
10
µA
Input Current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
Input Pullup Current(6)
PB7–PB0 (With Pullup)
IIN
IIN
—
0.5
—
1
µA
µA
0.5
20
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
COUT
CIN
—
—
—
—
12
8
pF
NOTES:
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 to +85 °C, unless otherwise noted
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD
all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2
,
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD–0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
MC68HC05C9A — Rev. 4.0
General Release Specification
Electrical Specifications
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Ele c tric a l Sp e c ific a tions
VDD = 5.5 V
T = -40° to 85°
5.00 mA
4.00 mA
3.00 mA
2.00 mA
1.00 mA
)
D
S
50 µA
STOP IDD
(MHz)
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 12-2. Maximum Supply Current vs Internal Clock Frequency, VDD = 5.5 V
VDD = 3.6 V
T = -40° to 85°
1.50 mA
1.00 mA
500 µA
STOP IDD
0.5 MHz
1.0 MHz
Figure 12-3. Maximum Supply Current vs Internal Clock Frequency, VDD = 3.6 V
General Release Specification
MC68HC05C9A — Rev. 4.0
Electrical Specifications
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Electrical Specifications
Control Timing
12.7 Control Tim ing
(1)
Table 12-3. Control Timing (V = 5.0 V ±10%)
DD
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
fOSC
—
DC
4.2
4.2
MHz
Crystal
External Clock
Internal Operating Frequency (f
Crystal
External Clock
÷ 2)
OSC
fOP
—
DC
2.1
2.1
MHz
tCYC
tOXOV
tILCH
tRL
480
—
—
100
100
—
ns
ms
Cycle Time
Crystal Oscillator Startup Time
—
ms
Stop Recovery Start-up Time (Crystal Oscillator)
1.5
tCYC
RESET Pulse Width
Timer
Resolution
Input Capture Pulse Width
Input Capture Pulse Period
(2)
tRESL
tTH, tTL
tTLTL
4.0
—
—
—
tCYC
ns
tCYC
125
(3)
tILIH
tILIL
125
—
—
—
ns
tCYC
ns
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
(4)
tOH,tOL
90
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85 °C, unless otherwise noted
2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting
minimum factor in determining the timer resolution.
3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the
capture interrupt service routine plus 24 tCYC
4. The minimum tILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 19 tCYC
.
.
MC68HC05C9A — Rev. 4.0
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Ele c tric a l Sp e c ific a tions
(1)
Table 12-4. Control Timing (V = 3.3 V)
DD
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
fOSC
—
DC
2.0
2.0
MHz
Crystal
External Clock
Internal Operating Frequency (f
Crystal
External Clock
÷ 2)
OSC
fOP
—
DC
1.0
1.0
MHz
tCYC
tOXOV
tILCH
tRL
1000
—
—
100
100
—
ns
ms
Cycle Time
Crystal Oscillator Start-up Time
—
ms
Stop Recovery Start-up Time (Crystal Oscillator)
1.5
tCYC
RESET Pulse Width
Timer
Resolution
Input Capture Pulse Width
Input Capture Pulse Period
(2)
tRESL
tTH, tTL
tTLTL
4.0
—
—
—
tCYC
ns
tCYC
125
(3)
tILIH
tILIL
250
—
—
—
ns
tCYC
ns
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
(4)
tOH,tOL
200
NOTES:
1. VDD = 3.3Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 to +85 °C, unless otherwise noted
2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting
minimum factor in determining the timer resolution.
3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute
the capture interrupt service routine plus 24 tCYC
.
4. The minimum tILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 19 tCYC
.
tTH
tTL
*
tTLTL
*
*
TCAP PIN
* Refer to timer resolution data in Table 12-3 and Table 12-4.
Figure 12-4. TCAP Timing Relationships
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MC68HC05C9A — Rev. 4.0
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Electrical Specifications
Control Timing
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to
execute the interrupt service routine plus 19 tCYC cycles.
tILIH
IRQ1
.
.
.
NORMALLY
USED WITH
WIRED-OR
IRQN
CONNECTION
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low,
the next interrupt is recognized
Figure 12-5. External Interrupt Timing
OSC1
tRL
RESET
tILIH
IRQ2
IRQ3
4064 tCYC
INTERNAL
CLOCK
3FFE
3FFE
3FFE
3FFE
3FFE
3FFF4
NOTES:
RESET OR INTERRUPT
VECTOR FETCH
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
Figure 12-6. STOP Recovery Timing Diagram
MC68HC05C9A — Rev. 4.0
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Ele c tric a l Sp e c ific a tions
(NOTE 1)
V
DD
2
OSC1 PIN
4064 tCYC
INTERNAL
3
CLOCK
INTERNAL
3FFE
3FFE
3FFE
3FFE
3FFE
3FFE
3FFF
ADDRESS BUS3
INTERNAL
DATA BUS3
NEW
PCH
NEW
PCL
(NOTE 4)
RESET PIN
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
4. RESET outputs VOL during 4064 POR cycles.
Figure 12-7. Power-On Reset Timing Diagram
INTERNAL
1
CLOCK
INTERNAL
3FFE
3FFE
3FFE
3FFE
3FFF
NEW PC
ADDRESS BUS1
INTERNAL
DATA BUS1
NEW
PCH
NEW
PCL
OP
CODE
RESET2
tRL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-8. External Reset Timing
General Release Specification
MC68HC05C9A — Rev. 4.0
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Electrical Specifications
Serial Peripheral Interface Timing
12.8 Se ria l Pe rip he ra l Inte rfa c e Tim ing
Table 12-5. Serial Peripheral Interface Timing (VDD = 5.0 Vdc)*
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Cycle Time
Master
Slave
1
2
3
4
5
6
7
tCYC(M)
tCYC(S)
2.0
480
—
—
tCYC
ns
Enable Lead Time
Master
Slave
tLEAD(M)
tLEAD(S)
†
240
—
—
ns
ns
ns
ns
ns
ns
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
†
720
—
—
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
Slave Access Time (Time to Data Active from
High-Impedance State)
8
9
tA
0
120
240
ns
ns
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
Data Valid
10
11
12
Master (Before Capture Edge)
Slave (After Enable Edge)‡
tV(M)
tV(S)
0.25
—
—
240
tCYC(M)
ns
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
13
tFM
tFS
—
—
100
2.0
ns
µs
NOTES:
* VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = –40 to +85 °C, unless otherwise noted. Refer to Figure 12-7 and Figure 12-8 for
timing diagrams.
† Signal production depends on software.
‡ Assumes 200 pF load on all SPI pins
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Ele c tric a l Sp e c ific a tions
Table 12-6. Serial Peripheral Interface Timing (VDD = 3.3 Vdc)*
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
1.0
fOP
MHz
Cycle Time
Master
Slave
1
2
3
4
5
6
7
tCYC(M)
tCYC(S)
2.0
1.0
—
—
tCYC
µs
Enable Lead Time
Master
Slave
tLEAD(M)
tLEAD(S)
†
500
—
—
ns
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
†
1.5
—
—
ns
µs
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
720
400
—
—
ns
ns
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
720
400
—
—
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
200
200
—
—
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
200
200
—
—
Slave Access Time (Time to Data Active from
High-Impedance State)
8
9
tA
0
250
500
ns
ns
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
Data Valid
10
11
12
13
Master (Before Capture Edge)
Slave (After Enable Edge)‡
tV(M)
tV(S)
0.25
—
—
500
tCYC(M)
ns
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
200
2.0
ns
µs
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
200
2.0
ns
µs
NOTES:
* VDD = 3.3 Vdc ± 0.3 Vdc; VSS = 0 Vdc, TA = –40 to +85 °C. Refer to Figure 12-7 and Figure 12-8 for timing diagrams.
† Signal production depends on software
‡ Assumes 200 pF load on all SPI pins.
General Release Specification
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Electrical Specifications
Serial Peripheral Interface Timing
SS
(INPUT)
SS pin of master held high.
1
12
13
12
13
5
4
SCK (CPOL = 0)
(OUTPUT)
NOTE
4
5
12
SCK (CPOL = 1)
(OUTPUT)
NOTE
6
7
MISO
MSB IN
BIT 6–1
BIT 6–1
LSB IN
(INPUT)
10 (ref)
11
MASTER MSB OUT
10
11 (ref)
MOSI
(OUTPUT)
MASTER LSB OUT
12
13
NOTE:
This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS pin of master held high.
1
13
12
12
SCK (CPOL = 0)
(OUTPUT)
5
4
NOTE
NOTE
4
5
13
SCK (CPOL = 1)
(OUTPUT)
6
7
MISO
MSB IN
BIT 6–1
BIT 6–1
LSB IN
(INPUT)
10 (ref)
11
MASTER MSB OUT
10
11
MASTER LSB OUT
12
MOSI
(OUTPUT)
13
NOTE:
This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 12-9. SPI Master Timing Diagram
MC68HC05C9A — Rev. 4.0
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Ele c tric a l Sp e c ific a tions
SS
(INPUT)
1
13
12
3
SCK (CPOL = 0)
(INPUT)
5
4
4
5
2
SCK (CPOL = 1)
(INPUT)
8
12
11
13
SLAVE LSB OUT
11
9
MISO
(INPUT)
SLAVE MSB OUT
BIT 6–1
BIT 6–1
NOTE
10
6
7
MOSI
(OUTPUT)
MSB IN
LSB IN
NOTE:
Not defined but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
13
12
13
SCK (CPOL = 0)
(INPUT)
5
4
4
5
2
3
SCK (CPOL = 1)
(INPUT)
10
SLAVE MSB OUT
12
9
8
MISO
(OUTPUT)
NOTE
BIT 6–1
BIT 6–1
SLAVE LSB OUT
10
6
7
11
MOSI
(INPUT)
MSB IN
LSB IN
NOTE:
Not defined but normally LSB of character previously transmitted.
a) SPI Slave Timing (CPHA = 1)
Figure 12-10. SPI Slave Timing Diagram
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 13. Me c ha nic a l Sp e c ific a tions
13.1 Conte nts
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
13.3 40-Pin Plastic Dual In-Line (DIP)
Package (Case 711-03). . . . . . . . . . . . . . . . . . . . . . . . . . .136
13.4 42-Pin Plastic Shrink Dual In-Line (SDIP)
Package (Case 858-01). . . . . . . . . . . . . . . . . . . . . . . . . . .136
13.5 44-Lead Plastic Leaded Chip Carrier (PLCC)
(Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . .138
13.2 Introd uc tion
This section describes the dimensions of the plastic dual in-line package
(DIP), plastic shrink dual in-line package (SDIP), plastic leaded chip
carrier (PLCC), and quad flat pack (QFP) MCU packages. Package
dimensions available at time of this publication are provided in this
section. To make sure that you have the latest case outline
specifications, contact one of the following:
• Local Freescale Sales Office
MC68HC05C9A — Rev. 4.0
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Me c ha nic a l Sp e c ific a tions
13.3 40-Pin Pla stic Dua l In-Line (DIP) Pa c ka g e (Ca se 711-03)
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2.DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
40
21
20
B
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
B
C
D
F
51.69
13.72
3.94
0.36
1.02
52.45
14.22
5.08
0.56
1.52
2.035
0.540
0.155
0.014
0.040
2.065
0.560
0.200
0.022
0.060
L
A
C
N
2.54 BSC
0.100 BSC
G
H
J
K
L
J
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
K
SEATING
PLANE
M
H
G
F
D
15.24 BSC
0.600 BSC
0°
1°
0°
1°
M
N
0.51
1.02
0.020
0.040
Figure 13-1. 40-Pin Plastic DIP Package (Case 711-03)
13.4 42-Pin Pla stic Shrink Dua l In-Line (SDIP) Pa c ka g e (Ca se 858-01)
-A-
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
42
1
22
21
3. DIMENSION
FORMED PARALLEL.
4. DIMENSIONS AND
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
L
TO CENTER OF LEAD WHEN
-B-
A
B
DO NOT INCLUDE
MOLD
INCHES MILLIMETERS
MIN MAX MIN MAX
L
DIM
A
B
C
D
F
1.435 1.465 36.45 37.21
0.540 0.560 13.72 14.22
H
C
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
0.300 BSC
0.008 0.015
0.115 0.135
0.600 BSC
3.94
0.36
0.81
5.08
0.56
1.17
G
H
J
1.778 BSC
7.62 BSC
0.20
2.92
-T-
SEATING
PLANE
0.38
3.43
K
L
N
G
15.24 BSC
M
F
M
N
0° 15°
0.020 0.040
0°
0.51
15°
1.02
K
J 42 PL
0.25 (0.010M)
D 42 PL
S
B
0.25 (0.010M)
S
T A
T
Figure 13-2. 42-Pin Plastic SDIP Package (Case 858-01)
General Release Specification
MC68HC05C9A — Rev. 4.0
Mechanical Specifications
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Mechanical Specifications
44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
13.5 44-Le a d Pla stic Le a d e d Chip Ca rrie r (PLCC) (Ca se 777-02)
M
S
S
N
0.007(0.180)
T
L-M
B
D
-N-
YBRK
-M-
M
S
S
0.007(0.180)
T
L-M
N
U
Z
-L-
V
X
G1
W
D
44
1
S
S
S
N
0.010 (0.25)
T
L-M
VIEW D-D
M
M
S
S
S
S
A
R
0.007(0.180)
0.007(0.180)
T
T
L-M
L-M
N
N
M
S
S
N
0.007(0.180)
T
L-M
H
Z
J
K1
E
0.004 (0.10)
G
K
C
SEATING
PLANE
-T-
G1
F
VIEW S
S
S
N
S
M
S
S
0.010 (0.25)
T
L-M
0.007(0.180)
T
L-M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1.DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2.DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3.DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5.CONTROLLING DIMENSION: INCH.
6.THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETER-
DIM MIN
MAX
0.695
0.695
0.180
0.110
0.019
MIN
17.40
17.40
4.20
MAX
17.65
17.65
4.57
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
0.685
0.685
0.165
0.090
0.013
2.29
2.79
0.33
0.48
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.650
0.650
0.042
0.042
0.042
0.032
0.66
0.51
0.81
0.64
0.656
0.656
0.048
0.048
0.056
0.020
10°
16.51
16.51
1.07
1.07
1.07
16.66
16.66
1.21
1.21
1.42
0.50
10°
MINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7.DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940138). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
2°
2°
15.50
1.02
G1
K1
0.610
0.040
0.630
16.00
Figure 13-3. 44-Lead PLCC (Case 777-02)
MC68HC05C9A — Rev. 4.0
General Release Specification
Mechanical Specifications
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Me c ha nic a l Sp e c ific a tions
13.6 44-Le a d Qua d Fla t Pa c k (QFP) (Ca se 824A-01)
L
33
23
34
22
S
S
B
B
D
D
-A,B,D-
A
A
-A-
-B-
C
H
L
B
V
M
M
A
DETAIL A
DETAIL A
44
12
1
11
F
-D-
0.20 (0.008)
A
C
BASE METAL
M
S
A-B
S
D
0.05 (0.002A) -B
S
J
N
M
S
A-B
S
D
0.20 (0.008)
H
D
M
S
A-B
S
D
0.20 (0.008)
C
M
DETAIL C
SECTION B–B
E
C
DATUM
PLANE
-H-
-C-
SEATING
PLANE
0.01 (0.004)
H
G
M
MILLIMETERS
MIN MAX
INCHES
MIN MAX
NOTES:
DIM
A
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF
D
9.90 10.10
9.90 10.10
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
M
B
C
2.10
0.30
2.45
0.45
2.10
0.40
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
E
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
2.00
0.30
T
F
0.80 BSC
4. DATUMS ĆAĆ, ĆBĆ AND ĆDĆ TO BE DETERMINGED AT
DATUM PLANE ĆHĆ.
5. DIMENSIONS AND
SEATING PLANE ĆCĆ.
6. DIMENSIONS AND
H
Ċ
0.25
0.23
0.95
Ċ
0.010
DATUM
-H-
S
V
B
TO BE DETERMINED AT
PLANE
J
0.13
0.65
0.005 0.009
0.026 0.037
0.315 REF
R
K
A
DO NOT INCLUDE MOLD
8.00 REF
L
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS B
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE ĆHĆ.
7. DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
M
5°
0.13
10°
0.17
7°
5°
0.005 0.007
0°
7°
10°
A
AND
DO
N
Q
0°
0.13
K
R
0.30
0.005 0.012
0.510 0.530
Q
D
W
S
12.95 13.45
T
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE
0.13
Ċ
Ċ
0.005
0°
Ċ
Ċ
X
D
U
0°
DIMENSION AT MAXIMUM MATERIAL CONDITION.
V
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
12.95 13.45
0.40
Ċ
1.6 REF
0.510 0.530
0.016
Ċ
0.063 REF
W
DETAIL C
X
Figure 13-4. 44-Lead QFP (Case 824A-01)
General Release Specification
MC68HC05C9A — Rev. 4.0
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Se c tion 14. Ord e ring Inform a tion
14.1 Conte nts
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
14.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
14.2 Introd uc tion
This section contains ordering information for the available package
types.
MC68HC05C9A — Rev. 4.0
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Ord e ring Inform a tion
14.3 MC Ord e r Num b e rs
Table 14-1 shows the MC order numbers for the available package
types.
Table 14-1. MC Order Numbers
Temperature
Package Type
Order Number
Range
0 °C to 70°C
–40 °C to 85°C
0 °C to 70°C
–40 °C to 85°C
0 °C to 70°C
–40 °C to 85°C
0 °C to 70°C
–40 °C to 85°C
MC68HC05C9AP
MC68HC05C9ACP
MC68HC05C9AB
MC68HC05C9ACB
MC68HC05C9AFN
MC68HC05C9ACFN
MC68HC05C9AFB
MC68HC05C9ACFB
40-Pin Plastic Dual In-Line Package (DIP)
42-Pin Shrink Dual In-Line Package (SDIP)
44-Lead Plastic Leaded Chip Carrier (PLCC)
44-Pin Quad Flat Pack (QFP)
NOTES:
1. P = Plastic dual in-line package (PDIP)
2. B = Shrink dual in-line package (SDIP)
3. FN = Plastic-leaded chip carrier (PLCC)
4. FB = Quad flat pack (QFP)
General Release Specification
MC68HC05C9A — Rev. 4.0
Ordering Information
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Ap p e nd ix A. MC68HCL05C9A
A.1 Conte nts
A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
A.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .141
A.2 Introd uc tion
Appendix A introduces the MC68HCL05C9A, a low-power version of the
MC68HC05C9A. The technical data applying to the MC68HC05C9A
applies to the MC68HCL05C9 with the exceptions given in this
appendix.
A.3 DC Ele c tric a l Cha ra c te ristic s
The data in Table A-1 replaces the corresponding data in 12.3
Operating Temperature.
Table A-1. Low-Power Operating Temperature Range
Rating
Symbol
Value
Unit
Operating Temperature Range
MC68HCL05C9AP, FN, B, FB
T to T
0 to +70
L
H
T
°C
A
NOTES:
1. P = Plastic dual-in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. B = Shrink dual-in-line-package (SDIP)
4. FB = Quad flat pack (QFP)
The data in Table 12-1 and Table 12-2 (MC68HC05C9A DC electrical
characteristics data) applies to the MC68HCL05C9A with the exceptions
given in Table A-2, Table A-4, and Table A-6.
MC68HC05C9A — Rev. 4.0
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MC68HCL05C9A
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MC68HCL05C9A
Table A-2. Low-Power Output Voltage (VDD = 1.8-2.4 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(ILOAD = –0.1 mA) PA7–PA0, PB7–PB0, PC6–PC0,
TCMP, PD7, PD0
(ILOAD = –0.2 mA) PD5–PD1
(ILOAD = –0.75 mA) PC7
V
V
V
V
–0.3
–0.3
–0.3
—
—
—
—
—
—
V
OH
DD
DD
DD
Output Low Voltage
(ILOAD = 0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, PD7,
PD5–PD0, TCMP
(ILOAD = 2.0 mA) PC7
V
V
OL
—
—
—
—
0.3
0.3
Table A-3. Input Pullup Current (VDD = 1.8–2.4 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Pullup Current
PB7–PB0 (With Pullup)
I
0.45
1.5
6.5
µA
IN
Table A-4. Low-Power Output Voltage (VDD = 2.5-3.6 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(ILOAD = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
TCMP, PD7, PD0
(ILOAD = –0.4 mA) PD5–PD1
(ILOAD = –1.5 mA) PC7
V
V
V
V
– 0.3
– 0.3
– 0.3
—
—
—
—
—
—
V
OH
DD
DD
DD
Output Low Voltage
(ILOAD = 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0, PD7,
PD5–PD0, TCMP
(ILOAD = 5.0 mA) PC7
V
V
OL
—
—
—
—
0.3
0.3
Table A-5. Input Pullup Current (VDD = 2.5–3.6 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Pullup Current
PB7–PB0 (With Pullup)
I
1
5
16
µA
IN
General Release Specification
MC68HC05C9A — Rev. 4.0
MC68HCL05C9A
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Table A-6. Low-Power Supply Current
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Supply Current (4.5–5.5 Vdc @ f
Run
Wait
Stop
= 2.1 MHz)
= 1.0 MHz)
= 500 kHz)
= 500 kHz)
BUS
BUS
BUS
BUS
—
—
3.5
1.6
4.25
2.25
mA
mA
I
I
I
I
DD
DD
DD
DD
25 °C
—
—
1
2
15
25
µA
µA
0 °C to +70 °C (Standard)
Supply Current (2.4–3.6 Vdc @ f
(2)
Run
—
—
1.00
0.7
1.4
1.0
mA
mA
(3)
Wait
(4)
Stop
25 °C
—
—
1
1
5
10
µA
µA
0 °C to +70 °C (Standard)
Supply Current (2.5–3.6 Vdc @ f
Run
Wait
Stop
—
—
500
300
750
500
µA
µA
25 °C
—
—
1
1
5
10
µA
µA
0 °C to +70 °C (Standard)
Supply Current (1.8–2.4 Vdc @ f
Run
Wait
Stop
—
—
300
250
600
400
µA
µA
25 °C
—
—
1
1
2
5
µA
µA
0 °C to +70 °C (Standard)
NOTES:
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs,
Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2.
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is
affected linearly by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V,
V
IH = VDD–0.2 V.
MC68HC05C9A — Rev. 4.0
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MC68HCL05C9A
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MC68HCL05C9A
General Release Specification
MC68HC05C9A — Rev. 4.0
MC68HCL05C9A
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Ap p e nd ix B. MC68HSC05C9A
B.1 Conte nts
B.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
B.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .146
B.4 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
B.2 Introd uc tion
Appendix B introduces the MC68HSC05C9A, a high-speed version of
the MC68HC05C9A. The technical data applying to the MC68HC05C9A
applies to the MC68HSC05C9A with the exceptions given in this
appendix.
MC68HC05C9A — Rev. 4.0
General Release Specification
MC68HSC05C9A
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MC68HSC05C9A
B.3 DC Ele c tric a l Cha ra c te ristic s
The data in Table B-1 replaces the corresponding data in 12.3
Operating Temperature.
Table B-1. High-Speed Operating Temperature Range
Rating
Symbol
Value
Unit
Operating Temperature Range
MC68HSC05C9AP, FN, B, FB
MC68HSC05C9ACP, CFN, CB, CFB
T to T
0 to +70
–40 to +85
L
H
T
°C
A
NOTES:
1. P = Plastic dual-in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. C = Extended temperature range (–40 °C to +85 °C)
4. B = Shrink dual-in-line-package (SDIP)
5. FB = Quad flat pack (QFP)
The data in Table 12-1 and Table 12-2 (MC68HC05C9A DC electrical
characteristics data) applies to the MC68HSC05C9A with the
exceptions given in Table B-2.
General Release Specification
MC68HC05C9A — Rev. 4.0
MC68HSC05C9A
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MC68HSC05C9A
Table B-2. High-Speed Supply Current
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Supply Current (4.5–5.5 Vdc @ f
= 4.0 MHz)
BUS
(2)
Run
Wait
—
—
7.00
2.00
11.0
6.50
mA
mA
(3)
(4)
Stop
I
I
DD
25°C
—
—
—
1
1.0
7.0
20
40
50
µA
µA
µA
0 °C to 70 °C (Standard)
–40 °C to 85 °C (Standard)
Supply Current (2.4–3.6 Vdc @ f
= 2.0 MHz)
BUS
(2)
Run
—
—
2.50
1.00
4.00
2.00
mA
mA
(3)
Wait
(4)
Stop
DD
25 °C
—
—
—
1
1.0
2.5
8
16
20
µA
µA
µA
0 °C to 70 °C (Standard)
–40 °C to 85 °C (Standard)
NOTES:
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs,
Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2.
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is
affected linearly by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V,
V
IH = VDD–0.2 V.
Table B-3. Input Pullup Current
Characteristic
Symbol
Min
Typ
Max
Unit
Input Pullup Current (V = 4.5–5.5 V)
PB7–PB0 (With Pullup)
DD
I
I
5
15
60
µA
IN
IN
Input Pullup Current (V = 2.4–3.6 V)
DD
1
5
16
µA
PB7–PB0 (With Pullup)
MC68HC05C9A — Rev. 4.0
General Release Specification
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B.4 Control Tim ing
The data in Table 12-3, Table 12-4, Table 12-5, and Table 12-6
(MC68HC05C9A control timing data) applies to the MC68HSC05C9A
with the exceptions given in Table B-4, Table B-5, Table B-6, and
Table B-7.
Table B-4. High-Speed Control Timing (VDD = 4.5–5.5 Vdc)
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
f
—
dc
8.2
8.2
MHz
OSC
Internal Operating Frequency (f
Crystal
External Clock
÷ 2)
OSC
—
dc
f
4.1
4.1
MHz
OP
Cycle Time
t
244
—
100
100
—
ns
ms
ms
tCYC
CYC
Crystal Oscillator Startup Time
Stop Recovery Startup Time
RESET Pulse Width
Timer
Resolution
Input Capture Pulse Width
Input Capture Pulse Width
t
OXOV
t
ILCH
t
1.5
4.0
RL
(1)
t
—
—
—
tCYC
ns
tCYC
RESL
t
or t
64
TH
TL
(2)
t
l
THT
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
t
64
—
—
—
ns
tCYC
ns
ILIH
(3)
t
ILIL
t
or t
50
OH
OL
NOTES:
1. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tCYC
3. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tCYC
.
.
General Release Specification
MC68HC05C9A — Rev. 4.0
MC68HSC05C9A
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MC68HSC05C9A
Table B-5. High-Speed Control Timing (VDD = 2.4–3.6 Vdc)
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fOSC
—
dc
4.2
4.2
MHz
Internal Operating Frequency (f
Crystal
External Clock
÷ 2)
OSC
—
dc
fOP
2.1
2.1
MHz
Cycle Time
tCYC
tOXOV
tILCH
480
—
—
100
100
—
ns
ms
ms
Crystal Oscillator Startup Time
Stop Recovery Startup Time
RESET Pulse Width
Timer
Resolution
Input Capture Pulse Width
Input Capture Pulse Width
—
t
1.5
t
RL
CYC
(1)
t
4.0
—
—
—
t
t
RESL
CYC
ns
t
or t
125
TH
TL
(2)
tTHTL
tILIH
tILIL
CYC
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
125
—
—
—
ns
(3)
t
CYC
OSC1 Pulse Width
tOH or t
90
ns
OL
1. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tCYC
3. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tCYC
.
.
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Table B-6. High-Speed Control Timing (VDD = 4.5–5.5 Vdc)
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
4.1
fOP
MHz
Cycle Time
Master
Slave
1
2
3
4
5
6
7
tCYC(M)
tCYC(S)
2.0
244
—
—
tCYC
ns
Enable Lead Time
Master
Slave
tLEAD(M)
tLEAD(S)
†
122
—
—
ns
ns
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
†
366
—
—
ns
ns
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
166
93
—
—
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
166
93
—
—
ns
ns
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
49
49
—
—
ns
ns
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
49
49
—
—
ns
ns
Slave Access Time (Time to Data Active from
High-Impedance State)
8
9
tA
0
61
ns
ns
Slave Disable Time (Hold Time to High-Impedance
State)
tDIS
—
122
Data Valid
10
11
12
13
Master (Before Capture Edge)
Slave (After Enable Edge)‡
tV(M)
tV(S)
0.25
—
—
122
tCYC(M)
ns
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
50
1.0
ns
µs
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
50
1.0
ns
µs
†
‡
Signal production depends on software.
Assumes 200 pF load on all SPI pins.
General Release Specification
MC68HC05C9A — Rev. 4.0
MC68HSC05C9A
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MC68HSC05C9A
Table B-7. High-Speed SPI Timing (VDD = 2.4–3.6 Vdc)
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Cycle Time
Master
Slave
1
2
3
4
5
6
7
tCYC(M)
tCYC(S)
2.0
480
—
—
tCYC
ns
Enable Lead Time
Master
Slave
tLEAD(M)
tLEAD(S)
†
240
—
—
ns
ns
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
†
720
—
—
ns
ns
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
ns
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
ns
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
ns
ns
Slave Access Time (Time to Data Active from
High-Impedance State)
8
9
tA
0
120
240
ns
ns
Slave Disable Time (Hold Time to High-Impedance
State)
tDIS
—
Data
10
11
12
13
Master (Before Capture Edge)
Slave (After Enable Edge)‡
tV(M)
tV(S)
0.25
—
—
240
tCYC(M)
ns
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
µs
†
‡
Signal production depends on software.
Assumes 200 pF load on all SPI pins.
MC68HC05C9A — Rev. 4.0
General Release Specification
MC68HSC05C9A
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MC68HSC05C9A
General Release Specification
MC68HC05C9A — Rev. 4.0
MC68HSC05C9A
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Ap p e nd ix C. Se lf-Che c k Mod e
C.1 Conte nts
C. 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
C.3 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
C.3.1
C.3.2
Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Self-Check Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
C.2 Introd uc tion
This appendix describes the self-check mode.
MC68HC05C9A — Rev. 4.0
General Release Specification
Self-Check Mode
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Se lf-Che c k Mod e
C.3 Se lf-Che c k Mod e
Self-check mode is entered upon the rising edge of RESET if the IRQ pin
is at VTST and the TCAP pin is at logic one.
C.3.1 Se lf-Che c k Te sts
The self-check ROM at mask ROM location $3F00–$3FEF determines
if the MCU is functioning properly.The following tests are performed:
1. I/O — Functional test of ports A, B, and C
2. RAM — Counter test for each RAM byte
3. Timer — Test of counter register and OCF bit
4. SCI — Transmission test: Checks for RDRF, TDRE, TC, and FE
flags
5. ROM — Exclusive OR with odd ones parity result
6. SPI — Transmission test: Checks for SPIF and WCOL flags
The self-check circuit is shown in Figure C-1.
General Release Specification
MC68HC05C9A — Rev. 4.0
Self-Check Mode
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Self-Check Mode
V
V
DD
DD
10 V
V
DD
MC34064
MC68HC05C9A
4.7 KΩ
RESET
V
DD
1
2
3
4
5
40
39
38
37
36
IRQ
NC
OSC1
OSC2
TCAP
PD7
4 MHz
PA7
PA6
10 MΩ
20 pF
V
DD
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
TCMP
6
35
34
33
32
31
30
29
28
20 pF
10K
PD5/SS
7
1 MΩ
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
8
9
10
11
12
13
PB2
PB3
PC1
PC2
14
15
27
26
CMOS
BUFFER
(MC74HC125)
PB4
PB5
PB6
PB7
PC3
16
17
18
19
20
25
24
PC4
PC5
PC6
PC7
23
22
21
V
SS
V
DD
NOTES:
1. VDD = 5.0 V
2. TCMP = NC
Figure C-1. Self-Check Circuit Schematic
MC68HC05C9A — Rev. 4.0
General Release Specification
Self-Check Mode
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Se lf-Che c k Mod e
C.3.2 Se lf-Che c k Re sults
Table C-1 shows the LED codes that indicate self-check test results.
Table C-1. Self-Check Circuit LED Codes
PC3
Off
Off
Off
Off
Off
Off
PC2
On
On
On
Off
Off
Off
PC1
On
Off
Off
On
On
Off
PC0
Off
On
Off
On
Off
On
Remarks
I/O Failure
RAM Failure
Timer Failure
SCI Failure
ROM Failure
SPI Failure
No Failure
Flashing
All Others
Device Failure
Perform the following steps to activate the self-check tests:
1. Apply 10 V (2 x VDD) to the IRQ pin.
2. Apply a logic one to the TCAP pin.
3. Apply a logic zero to the RESET pin.
The self-check tests begin on the rising edge of the RESET pin.
RESET must be held low for 4064 cycles after power-on reset (POR), or
for a time, t , for any other reset. (For the t value, see Table 12-3.)
RL
RL
General Release Specification
MC68HC05C9A — Rev. 4.0
Self-Check Mode
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C9A
Ap p e nd ix D. M68HC05Cx Fa m ily Fe a ture Com p a risons
D.1 Conte nts
Table D-1. M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . .158
D.2 Introd uc tion
Refer to Table D-1 for a comparison of the features for all the
M68HC05C Family members.
MC68HC05C9A — Rev. 4.0
General Release Specification
M68HC05Cx Family Feature Comparisons
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M68HC05Cx Fa m ily Fe a ture Com p a risons
O
A
A
A
A
—
O
Y
Y
Y
M
M
M
M OR
H
$ 3F DF
O
C
T
1
$ F3 F 0 -1
7
P
B
T
M
C
(
C
T
(
S
S
S
S
S
1
(
P
W
O
A
A
A
—
N
N
N
NO
E
Y
$
A
7
W
O
C
T
1
$
P
B
T
M
P
(
T
S
S
S
1
O
A
A
—
N
NO
Y
Y
E
Y
C9A
H
MA S K
$ 3F DF
W
O
C
T
1
O
$
P
B
T
M
C
P
(
S
S
S
1
O
R
A
A
A
—
C
N
N
N
NO
E
Y
General Release Specification
MC68HC05C9A — Rev. 4.0
M68HC05Cx Family Feature Comparisons
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