MC7447AVS867NB_技术文档

MPC7447AEC

Rev. 5, 01/2006

Freescale Semiconductor

Technical Data

MPC7447A

RISC Microprocessor

Hardware Specifications

Contents

This document is primarily concerned with the PowerPC™

MPC7447A; however, unless otherwise noted, all

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

information here also applies to the MPC7447. The

MPC7447A is an implementation of the PowerPC

3. Comparison with the MPC7447, MPC7445, and

MPC7441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Electrical and Thermal Characteristics . . . . . . . . . . . . 9

6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 27

9. System Design Information . . . . . . . . . . . . . . . . . . . 34

10. Document Revision History . . . . . . . . . . . . . . . . . . . 52

11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 52

microprocessor family of reduced instruction set computer

(RISC) microprocessors. This document describes pertinent

electrical and physical characteristics ofthe MPC7447A. For

functional characteristics of the processor, refer to the

MPC7450 RISC Microprocessor Family Reference Manual.

To locate any published updates for this document, refer to

the Freescale website located at

http://www.freescale.com.

1 Overview

The MPC7447A is the fifth implementation of the

fourth-generation (G4) microprocessors from Freescale. The

MPC7447A implements the full PowerPC 32-bit

architecture and is targeted at networking and computing

systems applications. The MPC7447A consists of a

processor core and a 512-Kbyte L2.

Figure 1 shows a block diagram of the MPC7447A. The core

is a high-performance superscalar design supporting a

double-precision floating-point unit and a SIMD multimedia

unit. The memory storage subsystem supports the MPX bus

protocol and a subset of the 60x bus protocol to main

memory and other system resources.

Overview

Figure 1. MPC7447A Block Diagram

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

2

Freescale Semiconductor

Features

NOTE

The MPC7447A is a footprint-compatible, drop-in replacement in an

MPC7447 application if the core power supply is 1.3 V.

2 Features

This section summarizes features of the MPC7447A implementation of the PowerPC architecture.

Major features of the MPC7447A are as follows:

•

High-performance, superscalar microprocessor

— Up to four instructions can be fetched from the instruction cache at a time.

— Up to 12 instructions can be in the instruction queue (IQ).

— Up to 16 instructions can be at some stage of execution simultaneously.

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

•

Eleven independent execution units and three register files

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, a fetch that hits the BTIC provides

the first four instructions in the target stream.

– 2048-entry branch history table (BHT) with 2 bits per entry for four levels of

prediction—not taken, strongly not taken, taken, and strongly taken

– Up to three outstanding speculative branches

– Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream.

– Eight-entry link register stack to predict the target address of Branch Conditional to Link

Register (bclr) instructions

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions.

– IU2 executes miscellaneous instructions including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions.

— Five-stage FPU and a 32-entry FPR file

– Fully IEEE 754-1985–compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64-bit FPRs for single- or double-precision operands

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

3

Features

— Four vector units and 32-entry vector register file (VRs)

– Vector permute unit (VPU)

– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as

vector add instructions (for example, vaddsbs, vaddshs, and vaddsws).

– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as

vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and

vmladduhm).

– Vector floating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, floating-point, and vector instruction load/store traffic

– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream

operations

– 3-cycle GPR and AltiVec load latency (byte, half word, word, vector) with 1-cycle

throughput

– 4-cycle FPR load latency (single, double) with 1-cycle throughput

– No additional delay for misaligned access within double-word boundary

– Dedicated adder calculates effective addresses (EAs)

– Supports store gathering

– Performs alignment, normalization, and precision conversion for floating-point data

– Executes cache control and TLB instructions

– Performs alignment, zero padding, and sign extension for integer data

– Supports hits under misses (multiple outstanding misses)

– Supports both big- and little-endian modes, including misaligned little-endian accesses

•

Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle. Instruction dispatch requires the following:

— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2.

— A maximum of three instructions can be dispatched to the issue queues per clock cycle.

— Space must be available in the CQ for an instruction to dispatch. (This includes instructions that

are assigned a space in the CQ but not in an issue queue.)

Rename buffers

— 16 GPR rename buffers

— 16 FPR rename buffers

— 16 VR rename buffers

Dispatch unit

•

— Decode/dispatch stage fully decodes each instruction

Completion unit

— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all

instructions ahead of it have been completed, the instruction has finished execution, and no

exceptions are pending.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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Freescale Semiconductor

Features

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

— Tracks unresolved branches and flushes instructions after a mispredicted branch

— Retires as many as three instructions per clock cycle

•

Separate on-chip L1 instruction and data caches (Harvard architecture)

— 32-Kbyte, eight-way set-associative instruction and data caches

— Pseudo least-recently-used (PLRU) replacement algorithm

— 32-byte (eight-word) L1 cache block

— Physically indexed/physical tags

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— Instruction cache can provide four instructions per clock cycle; data cache can provide four

words per clock cycle

— Caches can be disabled in software.

— Caches can be locked in software.

— MESI data cache coherency maintained in hardware

— Separate copy of data cache tags for efficient snooping

— Parity support on cache and tags

— No snooping of instruction cache except for icbi instruction

— Data cache supports AltiVec LRU and transient instructions

— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word

forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical

double-word forwarding.

•

Level 2 (L2) cache interface

— On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache

— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

— A total 9-cycle load latency for an L1 data cache miss that hits in L2

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— 64-byte, two-sectored line size

— Parity support on cache

Separate memory management units (MMUs) for instructions and data

— 52-bit virtual address, 32- or 36-bit physical address

— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments

— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and

memory coherency enforced/memory coherency not enforced on a page or block basis

— Separate IBATs and DBATs (eight each) also defined as SPRs

— Separate instruction and data translation lookaside buffers (TLBs)

– Both TLBs are 128-entry, two-way set-associative, and use an LRU replacement algorithm.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

5

Features

– TLBs are hardware- or software-reloadable (that is, a page table search is performed in

hardware or by system software on a TLB miss).

•

Efficient data flow

— Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits.

— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs.

— The L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache.

— As many as eight outstanding out-of-order cache misses are allowed between the L1 data cache

and the L2 bus.

— As many as 16 out-of-order transactions can be present on the MPX bus.

— Store merging for multiple store misses to the same line. Only coherency action taken

(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).

— Three-entry finished store queue and five-entry completed store queue between the LSU and

the L1 data cache

— Separate additional queues for efficient buffering of outbound data (such as castouts and

write-through stores) from the L1 data cache and L2 cache

•

Multiprocessing support features include the following:

— Hardware-enforced, MESI cache coherency protocols for data cache

— Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

Power and thermal management

— A new dynamic frequency switching (DFS) feature allows processor core frequency to be

halved through software to reduce power consumption.

— The following three power-saving modes are available to the system:

– Nap—Instruction fetching is halted. Only the clocks for the time base, decrementer, and

JTAG logic remain running. The part goes into the doze state to snoop memory operations

on the bus and then back to nap using a QREQ/QACK processor-system handshake

protocol.

– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the

PLL in a locked and running state. All internal functional units are disabled.

– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system

can then disable the SYSCLK source for greater system power savings. Power-on reset

procedures for restarting and relocking the PLL must be followed upon exiting the deep

sleep state.

— Instruction cache throttling provides control of instruction fetching to limit device temperature.

— A new temperature diode can determine the temperature of the microprocessor.

— Support for core voltage derating to further reduce power consumption

Performance monitor can be used to help debug system designs and improve software efficiency.

In-system testability and debugging features through JTAG boundary-scan capability

Testability

•

— LSSD scan design

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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Comparison with the MPC7447, MPC7445, and MPC7441

— IEEE 1149.1 JTAG interface

— Array built-in self test (ABIST)—factory test only

Reliability and serviceability

•

— Parity checking on system bus

— Parity checking on the L1 and L2 caches

3 Comparison with the MPC7447, MPC7445, and

MPC7441

Table 1 compares the key features of the MPC7447A with the key features of the earlier MPC7447,

MPC7445, and MPC7441. All are based on the MPC7450 RISC microprocessor and are very similar

architecturally. The MPC7447A is identical to the MPC7447 but includes the DFS and temperature diode

features.

Table 1. Microarchitecture Comparison

Microarchitectural Specs

MPC7447A

MPC7447

MPC7445

MPC7441

Basic Pipeline Functions

Logic inversions per cycle

18

5

Pipeline stages up to execute

Total pipeline stages (minimum)

Pipeline maximum instruction throughput

7

3 + branch

Pipeline Resources

Instruction buffer size

12

16

Completion buffer size

Renames (integer, float, vector)

16, 16, 16

Maximum Execution Throughput

SFX

3

Vector

2 (any 2 of 4 units)

1

Scalar floating-point

Out-of-Order Window Size in Execution Queues

1 entry × 3 queues

SFX integer units

Vector units

In order, 4 queues

In order

Scalar floating-point unit

Branch Processing Resources

Prediction structures

BTIC, BHT, link stack

128-entry, 4-way

BTIC size, associativity

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

7

Comparison with the MPC7447, MPC7445, and MPC7441

Table 1. Microarchitecture Comparison (continued)

Microarchitectural Specs

MPC7447A

MPC7447

MPC7445

MPC7441

BHT size

2K-entry

Link stack depth

8

3

1

6

Unresolved branches supported

Branch taken penalty (BTIC hit)

Minimum misprediction penalty

Execution Unit Timings (Latency-Throughput)

Aligned load (integer, float, vector)

Misaligned load (integer, float, vector)

L1 miss, L2 hit latency

3-1, 4-1, 3-1

4-2, 5-2, 4-2

9 data/13 instruction

SFX (aDd Sub, Shift, Rot, Cmp, logicals)

Integer multiply (32 × 8, 32 × 16, 32 × 32)

Scalar float

1-1

3-1, 3-1, 4-2

5-1

VSFX (vector simple)

1-1

VCFX (vector complex)

4-1

VFPU (vector float)

4-1

VPER (vector permute)

2-1

MMUs

TLBs (instruction and data)

Tablewalk mechanism

128-entry, 2-way

Hardware + software

Instruction BATs/data BATs

8/8

L1 I Cache/D Cache Features

8/8

4/4

Size

32K/32K

8-way

Way

Associativity

Locking granularity

Parity on Instruction cache

Parity on data cache

Number of data cache misses (load/store)

Data stream touch engines

Word

Byte

5/1

4 streams

On-Chip Cache Features

Cache level

L2

Size/associativity

Access width

512-Kbyte/8-way

256-Kbyte/8-way

256 bits

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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Freescale Semiconductor

General Parameters

MPC7441

Table 1. Microarchitecture Comparison (continued)

Microarchitectural Specs MPC7447A MPC7447

Number of 32-byte sectors/line

MPC7445

2

Parity

Byte

Thermal Control

Dynamic frequency switching (DFS)

Thermal diode

Yes

No

4 General Parameters

The following list is a summary of the general parameters of the MPC7447A:

Technology

Die size

0.13-μm CMOS, nine-layer metal

8.51 mm × 9.86 mm

48.6 million

Transistor count

Logic design

Packages

Fully-static

Surface mount 360 ceramic ball grid array (HCTE)

Surface mount RoHS-compliant 360 ceramic ball grid array (HCTE)

Surface mount 360 ceramic land grid array (HCTE)

1.3 V ± 50 mV DC (nominal), or

1.2 V ± 50 mV DC (derated)

Core power supply

I/O power supply

1.8 V ± 5% DC, or

2.5 V ± 5% DC

5 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC7447A.

5.1

DC Electrical Characteristics

The tables in this section describe the MPC7447A DC electrical characteristics. Table 2 provides the

absolute maximum ratings.

1

Table 2. Absolute Maximum Ratings

Characteristic

Symbol Maximum Value Unit Notes

Core supply voltage

V

–0.3 to 1.60

–0.3 to 1.95

–0.3 to 2.7

V

2

DD

PLL supply voltage

AV

OV

2

DD

in

Processor bus supply voltage

BVSEL = 0

3, 4

3, 5

6, 7

—

BVSEL = HRESET or OV

Processor bus

DD

Input voltage

V

–0.3 to OV + 0.3

DD

JTAG signals

–0.3 to OV + 0.3

DD

in

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

9

Electrical and Thermal Characteristics

Table 2. Absolute Maximum Ratings (continued)

1

Characteristic

Symbol Maximum Value Unit Notes

–55 to 150 °C

Storage temperature range

T

—

stg

Notes:

1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: V /AV must not exceed OV by more than 1.0 V during normal operation; this limit may be exceeded for a

DD

maximum of 20 ms during the power-on reset and power-down sequences.

3. Caution: OV must not exceed V /AV by more than 2.0 V during normal operation; this limit may be exceeded for a

DD

maximum of 20 ms during the power-on reset and power-down sequences.

4. BVSEL must be set to 0, such that the bus is in 1.8-V mode.

5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.

6. Caution: V must not exceed OV by more than 0.3 V at any time including during power-on reset.

in

DD

7. V may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

in

Figure 2 shows the undershoot and overshoot voltage on the MPC7447A.

OV + 20%

DD

OV + 5%

DD

OV

DD

V

IH

V

IL

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

of t

SYSCLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7447A provides several I/O voltages to support both compatibility with existing systems and

migration to future systems. The MPC7447A core voltage must always be provided at the nominal voltage

(see Table 4) or at the supported derated voltage (see Section 5.3, “Voltage and Frequency Derating”). The

input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the

negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied

to the OV power pins. Table 3 provides the input threshold voltage settings. Because these settings may

DD

change in future products, it is recommended that BVSEL be configured using resistor options, jumpers,

or some other flexible means, with the capability to reconfigure the termination of this signal in the future

if necessary.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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Freescale Semiconductor

Electrical and Thermal Characteristics

Table 3. Input Threshold Voltage Settings

BVSEL Signal

Processor Bus Input Threshold is Relative to:

Notes

0

1.8 V

Not available

2.5 V

1, 2

1

¬HRESET

HRESET

1

2.5 V

1

Notes:

1. Caution: The input threshold selection must agree with the OV voltages supplied. See notes in Table 2.

DD

2. If used, pull-down resistors should be less than 250 Ω.

Table 4 provides the recommended operating conditions for the MPC7447A.

NOTE

Table 4 describes the nominal operating conditions of the device. For

information regarding the operation of the device at supported derated core

voltage conditions, see Section 5.3, “Voltage and Frequency Derating.”

1

Table 4. Recommended Operating Conditions

Recommended Value

Characteristic

Symbol

Unit

Notes

Minimum Maximum

Core supply voltage

PLL supply voltage

V

1.3 V 50 mV

1.8 V 5%

V

3

DD

AV

OV

2, 3

DD

in

Processor bus supply voltage BVSEL = 0

BVSEL = HRESET or OV

2.5 V 5%

DD

Input voltage

Processor bus

JTAG signals

V

GND

0

OV

V

DD

in

Die-junction temperature

T

105

°C

j

Notes:

1. These are the recommended and tested operating conditions. In addition, these devices also support voltage

derating; see Section 5.3, “Voltage and Frequency Derating.” Proper device operation outside of these conditions

and those specified in Section 5.3 is not guaranteed.

2. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the

voltage at the AV pin, which may be reduced from V by the filter.

DD

3. V and AV may be reduced in order to reduce power consumption if further maximum core frequency

DD

constraints are observed. See Section 5.3, “Voltage and Frequency Derating,” for specific information.

Table 5 provides the package thermal characteristics for the MPC7447A.

1

Table 5. Package Thermal Characteristics

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board

Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board

R

26

19

20

°C/W

2, 3

2, 4

JA

θ

R

JMA

θ

R

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

11

Electrical and Thermal Characteristics

Table 5. Package Thermal Characteristics (continued)

1

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board

R

16

10

°C/W

2, 4

5

JMA

θ

Junction-to-board thermal resistance

Junction-to-case thermal resistance

Notes:

R

JB

θ

R

< 0.1

6

JC

θ

1. Refer to Section 9.8, “Thermal Management Information,” for details about thermal management.

2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.

3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

4. Per JEDEC JESD51-6 with the board horizontal.

5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

6. This is the thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of R

for the part is less than 0.1°C/W.

θJC

Table 6 provides the DC electrical characteristics for the MPC7447A.

Table 6. DC Electrical Specifications

At recommended operating conditions. See Table 4.

Nominal

Characteristic

Bus

Voltage

Symbol

Min

Max

Unit Notes

1

Input high voltage

(all inputs)

1.8

2.5

1.8

2.5

—

V

OV × 0.65

OV + 0.3

V

2

IH

DD

1.7

–0.3

—

OV + 0.3

DD

Input low voltage

(all inputs)

V

OV × 0.35

2, 6

2, 3

IL

DD

0.7

Input leakage current,

I

µA

in

V

= OV

= GND

30

– 30

in

DD

High-impedance (off-state) leakage current,

—

I

—

µA

2, 3, 4

TSI

V

= OV

= GND

30

– 30

in

DD

Output high voltage @ I

= –5 mA

1.8

2.5

1.8

2.5

V

OV – 0.45

—

V

OH

DD

1.8

—

Output low voltage @ I = 5 mA

V

0.45

0.6

OL

—

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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Electrical and Thermal Characteristics

Table 6. DC Electrical Specifications (continued)

At recommended operating conditions. See Table 4.

Nominal

Bus

Voltage

Characteristic

Symbol

Min

Max

Unit Notes

1

Capacitance,

= 0 V, f = 1 MHz

All other inputs

C

—

8.0

pF

5

in

V

in

Notes:

1. Nominal voltages; see Table 4 for recommended operating conditions.

2. For processor bus signals, the reference is OV

DD

3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals

4. The leakage is measured for nominal OV and V , or both OV and V must vary in the same direction (for

DD

example, both OV and V vary by either +5% or –5%).

DD

5. Capacitance is periodically sampled rather than 100% tested.

6. Excludes signals with internal pullups: BVSEL, LSSD_MODE, TDI, TMS, and TRST.

Table 7 provides the power consumption for the MPC7447A. For information regarding power

consumption when dynamic frequency switching is enabled, see Section 9.8.5, “Dynamic Frequency

Switching (DFS).”

NOTE

The power consumption information in this table applies when the device is

operated at the nominal core voltage indicated in Table 4. For power

consumption at derated core voltage conditions, see Section 5.3, “Voltage

and Frequency Derating.”

Table 7. Power Consumption for MPC7447A

Processor (CPU) Frequency

Unit

Notes

5

1000

1267

1333

1420 MHz

Full-Power Mode

Typical

16.0

23.0

18.3

26.0

18.0

21.0

30.0

W

1, 2

1, 3

Maximum

25.0

Nap Mode

Typical

4.1

3.3

4.1

W

1, 2

Sleep Mode

4.1

Deep Sleep Mode (PLL Disabled)

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

13

Electrical and Thermal Characteristics

Table 7. Power Consumption for MPC7447A (continued)

Processor (CPU) Frequency

Unit

Notes

5

1000

1267

1333

1420 MHz

Typical

4.1

4.0

3.2

4.0

W

1, 2

Notes:

1. These values specify the power consumption for the core power supply (V ) at nominal voltage and apply

DD

to all valid processor bus frequencies and configurations. The values do not include I/O supply power (OV

)

DD

or PLL supply power (AV ). OV power is system dependent but is typically < 5% of V power. Worst

DD

case power consumption for AV < 3 mW.

DD

2. Typical power is an average value measured at the nominal recommended V (see Table 4) and 65°C while

DD

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

3. Maximum power is the average measured at nominal V and maximum operating junction temperature (see

DD

Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the

execution units maximally busy.

4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep

mode. As a result, power consumption for this mode is not tested.

5. Power consumption for these devices is artificially constrained during screening to assure lower power

consumption than other speed grades.

5.2

AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7447A. After fabrication, functional

parts are sorted by maximum processor core frequency as shown in Section 5.2.1, “Clock AC

Specifications,” and tested for conformance to the AC specifications for that frequency. The processor core

frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals,

and can be dynamically modified using dynamic frequency switching (DFS). Parts are sold by maximum

processor core frequency; see Section 11, “Ordering Information,” for information on ordering parts. DFS

is described in Section 9.8.5, “Dynamic Frequency Switching (DFS).”

5.2.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3 and represents the tested

operating frequencies of the devices. The maximum system bus frequency, f , given in Table 8, is

SYSCLK

considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK

frequency for any application of the MPC7447A will be a function of the AC timings of the MPC7447A,

the AC timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so

forth, and may be less than the value given in Table 8.

NOTE

The core frequency information in this table applies when operating the

device at the nominal core voltage indicated in Table 4. For core frequency

specifications at derated core voltage conditions, see Section 5.3, “Voltage

and Frequency Derating.”

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

14

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Maximum Processor Core Frequency

Symbol 1000 MHz 1267 MHz 1333 MHz 1420 MHz Unit Notes

Characteristic

Min Max Min Max Min Max Min Max

Processor core frequency

VCO frequency

f

600 1000 600 1267 600 1333 600 1420 MHz 1, 8, 9

1200 2000 1200 2533 1200 2667 1200 2840 MHz 1, 9

core

f

VCO

SYSCLK frequency

f

t

33

6.0

—

167

30

33

6.0

—

167

30

33

6.0

—

167

30

33

6.0

—

167 MHz 1, 2, 8

SYSCLK

SYSCLK cycle time

30

1.0

60

ns

%

2

3

4

SYSCLK rise and fall time

SYSCLK duty cycle measured at

t

, t

1.0

60

1.0

60

1.0

60

KR KF

t

/

40

KHKL

OV /2

t

DD

SYSCLK

SYSCLK cycle-to-cycle jitter

Internal PLL relock time

Notes:

—

150

100

—

150

100

—

150

100

—

150

100

ps

5, 6

7

μs

1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)

frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 9.1.1, “PLL Configuration,” for valid

PLL_CFG[0:4] settings.

2. Assumes a lightly-loaded, single-processor system.

3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.

4. Timing is guaranteed by design and characterization.

5. Guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.

7. Relock timing is guaranteed by design and characterization. PLL relock time is the maximum amount of time required

for PLL lock after a stable V and SYSCLK are reached during the power-on reset sequence. This specification also

DD

applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET

must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.

8. Caution: If DFS is enabled, the SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the

resulting processor frequency is greater than or equal to the minimum core frequency.

9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at

the nominal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies

must be reduced. See Section 5.3, “Voltage and Frequency Derating,” for more information.

Figure 3 provides the SYSCLK input timing diagram.

CV

t

IH

V

M

SYSCLK

M

CV

IL

t

KHKL

t

KF

KR

t

SYSCLK

V

= Midpoint Voltage (OV /2)

DD

M

Figure 3. SYSCLK Input Timing Diagram

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

15

Electrical and Thermal Characteristics

5.2.2

Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7447A as defined in Figure 4 and

Figure 5.

1

Table 9. Processor Bus AC Timing Specifications

At recommended operating conditions. See Table 4.

All Speed Grades

2

Parameter

Symbol

Unit

Notes

Min

Max

Input setup times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

ns

t

1.8

—

AVKH

DVKH

IVKH

BMODE[0:1], BVSEL

t

1.8

—

8

MVKH

Input hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

ns

t

0

—

AXKH

DXKH

IXKH

BMODE[0:1], BVSEL

t

0

—

8

MXKH

Output valid times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,

PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT

TS

ARTRY, SHD[0:1]

t

—

2.0

KHAV

KHDV

KHOV

t

—

2.0

KHTSV

KHARV

Output hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,

t

0.5

—

KHAX

KHDX

KHOX

PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT

TS

t

0.5

—

KHTSX

t

KHARX

ARTRY, SHD[0:1]

SYSCLK to output enable

t

0.5

—

ns

5

KHOE

KHOZ

SYSCLK to output high impedance (all except TS, ARTRY,

SHD0, SHD1)

3.5

SYSCLK to TS high impedance after precharge

Maximum delay to ARTRY/SHD0/SHD1 precharge

t

—

1

t

3, 4, 5

KHTSPZ

SYSCLK

t

3, 5, 6, 7

KHARP

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

16

Freescale Semiconductor

Electrical and Thermal Characteristics

1

Table 9. Processor Bus AC Timing Specifications (continued)

At recommended operating conditions. See Table 4.

All Speed Grades

2

Parameter

Symbol

Unit

Notes

Min

Max

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

precharge

t

—

2

t

3, 5, 6, 7

KHARPZ

SYSCLK

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to

the midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input

and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and

connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of t

for inputs

(signal)(state)(reference)(state)

and t

for outputs. For example, t

symbolizes the time input signals (I) reach the valid

(reference)(state)(signal)(state)

IVKH

state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

KHOV

symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold

time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)

(note the position of the reference and its state for inputs) and output hold time can be read as the time from the

rising edge (KH) until the output went invalid (OX).

3. t

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by

sysclk

the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and

precharged high before returning to high impedance, as shown in Figure 6. The nominal precharge width for TS

is 0.5 × t

, that is, less than the minimum t

period, to ensure that another master asserting TS on

SYSCLK

the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal

asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately

following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any

master asserting it low in the first clock following AACK will then go to high impedance for 1 clock before

precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY

is 1.0 t

; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another

SYSCLK

master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance

behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle

of TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated

for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge

width for SHD0 and SHD1 is 1.0 t

. The edges of the precharge vary depending on the programmed ratio

SYSCLK

of core to bus (PLL configurations).

8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These

parameters represent the input setup and hold times for each sample. These values are guaranteed by design

and not tested. These inputs must remain stable after the second sample. See Figure 5 for sample timing.

Figure 4 provides the AC test load for the MPC7447A.

Output

OV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 4. AC Test Load

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

17

Electrical and Thermal Characteristics

Figure 5 provides the mode select input timing diagram for the MPC7447A. The mode select inputs are

sampled twice, once before and once after HRESET negation.

V

SYSCLK

HRESET

M

Mode Signals

2nd Sample

1st Sample

= Midpoint Voltage (OV /2)

V

DD

M

Figure 5. Mode Input Sample Timing Diagram

Figure 6 provides the input/output timing diagram for the MPC7447A.

SYSCLK

V

M

t

AXKH

t

AVKH

IXKH

IVKH

MXKH

t

MVKH

All Inputs

t

KHAV

KHAX

KHDX

KHOX

t

KHDV

KHOV

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

t

KHOE

t_KHOZ

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

t_KHTSPZ

t

KHTSV

t

KHTSX

t_KHTSV

TS

t_KHARPZ

t_KHARV

t_KHARP

ARTRY,

SHD0,

SHD1

t_KHARX

V

= Midpoint Voltage (OV /2)

DD

M

Figure 6. Input/Output Timing Diagram

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

18

Freescale Semiconductor

Electrical and Thermal Characteristics

5.2.3

IEEE 1149.1 AC Timing Specifications

Table 10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 16 through

Figure 19.

1

Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions. See Table 4.

Parameter

TCK frequency of operation

Symbol

Min

Max

Unit

Notes

f

t

0

33.3

—

MHz

ns

TCLK

TCK cycle time

30

15

—

25

TCLK

TCK clock pulse width measured at 1.4 V

TCK rise and fall times

TRST assert time

t

—

ns

JHJL

t

and t

2

ns

JR

JF

t

—

ns

2

3

TRST

Input setup times:

Boundary-scan data

TMS, TDI

ns

t

4

0

—

DVJH

t

IVJH

Input hold times:

Boundary-scan data

TMS, TDI

ns

3

4

t

20

25

—

DXJH

IXJH

Valid times:

Boundary-scan data

TDO

t

4

20

25

JLDV

JLOV

Output hold times:

Boundary-scan data

TDO

4

t

30

—

JLDX

JLOX

TCK to output high impedance:

Boundary-scan data

TDO

4, 5

t

3

19

9

JLDZ

JLOZ

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load

(see Figure 7). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Figure 7 provides the AC test load for TDO and the boundary-scan outputs of the MPC7447A.

Output

OV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 7. Alternate AC Test Load for the JTAG Interface

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

19

Electrical and Thermal Characteristics

Figure 8 provides the JTAG clock input timing diagram.

TCLK

V

M

t

JF

JHJL

JR

t

TCLK

V

= Midpoint Voltage (OV /2)

DD

M

Figure 8. JTAG Clock Input Timing Diagram

Figure 9 provides the TRST timing diagram.

V

M

TRST

t

TRST

V

= Midpoint Voltage (OV /2)

DD

M

Figure 9. TRST Timing Diagram

Figure 10 provides the boundary-scan timing diagram.

TCK

V

M

t

DVJH

t

DXJH

Boundary

Data Inputs

Input

Data Valid

t

JLDV

t

JLDX

Boundary

Data Outputs

Output Data Valid

t

JLDZ

Boundary

Data Outputs

Output Data Valid

= Midpoint Voltage (OV /2)

V

M

DD

Figure 10. Boundary-Scan Timing Diagram

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

20

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 11 provides the test access port timing diagram.

TCK

TDI, TMS

TDO

V

M

t

IVJH

t

IXJH

Input

Data Valid

t

JLOV

t

JLOX

Output Data Valid

t

JLOZ

TDO

Output Data Valid

= Midpoint Voltage (OV /2)

V

M

DD

Figure 11. Test Access Port Timing Diagram

5.3

Voltage and Frequency Derating

To reduce the power consumption of the device, these devices support voltage and frequency derating

whereby the core voltage (V ) may be reduced if the reduced maximum processor core frequency

DD

requirements are observed. The supported derated core voltage, resulting maximum processor core

frequency (f ), and power consumption are provided in Table 11. Only those parameters in Table 11 are

core

affected; all other parameter specifications are unaffected.

Table 11. Supported Voltage, Core Frequency, and Power Consumption Derating

Full-Power Mode Power

Maximum Rated

Core Frequency

(Device Marking)

Supported

Derated Core

Maximum Derated Core

Consumption

Frequency (f

)

core

Voltage (V

)

DD

Maximum

Typical

1000

1267

1333

1420

1.20 V 50mV

867 MHz

15.5 W

18.2 W

18.1 W

21.0 W

10.5 W

12.3 W

14.2 W

1065 MHz

1167 MHz

1267 MHz

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

21

Pin Assignments

6 Pin Assignments

Figure 12 (in Part A) shows the pinout of the MPC7447A, 360 high coefficient of thermal expansion

ceramic ball grid array (HCTE) package as viewed from the top surface. Part B shows the side profile of

the HCTE package to indicate the direction of the top surface view.

Part A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Not to Scale

Part B

Substrate Assembly

Encapsulant

View

Die

Figure 12. Pinout of the MPC7447A, 360 HCTE Package as Viewed from the Top Surface

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

22

Freescale Semiconductor

Pinout Listings

7 Pinout Listings

Table 12 provides the pinout listing for the MPC7447A, 360 HCTE package. The pinouts of the

MPC7447A and MPC7447 are pin compatible, but there have been some changes. An MPC7447A may

be populated on a board designed for a MPC7447 provided all pins defined as ‘no connect’ for the

MPC7447 are unterminated as required by the MPC7457 RISC Microprocessor Hardware Specifications.

The MPC7447A uses pins previously marked ‘no connect’ for the temperature diode pins and for

additional power and ground connections. Because these ‘no connect’ pins in the MPC7447 360 pin

package are not driven in functional mode, an MPC7447 can be populated in an MPC7447A board. See

Section 9.4, “Connection Recommendations,” for additional information.

NOTE

Caution must be exercised when performing boundary scan test operations

on a board designed for an MPC7447A but populated with an MPC7447.

This is because in the MPC7447 it is possible to drive the latches associated

with the former ‘no connect’ pins in the MPC7447, potentially causing

contention on those pins. To prevent this, ensure that these pins are not

connected on the board or, if they are connected, ensure that the states of

internal MPC7447 latches do not cause these pins to be driven during board

testing.

NOTE

This pinout is not compatible with the MPC750, MPC7400, or MPC7410

360 BGA and LGA package.

Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package

1

Signal Name

A[0:35]

Pin Number

Active

I/O

I/F Select

Notes

E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12,

L3, G4, T2, F4, V1, J4, R2, K5, W2, J2, K4, N4, J3, M5,

P5, N3, T1, V2, U1, N5, W1, B12, C4, G10, B11

High

I/O

BVSEL

2

AACK

R1

Low

High

Low

—

Input

I/O

BVSEL

N/A

AP[0:4]

ARTRY

C1, E3, H6, F5, G7

2

3

N2

A8

M1

G9

F8

D2

B7

J1

I/O

AV

Input

Output

Input

Output

Input

Output

DD

BG

Low

High

Low

BVSEL

BMODE0

BMODE1

BR

4

5

BVSEL

CI

1, 6

CKSTP_IN

CKSTP_OUT

A3

B1

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

23

Pinout Listings

Signal Name

Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued)

1

Pin Number

Active

I/O

I/F Select

Notes

CLK_OUT

D[0:63]

H2

High

Output

I/O

BVSEL

R15, W15, T14, V16, W16, T15, U15, P14, V13, W13,

T13, P13, U14, W14, R12, T12, W12, V12, N11, N10,

R11, U11, W11, T11, R10, N9, P10, U10, R9, W10,

U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17, R19,

V18, R18, V19, T19, U19, W19, U18, W17, W18, T16,

T18, T17, W3, V17, U4, U8, U7, R7, P6, R8, W8, T8

DBG

M2

Low

High

Low

High

Low

—

Input

I/O

BVSEL

N/A

DP[0:7]

DRDY

T3, W4, T4, W9, M6, V3, N8, W6

R3

Output

Input

I/O

7

8

9

DTI[0:3]

EXT_QUAL

GBL

G1, K1, P1, N1

A11

E2

GND

B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13,

J6, J8, J10, J12, K7, K3, K9, K11, K13, L6, L8, L10,

L12, M4, M7, M9, M11, M13, N7, P3, P9, P12, R5,

R14, R17, T7, T10, U3, U13, U17, V5, V8, V11, V15

—

GND

A17, A19, B13, B16, B18, E12, E19, F13, F16, F18,

G19, H18, J14, L14, M15, M17, M19, N14, N16, P15,

P19

—

N/A

15

GND_SENSE

HIT

G12, N13

B2

—

Output

Input

—

N/A

19

7

Low

High

—

BVSEL

—

HRESET

D8

INT

D4

L1_TSTCLK

L2_TSTCLK

NC (no connect)

G8

9

B3

10

11

A6, A14, A15, B14, B15, C14, C15, C16, C17, C18,

C19, D14, D15, D16, D17, D18, D19, E14, E15, F14,

F15, G14, G15, H15, H16, J15, J16, J17, J18, J19,

K15, K16, K17, K18, K19, L15, L16, L17, L18, L19

LSSD_MODE

MCP

E8

C9

Low

—

Input

—

BVSEL

N/A

6, 12

OV

B4, C2, C12, D5, F2, H3, J5, K2, L5, M3, N6, P2, P8,

P11, R4, R13, R16, T6, T9, U2, U12, U16, V4, V7,

V10, V14

DD

OVDD_SENSE

PLL_CFG[0:4]

PMON_IN

E18, G18

—

N/A

16

13

B8, C8, C7, D7, A7

High

Low

Input

Output

BVSEL

D9

A9

PMON_OUT

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

24

Freescale Semiconductor

Pinout Listings

Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued)

1

Signal Name

QACK

Pin Number

Active

I/O

I/F Select

Notes

G5

Low

—

Input

Output

I/O

BVSEL

QREQ

SHD[0:1]

SMI

P4

E4, H5

F9

3

Input

Output

Input

Output

Input

SRESET

SYSCLK

TA

A2

A10

K6

Low

High

Low

High

Low

TBEN

TBST

E1

F11

C6

TCK

TDI

B9

6

TDO

A4

TEA

L1

TEMP_ANODE

N18

17

12

9

TEMP_CATHODE N19

TEST[0:3]

TEST[4]

TMS

A12, B6, B10, E10

—

Input

I/O

BVSEL

N/A

D10

—

F1

High

Low

High

Low

—

6

TRST

TS

A5

6, 14

3

L4

TSIZ[0:2]

TT[0:4]

WT

G6, F7, E7

E5, E6, F6, E9, C5

D3

Output

I/O

Output

—

V

H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7,

L9, L11, L13, M8, M10, M12

DD

V

A13, A16, A18, B17, B19, C13, E13, E16, F12, F17,

F19, G11, G16, H14, H17, H19, M14, M16, M18, N15,

N17, P16, P18

—

N/A

15

DD

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

25

Pinout Listings

Signal Name

Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued)

1

Pin Number

Active

I/O

I/F Select

Notes

VDD_SENSE

G13, N12

—

N/A

18

Notes:

1. OV supplies power to the processor bus, JTAG, and all control signals; V supplies power to the processor core and the

DD

PLL (after filtering to become AV ). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V), or to

DD

HRESET or OV (selects 2.5 V); see Table 3. If used, the pull-down resistor should be less than 250 Ω.Because these

DD

settings may change in future products, it is recommended BVSEL be configured using resistor options, jumpers, or some

other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. For actual

recommended value of V or supply voltages see Table 4.

in

2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OV

.

DD

3. These pins require weak pull-up resistors (for example, 4.7 KΩ) to maintain the control signals in the negated state after they

have been actively negated and released by the MPC7447A and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going

high.

5. This signal must be negated during reset, by pull-up resistor to OV or negation by ¬HRESET (inverse of HRESET), to

DD

ensure proper operation.

6. Internal pull up on die.

7. Ignored in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the MPC7447A is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.

11.These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were

NCs on the MPC7447, MPC7445, and MPC7441 have now been defined for other purposes.

12.These input signals are for factory use only and must be pulled up to OV for normal machine operation.

DD

13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software.

14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.

15.These pins were NCs on the MPC7447, MPC7445, and MPC7441. They may be left unconnected for backward compatibility

with these devices, but it is recommended they be connected in new designs to facilitate future products. See Section 9.4,

“Connection Recommendations,” for more information.

16.These pins were OV pins on the MPC7447, MPC7445, and MPC7441. These pins are internally connected to OV and

DD

are intended to allow an external device to detect the I/O voltage level present inside the device package. If unused, they

must be connected directly to OV or left unconnected.

DD

17.These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature

of the processor. These pins may be left unterminated if unused.

18.These pins are internally connected to V and are intended to allow an external device to detect the processor core voltage

DD

level present inside the device package. If unused, they must be connected directly to V or left unconnected.

DD

19.These pins are internally connected to GND and are intended to allow an external device to detect the processor ground

voltage level present inside the device package. If unused, they must be connected directly to GND or left unconnected.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

26

Freescale Semiconductor

Package Description

8 Package Description

The following sections provide the package parameters and mechanical dimensions for the HCTE

package.

8.1

Package Parameters for the MPC7447A, 360 HCTE BGA

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead

high coefficient of thermal expansion ceramic ball grid array (HCTE).

Package outline

Interconnects

Pitch

Minimum module height

Maximum module height

Ball diameter

25 × 25 mm

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

2.72 mm

3.24 mm

0.89 mm (35 mil)

Coefficient of thermal expansion 12.3 ppm/°C

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

27

Package Description

8.2

Mechanical Dimensions for the MPC7447A, 360 HCTE BGA

Figure 13 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360

HCTE BGA package.

2X

Capacitor Region

0.2

NOTES:

D

B

1. Dimensioning and

tolerancing per ASME

Y14.5M, 1994

2. Dimensions in millimeters.

3. Top side A1 corner index is a

metalized feature with

various shapes. Bottom side

A1 corner is designated with

a ball missing from the array.

D1

D2

D3

A1 CORNER

A

0.15 A

E3

E4

E

Millimeters

E2

E1

Dim

Min

Max

A

2.72

0.80

1.10

—

3.24

1.00

1.30

0.6

2X

A1

A2

A3

b

0.2

D4

C

1

2 3 4 5 6 7 8 9 10 111213141516171819

W

V

U

0.82

0.93

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

D

25.00 BSC

D1

D2

D3

D4

e

—

8.0

—

11.3

—

A3

6.5

A2

A1

9.76

9.96

A

1.27 BSC

25.00 BSC

0.35 A

E

E1

E2

E3

E4

—

8.0

—

11.3

e

360X

b

—

6.5

0.3 A B C

A

0.15

8.41

8.61

Figure 13. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A,

360 HCTE BGA Package

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

28

Freescale Semiconductor

Package Description

8.3

Package Parameters for the MPC7447A, 360 HCTE LGA

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360 high

coefficient of thermal expansion ceramic land grid array (HCTE).

Package outline

25 × 25 mm

Interconnects

Pitch

Minimum module height

Maximum module height

Coefficient of thermal expansion

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

1.92 mm

2.20 mm

12.3 ppm/°C

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

29

Package Description

8.4

Mechanical Dimensions for the MPC7447A, 360 HCTE LGA

Figure 14 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360

HCTE LGA package.

2X

Capacitor Region

0.2

NOTES:

D

B

1. Dimensioning and

tolerancing per ASME

Y14.5M, 1994

2. Dimensions in millimeters.

3. Top side A1 corner index is a

metalized feature with

various shapes. Bottom side

A1 corner is designated with

a pad missing from the array.

D1

D2

D3

A1 CORNER

A

0.15 A

E3

E4

E

Millimeters

E2

E1

Dim

Min

Max

A

1.92

1.10

—

2.20

1.30

0.6

2X

A1

A2

b

0.2

D4

C

1

2 3 4 5 6 7 8 9 10 111213141516171819

0.82

0.93

W

V

U

D

25.00 BSC

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

D1

D2

D3

D4

e

—

8.0

—

11.3

—

A2

6.5

9.76

9.96

A1

1.27 BSC

25.00 BSC

A

E

0.35 A

E1

E2

E3

E4

—

8.0

—

11.3

—

6.5

e

360X

b

0.3 A B C

8.41

8.61

A

0.15

Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A,

360 HCTE LGA Package

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

30

Freescale Semiconductor

Package Description

8.5

Package Parameters for the MPC7447A, 360 HCTE

RoHS-Compliant BGA

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360

lead-free high coefficient of thermal expansion ceramic ball grid array (HCTE).

Package outline

25 × 25 mm

Interconnects

Pitch

Minimum module height

Maximum module height

Ball diameter

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

2.32 mm

2.80 mm

0.75 mm (30 mil)

12.3 ppm/°C

Coefficient of thermal expansion

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

31

Package Description

8.6

Mechanical Dimensions for the MPC7447A, 360 HCTE

RoHS-Compliant BGA

Figure 15 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360

HCTE BGA package.

2X

Capacitor Region

0.2

NOTES:

1. Dimensioning and

D

B

tolerancing per ASME

Y14.5M, 1994

2. Dimensions in millimeters.

3. Top side A1 corner index is a

metalized feature with

D1

D2

D3

A1 CORNER

A

0.15 A

various shapes. Bottom side

A1 corner is designated with

a ball missing from the array.

4. Dimension A1 represents the

collapsed sphere diameter.

E3

E4

E

Millimeters

E2

E1

Dim

Min

Max

A

2.32

0.40

1.10

—

2.80

0.60

1.30

0.6

2X

4

A1

0.2

D4

A2

A3

b

C

1

2 3 4 5 6 7 8 9 10 111213141516171819

W

V

U

0.60

0.90

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

D

25.00 BSC

D1

D2

D3

D4

e

—

8.0

—

11.3

—

A3

6.5

A2

A1

9.76

9.96

A

1.27 BSC

25.00 BSC

0.35 A

E

E1

E2

E3

E4

—

8.0

—

11.3

e

360X

b

—

6.5

0.3 A B C

A

0.15

8.41

8.61

Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A,

360 HCTE RoHS-Compliant BGA Package

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

32

Freescale Semiconductor

Package Description

8.7

Substrate Capacitors for the MPC7447A, 360 HCTE

Figure 16 shows the connectivity of the substrate capacitor pads for the MPC7447A, 360 HCTE. All

capacitors are 100 nF.

Pad Number

Capacitor

A1 CORNER

–1

–2

C1

C2

GND

V

DD

V

C1-1 C2-1 C3-1 C4-1 C5-1 C6-1

C3

OV

DD

C4

V

DD

C1-2 C2-2 C3-2

C4-2 C5-2 C6-2

C5

DD

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C18-1 C17-1 C16-1 C15-1 C14-1 C13-1

OV

DD

V

DD

OV

DD

V

DD

OV

DD

V

DD

OV

V

DD

Figure 16. Substrate Bypass Capacitors for the MPC7447A, 360 HCTE

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

33

System Design Information

9 System Design Information

This section provides system and thermal design recommendations for successful application of the

MPC7447A.

9.1

Clocks

9.1.1

PLL Configuration

The MPC7447A PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency,

the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL

configuration for the MPC7447A is shown in Table 13 for a set of example frequencies. In this example,

shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies

that do not comply with the 1400 MHz column in Table 8. When enabled, dynamic frequency switching

(DFS) also affects the core frequency by halving the bus-to-core multiplier; see Section 9.8.5, “Dynamic

Frequency Switching (DFS),” for more information. Note that when DFS is enabled the resulting core

frequency must meet the minimum core frequency requirements described in Table 8.

Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_

CFG[0:4]

Bus (SYSCLK) Frequency

Bus-to-

Core

Multiplier Multiplier

Core-to-

VCO

33

MHz

50

MHz

67

75

83

100

133

167

MHz

1

01000

10000

10100

10110

10010

11010

01010

00100

00010

11000

2x

3x

4x

2x

1

668

(1333)

5x

665

835

(1333) (1670)

5.5x

6x

732 919

(1466) (1837)

798 1002

600

(1200) (1600) (2004)

6.5x

7x

650 865 1086

(1300) (1730) (2171)

700 931 1169

(1400) (1862) (2338)

7.5x

8x

623

750 998 1253

(1245) (1500) (2000) (2505)

600

664 800 1064 1336

(1200) (1328) (1600) (2128) (2672)

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

34

Freescale Semiconductor

System Design Information

Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_

CFG[0:4]

Bus (SYSCLK) Frequency

Bus-to-

Core

Multiplier Multiplier

Core-to-

VCO

33

MHz

50

MHz

67

75

83

100

133

167

MHz

01100

01111

01110

10101

10001

10011

00000

10111

11111

01011

11100

11001

00011

11011

00001

00101

00111

01001

8.5x

9x

2x

638

706

850

1131

1420

(1276) (1412) (1700) (2261) (2833)

603

675 747 900 1197

(1200) (1350) (1494) (1800) (2394)

9.5x

10x

637 713 789 950 1264

(1266) (1524) (1578) (1900) (2528)

670 750 830 1000 1330

(1333) (1500) (1660) (2000) (2667)

10.5x

11x

704 788 872 1050 1397

(1400) (1876) (1744) (2100) (2793)

737 825 913 1100

(1466) (1650) (1826) (2200)

11.5x

12x

771

(532)

863

955

1150

(1726) (1910) (2300)

600

804

900 996 1200

(1200) (1600) (1800) (1992) (2400)

12.5x

13x

625 838 938 1038 1250

(1200) (1666) (1876) (2076) (2500)

650 871 975 1079 1300

(1300) (1730) (1950) (2158) (2600)

13.5x

14x

675 905 1013 1121 1350

(1350) (1800) (2026) (2242) (2700)

700 938 1050 1162 1400

(1400) (1866) (2100) (2324) (2800)

15x

750 1005 1125 1245

(1500) (2000) (2250) (2490)

800 1072 1200 1328

16x

(1600) (2132) (2400) (2656)

17x

850 1139 1275 1411

(1900) (2264) (2550) (2822)

900 1206 1350

18x

(1800) (2400) (2700)

20x

660

1000 1340

(1334) (2000) (2664)

21x

693 1050 1407

(1400) (2100) (2797)

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

35

System Design Information

Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_

CFG[0:4]

Bus (SYSCLK) Frequency

Bus-to-

Core

Multiplier Multiplier

Core-to-

VCO

33

MHz

50

MHz

67

75

83

100

133

167

MHz

01101

11101

24x

28x

2x

792

1200

(1600) (2400)

924 1400

(1866) (2800)

00110

11110

PLL bypass

PLL off

PLL off, SYSCLK clocks core circuitry directly

PLL off, no core clocking occurs

Notes:

1. Ratios below 5:1 require an AACK delay See MPC7450 RISC Microprocessor Family Reference Manual, Section

9.3.3, “MPX Bus Address Tenure Termination.”

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,

or VCO frequencies that are not useful, not supported, or not tested for by the MPC7455; see Section 5.2.1, “Clock

AC Specifications,” for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.

However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be

driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup t

and hold time

IVKH

t

(see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the internal

IXKH

processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the MPC7447A regardless of the SYSCLK input.

9.1.2

System Bus Clock (SYSCLK) and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference

emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise

magnitude in order to meet industry and government requirements. These clock sources intentionally add

long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 8

considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter

should meet the MPC7457 input cycle-to-cycle jitter requirement. Frequency modulation and spread are

separate concerns, and the MPC7457 is compatible with spread spectrum sources if the recommendations

listed in Table 14 are observed.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

36

Freescale Semiconductor

System Design Information

Table 14. Spread Specturm Clock Source Recommendations

At recommended operating conditions. See Table 4.

Parameter

Min

Max

Unit

Notes

Frequency modulation

Frequency spread

—

50

kHz

%

1

1.0

1, 2

Notes:

1. Guaranteed by design.

2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO

frequencies, must meet the minimum and maximum specifications given in Table 8.

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is

operated at its maximum rated core or bus frequency should avoid violating the stated limits by using

down-spreading only.

9.2

PLL Power Supply Filtering

The AV power signal is provided on the MPC7447A to provide power to the clock generation PLL. To

DD

ensure stability of the internal clock, the power supplied to the AV input signal should be filtered of any

DD

noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. A circuit similar to the one shown

in Figure 17 using surface-mount capacitors with minimum effective series inductance (ESL) is

recommended.

The circuit should be placed as close as possible to the AV pin to minimize noise coupled from nearby

DD

circuits. It is often possible to route directly from the capacitors to the AV pin, which is on the periphery

DD

of the 360 HCTE footprint.

10 Ω

V

AV

DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 17. PLL Power Supply Filter Circuit

9.3

Decoupling Recommendations

Due to the MPC7447A dynamic power management feature, large address and data buses, and high

operating frequencies, the MPC7447A can generate transient power surges and high frequency noise in its

power supply, especially while driving large capacitive loads. This noise must be prevented from reaching

other components in the MPC7447A system, and the MPC7447A itself requires a clean, tightly regulated

source of power. Therefore, it is recommended that the system designer use sufficient decoupling

capacitors, typically one capacitor for every 1–2 V pins, and a similar or lesser number for the OV

DD

pins, placed as close as possible to the power pins of the MPC7447A. It is also recommended that these

decoupling capacitors receive their power from separate V , OV , and GND power planes in the PCB,

DD

utilizing short traces to minimize inductance.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

37

System Design Information

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT)

capacitors should be used to minimize lead inductance. Orientations where connections are made along

the length of the part, such as 0204, are preferable but not mandatory. Consistent with the

recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic

(Prentice Hall, 1993) and contrary to previous recommendations for decoupling Freescale

microprocessors, multiple small capacitors of equal value are recommended over using multiple values of

capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V and OV planes, to enable quick recharging of the smaller chip capacitors. These bulk

DD

capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time

necessary. They should also be connected to the power and ground planes through two vias to minimize

inductance. Suggested bulk capacitors are: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

9.4

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unless otherwise noted, unused active-low inputs should be tied to OV , and unused active-high

DD

inputs should be connected to GND. All NC (no connect) signals must remain unconnected.

Power and ground connections must be made to all external V , OV , and GND pins in the

DD

MPC7447A. For backward compatibility with the MPC7447, MPC7445, and MP7441, or for migrating a

system originally designed for one of these devices to the MPC7447A, the new power and ground signals

(formerly NC, see Table 12) may be left unconnected. There is no performance degradation associated

with leaving these pins unconnected. However, future devices may require these additional power and

ground signals to be connected to achieve maximum performance, and it is recommended that new designs

include the additional connections to facilitate future upgrades. See also Section 7, “Pinout Listings,” for

additional information.

9.5

Output Buffer DC Impedance

The MPC7447A processor bus drivers are characterized over process, voltage, and temperature. To

measure Z , an external resistor is connected from the chip pad to OV or GND. The value of each

0

DD

resistor is varied until the pad voltage is OV /2. Figure 18 shows the driver impedance measurement.

DD

The output impedance is the average of two components—the resistances of the pull-up and pull-down

devices. When data is held low, SW2 is closed (SW1 is open), and R is trimmed until the voltage at the

N

pad equals OV /2. R then becomes the resistance of the pull-down devices. When data is held high,

DD

N

SW1 is closed (SW2 is open), and R is trimmed until the voltage at the pad equals OV /2. R then

P

DD

P

becomes the resistance of the pull-up devices. R and R are designed to be close to each other in value.

P

N

Then, Z = (R + R )/2.

0

P

N

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

38

Freescale Semiconductor

System Design Information

OV

DD

R

N

SW2

SW1

Pad

Data

R

P

OGND

Figure 18. Driver Impedance Measurement

Table 15 summarizes the signal impedance results. The impedance increases with junction temperature

and is relatively unaffected by bus voltage.

Table 15. Impedance Characteristics

V_DD= 1.5 V, OV_DD= 1.8 V 5%, T_j= 5°–85°C

Impedance

Processor Bus

Unit

Z

Typical

Maximum

33–42

31–51

Ω

0

9.6

Pull-Up/Pull-Down Resistor Requirements

The MPC7447A requires high-resistive (weak: 4.7 KΩ) pull-up resistors on several control pins of the bus

interface to maintain the control signals in the negated state after they have been actively negated and

released by the MPC7447A or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.

Some pins designated as being factory test pins must be pulled up to OV or down to GND to ensure

DD

proper device operation. The pins that must be pulled up to OV are: LSSD_MODE and TEST[0:3]; the

DD

pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. The CKSTP_IN signal should

likewise be pulled up through a pull-up resistor (weak or stronger: 4.7 KΩ–1 KΩ) to prevent erroneous

assertions of this signal.

In addition, the MPC7447A has one open-drain style output that requires a pull-up resistor (weak or

stronger: 4.7 KΩ–1 KΩ) if it is used by the system. This pin is CKSTP_OUT.

If pull-down resistors are used to configure BVSEL, the resistors should be less than 250 Ω (see Table 12).

Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and pull-down

resistors (1 KΩ or less) are recommended to configure these signals in order to protect against erroneous

switching due to ground bounce, power supply noise or noise coupling.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

39

System Design Information

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and

may, therefore, float in the high-impedance state for relatively long periods of time. Because the

MPC7447A must continually monitor these signals for snooping, this float condition may cause excessive

power draw by the input receivers on the MPC7447A or by other receivers in the system. These signals

can be pulled up through weak (10-KΩ) pull-up resistors by the system, address bus driven mode enabled

(see the MPC7450 RISC Microprocessor Family Users’ Manual for more information on this mode), or

they may be otherwise driven by the system during inactive periods of the bus to avoid this additional

power draw. Preliminary studies have shown the additional power draw by the MPC7447A input receivers

to be negligible and, in any event, none of these measures are necessary for proper device operation. The

snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.

If address or data parity is not used by the system, and respective parity checking is disabled through HID1,

the input receivers for those pins are disabled and do not require pull-up resistors, and may be left

unconnected by the system. If extended addressing is not used (HID0[XAEN] = 0), A[0:3] are unused and

must be pulled low to GND through weak pull-down resistors; additionally, if address parity checking is

enabled (HID1[EBA] = 1) and extended addressing is not used, AP[0] must be pulled up to OV through

DD

a weak pull-up resistor. If the MPC7447A is in 60x bus mode, DTI[0:3] must be pulled low to GND

through weak pull-down resistors.

The data bus input receivers are normally turned off when no read operation is in progress and, therefore,

do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require

pull-ups, or that those signals be otherwise driven by the system during inactive periods. The data bus

signals are: D[0:63] and DP[0:7].

9.7

JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture.

While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more

reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.

Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,

simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic.

The arrangement shown in Figure 19 allows the COP port to independently assert HRESET or TRST,

while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not

be used, TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

power-on. Although Freescale recommends that the COP header be designed into the system as shown in

Figure 19, if this is not possible, the isolation resistor will allow future access to TRST in the case where

a JTAG interface may need to be wired onto the system in debug situations.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

40

Freescale Semiconductor

System Design Information

The COP header shown in Figure 19 adds many benefits—breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features are possible through this interface—and

can be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has

pin 14 removed as a connector key.

There is no standardized way to number the COP header shown in Figure 19; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 19 is common to all known emulators.

The QACK signal shown in Figure 19 is usually connected to the PCI bridge chip in a system and is an

input to the MPC7447A informing it that it can go into the quiescent state. Under normal operation this

occurs during a low-power mode selection. In order for COP to work, the MPC7447A must see this signal

asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the

product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator

products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up

resistor can be implemented to ensure this signal is negated when it is not being driven by the tool. Note

that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never

necessary to populate both in a system. To preserve correct power-down operation, QACK should be

merged through logic so that it also can be driven by the PCI bridge.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

41

System Design Information

SRESET

From Target

SRESET

HRESET

Board Sources HRESET

6

(if any)

QACK

10 KΩ

HRESET

13

11

OV

DD

SRESET

OV

DD

OV

5

0 Ω

6

TRST

1

3

2

4

TRST

4

6

VDD_SENSE

OV

DD

10 KΩ

2 KΩ

5

6

1

5

DD

7

8

CHKSTP_OUT

15

10 KΩ

9

10

12

OV

DD

Key

14

11

10 KΩ

2

DD

KEY

No Pin

13

15

CHKSTP_IN

TMS

CHKSTP_IN

TMS

8

9

1

3

16

TDO

TDI

COP Connector

Physical Pin Out

TDO

TDI

TCK

7

2

TCK

QACK

10

NC

OV

DD

3

2 KΩ

10 KΩ

12

16

OV

4

10 KΩ

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7447A. Connect

pin 5 of the COP header to OV with a 10-KΩ pull-up resistor.

DD

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP

header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect

HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.

6. The COP port and target board should be able to independently assert HRESET and TRST to the

processor in order to fully control the processor as shown above.

Figure 19. JTAG Interface Connection

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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System Design Information

9.8

Thermal Management Information

This section provides thermal management information for the high coefficient of thermal expansion

(HCTE) package for air-cooled applications. Proper thermal control design is primarily dependent on the

system-level design—the heat sink, airflow, and thermal interface material. The MPC7447A implements

several features designed to assist with thermal management, including DFS and the temperature diode.

DFS reduces the power consumption of the device by reducing the core frequency; see Section 9.8.5.1,

“Power Consumption with DFS Enabled,” for specific information regarding power reduction and DFS.

The temperature diode allows an external device to monitor the die temperature in order to detect excessive

temperature conditions and alert the system; see Section 9.8.4, “Temperature Diode,” for more

information.

To reduce the die-junction temperature, heat sinks may be attached to the package by several

methods—spring clip to holes in the printed-circuit board or package, and mounting clip and screw

assembly (see Figure 20 and Figure 21); however, due to the potential large mass of the heat sink,

attachment through the printed-circuit board is suggested. In any implementation of a heat sink solution,

the force on the die should not exceed ten pounds.

HCTE BGA Package

Heat Sink

Clip

Thermal

Interface Material

Printed-Circuit Board

Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options

NOTE

A clip on heat sink is not recommended for LGA because there may not be

adequate clearance between the device and the circuit board. A through-hole

solution is recommended, as shown in Figure 21 below.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

43

System Design Information

HCTE LGA Package

Heat Sink

Clip

Thermal

Interface Material

Printed-Circuit Board

Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options

The board designer can choose between several types of heat sinks to place on the MPC7447A. There are

several commercially-available heat sinks for the MPC7447A provided by the following vendors:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

408-567-8082

401-732-8100

Alpha Novatech

473 Sapena Ct. #12

Santa Clara, CA 95054

Internet: www.alphanovatech.com

Calgreg Thermal Solutions

60 Alhambra Road

Warwick, RI 02886

Internet: www.calgregthermalsolutions.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Tyco Electronics

Chip Coolers™

P.O. Box 3608

Harrisburg, PA 17105-3608

Internet: www.chipcoolers.com

717-564-0100

603-635-2800

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

44

Freescale Semiconductor

System Design Information

9.8.1

Internal Package Conduction Resistance

For the exposed-die packaging technology described in Table 5, the intrinsic conduction thermal resistance

paths are as follows:

•

The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die)

The die junction-to-board thermal resistance

Figure 22 depicts the primary heat transfer path for a package with an attached heat sink mounted to a

printed-circuit board.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

(Note the internal versus external package resistance.)

Figure 22. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach

material (or thermal interface material), and finally to the heat sink where it is removed by forced-air

convection.

Because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected

for a first-order analysis. Thus the thermal interface material and the heat sink conduction/convective

thermal resistances are the dominant terms.

9.8.2

Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the

thermal contact resistance. For those applications where the heat sink is attached by spring clip

mechanism, Figure 23 shows the thermal performance of three thin-sheet thermal interface materials

(silicone, graphite/oil, fluoroether oil), a bare joint, and a joint with thermal grease as a function of contact

pressure. As shown, the performance of these thermal interface materials improves with increasing contact

pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare

joint results in a thermal resistance approximately seven times greater than the thermal grease joint.

Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board

(see Figure 20). Therefore, synthetic grease offers the best thermal performance, considering the low

interface pressure, and is recommended due to the high power dissipation of the MPC7447A. Of course,

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

45

System Design Information

the selection of any thermal interface material depends on many factors—thermal performance

requirements, manufacturability, service temperature, dielectric properties, cost, and so on.

Silicone Sheet (0.006 in.)

Bare Joint

2

Fluoroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

1.5

1

0.5

0

10

20

30

Contact Pressure (psi)

Figure 23. Thermal Performance of Select Thermal Interface Material

40

50

60

70

80

The board designer can choose between several types of thermal interface. Heat sink adhesive materials

should be selected based on high conductivity and mechanical strength to meet equipment shock/vibration

requirements. There are several commercially available thermal interfaces and adhesive materials

provided by the following vendors:

The Bergquist Company

18930 West 78 St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

800-347-4572

781-935-4850

800-248-2481

th

Chomerics, Inc.

77 Dragon Ct.

Woburn, MA 01801

Internet: www.chomerics.com

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

Midland, MI 48686-0997

Internet: www.dowcorning.com

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

46

Freescale Semiconductor

System Design Information

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

888-246-9050

Internet: www.microsi.com

Thermagon Inc.

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

The following section provides a heat sink selection example using one of the commercially available heat

sinks.

9.8.3

Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T = T + T + (R + R + R ) × P

j

i

r

θJC

θint

θsa

d

where:

T is the die-junction temperature

j

T is the inlet cabinet ambient temperature

i

T is the air temperature rise within the computer cabinet

r

R

is the junction-to-case thermal resistance

θJC

θint

θsa

is the adhesive or interface material thermal resistance

is the heat sink base-to-ambient thermal resistance

P is the power dissipated by the device

d

During operation, the die-junction temperatures (T ) should be maintained less than the value specified in

j

Table 4. The temperature of air cooling the component greatly depends on the ambient inlet air temperature

and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T )

i

may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the range of 5° to

r

10°C. The thermal resistance of the thermal interface material (R ) is typically about 1.5°C/W. For

θint

example, assuming a T of 30°C, a T of 5°C, an HCTE package R = 0.1, and a typical power

i

r

θJC

consumption (P ) of 18.7 W, the following expression for T is obtained:

d

j

Die-junction temperature: T = 30°C + 5°C + (0.1°C/W + 1.5°C/W + R ) × 18.7 W

j

θsa

For this example, a R value of 2.1°C/W or less is required to maintain the die junction temperature below

θsa

the maximum value of Table 4.

Though the die-junction-to-ambient and the heat-sink-to-ambient thermal resistances are a common

figure-of-merit used for comparing the thermal performance of various microelectronic packaging

technologies, one should exercise caution when only using this metric in determining thermal management

because no single parameter can adequately describe three-dimensional heat flow. The final die-junction

operating temperature is not only a function of the component-level thermal resistance, but the

system-level design and its operating conditions. In addition to the component's power consumption, a

number of factors affect the final operating die-junction temperature—airflow, board population (local

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

47

System Design Information

heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level

interconnect technology, system air temperature rise, altitude, and so on.

Due to the complexity and variety of system-level boundary conditions for today's microelectronic

equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction)

may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as

well as system-level designs.

For system thermal modeling, the MPC7447A thermal model is shown in Figure 24. Four volumes

represent this device. Two of the volumes, solder ball-air and substrate, are modeled using the package

outline size of the package. The other two, die and bump-underfill, have the same size as the die. The

3

silicon die should be modeled 8.5 × 9.9 × 0.7 mm with the heat source applied as a uniform source at the

3

bottom of the volume. The bump and underfill layer is modeled as 8.5 × 9.9 × 0.07 mm (or as a collapsed

volume) with orthotropic material properties: 0.6 W/(m • K) in the xy-plane and 1.9 W/(m • K) in the

3

direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm , and has 8.1 W/(m • K) isotropic

conductivity in the xy-plane and 4 W/(m • K) in the direction of the z-axis. The solder ball and air layer

are modeled with the same horizontal dimensions as the substrate and are 0.6 mm thick. They can also be

modeled as a collapsed volume using orthotropic material properties: 0.034 W/(m • K) in the xy-plane

direction and 3.8 W/(m • K) in the direction of the z-axis.

Conductivity

Value

Unit

Die

3

Bump and Underfill (8.5 × 9.9 × 0.07 mm )

Bump and Underfill

z

k

0.6

1.9

W/(m • K)

x

y

z

Substrate

Solder and Air

Side View of Model (Not to Scale)

3

Substrate (25 × 25 × 1.2 mm )

x

k

8.1

4.0

x

y

z

Substrate

3

Solder Ball and Air (25 × 25 × 0.6 mm )

k

0.034

3.8

x

y

z

Die

y

Top View of Model (Not to Scale)

Figure 24. Recommended Thermal Model of MPC7447A

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

48

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System Design Information

9.8.4

Temperature Diode

The MPC7447A has a temperature diode on the microprocessor that can be used in conjunction with other

system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the

negative temperature coefficient of a diode operated at a constant current to determine the temperature of

the microprocessor and its environment. For proper operation, the monitoring device used should

auto-calibrate the device by canceling out the V variation of each MPC7447A’s internal diode.

BE

The following are the specifications of the MPC7447A on-board temperature diode:

0.40 V <V <0.90 V

f

Operating range 2–300 μA

Diode leakage < 10 nA @ 125 C

Ideality factor (n) over 5–150 μA @ 60 C: 1.0275 ± 0.9 %

Ideality factor is defined as the deviation from the ideal diode equation:

qV

___f

nKT

I_fw= I_se

– 1

Where:

I

= Forward current

fw

I = Saturation current

s

V = Voltage at diode BM: this does not show up in any equations.

d

V = Voltage forward biased

f

-19

q = Charge of electron (1.6 x 10

C)

n = Ideality factor (normally 1.0)

-23

K = Boltzman’s constant (1.38 x 10 Joules/K)

T = Temperature (Kelvins)

Another useful equation is :

KT

I

__

V_H– V_L= n

_H_

ln

q

I

L

Where:

V = Diode voltage while I is flowing

H

V = Diode voltage while I is flowing

L

I = Larger diode bias current

H

I = Smaller diode bias current

L

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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49

System Design Information

The ratio of I to I is usually selected to be 10:1. The above simplifies to the following:

H

L

-4

V – V = 1.986 × 10 × nT

H

L

Solving for T, the equation becomes:

V – V

H

L

__________

nT =

-4

1.986 × 10

9.8.5

Dynamic Frequency Switching (DFS)

The new DFS feature in the MPC7447A adds the ability to divide the processor-to-system bus ratio by two

during normal functional operation by setting the HID1[DFS2] bit. The frequency change occurs in 1 clock

cycle, and no idle waiting period is required to switch between modes. Additional information regarding

DFS can be found in the MPC7450 RISC Microprocessor Family Reference Manual.

9.8.5.1

Power Consumption with DFS Enabled

Power consumption with DFS enabled can be approximated using the following formula:

f

DFS

___

P_DFS

=

(P – P_DS) + P_DS

f

Where:

P

= Power consumption with DFS enabled

= Core frequency with DFS enabled

DFS

f

DFS

f = Core frequency prior to enabling DFS

P = Power consumption prior to enabling DFS (see Table 7)

P

= Deep sleep mode power consumption (see Table 7)

DS

The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed.

9.8.5.2 Bus-to-Core Multiplier Constraints with DFS

DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:4] during hard reset.

Specifically, because the MPC7447A does not support quarter clock ratios or the 1x multiplier, the DFS

feature is limited to integer PLL multipliers of 4x and higher. The complete listing is shown in Table 16.

Table 16. Valid Divide Ratio Configurations

Bus-to-Core Multiplier Configured

by PLL_CFG[0:4]

Bus-to-Core Multiplier with

HID1[DFS1] = 1

(÷2)

(see Table 13)

2x

3x

N/A

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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System Design Information

Table 16. Valid Divide Ratio Configurations (continued)

Bus-to-Core Multiplier Configured

by PLL_CFG[0:4]

Bus-to-Core Multiplier with

HID1[DFS1] = 1

(÷2)

(see Table 13)

4x

5x

2x

2.5x

N/A

3x

5.5x

6x

6.5x

7x

N/A

3.5x

N/A

4x

7.5x

8x

8.5x

9x

N/A

4.5x

N/A

5x

9.5x

10x

10.5x

11x

11.5x

12x

12.5x

13x

13.5x

14x

15x

16x

17x

18x

20x

21x

24x

28x

N/A

5.5x

N/A

6x

N/A

6.5x

N/A

7x

7.5x

8x

8.5x

9x

10x

10.5x

12x

14x

9.8.5.3

Minimum Core Frequency Requirements with DFS

In many systems, enabling DFS can result in very low processor core frequencies. However, care must be

taken to ensure that the resulting processor core frequency is within the limits specified in Table 8. Proper

operation of the device is not guaranteed at core frequencies below the specified minimum f

.

core

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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51

Document Revision History

10 Document Revision History

Table 17 provides a revision history for this hardware specification.

Table 17. Document Revision History

Revision

Number

Date

Substantive Changes

Corrected RoHS BGA sphere diameter dimensions

5

4

01/30/2005

09/23/2005 Added RoHS BGA case outlines and part numbers.

Removed note references for CI and WT in Table 12

3

08/23/2005 Added “Section 9.1.2, “System Bus Clock (SYSCLK) and Spread Spectrum Sources”

Section 9.8, “Thermal Management Information”: Added vendor to list

Section 9.8.3, “Heat Sink Selection Example”: Correct silicon die and underfil/bump model dimensions

02/16/2005 Changed die size

2

Table 8: Modified jitter specifications to conform to JEDEC standards, changed jitter specification to

cycle-to-cycle jitter (instead of long- and short-term jitter); changed jitter bandwidth recommendations.

Added information for LGA package.

1

—

Added t

, t

, and t

to Table 9; these were previously grouped with t

and

KHOV

KHTSV KHARV KHTSX

KHARX

t

. NOTE: Documentation change only; the values for the output valid and output hold AC timing

KHOX

specifications remain unchanged for TS, ARTRY, and SHD[0:1].

Added derating section with table; added 1000 MHz speed bin

0.1

0

—

Retitled Table 19 to include document order information for MC7447AnnnnNx series hardware

specification addendum.

Initial revision.

11 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 11.1, “Part Numbers Fully Addressed by This Document.” Note that the individual part numbers

correspond to a maximum processor core frequency. For available frequencies, contact a local Freescale

sales office. In addition to the processor frequency, the part numbering scheme also includes an application

modifier that may specify special application conditions. Each part number also contains a revision level

code that refers to the die mask revision number. Section 11.2, “Part Numbers Not Fully Addressed by This

Document,” lists the part numbers that do not fully conform to the specifications of this document. These

special part numbers require an additional document called a hardware specification addendum.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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Ordering Information

11.1 Part Numbers Fully Addressed by This Document

Table 18 provides the Freescale part numbering nomenclature for the MPC7447A.

Table 18. Part Numbering Nomenclature

MC

7447A

xx

nnnn

L

x

Product

Code

Part

Identifier

Processor

Frequency

Application

Modifier

Package

Revision Level

B: 1.1:PVR = 8003 0101

MC

7447A

HX = HCTE BGA

VS = RoHS LGA

VU = RoHS BGA

1000

1267

1333

1420

L: 1.3 V 50 mV

0 to 105°C

11.2 Part Numbers Not Fully Addressed by This Document

Parts with application modifiers or revision levels not fully addressed in this specification document are

described in separate hardware specification addenda which supplement and supersede this document. As

such parts are released, these specifications will be listed in this section.

Table 19. Part Numbers Addressed by MC7447AxxnnnnNx Series Hardware Specification Addendum

(Document Order No. MPC7447AECS01AD)

MC 7447A

xx

nnnn

N

x

Product

Code

Part

Identifier

Processor

Frequency

Package

Application Modifier

Revision Level

MC

7447A

HX = HCTE BGA

VS = RoHS LGA

VU = RoHS BGA

600

733

867

N: 1.1 V 50 mV

B:1.1: PVR = 8003 0101

0 to 105°C

1000

1167

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

53

Ordering Information

Table 20. Part Numbers Addressed by MC7447ATxxnnnnNx Series Hardware Specification Addendum

(Document Order No. MPC7447AECS02AD)

MC 7447A

T

xx

nnnn

N

x

Product

Code

Part

Identifier

Specification

Modifier

Processor

Frequency

Application

Modifier

Package

Revision Level

MC

7447A

T = Extended HX = HCTE BGA

Temperature

867

1000

1167

N: 1.1 V 50 mV

B:1.1: PVR = 8003 0101

–40 to 105°C

Device

11.3 Part Marking

Parts are marked as the example shown in Figure 25.

MC7447A

xxnnnnLx

AWLYYWW

MMMMMM

YWWLAZ

7447A

BGA / LGA

Notes:

AWLYYWW is the test code.

MMMMMM is the M00 (mask) number.

YWWLAZ is the assembly traceability code.

Figure 25. Part Marking for BGA and LGA Device

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

54

Freescale Semiconductor

Ordering Information

THIS PAGE INTENTIONALLY LEFT BLANK

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

55

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MPC7447AEC

Rev. 5

01/2006


型号：	MC7447AVS867NB
厂家：	NXP
描述：	RISC Microprocessor Hardware Specifications
文件：	总56页 (文件大小：1285K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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