MC9S08LL16CLFR [NXP]
IC,MICROCONTROLLER,8-BIT,CMOS,QFP,48PIN,PLASTIC;
| 型号： | MC9S08LL16CLFR |
| 厂家： | 
NXP |
| 描述： | IC,MICROCONTROLLER,8-BIT,CMOS,QFP,48PIN,PLASTIC |
| 文件： | 总44页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08LL16
Rev. 7, 1/2013
48-LQFP
Case 932
64-LQFP
Case 840F
MC9S08LL16 Series
Covers: MC9S08LL16 and
MC9S08LL8
48-QFN
1314
Features
•
8-Bit HCS08 Central Processor Unit (CPU)
– Up to 20-MHz CPU at 3.6V to 1.8V across temperature range
of -40°C to 85°C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
On-Chip Memory
– Dual Array FLASH read/program/erase over full operating
voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
FLASH contents
Power-Saving Modes
– Two low power stop modes
– Reduced power wait mode
– Low power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents.
– Very low power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to real time
counter
– 6 usec typical wake up time from stop3 mode
Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal
or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz
to 16 MHz
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by
internal or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supports bus frequencies from 1MHz
to 10 MHz.
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes. Eight deep FIFO for
storing change-of-flow addresses and event-only data. Debug
module supports both tag and force breakpoints
Peripherals
– LCD — 4x28 or 8x24 LCD driver with internal charge pump
and option to provide an internally regulated LCD reference
that can be trimmed for contrast control.
– ADC — 8-channel, 12-bit resolution; 2.5 μs conversion time;
automatic compare function; temperature sensor; internal
bandgap reference channel; operation in stop3; fully functional
from 3.6V to 1.8V
– ACMP — Analog comparator with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can
be optionally routed to TPM module; operation in stop3
– SCI — Full duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break
detection; wake up on active edge
– SPI— Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or Slave mode;
MSB-first or LSB-first shifting
– IIC — IIC with up to 100 kbps with maximum bus loading;
Multi-master operation; Programmable slave address;
Interrupt driven byte-by-byte data transfer; supports broadcast
mode and 10-bit addressing
– TPMx — Two 2-channel (TPM1 and TPM2); Selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel;
– TOD— (Time Of Day) 8-bit quarter second counter with
match register; External clock source for precise time base,
time-of-day, calendar or task scheduling functions; Free
running on-chip low power oscillator (1 kHz) for cyclic
wake-up without external components.
•
•
•
•
•
•
System Protection
– Watchdog computer operating properly (COP) reset with
option to run from dedicated 1-kHz internal clock source or
bus clock
– Low-Voltage Warning with interrupt
– Low-Voltage Detection with reset or interrupt
– Illegal opcode and illegal address detection with reset
– Flash block protection
•
•
Input/Output
– 38 GPIOs, 2 output-only pins
– 8 KBI interrupts with selectable polarity
– Hysteresis and configurable pull up device on all input pins;
Configurable slew rate and drive strength on all output pins.
Package Options
Development Support
– 64-LQFP, 48-LQFP and 48-QFN
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip
debug module)
Table of Contents
1
2
3
Devices in the MC9S08LL16 Series . . . . . . . . . . . . . . 4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . 10
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 11
3.5 ESD Protection and Latch-Up Immunity . . . . . . 12
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Supply Current Characteristics . . . . . . . . . . . . . 25
3.8 External Oscillator (XOSCVLP) Characteristics 27
3.9 Internal Clock Source (ICS) Characteristics . . . 28
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . .30
3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . . .30
3.10.2TPM Module Timing . . . . . . . . . . . . . . . . .31
3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .32
3.11 Analog Comparator (ACMP) Electricals . . . . . . .35
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .35
3.13 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . .39
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .39
3.15 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .40
3.15.1Radiated Emissions . . . . . . . . . . . . . . . . .40
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.1 Device Numbering System . . . . . . . . . . . . . . . . .41
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
2
9/2008
Initial Release.
10/2008
Updated electrical characteristics.
Corrected 48-Pin QFN/LQFP pinouts for pins 29, 30, 32, and 32 in Figure 3.
Extracted Stop Mode Adders from the Supply Current table and created a Separate
table for the data (See Table 10). Added missing power consumption parameters in
Supply Current Characteristics (Table 9).
3
01/2009
Completed all the TBDs.
Changed V
to V
, V
to V
, I
to I
DDAD
DDA
SSAD
SSA DDAD DDA.
Corrected the data in the Table 8, and added |IInT|. Completed the Figure in the
Section 3.6, “DC Characteristics.”
4
5
07/21/2009
10/13/2009
Corrected RI in FEI mode with all modules on, WI at 8 MHz, FEI mode with all
DD
DD
modules off, S2I , S3I ; added ApS3I in the Table 9.
DD
DD
DD
Corrected E
, DNL, INL, E , E , E , and E in the Table 18.
TUE
ZS FS Q IL
Updated R /R data in the Table 8.
PU PD
Added Figure 5.
Changed the Max. of R /R at PTA[4:5], PTD[0:77] and PTE[0:7] to 69.5 kΩ in the
Table 8.
PU PD
6
7
10/27/2010
1/23/2013
Updated |IIn| in the Table 8.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
2
Freescale Semiconductor
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08LL16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
3
Devices in the MC9S08LL16 Series
1
Devices in the MC9S08LL16 Series
Table 1 summarizes the feature set available in the MC9S08LL16 series of MCUs.
t
Table 1. MC9S08LL16 Series Features by MCU and Package
Feature
MC9S08LL16
MC9S08LL8
64-pin
LQFP
48-pin
QFN/LQFP
48-pin
QFN/LQFP
Package
10,240
(8K and 2K
arrays)
16,384
(Dual 8K Arrays)
FLASH
RAM
ACMP
ADC
IIC
2080
2080
yes
8-ch
yes
yes
8
2080
yes
8-ch
yes
yes
8
yes
8-ch
yes
yes
8
IRQ
KBI
SCI
yes
yes
2-ch
2-ch
Yes
yes
yes
2-ch
-
yes
yes
2-ch
-
SPI
TPM1
TPM2
TOD
Yes
Yes
8x24
4x28
8x16
4x20
8x16
4x20
LCD
I/O pins1
38
31
31
1
I/O does not include two output-only port pins.
The block diagram in Figure 1 shows the structure of the MC9S08LL16 series MCU.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
4
Freescale Semiconductor
Devices in the MC9S08LL16 Series
HCS08 CORE
ON-CHIP ICE
PTA0/KBIP0/SS/ADP0
DEBUG MODULE (DBG)
PTA1/KBIP1/SPSCK/ADP1
PTA2/KBIP2/SDA/MISO/ADP2
PTA3/KBIP3/SCL/MOSI/ADP3
PTA4/KBIP4/ADP4/LCD30
PTA5/KBIP5/ADP5/LCD31
PTA6/KBIP6/ADP6/ACMP+
PTA7/KBIP7/ADP7/ACMP–
CPU
INT
TIME OF DAY MODULE
BKGD
BKP
(TOD)
KBI[7:0]
HCS08 SYSTEM CONTROL
8-BIT KEYBOARD
INTERRUPT (KBI)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
BKGD/MS
SS
SPSCK
MISO
SERIAL PERIPHERAL
PTB7/SS
PTB6/SPSCK
INTERFACE (SPI)
RESET
IRQ
MOSI
COP
SCL
SDA
IRQ
LVD
IIC MODULE (IIC)
PTB5/MOSI/SCL
PTB4/MISO/SDA
TPM2CH0
USER FLASH A
(LL16 = 8K BYTES)
(LL8 = 8K BYTES)
PTB3
PTB2/RESET
TPM2CH1
TCLK
2-CHANNEL TIMER/PWM
(TPM2)
TPM1CH0
PTB1/XTAL
USER FLASH B
(LL16 = 8K BYTES)
(LL8 = 2K BYTES)
PTB0/EXTAL
2-CHANNEL TIMER/PWM
TPM1CH1
TCLK
(TPM1)
PTC7/IRQ/TCLK
PTC6/ACMPO//BKGD/MS
TxD
RxD
SERIAL COMMUNICATIONS
PTC5/TPM2CH1
PTC4/TPM2CH0
USER RAM
INTERFACE (SCI)
(LL16 = 2K BYTES)
(LL8 = 2K BYTES)
PTC3/TPM1CH1
PTC2/TPM1CH0
XTAL
INTERNAL CLOCK
Source (ICS)
PTC1/TxD
PTC0/RxD
EXTAL
LOW-POWER OSCILLATOR
VLCD
VLL1
VLL2
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
AD[7:0]
PTD[7:0]/LCD[7:0]
PTE[7:0]/LCD[15:8]
LIQUID CRYSTAL
DISPLAY DRIVER
LCD
VLL3
VCAP1
VCAP2
ACMP–
ACMP+
ANALOG COMPARATOR
(ACMP)
LCD[31:0]
ACMPO
V
DD
VOLTAGE
REGULATOR
K
EY
Pins not available on 48-pin packages.
LCD[23:16] not available on 48-pin packages.
:
V
SS
Notes: When PTB2 is configured as RESET, pin becomes bi-directional with
V
V
/V
DDA REFH
output being open-drain drive containing an internal pull-up device.
/V
SSA REFL
When PTC6 is configured as BKGD, pin becomes bi-directional.
Figure 1. MC9S08LL16 Series Block Diagram
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
5
Pin Assignments
2
Pin Assignments
This section shows the pin assignments for the MC9S08LL16 series devices.
LCD26
LCD27
LCD28
LCD29
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTE1/LCD9
PTE0/LCD8
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
VCAP1
1
2
3
4
5
6
7
8
PTA5/KBIP5/ADP5/LCD30
PTA4/KBIP4/ADP4/LCD31
PTA3/KBIP3/SCL/MOSI/ADP3
PTA2/KBIP2/SDA/MISO/ADP2
PTA1/KBIP1/SPSCK/ADP1
PTA0/KBIP0/SS/ADP0
PTC7/IRQ/TCLK
PTC6/ACMPO/BKGD/MS
PTC5/TPM2CH1
PTC4/TPM2CH0
64-Pin LQFP
9
10
11
12
13
14
15
16
VCAP2
VLL1
VLL2
VLL3
PTC3/TPM1CH1
PTC2/TPM1CH0
VLCD
Note: VREFH/VREFL are internally connected to VDDA/VSSA
.
Figure 2. MC9S08LL16 Series in 64-pin LQFP Package
MC9S08LL16 Series MCU Data Sheet, Rev. 7
6
Freescale Semiconductor
Pin Assignments
37
48
47 46 45 44 43 42 41 40 39 38
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
LCD28
LCD29
1
36
35
34
33
2
3
4
5
6
7
8
9
PTA5/KBIP5/ADP5/LCD30
PTA4/KBIP4/ADP4/LCD31
PTA3/KBIP3/SCL/MOSI/ADP3
PTA2/KBIP2/SDA/MISO/ADP2
PTA1/KBIP1/SPSCK/ADP1
PTD4/LCD4/
PTD3/LCD3
PTD2/LCD2
32
31
30
29
28
27
26
48-Pin QFN/LQFP
PTD1/LCD1
PTD0/LCD0
VCAP1
PTA0/KBIP0/SS/ADP0
PTC7/IRQ/TCLK
10
11
VCAP2
VLL1
PTC6/ACMPO/BKGD/MS
PTC3/TPM1CH1
PTC2/TPM1CH0
25
VLL2
12
19 20 21 22 23
14 15
17 18
16
24
13
Note: VREFH/VREFL are internally connected to VDDA/VSSA
Figure 3. MC9S08LL16 Series in 48-Pin QFN/LQFP Packages
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
7
Pin Assignments
Table 2. Pin Availability by Package Pin-Count
<-- Lowest Priority --> Highest
64
48
Port Pin
Alt 1
Alt 2
Alt3
Alt4
1
2
47
48
1
PTE1
PTE0
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
LCD9
LCD8
LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
Vcap1
Vcap2
VLL1
3
4
2
5
3
6
4
7
5
8
6
9
7
10
11
12
13
14
15
16
17
18
8
9
10
11
12
13
—
14
15
VLL2
VLL3
VLCD
KBIP6
KBIP7
PTA6
PTA7
ADP6
ADP7
ACMP+
ACMP–
VSSA
19
20
16
17
VREFL
VREFH
VDDA
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
PTB0
PTB1
EXTAL
XTAL
18
19
20
21
22
—
—
—
—
—
23
24
25
26
—
—
27
28
29
VDD
VSS
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTA0
RESET
—
—
—
—
MISO
MOSI
SPSCK
SS
SDA
SCL
RxD
TxD
TPM1CH0
TPM1CH1
TPM2CH0
TPM2CH1
BKGD
ACMPO
KBIP0
MS
IRQ
TCLK
SS
—
ADP0
MC9S08LL16 Series MCU Data Sheet, Rev. 7
8
Freescale Semiconductor
Electrical Characteristics
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest Priority --> Highest
64
48
Port Pin
Alt 1
Alt 2
Alt3
Alt4
40
41
42
43
44
45
46
47
30
31
32
33
34
35
36
37
PTA1
PTA2
PTA3
PTA4
PTA5
KBIP1
KBIP2
KBIP3
KBIP4
KBIP5
LCD29
LCD28
LCD27
—
SPSCK
MISO
ADP1
ADP2
ADP3
SDA
SCL
ADP4
ADP5
MOSI
LCD31
LCD30
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
38
39
40
—
—
—
—
LCD26
LCD25
LCD24
LCD23
LCD22
LCD21
LCD20
LCD19
LCD18
LCD17
LCD16
LCD15
LCD14
LCD13
LCD12
LCD11
LCD10
41
42
43
44
45
46
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08LL16 series of microcontrollers
available at the time of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
9
Electrical Characteristics
Table 3. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
ID
–0.3 to 3.8
120
V
Maximum current into VDD
Digital input voltage
mA
V
–0.3 to VDD + 0.3
± 25
Instantaneous maximum current
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
I
DD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
MC9S08LL16 Series MCU Data Sheet, Rev. 7
10
Freescale Semiconductor
Electrical Characteristics
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range
(packaged)
TL to TH
–40 to 85
TA
°C
°C
Maximum junction temperature
TJM
95
Thermal resistance
Single-layer board
64-pin LQFP
48-pin QFN
48-pin LQFP
72
84
81
θJA
°C/W
°C/W
Thermal resistance
Four-layer board
64-pin LQFP
48-pin QFN
48-pin LQFP
54
30
57
θJA
The average chip-junction temperature (TJ) in °C can be obtained from:
T = T + (P × θ )
JA
Eqn. 3-1
J
A
D
where:
TA = Ambient temperature, °C
JA = Package thermal resistance, junction-to-ambient, °C/W
θ
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
P = K ÷ (T + 273°C)
Eqn. 3-2
Eqn. 3-3
D
J
Solving Equation 3-1 and Equation 3-2 for K gives:
2
K = P × (T + 273°C) + θ × (P )
D
A
JA
D
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
11
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 3-1 and Equation 3-2 iteratively for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
Ω
R1
1500
Human
Body Model
Storage capacitance
C
100
3
pF
Number of pulses per pin
—
Series resistance
R1
0
Ω
Charge
Device
Model
Storage capacitance
C
200
3
pF
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
—
–2.5
7.5
V
V
Latch-up
Table 7. ESD and Latch-Up Protection Characteristics
1
No.
1
Symbol
VHBM
VCDM
ILAT
Min
±2000
±500
±100
Max
—
Unit
V
Rating
Human body model (HBM)
Charge device model (CDM)
Latch-up current at TA = 85°C
2
—
V
3
—
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
12
Freescale Semiconductor
Electrical Characteristics
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num
C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
1
Operating voltage
1.8
3.6
V
PTA[0:3], PTA[6:7],
VDD >1.8 V
ILoad = –0.6 mA
C
PTB[0:7], PTC[0:7]2,
low-drive strength
VDD – 0.5
—
—
Output high
2
VOH
V
DD > 2.7 V
V
P voltage
C
VDD – 0.5
VDD – 0.5
—
—
—
—
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7]2,
high-drive strength
ILoad = –10 mA
V
DD > 1.8 V
ILoad = –3 mA
PTA[4:5], PTD[0:7],
PTE[0:7],
low-drive strength
VDD > 1.8 V
ILoad = –0.5 mA
C
VDD – 0.5
VDD – 0.5
—
—
Output high
3
4
5
VOH
VDD > 2.7 V
ILoad = –3 mA
V
mA
V
P voltage
—
—
—
—
—
PTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
V
DD > 1.8 V
C
V
DD – 0.5
—
ILoad = –1 mA
Output high
current
D
C
Max total IOH for all ports IOHT
100
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
low-drive strength
VDD >1.8 V
ILoad = 0.6 mA
—
—
0.5
Output low
VOL
VDD > 2.7 V
ILoad = 10 mA
P voltage
—
—
—
—
0.5
0.5
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
high-drive strength
VDD > 1.8 V
ILoad = 3 mA
C
PTA[4:5], PTD[0:7],
PTE[0:7],
low-drive strength
VDD > 1.8 V
ILoad = 0.5 mA
C
—
—
0.5
Output low
6
VOL
VDD > 2.7 V
ILoad = 3 mA
V
P voltage
—
—
—
—
—
—
0.5
0.5
PTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
VDD > 1.8 V
ILoad = 1 mA
C
Output low
current
7
8
D
Max total IOL for all ports
all digital inputs
IOLT
VIH
100
mA
V
P
C
P
C
VDD > 2.7 V
VDD > 1.8 V
VDD > 2.7 V
VDD > 1.8 V
0.70 × VDD
—
—
—
—
—
Input high
voltage
0.85 × VDD
—
all digital inputs
all digital inputs
—
—
0.35 x VDD
0.30 x VDD
Input low
voltage
9
VIL
Input
hysteresis
10
C
Vhys
0.06 × VDD
—
—
mV
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
13
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num
C
Characteristic
Symbol
Condition
In = VDD
In = VSS
In = VDD
Min
Typ1
Max
Unit
all input only pins except for
LCD only pins (LCD 16-29)
V
—
0.025
1
μA
V
—
0.025
1
μA
Input leakage
current
11
P
|IIn|
V
—
—
100
150
1
μA
μA
LCD only pins (LCD 16-29)
all input/output
VIn = VSS
0.025
Hi-Z (off-state)
12 P leakage
current
(per pin) |IOZ
|
VIn = VDD or VSS
—
—
0.025
—
1
μA
μA
Total leakage Total leakage current for all
13
P
P
P
|IInT
|
VIn = VDD or VSS
2
current3
pins
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7]
Pullup,
52.5
pulldown
resistors when
enabled
RPU,
RPD
14
—
17.5
—
kΩ
PTA[4:5], PTD[0:7],
PTE[0:7]
69.5
0.2
5
Single pin limit
–0.2
–5
—
—
mA
mA
DC injection
current 4, 5, 6
15
D
IIC
VIN < VSS, VIN > VDD
Total MCU limit, includes
sum of all stressed pins
16 C Input capacitance, all pins
17 C RAM retention voltage
18 C POR re-arm voltage7
19 D POR re-arm time
CIn
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
2.0
—
0.9
10
V
μs
VDD falling
VDD rising
1.80
1.88
1.84
1.92
1.88
1.96
20 P Low-voltage detection threshold
21 P Low-voltage warning threshold
VLVD
VLVW
V
V
VDD falling
VDD rising
2.08
2.14
2.2
22 P Low-voltage inhibit reset/recover hysteresis Vhys
23 P Bandgap voltage reference8
VBG
—
80
—
mV
V
1.15
1.17
1.18
1
2
3
Typical values are measured at 25 °C. Characterized, not tested
All I/O pins except for LCD pins in open drain mode.
Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but
characterization data shows that individual pin leakage current maximums are less than 250 nA.
4
5
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
6
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
7
8
POR will occur below the minimum voltage.
Factory trimmed at VDD = 3.0 V, Temp = 25 °C.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
14
Freescale Semiconductor
Electrical Characteristics
Figure 4. Non-LCD pins I/O Pullup and Pulldown Typical Resistor Values (V = 3.0 V)
DD
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
15
Electrical Characteristics
Figure 5. LCD/GPIO Pins I/O Pullup/Pulldown Typical Resistor Values
MC9S08LL16 Series MCU Data Sheet, Rev. 7
16
Freescale Semiconductor
Electrical Characteristics
Figure 6. Typical Low-Side Driver (Sink) Characteristics (Non-LCD pins)
—
Low Drive (PTxDSn = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
17
Electrical Characteristics
Figure 7. Typical Low-Side Driver (Sink) Characteristics(Non-LCD pins)
—
High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
18
Freescale Semiconductor
Electrical Characteristics
Figure 8. Typical High-Side (Source) Characteristics (Non-LCD Pins)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
— Low Drive (PTxDSn = 0)
Freescale Semiconductor
19
Electrical Characteristics
Figure 9. Typical High-Side (Source) Characteristics(Non-LCD Pins)
— High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
20
Freescale Semiconductor
Electrical Characteristics
Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)
— Low Drive (PTxDSn = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
21
Electrical Characteristics
Figure 11. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO Pins)
—
High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
22
Freescale Semiconductor
Electrical Characteristics
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)
—
Low Drive (PTxDSn = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
23
Electrical Characteristics
Figure 13. Typical High-Side (Source) Characteristics(LCD/GPIO pins)
—
High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
24
Freescale Semiconductor
Electrical Characteristics
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Parameter
VDD
(V)
Bus
Freq
Temp
(°C)
Typ1
Num
C
Symbol
Max
Unit
P
T
T
T
8 MHz
1 MHz
10 MHz
1 MHz
4.2
1
5.7
1.52
—
Run supply current
FEI mode, all modules on
mA
1
RIDD
–40 to 85 °C
–40 to 85 °C
3
3
3.60
0.50
Run supply current
FEI mode, all modules off
2
3
RIDD
mA
—
16 kHz
FBILP
T
T
T
T
T
T
165
105
77
—
—
—
—
—
—
Run supply current
LPRS=0, all modules off
RIDD
3
3
3
μA
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
16 kHz
FBELP
16 kHz
FBILP
Run supply current
LPRS=1, all modules off; running
from Flash
4
5
RIDD
μA
μA
16 kHz
FBELP
21
16 kHz
FBILP
77
Run supply current
LPRS=1, all modules off; running
from RAM
RIDD
16 kHz
FBELP
7.3
P
C
8 MHz
1 MHz
1.4
0.8
1.3
3.5
1.15
—
Wait mode supply current
FEI mode, all modules off
6
7
WIDD
WIDD
3
3
mA
–40 to 85 °C
–40 to 85 °C
Wait mode supply current
LPRS = 1, all modules off
16 kHz
FBELP
μA
T
350
1000
2500
5100
250
930
—
–40 to 25 °C
50 °C
P
n/a
n/a
n/a
n/a
3
2
3
2
4000
—
70 °C
8
Stop2 mode supply current
S2IDD
nA
85 °C
—
–40 to 25 °C
70 °C
C
P
C
2000
4000
400
—
—
85 °C
1030
—
–40 to 25 °C
50 °C
1300
4000
8000
350
6000
—
70 °C
Stop3 mode supply current
No clocks active
9
S3IDD
nA
85 °C
—
–40 to 25 °C
70 °C
3000
6000
—
—
85 °C
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
25
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
Parameter
VDD
(V)
Bus
Freq
Temp
(°C)
Typ1
Num
C
Symbol
Max
Unit
Application Stop3 mode supply
current2
ApS3IDD
10
C
n/a
n/a
3
3
6.1
—
μA
25 °C
50 °C
Application Stop3 mode supply
current2
ApS3IDD
11
C
7.5
—
μA
1
2
Typical values are measured at 25 °C. Characterized, not tested.
32 kHz crystal enabled in low power mode. TOD module enabled. VIREG enabled for 3 V LCD glass 500pf 8x24 LCD glass at
32 Hz frame rate with LCD Charge pump clock set to low setting and every other segment “on.”
Table 10. Stop Mode Adders
Temperature (°C)
Num
C
Parameter
Condition
Units
–40
25
70
85
1
2
3
4
5
6
T
T
T
T
T
T
LPO
100
250
63
100
360
70
150
400
77
175
460
81
nA
nA
μA
nA
μA
μA
ERREFSTEN
IREFSTEN1
TOD
RANGE = HGO = 0
Does not include clock source current
LVDSE = 1
50
50
75
100
115
23
LVD1
110
12
110
12
112
20
ACMP1
Not using the bandgap (BGBE = 0)
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
7
T
ADC1
LCD
95
95
101
120
μA
VIREG enabled for Contrast control, 1/8
Duty cycle, 8x24 configuration for
driving 192 Segments, 32Hz frame rate,
No LCD glass connected.
8
T
1
1
4.2
12
μA
1
Not available in stop2 mode.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
26
Freescale Semiconductor
Electrical Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Refer to Figure 14 and Figure 15 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85 °C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
1
C
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
See Note 2
See Note 3
C1,C2
2
3
D
D
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
—
—
—
—
10
1
—
—
—
RF
MΩ
kΩ
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
—
—
—
—
100
0
—
—
—
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
RS
4
D
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
Crystal start-up time 4
Low range, low power
Low range, high gain
High range, low power
High range, high gain
—
—
—
—
600
400
5
—
—
—
—
t
CSTL
5
6
C
D
ms
t
CSTH
15
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
fextal
0.03125
0
—
—
20
20
MHz
MHz
FBE or FBELP mode
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
27
Electrical Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Average internal reference frequency — factory trimmed at
VDD = 3.6 V and temperature = 25 °C
fint_ft
1
P
—
32.768
—
kHz
fint_t
tIRST
fdco_ut
fdco_t
2
3
4
5
P
T
P
P
Average internal reference frequency - trimmed
Internal reference start-up time
31.25
—
—
—
39.063
6
kHz
μs
DCO output frequency range - untrimmed
DCO output frequency range - trimmed
12.8
16
16.8
—
21.33
20
MHz
MHz
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δfdco_res_t
Δfdco_res_t
Δfdco_t
%fdco
%fdco
%fdco
6
7
8
C
C
C
—
—
—
±0.1
±0.2
±0.2
±0.4
±2
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Total deviation from trimmed DCO output frequency over
voltage and temperature
+ 0.5
–1.0
MC9S08LL16 Series MCU Data Sheet, Rev. 7
28
Freescale Semiconductor
Electrical Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num
9
C
C
C
C
Characteristic
Symbol
Δfdco_t
tAcquire
CJitter
Min
—
Typ1
±0.5
—
Max
±1
Unit
%fdco
ms
Total deviation from trimmed DCO output frequency over
fixed voltage and temperature range of 0
°C to 70 °C
FLL acquisition time 2
10
—
1
Long term jitter of DCO output clock (averaged over 2-ms
interval) 3
%fdco
11
—
0.02
0.2
1
2
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter
percentage for a given interval.
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
29
Electrical Characteristics
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1 Control Timing
Table 13. Control Timing
Num
C
D
D
D
D
Rating
Symbol
fBus
Min
Typ1
—
Max
10
Unit
MHz
μs
Bus frequency (tcyc = 1/fBus
)
1
2
3
4
dc
700
tLPO
Internal low power oscillator period
—
1300
—
External reset pulse width2
Reset low drive
textrst
trstdrv
100
—
ns
34 × tcyc
500
—
—
ns
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
tMSH
5
6
D
D
—
—
—
—
ns
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
100
μs
IRQ pulse width
D
7
8
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
1.5 × tcyc
—
—
—
—
ns
ns
D
Keyboard interrupt pulse width
Asynchronous path2
tILIH, IHIL
t
100
1.5 × tcyc
—
—
—
—
Synchronous path4
Port rise and fall time — Non-LCD Pins
Low output drive (PTxDS = 0) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise, tFall
ns
—
—
16
23
—
—
C
C
9
Port rise and fall time — Non-LCD Pins
High output drive (PTxDS = 1) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
us
—
—
5
9
—
—
tVRR
10
Voltage Regulator Recovery time
—
6
10
1
2
3
Typical values are based on characterization data at VDD = 3.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5
6
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C.
Except for LCD pins in Open Drain mode.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
30
Freescale Semiconductor
Electrical Characteristics
textrst
RESET PIN
Figure 17. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
3.10.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 14. TP Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
31
Electrical Characteristics
t
ICPW
TPMCHn
TPMCHn
t
ICPW
Figure 20. Timer Input Capture Pulse
3.10.3 SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No.
C
Function
Operating frequency
Symbol
Min
Max
Unit
—
D
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
SPSCK period
Master
Slave
D
D
D
D
D
D
tSPSCK
tLead
tLag
2
4
2048
—
tcyc
tcyc
1
2
3
4
5
6
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
D
D
Slave access time
ta
—
—
1
1
tcyc
7
8
9
Slave MISO disable time
tdis
tcyc
Data valid (after SPSCK edge)
Master
Slave
D
tv
—
—
25
25
ns
ns
MC9S08LL16 Series MCU Data Sheet, Rev. 7
32
Freescale Semiconductor
Electrical Characteristics
Table 15. SPI Timing (continued)
No.
C
Function
Symbol
Min
Max
Unit
Data hold time (outputs)
D
Master
Slave
tHO
0
0
—
—
ns
ns
10
Rise time
Input
Output
D
D
tRI
tRO
—
—
tcyc – 25
25
ns
ns
11
12
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
SS1
(OUTPUT)
1
2
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MS BIN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
33
Electrical Characteristics
SS1
(OUTPUT)
1
2
11
12
3
12
11
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
9
MOSI
MASTER MSB OUT2
PORT DATA
(OUTPUT)
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
SS
(INPUT)
11
12
3
1
12
11
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
10
9
10
MISO
(OUTPUT)
SEE
NOTE 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received.
Figure 23. SPI Slave Timing (CPHA = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 7
34
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
1
3
12
2
11
SPSCK
(CPOL = 0)
(INPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(INPUT)
9
10
8
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE
5
MSB OUT
6
NOTE 1
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received.
Figure 24. SPI Slave Timing (CPHA = 1)
3.11 Analog Comparator (ACMP) Electricals
Table 16. Analog Comparator Electrical Specifications
C
Characteristic
Symbol
VDD
Min
Typical
Max
Unit
D
Supply voltage
1.8
—
—
3.6
V
IDDAC
C
D
P
C
Supply current (active)
20
—
35
VDD
40
μA
V
Analog input voltage
VAIN
VAIO
VH
VSS – 0.3
Analog input offset voltage
Analog comparator hysteresis
20
9.0
mV
mV
3.0
—
15.0
IALKG
tAINIT
P
C
Analog input leakage current
—
—
1.0
1.0
μA
μs
Analog comparator initialization delay
—
3.12 ADC Characteristics
Table 17. 12-bit ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Absolute
Delta to VDD (VDD–VDDA
VDDA
ΔVDDA
ΔVSSA
1.8
—
0
3.6
100
100
V
Supply voltage
Ground voltage
2
)
–100
–100
mV
mV
2
Delta to VSS (VSS–VSSA
)
0
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
35
Electrical Characteristics
Characteristic
Table 17. 12-bit ADC Operating Conditions
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Ref Voltage
High
VREFH
VADIN
CADIN
1.8
VREFL
—
VDDA
—
VDDA
VREFH
5.5
V
V
Input Voltage
Input
Capacitance
4.5
pF
Input
Resistance
RADIN
—
5
7
kΩ
kΩ
12-bit mode
fADCK > 4MHz
ADCK < 4MHz
—
—
—
—
2
5
f
Analog Source
Resistance
10-bit mode
ADCK > 4MHz
RAS
External to MCU
f
—
—
—
—
5
10
fADCK < 4MHz
8-bit mode (all valid fADCK
)
—
—
—
10
ADC
High speed (ADLPC = 0)
0.4
8.0
Conversion
Clock Freq.
fADCK
MHz
Low power (ADLPC = 1)
0.4
—
4.0
1
2
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
DC potential difference.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
ADC SAR
ENGINE
input
protection
RAS
RADIN
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 25. ADC Input Impedance Equivalency Diagram
MC9S08LL16 Series MCU Data Sheet, Rev. 7
36
Freescale Semiconductor
Electrical Characteristics
Table 18. 12-bit ADC Characteristics (V
= V
, V
= V
)
SSA
REFH
DDA
REFL
C
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDA
—
—
—
—
120
—
—
—
1
μA
μA
μA
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
T
P
IDDA
IDDA
IDDA
200
290
0.53
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
mA
P
C
P
C
P
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
Low Power (ADLPC=1)
2
1.25
—
3.3
2
5
tADACK
1/fADACK
=
fADACK
MHz
3.3
—
—
—
Conversion
Time(Including
sample time)
Short Sample (ADLSMP=0)
Long Sample (ADLSMP=1)
Short Sample (ADLSMP=0)
20
40
3.5
See ADC
chapter in the
LL16
Reference
Manual for
conversion
time variances
ADCK
cycles
tADC
—
—
ADCK
cycles
Sample Time
tADS
C
T
Long Sample (ADLSMP=1)
—
—
23.5
—
12-bit mode,
3.6>VDDA>2.7V
–2.5 to
5.5
–1 to 3
Total
Unadjusted
Error
12-bit mode,
2.7>VDDA>1.8V
–3.0 to
6.0
Includes
quantization
—
–1 to 3
ETUE
LSB2
P
T
10-bit mode
8-bit mode
—
—
±1
±2.5
±1.0
±0.5
–1.5 to
2.0
T
12-bit mode
—
±1
Differential
Non-Linearity
DNL
INL
LSB2
LSB2
P
T
10-bit mode3
8-bit mode3
—
—
±0.5
±0.3
±1.0
±0.5
–2.5 to
1.0
T
12-bit mode
—
±1.5
Integral
Non-Linearity
P
T
10-bit mode
8-bit mode
—
—
±0.5
±0.3
±1.0
±0.5
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
37
Electrical Characteristics
Table 18. 12-bit ADC Characteristics (V
= V
, V
= V
) (continued)
SSA
REFH
DDA
REFL
Typ1
C
Characteristic
Conditions
12-bit mode
Symb
Min
Max
±2.5
Unit
Comment
T
P
T
—
—
—
±1.5
±0.5
±0.5
Zero-Scale
Error
10-bit mode
8-bit mode
EZS
±1.5
±0.5
LSB2
VADIN = VSSA
–3.5 to
1.0
T
12-bit mode
—
±1
Full-Scale
Error
EFS
LSB2
VADIN = VDDA
P
T
10-bit mode
8-bit mode
—
—
—
—
—
—
—
—
—
—
±0.5
±0.5
±1
±0.5
—
12-bit mode
10-bit mode
8-bit mode
–1 to 0
—
Quantization
Error
D
D
EQ
±0.5
±0.5
—
LSB2
LSB2
—
12-bit mode
10-bit mode
8-bit mode
±2
Input Leakage
Error
Padleakage4 *
RAS
EIL
±0.2
±0.1
1.646
1.769
±4
±1.2
—
–40 °C to 25 °C
25 °C to 85 °C
Temp Sensor
Slope
D
D
m
mV/°C
—
Temp Sensor
Voltage
25 °C
VTEMP25
—
701.2
—
mV
1
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
3
4
1 LSB = (VREFH – VREFL)/2N
Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
Based on input pad leakage current. Refer to pad electricals.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
38
Freescale Semiconductor
Electrical Characteristics
3.13 LCD Specifications
Table 19. LCD Electricals, 3 V Glass
C
Characteristic
Symbol
Min
Typ
Max
Unit
D
LCD Supply Voltage
VLCD
V
0.9
28
1.5
30
1.8
58
D
D
D
D
D
LCD Frame Frequency
fFrame
CLCD
Hz
nF
nF
pF
LCD Charge Pump Capacitance
LCD Bypass Capacitance
LCD Glass Capacitance
VIREG
100
100
2000
1.00
1.67
100
CBYLCD
Cglass
VIREG
100
8000
1.15
1.851
HRefSel = 0
HRefSel = 1
.89
1.49
1.5
V
D
D
V
IREG TRIM Resolution
VIREG Ripple
LCD Buffered Adder2
ΔRTRIM
%
VIREG
HRefSel = 0
HRefSel = 1
0.1
V
0.15
D
V
IBuff
1
μA
1
2
VIREG Max can not exceed VDD – 0.15 V
VSUPPLY = 10, BYPASS = 0
3.14 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
39
Electrical Characteristics
Table 20. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
-40°C to 85°C
D
Vprog/erase
VRead
fFCLK
1.8
1.8
150
5
3.6
3.6
V
D
D
D
P
P
P
P
D
D
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
Mass erase time2
Byte program current3
Page erase current3
V
200
6.67
kHz
μs
tFcyc
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
tBurst
4
4000
20,000
4
tPage
tMass
RIDDBP
RIDDPE
—
—
—
—
6
Program/erase endurance4
TL to TH = –40°C to + 85°C
T = 25°C
C
C
10,000
15
—
100,000
—
—
cycles
years
Data retention5
tD_ret
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
4
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please
refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
3.15 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
3.15.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East).
MC9S08LL16 Series MCU Data Sheet, Rev. 7
40
Freescale Semiconductor
Ordering Information
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal
to the reported emissions levels.
Table 21. Radiated Emissions, Electric Field
Level1
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
Unit
(Max)
VRE_TEM
VDD = 3.3 V
TA = 25 oC
package type
64-pin LQFP
0.15 – 50 MHz
50 – 150 MHz
150 – 500 MHz
500 – 1000 MHz
IEC Level
32 kHz crystal
10 MHz bus
–7
–9
–6
–6
N
dBμV
Radiated emissions,
electric field
—
—
SAE Level
1
1
Data based on qualification test results.
4
Ordering Information
This section contains the ordering information and the device numbering system for the MC9S08LL16
Series.
4.1
Device Numbering System
Example of the device numbering system:
16
C
XX
9
MC S08 LL
Status
(MC = Fully Qualified)
Package designator (see Table 22)
Temperature range
(C = –40 °C to 85 °C)
Memory
(9 = Flash-based)
Core
Approximate FLASH size in KB
Family
5
Package Information and Mechanical Drawings
Table 22 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MC9S08LL16 Series Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
•
•
Click on the appropriate link in Table 22, or
Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate
document number (from Table 22) in the “Enter Keyword” search box at the top of the page.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
41
Package Information and Mechanical Drawings
Table 22. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
64
48
48
Low Quad Flat Package
Low Quad Flat Package
Quad Flat No-Leads
LQFP
LQFP
QFN
LH
LF
840F
932
98ASS23234W
98ASH00962A
98ARH99048A
GT
1314
MC9S08LL16 Series MCU Data Sheet, Rev. 7
42
Freescale Semiconductor
Package Information and Mechanical Drawings
MC9S08LL16 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
43
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MC9S08LL16
Rev. 7
1/2013
MC9S08LL16
Rev. 7, 1/2013
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