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MC9S08MM128VLH64 [NXP]

8-BIT, FLASH, 48MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64;
MC9S08MM128VLH64
型号： MC9S08MM128VLH64
厂家： NXP    NXP
描述：

8-BIT, FLASH, 48MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

时钟 外围集成电路
文件： 总52页 (文件大小：533K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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Freescale Semiconductor  
Document Number: MC9S08MM128  
Rev. 3, 10/2010  
Data Sheet: Technical Data  
An Energy-Efficient Solution from Freescale  
MC9S08MM128 series  
Covers: MC9S08MM128, and MC9S08MM64, MC9S08MM32,  
and MC9S08MM32A  
64-LQFP 10mm x 10mm  
80-LQFP 12mm x 12mm  
81-MapBGA 10mm x10mm  
byte-by-byte data transfer; supports broadcast mode and 11-bit  
addressing  
PRACMP — Analog comparator with selectable interrupt;  
compare option to programmable internal reference voltage;  
operation in stop3  
SCI — Two serial communications interfaces with optional 13-bit  
break; option to connect Rx input to PRACMP output on SCI1 and  
SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from  
stop3 on Rx edge  
SPI1— Serial peripheral interface (SPI) with 64-bit FIFO buffer;  
16-bit or 8-bit data transfers; full-duplex or single-wire  
bidirectional; double-buffered transmit and receive; master or  
slave mode; MSB-first or LSB-first shifting  
8-Bit HCS08 Central Processor Unit (CPU)  
–
Up to 48-MHz CPU above 2.4 V, 40 MHz CPU above 2.1 V, and  
20 MHz CPU above 1.8 V across temperature of -40°C to 105°C  
HCS08 instruction set with added BGND instruction  
Support for up to 33 interrupt/reset sources  
–
–
–
–
On-Chip Memory  
–
128 K Dual Array Flash read/program/erase over full operating  
voltage and temperature  
–
–
12 KB Random-access memory (RAM)  
Security circuitry to prevent unauthorized access to RAM and  
Flash  
–
Power-Saving Modes  
–
–
–
Two ultra-low power stop modes. Peripheral clock enable register  
can disable clocks to unused modules to reduce currents  
Time of Day (TOD) — Ultra-low power 1/4 sec counter with up to  
64s timeout.  
Ultra-low power external oscillator that can be used in stop modes  
to provide accurate clock source to the TOD. 6 usec typical wake  
up time from stop3 mode  
–
–
–
SPI2— Serial peripheral interface with full-duplex or single-wire  
bidirectional; Double-buffered transmit and receive; Master or  
Slave mode; MSB-first or LSB-first shifting  
TPM — Two 4-channel Timer/PWM Module; Selectable input  
capture, output compare, or buffered edge- or center-aligned  
PWM on each channel; external clock input/pulse accumulator  
USB — Supports USB in full-speed device configuration. On-chip  
transceiver and 3.3V regulator help save system cost, fully  
compliant with USB Specification 2.0. Allows control, bulk,  
interrupt and isochronous transfers. Not available on  
MC9S08MM32A devices.  
Clock Source Options  
–
–
–
Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz  
crystal or ceramic resonator dedicated for TOD operation.  
Oscillator (XOSC2) — for high frequency crystal input for MCG  
reference to be used for system clock and USB operations.  
Multipurpose Clock Generator (MCG) — PLL and FLL; precision  
trimming of internal reference allows 0.2% resolution and 2%  
deviation over temperature and voltage; supports CPU  
frequencies from 4 kHz to 48 MHz.  
–
–
ADC16 — 16-bit Successive approximation ADC with up to 4  
dedicated differential channels and 8 single-ended channels;  
range compare function; 1.7 mV/C temperature sensor; internal  
bandgap reference channel; operation in stop3; fully functional  
from 3.6V to 1.8V, Configurable hardware trigger for 8 Channel  
select and result registers  
PDB — Programmable delay block with 16-bit counter and  
modulus and prescale to set reference clock to bus divided by 1 to  
bus divided by 2048; 8 trigger outputs for ADC16 module provides  
periodic coordination of ADC sampling sequence with sequence  
completion interrupt; Back-to-Back mode and Timed mode  
System Protection  
–
Watchdog computer operating properly (COP) reset Watchdog  
computer operating properly (COP) reset with option to run from  
dedicated 1-kHz internal clock source or bus clock  
Low-voltage detection with reset or interrupt; selectable trip points;  
separate low-voltage warning with optional interrupt; selectable  
trip points  
Illegal opcode and illegal address detection with reset  
Flash block protection for each array to prevent accidental  
write/erasure  
–
–
–
–
DAC  
— 12-bit resolution; 16-word data buffers with configurable  
–
–
watermark  
.
OPAMP — Two flexible operational amplifiers configurable for  
general operations; Low offset and temperature drift.  
TRIAMP — Two trans-impedance amplifiers dedicated for  
converting current inputs into voltages.  
–
Hardware CRC to support fast cyclic redundancy checks  
Development Support  
–
–
Single-wire background debug interface  
Input/Output  
Real-time debug with 6 hardware breakpoints (4 PC, 1 address  
and 1 data) Breakpoint capability to allow single breakpoint setting  
during in-circuit debugging  
On-chip in-circuit emulator (ICE) debug module containing 3  
comparators and 9 trigger modes  
–
–
–
Up to 47 GPIOs and 2 output-only pin and 1 input-only pin.  
Voltage Reference output (VREFO).  
Dedicated infrared output pin (IRO) with  
high current sink capability.  
–
–
Up to 16 KBI pins with selectable polarity.  
Peripherals  
Package Options  
–
CMT— Carrier Modulator timer for remote control  
–
–
–
81-MBGA 10x10 mm  
80-LQFP 12x12 mm  
64-LQFP 10x10 mm  
communications. Carrier generator, modulator and driver for  
dedicated infrared out. Can be used as an output compare timer.  
IIC— Up to 100 kbps with maximum bus loading; Multi-master  
operation; Programmable slave address; Interrupt driven  
–
Freescale reserves the right to change the detail specifications as may be required to permit  
improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Contents  
1 Devices in the MC9S08MM128 series. . . . . . . . . . . . . . . . . . . . .3  
1.1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6  
1.1.1 64-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .6  
1.1.2 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .8  
1.1.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .9  
1.2 Pin Assignments by Packages . . . . . . . . . . . . . . . . . . .10  
2.10 MCG and External Oscillator (XOSC) Characteristics .33  
2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .36  
2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .36  
2.11.2 TPM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .38  
2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39  
2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .42  
2.14 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43  
2.15 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .44  
2.16 TRIAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .46  
2.17 OPAMP Electrical Parameters. . . . . . . . . . . . . . . . . . . .47  
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
2.1 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . .13  
2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14  
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15  
2.4 ESD Protection Characteristics . . . . . . . . . . . . . . . . . .16  
2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17  
2.6 Supply Current Characteristics. . . . . . . . . . . . . . . . . . .20  
2.7 PRACMP Electricals. . . . . . . . . . . . . . . . . . . . . . . . . . .23  
2.8 12-Bit DAC Electricals. . . . . . . . . . . . . . . . . . . . . . . . . .24  
2.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .26  
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48  
3.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .48  
3.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .49  
3.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .49  
4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49  
Related Documentation  
Find the most current versions of all documents at: http://www.freescale.com.  
Reference Manual —MC9S08MM128RM  
Contains extensive product information including modes of operation, memory,  
resets and interrupts, register definition, port pins, CPU, and all module  
information.  
–
2
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
1
Devices in the MC9S08MM128 series  
The following table summarizes the feature set available in the MC9S08MM128 series of MCUs.  
Table 1. MC9S08MM128 series Features by MCU and Package  
Feature  
MC9S08MM128  
MC9S08MM64 MC9S08MM32 MC9S08MM32A  
Pin quantity  
81  
80  
131072  
12K  
yes  
yes  
yes  
yes  
yes  
16  
64  
64  
65535  
12K  
yes  
yes  
yes  
yes  
yes  
6
64  
32768  
4K  
64  
32768  
2K  
yes  
yes  
yes  
yes  
yes  
6
FLASH size (bytes)  
RAM size (bytes)  
Programmable Analog Comparator (PRACMP)  
Debug Module (DBG)  
yes  
yes  
yes  
yes  
yes  
6
Multipurpose Clock Generator (MCG)  
Inter-Integrated Communication (IIC)  
Interrupt Request Pin (IRQ)  
Keyboard Interrupt (KBI)  
16  
47  
6
Port I/O1  
46  
33  
33  
33  
33  
Dedicated Analog Input Pins  
Power and Ground Pins  
12  
12  
12  
12  
8
8
8
8
Time Of Day (TOD)  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
4
yes  
yes  
yes  
yes  
yes  
yes  
yes  
4
yes  
yes  
yes  
yes  
yes  
yes  
yes  
4
yes  
yes  
yes  
yes  
yes  
yes  
yes  
4
Serial Communications (SCI1)  
Serial Communications (SCI2)  
Serial Peripheral Interface 1 (SPI1 (FIFO))  
Serial Peripheral Interface 2 (SPI2)  
Carrier Modulator Timer pin (IRO)  
TPM input clock pin (TPMCLK)  
TPM1 channels  
TPM2 channels  
4
4
2
2
2
2
XOSC1  
yes  
yes  
yes  
yes  
4
yes  
yes  
yes  
yes  
3
yes  
yes  
yes  
yes  
3
yes  
yes  
no  
XOSC2  
USB  
Programmable Delay Block (PDB)  
SAR ADC differential channels2  
SAR ADC single-ended channels  
DAC ouput pin (DACO)  
yes  
3
4
8
3
6
8
6
6
6
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
Voltage reference output pin (VREFO)  
General Purpose OPAMP (OPAMP)  
Trans-Impedance Amplifier (TRIAMP)  
1
Port I/O count does not include two (2) output-only and one (1) input-only pins.  
Each differential channel is comprised of 2 pin inputs.  
2
Freescale Semiconductor  
3
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
A complete description of the modules included on each device is provided in the following table.  
Table 2. Versions of On-Chip Modules  
Module  
Version  
Analog-to-Digital Converter (ADC16)  
General Purpose Operational Amplifier (OPAMP)  
Trans-Impedance Operational Amplifier (TRIAMP)  
Digital to Analog Converter (DAC)  
Programmable Delay Block  
1
1
1
1
1
3
5
3
3
1
1
1
4
5
1
1
3
1
3
2
1
1
3
1
2
1
Inter-Integrated Circuit (IIC)  
Central Processing Unit (CPU)  
On-Chip In-Circuit Debug/Emulator (DBG)  
Multi-Purpose Clock Generator (MCG)  
Low Power Oscillator (XOSCVLP)  
Carrier Modulator Timer (CMT)  
Programable Analog Comparator (PRACMP)  
Serial Communications Interface (SCI)  
Serial Peripheral Interface (SPI)  
Time of Day (TOD)  
Universal Serial Bus (USB)1  
Timer Pulse-Width Modulator (TPM)  
System Integration Module (SIM)  
Cyclic Redundancy Check (CRC)  
Keyboard Interrupt (KBI)  
Voltage Reference (VREF)  
Voltage Regulator (VREG)  
Interrupt Request (IRQ)  
Flash Wrapper  
GPIO  
Port Control  
1
USB Module not available on MC9S08MM32A devices.  
The block diagram in Figure 1 shows the structure of the MC9S08MM128 series MCU.  
4
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
Figure 1. MC9S08MM128 series Block Diagram  
Freescale Semiconductor  
5
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
1.1  
Pin Assignments  
This section shows the pin assignments for the MC9S08MM128 series devices.  
1.1.1  
64-Pin LQFP  
The following two figures show the 64-pin LQFP pinout configuration. The first illustrates the pinout configuration for  
MC9S08MM128, MC9S08MM64, and MC9S08MM32 devices.  
PTA0/SS1  
IRO  
PTA4/INP1+  
PTA5  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
PTD7/RX1  
2
PTD6/TX1  
3
PTD5/SCL/TPM1CH3  
PTD4/SDA/TPM1CH2  
PTD3/TPM1CH1  
4
PTA6  
PTA7/INP2+  
5
6
PTD2/TPM1CH0  
PTB0  
PTB1/BLMS  
VSSA  
7
PTD1/CMPP2/RESET  
PTD0/BKGD/MS  
8
64-LQFP  
9
PTC7/KBI2P2/CLKOUT/ADP11  
PTC6/KBI2P1/PRACMPO/ADP10  
PTC5/KBI2P0/CMPP1/ADP9  
PTC4/KBI1P7/CMPP0/ADP8  
PTC3/KBI1P6/SS2/ADP7  
PTC2/KBI1P5/SPSCK2/ADP6  
PTC1/MISO2  
10  
11  
12  
13  
14  
15  
16  
VREFL  
INP1-  
OUT1-  
TRIOUT1/DADP2  
VINP1  
VINN1/DADM2  
INP2-  
PTC0/MOSI2  
Figure 2. 64-Pin LQFP for MC9S08MM128, MC9S08MM64, and MC9S08MM32 devices  
For MC9S08MM32A devices, pins 56, 57, 58, and 59 are no connects (NC) as illustrated in the following figure.  
6
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
PTA0/SS1  
IRO  
PTA4/INP1+  
PTA5  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
PTD7/RX1  
2
PTD6/TX1  
3
PTD5/SCL/TPM1CH3  
PTD4/SDA/TPM1CH2  
PTD3/TPM1CH1  
4
PTA6  
PTA7/INP2+  
5
6
PTD2/TPM1CH0  
PTB0  
PTB1/BLMS  
VSSA  
7
PTD1/CMPP2/RESET  
PTD0/BKGD/MS  
8
64-LQFP  
9
PTC7/KBI2P2/CLKOUT/ADP11  
PTC6/KBI2P1/PRACMPO/ADP10  
PTC5/KBI2P0/CMPP1/ADP9  
PTC4/KBI1P7/CMPP0/ADP8  
PTC3/KBI1P6/SS2/ADP7  
PTC2/KBI1P5/SPSCK2/ADP6  
PTC1/MISO2  
10  
11  
12  
13  
14  
15  
16  
VREFL  
INP1-  
OUT1-  
TRIOUT1/DADP2  
VINP1  
VINN1/DADM2  
INP2-  
PTC0/MOSI2  
Figure 3. 64-Pin LQFP for MC9S08MM32A devices  
Freescale Semiconductor  
7
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
1.1.2  
80-Pin LQFP  
The following figure shows the 80-pin LQFP pinout configuration.  
PTA0/SS1  
IRO  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
PTE4/CMPP3/TPMCLK/IRQ  
PTE3/KBI2P6  
2
PTA1/KBI1P0/TX1  
PTA2/KBI1P1/RX1/ADP4  
PTA3/KBI1P2/ADP5  
PTA4/INP1+  
3
PTE2/KBI2P5  
4
PTE1/KBI2P4  
5
PTE0/KBI2P3  
6
PTD7/RX1  
PTA5  
7
PTD6/TX1  
PTA6  
8
PTD5/SCL/TPM1CH3  
PTD4/SDA/TPM1CH2  
PTD3/TPM1CH1  
PTA7/INP2+  
PTB0  
9
80-LQFP  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
PTB1/BLMS  
VSSA  
PTD2/TPM1CH0  
PTD1/CMPP2/RESET  
PTD0/BKGD/MS  
VREFL  
INP1-  
PTC7/KBI2P2/CLKOUT/ADP11  
PTC6/KBI2P1/PRACMPO/ADP10  
PTC5/KBI2P0/CMPP1/ADP9  
PTC4/KBI1P7/CMPP0/ADP8  
PTC3/KBI1P6/SS2/ADP7  
PTC2/KBI1P5/SPSCK2/ADP6  
PTC1/MISO2  
OUT1-  
TRIOUT1/DADP2  
VINP1  
VINN1/DADM2  
INP2-  
OUT2-  
Figure 4. 80-Pin LQFP  
8
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
1.1.3  
81-Pin MAPBGA  
The following figure shows the 81-pin MAPBGA pinout configuration.  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IRO  
PTG0  
PTF6  
USB_DP  
USB_DM  
PTA1  
VBUS  
PTF5  
PTF2  
PTA2  
VDD3  
VSS3  
VREFO  
PTC3  
PTB2  
VUSB33  
PTE7  
PTE6  
PTA3  
VDD1  
VSS1  
PTB6  
PTC4  
PTB3  
PTF4  
PTF1  
PTE5  
PTD5  
PTD2  
PTB7  
PTC0  
PTD0  
PTD1  
PTF3  
PTF0  
PTE2  
PTD7  
PTD3  
PTC7  
PTC1  
PTC5  
PTB4  
PTE4  
PTE3  
PTE1  
PTE0  
PTD6  
PTD4  
PTC2  
PTC6  
PTB5  
PTF7  
PTA4  
INP1-  
OUT1  
VINP1  
DADP0  
DADM0  
VSSA  
PTA0  
PTG1  
PTA5  
PTA6  
PTA7  
PTB0  
PTB1  
VINN1  
TRIOUT1  
DACO  
DADM1  
VREFL  
OUT2  
INP2-  
VDD2  
VSS2  
G
H
J
TRIOUT2  
DADP1  
VREFH  
VINN2  
VINP2  
VDDA  
Figure 5. 81-Pin MAPBGA  
Freescale Semiconductor  
9
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
1.2  
Pin Assignments by Packages  
Table 3. Package Pin Assignments  
Package  
Default  
Function  
ALT1  
ALT2  
ALT3  
Composite Pin Name  
B2  
1
2
1
2
PTA0  
IRO  
SS1  
—
—
—
—
—
PTA0/SS1  
IRO  
A1  
C4  
D5  
D6  
C1  
C2  
C3  
D2  
D3  
D4  
J1  
3
—
—
—
3
PTA1  
PTA2  
PTA3  
PTA4  
PTA5  
PTA6  
PTA7  
PTB0  
PTB1  
VSSA  
VREFL  
INP1-  
OUT1  
DADP2  
KBI1P0  
KBI1P1  
KBI1P2  
INP1+  
—
TX1  
RX1  
ADP5  
—
—
PTA1/KBI1P0/TX1  
PTA2/KBI1P1/RX1/ADP4  
PTA3/KBI1P2/ADP5  
PTA4/INP1+  
PTA5  
4
ADP4  
—
5
6
—
7
4
—
—
8
5
—
—
—
PTA6  
9
6
INP2+  
—
—
—
PTA7/INP2+  
PTB0  
10  
11  
12  
13  
14  
15  
16  
7
—
—
8
BLMS  
—
—
—
PTB1/BLMS  
VSSA  
9
—
—
J2  
10  
11  
12  
13  
—
—
—
VREFL  
D1  
E1  
F2  
—
—
—
INP1-  
—
—
—
OUT1  
TRIOUT1  
—
—
DADP2/TRIOUT1  
F1  
E2  
F3  
E3  
G2  
G3  
H4  
G4  
G1  
H1  
G5  
H3  
H2  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
—
—
VINP1  
DADM2  
INP2-  
—
VINN1  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VINP1  
DADM2/VINN1  
INP2-  
OUT2  
—
OUT2  
DACO  
—
DACO  
DADP3  
VINP2  
DADM3  
DADP0  
DADM0  
VREFO  
DADP1  
DADM1  
TRIOUT2  
—
DADP3/TRIOUT2  
VINP2  
VINN2  
—
DADM3/VINN2  
DADP0  
—
DADM0  
—
VREFO  
—
DADP1  
—
DADM1  
10  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
Table 3. Package Pin Assignments (Continued)  
Package  
Default  
Function  
ALT1  
ALT2  
ALT3  
Composite Pin Name  
J3  
J4  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
25  
26  
27  
28  
29  
30  
31  
32  
—
—
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
—
—
—
—
49  
VREFH  
VDDA  
VSS2  
PTB2  
PTB3  
VDD2  
PTB4  
PTB5  
PTB6  
PTB7  
PTC0  
PTC1  
PTC2  
PTC3  
PTC4  
PTC5  
PTC6  
PTC7  
PTD0  
PTD1  
PTD2  
PTD3  
PTD4  
PTD5  
PTD6  
PTD7  
PTE0  
PTE1  
PTE2  
PTE3  
PTE4  
—
—
—
—
—
—
VREFH  
VDDA  
F4  
J5  
—
—
—
VSS2  
EXTAL1  
XTAL1  
—
—
—
PTB2/EXTAL1  
J6  
—
—
PTB3/XTAL1  
E4  
J8  
—
—
VDD2  
EXTAL2  
XTAL2  
KBI1P3  
KBI1P4  
MOSI2  
MISO2  
KBI1P5  
KBI1P6  
KBI1P7  
KBI2P0  
KBI2P1  
KBI2P2  
BKGD  
CMPP2  
TPM1CH0  
TPM1CH1  
SDA  
—
—
PTB4/EXTAL2  
J9  
—
—
PTB5/XTAL2  
G6  
F7  
G7  
G8  
G9  
H5  
H6  
H8  
H9  
F8  
H7  
J7  
—
—
PTB6/KBI1P3  
—
—
PTB7/KBI1P4  
—
—
PTC0/MOSI2  
—
—
PTC1/MISO2  
SPSCK2  
SS2  
CMPP0  
CMPP1  
ADP6  
ADP7  
ADP8  
ADP9  
PTC2/KBI1P5/SPSCK2/ADP6  
PTC3/KBI1P6/SS2/ADP7  
PTC4/KBI1P7/CMPP0/ADP8  
PTC5/KBI2P0/CMPP1/ADP9  
PTC6/KBI2P1/PRACMPO/ADP10  
PTC7/KBI2P2/CLKOUT/ADP11  
PTD0/BKGD/MS  
PTD1/CMPP2/RESET  
PTD2TPM1CH0  
PTD3/TPM1CH1  
PTD4/SDA/TPM1CH2  
PTD5/SCL/TPM1CH3  
PTD6/TX1  
PRACMPO ADP10  
CLKOUT  
ADP11  
—
MS  
RESET  
—
E7  
E8  
F9  
D7  
E9  
D8  
D9  
C9  
C8  
B9  
A9  
—
—
—
—
TPM1CH2  
—
SCL  
TPM1CH3  
—
TX1  
—
—
RX1  
—
—
PTD7/RX1  
KBI2P3  
KBI2P4  
KBI2P5  
KBI2P6  
CMPP3  
—
—
—
PTE0/KBI2P3  
—
PTE1/KBI2P4  
—
—
PTE2/KBI2P5  
—
—
PTE3/KBI2P6  
TPMCLK  
IRQ  
PTE4/CMPP3/TPMCLK/IRQ  
Freescale Semiconductor  
11  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Devices in the MC9S08MM128 series  
Table 3. Package Pin Assignments (Continued)  
Package  
Default  
Function  
ALT1  
ALT2  
ALT3  
Composite Pin Name  
F5  
E5  
C7  
C6  
B6  
B8  
B7  
C5  
A8  
A7  
B5  
A6  
B4  
A4  
A5  
F6  
E6  
A3  
B1  
A2  
B3  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
—
50  
51  
52  
53  
—
—
54  
55  
—
—
—
VSS3  
VDD3  
PTE5  
PTE6  
PTE7  
PTF0  
PTF1  
PTF2  
PTF3  
PTF4  
PTF5  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS3  
VDD3  
—
TX2  
—
PTE5/TX2  
RX2  
—
PTE6/RX2  
PTE7/TPM2CH3  
PTF0/TPM2CH2  
PTF1/RX2/TPM2CH1  
PTF2/TX2/TPM2CH0  
PTF3/SCL  
TPM2CH3  
TPM2CH2  
RX2  
—
—
TPM2CH1  
TX2  
TPM2CH0  
SCL  
—
—
—
—
—
—
—
—
—
—
—
—
—
SDA  
KBI2P7  
—
PTF4/SDA  
PTF5/KBI2P7  
VUSB33  
56 VUSB331  
57 USB_DM2  
58 USB_DP3  
—
USB_DM  
—
USB_DP  
59  
60  
61  
62  
63  
64  
—
VBUS4  
VSS1  
VDD1  
PTF6  
PTF7  
PTG0  
PTG1  
—
VBUS  
—
VSS1  
—
VDD1  
MOSI1  
MISO1  
SPSCK1  
—
PTF6/MOSI1  
PTF7/MISO1  
PTG0/SPSCK1  
PTG1  
1
2
3
4
NC on MC9S08MM32A devices.  
NC on MC9S08MM32A devices.  
NC on MC9S08MM32A devices.  
NC on MC9S08MM32A devices.  
12  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2
Electrical Characteristics  
This section contains electrical specification tables and reference timing diagrams for the MC9S08MM128/64/32/32A  
microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing  
specifications.  
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not  
be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for  
production silicon. Finalized specifications will be published after complete characterization and device qualifications have  
been completed.  
NOTE  
The parameters specified in this data sheet supersede any values found in the module  
specifications.  
2.1  
Parameter Classification  
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better  
understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate:  
Table 4. Parameter Classifications  
Those parameters are guaranteed during production testing on each individual device.  
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant  
sample size across process variations.  
Those parameters are achieved by design characterization on a small sample size from typical devices  
under typical conditions unless otherwise noted. All values shown in the typical column are within this  
category.  
T
Those parameters are derived mainly from simulations.  
D
NOTE  
The classification is shown in the column labeled “C” in the parameter tables where  
appropriate.  
Freescale Semiconductor  
13  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.2  
Absolute Maximum Ratings  
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the  
limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional  
operating conditions, refer to the remaining tables in this section.  
Table 5. Absolute Maximum Ratings  
#
Rating  
Symbol  
Value  
Unit  
1
2
3
Supply voltage  
VDD  
IDD  
VIn  
ID  
–0.3 to +3.8  
120  
V
mA  
V
Maximum current into VDD  
Digital input voltage  
–0.3 to VDD + 0.3  
25  
Instantaneous maximum current  
mA  
4
5
Single pin limit (applies to all port pins)1, 2, 3  
Storage temperature range  
Tstg  
–55 to 150  
C  
1
Input must be current limited to the value specified. To determine the value of the required  
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp  
voltages, then use the larger of the two resistance values.  
2
3
All functional non-supply pins are internally clamped to VSS and VDD  
.
Power supply must maintain regulation within operating VDD range during instantaneous and operating  
maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection  
current may flow out of VDD and could result in external power supply going out of regulation. Ensure  
external VDD load will shunt current greater than maximum injection current. This will be the greatest  
risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock  
rate is very low (which would reduce overall power consumption).  
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised  
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this  
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for  
instance, either V or V ).  
SS  
DD  
14  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.3  
Thermal Characteristics  
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power  
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than  
being controlled by the MCU design. In order to take P into account in power calculations, determine the difference between  
I/O  
actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current  
SS  
DD  
(heavy loads), the difference between pin voltage and V or V will be very small.  
SS  
DD  
Table 6. Thermal Characteristics  
#
Symbol  
Rating  
Value  
Unit  
1
TA  
Operating temperature range (packaged):  
MC9S08MM128  
C  
–40 to 105  
–40 to 105  
–40 to 105  
–40 to 105  
135  
MC9S08MM64  
MC9S08MM32  
MC9S08MM32A  
2
3
TJMAX  
Maximum junction temperature  
Thermal resistance1,2,3,4 Single-layer board — 1s  
81-pin MBGA  
C  
JA  
C/W  
77  
55  
68  
80-pin LQFP  
64-pin LQFP  
4
JA  
Thermal resistance1, 2, 3, 4 Four-layer board — 2s2p  
C/W  
81-pin MBGA  
47  
40  
49  
80-pin LQFP  
64-pin LQFP  
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting  
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and  
board thermal resistance.  
2
3
4
Junction to Ambient Natural Convection  
1s — Single layer board, one signal layer  
2s2p — Four layer board, 2 signal and 2 power layers  
The average chip-junction temperature (T ) in C can be obtained from:  
J
T = T + (P   )  
JA  
Eqn. 1  
J
A
D
where:  
T = Ambient temperature, C  
A
= Package thermal resistance, junction-to-ambient, C/W  
JA  
P = P P  
I/O  
D
int  
P = I V , Watts — chip internal power  
int  
DD  
DD  
P
= Power dissipation on input and output pins — user determined  
I/O  
Freescale Semiconductor  
15  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
For most applications, P  P and can be neglected. An approximate relationship between P and T (if P is neglected)  
I/O  
int  
D
J
I/O  
is:  
P = K (T + 273C)  
Eqn. 2  
D
J
Solving Equation 1 and Equation 2 for K gives:  
K = P (T + 273C) +   (P )  
2
Eqn. 3  
D
A
JA  
D
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)  
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively  
A
D
J
for any value of T .  
A
2.4  
ESD Protection Characteristics  
Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling  
precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices  
can withstand exposure to reasonable levels of static without suffering any permanent damage.  
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits.  
(http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.  
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification  
requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room  
temperature followed by hot temperature, unless specified otherwise in the device specification.  
Table 7. ESD and Latch-up Test Conditions  
Model  
Description  
Symbol  
Value  
Unit  
Human Body  
Series Resistance  
R1  
C
1500  
100  
3
pF  
—
Storage Capacitance  
Number of Pulse per pin  
Series Resistance  
—
R1  
C
Machine  
Latch-up  
0
Storage Capacitance  
200  
3
pF  
—
V
Number of Pulse per pin  
Minimum input voltage limit  
Maximum input voltage limit  
—
—
—
–2.5  
7.5  
V
Table 8. ESD and Latch-Up Protection Characteristics  
#
Rating  
Symbol  
Min  
Max  
Unit  
C
1
2
3
4
Human Body Model (HBM)  
Machine Model (MM)  
VHBM  
VMM  
VCDM  
ILAT  
2000  
200  
500  
00  
—
—
—
—
V
V
T
T
T
T
Charge Device Model (CDM)  
Latch-up Current at TA = 125C  
V
mA  
16  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.5  
DC Characteristics  
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various  
operating modes.  
Table 9. DC Characteristics  
Num Symbol  
Characteristic  
Condition  
Min  
Typ1  
Max  
Unit  
C
VDD Operating  
—
1.82  
—
3.6  
V
1
2
—
Voltage  
VOH Output high  
voltage  
All I/O pins, low-drive strength  
VDD 1.8 V,  
ILoad = –600 A  
VDD – 0.5  
VDD – 0.5  
—
—
V
C
All I/O pins, high-drive strength  
VDD 2.7 V,  
ILoad = –10 mA  
—
—
—
—
V
V
P
C
VDD 1.8V,  
ILoad = –3 mA  
VDD – 0.5  
IOHT Output high  
current  
Max total IOH for all ports  
3
4
—
—
—
—
—
100  
0.5  
mA  
V
D
C
VOL Output low  
voltage  
All I/O pins, low-drive strength  
VDD 1.8 V,  
ILoad = 600 A  
All I/O pins, high-drive strength  
VDD 2.7 V,  
ILoad = 10 mA  
—
—
—
—
—
—
0.5  
0.5  
100  
V
V
P
C
D
VDD 1.8 V,  
ILoad = 3 mA  
IOLT Output low  
current  
Max total IOL  
for all ports  
—
mA  
5
6
VIH  
Input high voltage all digital inputs  
all digital inputs, 0.70 x VDD  
VDD 2.7 V  
—
—
—
—
V
V
P
P
all digital inputs, 0.85 x VDD  
2.7 V > VDD  
1.8 V  
Freescale Semiconductor  
17  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Num Symbol  
Table 9. DC Characteristics (Continued)  
Characteristic  
Input low voltage all digital inputs  
Condition  
Min  
Typ1  
Max  
Unit  
C
7
VIL  
all digital inputs,  
VDD 2.7 V  
—
—
—
—
0.35 x  
VDD  
V
V
P
all digital inputs,  
2.7 VDD 1.8  
V
0.30 x  
VDD  
P
C
P
8
9
Vhys Input hysteresis  
all digital inputs  
—
0.06 x VDD  
—
—
—
—
mV  
|IIn|  
Input leakage  
current  
all input only VIn = VDD or VSS  
0.5  
A  
pins  
(Per pin)  
|IOZ| Hi-Z (off-state)  
leakage current3  
all digital VIn = VDD or VSS  
input/output  
—
0.003  
0.5  
A  
10  
11  
12  
P
P
P
(per pin)  
RPU Pull-up resistors  
—
17.5  
17.5  
—
—
52.5  
52.5  
k  
k  
RPD Internal  
pull-down  
—
resistors4  
IIC  
DC injection  
current 5, 6, 7  
Single pin limit  
13  
VSS > VIN > VDD  
–0.2  
—
0.2  
mA  
D
Total MCU limit, includes sum of all stressed pins  
VSS > VIN > VDD  
–5  
—
—
—
5
8
mA  
pF  
V
D
C
C
C
D
14  
15  
16  
17  
CIn  
Input Capacitance, all pins  
—
—
—
—
VRAM RAM retention voltage  
VPOR POR re-arm voltage8  
—
0.6  
1.4  
—
1.0  
1.79  
—
0.9  
10  
V
tPOR POR re-arm time  
s  
9
VLVDH Low-voltage  
detection  
VDD falling  
18  
threshold —  
high range  
—
—
2.11  
2.16  
2.16  
2.23  
2.22  
2.27  
V
V
P
P
VDD rising  
VDD falling  
VLVDL Low-voltage  
detection  
19  
threshold —  
low range9  
—
—
1.80  
1.88  
1.84  
1.93  
1.88  
1.96  
V
V
P
P
VDD rising  
18  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 9. DC Characteristics (Continued)  
Num Symbol  
Characteristic  
Condition  
Min  
Typ1  
Max  
Unit  
C
VLVWH Low-voltage  
VDD falling  
warning  
20  
threshold —  
high range9  
—
—
2.36  
2.36  
2.46  
2.46  
2.56  
2.56  
V
V
P
P
VDD rising  
VDD falling  
VLVWL Low-voltage  
warning  
21  
threshold —  
low range9  
—
2.11  
2.16  
2.22  
V
P
VDD rising  
—
—
—
2.16  
—
2.23  
50  
2.27  
—
V
mV  
V
P
C
P
Vhys Low-voltage inhibit reset/recover  
hysteresis10  
22  
23  
VBG Bandgap Voltage Reference11  
1.15  
1.17  
1.18  
1
2
3
Typical values are measured at 25C. Characterized, not tested  
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL  
.
Does not include analog module pins. Dedicated analog pins should not be pulled to VDD or VSS and should be left  
floating when not used to reduce current leakage.  
4
5
6
Measured with VIn = VDD  
.
All functional non-supply pins are internally clamped to VSS and VDD except PTD1.  
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,  
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.  
7
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum  
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD  
and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater  
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are:  
if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).  
8
9
Maximum is highest voltage that POR is guaranteed.  
Run at 1 MHz bus frequency  
10 Low voltage detection and warning limits measured at 1 MHz bus frequency.  
11 Factory trimmed at VDD = 3.0 V, Temp = 25C  
Freescale Semiconductor  
19  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.6  
Supply Current Characteristics  
Table 10. Supply Current Characteristics  
Bus  
Freq  
Temp  
(C)  
#
Symbol  
Parameter  
VDD (V)  
Typ1  
Max  
Unit  
C
RIDD  
Run supply FEI mode; all modules ON2  
current  
1
3
–40 to  
25  
24 MHz  
24 MHz  
20 MHz  
20  
20  
18  
24  
24  
—
mA  
mA  
mA  
P
P
T
3
3
105  
–40 to  
105  
3
3
–40 to  
105  
8 MHz  
8
—
—
mA  
mA  
T
T
–40 to  
105  
1 MHz  
1.8  
RIDD  
Run supply FEI mode; all modules OFF3  
current  
2
–40 to  
105  
24 MHz  
20 MHz  
8 MHz  
1 MHz  
3
12.3  
10.5  
4.8  
14.1  
—
mA  
mA  
mA  
mA  
C
T
T
T
–40 to  
105  
3
3
–40 to  
105  
—
3
–40 to  
105  
1.3  
—
RIDD  
Run supply LPS=0; all modules OFF3  
current  
3
4
16 kHz  
FBILP  
3
3
–40 to  
105  
153  
143  
222  
200  
A  
A  
T
T
16 kHz  
FBELP  
–40 to  
105  
LPS=1, all modules OFF3  
Run supply  
RIDD  
current  
16 kHz  
FBELP  
3
3
20  
20  
26  
70  
A  
A  
0 to 70  
T
T
16 kHz  
FBELP  
–40 to  
105  
20  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Temp  
Table 10. Supply Current Characteristics (Continued)  
Bus  
#
Symbol  
Parameter  
VDD (V)  
Typ1  
Max  
Unit  
C
Freq  
FEI mode, all modules OFF3  
(C)  
Wait mode  
supply current  
WIDD  
5
3
–40 to  
105  
24 MHz  
20 MHz  
8 MHz  
1 MHz  
6.7  
5.6  
2.4  
1
—
—
—
—
mA  
mA  
mA  
mA  
C
T
T
T
3
3
3
–40 to  
105  
–40 to  
105  
–40 to  
105  
Low-Power  
Wait mode  
LPWIDD  
6
7
supply current  
3
–40 to  
105  
16 KHz  
10  
40  
µA  
T
Stop2 mode  
supply cur-  
rent4  
S2IDD  
3
–40 to  
25  
N/A  
0.39  
0.8  
µA  
P
N/A  
N/A  
N/A  
3
3
3
2
2.4  
7
4.5  
11  
22  
µA  
µA  
µA  
70  
85  
C
C
P
16  
105  
–40 to  
25  
N/A  
0.2  
0.45  
µA  
C
N/A  
N/A  
N/A  
2
2
2
2
8
3.8  
12  
20  
µA  
µA  
µA  
70  
85  
C
C
C
10  
105  
Freescale Semiconductor  
21  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 10. Supply Current Characteristics (Continued)  
Bus  
Temp  
(C)  
#
Symbol  
Parameter  
VDD (V)  
Typ1  
Max  
Unit  
C
Freq  
Stop3 mode  
No clocks active  
S3IDD  
supply  
current4  
3
–40 to  
25  
N/A  
0.55  
0.9  
µA  
P
N/A  
N/A  
N/A  
3
3
3
2
5.5  
14  
8.9  
18  
µA  
µA  
µA  
70  
85  
C
C
P
8
37  
42  
105  
0.35  
0.5  
–40 to  
25  
N/A  
µA  
C
N/A  
N/A  
N/A  
2
2
2
3.8  
14  
25  
6.8  
20  
46  
µA  
µA  
µA  
70  
85  
C
C
C
105  
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.  
ON = System Clock Gating Control registers turn on system clock to the corresponding modules.  
OFF = System Clock Gating Control registers turn off system clock to the corresponding modules.  
All digital pins must be configured to a known state to prevent floating pins from adding current. Smaller packages  
may have some pins that are not bonded out; however, software must still be configured to the largest pin package  
available so that all pins are in a known state. Otherwise, floating pins that are not bonded in the smaller packages  
may result in a higher current draw.  
NOTE: I/O pins are configured to output low, input-only pins are configured to pullup enabled. IRO pin connects to  
ground. TRIAMPx, OPAMPx, DACO, and VREFO pins are at reset state and unconnected.  
Table 11. Typical Stop Mode Adders  
Temperature (°C)  
#
Parameter  
Condition  
Units  
C
–40  
25  
70  
85  
105  
1
2
3
LPO  
—
50  
600  
—
75  
650  
73  
100  
750  
80  
150  
850  
92  
250  
1000  
125  
nA  
nA  
µA  
nA  
D
D
T
EREFSTEN RANGE = HGO = 0  
IREFSTEN1  
—
TOD  
Does not include clock source  
current  
50  
75  
100  
150  
250  
D
4
5
PRACMP1  
ADC1  
Not using the bandgap  
(BGBE = 0)  
30  
35  
40  
55  
75  
µA  
µA  
T
T
ADLPC = ADLSMP = 1  
Not using the bandgap  
(BGBE = 0)  
190  
195  
210  
220  
260  
6
22  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 11. Typical Stop Mode Adders (Continued)  
Temperature (°C)  
Condition  
#
Parameter  
Units  
C
–40  
25  
70  
85  
105  
DAC1  
High-Power mode; no load on  
DACO  
369  
377  
377  
390  
410  
µA  
T
7
Low-Power mode  
High-Power mode  
Low-Power mode  
High-Power mode  
Low-Power mode  
50  
453  
56  
51  
538  
67  
51  
538  
67  
52  
540  
68  
60  
540  
70  
µA  
µA  
µA  
µA  
µA  
T
T
T
T
T
OPAMP1  
TRIAMP1  
8
9
430  
52  
432  
52  
433  
52  
438  
55  
478  
60  
1
Not available in stop2 mode.  
2.7  
PRACMP Electricals  
Table 12. PRACMP Electrical Specifications  
#
Characteristic  
Supply voltage  
Symbol  
Min  
Typical  
Max  
Unit  
C
1
2
3
VPWR  
IDDACT1  
IDDACT2  
IDDDIS  
1.8  
—
—
—
—
—
—
—
3.6  
80  
40  
2
V
P
D
D
D
Supply current (active) (PRG enabled)  
Supply current (active) (PRG disabled)  
A  
A  
nA  
Supply current (ACMP and PRG all  
disabled)  
4
5
6
7
8
9
Analog input voltage  
VAIN  
VAIO  
V
SS – 0.3  
—
—
5
VDD  
40  
V
mV  
mV  
nA  
s  
V
D
D
D
D
D
D
D
Analog input offset voltage  
Analog comparator hysteresis  
Analog input leakage current  
Analog comparator initialization delay  
VH  
3.0  
—
—
—
—
—
1
20.0  
1
IALKG  
tAINIT  
VIn2 (VDD25  
tPRGST  
—
1.0  
2.75  
—
10 Programmable reference generator inputs  
)
1.8  
—
Programmable reference generator setup  
delay  
µs  
11  
Programmable reference generator step  
size  
Vstep  
0.75  
1
1.25  
Vin  
LSB  
V
D
P
12  
Programmable reference generator voltage  
range  
Vprgout  
VIn/32  
—
13  
Freescale Semiconductor  
23  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.8  
12-Bit DAC Electricals  
Table 13. DAC 12LV Operating Requirements  
#
Characteristic  
Supply voltage  
Symbol  
Min  
Max  
Unit  
C
Notes  
1.8  
3.6  
V
V
P
1
2
3
VDDA  
VDACR  
TA  
1.15  
–40  
3.6  
C
C
Reference voltage  
Temperature  
105  
°C  
A small load capacitance  
(47 pF) can improve the  
bandwidth performance  
of the DAC.  
Output load capacitance  
CL  
—
—
100  
1
pF  
mA  
C
C
4
5
Output load current  
IL  
Table 14. DAC 12-Bit Operating Behaviors  
#
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
C
Notes  
1
Resolution  
N
12  
—
12  
bit  
T
µA  
Supply current low-power mode  
IDDA_DACLP  
—
—
50  
100  
500  
T
T
2
3
345  
µA  
Supply current high-power mode  
IDDA_DACHP  
TsFSLP  
• VDDA = 3 V  
or 2.2 V  
Full-scale Settling time  
(±1 LSB)  
• VREFSEL = 1  
• Temperature  
= 25°C  
—
—
—
—
200  
30  
µs  
µs  
T
T
4
5
(0x080 to 0xF7F or 0xF7F to  
0x080)  
low-power mode  
• VDDA = 3 V  
or 2.2 V  
• VREFSEL = 1  
• Temperature  
= 25°C  
Full-scale Settling time  
(±1 LSB)  
(0x080 to 0xF7F or 0xF7F to  
0x080)  
TsFSHP  
TsC-CLP  
TsC-CHP  
high-power mode  
• VDDA = 3 V  
or 2.2 V  
• VREFSEL = 1  
• Temperature  
= 25°C  
Code-to-code Settling time  
(±1 LSB)  
(0xBF8 to 0xC08 or 0xC08 to  
0xBF8)  
6
—
—
5
µs  
T
low-power mode  
• VDDA = 3 V  
or 2.2 V  
• VREFSEL = 1  
• Temperature  
= 25°C  
Code-to-code Settling time  
(±1 LSB)  
(0xBF8 to 0xC08 or 0xC08 to  
0xBF8)  
high-power mode (3 V at Room  
Temperature)  
—
—
1
—
µs  
T
T
7
8
DAC output voltage range low  
(high-power mode, no load, DAC  
set to 0) (3 V at Room  
Vdacoutl  
—
100  
mV  
Temperature)  
24  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 14. DAC 12-Bit Operating Behaviors (Continued)  
#
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
C
Notes  
DAC output voltage range high  
(high-power mode, no load, DAC  
set to 0x0FFF)  
Vdacouth  
VDACR  
100  
-
—
—
mV  
T
9
10  
11  
Integral non-linearity error  
INL  
—
—
—
—
± 8  
± 1  
LSB  
LSB  
T
T
Differential non-linearity error  
VDACR is > 2.4 V  
DNL  
Calculated by a  
best fit curve  
Offset error  
EO  
—
±0.4  
± 3  
%FSR  
T
from VSS +  
12  
100mV to  
VREFH –100mV  
Calculated by a  
best fit curve  
Gain error, V  
= Vext = VDD  
EG  
REFH  
from VSS  
+
—
±0.1  
—
± 0.5  
—
%FSR  
dB  
T
T
13  
14  
100mV to  
VREFH –100mV  
Power supply rejection ratio  
VDD 2.4 V  
PSRR  
Tco  
60  
See Typical  
Drift figure that  
follows.  
Temperature drift of offset voltage  
(DAC set to 0x0800)  
—
—
—
—
2
8
mV  
T
T
15  
16  
µV/yr  
Offset aging coefficient  
Ac  
Figure 6. Offset at Half Scale vs Temperature  
Freescale Semiconductor  
25  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.9  
ADC Characteristics  
Table 15. 16-Bit ADC Operating Conditions  
#
Symb Characteristic  
Conditions  
Min  
Typ1  
Max  
Unit  
C
Comment  
1
VDDA Supply voltage Absolute  
1.8  
—
0
3.6  
V
D
VDDA  
Delta to VDD  
(VDD–VDDA  
–100  
+100  
2
3
mV  
mV  
D
D
2
)
VSSA Ground voltage  
Delta to VSS2  
–100  
0
+100  
(VSS–VSSA  
)
4
5
6
VREFH Ref Voltage High  
VREFL Ref Voltage Low  
VADIN Input Voltage  
1.15  
VSSA  
VREFL  
—
VDDA VDDA  
VSSA VSSA  
V
V
V
D
D
D
—
VREFH  
CADIN Input  
Capacitance  
16-bit modes  
8/10/12-bit modes  
8
4
10  
5
7
8
pF  
T
T
RADIN Input Resistance  
—
2
5
k  
RAS Analog Source  
Resistance  
External to  
MCU  
Assumes  
ADLSMP=0  
9
16-bit mode  
—
—
—
—
0.5  
1
k  
T
fADCK > 8 MHz  
4 MHz < fADCK < 8  
MHz  
k  
k  
k  
T
T
T
f
ADCK < 4 MHz  
—
—
—
—
2
1
13/12-bit mode  
11/10-bit mode  
9/8-bit mode  
fADCK > 8 MHz  
4 MHz < fADCK < 8  
MHz  
—
—
2
k  
k  
k  
T
T
T
fADCK < 4 MHz  
—
—
—
—
5
2
f
ADCK > 8 MHz  
4 MHz < fADCK < 8  
MHz  
—
—
5
k  
k  
k  
k  
T
T
T
T
f
ADCK < 4 MHz  
—
—
—
—
10  
5
fADCK > 8 MHz  
ADCK < 8 MHz  
f
—
—
10  
26  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 15. 16-Bit ADC Operating Conditions (Continued)  
#
Symb Characteristic  
Conditions  
Min  
Typ1  
Max  
Unit  
C
Comment  
fADCK ADC Conversion Clock  
Frequency  
10  
ADLPC=0, ADHSC=1  
1.0  
1.0  
—
—
8.0  
5.0  
MHz  
MHz  
D
D
ADLPC=0, ADHSC=0  
ADLPC=1, ADHSC=0  
1.0  
—
2.5  
MHz  
D
1
2
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for  
reference only and are not tested in production.  
DC potential difference.  
SIMPLIFIED  
INPUT PIN EQUIVALENT  
ZADIN  
CIRCUIT  
SIMPLIFIED  
CHANNEL SELECT  
CIRCUIT  
Pad  
ZAS  
leakage  
due to  
ADC SAR  
ENGINE  
input  
protection  
RAS  
RADIN  
+
VADIN  
–
CAS  
VAS  
+
–
RADIN  
RADIN  
RADIN  
INPUT PIN  
INPUT PIN  
INPUT PIN  
CADIN  
Figure 7. ADC Input Impedance Equivalency Diagram  
Freescale Semiconductor  
27  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 16. 16-Bit SAR ADC Characteristics full operating range  
(V  
= VDDA, > 1.8, V  
= VSSA 8 MHz, –40 to 85 °C)  
REFH  
REFL  
#
Characteristic  
Conditions1  
Symb  
Min  
Typ2  
Max  
Unit  
C
Comment  
Supply Current  
ADLPC=1, ADHSC=0  
ADLPC=0, ADHSC=0  
ADLPC=0, ADHSC=1  
Stop, Reset, Module Off  
ADLPC=1, ADHSC=0  
ADLPC=0, ADHSC=0  
ADLPC=0, ADHSC=1  
—
—
—
—
—
—
—
215  
470  
610  
0.01  
2.4  
—
—
—
—
—
—
—
ADLSMP  
=0  
ADCO=1  
1
2
3
IDDAD  
A  
A  
T
Supply Current  
IDDAD  
T
ADC  
Asynchronous  
Clock Source  
C
5.2  
fADACK  
MHz  
tADACK =  
1/fADACK  
6.2  
4
5
Sample Time  
See Reference Manual for sample times  
See Reference Manual for conversion times  
Conversion  
Time  
Total  
Unadjusted  
Error  
16-bit differential mode  
16-bit single-ended mode  
TUE  
—
—
16  
20  
48/ –40  
56/ –28  
LSB3  
T
32x  
Hardware  
Averaging  
(AVGE =  
%1  
6
AVGS =  
%11)  
13-bit differential mode  
12-bit single-ended mode  
—
—
1.5  
1.75  
3.0  
3.5  
T
T
T
T
T
T
T
11-bit differential mode  
10-bit single-ended mode  
—
—
0.7  
0.8  
1.5  
1.5  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.5  
0.5  
1.0  
1.0  
Differential  
Non-Linearity  
16-bit differential mode  
16-bit single-ended mode  
DNL  
—
—
2.5  
2.5  
5/–3  
+5/–3  
LSB2  
7
13-bit differential mode  
12-bit single-ended mode  
—
—
0.7  
0.7  
1  
1  
11-bit differential mode  
10-bit single-ended mode  
—
—
0.5  
0.5  
0.75  
0.75  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.2  
0.2  
0.5  
0.5  
28  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 16. 16-Bit SAR ADC Characteristics full operating range  
(V  
= VDDA, > 1.8, V  
= VSSA 8 MHz, –40 to 85 °C) (Continued)  
REFH  
REFL  
#
Characteristic  
Conditions1  
Symb  
Min  
Typ2  
Max  
Unit  
C
Comment  
Integral  
Non-Linearity  
16-bit differential mode  
16-bit single-ended mode  
INL  
—
—
6.0  
10.0  
16.0  
20.0  
LSB2  
T
8
13-bit differential mode  
12-bit single-ended mode  
—
—
1.0  
1.0  
2.5  
2.5  
T
T
T
T
T
T
T
T
T
T
T
D
11-bit differential mode  
10-bit single-ended mode  
—
—
0.5  
0.5  
1.0  
1.0  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.3  
0.3  
0.5  
0.5  
Zero-Scale  
Error  
16-bit differential mode  
16-bit single-ended mode  
EZS  
—
—
4.0  
4.0  
+32/ –24  
+24/ –16  
LSB2  
VADIN  
VSSA  
=
9
13-bit differential mode  
12-bit single-ended mode  
—
—
0.7  
0.7  
2.5  
2.0  
11-bit differential mode  
10-bit single-ended mode  
—
—
0.4  
0.4  
1.0  
1.0  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.2  
0.2  
0.5  
0.5  
Full-Scale Error 16-bit differential mode  
16-bit single-ended mode  
EFS  
—
—
+10/0  
+14/0  
+42/–2  
+46/–2  
LSB2  
VADIN =  
VDDA  
10  
13-bit differential mode  
12-bit single-ended mode  
—
—
1.0  
1.0  
3.5  
3.5  
11-bit differential mode  
10-bit single-ended mode  
—
—
0.4  
0.4  
1.5  
1.5  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.2  
0.2  
0.5  
0.5  
Quantization  
Error  
16-bit modes  
EQ  
—
–1 to 0  
—
LSB2  
Bits  
11  
<13-bit modes  
—
—
0.5  
Effective  
Number of Bits  
16-bit differential mode  
Avg=32  
Avg=16  
Avg=8  
Avg=4  
ENOB  
C
Fin =  
12.8  
12.7  
12.6  
12.5  
11.9  
14.2  
13.8  
13.6  
13.3  
12.5  
—
—
—
—
—
Fsample/10  
0
12  
13  
Avg=1  
Signal to Noise  
plus Distortion  
See ENOB  
SINAD  
dB  
SINAD = 6.02 ENOB + 1.76  
Freescale Semiconductor  
29  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
(V  
Table 16. 16-Bit SAR ADC Characteristics full operating range  
= VDDA, > 1.8, V  
= VSSA 8 MHz, –40 to 85 °C) (Continued)  
REFH  
REFL  
#
Characteristic  
Conditions1  
Symb  
Min  
Typ2  
Max  
Unit  
C
Comment  
Fin  
Total Harmonic  
Distortion  
16-bit differential mode  
Avg=32  
THD  
C
=
14  
—
—
–91.5  
–85.5  
92.2  
–74.3  
—
dB  
Fsample/10  
0
16-bit single-ended mode  
Avg=32  
D
C
D
D
Spurious Free  
Dynamic  
Range  
16-bit differential mode  
Avg=32  
SFDR  
dB  
Fin =  
15  
16  
75.0  
—
—
Fsample/10  
0
16-bit single-ended mode  
Avg=32  
86.2  
—
Input Leakage  
Error  
all modes  
EIL  
IIn * RAS  
mV  
IIn =  
leakage  
current  
(refer to  
DC  
characteri  
stics)  
Temp Sensor  
Slope  
m
—
1.646  
—
mV/×  
C
C
C
17  
18  
–40C – 25C  
25C – 125C  
25C  
—
—
1.769  
718.2  
—
—
Temp Sensor  
Voltage  
VTEMP2  
mV  
5
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA  
Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference  
only and are not tested in production.  
1 LSB = (VREFH – VREFL)/2N  
3
30  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 17. 16-bit SAR ADC Characteristics full operating range  
(V = V , 2.7 V, V = V , f 4 MHz, ADHSC = 1)  
REFH  
DDA  
REFL  
SSA ADACK  
#
Characteristic  
Conditions1  
Symb  
Min  
Typ2  
Max  
Unit  
C
Comment  
Total  
Unadjusted  
Error  
16-bit differential mode  
16-bit single-ended mode  
TUE  
—
—
16  
20  
24/ –24  
32/–20  
LSB3  
T
32x  
Hardware  
Averaging  
(AVGE =  
%1  
1
AVGS =  
%11)  
13-bit differential mode  
12-bit single-ended mode  
—
—
1.5  
1.75  
2.0  
2.5  
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
11-bit differential mode  
10-bit single-ended mode  
—
—
0.7  
0.8  
1.0  
1.25  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.5  
0.5  
1.0  
1.0  
Differential  
Non-Linearity  
16-bit differential mode  
16-bit single-ended mode  
DNL  
—
—
2.5  
2.5  
3  
3  
LSB2  
LSB2  
LSB2  
2
3
4
13-bit differential mode  
12-bit single-ended mode  
—
—
0.7  
0.7  
1  
1  
11-bit differential mode  
10-bit single-ended mode  
—
—
0.5  
0.5  
0.75  
0.75  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.2  
0.2  
0.5  
0.5  
Integral  
Non-Linearity  
16-bit differential mode  
16-bit single-ended mode  
INL  
—
—
6.0  
10.0  
12.0  
16.0  
13-bit differential mode  
12-bit single-ended mode  
—
—
1.0  
1.0  
2.0  
2.0  
11-bit differential mode  
10-bit single-ended mode  
—
—
0.5  
0.5  
1.0  
1.0  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.3  
0.3  
0.5  
0.5  
Zero-Scale  
Error  
16-bit differential mode  
16-bit single-ended mode  
EZS  
—
—
4.0  
4.0  
+16/0  
+16/-8  
VADIN  
=
VSSA  
13-bit differential mode  
12-bit single-ended mode  
—
—
0.7  
0.7  
2.0 2.0  
11-bit differential mode  
10-bit single-ended mode  
—
—
0.4  
0.4  
1.0  
1.0  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.2  
0.2  
0.5  
0.5  
Freescale Semiconductor  
31  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 17. 16-bit SAR ADC Characteristics full operating range  
= V , 2.7 V, V = V , f 4 MHz, ADHSC = 1) (Continued)  
(V  
REFH  
DDA  
REFL  
SSA ADACK  
#
Characteristic  
Conditions1  
Symb  
Min  
Typ2  
Max  
Unit  
C
Comment  
Full-Scale Error 16-bit differential mode  
EFS  
—
—
+8/0  
+12/0  
+24/0  
+24/0  
LSB2  
T
VADIN  
VDDA  
=
5
16-bit single-ended mode  
13-bit differential mode  
12-bit single-ended mode  
—
—
0.7  
0.7  
2.0  
2.5  
T
T
T
D
11-bit differential mode  
10-bit single-ended mode  
—
—
0.4  
0.4  
1.0  
1.0  
9-bit differential mode  
8-bit single-ended mode  
—
—
0.2  
0.2  
0.5  
0.5  
Quantization  
Error  
16-bit modes  
EQ  
—
–1 to 0  
—
LSB2  
Bits  
6
7
<13-bit modes  
—
—
0.5  
Effective  
Number of Bits  
16-bit differential mode  
Avg=32  
Avg=16  
Avg=8  
Avg=4  
ENO  
B
C
Fin =  
Fsample/10  
0
14.3  
13.8  
13.4  
13.1  
12.4  
14.5  
14.0  
13.7  
13.4  
12.6  
—
—
—
—
—
Avg=1  
Signal to Noise  
plus Distortion  
See ENOB  
SINA  
D
dB  
dB  
SINAD = 6.02 ENOB + 1.76  
8
9
Total Harmonic  
Distortion  
16-bit differential mode  
Avg=32  
THD  
SFDR  
EIL  
C
D
C
D
D
Fin =  
Fsample/10  
0
—
—
–95.8  
—
–90.4  
—
16-bit single-ended mode  
Avg=32  
Spurious Free  
Dynamic  
Range  
16-bit differential mode  
Avg=32  
dB  
Fin =  
Fsample/10  
0
10  
91.0  
—
96.5  
—
16-bit single-ended mode  
Avg=32  
—
—
Input Leakage  
Error  
all modes  
IIn * RAS  
mV  
IIn =  
leakage  
current  
(refer to  
DC  
11  
characteri  
stics)  
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA  
Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference  
only and are not tested in production.  
1 LSB = (VREFH – VREFL)/2N  
3
32  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.10 MCG and External Oscillator (XOSC) Characteristics  
Table 18. MCG (Temperature Range = –40 to 105°C Ambient)  
#
Rating  
Symbol  
Min  
Typical  
Max  
Unit  
C
D
C
tirefst  
Internal reference startup time  
1
—
55  
100  
s  
factory trimmed at  
VDD=3.0 V and  
temp=25C  
—
31.25  
—
fint_ft  
Average internal reference frequency  
2
3
kHz  
user trimmed  
31.25  
16  
—
—
39.0625  
20  
C
C
Low range  
(DRS=00)  
DCO output frequency range —  
trimmed  
fdco_t  
MHz  
Mid range  
(DRS=01)  
High range1  
C
C
32  
40  
—
—
40  
60  
(DRS=10)  
Resolution of trimmed DCO output fre-  
quency at fixed voltage and tempera-  
ture  
with FTRIM  
—
—
0.1  
0.2  
0.2  
0.4  
C
C
P
fdco_res_t  
%fdco  
4
5
without FTRIM  
over voltage and  
temperature  
—
1.0  
2  
Total deviation of trimmed DCO output  
frequency over voltage and tempera-  
ture  
fdco_t  
%fdco  
over fixed voltage  
and temp range  
of 0 – 70 C  
C
—
0.5  
1  
FLL2  
PLL3  
tfll_acquire  
tpll_acquire  
C
D
C
—
—
—
—
1
1
Acquisition time  
6
7
ms  
Long term Jitter of DCO output clock (averaged over 2mS  
interval) 4  
CJitter  
%fdco  
—
0.02  
0.2  
fvco  
D
D
D
VCO operating frequency  
8
9
7.0  
1.0  
—
—
55.0  
2.0  
MHz  
MHz  
fpll_ref  
PLL reference frequency range  
Long term  
fpll_jitter_625  
Jitter of PLL output clock measured  
over 625ns 5  
0.5664  
%fpll  
%
10  
11  
—
—
ns  
Entry6  
Exit7  
FLL  
Dlock  
Dunl  
D
D
D
1.49  
4.47  
—
—
2.98  
5.97  
Lock frequency tolerance  
Lock time  
tfll_acquire+  
1075(1/fint_t)  
tfll_lock  
—
—
—
12  
s
PLL  
tpll_acquire+  
1075(1/fpll_re  
f)  
D
tpll_lock  
—
Loss of external clock minimum frequency - RANGE = 0  
Loss of external clock minimum frequency - RANGE = 1  
D
D
(3/5) x  
fint_t  
floc_low  
13  
14  
—
—
—
—
kHz  
kHz  
(16/5) x  
fint_t  
floc_high  
1
2
This should not exceed the maximum CPU frequency for this device which is 48 MHz.  
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,  
DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,  
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.  
Freescale Semiconductor  
33  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
3
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL  
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this  
specification assumes it is already running.  
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS  
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.  
Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter  
percentage for a given interval.  
.
5
625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps  
CAN Bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a  
synchronization edge and the sample point of a bit using 8 time quanta per bit.  
6
7
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But  
if the MCG is already in lock, then the MCG may stay in lock.  
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit  
lock.  
Table 19. XOSC (Temperature Range = –40 to 105°C Ambient)  
#
Characteristic  
Symbol  
Min  
Typ1  
Max  
Unit  
C
Oscillator crystal or resonator  
• Low range (RANGE = 0)  
D
(EREFS = 1, ERCLKEN = 1)  
flo  
32  
1
—
—
38.4  
5
kHz  
• High range (RANGE = 1),  
• FEE or FBE mode 2  
fhi-fll  
MHz  
D
D
D
• High range (RANGE = 1),  
• PEE or PBE mode 3  
fhi-pll  
1
1
—
—
16  
16  
MHz  
MHz  
1
• High range (RANGE = 1),  
• High gain (HGO = 1),  
• BLPE mode  
fhi-hgo  
• High range (RANGE = 1),  
• Low power (HGO = 0),  
• BLPE mode  
fhi-lp  
1
—
8
MHz  
D
See crystal or resonator manufacturer’s  
recommendation.  
Load capacitors  
C1  
C2  
D
D
D
2
3
Feedback resistor  
• Low range  
(32 kHz to 38.4 kHz)  
RF  
—
—
—
—
10  
1
M  
k  
• High range  
(1 MHz to 16 MHz)  
—
Series resistor — Low range  
Series resistor — High range  
• Low Gain (HGO = 0)  
• High Gain (HGO = 1)  
• Low Gain (HGO = 0)  
• High Gain (HGO = 1)  
8 MHz  
RS  
—
—
—
0
100  
0
—
—
—
D
D
D
D
D
D
D
4
5
RS  
—
—
—
0
0
0
0
k  
4 MHz  
10  
20  
1 MHz  
34  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 19. XOSC (Temperature Range = –40 to 105°C Ambient)  
#
Characteristic  
• Low range, low gain (RANGE =  
Symbol  
Min  
Typ1  
Max  
Unit  
C
Crystal start-up time 4  
—
—
D
t
0, HGO = 0)  
200  
400  
CSTL-LP  
t
• Low range, high gain  
(RANGE = 0, HGO = 1)  
—
—
—
—
—
—
D
D
D
CSTL-HG  
O
6
• High range, low gain  
(RANGE = 1, HGO = 0)5  
tCSTH-LP  
5
ms  
• High range, high gain  
(RANGE = 1, HGO = 1)5  
tCSTH-HG  
15  
O
1
2
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.  
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz  
to 39.0625 kHz.  
3
4
5
When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to  
2 MHz.  
This parameter is characterized and not tested on each device. Proper PC board layout porcedures must be followed to achieve  
specifications.  
4 MHz crystal.  
MCU  
EXTAL  
XTAL  
R
RS  
F
C1  
C2  
Crystal or Resonator  
o
Freescale Semiconductor  
35  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.11 AC Characteristics  
This section describes ac timing characteristics for each peripheral system.  
2.11.1 Control Timing  
Table 20. Control Timing  
#
Symbol  
Parameter  
Min  
Typical1  
Max  
C
Unit  
fBus  
Bus frequency (tcyc = 1/fBus  
)
MHz  
1
VDD 1.8 V  
dc  
dc  
—
—
10  
20  
D
D
VDD > 2.1 V  
VDD > 2.4 V  
dc  
—
1000  
—
D
P
D
24  
tLPO  
Internal low-power oscillator  
period  
700  
100  
1300  
s  
2
textrst  
External reset pulse width2  
—
ns  
3
4
5
(tcyc = 1/fSelf_reset  
)
trstdrv  
Reset low drive  
66 x tcyc  
500  
—
—
—
—
D
D
ns  
ns  
tMSSU  
Active background debug  
mode latch setup time  
tMSH  
Active background debug  
mode latch hold time  
100  
—
—
—
—
—
—
D
D
ns  
ns  
ns  
6
7
IRQ pulse width  
tILIH, IHIL  
t
•
•
Asynchronous path2  
Synchronous path3  
100  
1.5 x tcyc  
KBIPx pulse width  
D
8
tILIH, IHIL  
t
•
•
Asynchronous path2  
Synchronous path3  
100  
1.5 x tcyc  
36  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Table 20. Control Timing  
#
Symbol  
Parameter  
Min  
Typical1  
Max  
C
Unit  
9
tRise, tFall  
Port rise and fall time (load = 50 pF)4, Low Drive  
ns  
Slew rate  
control  
—
11  
—
D
disabled  
(PTxSE = 0)  
Slew rate  
control  
enabled  
—
—
—
35  
40  
75  
—
—
—
D
D
D
(PTxSE = 1)  
Slew rate  
control  
disabled  
(PTxSE = 0)  
Slew rate  
control  
enabled  
(PTxSE = 1)  
1
2
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.  
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed  
to override reset requests from internal sources.  
3
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may  
or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.  
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.  
textrst  
RESET PIN  
Figure 8. Reset Timing  
tIHIL  
IRQ/KBIPx  
IRQ/KBIPx  
tILIH  
Figure 9. IRQ/KBIPx Timing  
Freescale Semiconductor  
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Electrical Characteristics  
2.11.2 TPM Timing  
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the  
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.  
Table 21. TPM Input Timing  
#
C
Function  
Symbol  
Min  
Max  
Unit  
1
2
3
4
5
—
—
D
External clock frequency  
External clock period  
fTPMext  
tTPMext  
tclkh  
dc  
4
fBus/4  
—
MHz  
tcyc  
tcyc  
tcyc  
tcyc  
External clock high time  
External clock low time  
Input capture pulse width  
1.5  
1.5  
1.5  
—
D
tclkl  
—
D
tICPW  
—
tTPMext  
tclkh  
TPMxCLK  
tclkl  
Figure 10. Timer External Clock  
tICPW  
TPMxCHn  
TPMxCHn  
tICPW  
Figure 11. Timer Input Capture Pulse  
38  
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Electrical Characteristics  
2.12 SPI Characteristics  
Table 22 and Figure 12 through Figure 15 describe the timing requirements for the SPI system.  
Table 22. SPI Timing  
No.1  
Characteristic2  
Operating frequency  
Symbol  
Min  
Max  
Unit  
C
fop  
1
Master  
Slave  
fBus/2048  
0
fBus/2  
Hz  
Hz  
D
f
Bus/4  
SPSCK period  
tSPSCK  
2
3
4
5
6
7
Master  
Slave  
2
4
2048  
—
tcyc  
tcyc  
D
D
D
D
D
D
Enable lead time  
tLead  
Master  
Slave  
12  
1
—
—
tSPSCK  
tcyc  
Enable lag time  
tLag  
Master  
Slave  
12  
1
—
—
tSPSCK  
tcyc  
Clock (SPSCK) high or low time  
Data setup time (inputs)  
Data hold time (inputs)  
tWSPSCK  
Master  
Slave  
tcyc –30  
tcyc – 30  
1024 tcyc  
—
ns  
ns  
tSU  
tSU  
Master  
Slave  
15  
15  
—
—
ns  
ns  
tHI  
tHI  
Master  
Slave  
0
25  
—
—
ns  
ns  
8
9
Slave access time3  
ta  
tdis  
tv  
—
—
1
1
tcyc  
tcyc  
D
D
Slave MISO disable time4  
Data valid (after SPSCK edge)  
10  
11  
12  
13  
Master  
Slave  
—
—
25  
25  
ns  
ns  
D
D
D
D
Data hold time (outputs)  
Rise time  
tHO  
Master  
Slave  
0
0
—
—
ns  
ns  
Input  
Output  
tRI  
tRO  
—
—
tcyc – 25  
25  
ns  
ns  
Fall time  
Input  
Output  
tFI  
tFO  
—
—
tcyc – 25  
25  
ns  
ns  
1
2
Numbers in this column identify elements in Figure 12 through Figure 15.  
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing  
assumes slew rate control disabled and high drive strength enabled for SPI output pins.  
3
4
Time to data active from high-impedance state.  
Hold time to high-impedance state.  
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Electrical Characteristics  
SS1  
(OUTPUT)  
2
2
3
SCK  
(CPOL = 0)  
(OUTPUT)  
5
4
4
5
SCK  
(CPOL = 1)  
(OUTPUT)  
6
7
MISO  
(INPUT)  
MSB IN2  
11  
BIT 6 . . . 1  
11  
LSB IN  
12  
MOSI  
(OUTPUT)  
MSB OUT2  
BIT 6 . . . 1  
LSB OUT  
NOTES:  
1. SS output mode (MODFEN = 1, SSOE = 1).  
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.  
Figure 12. SPI Master Timing (CPHA = 0)  
SS(1)  
(OUTPUT)  
2
2
3
SCK  
(CPOL = 0)  
(OUTPUT)  
5
4
SCK  
(CPOL = 1)  
5
4
(OUTPUT)  
6
7
MISO  
(INPUT)  
MSB IN(2)  
BIT 6 . . . 1  
12  
BIT 6 . . . 1  
LSB IN  
11  
MOSI  
(OUTPUT)  
MSB OUT(2)  
LSB OUT  
NOTES:  
1. SS output mode (MODFEN = 1, SSOE = 1).  
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.  
Figure 13. SPI Master Timing (CPHA = 1)  
40  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
SS  
(INPUT)  
3
2
SCK  
5
4
(CPOL = 0)  
4
5
(INPUT)  
2
SCK  
(CPOL = 1)  
(INPUT)  
9
8
12  
11  
MISO  
(OUTPUT)  
SEE  
NOTE  
BIT 6 . . . 1  
BIT 6 . . . 1  
SLAVE LSB OUT  
MSB OUT  
7
SLAVE  
6
MOSI  
(INPUT)  
MSB IN  
LSB IN  
NOTE:  
1. Not defined, but normally MSB of character just received  
Figure 14. SPI Slave Timing (CPHA = 0)  
SS  
(INPUT)  
2
3
2
SCK  
(CPOL = 0)  
(INPUT)  
5
4
4
5
SCK  
(CPOL = 1)  
(INPUT)  
11  
SLAVE MSB OUT  
12  
9
MISO  
(OUTPUT)  
SEE  
NOTE  
BIT 6 . . . 1  
SLAVE LSB OUT  
6
7
8
MOSI  
(INPUT)  
MSB IN  
BIT 6 . . . 1  
LSB IN  
NOTE:  
1. Not defined, but normally LSB of character just received  
Figure 15. SPI Slave Timing (CPHA = 1)  
Freescale Semiconductor  
41  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.13 Flash Specifications  
This section provides details about program/erase times and program-erase endurance for the Flash memory.  
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed  
DD  
information about program/erase operations, see the Memory chapter in the Reference Manual for this device  
(MC9S08MM128RM).  
Table 23. Flash Characteristics  
#
Characteristic  
Symbol  
Min  
Typical  
Max  
Unit  
C
Supply voltage for program/erase  
–40C to 105C  
1
—
D
Vprog/erase  
VRead  
fFCLK  
tFcyc  
1.8  
1.8  
150  
5
3.6  
3.6  
V
2
3
4
5
6
7
8
Supply voltage for read operation  
Internal FCLK frequency1  
Internal FCLK period (1/FCLK)  
Byte program time (random location)2  
Byte program time (burst mode)2  
Page erase time2  
—
—
V
D
D
D
P
P
P
P
200  
6.67  
kHz  
s  
—
tprog  
9
tFcyc  
tFcyc  
tFcyc  
tFcyc  
tBurst  
4
tPage  
4000  
20,000  
Mass erase time2  
tMass  
Program/erase endurance3  
TL to TH = –40C to + 105C  
T = 25C  
9
10,000  
—
—
100,000  
—
—
cycles  
years  
C
C
10  
Data retention4  
tD_ret  
15  
100  
—
1
2
The frequency of this clock is controlled by a software setting.  
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for  
calculating approximate time to program and erase.  
3
4
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how  
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.  
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to  
25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to  
Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.  
42  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.14 USB Electricals  
The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus  
Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.  
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the standard or require  
additional information, this space would be used to communicate that information.  
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics  
#
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
C
1
2
Regulator operating voltage  
VREG output  
Vregin  
Vregout  
Vusb33in  
3.9  
3
—
5.5  
3.75  
3.6  
V
V
V
C
P
C
3.3  
3.3  
VUSB33 input with internal VREG  
disabled  
3
3
4
VREG Quiescent Current  
IVRQ  
—
0.5  
—
mA  
C
Freescale Semiconductor  
43  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.15 VREF Electrical Specifications  
Table 25. VREF Electrical Specifications  
#
Characteristic  
Supply voltage  
Symbol  
Min  
Max  
Unit  
C
1
2
3
4
VDDA  
TA  
1.80  
–40  
—
3.6  
105  
100  
10  
V
°C  
nf  
C
C
D
—
P
Temperature  
Output Load Capacitance  
Maximum Load  
CL  
—
—
mA  
V
Voltage Reference Output with Factory  
Trim. VDD = 3 V at 25°C.  
Vout  
1.140  
1.160  
5
Temperature Drift (Vmin – Vmax across  
the full temperature range)  
Tdrift  
—
25  
mV1  
T
6
7
8
9
Aging Coefficient2  
Ac  
I
—
—
60  
µV/year  
µA  
C
C
Powered down Current (Off Mode,  
VREFEN=0, VRSTEN=0)  
0.10  
Bandgap only (MODE_LV[1:0] = 00)  
I
I
I
—
—
—
75  
125  
1.1  
µA  
µA  
T
T
T
10 Low-Power buffer (MODE_LV[1:0] = 01)  
Tight-Regulation buffer (MODE_LV[1:0]  
= 10)  
mA  
11  
12 Load Regulation MODE_LV = 10  
Line Regulation MODE = 1:0, Tight  
—
—
100  
—
µV/mA  
dB  
C
C
DC  
70  
Regulation VDD < 2.3 V, Delta VDDA  
13 100 mV, VREFH = 1.2 V driven  
externally with VREFO disabled.  
(Power Supply Rejection)  
=
1
2
See typical chart that follows (Figure 16).  
Linear reliability model (1008 hours stress at 125°C = 10 years operating life) used to calculate Aging µV/year. Vrefo data  
recorded per month.  
Table 26. VREF Limited Range Operating Behaviors  
#
Characteristic  
Symbol  
Min  
Max  
Unit  
C
Notes  
Voltage Reference Output with  
Factory Trim (Temperature range  
from 0° C to 50° C)  
Vout  
1.149  
1.152  
mV  
T
1
Temperature Drift (Vmin – Vmax  
Temperature range from 0° C to  
50° C)  
Tdrift  
—
3
mV1  
T
2
1
See typical chart that follows (Figure 16).  
44  
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Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
Figure 16. Typical VREF Output vs. Temperature  
Figure 17. Typical VREF Output vs. V  
DD  
Freescale Semiconductor  
45  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.16 TRIAMP Electrical Parameters  
Table 27. TRIAMP Characteristics 1.8–3.6 V, –40°C~105°C  
#
Characteristic1  
Symbol  
Min  
Typ2  
Max  
Unit  
C
VDD  
Operating Voltage  
1
1.8  
—
3.6  
V
C
Supply Current (IOUT=0mA, CL=0) Low-power  
mode  
ISUPPLY  
ISUPPLY  
2
3
—
—
52  
60  
A  
A  
T
T
Supply Current (IOUT=0mA, CL=0) High-speed  
mode  
432  
480  
VOS  
VOS  
IOS  
Input Offset Voltage  
4
5
—
—
—
—
—
0
± 1  
600  
±120  
< 350  
3
± 5  
—
mV  
V  
pA  
pA  
nA  
V
T
T
T
T
T
T
T
T
D
D
Input Offset Voltage Temperature Drift  
Input Offset Current  
6
500  
IBIAS  
IBIAS  
VCML  
VCMH  
RIN  
7
Input Bias Current (0 ~ 50°C)  
Input Bias Current (–40 ~ 105°C)  
Input Common Mode Voltage Low  
Input Common Mode Voltage High  
Input Resistance  
< ±500  
6.55  
8
9
—
—
VDD–1.4  
10  
11  
12  
13  
—
500  
—
—
—
V
—
—
5
M  
pF  
M  
CIN  
Input Capacitances  
—
AC Input Impedance (fIN=100kHz)  
1
—
|XIN|  
Input Common Mode Rejection Ratio  
Power Supply Rejection Ration  
14  
15  
16  
17  
18  
19  
20  
21  
CMRR  
PSRR  
SR  
60  
60  
—
70  
70  
—
—
dB  
dB  
T
T
T
T
T
T
T
T
Slew Rate (VIN=100mV) Low-power mode  
Slew Rate (VIN=100mV) High-speed mode  
Unity Gain Bandwidth (Low-power mode) 50pF  
Unity Gain Bandwidth (High-speed mode) 50pF  
DC Open Loop Voltage Gain  
0.1  
1
—
V/s  
V/s  
MHz  
MHz  
dB  
SR  
—
—
GBW  
GBW  
AV  
0.15  
—
0.25  
1.6  
80  
—
—
—
—
Load Capacitance Driving Capability  
CL(max)  
ROUT  
—
—
100  
pF  
Output Impedance AC Open Loop (@100 kHz  
Low-power mode)  
22  
23  
—
—
1.4  
—
—
k  
D
D
Output Impedance AC Open Loop (@100 kHz  
High-speed mode)  
ROUT  
184  
VDD  
–
Output Voltage Range  
24  
triout  
IOUT  
0.15  
—
V
T
0.15  
Output Drive Capability  
Gain Margin  
25  
26  
27  
28  
—
20  
45  
—
± 1.0  
—
—
mA  
dB  
T
D
T
T
GM  
PM  
—
Phase Margin  
55  
—
deg  
Input Voltage Noise Density  
f= 1 kHz  
160  
—
nV/Hz  
1
2
All parameters are measured at 3.0 V, CL= 47 pF across temperature –40 to + 105 °C unless specified.  
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.  
46  
Freescale Semiconductor  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Electrical Characteristics  
2.17 OPAMP Electrical Parameters  
Table 28. OPAMP Characteristics 1.8–3.6 V  
#
Characteristics1  
Operating Voltage  
Symbol  
Min  
Typ2  
Max  
Unit  
C
1
VDD  
1.8  
—
—
3.6  
80  
V
C
T
Supply Current (IOUT=0mA, CL=0 Low-Power  
mode)  
ISUPPLY  
67  
2
3
A  
A  
Supply Current (IOUT=0mA, CL=0 High-Speed  
mode)  
ISUPPLY  
—
538  
550  
T
4
5
Input Offset Voltage  
VOS  
VOS  
IOS  
—
—
—
—
—
—
—
—
0.1  
—
—
—
—
2  
10  
6  
—
mV  
V/C  
nA  
nA  
nA  
nA  
nA  
nA  
V
T
T
T
T
T
T
T
T
T
T
T
D
D
Input Offset Voltage Temperature Coefficient  
Input Offset Current (–40°C to 105°C)  
Input Offset Current (–40°C to 50°C)  
Positive Input Bias Current (–40°C to 105°C)  
Positive Input Bias Current (–40°C to 50°C)  
Negative Input Bias Current (–40°C to 105°C)  
Negative Input Bias Current (–40°C to 50°C)  
Input Common Mode Voltage Low  
Input Common Mode Voltage High  
Input Resistance  
6
2.5  
—
250  
45  
7
IOS  
8
IBIAS  
IBIAS  
IBIAS  
IBIAS  
VCML  
VCMH  
RIN  
0.8  
—
3.5  
2  
9
10  
11  
12  
13  
14  
15  
2.5  
—
250  
45  
—
—
—
VDD  
—
V
500  
—
M  
pF  
Input Capacitances  
CIN  
10  
AC Input Impedance (fIN=100kHz Negative  
Channel)  
|XIN|  
52  
—
16  
17  
k  
k  
AC Input Impedance (fIN=100kHz Positive  
Channel)  
|XIN|  
—
132  
—
D
18  
19  
20  
21  
22  
23  
24  
25  
Input Common Mode Rejection Ratio  
Power Supply Rejection Ratio  
CMRR  
PSRR  
SR  
55  
60  
0.1  
1
65  
65  
—
—
—
—
90  
—
4k  
—
—
dB  
dB  
T
T
T
T
T
T
T
T
D
Slew Rate (VIN=100mV Low-Power mode)  
Slew Rate (VIN=100mV High-Speed mode)  
Unity Gain Bandwidth (Low-Power mode)  
Unity Gain Bandwidth (High-Speed mode)  
DC Open Loop Voltage Gain  
—
V/s  
V/s  
MHz  
MHz  
dB  
SR  
—
GBW  
GBW  
AV  
0.2  
1
—
—
80  
—
—
—
Load Capacitance Driving Capability  
CL(max)  
ROUT  
100  
—
pF  
Output Impedance AC Open Loop (@100 kHz  
Low-Power mode)  
26  
27  
28  
V
Output Impedance AC Open Loop (@100 kHz  
High-Speed mode)  
ROUT  
VOUT  
—
220  
—
—
D
T
Output Voltage Range  
0.15  
VDD–0.1  
5
29  
30  
31  
Output Drive Capability  
Gain Margin  
IOUT  
GM  
PM  
0.5  
20  
1.0  
—
—
—
—
mA  
dB  
T
D
T
Phase Margin  
45  
55  
deg  
Freescale Semiconductor  
47  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
Ordering Information  
Table 28. OPAMP Characteristics 1.8–3.6 V (Continued)  
#
Characteristics1  
Symbol  
Min  
Typ2  
Max  
Unit  
C
GPAMP startup time (Low-Power mode)  
(Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF,  
RL = 100k)  
Tstartup  
—
4
—
T
32  
uS  
GPAMP startup time (Low-Power mode)  
(Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF,  
RL = 100k)  
Tstartup  
—
—
1
—
—
T
T
33  
34  
uS  
Input Voltage Noise Density  
f=1 kHz  
250  
nV/Hz  
1
All parameters are measured at 3.3 V, CL =4 7 pF across temperature –40 to + 105°C unless specified.  
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.  
2
3
Ordering Information  
This appendix contains ordering information for the device numbering system. MC9S08MM128 and MC9S08MM64 devices.  
3.1  
Device Numbering System  
Example of the device numbering system:  
128 V  
9
XX  
MC S08 MM  
Status  
(MC = Fully Qualified)  
Package designator (see Table 30)  
Temperature range  
(V = –40C to 105C)  
(C = –40C to 85C)  
Memory  
(9 = Flash-based)  
Core  
Approximate Flash size in Kbytes  
Family  
Table 29. Device Numbering System  
Memory  
Device Number1  
Available Packages2  
Flash  
RAM  
131,072  
131,072  
131,072  
65,536  
32768  
12,288  
12,288  
12,288  
12,288  
4096  
64 LQFP  
80 LQFP  
MC9S08MM128  
81 MAPBGA  
64 LQFP  
MC9S08MM64  
MC9S08MM32  
MC9S08MM32A  
64 LQFP  
32768  
2048  
64 LQFP  
1
2
See Table 2 for a complete description of modules included on each device.  
See Table 30 for package information.  
48  
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Revision History  
3.2  
Package Information  
Table 30. Package Descriptions  
Pin Count  
Package Type  
Abbreviation  
Designator  
Case No.  
Document No.  
64  
80  
81  
Low Quad Flat Package  
Low Quad Flat Package  
MAPBGA Package  
LQFP  
LQFP  
LH  
LK  
840F-02  
917-01  
98ASS23234W  
98ASS23174W  
98ASA10670D  
Map PBGA  
MB  
1662-01  
3.3  
Mechanical Drawings  
Table 30 provides the available package types and their document numbers. The latest package outline/mechanical drawings  
are available on the MC9S08MM128 series Product Summary pages at http://www.freescale.com.  
To view the latest drawing, either:  
•
•
Click on the appropriate link in Table 30, or  
Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate document number (from  
Table 30) in the “Enter Keyword” search box at the top of the page.  
®
4
Revision History  
Table 31. Revision History  
Rev  
Date  
Description of Changes  
0
1
2
06/2009  
07/2009  
01/2010  
Initial release of the Data Sheet.  
Updated MCG and XOSC Average internal reference frequency.  
Revised to include MC9S08MM32 and MC9S08MM32A devices.Updated electrical  
characteristic data.  
3
10/2010  
Updated with the latest characteristic data. Added several figures. Added the ADCTypical  
Operation table.  
Freescale Semiconductor  
49  
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Revision History  
50  
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Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
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MC9S08MM128  
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 SMBus Multi-Output Power-Supply Controller

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VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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VISHAY
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