MC9S12DT512MPV [NXP]
IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC;型号: | MC9S12DT512MPV |
厂家: | NXP |
描述: | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC 时钟 微控制器 外围集成电路 |
文件: | 总124页 (文件大小:4657K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DOCUMENT NUMBER
9S12DP512DGV1/D
Freescale Semiconductor
MC9S12DP512
Device Guide
V01.25
Covers also
MC9S12DT512, MC9S12DJ512,
MC9S12A512
Original Release Date: 27 Nov 2001
Revised: 05 Jul 2005
Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
1
DOCUMENT NUMBER
9S12DP512DGV1/D
Revision History
Version Revision Effective
Author
Description of Changes
Number
Date
Date
27 Nov
2001
11 Feb
2002
V01.00
- Initial version based on DP256 V2.09.
- Updated document formats.
- Removed reference to SIM in overview.
- Changed XCLKS to PE7 in signal description.
- Removed "Oscillator start-up time from POR or STOP" from Oscillator
Characterisitcs.
13 Mar
2002
13 Mar
2002
V01.01
- Changed VDD and VDDPLL to 2.35V.
- Updated CINS
.
- Updated IOL/IOH values.
- Updated input capacitance.
- Updated NVM timing characteristics.
02 Apr
2002
02 Apr
2002
V01.02
V01.03
V01.04
- Updated document reference (SPI, SCI).
- Corrected values in device memory map (RAM start, flash protected
sector sizes).
- Updated document reference (SCI).
15 Apr
2002
15 Apr
2002
06 Jun
2002
06 Jun
2002
- Changed all operating frequency references to 50MHz EXTAL and
removed references to 80 pin LQFP.
- Preface Table "Document References": Changed to full naming for
each block.
- Table "Interrupt Vector Locations", Column "Local Enable": Corrected
several register and bit names.
05 Jul
2002
05 Jul
2002
- Table "Signal Properties": Added column "Internal Pull Resistor".
- Table "PLL Characteristics": Updated parameters K1 and f1
- Figure "Basic Pll functional diagram": Inserted XFC pin in diagram
- Enhanced section "XFC Component Selection"
- Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode.
V01.05
Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or
design.Freescale does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others.Freescale products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was
negligent regarding the design or manufacture of the part.
MC9S12DP512 Device Guide V01.25
Version Revision Effective
Author
Description of Changes
Number
Date
Date
- Updated SPI electrical characteristics.
- Updated Derivative Differences table.
- Added ordering number example.
- Added Detailed Register Map.
- Changed Internal Pull Resistor column of signal table.
- Added pull device description for MODC pin.
- Corrected XCLKS figure titles. Moved table to section Modes of
Operation.
24 Jul
2002
24 Jul
2002
- Removed ’1/2’ from BDM in Figure Clock Connections.
- Completely reworked section Modes of Operation. Added Chip
Configuration Summary and Low Power Mode description.
- Changed classification to C for internal pull currents inTable 5V I/O
Characteristics.
V01.06
- Changed input leakage to 1uA for all pins.
- Updated VREG section and layout recommendation.
- Moved Power and Gound Connection Summary table to start of
Power Supply Pins section.
- Added ROMONE to pinout
- Corrected mem map: ’MEBI map x of 3’
- Corrected mem map: KEYEN bits in FSEC.
- Added section Printed Circuit Board Layout Proposal.
- Corrected addresses in Reserved, CAN and EEP buffer map.
- Updated NVM electricals.
29 Jul
2002
05 Aug
2002
V01.07
21 Aug
2002
21 Aug
2002
- Updated table ’Document References’
- Added section ’Oscillator (OSC) Block Description’
V01.08
V01.09
- Section HCS12 Core Block Desciption: mentioned alternalte clock of
BDM to be equivalent to oscillator clock
- Corrected tables 0-1 and 0-2
24 Sep
2002
24 Sep
2002
- Added derivatives to cover sheet.
- Added part ID for 1L00M maskset.
- Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz.
18 Oct
2002
18 Oct
2002
V01.10
V01.11
V01.12
- Renamed Preface section to Derivative Differences and Document
references.
- Added A512 derivative.
- Updated module set of DJ512 in Table 0-1.
- Added details for derivatives without CAN and/or BDLC modules.
29 Oct
2002
29 Oct
2002
- Corrected several entries in ’Detailed Memory Map’.
- Removed footnote on input leakage current from table ’5V I/O
Characteristics’.
03 Dec
2002
03 Dec
2002
08 Jan
2003
08 Jan
2003
- Updated section ’Unsecuring the Microcontroller’.
- Updated footnote 1 in table ’Operating Conditions’.
V01.13
V01.14
V01.15
23 Jan
2003
23 Jan
2003
- Renamed ROMONE pin to ROMCTL.
28 Feb
2003
28 Feb
2003
- Corrected PE[1,0] pull specification in Signal Properties Summary
Table.
3
MC9S12DP512 Device Guide V01.25
Version Revision Effective
Author
Description of Changes
Number
Date
Date
- Corrections in App. A ’NVM, Flash and EEPROM’:
- Number of words per flash row = 64
31 Mar
2003
31 Mar
2003
- Replaced ’burst programming’ with ’row programming’
- Sector erase size = 1024 bytes
V01.16
- Corrected feature description ECT
- Corrected min. bus freq. in table ’Operating Conditions’
- Replaced references to HCS12 Core Guide with the individual HCS12
Block guides throughout document
- Table ’Absolute Maximum Ratings’ corrected footnote on clamp of
TEST pin
30 May
2003
30 May
2003
V01.17
23 Jul
2003
23 Jul
2003
- Mentioned ’S12 LRAE’ bootloader in Flash section
- Document References: corrected S12 CPU document reference
V01.18
V01.19
24 Jul
2003
24 Jul
2003
- Added part ID for 2L00M maskset.
- Added part ID for 3L00M maskset.
- Added cycle definition to ’CPU 12 Block Description’.
- Diagram ’Clock Connections’: Connected Bus Clock to HCS12 Core.
- Corrected ’Background Debug Module’ to ’HCS12 Breakpoint’ at
address $0028 - $002F in table 1-1.
- Corrected ’Blank Check Time Flash’ value in table ’NVM Timing
Characteristics’
01 Sep
2003
01 Sep
2003
V01.20
- Added EXTAL pin VIH, VIL and EXTAL pin hysteresis value to
’Oscillator Characteristics’. Updated oscillator description and table
note.
08 Mar
2004
08 Mar
2004
- Added part ID for 4L00M maskset.
- Corrected pin name KWP5 in device pinout.
V01.21
V01.22
- Updated VIH,EXTAL and VIL,EXTAL in table ’Oscillator Characteristics’
23 Aug
2004
23 Aug
2004
- Removed item ’Oscillator’ from table ’Operating Conditions’ as
already covered in table ’Oscillator Characteristics’
09 Feb
2005
09 Feb
2005
- Corrected Flash Row Programming Time in NVM Timing
Characteristics
V01.23
V01.24
V01.25
- Changed TJavg and added footnote to data retention time in NVM
Reliability Characteristics
01 Apr
2005
01 Apr
2005
05 Jul
2005
05 Jul
2005
- Updated NVM Reliability Characteristics
MC9S12DP512 Device Guide V01.25
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.5.1
1.6
1.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Memory Size Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .56
PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .56
PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .56
PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .56
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .56
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5
MC9S12DP512 Device Guide V01.25
2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.22 PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.23 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.24 PH4 / KWH4 / MISO2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.29 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7. . . . . . . . . . . . . . . . . .60
2.3.30 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . . . .60
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.32 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.34 PM7 / TXCAN3 / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.35 PM6 / RXCAN3 / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.36 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5. . . . . . . . . . . . . . .61
2.3.37 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . . .61
2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.39 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . .61
2.3.40 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.41 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.43 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.45 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.50 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.51 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.53 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.54 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.55 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
MC9S12DP512 Device Guide V01.25
2.3.56 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.57 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . . . .65
VDDR, VSSR — Power & Ground Pins for I/O Drivers & Internal Voltage Regulator65
VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins . . . . . . . . . . . . . . .65
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .65
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .65
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .65
VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
Section 3 System Clock Description
3.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 4 Modes of Operation
4.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Section 5 Resets and Interrupts
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.2
5.2.1
5.3
5.3.1
5.3.2
Section 6 HCS12 Core Block Description
7
MC9S12DP512 Device Guide V01.25
6.1
CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . . . .77
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . . . .77
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . .78
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.1.1
6.2
6.2.1
6.3
6.3.1
6.4
6.5
6.5.1
6.6
Section 7 Clock and Reset Generator (CRG) Block Description
7.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 8 Oscillator (OSC) Block Description
8.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 9 Enhanced Capture Timer (ECT) Block Description
Section 10 Analog to Digital Converter (ATD) Block Description
Section 11 Inter-IC Bus (IIC) Block Description
Section 12 Serial Communications Interface (SCI) Block Description
Section 13 Serial Peripheral Interface (SPI) Block Description
Section 14 J1850 (BDLC) Block Description
Section 15 Pulse Width Modulator (PWM) Block Description
Section 16 Flash EEPROM 512K Block Description
Section 17 EEPROM 4K Block Description
Section 18 RAM Block Description
Section 19 MSCAN Block Description
MC9S12DP512 Device Guide V01.25
Section 20 Port Integration Module (PIM) Block Description
Section 21 Voltage Regulator (VREG) Block Description
Section 22 Printed Circuit Board Layout Proposal
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.2.1
A.2.2
A.2.3
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.3.1
A.3.2
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.5.1
A.5.2
A.5.3
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.7.1
A.7.2
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
A.8.1
General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9
MC9S12DP512 Device Guide V01.25
Appendix B Package Information
B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
MC9S12DP512 Device Guide V01.25
List of Figures
Figure 0-1 Order Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 1-1 MC9S12DP512 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 1-2 MC9S12DP512 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 2-1 Pin Assignments in 112-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 2-2 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 2-3 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 2-4 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 2-5 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .82
Figure 22-2 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .83
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure A-2 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure A-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-4 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-6 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-7 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-8 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-9 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure A-10 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 122
11
MC9S12DP512 Device Guide V01.25
MC9S12DP512 Device Guide V01.25
List of Tables
Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
$0000 - $000F
$0010 - $0014
$0015 - $0016
$0017 - $0019
$001A - $001B
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .27
MMC map 1 of 4 (HCS12 Module Mapping Control). . . . . . . . . . . . . . . . . .27
INT map 1 of 2 (HCS12 Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Device ID Register (Table 1-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4) . . . . . . . . .28
$001E - $001E
$001F - $001F
$0020 - $0027
$0028 - $002F
$0030 - $0031
$0032 - $0033
$0034 - $003F
$0040 - $007F
$0080 - $009F
$00A0 - $00C7
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .28
INT map 2 of 2 (HCS12 Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
BKP (HCS12 Breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MMC map 4 of 4 (HCS12 Module Mapping Control). . . . . . . . . . . . . . . . . .29
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .29
CRG (Clock and Reset Generator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
ECT (Enhanced Capture Timer 16 Bit 8 Channels) . . . . . . . . . . . . . . . . . .30
ATD0 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .33
PWM (Pulse Width Modulator 8 Bit 8 Channel). . . . . . . . . . . . . . . . . . . . . .34
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
$00D8 - $00DF SPI0 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
$00E0 - $00E7
$00E8 - $00EF
$00F0 - $00F7
$00F8 - $00FF
$0100 - $010F
$0110 - $011B
$011C - $011F
$0120 - $013F
$0140 - $017F
IIC (Inter IC Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
BDLC (Bytelevel Data Link Controller J1850) . . . . . . . . . . . . . . . . . . . . . . .37
SPI1 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
SPI2 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Flash Control Register (fts512k4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
EEPROM Control Register (eets4k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Reserved for RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
ATD1 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .40
CAN0 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .42
$0180 - $01BF
CAN1 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .43
13
MC9S12DP512 Device Guide V01.25
$01C0 - $01FF
$0200 - $023F
$0240 - $027F
$0280 - $02BF
$02C0 - $03FF
CAN2 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .44
CAN3 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .45
PIM (Port Integration Module PIM_9DP256). . . . . . . . . . . . . . . . . . . . . . . .46
CAN4 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .48
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 2-2 MC9S12DP512 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . .64
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table A-3 ESD and Latch-up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table A-13 Voltage Regulator Recommended Load Capacitances. . . . . . . . . . . . . . . . . . . .103
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table A-18 Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table A-19 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table A-20 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table A-21 Expanded Bus Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
MC9S12DP512 Device Guide V01.25
Derivative Differences and Document References
Derivative Differences
Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the
compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
1
Table 0-1 Derivative Differences
Modules
# of CANs
CAN0
MC9S12DP512
MC9S12DT512
MC9S12DJ512
MC9S12A512
5
3
2
0
✓
✓
✓
—
CAN1
✓
✓
—
—
CAN2
✓
—
—
—
CAN3
✓
—
—
—
—
CAN4
✓
✓
✓
—
✓
✓
J1850/BDLC
Package
—
112 LQFP
112 LQFP
112 LQFP
112 LQFP
Package
Code
PV
PV
PV
PV
Mask set
L00M
L00M
L00M
L00M
C
Temp Options
M, V, C
M, V, C
M, V, C
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
Notes
NOTES:
1. ✓: Available for this device, —: Not available for this device
The following figure provides an ordering number example for the MC9S12D-Family devices.
Temperature Options
MC9S12 DP512 C PV
Package Option
Temperature Option
Device Title
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
FU = 80 QFP
PV = 112 LQFP
Controller Family
Figure 0-1 Order Part Number Example
15
MC9S12DP512 Device Guide V01.25
The following items should be considered when using a derivative (Table 0-1):
•
•
•
Registers
– Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a
derivative without CAN0.
– Do not write or read CAN1registers (after reset: address range $0180 - $01BF), if using a
derivative without CAN1.
– Do not write or read CAN2 registers (after reset: address range $01C0 - $01FF), if using a
derivative without CAN2.
– Do not write or read CAN3 registers (after reset: address range $0200 - $023F), if using a
derivative without CAN3.
– Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a
derivative without CAN4.
– Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC.
Interrupts
– Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for
unused interrupts, if using a derivative without CAN0.
– Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for
unused interrupts, if using a derivative without CAN1.
– Fill the four CAN2 interrupt vectors ($FFA0 - $FFA7) according to your coding policies for
unused interrupts, if using a derivative without CAN2.
– Fill the four CAN3 interrupt vectors ($FF98 - $FF9F) according to your coding policies for
unused interrupts, if using a derivative without CAN3.
– Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for
unused interrupts, if using a derivative without CAN4.
– Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused
interrupts, if using a derivative without BDLC.
Ports
– The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5,
PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0.
– The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if
using a derivative without CAN1.
– The CAN2 pin functionality (TXCAN2, RXCAN2) is not available on port PM5 and PM4, if
using a derivative without CAN2.
– The CAN3 pin functionality (TXCAN3, RXCAN3) is not available on port PM7 and PM6, if
using a derivative without CAN3.
MC9S12DP512 Device Guide V01.25
– The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7,
PM6, PM5 and PM4, if using a derivative without CAN0.
– The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
derivative without BDLC.
– Do not write MODRR1 and MODRR0 bits of Module Routing Register (PIM_9DP256 Block
Guide), if using a derivative without CAN0.
– Do not write MODRR3 and MODRR2 bits of Module Routing Register (PIM_9DP256 Block
Guide), if using a derivative without CAN4.
Document References
The Device Guide provides information about the MC9S12DP512 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
individual Block Guides of the implemented modules. In an effort to reduce redundancy, all module
specific information is located only in the respective Block Guide. If applicable, special implementation
details of the module are given in the block description sections of this document.
See Table 0-2 for names and versions of the referenced documents throughout the Device Guide.
Table 0-2 Document References
Block Guide
Version
V02
V04
V03
V01
V04
V01
V04
V01
V02
V02
V02
V03
V01
V01
V02
V01
V02
V01
V03
V02
Document Order Number
S12CPUV2/D
HCS12 CPU Reference Manual
HCS12 Module Mapping Control (MMC) Block Guide
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide
HCS12 Interrupt (INT) Block Guide
S12MMCV4/D
S12MEBIV3/D
S12INTV1/D
HCS12 Background Debug (BDM) Block Guide
HCS12 Breakpoint (BKP) Block Guide
S12BDMV4/D
S12BKPV1/D
Clock and Reset Generator (CRG) Block Guide
Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block Guide
Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block Guide
Inter IC Bus (IIC) Block Guide
S12CRGV4/D
S12ECT16B8V1/D
S12ATD10B8CV2/D
S12IICV2/D
Asynchronous Serial Interface (SCI) Block Guide
Serial Peripheral Interface (SPI) Block Guide
S12SCIV2/D
S12SPIV3/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide
512K Byte Flash (FTS512K4) Block Guide
S12PWM8B8CV1/D
S12FTS512K4V1/D
S12EETS4KV2/D
S12BDLCV1/D
S12MSCANV2/D
S12VREGV1/D
S12DP256PIMV3/D
S12OSCV2/D
4K Byte EEPROM (EETS4K) Block Guide
Byte Level Data Link Controller -J1850 (BDLC) Block Guide
Freescale Scalable CAN (MSCAN) Block Guide
Voltage Regulator (VREG) Block Guide
Port Integration Module (PIM_9DP256) Block Guide1
Oscillator (OSC) Block Guide
17
MC9S12DP512 Device Guide V01.25
NOTES:
1. Reused due to functional equivalence.
MC9S12DP512 Device Guide V01.25
Section 1 Introduction
1.1 Overview
The MC9S12DP512 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 512K bytes of Flash EEPROM, 14K
bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wake up capability, five CAN 2.0 A, B software compatible modules
(MSCAN12), and an Inter-IC Bus. The MC9S12DP512 has full 16-bit data paths throughout. However,
the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for
lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements.
1.2 Features
•
HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.Instruction queue
iv. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Mode)
CRG (Clock and Reset Generation)
– Low current Colpitts oscillator or
– Pierce oscillator
•
– PLL
– COP watchdog
– Real Time Interrupt
– Clock Monitor
•
8-bit and 4-bit ports with interrupt functionality
19
MC9S12DP512 Device Guide V01.25
– Digital filtering
– Programmable rising or falling edge trigger
•
Memory
– 512K Flash EEPROM
– 4K byte EEPROM
– 14K byte RAM
•
•
Two 8-channel Analog-to-Digital Converters
– 10-bit resolution
– External conversion trigger capability
Five 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
•
•
Enhanced Capture Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Four 8-bit or two 16-bit pulse accumulators
8 PWM channels
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
•
•
Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Three Synchronous Serial Peripheral Interface (SPI)
Byte Data Link Controller (BDLC)
– SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible
for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications
MC9S12DP512 Device Guide V01.25
•
•
Inter-IC Bus (IIC)
2
– Compatible with I C Bus standard
– Multi-master operation
– Software programmable for one of 256 different serial clock frequencies
112-Pin LQFP package
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
– Operation at 50MHz equivalent to 25MHz Bus Speed over -40˚C <= T <= 125˚C
A
– Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
1.3 Modes of Operation
User modes
•
Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
Special Operating Modes
•
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Freescale use only)
– Special Peripheral Mode (Freescale use only)
Low power modes
•
•
•
Stop Mode
Pseudo Stop Mode
Wait Mode
21
MC9S12DP512 Device Guide V01.25
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12DP512 device.
MC9S12DP512 Device Guide V01.25
Figure 1-1 MC9S12DP512 Block Diagram
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
512K Byte Flash EEPROM
14K Byte RAM
ATD0
ATD1
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
4K Byte EEPROM
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
A
A
Voltage Regulator
PAD07
PAD15
PIX0
PK0 XADDR14
PK1 XADDR15
Single-wire Background
BKGD
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
CPU12
Debug Module
PPAGE
PK2
XADDR16
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
PK3 XADDR17
PK4 XADDR18
PK5 XADDR19
Clock and
Reset
Generation
Module
P
D
PLL
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PK7
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
Enhanced Capture
Timer
System
Integration
Module
(SIM)
PT6
PT7
NOACC/XCLKS
RXD
TXD
RXD
TXD
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
SCI0
TEST
SCI1
SPI0
MISO
MOSI
SCK
SS
Multiplexed Address/Data Bus
DDRA
PTA
DDRB
PTB
BDLC
RXB
TXB
(J1850)
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
CAN0
CAN1
CAN2
CAN3
CAN4
Multiplexed
Wide Bus
KWJ0
KWJ1
KWJ6
KWJ7
PJ0
PJ1
PJ6
PJ7
Multiplexed
Narrow Bus
SDA
SCL
IIC
Internal Logic 2.5V
VDD1,2
VSS1,2
I/O Driver 5V
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
PP0
PP1
PP2
PP3
PP4
PP5
VDDX
VSSX
PWM
A/D Converter 5V &
Voltage Regulator Reference
PLL 2.5V
VDDPLL
VSSPLL
VDDA
VSSA
PP6
PP7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PH0
PH1
PH2
PH3
PH4
PH5
Voltage Regulator 5V & I/O
SPI1
SPI2
VDDR
VSSR
PH6
PH7
23
MC9S12DP512 Device Guide V01.25
1.5 Device Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DP512 after reset. Note that after
reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space
Table 1-1 Device Memory Map
Size
(Bytes)
Address
Module
$0000 - $000F HCS12 Multiplexed External Bus Interface
$0010 - $0014 HCS12 Module Mapping Control
$0015 - $0016 HCS12 Interrupt
16
5
2
$0017 - $0019 Reserved
3
$001A - $001B Device ID register (PARTID)
$001C - $001D HCS12 Module Mapping Control
2
2
$001E
$001F
HCS12 Multiplexed External Bus Interface
HCS12 Interrupt
1
1
$0020 - $0027 Reserved
8
$0028 - $002F HCS12 Breakpoint
8
$0030 - $0031 HCS12 Module Mapping Control
$0032 - $0033 HCS12 Multiplexed External Bus Interface
$0034 - $003F Clock and Reset Generator (PLL, RTI, COP)
$0040 - $007F Enhanced Capture Timer 16-bit 8 channels
$0080 - $009F Analog to Digital Converter 10-bit 8 channels (ATD0)
$00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM)
$00C8 - $00CF Serial Communications Interface 0 (SCI0)
$00D0 - $00D7 Serial Communications Interface 0 (SCI1)
$00D8 - $00DF Serial Peripheral Interface (SPI0)
$00E0 - $00E7 Inter IC Bus
2
2
12
64
32
40
8
8
8
8
$00E8 - $00EF Byte Data Link Controller (BDLC)
$00F0 - $00F7 Serial Peripheral Interface (SPI1)
$00F8 - $00FF Serial Peripheral Interface (SPI2)
$0100- $010F Flash Control Register
8
8
8
16
12
4
$0110 - $011B EEPROM Control Register
$011C - $011F Reserved
$0120 - $013F Analog to Digital Converter 10-bit 8 channels (ATD1)
$0140 - $017F Freescale Scalable Can (CAN
$0180 - $01BF Freescale Scalable Ca
32
64
64
64
64
64
64
320
4096
14336
$01C0 - $01FF Freescale Scalable Can (CAN
$0200 - $023F Freescale Scalable Can (CAN3)
$0240 - $027F Port Integration Module (PIM)
$0280 - $02BF Freescale Scalable Can (CAN4)
$02C0 - $03FF Reserved
$0000 - $0FFF EEPROM array
$0800 - $3FFF RAM array
Fixed Flash EEPROM array
$4000 - $7FFF
16384
incl. 1K, 2K, 4K or 8K Protected Sector at start
MC9S12DP512 Device Guide V01.25
Table 1-1 Device Memory Map
Size
(Bytes)
Address
Module
$8000 - $BFFF Flash EEPROM Page Window
Fixed Flash EEPROM array
16384
$C000 - $FFFF incl. 2K, 4K, 8K or 16K Protected Sector at end
and 256 bytes of Vector Space at $FF80 - $FFFF
16384
25
MC9S12DP512 Device Guide V01.25
Figure 1-2 MC9S12DP512 Memory Map
$0000
$0000
$0400
REGISTERS
(Mappable to any 2k Block
within the first 32K)
$03FF
$0000
$0800
4K Bytes EEPROM
(Mappable to any 4K Block)
$0FFF
$0800
14K Bytes RAM
(Mappable to any 16K
and alignable to top or
bottom)
$4000
$3FFF
$4000
16K Fixed Flash
Page $3E = 62
(This is dependant on the
state of the ROMHM bit)
$7FFF
$8000
$8000
16K Page Window
32 x 16K Flash EEPROM
pages
EXTERN
$BFFF
$C000
$C000
16K Fixed Flash
Page $3F = 63
$FFFF
$FF00
BDM
(if active)
$FF00
$FFFF
$FFFF
VECTORS
VECTORS
VECTORS
SPECIAL
SINGLE CHIP
EXPANDED*
NORMAL
SINGLE CHIP
* Assuming that a ‘0’ was driven onto port K bit 7 during MCU is reset into normal expanded wide or narrow mode.
MC9S12DP512 Device Guide V01.25
1.5.1 Detailed Register Map
$0000 - $000F
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$0000
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PORTA
$0001
$0002
$0003
PORTB
DDRA
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
DDRB
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
$0004 -
$0007
Reserved
PORTE
DDRE
Bit 1
Bit 0
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
Bit 7
Bit 7
6
5
5
4
4
3
3
2
0
0
0
0
6
0
Bit 2
PEAR
NOACCE
MODC
PUPKE
PIPOE
NECLK
0
LSTRE
RDWE
0
MODE
PUCR
MODB
0
MODA
0
IVIS
0
EMK
EME
0
0
0
0
PUPEE
PUPBE PUPAE
0
0
0
0
0
0
0
0
0
RDRIV
EBICTL
Reserved
RDPK
0
RDPE
0
RDPB
0
RDPA
ESTR
0
0
0
0
$0010 - $0014
MMC map 1 of 4 (HCS12 Module Mapping Control)
Address
$0010
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
RAMHAL
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
INITRM
RAM15 RAM14 RAM13 RAM12 RAM11
0
0
0
0
0
$0011
$0012
$0013
$0014
INITRG
INITEE
MISC
REG14
REG13
REG12
REG11
EE15
0
EE14
0
EE13
0
EE12
0
EE11
EEON
EXSTR1 EXSTR0 ROMHM ROMON
0
0
0
0
0
0
0
0
Reserved
27
MC9S12DP512 Device Guide V01.25
$0015 - $0016
INT map 1 of 2 (HCS12 Interrupt)
Address
$0015
Name
ITCR
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
WRINT
ADR3
ADR2
ADR1
ADR0
$0016
ITEST
INTE
INTC
INTA
INT8
INT6
INT4
INT2
INT0
$0017 - $0019
Reserved
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$0017-
$0019
Reserved
$001A - $001B
Device ID Register (Table 1-3)
Address
$001A
Name
Bit 7
ID15
Bit 6
ID14
Bit 5
ID13
Bit 4
ID12
Bit 3
ID11
Bit 2
ID10
Bit 1
ID9
Bit 0
ID8
Read:
Write:
Read:
Write:
PARTIDH
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
$001B
PARTIDL
$001C - $001D
MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4)
Address
$001C
Name
Bit 7
Read: reg_sw0
Write:
Bit 6
0
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
eep_sw1 eep_sw0
ram_sw2 ram_sw1 ram_sw0
MEMSIZ0
Read: rom_sw1 rom_sw0
Write:
0
0
0
0
pag_sw1 pag_sw0
$001D
MEMSIZ1
$001E - $001E
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$001E
Name
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
INTCR
IRQE
IRQEN
$001F - $001F
INT map 2 of 2 (HCS12 Interrupt)
Address
$001F
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read:
Write:
HPRIO
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
$0020 - $0027
Reserved
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$0020 -
$0027
Reserved
MC9S12DP512 Device Guide V01.25
$0028 - $002F
BKP (HCS12 Breakpoint)
Address
$0028
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
BKPCT0
BKEN
BKFULL BKBDM BKTAG
$0029
$002A
$002B
$002C
$002D
$002E
$002F
BKPCT1
BKP0X
BKP0H
BKP0L
BKP1X
BKP1H
BKP1L
BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
0
0
BK0V5
BK0V4
BK0V3
BK0V2
BK0V1
BK0V0
Bit 8
Bit 15
14
13
12
11
10
9
Bit 7
0
6
0
5
BK1V5
13
4
BK1V4
12
3
BK1V3
11
2
BK1V2
10
1
Bit 0
BK1V1
BK1V0
Bit 8
Bit 15
Bit 7
14
6
9
1
5
4
3
2
Bit 0
$0030 - $0031
MMC map 4 of 4 (HCS12 Module Mapping Control)
Address
$0030
Name
Bit 7
0
Bit 6
0
Bit 5
PIX5
0
Bit 4
PIX4
0
Bit 3
PIX3
0
Bit 2
PIX2
0
Bit 1
PIX1
0
Bit 0
PIX0
0
Read:
Write:
Read:
Write:
PPAGE
0
0
$0031
Reserved
$0032 - $0033
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$0032
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
PORTK
$0033
DDRK
Bit 7
6
5
4
3
2
1
Bit 0
$0034 - $003F
CRG (Clock and Reset Generator)
Address
$0034
Name
SYNR
Bit 7
0
Bit 6
0
Bit 5
SYN5
0
Bit 4
SYN4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
SYN3
SYN2
SYN1
SYN0
0
0
$0035
$0036
$0037
$0038
REFDV
REFDV3 REFDV2 REFDV1 REFDV0
Read: TOUT7
Write:
TOUT6
TOUT5
TOUT4
TOUT3
LOCK
0
TOUT2
TRACK
0
TOUT1
TOUT0
SCM
0
CTFLG
Test Only
Read:
Write:
Read:
Write:
0
0
CRGFLG
CRGINT
RTIF
PROF
0
LOCKIF
LOCKIE
SCMIF
SCMIE
RTIE
29
MC9S12DP512 Device Guide V01.25
$0034 - $003F
CRG (Clock and Reset Generator)
Address
$0039
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CLKSEL
PLLSEL
PSTP
SYSWAI ROAWAI PLLWAI
0
CWAI
RTIWAI COPWAI
$003A
$003B
$003C
$003D
$003E
$003F
PLLCTL
RTICTL
COPCTL
CME
0
PLLON
RTR6
AUTO
ACQ
PRE
PCE
RTR1
CR1
SCME
RTR0
RTR5
0
RTR4
0
RTR3
0
RTR2
WCOP
RSBCK
CR2
0
CR0
0
0
0
FORBYP
Test Only
RTIBYP COPBYP
PLLBYP
TCTL4
FCM
Read: TCTL7
Write:
TCTL6
TCTL5
TCLT3
TCTL2
TCTL1
TCTL0
CTCTL
Test Only
Read:
Write:
0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
ARMCOP
$0040 - $007F
ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address
$0040
Name
TIOS
Bit 7
IOS7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
$004A
$004B
$004C
$004D
$004E
CFORC
OC7M
OC7D
Write: FOC7
Read:
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
Read:
Write:
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
9
1
0
Bit 8
Bit 0
0
TCNT (hi)
TCNT (lo)
TSCR1
TTOV
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
0
TEN
TOV7
OM7
OM3
TSWAI
TOV6
OL7
TSFRZ
TOV5
OM6
TFFCA
TOV4
OL6
TOV3
OM5
OM1
TOV2
OL5
TOV1
OM4
OM0
TOV0
OL4
TCTL1
TCTL2
TCTL3
TCTL4
TIE
OL3
OM2
OL2
OL1
OL0
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
C7I
TOI
C7F
C6I
0
C5I
0
C4I
0
C3I
TCRE
C3F
C2I
PR2
C2F
C1I
PR1
C1F
C0I
PR0
C0F
TSCR2
TFLG1
C6F
C5F
C4F
MC9S12DP512 Device Guide V01.25
$0040 - $007F
ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address
$004F
Name
Bit 7
TOF
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
TFLG2
$0050
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
$005A
$005B
$005C
$005D
$005E
$005F
$0060
$0061
$0062
$0063
$0064
$0065
$0066
$0067
TC0 (hi)
TC0 (lo)
TC1 (hi)
TC1 (lo)
TC2 (hi)
TC2 (lo)
TC3 (hi)
TC3 (lo)
TC4 (hi)
TC4 (lo)
TC5 (hi)
TC5 (lo)
TC6 (hi)
TC6 (lo)
TC7 (hi)
TC7 (lo)
PACTL
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PAI
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
14
6
13
5
12
4
11
3
10
2
9
Bit 7
0
1
PAEN
0
PAMOD PEDGE
CLK1
0
CLK0
0
PAOVI
0
0
0
PAFLG
PAOVF
PAIF
Bit 0
Bit 0
Bit 0
Bit 0
PACN3 (hi)
PACN2 (lo)
PACN1 (hi)
PACN0 (lo)
MCCTL
Bit 7
Bit 7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
Bit 7
Bit 7
0
ICLAT
0
0
MCZI
MCZF
MODMC RDMCL
MCEN
POLF2
MCPR1 MCPR0
POLF1 POLF0
FLMC
POLF3
0
0
MCFLG
31
MC9S12DP512 Device Guide V01.25
$0040 - $007F
ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address
$0068
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
PA3EN
0
Bit 2
PA2EN
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ICPAR
PA1EN
PA0EN
0
0
0
0
$0069
$006A
$006B
$006C
$006D
DLYCT
ICOVW
ICSYS
DLY1
DLY0
NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
SH37
SH26
SH15
SH04
TFMOD PACMX BUFEN
LATQ
Reserved
0
0
0
0
0
0
0
TIMTST
Test Only
TCBYP
$006E -
$006F
Reserved
PBCTL
0
0
0
5
5
5
5
0
0
4
4
4
4
0
0
3
3
3
3
0
0
2
2
2
2
0
$0070
$0071
$0072
$0073
$0074
$0075
$0076
$0077
$0078
$0079
$007A
$007B
$007C
$007D
$007E
$007F
PBEN
0
PBOVI
0
0
PBFLG
PBOVF
1
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
Bit 0
Bit 0
Bit 0
Bit 0
PA3H
1
1
1
PA2H
PA1H
PA0H
MCCNT (hi)
MCCNT (lo)
TC0H (hi)
TC0H (lo)
TC1H (hi)
TC1H (lo)
TC2H (hi)
TC2H (lo)
TC3H (hi)
TC3H (lo)
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
9
Bit 0
Bit 8
Read: Bit 15
Write:
14
13
12
11
10
Read:
Write:
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
1
9
1
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Read: Bit 15
Write:
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
MC9S12DP512 Device Guide V01.25
$0080 - $009F
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0080
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATD0CTL0
0
0
0
0
0
0
0
0
$0081
$0082
$0083
$0084
$0085
$0086
$0087
$0088
$0089
$008A
$008B
$008C
$008D
$008E
$008F
$0090
$0091
$0092
$0093
$0094
$0095
$0096
$0097
$0098
ATD0CTL1
ATD0CTL2
ATD0CTL3
ATD0CTL4
ATD0CTL5
ATD0STAT0
Reserved
ASCIF
ADPU
0
AFFC
S8C
AWAI ETRIGLE ETRIGP ETRIG
ASCIE
FRZ1
PRS1
S4C
S2C
PRS4
MULT
S1C
FIFO
FRZ0
PRS0
SRES8
DJM
SMP1
SMP0
SCAN
PRS3
0
PRS2
DSGN
0
CC
CB
CA
0
CC2
CC1
CC0
SCF
0
ETORF
0
FIFOR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ATD0TEST0
ATD0TEST1
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
SC
0
Read: CCF7
Write:
CCF6
0
CCF5
0
CCF4
0
CCF3
0
CCF2
0
CCF1
0
CCF0
0
ATD0STAT1
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
ATD0DIEN
Reserved
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
1
9
1
9
1
9
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
PORTAD0
ATD0DR0H
ATD0DR0L
ATD0DR1H
ATD0DR1L
ATD0DR2H
ATD0DR2L
ATD0DR3H
ATD0DR3L
ATD0DR4H
Read: Bit 15
Write:
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
13
12
11
10
33
MC9S12DP512 Device Guide V01.25
$0080 - $009F
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0099
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
ATD0DR4L
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
$009A
$009B
$009C
$009D
$009E
$009F
ATD0DR5H
ATD0DR5L
ATD0DR6H
ATD0DR6L
ATD0DR7H
ATD0DR7L
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
$00A0 - $00C7
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address
$00A0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWME
PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
$00A1
$00A2
$00A3
$00A4
$00A5
$00A6
$00A7
$00A8
$00A9
$00AA
$00AB
$00AC
$00AD
$00AE
PWMPOL
PWMCLK
PWMPRCLK
PWMCAE
PWMCTL
PPOL7
PPOL6
PCLK6
PCKB2
CAE6
PPOL5
PCLK5
PCKB1
CAE5
PPOL4
PCLK4
PCKB0
CAE4
PPOL3
PPOL2
PCLK2
PCKA2
CAE2
PPOL1
PCLK1
PCKA1
PPOL0
PCLK0
PCKA0
PCLK7
0
PCLK3
0
CAE7
CAE3
CAE1
0
CAE0
0
CON67 CON45 CON23 CON01
PSWAI
0
PFRZ
0
0
0
0
0
0
0
0
0
0
0
0
0
PWMTST
Test Only
0
3
0
2
PWMPRSC
PWMSCLA
PWMSCLB
PWMSCNTA
PWMSCNTB
PWMCNT0
PWMCNT1
PWMCNT2
Bit 7
6
5
4
1
Bit 0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
0
0
0
Bit 7
0
Bit 7
0
Bit 7
0
6
0
6
0
6
0
5
0
5
0
5
0
4
0
4
0
4
0
3
0
3
0
3
0
2
0
2
0
2
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
MC9S12DP512 Device Guide V01.25
$00A0 - $00C7
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address
$00AF
Name
Bit 7
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 6
6
0
6
0
6
0
6
0
Bit 5
5
0
5
0
5
0
5
0
Bit 4
4
0
4
0
4
0
4
0
Bit 3
3
0
3
0
3
0
3
0
Bit 2
2
0
2
0
2
0
2
0
Bit 1
1
0
1
0
1
0
1
0
Bit 0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWMCNT3
$00B0
$00B1
$00B2
$00B3
$00B4
$00B5
$00B6
$00B7
$00B8
$00B9
$00BA
$00BB
$00BC
$00BD
$00BE
$00BF
$00C0
$00C1
$00C2
$00C3
$00C4
PWMCNT4
PWMCNT5
PWMCNT6
PWMCNT7
PWMPER0
PWMPER1
PWMPER2
PWMPER3
PWMPER4
PWMPER5
PWMPER6
PWMPER7
PWMDTY0
PWMDTY1
PWMDTY2
PWMDTY3
PWMDTY4
PWMDTY5
PWMDTY6
PWMDTY7
PWMSDN
Reserved
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
3
0
PWM
RSTRT
PWM7
INL
PWM7
ENA
PWMIF PWMIE
PWMLVL
0
PWM7IN
0
0
0
0
0
0
0
$00C5 -
$00C7
35
MC9S12DP512 Device Guide V01.25
$00C8 - $00CF
SCI0 (Asynchronous Serial Interface)
Address
$00C8
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SCI0BDH
SBR12
SBR11
SBR10
SBR9
SBR8
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
SCI0BDL
SC0CR1
SCI0CR2
SCI0SR1
SC0SR2
SCI0DRH
SCI0DRL
SBR7
SBR6
SBR5
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
LOOPS SCISWAI RSRC
WAKE
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
Read: TDRE
Write:
RDRF
IDLE
OR
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
0
0
RAF
0
BRK13
0
TXDIR
0
R8
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$00D0 - $00D7
SCI1 (Asynchronous Serial Interface)
Address
$00D0
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SCI1BDH
SBR12
SBR11
SBR10
SBR9
SBR8
$00D1
$00D2
$00D3
$00D4
$00D5
$00D6
$00D7
SCI1BDL
SC1CR1
SCI1CR2
SCI1SR1
SC1SR2
SCI1DRH
SCI1DRL
SBR7
SBR6
SBR5
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
LOOPS SCISWAI RSRC
WAKE
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
Read: TDRE
Write:
RDRF
IDLE
OR
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
0
0
RAF
0
BRK13
0
TXDIR
0
R8
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$00D8 - $00DF
SPI0 (Serial Peripheral Interface)
Address
$00D8
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPI0CR1
MSTR
CPOL
SSOE
LSBFE
$00D9
$00DA
$00DB
SPI0CR2
SPI0BR
SPI0SR
MODFEN BIDIROE
SPISWAI SPC0
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
SPIF
MODF
0
MC9S12DP512 Device Guide V01.25
$00D8 - $00DF
SPI0 (Serial Peripheral Interface)
Address
$00DC
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Reserved
$00DD
SPI0DR
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
$00DE -
$00DF
Reserved
$00E0 - $00E7
IIC (Inter IC Bus)
Address
$00E0
Name
IBAD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
$00E1
$00E2
$00E3
$00E4
IBFD
IBCR
IBC7
IBC6
IBC5
IBC4
TX/RX
IBAL
IBC3
IBC2
IBC1
0
IBC0
0
IBEN
TCF
IBIE
MS/SL
IBB
TXAK
0
IBSWAI
RXAK
RSTA
SRW
IAAS
IBSR
IBIF
IBDR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D 0
0
$00E5 -
$00E7
Reserved
$00E8 - $00EF
BDLC (Bytelevel Data Link Controller J1850)
Address
$00E8
Name
Bit 7
IMSG
0
Bit 6
CLKS
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
IE
Bit 0
WCM
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
DLCBCR1
I3
I2
I1
I0
0
$00E9
$00EA
$00EB
$00EC
$00ED
$00EE
$00EF
DLCBSVR
DLCBCR2
DLCBDR
SMRST DLOOP RX4XE
NBFS
TEOD
D3
TSIFR
D2
TMIFR1 TMIFR0
D7
0
D6
D5
0
D4
0
D1
D0
DLCBARD
DLCBRSR
DLCSCR
RXPOL
0
BO3
BO2
BO1
BO0
0
0
0
R5
0
R4
R3
0
R2
0
R1
0
R0
0
0
0
BDLCE
0
0
0
0
0
IDLE
DLCBSTAT
37
MC9S12DP512 Device Guide V01.25
$00F0 - $00F7
SPI1 (Serial Peripheral Interface)
Address
$00F0
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPI1CR1
MSTR
CPOL
SSOE
LSBFE
$00F1
$00F2
$00F3
$00F4
$00F5
SPI1CR2
SPI1BR
MODFEN BIDIROE
SPISWAI SPC0
0
SPIF
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
MODF
0
0
0
SPI1SR
0
0
0
0
0
Reserved
SPI1DR
Reserved
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
$00F6 -
$00F7
$00F8 - $00FF
SPI2 (Serial Peripheral Interface)
Address
$00F8
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPI2CR1
MSTR
CPOL
SSOE
LSBFE
$00F9
$00FA
$00FB
$00FC
$00FD
SPI2CR2
SPI2BR
MODFEN BIDIROE
SPISWAI SPC0
0
SPIF
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
MODF
0
0
0
SPI2SR
0
0
0
0
0
Reserved
SPI2DR
Reserved
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
$00FE -
$00FF
$0100 - $010F
Flash Control Register (fts512k4)
Address
$0100
Name
Bit 7
Read: FDIVLD
Write:
Bit 6
Bit 5
FDIV5
NV5
Bit 4
FDIV4
NV4
Bit 3
FDIV3
NV3
Bit 2
FDIV2
NV2
Bit 1
FDIV1
SEC1
Bit 0
FDIV0
SEC0
FCLKDIV
PRDIV8
Read: KEYEN1 KEYEN0
$0101
$0102
$0103
$0104
$0105
FSEC
FTSTMOD
FCNFG
FPROT
FSTAT
Write:
Read:
0
0
0
0
0
0
0
0
WRALL
0
0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CBEIE
FPOPEN
CBEIF
CCIE
KEYACC
BKSEL1 BKSEL0
NV6
FPHDIS FPHS1
PVIOL ACCERR
FPHS0 FPLDIS
FPLS1
0
FPLS0
0
CCIF
0
BLANK
MC9S12DP512 Device Guide V01.25
$0100 - $010F
Flash Control Register (fts512k4)
Address
$0106
Name
FCMD
Bit 7
0
Bit 6
Bit 5
Bit 4
0
Bit 3
0
Bit 2
CMDB2
0
Bit 1
0
Bit 0
CMDB0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CMDB6 CMDB5
0
0
0
0
0
0
$0107
$0108
$0109
$010A
$010B
Reserved
FADDRHI
FADDRLO
FDATAHI
FDATALO
Reserved
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
Bit 8
Bit 0
Bit 8
Bit 15
14
13
12
11
10
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
$010C -
$010F
$0110 - $011B
EEPROM Control Register (eets4k)
Address
$0110
Name
Bit 7
Read: EDIVLD
Write:
Bit 6
PRDIV8
0
Bit 5
EDIV5
0
Bit 4
EDIV4
0
Bit 3
EDIV3
0
Bit 2
EDIV2
0
Bit 1
EDIV1
0
Bit 0
EDIV0
0
ECLKDIV
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
$0111 -
$0112
Reserved
ECNFG
0
0
0
0
0
0
$0113
$0114
$0115
$0116
$0117
$0118
$0119
$011A
$011B
CBEIE
CCIE
NV6
NV5
NV4
EPROT
EPOPEN
EPDIS
0
EP2
EP1
0
EP0
0
CCIF
ESTAT
CBEIF
0
PVIOL ACCERR
0
BLANK
0
0
0
0
0
ECMD
CMDB6 CMDB5
CMDB2
0
CMDB0
0
0
0
0
0
0
0
0
0
Reserved
EADDRHI
EADDRLO
EDATAHI
EDATALO
10
2
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
10
2
$011C - $011F
Reserved for RAM Control Register
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$011C -
$011F
Reserved
39
MC9S12DP512 Device Guide V01.25
$0120 - $013F
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0120
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATD1CTL0
0
0
0
0
0
0
0
0
$0121
$0122
$0123
$0124
$0125
$0126
$0127
$0128
$0129
$012A
$012B
$012C
$012D
$012E
$012F
$0130
$0131
$0132
$0133
$0134
$0135
$0136
$0137
$0138
ATD1CTL1
ATD1CTL2
ATD1CTL3
ATD1CTL4
ATD1CTL5
ATD1STAT0
Reserved
ASCIF
ADPU
0
AFFC
S8C
AWAI ETRIGLE ETRIGP ETRIG
ASCIE
FRZ1
PRS1
S4C
S2C
S1C
FIFO
FRZ0
PRS0
SRES8
SMP1
SMP0
PRS4
PRS3
0
PRS2
DJM
SCF
DSGN
0
SCAN
MULT
CC
CB
CA
ETORF
FIFOR
0
CC2
CC1
CC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ATD1TEST0
ATD1TEST1
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
SC
0
Read: CCF7
Write:
CCF6
0
CCF5
0
CCF4
0
CCF3
0
CCF2
0
CCF1
0
CCF0
0
ATD1STAT1
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
ATD1DIEN
Reserved
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
1
9
1
9
1
9
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
PORTAD1
ATD1DR0H
ATD1DR0L
ATD1DR1H
ATD1DR1L
ATD1DR2H
ATD1DR2L
ATD1DR3H
ATD1DR3L
ATD1DR4H
Read: Bit 15
Write:
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
13
12
11
10
MC9S12DP512 Device Guide V01.25
$0120 - $013F
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0139
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
ATD1DR4L
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
$013A
$013B
$013C
$013D
$013E
$013F
ATD1DR5H
ATD1DR5L
ATD1DR6H
ATD1DR6L
ATD1DR7H
ATD1DR7L
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit 7
$0140 - $017F
CAN0 (Freescale Scalable CAN - FSCAN)
Address
$0140
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN0CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
INITAK
$0141
$0142
$0143
$0144
$0145
$0146
$0147
$0148
$0149
$014A
$014B
CAN0CTL1
CAN0BTR0
CAN0BTR1
CAN0RFLG
CAN0RIER
CAN0TFLG
CAN0TIER
CAN0TARQ
CAN0TAAK
CAN0TBSEL
CAN0IDAC
Reserved
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
BRP1
BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
$014C -
$014D
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$014E
$014F
CAN0RXERR
CAN0TXERR
Write:
Read:
Write:
$0150 - CAN0IDAR0 -
$0153 CAN0IDAR3
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
41
MC9S12DP512 Device Guide V01.25
$0140 - $017F
CAN0 (Freescale Scalable CAN - MSCAN)
Address
$0154 - CAN0IDMR0 -
$0157 CAN0IDMR3
Name
Bit 7
AM7
Bit 6
AM6
Bit 5
AM5
Bit 4
AM4
Bit 3
AM3
Bit 2
AM2
Bit 1
AM1
Bit 0
AM0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0158 - CAN0IDAR4 -
$015B CAN0IDAR7
AC7
AM7
AC6
AM6
AC5
AM5
AC4
AM4
AC3
AM3
AC2
AM2
AC1
AM1
AC0
AM0
$015C - CAN0IDMR4 -
$015F CAN0IDMR7
FOREGROUND RECEIVE BUFFER see Table 1-2
$0160 -
CAN0RXFG
$016F
$0170 -
CAN0TXFG
$017F
FOREGROUND TRANSMIT BUFFER see Table 1-2
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$xxx0
Name
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
Extended ID Read:
Standard ID Read:
CANxRIDR0 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR1 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR2 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR3 Write:
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID9
ID16
ID8
ID15
ID7
$xxx1
$xxx2
$xxx3
ID14
ID6
ID13
ID5
ID12
ID4
ID11
ID3
ID10
ID2
ID1
ID0
RTR
Read:
Write:
Read:
Write:
Read:
Write:
Read: TSR15
Write:
Read: TSR7
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$xxx4 - CANxRDSR0 -
$xxxB CANxRDSR7
DLC3
DLC2
DLC1
DLC0
$xxxC
$xxxD
$xxxE
$xxxF
CANRxDLR
Reserved
TSR14
TSR6
TSR13
TSR5
TSR12
TSR4
TSR11
TSR3
TSR10
TSR2
TSR9
TSR1
TSR8
TSR0
CANxRTSRH
CANxRTSRL
Extended ID Read:
CANxTIDR0 Write:
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR1 Write:
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR2 Write:
Standard ID Read:
Write:
ID28
ID10
ID20
ID2
ID27
ID9
ID26
ID8
ID25
ID7
ID24
ID6
ID23
ID5
ID22
ID4
ID21
ID3
$xx10
$xx11
$xx12
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID10
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID9
ID8
ID7
MC9S12DP512 Device Guide V01.25
Table 1-2 Detailed FSCAN Foreground Receive and Transmit Buffer Layout
Address
$xx13
Name
Bit 7
ID6
Bit 6
ID5
Bit 5
ID4
Bit 4
ID3
Bit 3
ID2
Bit 2
ID1
Bit 1
ID0
Bit 0
RTR
Extended ID Read:
CANxTIDR3 Write:
Standard ID Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: TSR15
Write:
Read: TSR7
Write:
$xx14 - CANxTDSR0 -
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$xx1B
CANxTDSR7
$xx1C
CANxTDLR
DLC3
DLC2
DLC1
DLC0
$xx1D
$xx1E
$xx1F
CANxTTBPR
CANxTTSRH
CANxTTSRL
PRIO7
PRIO6
TSR14
PRIO5
TSR13
PRIO4
TSR12
PRIO3
TSR11
PRIO2
TSR10
PRIO1
TSR9
PRIO0
TSR8
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
$0180 - $01BF
CAN1 (Freescale Scalable CAN - FSCAN)
Address
$0180
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN1CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
INITAK
$0181
$0182
$0183
$0184
$0185
$0186
$0187
$0188
$0189
$018A
$018B
CAN1CTL1
CAN1BTR0
CAN1BTR1
CAN1RFLG
CAN1RIER
CAN1TFLG
CAN1TIER
CAN1TARQ
CAN1TAAK
CAN1TBSEL
CAN1IDAC
Reserved
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
BRP1
BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
$018C -
$018D
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$018E
$018F
CAN1RXERR
CAN1TXERR
Write:
Read:
Write:
$0190 - CAN1IDAR0 -
$0193 CAN1IDAR3
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
43
MC9S12DP512 Device Guide V01.25
$0180 - $01BF
CAN1 (Freescale Scalable CAN - FSCAN)
Address
Name
Bit 7
AM7
Bit 6
AM6
Bit 5
AM5
Bit 4
AM4
Bit 3
AM3
Bit 2
AM2
Bit 1
AM1
Bit 0
AM0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0194 - CAN1IDMR0 -
$0197 CAN1IDMR3
$0198 - CAN1IDAR4 -
$019B CAN1IDAR7
AC7
AM7
AC6
AM6
AC5
AM5
AC4
AM4
AC3
AM3
AC2
AM2
AC1
AM1
AC0
AM0
$019C - CAN1IDMR4 -
$019F CAN1IDMR7
FOREGROUND RECEIVE BUFFER see Table 1-2
$01A0 -
CAN1RXFG
$01AF
$01B0 -
CAN1TXFG
$01BF
FOREGROUND TRANSMIT BUFFER see Table 1-2
$01C0 - $01FF
CAN2 (Freescale Scalable CAN - FSCAN)
Address
$01C0
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN2CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
INITAK
$01C1
$01C2
$01C3
$01C4
$01C5
$01C6
$01C7
$01C8
$01C9
$01CA
$01CB
CAN2CTL1
CAN2BTR0
CAN2BTR1
CAN2RFLG
CAN2RIER
CAN2TFLG
CAN2TIER
CAN2TARQ
CAN2TAAK
CAN2TBSEL
CAN2IDAC
Reserved
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
BRP1
BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
$01CC -
$01CD
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
$01CE CAN2RXERR
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$01CF
CAN2TXERR
Write:
Read:
$01D0 - CAN2IDAR0 -
$01D3 CAN2IDAR3
AC7
AM7
AC6
AM6
AC5
AM5
AC4
AM4
AC3
AM3
AC2
AM2
AC1
AM1
AC0
AM0
Write:
Read:
Write:
$01D4 - CAN2IDMR0 -
$01D7 CAN2IDMR3
MC9S12DP512 Device Guide V01.25
$01C0 - $01FF
CAN2 (Freescale Scalable CAN - FSCAN)
Address
Name
Bit 7
AC7
Bit 6
AC6
Bit 5
AC5
Bit 4
AC4
Bit 3
AC3
Bit 2
AC2
Bit 1
AC1
Bit 0
AC0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$01D8 - CAN2IDAR4 -
$01DB CAN2IDAR7
$01DC - CAN2IDMR4 -
$01DF CAN2IDMR7
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
FOREGROUND RECEIVE BUFFER see Table 1-2
$01E0 -
CAN2RXFG
$01EF
$01F0 -
CAN2TXFG
$01FF
FOREGROUND TRANSMIT BUFFER see Table 1-2
$0200 - $023F
CAN3 (Freescale Scalable CAN - FSCAN)
Address
$0200
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN3CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
BRP1
INITAK
BRP0
$0201
$0202
$0203
$0204
$0205
$0206
$0207
$0208
$0209
$020A
$020B
CAN3CTL1
CAN3BTR0
CAN3BTR1
CAN3RFLG
CAN3RIER
CAN3TFLG
CAN3TIER
CAN3TARQ
CAN3TAAK
CAN3TBSEL
CAN3IDAC
Reserved
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
$020C -
$020D
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$020E
$020F
CAN3RXERR
CAN3TXERR
Write:
Read:
$0210 - CAN3IDAR0 -
$0213 CAN3IDAR3
AC7
AM7
AC7
AC6
AM6
AC6
AC5
AM5
AC5
AC4
AM4
AC4
AC3
AM3
AC3
AC2
AM2
AC2
AC1
AM1
AC1
AC0
AM0
AC0
Write:
Read:
Write:
Read:
Write:
$0214 - CAN3IDMR0 -
$0217 CAN3IDMR3
$0218 - CAN3IDAR4 -
$021B CAN3IDAR7
45
MC9S12DP512 Device Guide V01.25
$0200 - $023F
CAN3 (Freescale Scalable CAN - FSCAN)
Address
$021C - CAN3IDMR4 -
$021F CAN3IDMR7
Name
Bit 7
AM7
Bit 6
AM6
Bit 5
AM5
Bit 4
AM4
Bit 3
AM3
Bit 2
AM2
Bit 1
AM1
Bit 0
AM0
Read:
Write:
Read:
Write:
Read:
Write:
FOREGROUND RECEIVE BUFFER see Table 1-2
$0220 -
CAN3RXFG
$022F
$0230 -
CAN3TXFG
$023F
FOREGROUND TRANSMIT BUFFER see Table 1-2
$0240 - $027F
PIM (Port Integration Module PIM_9DP256)
Address
$0240
Name
PTT
Bit 7
Bit 6
PTT6
PTIT6
Bit 5
PTT5
PTIT5
Bit 4
PTT4
PTIT4
Bit 3
PTT3
PTIT3
Bit 2
PTT2
PTIT2
Bit 1
PTT1
PTIT1
Bit 0
PTT0
PTIT0
Read:
Write:
PTT7
Read: PTIT7
Write:
$0241
$0242
$0243
$0244
$0245
PTIT
DDRT
RDRT
PERT
PPST
Reserved
PTS
Read:
DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST7
0
PPST6
0
PPST5
0
PPST4
0
PPST3
0
PPST2
0
PPST1
0
PPST0
0
$0246 -
$0247
$0248
$0249
$024A
$024B
$024C
$024D
$024E
$024F
$0250
$0251
$0252
$0253
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
Read: PTIS7
Write:
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
PTIS
Read:
DDRS
RDRS
PERS
PPSS
WOMS
Reserved
PTM
DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERS7
PPSS7
PERS6
PPSS6
PERS5
PPSS5
PERS4
PPSS4
PERS3
PPSS3
PERS2
PPSS2
PERS1
PPSS1
PERS0
PPSS0
WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
0
0
0
0
0
0
0
0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
Read: PTIM7
Write:
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
PTIM
Read:
DDRM
RDRM
DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
Write:
Read:
Write:
MC9S12DP512 Device Guide V01.25
$0240 - $027F
PIM (Port Integration Module PIM_9DP256)
Address
$0254
Name
PERM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
$0255
$0256
$0257
$0258
$0259
$025A
$025B
$025C
$025D
$025E
$025F
$0260
$0261
$0262
$0263
$0264
$0265
$0266
$0267
$0268
$0269
$026A
$026B
$026C
PPSM
WOMM
MODRR
PTP
0
MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
Read: PTIP7
Write:
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
PTIP
Read:
DDRP
RDRP
PERP
PPSP
PIEP
DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERP7
PPSP7
PIEP7
PIFP7
PTH7
PERP6
PPSP6
PIEP6
PIFP6
PERP5
PPSP5
PIEP5
PIFP5
PERP4
PPSP4
PIEP4
PIFP4
PERP3
PPSP3
PIEP3
PIFP3
PERP2
PPSP2
PIEP2
PIFP2
PERP1
PPSP1
PIEP1
PIFP1
PERP0
PPSS0
PIEP0
PIFP0
PIFP
PTH
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
Read: PTIH7
Write:
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
PTIH
Read:
DDRH
RDRH
PERH
PPSH
PIEH
DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PPSH7
PIEH7
PIFH7
PTJ7
PPSH6
PIEH6
PIFH6
PPSH5
PIEH5
PPSH4
PIEH4
PPSH3
PIEH3
PPSH2
PIEH2
PPSH1
PIEH1
PIFH1
PPSH0
PIEH0
PIFH0
PIFH
PIFH5
0
PIFH4
0
PIFH3
0
PIFH2
0
PTJ
PTJ6
PTJ1
PTJ0
Read: PTIJ7
Write:
Read:
DDRJ7
Write:
Read:
RDRJ7
Write:
Read:
PERJ7
Write:
PTIJ6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTIJ1
PTIJ0
PTIJ
DDRJ
RDRJ
PERJ
DDRJ7
RDRJ6
PERJ6
DDRJ1
RDRJ1
PERJ1
DDRJ0
RDRJ0
PERJ0
47
MC9S12DP512 Device Guide V01.25
$0240 - $027F
PIM (Port Integration Module PIM_9DP256)
Address
$026D
Name
PPSJ
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
PPSJ7
PPSJ6
PPSJ1
PPSJ0
0
0
0
0
0
0
0
0
$026E
$026F
PIEJ
PIFJ
PIEJ7
PIFJ7
PIEJ6
PIFJ6
PIEJ1
PIFJ1
PIEJ0
PIFJ0
$0270 -
$027F
Reserved
Read:
$0280 - $02BF
CAN4 (Freescale Scalable CAN - FSCAN)
Address
$0280
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN4CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
INITAK
$0281
$0282
$0283
$0284
$0285
$0286
$0287
$0288
$0289
$028A
$028B
CAN4CTL1
CAN4BTR0
CAN4BTR1
CAN4RFLG
CAN4RIER
CAN4TFLG
CAN4TIER
CAN4TARQ
CAN4TAAK
CAN4TBSEL
CAN4IDAC
Reserved
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
BRP1
BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
$028C -
$028D
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$028E
$028F
CAN4RXERR
CAN4TXERR
Write:
Read:
$0290 - CAN4IDAR0 -
$0293 CAN4IDAR3
AC7
AM7
AC7
AC6
AM6
AC6
AC5
AM5
AC5
AC4
AM4
AC4
AC3
AM3
AC3
AC2
AM2
AC2
AC1
AM1
AC1
AC0
AM0
AC0
Write:
Read:
Write:
Read:
Write:
$0294 - CAN4IDMR0 -
$0297 CAN4IDMR3
$0298 - CAN4IDAR4 -
$029B CAN4IDAR7
MC9S12DP512 Device Guide V01.25
$0280 - $02BF
CAN4 (Freescale Scalable CAN - FSCAN)
Address
$029C - CAN4IDMR4 -
$029F CAN4IDMR7
Name
Bit 7
AM7
Bit 6
AM6
Bit 5
AM5
Bit 4
AM4
Bit 3
AM3
Bit 2
AM2
Bit 1
AM1
Bit 0
AM0
Read:
Write:
Read:
Write:
Read:
Write:
FOREGROUND RECEIVE BUFFER see Table 1-2
$02A0 -
CAN4RXFG
$02AF
$02B0 -
CAN4TXFG
$02BF
FOREGROUND TRANSMIT BUFFER see Table 1-2
$02C0 - $03FF
Reserved
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$02C0 -
$03FF
Reserved
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned
part ID number.
Table 1-3 Assigned Part ID Numbers
1
Device
Mask Set Number
Part ID
$0400
$0401
MC9S12DP512
MC9S12DP512
0L00M
1L00M
MC9S12DP512
MC9S12DP512
MC9S12DP512
2L00M
3L00M
4L00M
$0402
$0403
$0404
NOTES:
1. The coding is as follows:
Bit 15 - 12: Major family identifier
Bit 11 - 8: Minor family identifier
Bit 7 - 4: Major mask set revision number including FAB transfers
Bit 3 - 0: Minor - non full - mask set revision
1.7 Memory Size Assignments
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to HCS12 Module
Mapping Control (MMC) Block Guide for further details.
Table 1-4 Memory size registers
Register name
MEMSIZ0
Value
$26
MEMSIZ1
$82
49
MC9S12DP512 Device Guide V01.25
MC9S12DP512 Device Guide V01.25
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
Guides of the individual IP blocks on the device.
51
MC9S12DP512 Device Guide V01.25
2.1 Device Pinout
The MC9S12DP512 is available in a 112-pin low profile quad flat pack (LQFP). Most pins perform two
or more functions, as described in the Signal Descriptions. Figure 2-1 shows the pin assignments.
S
A
S 2
O M C LT
E
S
P
P
P
P
P
V D X
V S X
P
M
P
P
P
P
P
P
V
P
S
S
S
S
S
S
S
P
P
V
V
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
1
VRH
VDDA
2
3
PAD15/AN15/ETRIG1
PAD07/AN07/ETRIG0
PAD14/AN14
4
5
6
PAD06/AN06
PAD13/AN13
7
8
PAD05/AN05
PAD12/AN12
9
IOC1/PT1
IOC2/PT2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PAD04/AN04
PAD11/AN11
IOC3/PT3
VDD1
PAD03/AN03
PAD10/AN10
VSS1
IOC4/PT4
PAD02/AN02
PAD09/AN09
MC9S12DP512
112LQFP
IOC5/PT5
IOC6/PT6
IOC7/PT7
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Figure 2-1 Pin Assignments in 112-pin LQFP
MC9S12DP512 Device Guide V01.25
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality.
Table 2-1 Signal Properties
Internal Pull
Resistor
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Description
Funct. 1
Funct. 2
Funct. 3 Funct. 4 Funct. 5 Supply
Reset
CTRL
State
EXTAL
XTAL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDPLL
Oscillator Pins
RESET
TEST
VDDR
NA
External Reset
None
None
Test Input
VREGEN
XFC
VDDX
VDDPLL
Voltage Regulator Enable Input
PLL Loop Filter
Always
Up
Background Debug, Tag High, Mode
Input
BKGD
PAD15
TAGHI
AN15
MODC
ETRIG1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDR
Up
Port AD Input, Analog Input AN7 of
ATD1, External Trigger Input of ATD1
Port AD Inputs, Analog Inputs
AN[6:0] of ATD1
PAD[14:8]
PAD07
AN[14:08]
AN07
VDDA
None
None
Port AD Input, Analog Input AN7 of
ATD0, External Trigger Input of ATD0
ETRIG0
—
Port AD Inputs, Analog Inputs
AN[6:0] of ATD0
PAD[06:00] AN[06:00]
ADDR[15:8]/
PA[7:0]
PUCR/
PUPAE
—
Port A I/O, Multiplexed Address/Data
Port B I/O, Multiplexed Address/Data
Port E I/O, Access, Clock Select
DATA[15:8]
Disabled
Up
ADDR[7:0]/
PB[7:0]
PUCR/
PUPBE
—
DATA[7:0]
PUCR/
PUPEE
PE7
PE6
NOACC
IPIPE1
XCLKS
While RESET
pin is low:
Down
MODB
MODA
—
—
—
—
Port E I/O, Pipe Status, Mode Input
Port E I/O, Pipe Status, Mode Input
VDDR
While RESET
pin is low:
Down
PE5
IPIPE0
PE4
PE3
PE2
PE1
PE0
ECLK
LSTRB
R/W
—
TAGLO
—
—
—
—
—
—
—
—
—
—
—
Port E I/O, Bus Clock Output
Port E I/O, Byte Strobe, Tag Low
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
Port E Input, Non Maskable Interrupt
PUCR/
PUPEE
Up
IRQ
—
XIRQ
—
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MC9S12DP512 Device Guide V01.25
Internal Pull
Resistor
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Description
Funct. 1
Funct. 2
Funct. 3 Funct. 4 Funct. 5 Supply
Reset
CTRL
State
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
SS2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Port H I/O, Interrupt, SS of SPI2
Port H I/O, Interrupt, SCK of SPI2
Port H I/O, Interrupt, MOSI of SPI2
Port H I/O, Interrupt, MISO of SPI2
Port H I/O, Interrupt, SS of SPI1
Port H I/O, Interrupt, SCK of SPI1
Port H I/O, Interrupt, MOSI of SPI1
Port H I/O, Interrupt, MISO of SPI1
SCK2
MOSI2
MISO2
SS1
PERH/
Disabled
PPSH
VDDR
SCK1
MOSI1
MISO1
Port J I/O, Interrupt, TX of CAN4,
SCL of IIC, TX of CAN0
PJ7
KWJ7
TXCAN4
SCL
TXCAN0
PERJ/
Up
VDDX
VDDX
Port J I/O, Interrupt, RX of CAN4,
SDA of IIC, RX of CAN0
PJ6
PJ[1:0]
PK7
KWJ6
KWJ[1:0]
ECS
RXCAN4
—
SDA
—
RXCAN0
PPSJ
—
—
Port J I/O, Interrupts
Port K I/O, Emulation Chip Select,
ROM Control
ROMCTL
—
PUCR/
Up
PUPKE
XADDR
[19:14]
PK[5:0]
—
—
—
Port K I/O, Extended Addresses
PM7
PM6
TXCAN3
RXCAN3
TXCAN4
RXCAN4
—
—
—
—
Port M I/O, TX of CAN3, TX of CAN4
Port M I/O, RX of CAN3, RX of CAN4
Port M I/O, TX of CAN2, CAN0,
CAN4, SCK of SPI0
PM5
PM4
PM3
PM2
TXCAN2
RXCAN2
TXCAN1
RXCAN1
TXCAN0
RXCAN0
TXCAN0
RXCAN0
TXCAN4
RXCAN4
—
SCK0
MOSI0
SS0
Port M I/O, RX of CAN2, CAN0,
CAN4, MOSI of SPI0
PERM/
Disabled
PPSM
VDDX
Port M I/O, TX of CAN1, CAN0, SS
of SPI0
Port M I/O, RX of CAN1, CAN0,
MISO of SPI0
—
MISO0
PM1
PM0
TXCAN0
RXCAN0
TXB
RXB
—
—
—
—
Port M I/O, TX of CAN0, RX of BDLC
Port M I/O, RX of CAN0, RX of BDLC
Port P I/O, Interrupt, Channel 7 of
PWM, SCK of SPI2
PP7
PP6
PP5
PP4
PP3
PP2
PP1
PP0
KWP7
KWP6
KWP5
KWP4
KWP3
KWP2
KWP1
KWP0
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
SCK2
SS2
—
—
—
—
—
—
—
—
Port P I/O, Interrupt, Channel 6 of
PWM, SS of SPI2
Port P I/O, Interrupt, Channel 5 of
PWM, MOSI of SPI2
MOSI2
MISO2
SS1
Port P I/O, Interrupt, Channel 4 of
PWM, MISO2 of SPI2
PERP/
Disabled
PPSP
VDDX
Port P I/O, Interrupt, Channel 3 of
PWM, SS of SPI1
Port P I/O, Interrupt, Channel 2 of
PWM, SCK of SPI1
SCK1
MOSI1
MISO1
Port P I/O, Interrupt, Channel 1 of
PWM, MOSI of SPI1
Port P I/O, Interrupt, Channel 0 of
PWM, MISO2 of SPI1
MC9S12DP512 Device Guide V01.25
Internal Pull
Resistor
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Description
Funct. 1
Funct. 2
Funct. 3 Funct. 4 Funct. 5 Supply
Reset
CTRL
State
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
SS0
SCK0
MOSI0
MISO0
TXD1
RXD1
TXD0
RXD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Port S I/O, SS of SPI0
Port S I/O, SCK of SPI0
Port S I/O, MOSI of SPI0
Port S I/O, MISO of SPI0
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
PERS/
PPSS
VDDX
VDDX
Up
PERT/
PPST
PT[7:0]
IOC[7:0]
—
—
—
Disabled Port T I/O, Timer channels
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
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MC9S12DP512 Device Guide V01.25
2.3.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Freescale representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
R
0
C
P
MCU
C
S
VDDPLL
VDDPLL
Figure 2-2 PLL Loop Filter Connections
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1
PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. It
can act as an external trigger input for the ATD1.
2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1
PAD14 - PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital
converter ATD1.
2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0
PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD0. It can
act as an external trigger input for the ATD0.
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0
PAD06 - PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital
converter ATD0.
MC9S12DP512 Device Guide V01.25
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
(low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this
pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an
external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured
on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left
floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
EXTAL
C
*
DC
C
MCU
Crystal or
ceramic resonator
1
XTAL
C
2
VSSPLL
* Due to the nature of a translated ground Colpitts oscillator a
DC voltage bias is applied to the crystal
Please contact the crystal manufacturer for crystal DC
bias conditions and recommended capacitor value C
.
DC
Figure 2-3 Colpitts Oscillator Connections (PE7=1)
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MC9S12DP512 Device Guide V01.25
EXTAL
C
1
MCU
RB
Crystal or
ceramic resonator
*
RS
XTAL
C
2
VSSPLL
* Rs can be zero (shorted) when used with higher frequency crystals.
Refer to manufacturer’s data.
Figure 2-4 Pierce Oscillator Connections (PE7=0)
EXTAL
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
(VDDPLL-Level)
MCU
XTAL
not connected
Figure 2-5 External Clock Connections (PE7=0)
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.16 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
MC9S12DP512 Device Guide V01.25
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.18 PE2 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.19 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.20 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
2 (SPI2).
2.3.22 PH6 / KWH6 / SCK2 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
2 (SPI2).
2.3.23 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.24 PH4 / KWH4 / MISO2 — Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
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MC9S12DP512 Device Guide V01.25
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
1 (SPI1).
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
1 (SPI1).
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.29 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for theFreescale Scalable
Controller Area Network controller 0 or 4 (CAN0 or CAN4) or the serial clock pin SCL of the IIC module.
2.3.30 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Freescale Scalable
Controller Area Network controller 0 or 4 (CAN 0 or CAN4) or the serial data pin SDA of the IIC module.
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
2.3.32 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (ECS). During MCU normal expanded modes of operation, this pin is
MC9S12DP512 Device Guide V01.25
used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET,
the state of this pin is latched to the ROMON bit.
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
2.3.34 PM7 / TXCAN3 / TXCAN4 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Freescale Scalable Controller Area Network controllers 3 or 4 (CAN3 or CAN4).
2.3.35 PM6 / RXCAN3 / RXCAN4 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Freescale Scalable Controller Area Network controllers 3 or 4 (CAN3 or CAN4).
2.3.36 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Freescale Scalable Controller Area Network controllers 2, 0 or 4 (CAN2, CAN0 or CAN4). It can be
configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Freescale Scalable Controller Area Network controllers 2, 0 or 4 (CAN2, CAN0 or CAN4). It can be
configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for
the Serial Peripheral Interface 0 (SPI0).
2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Freescale Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.39 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Freescale Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial
Peripheral Interface 0 (SPI0).
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MC9S12DP512 Device Guide V01.25
2.3.40 PM1 / TXCAN0 / TXB — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin
TXB of the BDLC.
2.3.41 PM0 / RXCAN0 / RXB — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin
RXB of the BDLC.
2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output or
an input for the PWM emergency shutdown. It can be configured as serial clock pin SCK of the Serial
Peripheral Interface 2 (SPI2).
2.3.43 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 2 (SPI2).
2.3.45 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 2 (SPI2).
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
MC9S12DP512 Device Guide V01.25
2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).
2.3.50 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.51 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.53 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.54 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
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2.3.55 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12DP512 power and ground pins are described below.
Table 2-2 MC9S12DP512 Power and Ground Connection Summary
Pin Number
Nominal
Voltage
Mnemonic
Description
112-pin QFP
VDD1, 2
VSS1, 2
VDDR
VSSR
13, 65
14, 66
41
2.5 V
0V
Internal power and ground generated by internal regulator
5.0 V
0 V
External power and ground, supply to pin drivers and internal voltage
regulator.
40
VDDX
VSSX
107
106
83
5.0 V
0 V
External power and ground, supply to pin drivers.
VDDA
Operating voltage and ground for the analog-to-digital converters and
the reference for the internal voltage regulator, allows the supply
voltage to the A/D to be bypassed independently.
5.0 V
VSSA
86
0 V
VRL
VRH
85
84
43
0 V
Reference voltages for the analog-to-digital converter.
5.0 V
2.5 V
VDDPLL
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed
independently. Internal power and ground generated by internal
regulator.
VSSPLL
45
97
0 V
5V
VREGEN
Internal Voltage Regulator enable/disable
MC9S12DP512 Device Guide V01.25
NOTE: All VSS pins must be connected together in the application.
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & Internal Voltage
Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE: No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
NOTE: No load allowed except for bypass capacitors.
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2.4.7 VREGEN — On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be
supplied externally.
MC9S12DP512 Device Guide V01.25
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block Guide and OSC Block Guide for details on clock generation.
Core Clock
HCS12 CORE
MEBI
CPU
MMC
BKP
INT
BDM
Flash
RAM
EEPROM
ECT
ATD0, 1
PWM
EXTAL
XTAL
Bus Clock
Oscillator Clock
OSC
CRG
SCI0, SCI1
SPI0, 1, 2
CAN0, 1, 2, 3, 4
IIC
BDLC
PIM
Figure 3-1 Clock Connections
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MC9S12DP512 Device Guide V01.25
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12DP512. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device (Section 4.4 Low Power Modes).
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the
memory map. ROMON = 1 means the Flash is visible in the memory map. The state of the ROMCTL pin
is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
ROMON
Bit
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
0
0
0
X
1
0
1
X
0
1
X
0
1
1
0
0
1
0
1
0
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
1
1
1
1
0
1
X
1
0
1
0
1
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface (MEBI)
Block Guide.
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Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
Description
1
0
Colpitts Oscillator selected
Pierce Oscillator/external clock selected
Table 4-3 Voltage Regulator VREGEN
VREGEN
Description
1
Internal Voltage Regulator enabled
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
0
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
•
•
•
Protection of the contents of FLASH,
Protection of the contents of EEPROM,
Operation in single-chip mode,
Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
MC9S12DP512 Device Guide V01.25
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode or via a sequence of BDM commands. Unsecuring
is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details..
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator Block Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.
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4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
MC9S12DP512 Device Guide V01.25
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
CCR
Mask
HPRIO Value
to Elevate
Vector Address
Interrupt Source
Local Enable
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Reset
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
None
PLLCTL (CME, SCME)
COP rate select
None
–
Clock Monitor fail reset
–
COP failure reset
–
Unimplemented instruction trap
SWI
–
None
–
XIRQ
None
–
IRQ
IRQCR (IRQEN)
CRGINT (RTIE)
TIE (C0I)
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
Real Time Interrupt
Enhanced Capture Timer channel 0
Enhanced Capture Timer channel 1
Enhanced Capture Timer channel 2
Enhanced Capture Timer channel 3
Enhanced Capture Timer channel 4
Enhanced Capture Timer channel 5
Enhanced Capture Timer channel 6
Enhanced Capture Timer channel 7
Enhanced Capture Timer overflow
Pulse accumulator A overflow
Pulse accumulator input edge
SPI0
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSRC2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SPICR1 (SPIE, SPTIE)
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD6, $FFD7
$FFD4, $FFD5
SCI0
SCI1
I-Bit
I-Bit
$D6
$D4
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3
$FFD0, $FFD1
ATD0
ATD1
I-Bit
I-Bit
ATDCTL2 (ASCIE)
ATDCTL2 (ASCIE)
$D2
$D0
PIEJ
$FFCE, $FFCF
$FFCC, $FFCD
Port J
Port H
I-Bit
I-Bit
$CE
$CC
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
PIEH (PIEH7-0)
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$FFCA, $FFCB
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
$FFBC, $FFBD
$FFBA, $FFBB
$FFB8, $FFB9
$FFB6, $FFB7
$FFB4, $FFB5
$FFB2, $FFB3
$FFB0, $FFB1
$FFAE, $FFAF
$FFAC, $FFAD
$FFAA, $FFAB
$FFA8, $FFA9
$FFA6, $FFA7
$FFA4, $FFA5
$FFA2, $FFA3
$FFA0, $FFA1
$FF9E, $FF9F
$FF9C, $FF9D
$FF9A, $FF9B
$FF98, $FF99
$FF96, $FF97
$FF94, $FF95
$FF92, $FF93
$FF90, $FF91
$FF8E, $FF8F
$FF8C, $FF8D
Modulus Down Counter underflow
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
MCCTL (MCZI)
PBCTL (PBOVI)
$CA
$C8
$C6
$C4
$C2
$C0
$BE
$BC
$BA
$B8
$B6
$B4
$B2
$B0
$AE
$AC
$AA
$A8
$A6
$A4
$A2
$A0
$9E
$9C
$9A
$98
$96
$94
$92
$90
$8E
$8C
Pulse Accumulator B Overflow
CRG PLL lock
CRG Self Clock Mode
BDLC
CRGINT (LOCKIE)
CRGINT (SCMIE)
DLCBCR1 (IE)
IIC Bus
IBCR (IBIE)
SPI1
SPICR1 (SPIE, SPTIE)
SPICR1 (SPIE, SPTIE)
ECNFG (CCIE, CBEIE)
FCNFG (CCIE, CBEIE)
CANRIER (WUPIE)
SPI2
EEPROM
FLASH
CAN0 wake-up
CAN0 errors
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CAN0 receive
CAN0 transmit
CAN1 wake-up
CAN1 errors
CANTIER (TXEIE2-TXEIE0)
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CAN1 receive
CAN1 transmit
CAN2 wake-up
CAN2 errors
CANTIER (TXEIE2-TXEIE0)
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CAN2 receive
CAN2 transmit
CAN3 wake-up
CAN3 errors
CANTIER (TXEIE2-TXEIE0)
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CAN3 receive
CAN3 transmit
CAN4 wake-up
CAN4 errors
CANTIER (TXEIE2-TXEIE0)
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CAN4 receive
CAN4 transmit
Port P Interrupt
PWM Emergency Shutdown
CANTIER (TXEIE2-TXEIE0)
PIEP (PIEP7-0)
PWMSDN (PWMIE)
$FF80 to
$FF8B
Reserved
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin
configuration of port A, B, E and K out of reset.
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
MC9S12DP512 Device Guide V01.25
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
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MC9S12DP512 Device Guide V01.25
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the HCS12 CPU Reference Manual for information on the CPU.
6.1.1 Device-specific information
When the HCS12 CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods.
So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Module Mapping Control (MMC) Block Description
Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module.
6.2.1 Device-specific information
•
INITEE
– Reset state: $01
– Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special
modes".
•
PPAGE
– Reset state: $00
– Register is "Write anytime in all modes"
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module.
6.3.1 Device-specific information
•
PUCR
– Reset state: $90
6.4 HCS12 Interrupt (INT) Block Description
Consult the INT Block Guide for information on the HCS12 Interrupt module.
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6.5 HCS12 Background Debug (BDM) Block Description
Consult the BDM Block Guide for information on the HCS12 Background Debug module.
6.5.1 Device-specific information
When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
6.6 HCS12 Breakpoint (BKP) Block Description
Consult the BKP Block Guide for information on the HCS12 Breakpoint module.
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
The Low Voltage Reset feature of the CRG is not available on this device.
Section 8 Oscillator (OSC) Block Description
8.1 Device-specific information
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Section 9 Enhanced Capture Timer (ECT) Block
Description
Consult the ECT_16B8C Block Guide for information about the Enhanced Capture Timer module.
When the ECT_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 10 Analog to Digital Converter (ATD) Block
Description
MC9S12DP512 Device Guide V01.25
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DP512.
Consult the ATD_10B8C Block Guide for information about each Analog to Digital Converter module.
When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 11 Inter-IC Bus (IIC) Block Description
Consult the IIC Block Guide for information about the Inter-IC Bus module.
Section 12 Serial Communications Interface (SCI) Block
Description
There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DP512
device.
Consult the SCI Block Guide for information about each Serial Communications Interface module.
Section 13 Serial Peripheral Interface (SPI) Block
Description
There are three Serial Peripheral Interfaces (SPI2, SPI1 and SPI0) implemented on MC9S12DP512.
Consult the SPI Block Guide for information about each Serial Peripheral Interface module.
Section 14 J1850 (BDLC) Block Description
Consult the BDLC Block Guide for information about the J1850 module.
Section 15 Pulse Width Modulator (PWM) Block
Description
Consult the PWM_8B6C Block Guide for information about the Pulse Width Modulator module.
When the PWM_8B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 16 Flash EEPROM 512K Block Description
Consult the FTS512K4 Block Guide for information about the flash module.
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MC9S12DP512 Device Guide V01.25
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into
the flash memory of this device during manufacture. This LRAE program will provide greater
programming flexibility to the end users by allowing the device to be programmed directly using CAN or
SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if
not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and
its implementation, please see the S12 LREA Application Note (AN2546/D).
It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE
programmed in the Flash. Exact details of the changeover (i.e. blank to programmed) for each product will
be communicated in advance via GPCN and will be traceable by the customer via datecode marking on
the device.
Please contact Freescale Sales if you have any additional questions.
Section 17 EEPROM 4K Block Description
Consult the EETS4K Block Guide for information about the EEPROM module.
Section 18 RAM Block Description
This module supports single-cycle misaligned word accesses.
Section 19 MSCAN Block Description
There are five MSCAN modules (CAN4, CAN3, CAN2, CAN1 and CAN0) implemented on the
MC9S12DP512.
Consult the MSCAN Block Guide for information about the Freescale Scalable CAN Module.
Section 20 Port Integration Module (PIM) Block Description
Consult the functionally equivalent PIM_9DP256 Block Guide for information about the Port Integration
Module.
Section 21 Voltage Regulator (VREG) Block Description
Consult the VREG Block Guide for information about the dual output linear voltage regulator.
MC9S12DP512 Device Guide V01.25
Section 22 Printed Circuit Board Layout Proposal
Table 22-1 Suggested External Component Values
Component
Purpose
Type
Value
100 … 220nF
100 … 220nF
100nF
C1
C2
VDD1 filter cap
VDD2 filter cap
VDDA filter cap
VDDR filter cap
VDDPLL filter cap
VDDX filter cap
OSC load cap
ceramic X7R
ceramic X7R
ceramic X7R
X7R/tantalum
ceramic X7R
X7R/tantalum
C3
C4
>= 100nF
100nF
C5
C6
>= 100nF
C7
C8
OSC load cap
C9 / CS
PLL loop filter cap
See PLL specification chapter
C10 / CP
PLL loop filter cap
DC cutoff cap
Colpitts mode only, if recommended by
quartz manufacturer
C11 / CDC
R1 / R
PLL loop filter res
See PLL Specification chapter
R2 / RB
Pierce mode only
R3 / RS
Q1
Quartz
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 – C6).
•
•
•
•
Central point of the ground star should be the VSSR pin.
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
VSSPLL must be directly connected to VSSR.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
•
•
Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
81
MC9S12DP512 Device Guide V01.25
Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator
V
V DDX
C
VSSA
C3
VSSX
VDDA
VDD1
VSS1
C1
VSS2
C2
VDD2
VSSR
VDDR
Q1
VSSPLL
VDDPLL
R1
MC9S12DP512 Device Guide V01.25
Figure 22-2 Recommended PCB Layout for 112LQFP Pierce Oscillator
V
V DDX
C
VSSA
C3
VSSX
VDDA
VDD1
VSS1
C1
VSS2
C2
VDD2
VSSR
VDDR
VSSPLL
R3
R2
Q1
VDDPLL
R1
83
MC9S12DP512 Device Guide V01.25
MC9S12DP512 Device Guide V01.25
Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Freescale and are subject to
change without notice.
This supplement contains the most accurate electrical information for the MC9S12DP512 microcontroller
available at the time of publication. The information should be considered PRELIMINARY and is subject
to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE: This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12DP512 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL
and internal logic.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
85
MC9S12DP512 Device Guide V01.25
The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage
regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the
oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.3.5 VREGEN
This pin is used to enable the on chip voltage regulator.
MC9S12DP512 Device Guide V01.25
A.1.4 Current Injection
Power supply must maintain regulation within operating V
or V range during instantaneous and
DD
DD5
operating maximum current conditions. If positive injection current (V > V
) is greater than I
, the
in
DD5
DD5
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
or V
).
SS5
DD5
1
Table A-1 Absolute Maximum Ratings
Num
Rating
Symbol
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max
6.0
3.0
3.0
0.3
0.3
6.0
6.0
3.0
10.0
Unit
V
VDD5
1
2
3
4
5
6
7
8
9
I/O, Regulator and Analog Supply Voltage
Digital Logic Supply Voltage 2
VDD
V
PLL Supply Voltage (2)
VDDPLL
V
∆
Voltage difference VDDX to VDDR and VDDA
Voltage difference VSSX to VSSR and VSSA
Digital I/O Input Voltage
V
VDDX
∆
V
VSSX
VIN
VRH, VRL
VILV
V
Analog Reference
V
XFC, EXTAL, XTAL inputs
TEST input
V
VTEST
V
Instantaneous Maximum Current
Single pin limit for all digital I/O pins 3
ID
10
11
12
-25
-25
+25
+25
mA
mA
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL4
IDL
Instantaneous Maximum Current
Single pin limit for TEST 5
IDT
-0.25
– 65
0
mA
Tstg
13
Storage Temperature Range
155
°C
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
87
MC9S12DP512 Device Guide V01.25
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA
.
4. Those pins are internally clamped to VSSPLL and VDDPLL
.
5. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
1500
100
Unit
Ohm
pF
Series Resistance
R1
C
Storage Capacitance
Human Body
Number of Pulse per pin
positive
negative
-
3
3
-
Series Resistance
R1
C
0
Ohm
pF
Storage Capacitance
200
Machine
Latch-up
Number of Pulse per pin
positive
negative
-
3
3
-
Minimum input voltage limit
Maximum input voltage limit
-2.5
7.5
V
V
Table A-3 ESD and Latch-up Protection Characteristics
Num C
Rating
Symbol
VHBM
Min
2000
200
Max
Unit
1
2
3
C Human Body Model (HBM)
-
-
-
V
V
V
VMM
C Machine Model (MM)
VCDM
C Charge Device Model (CDM)
Latch-up Current at TA = 125°C
500
ILAT
4
5
C
+100
-100
-
-
mA
mA
positive
negative
Latch-up Current at TA = 27°C
ILAT
C
+200
-200
positive
negative
MC9S12DP512 Device Guide V01.25
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature T and the junction temperature T . For power dissipation
A
J
calculations refer to Section A.1.8 Power Dissipation and Thermal
Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
4.5
Typ
5
Max
5.25
2.75
2.75
0.1
Unit
V
VDD5
I/O, Regulator and Analog Supply Voltage
Digital Logic Supply Voltage 1
VDD
2.35
2.35
-0.1
-0.1
2.5
2.5
0
V
PLL Supply Voltage (1)
VDDPLL
V
∆
Voltage Difference VDDX to VDDR and VDDA
Voltage Difference VSSX to VSSR and VSSA
Bus Frequency (MC9S12DP512C, V, M)
MC9S12DP512C
V
VDDX
∆
0
0.1
V
VSSX
0.25 2
fbus
-
25
MHz
TJ
TA
Operating Junction Temperature Range
-40
-40
-
100
85
°C
°C
Operating Ambient Temperature Range 3
MC9S12DP512V
27
TJ
TA
Operating Junction Temperature Range
-40
-40
-
120
105
°C
°C
Operating Ambient Temperature Range (3)
MC9S12DP512M
27
TJ
TA
Operating Junction Temperature Range
-40
-40
-
140
125
°C
°C
Operating Ambient Temperature Range (3)
27
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
given operating range applies when this regulator is disabled and the device is powered from an external source.
2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper oper-
ation.
3. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the rela-
tion between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (T ) in °C can be
J
obtained from:
89
MC9S12DP512 Device Guide V01.25
T = T + (P • Θ
)
J
A
D
JA
T = Junction Temperature, [°C]
J
T
= Ambient Temperature, [°C]
A
D
P
= Total Chip Power Dissipation, [W]
Θ
= Package Thermal Resistance, [°C/W]
JA
The total power dissipation can be calculated from:
= P
P
+ P
D
INT
IO
P
= Chip Internal Power Dissipation, [W]
INT
Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled
P
= I
⋅ V
+ I
⋅ V
+ I
⋅ V
INT
DD DD DDPLL DDPLL DDA DDA
2
P
=
R
⋅ I
DSON IO
∑
IO
i
i
P is the sum of all output currents on I/O ports associated with VDDX and VDDR.
IO
For R
is valid:
DSON
V
OL
R
= ----------- ;for outputs driven low
DSON
V
I
OL
respectively
– V
DD5
OH
R
= ----------------------------------- ;for outputs driven high
DSON
I
OH
2. Internal voltage regulator enabled
= I
P
⋅ V
+ I
⋅ V
INT
DDR DDR DDA DDA
I
is the current shown in Table A-7 and not the overall current flowing into VDDR, which
DDR
additionally contains the current flowing into the external loads with output high.
2
P
=
R
⋅ I
DSON IO
∑
IO
i
i
P is the sum of all output currents on I/O ports associated with VDDX and VDDR.
IO
MC9S12DP512 Device Guide V01.25
1
Table A-5 Thermal Package Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
Thermal Resistance LQFP112, single sided PCB2
oC/W
θJA
1
T
-
-
54
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
oC/W
θJA
2
T
-
-
41
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all pins feature pull up/down resistances.
91
MC9S12DP512 Device Guide V01.25
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
-
Unit
V
VIH
0.65*VDD5
1
2
P Input High Voltage
-
VIH
VIL
T Input High Voltage
P Input Low Voltage
T Input Low Voltage
C Input Hysteresis
-
-
VDD5 + 0.3
0.35*VDD5
V
-
-
-
V
VIL
VSS5 - 0.3
-
-
-
V
VHYS
3
4
250
mV
Input Leakage Current (pins in high impedance input
mode)
Iin
P
P
–1
-
-
1
-
µA
V
in = VDD5 or VSS5
Output High Voltage (pins in output mode)
Partial Drive I
= –2mA
VOH
VDD5 – 0.8
5
6
OH
= –10mA
V
Full Drive I
OH
Output Low Voltage (pins in output mode)
Partial Drive I = +2mA
VOL
P
OL
= +10mA
-
-
0.8
V
Full Drive I
OL
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
7
8
P
C
P
C
-
-10
-
-
-
-
-130
-
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
Internal Pull Down Device Current,
tested at VIH Min.
9
130
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
Cin
10
10
-
-
-
-
µA
11 D Input Capacitance
Injection current1
6
pF
IICS
IICP
12
T
-2.5
-25
-
2.5
25
mA
Single Pin limit
Total Device Limit. Sum of all injected currents
Port H, J, P Interrupt Input Pulse filtered2
Port H, J, P Interrupt Input Pulse passed(2)
tPIGN
tPVAL
13
14
P
P
-
-
-
3
-
µs
µs
10
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
MC9S12DP512 Device Guide V01.25
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Run supply currents
1
P
-
-
mA
IDD5
Single Chip, Internal regulator enabled
65
Wait Supply current
All modules enabled, PLL on
only RTI enabled (1)
IDDW
2
P
P
-
-
-
40
5
mA
Pseudo Stop Current (RTI and COP disabled) 1, 2
C
P
C
C
P
C
P
C
P
370
400
450
550
600
650
800
850
1200
-40°C
500
27°C
70°C
85°C
IDDPS
3
4
5
µA
1600
2100
5000
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
Pseudo Stop Current (RTI and COP enabled) (1), (2)
C
C
C
C
C
C
C
570
600
650
750
850
-40°C
27°C
70°C
85°C
105°C
125°C
140°C
IDDPS
-
-
µA
1200
1500
Stop Current (2)
C
P
C
C
P
C
P
C
P
12
25
-40°C
100
27°C
70°C
100
130
160
200
350
400
600
85°C
IDDS
-
µA
1200
1700
5000
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
93
MC9S12DP512 Device Guide V01.25
NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed
MC9S12DP512 Device Guide V01.25
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V
≤ V ≤ V ≤ V ≤ V
. This constraint exists since the sample buffer amplifier can not drive
SSA
RL
IN
RH
DDA
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
VRL
VRH
VSSA
VDDA/2
VDDA
1
D
Low
High
-
V
V
VDDA/2
Differential Reference Voltage1
V
RH-VRL
2
3
C
4.50
0.5
5.00
-
5.25
2.0
V
fATDCLK
D ATD Clock Frequency
MHz
ATD 10-Bit Conversion Period
D
Clock Cycles2
NCONV10
TCONV10
4
5
14
7
-
-
28
14
Cycles
µs
Conv, Time at 2.0MHz ATD Clock fATDCLK
ATD 8-Bit Conversion Period
Clock Cycles(2)
NCONV8
TCONV8
D
D
12
6
26
13
Cycles
µs
Conv, Time at 2.0MHz ATD Clock fATDCLK
Recovery Time (VDDA=5.0 Volts)
tREC
IREF
IREF
6
7
8
-
-
-
-
-
-
20
µs
P Reference Supply current 2 ATD blocks on
P Reference Supply current 1 ATD block on
0.750
0.375
mA
mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
S
95
MC9S12DP512 Device Guide V01.25
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, C ≥ 1024 * (C - C ).
f
INS
INN
A.2.2.3 Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than V and $000 for values less than
RH
V
unless the current is higher than specified as disruptive condition.
RL
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V
= K * R *
ERR
S
I
, with I being the sum of the currents injected into the two pins adjacent to the converted
INJ
INJ
channel.
Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
RS
1
C Max input Source Resistance
-
-
1
KΩ
Total Input Capacitance
T Non Sampling
Sampling
CINN
CINS
2
-
-
10
22
pF
INA
Kp
Kn
3
4
5
C Disruptive Analog Input Current
-2.5
-
-
-
2.5
10-4
10-2
mA
A/A
A/A
C Coupling Ratio positive current injection
C Coupling Ratio negative current injection
-
-
MC9S12DP512 Device Guide V01.25
A.2.3 ATD accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
f
= 2.0MHz
ATDCLK
Num C
Rating
Symbol
LSB
DNL
INL
Min
-
Typ
5
Max
-
Unit
mV
1
2
3
4
5
6
7
8
P 10-Bit Resolution
P 10-Bit Differential Nonlinearity
P 10-Bit Integral Nonlinearity
–1
-
1
Counts
Counts
Counts
mV
–2.5
-3
1.5
2.0
20
-
2.5
3
10-Bit Absolute Error1
P
AE
P 8-Bit Resolution
LSB
DNL
INL
-
-
P 8-Bit Differential Nonlinearity
P 8-Bit Integral Nonlinearity
–0.5
–1.0
-1.5
0.5
1.0
1.5
Counts
Counts
Counts
0.5
1.0
8-Bit Absolute Error(1)
P
AE
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
V – V
i
i – 1
DNL(i) =
– 1
------------------------
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
V – V
n
0
-------------------
1LSB
INL(n) =
DNL(i) =
– n
∑
i = 1
97
MC9S12DP512 Device Guide V01.25
DNL
10-Bit Absolute Error Boundary
LSB
V
V
i
i-1
$3FF
$3FE
$3FD
$3FC
$3FB
$3FA
$3F9
$3F8
$3F7
$3F6
$3F5
$3F4
$3F3
8-Bit Absolute Error Boundary
$FF
$FE
$FD
2
9
8
7
6
5
4
3
2
1
0
Ideal Transfer Curve
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5
10
15
20
25
30
35
40
45
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-1 ATD Accuracy Definitions
NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10.
MC9S12DP512 Device Guide V01.25
A.3 NVM, Flash and EEPROM
NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.3.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f
is required for performing program or erase operations. The NVM modules
NVMOSC
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as f
.
NVMOP
The minimum program and erase times shown in Table A-11 are calculated for maximum f
and
NVMOP
maximum f . The maximum times are calculated for minimum f
and a f of 2MHz.
bus
NVMOP
bus
A.3.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency f and can be calculated according to the following formula.
NVMOP
1
1
t
= 9 ⋅
+ 25 ⋅
---------------------
----------
swpgm
f
f
NVMOP
bus
A.3.1.2 Row Programming
This applies only to the Flash where up to 64 words in a row can be programmed consecutively by keeping
the command pipeline filled. The time to program a consecutive word can be calculated as:
1
1
t
= 4 ⋅
+ 9 ⋅
---------------------
----------
bwpgm
f
f
NVMOP
bus
The time to program a whole row is:
t
= t
+ 63 ⋅ t
swpgm bwpgm
brpgm
Row programming is more than 2 times faster than single word programming.
A.3.1.3 Sector Erase
Erasing a 1024 byte Flash sector or a 4 byte EEPROM sector takes:
1
t
≈ 4000 ⋅
---------------------
era
f
NVMOP
99
MC9S12DP512 Device Guide V01.25
The setup time can be ignored for this operation.
A.3.1.4 Mass Erase
Erasing a NVM block takes:
1
t
≈ 20000 ⋅
---------------------
mass
f
NVMOP
The setup time can be ignored for this operation.
A.3.1.5 Blank Check
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t
≈ location ⋅ t
+ 10 ⋅ t
cyc cyc
check
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fNVMOSC
fNVMBUS
fNVMOP
tswpgm
Min
0.5
1
Typ
Max
Unit
MHz
MHz
kHz
µs
50 1
-
1
2
3
4
5
6
7
8
9
D External Oscillator Clock
-
-
-
-
-
-
-
-
-
-
D Bus frequency for Programming or Erase Operations
D Operating Frequency
150
200
46 2
20.4 (2)
1331.2 (2)
20 5
74.5 3
31 (3)
P Single Word Programming Time
Flash Row Programming consecutive word 4
Flash Row Programming Time for 64 Words (4)
tbwpgm
tbrpgm
tera
D
D
µs
(3)
µs
2027.5
26.7 (3)
133 (3)
P Sector Erase Time
ms
100 (5)
11 6
tmass
tcheck
tcheck
P Mass Erase Time
ms
65546 7
2058 (7)
tcyc
tcyc
D Blank Check Time Flash per block
11 (6)
10 D Blank Check Time EEPROM per block
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus
3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus
.
.
Refer to formulae in Sections Section A.3.1.1 Single Word Programming- Section A.3.1.4 Mass Erasefor guidance.
4. Row Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP
.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block
MC9S12DP512 Device Guide V01.25
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed
1
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Flash Reliability Characteristics
Data retention after 10,000 program/erase cycles at
1002
1002
—
1
2
3
4
C
C
C
C
15
—
—
—
—
an average junction temperature of TJavg ≤ 85°C
tFLRET
Years
Data retention with <100 program/erase cycles at an
20
average junction temperature TJavg ≤ 85°C
Number of program/erase cycles
10,000
10,000
(–40°C ≤ TJ ≤ 0°C)
nFL
Cycles
Number of program/erase cycles
100,0003
(0°C ≤ TJ ≤ 140°C)
EEPROM Reliability Characteristics
Data retention after up to 100,000 program/erase
1002
cycles at an average junction temperature of
5
C
15
—
TJavg ≤ 85°C
tEEPRET
Years
Data retention with <100 program/erase cycles at an
1002
—
6
7
8
C
C
C
20
—
—
—
average junction temperature TJavg ≤ 85°C
Number of program/erase cycles
10,000
100,000
(–40°C ≤ TJ ≤ 0°C)
nEEP
Cycles
Number of program/erase cycles
300,0003
(0°C < TJ ≤ 140°C)
NOTES:
1. TJavg will not exeed 85°C considering a typical temperature profile over the lifetime of a consumer, industrial or automotive
application.
2. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618.
3. Spec table quotes typical endurance evaluated at 25°C for this product family, typical endurance at various temperature can
be estimated using the graph below. For additional information on how Freescale defines Typical Endurance, please refer
to Engineering Bulletin EB619.
101
MC9S12DP512 Device Guide V01.25
Figure A-2 Typical Endurance vs Temperature
500
450
400
350
300
250
200
150
100
50
Cycl es]
3
0
60
80
120
-40
-20
0
20
40
100
140
Operating Temperature T [°C]
J
------ Flash
------ EEPROM
MC9S12DP512 Device Guide V01.25
A.4 Voltage Regulator
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external
DC load is allowed.
Table A-13 Voltage Regulator Recommended Load Capacitances
Rating
Load Capacitance on VDD1, 2
Load Capacitance on VDDPLL
Symbol
CLVDD
Min
Typ
220
220
Max
Unit
nF
-
-
-
-
CLVDDfcPLL
nF
103
MC9S12DP512 Device Guide V01.25
MC9S12DP512 Device Guide V01.25
A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
Table A-14 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
VPORR
VPORA
PWRSTL
nRST
Min
-
Typ
Max
Unit
V
1
2
3
4
5
6
T POR release level
T POR assert level
-
-
-
-
-
-
2.07
0.97
2
-
-
V
tosc
nosc
D Reset input pulse width, minimum input time
D Startup from Reset
192
20
-
196
-
PWIRQ
tWRS
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
ns
tcyc
14
A.5.1.1 POR
The release level V
and the assert level V
are derived from the V Supply. They are also valid
PORA DD
PORR
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t no valid oscillation is detected, the MCU will start using the internal self
CQOUT
clock. The fastest startup time possible is given by n
.
uposc
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW
the CRG module generates an internal
RSTL
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.5.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
105
MC9S12DP512 Device Guide V01.25
A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts
wrs
fetching the interrupt vector.
A.5.2 Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce
oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. t
specifies the maximum time before switching to the internal self clock mode after
CQOUT
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time t . The device also features a clock monitor. A Clock Monitor Failure is
UPOSC
asserted if the frequency of the incoming clock signal is below the Assert Frequency f
CMFA.
Table A-15 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
0.5
0.5
100
-
Typ
Max
Unit
MHz
MHz
µA
fOSC
1a C Crystal oscillator range (Colpitts)
-
-
-
16
40
-
Crystal oscillator range (Pierce) 1
C
fOSC
iOSC
1b
2
P Startup Current
82
-
1003
2.5
tUPOSC
tCQOUT
fCMFA
fEXT
3
C Oscillator start-up time (Colpitts)
D Clock Quality check time-out
P Clock Monitor Failure Assert Frequency
ms
s
4
0.45
50
0.5
9.5
9.5
-
5
100
-
200
50
KHz
MHz
ns
External square wave input frequency 4
P
6
External square wave pulse width low 4
D
tEXTL
tEXTH
tEXTR
tEXTF
CIN
7
-
-
-
-
External square wave pulse width high 4
D
8
ns
External square wave rise time 4
D
9
-
1
1
-
ns
External square wave fall time 4
D
10
-
-
ns
11 D Input Capacitance (EXTAL, XTAL pins)
DC Operating Bias in Colpitts Configuration on
-
7
pF
VDCBIAS
12
C
-
1.1
-
V
EXTAL Pin
EXTAL Pin Input High Voltage 4
EXTAL Pin Input High Voltage 4
EXTAL Pin Input Low Voltage 4
EXTAL Pin Input Low Voltage 4
EXTAL Pin Input Hysteresis 4
VIH,EXTAL 0.75*VDDPLL
13
P
T
P
T
C
-
-
V
V
VIH,EXTAL
VIL,EXTAL
VDDPLL + 0.3
0.25*VSSPLL
-
-
-
14
15
-
-
V
VIL,EXTAL VSSPLL - 0.3
VHYS,EXTAL
-
-
V
-
250
mV
MC9S12DP512 Device Guide V01.25
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. fosc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. Only valid if Pierce oscillator/external clock mode is selected
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
C
p
VDDPLL
R
C
XFC Pin
s
Phase
VCO
f
f
vco
f
1
ref
osc
∆
K
K
Φ
V
refdv+1
Detector
f
cmp
Loop Divider
1
1
2
synr+1
Figure A-3 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K , f and i from Table A-16.
1
1
ch
The grey boxes show the calculation for f
= 50MHz and f = 1MHz. E.g., these frequencies are used
ref
VCO
for f
= 4MHz and a 25MHz bus clock.
OSC
The VCO Gain at the desired VCO frequency is approximated by:
(f1 – fvco
-----------------------
K1 ⋅ 1V
)
(60 – 50)
-----------------------
–100
K = K ⋅ e
= -90.48MHz/V
= –100 ⋅ e
V
1
107
MC9S12DP512 Device Guide V01.25
The phase detector relationship is given by:
K = – i ⋅ K
V
= 316.7Hz/Ω
Φ
ch
i is the current in tracking mode.
ch
The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
C
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ⋅ ζ ⋅ f
f
ref
1
ref
f < ------------------------------------------
→ f < ------------- ;(ζ = 0.9)
------
10
C
C
4 ⋅ 10
fC < 25kHz
2
⎛
⎞
π ⋅ ζ + 1 + ζ
⎝
⎠
And finally the frequency relationship is defined as
f
VCO
n = ------------- = 2 ⋅ (s y n r + 1 )
= 50
f
ref
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f =10kHz:
C
2 ⋅ π ⋅ n ⋅ f
C
= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
R = ----------------------------
K
Φ
The capacitance C can now be calculated as:
s
2
0.516
2 ⋅ ζ
= 5.19nF =~ 4.7nF
C =
≈ --------------;(ζ = 0.9)
---------------------
s
f ⋅ R
π ⋅ f ⋅ R
C
C
The capacitance C should be chosen in the range of:
p
C ⁄ 20 ≤ C ≤ C ⁄ 10
Cp = 470pF
s
p
s
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock f , the
cmp
deviation from the reference clock f is measured and input voltage to the VCO is adjusted
ref
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
MC9S12DP512 Device Guide V01.25
1
2
3
N-1
N
0
t
min1
t
nom
t
max1
t
minN
t
maxN
Figure A-4 Jitter Definitions
is at its maximum for one clock period, and decreases towards zero for larger
The relative deviation of t
nom
number of clock periods (N).
Defining the jitter as:
t
(N)
t
(N)
min
⎛
⎞
⎟
⎠
max
J(N) = max 1 –
, 1 –
--------------------
---------------------
⎜
N ⋅ t
N ⋅ t
⎝
nom
nom
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
J(N) =
+ j
-------
2
N
J(N)
1
5
10
20
N
Figure A-5 Maximum bus clock jitter approximation
109
MC9S12DP512 Device Guide V01.25
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Table A-16 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fSCM
Min
1
Typ
Max
5.5
Unit
MHz
MHz
1
2
P Self Clock Mode frequency
D VCO locking range
-
-
fVCO
8
50
Lock Detector transition from Acquisition to Tracking
mode
1
|∆trk
|
3
D
3
-
4
%
(1)
|∆Lock
|
4
5
D Lock Detection
0
-
-
1.5
2.5
%
(1)
|∆unl
|
D Un-Lock Detection
0.5
%
Lock Detector transition from Tracking to Acquisition
mode
(1)
|∆unt
|
6
D
6
-
8
%
PLLON Total Stabilization delay (Auto Mode) 2
C
tstab
tacq
tal
7
8
9
-
-
-
-
-
-
-
-
-
0.5
0.3
0.2
-100
60
-
ms
ms
PLLON Acquisition mode stabilization delay (2)
D
-
PLLON Tracking mode stabilization delay (2)
D
-
ms
K1
f1
10 D Fitting parameter VCO loop gain
11 D Fitting parameter VCO loop frequency
12 D Charge pump current acquisition mode
13 D Charge pump current tracking mode
-
MHz/V
MHz
µA
-
-
| ich
| ich
j1
|
38.5
3.5
-
|
-
µA
Jitter fit parameter 1(2)
Jitter fit parameter 2(2)
14
15
C
C
1.1
0.13
%
j2
-
%
NOTES:
1. % deviation from target frequency
2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
10KΩ.
MC9S12DP512 Device Guide V01.25
A.6 MSCAN
Table A-17 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
tWUP
Min
Typ
Max
Unit
µs
1
2
P MSCAN Wake-up dominant pulse filtered
P MSCAN Wake-up dominant pulse pass
-
-
-
2
-
tWUP
5
µs
111
MC9S12DP512 Device Guide V01.25
MC9S12DP512 Device Guide V01.25
A.7 SPI
This section provides electrical parametrics and ratings for the SPI.
In Table A-18 the measurement conditions are listed.
Table A-18 Measurement Conditions
Description
Value
Unit
Drive mode
full drive mode
—
Load capacitance CLOAD,
on all outputs
50
pF
V
Thresholds for delay
measurement points
(20% / 80%) VDDX
A.7.1 Master Mode
In Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1
(OUTPUT)
2
1
12
12
13
13
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
10
9
11
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6 SPI Master Timing (CPHA=0)
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
113
MC9S12DP512 Device Guide V01.25
SS1
(OUTPUT)
1
12
12
13
13
3
2
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
11
BIT 6 . . . 1
LSB IN
9
MOSI
(OUTPUT)
MASTER MSB OUT2
PORT DATA
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-7 SPI Master Timing (CPHA=1)
In Table A-19 the timing characteristics for master mode are listed.
Table A-19 SPI Master Mode Timing Characteristics
Num
Characteristic
Symbol
Unit
Min
1/2048
2
Typ
—
Max
fsck
tsck
tlead
tlag
twsck
tsu
fbus
tbus
tsck
tsck
tsck
ns
1
1
SCK Frequency
1/2
2048
—
SCK Period
—
2
Enable Lead Time
—
1/2
1/2
1/2
—
3
Enable Lag Time
—
—
4
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
—
—
5
8
—
thi
6
8
—
—
ns
tvsck
tvss
tho
9
—
—
30
15
—
ns
10
11
12
13
—
—
ns
20
—
—
ns
trfi
—
8
ns
trfo
—
—
8
ns
MC9S12DP512 Device Guide V01.25
A.7.2 Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS
(INPUT)
1
12
12
13
13
3
SCK
(CPOL = 0)
(INPUT)
4
4
2
SCK
(CPOL = 1)
(INPUT)
10
7
8
9
11
11
MISO
(OUTPUT)
see
note
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined!
Figure A-8 SPI Slave Timing (CPHA=0)
In Figure A-9 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
115
MC9S12DP512 Device Guide V01.25
SS
(INPUT)
3
1
12
13
13
2
SCK
(CPOL = 0)
(INPUT)
4
4
12
11
SCK
(CPOL = 1)
(INPUT)
8
9
MISO
(OUTPUT)
see
note
BIT 6 . . . 1
SLAVE
5
MSB OUT
6
SLAVE LSB OUT
LSB IN
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE: Not defined!
Figure A-9 SPI Slave Timing (CPHA=1)
In Table A-20 the timing characteristics for slave mode are listed.
Table A-20 SPI Slave Mode Timing Characteristics
Num
Characteristic
Symbol
Unit
Min
DC
4
Typ
—
—
—
—
—
—
—
—
—
Max
1/4
∞
fsck
tsck
tlead
tlag
twsck
tsu
fbus
tbus
tbus
tbus
tbus
ns
1
1
2
3
4
5
6
7
8
9
SCK Frequency
SCK Period
Enable Lead Time
4
—
Enable Lag Time
4
—
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Slave Access Time (time to data active)
Slave MISO Disable Time
Data Valid after SCK Edge
4
—
8
—
thi
8
—
ns
ta
—
—
20
22
ns
tdis
tvsck
ns
1
1
—
—
ns
30 + tbus
tvss
tho
trfi
10
11
Data Valid after SS fall
—
20
—
—
—
—
—
—
ns
ns
ns
ns
30 + tbus
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
—
8
12
trfo
13
8
NOTES:
1. tbus added due to internal synchronization delay
MC9S12DP512 Device Guide V01.25
A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing
values shown on table Table A-21. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
117
MC9S12DP512 Device Guide V01.25
1, 2
3
4
ECLK
PE4
5
9
6
16
10
15
11
Addr/Data
(read)
PA, PB
data
data
addr
7
8
12
14
data
13
Addr/Data
(write)
PA, PB
data
addr
17
19
23
26
18
Non-Multiplexed
Addresses
PK5:0
20
21
22
ECS
PK7
24
27
25
28
R/W
PE2
29
32
LSTRB
PE3
31
34
30
33
NOACC
PE7
35
36
IPIPE0
IPIPE1, PE6,5
Figure A-10 General External Bus Timing
MC9S12DP512 Device Guide V01.25
Table A-21 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
Rating
Symbol
fo
Min
0
Typ
Max
Unit
MHz
ns
1
2
3
4
5
6
7
8
9
P Frequency of operation (E-clock)
P Cycle time
-
-
-
-
-
-
-
-
-
-
-
-
-
25.0
tcyc
40
19
19
-
-
-
PWEL
D Pulse width, E low
ns
Pulse width, E high1
D
PWEH
tAD
-
ns
D Address delay time
8
-
ns
Address valid time to E rise (PWEL–tAD
)
tAV
D
11
2
ns
tMAH
tAHDS
tDHA
tDSR
tDHR
tDDW
tDHW
tDSW
D Muxed address hold time
D Address hold to data valid
D Data hold to address
-
ns
7
-
ns
2
-
ns
10 D Read data setup time
11 D Read data hold time
12 D Write data delay time
13 D Write data hold time
13
0
-
ns
-
ns
-
7
-
ns
2
ns
Write data setup time(1) (PWEH–tDDW
)
14
15
16
D
D
D
12
19
-
-
-
-
ns
ns
Address access time(1) (tcyc–tAD–tDSR
E high access time(1) (PWEH–tDSR
)
tACCA
tACCE
tNAD
tNAV
tNAH
tCSD
tACCS
tCSH
tCSN
tRWD
tRWV
tRWH
tLSD
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
17 D Non-multiplexed address delay time
Non-muxed address valid to E rise (PWEL–tNAD
)
18
D
13
2
19 D Non-multiplexed address hold time
20 D Chip select delay time
-
-
16
-
Chip select access time(1) (tcyc–tCSD–tDSR
)
21
D
11
2
22 D Chip select hold time
23 D Chip select negated time
24 D Read/write delay time
-
8
-
-
7
-
Read/write valid time to E rise (PWEL–tRWD
)
25
D
14
2
26 D Read/write hold time
27 D Low strobe delay time
-
-
7
-
Low strobe valid time to E rise (PWEL–tLSD
)
tLSV
28
D
14
2
tLSH
29 D Low strobe hold time
-
tNOD
tNOV
30 D NOACC strobe delay time
-
7
-
NOACC valid time to E rise (PWEL–tNOD
)
31
D
14
119
MC9S12DP512 Device Guide V01.25
Table A-21 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
Rating
Symbol
tNOH
Min
2
Typ
Max
Unit
ns
32 D NOACC hold time
33 D IPIPE[1:0] delay time
-
-
-
-
7
-
tP0D
2
ns
IPIPE[1:0] valid time to E rise (PWEL–tP0D
)
tP0V
34
35
D
D
11
ns
IPIPE[1:0] delay time(1) (PWEH-tP1V
)
tP1D
tP1V
2
-
-
7
-
ns
ns
36 D IPIPE[1:0] valid time to E fall
11
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
MC9S12DP512 Device Guide V01.25
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12DP512 packages.
121
MC9S12DP512 Device Guide V01.25
B.2 112-pin LQFP package
4X
0.20 T L-M N
4X 28 TIPS
0.20 T L-M N
4X
P
J1
J1
PIN 1
IDENT
112
85
C
1
84
L
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
METAL
F
D
29
56
M
0.13
T L-M N
N
SECTION J1-J1
A1
S1
ROTATED 90 COUNTERCLOCKWISE
°
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
S
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
C2
VIEW AB
θ2
C
0.050
112X
0.10
T
SEATING
PLANE
MILLIMETERS
DIM MIN
MAX
20.000 BSC
10.000 BSC
θ3
A
A1
B
B1
C
T
20.000 BSC
10.000 BSC
---
1.600
C1 0.050
C2 1.350
0.150
1.450
0.370
0.750
0.330
θ
D
E
F
0.270
0.450
0.270
G
J
K
0.650 BSC
0.090
0.170
R R2
0.500 REF
0.325 BSC
P
R1 0.100
R2 0.100
0.200
0.200
0.25
R R1
S
S1
V
V1
Y
22.000 BSC
11.000 BSC
GAGE PLANE
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
(K)
Z
C1
θ1
AA 0.090
0.160
8 °
E
0 °
θ
θ1
θ2
θ3
3 °
11 °
11 °
7 °
(Y)
(Z)
13 °
13 °
VIEW AB
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987)
MC9S12DP512 Device Guide V01.25
User Guide End Sheet
123
MC9S12DP512 Device Guide V01.25
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