MCF51JM128VLH_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF51JM128

Rev. 4, 05/2012

MCF51JM128

80 LQFP

64 LQFP

14 mm  14 mm

10 mm  10 mm

MCF51JM128 ColdFire

Microcontroller

64 QFP

14 mm  14 mm

44 LQFP

10 mm  10 mm

The MCF51JM128 is a member of the ColdFire family of

32-bit reduced instruction set computing (RISC)

microprocessors. This document provides an overview of the

MCF51JM128 series, focusing on its highly integrated and

diverse feature set.

The MCF51JM128 series is based on the V1 ColdFire core

and operates at processor core speeds up to 50.33 MHz. As

®

part of Freescale’s Controller Continuum , it is an ideal

upgrade for designs based on the MC9S08JM60 series of 8-bit

microcontrollers.

The MCF51JM128 features the following functional units:

• V1 ColdFire core with background debug module

• Up to 128 KB of flash memory

• Up to 16 KB of static RAM (SRAM)

• Multipurpose clock generator (MCG)

• Dual-role Universal Serial Bus On-The-Go device

(USBOTG)

• Controller-area network (MSCAN)

• Cryptographic acceleration unit (CAU)

• Random number generator accelerator (RNGA)

• Analog comparators (ACMP)

• Analog-to-digital converter (ADC) with up to 12 channels

• Two Inter-integrated circuit (IIC) modules

• Two serial peripheral interfaces (SPI)

• Two serial communications interfaces (SCI)

• Carrier modulation timer (CMT)

• Eight-channel timer/pulse-width modulators (TPM)

• Real-time counter (RTC)

• 66 general-purpose input/output (GPIO) modules plus

Interrupt request input

• Eight keyboard interrupts (KBI)

• 16-bit Rapid GPIO

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Table of Contents

1

2

MCF51JM128 Family Configurations . . . . . . . . . . . . . . . . . . . .3

Figure 13.Timer Input Capture Pulse. . . . . . . . . . . . . . . . . . . . . 30

Figure 14.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 32

Figure 15.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 32

Figure 16.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 33

Figure 17.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 33

Figure 18.80-pin LQFP Diagram - I . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.80-pin LQFP Diagram - II. . . . . . . . . . . . . . . . . . . . . . 37

Figure 20.80-pin LQFP Diagram - III . . . . . . . . . . . . . . . . . . . . . 38

Figure 21.64-pin LQFP Diagram - I . . . . . . . . . . . . . . . . . . . . . . 39

Figure 22.64-pin LQFP Diagram - II. . . . . . . . . . . . . . . . . . . . . . 40

Figure 23.64-pin LQFP Diagram - III . . . . . . . . . . . . . . . . . . . . . 41

Figure 24.64-pin QFP Diagram - I . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 25.64-pin QFP Diagram - II. . . . . . . . . . . . . . . . . . . . . . . 43

Figure 26.64-pin QFP Diagram - III . . . . . . . . . . . . . . . . . . . . . . 44

Figure 27.44-pin LQFP Diagram - I . . . . . . . . . . . . . . . . . . . . . . 45

Figure 28.44-pin LQFP Diagram - II. . . . . . . . . . . . . . . . . . . . . . 46

Figure 29.44-pin LQFP Diagram - III . . . . . . . . . . . . . . . . . . . . . .47

1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.5 Pinouts and Packaging . . . . . . . . . . . . . . . . . . . . . . . . .10

Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .15

2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15

2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15

2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .16

2.4 Electrostatic Discharge (ESD) Protection Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21

2.7 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .23

2.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.9 External Oscillator (XOSC) Characteristics . . . . . . . . .26

2.10 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34

2.14 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

2.15 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36

3.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

3.3 64-pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.4 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

List of Tables

Table 1. MCF51JM128 Series Device Comparison . . . . . . . . . . 3

Table 2. MCF51JM128 Series Functional Units . . . . . . . . . . . . . 5

Table 3. Orderable Part Number Summary. . . . . . . . . . . . . . . . . 8

Table 4. Pin Assignments by Package and Pin Sharing Priority 12

Table 5. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16

Table 7. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 17

Table 9. ESD and Latch-Up Protection Characteristics. . . . . . . 18

Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 21

Table 12.Analog Comparator Electrical Specifications. . . . . . . . 23

Table 13.5 Volt 12-bit ADC Operating Conditions . . . . . . . . . . . 23

Table 14.5 Volt 12-bit ADC Characteristics (VREFH = VDDA, VREFL

= VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15.Oscillator Electrical Specifications (Temperature Range =

–40 to 105×C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16.MCG Frequency Specifications (Temperature Range = –40

to 125×C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 18.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19.MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . 30

Table 20.SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21.Flash Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 22.Internal USB 3.3V Voltage Regulator Characteristics . 35

Table 23.Internal Revision History . . . . . . . . . . . . . . . . . . . . . . . 50

Table 24.Changes Between Revisions. . . . . . . . . . . . . . . . . . . . 51

3

4

List of Figures

Figure 1.MCF51JM128 Block Diagram . . . . . . . . . . . . . . . . . . . . 4

Figure 2.80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3.64-pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.Typical Low-side Drive (sink) characteristics – High Drive

(PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.Typical Low-side Drive (sink) characteristics – Low Drive

(PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7.Typical High-side Drive (source) characteristics – High

Drive (PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8.Typical High-side Drive (source) characteristics – Low Drive

(PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9.ADC Input Impedance Equivalency Diagram . . . . . . . 24

Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 11.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 29

MCF51JM128 ColdFire Microcontroller, Rev. 4

2

Freescale Semiconductor

MCF51JM128 Family Configurations

1

MCF51JM128 Family Configurations

1.1

Device Comparison

The MCF51JM128 series consists of the devices compared in Table 1.

Table 1. MCF51JM128 Series Device Comparison

MCF51JM32

MCF51JM128

Feature

MCF51JM64

80-pin 64-pin 44-pin 80-pin 64-pin 44-pin 80-pin 64-pin 44-pin

Flash memory size (KB)

RAM size (KB)

128

16

64

16

32

16

V1 ColdFire core with BDM (background

debug module)

Yes

ACMP (analog comparator)

ADC channels (12-bit)

CAN (controller area network)

RNGA + CAU

Yes

12

8

12

8

12

8

Yes

No

Yes

Yes¹

Yes

No

Yes

No

CMT (carrier modulator timer)

COP (computer operating properly)

IIC1 (inter-integrated circuit)

IIC2

Yes

8

No

Yes

8

No

Yes

8

No

IRQ (interrupt request input)

KBI (keyboard interrupts)

LVD (low-voltage detector)

MCG (multipurpose clock generator)

Port I/O²

Yes

8

6

8

6

Yes

51

66

16

51

6

33

0

66

16

33

0

66

16

51

6

33

0

RGPIO (rapid general-purpose I/O)

RTC (real-time counter)

SCI1 (serial communications interface)

SCI2

6

Yes

6

SPI1 (serial peripheral interface)

SPI2

TPM1 (timer/pulse-width modulator)

channels

6

4

6

4

6

4

TPM2 channels

2

USBOTG (USB On-The-Go dual-role

controller)

Yes

XOSC (crystal oscillator)

Yes

1

Only existed on special part number

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

3

MCF51JM128 Family Configurations

2

Up to 16 pins on Ports A, H, and J are shared with the ColdFire Rapid GPIO module.

1.2

Block Diagram

Figure 1 shows the connections between the MCF51JM128 series pins and modules.

PTA7/RGPIO7

PTA6/RGPIO6

PTA5/RGPIO5

PTA4/RGPIO4

PTA3/RGPIO3

PTA2/RGPIO2

PTA1/RGPIO1

PTA0/RGPIO0

VREFH

VREFL

VDDA

VSSA

VREFH

VREFL

VDDAD

VSSAD

Port B:

ADP7

ADP6

ADP5

ADP4

ADP3

ADP2

ADP1

ADP0

Port D:

ADP11

ADP10

ADP9

ADP8

Port D:

ACMPO

ACMP–

ACMP+

ACMP

Port C:

IRO

BKGD/MS

CMT

IIC1

DBG

BDM

CAU

ADC

PTB7/ADP7

PTB6/ADP6

Port C:

SDA1

SCL1

PTB5/KBIP5/ADP5

PTB4/KBIP4/ADP4

PTB3/SS2/ADP3

PTB2/SPSCK2/ADP2

PTB1/MOSI2/ADP1

PTB0/MISO2/ADP0

V1 ColdFire core

SYSCTL

RESET

Port H:

SCL2

SDA2

IIC2

IRQ/TPMCLK

TPMCLK

Port F:

TPM1CH5

TPM1CH4

TPM1CH3

TPM1CH2

Port E:

PTC7

Port B:

KBIP5

KBIP4

Port D:

KBIP3

KBIP2

Port G:

KBIP7

KBIP6

KBIP1

KBIP0

PTC6/RXCAN

PTC5/RXD2

PTC4

PTC3/TXD2

PTC2/IRO

PTC1/SDA1

PTC0/SCL1

TPM1

TPM2

TPM1CH1

TPM1CH0

IRQ

COP

LVD

KBI

TPMCLK

Port F:

TPM2CH1

TPM2CH0

PTD7

PTD6

PTD5

PTD4/ADP11

PTD3/KBIP3/ADP10

PTD2/KBIP2/ACMPO

PTD1/ACMP–/ADP9

PTD0/ACMP+/ADP8

FLASH

128 or 64 KB

Port G:

EXTAL

XTAL

MCG

XOSC

CAN

RAM

16 or 8 KB

PTE7/SS1

Port C:

RXCAN

Port F:

TXCAN

Port J:

PTE6/SPSCK1

PTE5/MOSI1

PTE4/MISO1

PTE3/TPM1CH1

PTE2/TPM1CH0

PTE1/RXD1

RGPIO15

RGPIO14

RGPIO13

RGPIO12

RGPIO11

Port H:

PTE0/TXD1

RGPIO10

RGPIO9

RGPIO8

Port A:

RGPIO7

RGPIO6

RGPIO5

RGPIO4

RGPIO3

RGPIO2

RGPIO1

RGPIO0

PTF7/TXCAN

PTF6

RGPIO

PTF5/TPM2CH1

PTF4/TPM2CH0

PTF3/TPM1CH5

PTF2/TPM1CH4

PTF1/TPM1CH3

PTF0/TPM1CH2

Port E:

RXD1

TXD1

PTG7

PTG6

SCI1

SCI2

PTG5/EXTAL

PTG4/XTAL

PTG3/KBIP7

PTG2/KBIP6

PTG1/KBIP1

PTG0/KBIP0

Port C:

RXD2

TXD2

VDD

VSS

VREG

Port E:

SS1

SPSCK1

MOSI1

MISO1

PTH4/RGPIO10

PTH3/RGPIO9

PTH2/RGPIO8

PTH1/SCL2

SPI1

SPI2

INTC

RNGA

RTC

PTH0/SDA2

Port B:

SS2

SPSCK2

MOSI2

MISO2

PTJ4/RGPIO15

PTJ3/RGPIO14

PTJ2/RGPIO13

PTJ1/RGPIO12

PTJ0/RGPIO11

USBDN

USBDP

VUSB33

USB

Figure 1. MCF51JM128 Block Diagram

MCF51JM128 ColdFire Microcontroller, Rev. 4

4

Freescale Semiconductor

MCF51JM128 Family Configurations

1.3

Features

Table 2 describes the functional units of the MCF51JM128 series.

Table 2. MCF51JM128 Series Functional Units

Unit

Function

CF1CORE (V1 ColdFire core)

BDM (background debug module)

DBG (debug)

Executes programs and interrupt handlers

Provides a single-pin debugging interface (part of the V1 ColdFire core)

Provides debugging and emulation capabilities (part of the V1 ColdFire core)

Provides LVD, COP, external interrupt request, and so on

Provides storage for program code and constants

Provides storage for program code, constants, and variables

Allows I/O port access at CPU clock speeds

SYSCTL (system control)

FLASH (flash memory)

RAM (random-access memory)

RGPIO (rapid general-purpose input/output)

VREG (voltage regulator)

Controls power management throughout the device

Supports the USB On-The-Go dual-role controller

Measures analog voltages at up to 12 bits of resolution

Provide a variety of timing-based features

USBOTG (USB On-The-Go)

ADC (analog-to-digital converter)

TPM1, TPM2 (timer/pulse-width modulators)

CF1_INTC (interrupt controller)

CAU (cryptographic acceleration unit)

Controls and prioritizes all device interrupts

Co-processor support for DES, 3DES, AES, MD5, and SHA-1

RNGA (random number generator accelerator) 32-bit random number generator that complies with FIPS-140

RTC (real-time counter)

Provides a constant-time base with optional interrupt

Compares two analog inputs

ACMP (analog comparator)

CMT (carrier modulator timer)

IIC1, IIC2 (inter-integrated circuits)

KBI (keyboard interrupt)

Infrared output used for the Remote Controller

Supports the standard IIC communications protocol

Provides pin interrupt capabilities

MCG (multipurpose clock generator)

Provides clocking options for the device, including a phase-locked loop (PLL)

and frequency-locked loop (FLL) for multiplying slower reference clock

sources

XOSC (crystal oscillator)

Supports low/high range crystals

CAN (controller area network)

Supports standard CAN communications protocol

Serial communications UARTs that can support RS-232 and LIN protocols

Provide a 4-pin synchronous serial interface

SCI1, SCI2 (serial communications interfaces)

SPI1, SPI2 (serial peripheral interfaces)

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

5

MCF51JM128 Family Configurations

1.3.1

Feature List

•

32-bit Version 1 ColdFire Central Processor Unit (CPU)

— Up to 50.33 MHz at 2.7 V – 5.5 V

— Performance (Dhrystone 2.1):

–

0.94 Dhrystone 2.1 MIPS per MHz when running from internal RAM

0.76 Dhrystone 2.1 MIPS per MHz when running from flash

— Implements Instruction Set Revision C (ISA_C)

— Supports up to 30 peripheral interrupt requests and seven software interrupts

On-chip memory

•

— Up to 128 KB Flash memory with read/program/erase over full operating voltage and temperature range

— Up to 16 KB static random access memory (RAM)

— Security circuitry to prevent unauthorized access to RAM and flash contents

Power-saving modes

— Two low-power stop plus wait modes

— Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents; this behavior

allows clocks to remain enabled to specific perhipherals in Stop3 mode

— Very lower power real-time counter for use in run, wait, and stop modes with internal and external clock sources

Four Clock Source Options

•

— Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz

or 1 MHz to 16 MHz

— FLL/PLL controlled by internal or external reference

— Trimmable internal reference allows 0.2% resolution and 2% deviation

System protection features

— Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source

or bus clock

— Low-voltage detection with reset or interrupt; selectable trip points

— Illegal opcode and illegal address detection with programmable reset or exception response

— Flash block protection

•

Debug support

— Single-wire Background debug interface

— 4 Program Counters plus two address (optional data) breakpoint registers with programmable 1- or 2-level trigger

response

— 64-entry processor status and debug data trace buffer with programmable start/stop conditions

Universal Serial Bus (USB) On-The-Go dual-role controller

— Full-speed USB device controller

–

Fully compliant with USB specification 1.1 and 2.0

16 bidirectional endpoints, with double buffering to provide the maximum throughput

Supports control, bulk, interrupt, and isochronous endpoints

Supports bus-powered capability with low-power consumption

— Full-speed / low-speed host controller

Host mode allows control, bulk, interrupt, and isochronous transfers

–

— OTG protocol logic

— On-chip USB transceiver

— On-chip 3.3 V USB regulator and pull-up resistors save system cost

MCF51JM128 ColdFire Microcontroller, Rev. 4

6

Freescale Semiconductor

MCF51JM128 Family Configurations

•

Controller area network (MSCAN)

— Implementation of the CAN protocol — Version 2.0A/B

— Five receive buffers with FIFO storage scheme

— Three transmit buffers with internal prioritization using a “local priority” concept

— Flexible maskable identifier filter programmable as 2x32-bit, 4x16-bit, or 8x8-bit

— Programmable wakeup functionality with integrated low-pass filter

— Programmable loopback mode supports self-test operation

— Programmable bus-off recovery functionality

— Internal timer for time-stamping of received and transmitted messages

Cryptographic acceleration unit (CAU)

•

— Co-processor support of DES, 3DES, AES, MD5, and SHA-1

Random number generator accelerator (RNGA)

— 32-bit random number generator that complies with FIPS-140

Analog-to-digital converter (ADC)

— 12-channel, 12-bit resolution

— Output formatted in 12-, 10-, or 8-bit right-justified format

— Single or continuous conversion, and selectable asynchronous hardware conversion trigger

— Operation in Stop3 mode

— Automatic compare function

— Internal temperature sensor

•

Analog comparators (ACMP)

— Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output

— Option to compare to fixed internal bandgap reference voltage

— Option to route output to TPM module

— Operation in Stop3 mode

Inter-integrated circuit (IIC)

— Up to 100 kbps with maximum bus loading

— Multi-master operation

— Programmable slave address

— Supports broadcast mode and 10-bit address extension

Serial communications interfaces (SCI)

— Two SCIs with full-duplex, non-return-to-zero (NRZ) format

— LIN master extended break generation

— LIN slave extended break detection

— Programmable 8-bit or 9-bit character length

— Wake up on active edge

•

Serial peripheral interfaces (SPI)

— Two serial peripheral interfaces with full-duplex or single-wire bidirectional

— Double-buffered transmit and receive

— Programmable transmit bit rate, phase, polarity, and Slave Select output

— MSB-first or LSB-first shifting

Timer/pulse width modulator (TPM)

— 16-bit free-running or modulo up/down count operation

— Up to eight channels, where each channel can be an input capture, output compare, or edge-aligned PWM

— One interrupt per channel plus terminal count interrupt

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

7

MCF51JM128 Family Configurations

•

RTC

— 8-bit modulus counter with binary- or decimal-based prescaler

— External clock source for precise time base, time-of-day, calendar or task scheduling functions

— Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components

Carrier modulator timer (CMT)

•

— carrier generator, modulator, and transmitter drive the infrared out (IRO) pin

— operation in independent high/low time control, baseband, FSK, and direct IRO control modes

Input/Output

— 66 GPIOs

— Eight keyboard interrupt pins with selectable polarity

— Hysteresis and configurable pull-up device on all input pins; configurable slew rate and drive strength on all output

pins

— 16 bits of Rapid GPIO connected to the processor’s local 32-bit platform bus with set, clear, and faster toggle

functionality

1.4

Part Numbers

Table 3. Orderable Part Number Summary

Freescale Part

Number

Flash / SRAM

(KB)

Description

Package

Temperature

MCF51JM128EVLK

MCF51JM128 ColdFire Microcontroller

with CAU and RNGA Enabled

128 / 16

80 LQFP

–40 to +105 C

MCF51JM128VLK

MCF51JM128EVLH

MCF51JM128 ColdFire Microcontroller

128 / 16

80 LQFP

64 LQFP

–40 to +105 C

MCF51JM128 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM128VLH

MCF51JM128 ColdFire Microcontroller

128 / 16

64 LQFP

64 QFP

–40 to +105 C

MCF51JM128EVQH

MCF51JM128 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM128VQH

MCF51JM128EVLD

MCF51JM128 ColdFire Microcontroller

128 / 16

64 QFP

–40 to +105 C

MCF51JM128 ColdFire Microcontroller

with CAU and RNGA Enabled

44 LQFP

MCF51JM128VLD

MCF51JM64EVLK

MCF51JM128 ColdFire Microcontroller

128 / 16

64 / 16

44 LQFP

80 LQFP

–40 to +105 C

MCF51JM64 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM64VLK

MCF51JM64EVLH

MCF51JM64 ColdFire Microcontroller

64 / 16

80 LQFP

64 LQFP

–40 to +105 C

MCF51JM64 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM64VLH

MCF51JM64 ColdFire Microcontroller

64 / 16

64 LQFP

64 QFP

–40 to +105 C

MCF51JM64EVQH

MCF51JM64 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM64VQH

MCF51JM64 ColdFire Microcontroller

64 / 16

64 QFP

–40 to +105 C

MCF51JM128 ColdFire Microcontroller, Rev. 4

8

Freescale Semiconductor

MCF51JM128 Family Configurations

Table 3. Orderable Part Number Summary (continued)

MCF51JM64EVLD

MCF51JM64 ColdFire Microcontroller

with CAU and RNGA Enabled

64 / 16

44 LQFP

–40 to +105 C

MCF51JM64VLD

MCF51JM32EVLK

MCF51JM64 ColdFire Microcontroller

64 / 16

32 / 16

44 LQFP

80 LQFP

–40 to +105 C

MCF51JM32 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM32VLK

MCF51JM32EVLH

MCF51JM32 ColdFire Microcontroller

32 / 16

80 LQFP

64 LQFP

–40 to +105 C

MCF51JM32 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM32VLH

MCF51JM32 ColdFire Microcontroller

32 / 16

64 LQFP

64 QFP

–40 to +105 C

MCF51JM32EVQH

MCF51JM32 ColdFire Microcontroller

with CAU and RNGA Enabled

MCF51JM32VQH

MCF51JM32EVLD

MCF51JM32 ColdFire Microcontroller

32 / 16

64 QFP

–40 to +105 C

MCF51JM32 ColdFire Microcontroller

with CAU and RNGA Enabled

44 LQFP

MCF51JM32VLD

MCF51JM32 ColdFire Microcontroller

32 / 16

44 LQFP

–40 to +105 C

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

9

MCF51JM128 Family Configurations

1.5

Pinouts and Packaging

Figure 2 shows the pinout of the 80-pin LQFP.

PTC4

IRQ / TPMCLK

RESET

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

PTJ3 / RGPIO14

PTJ2 / RGPIO13

PTJ1 / RGPIO12

PTJ0 / RGPIO11

PTD2 / KBIP2 / ACMPO

VSSA

2

3

PTF0 / TPM1CH2

PTF1 / TPM1CH3

PTF2 / TPM1CH4

PTF3 / TPM1CH5

PTF4 / TPM2CH0

PTC6 / RXCAN

PTF7 / TXCAN

PTF5 / TPM2CH1

PTF6

4

5

6

7

VREFL

8

VREFH

9

VDDA

10

11

12

13

14

15

16

17

18

19

20

PTD1 / ADP9 / ACMP–

PTD0 / ADP8 / ACMP+

PTB7 / ADP7

PTE0 / TXD1

PTB6 / ADP6

PTE1 / RXD1

PTE2 / TPM1CH0

PTE3 / TPM1CH1

PTC7

PTB5 / KBIP5 / ADP5

PTB4 / KBIP4 / ADP4

PTB3 / SS2 / ADP3

PTB2 / SPSCK2 / ADP2

PTB1 / MOSI2 / ADP1

PTB0 / MISO2 / ADP0

PTA7 / RGPIO7

PTH0 / SDA2

PTH1 / SCL2

PTH2 / RGPIO8

Figure 2. 80-pin LQFP

MCF51JM128 ColdFire Microcontroller, Rev. 4

10

Freescale Semiconductor

MCF51JM128 Family Configurations

Figure 3 shows the pinout of the 64-pin LQFP and QFP.

PTC4

IRQ / TPMCLK

RESET

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PTD2 / KBIP2 / ACMPO

VSSA

2

3

VREFL

PTF0 / TPM1CH2

PTF1 / TPM1CH3

PTF2 / TPM1CH4

PTF3 / TPM1CH5

PTF4 / TPM2CH0

PTC6 / RXCAN

PTF7 / TXCAN

PTF5 / TPM2CH1

PTF6

4

VREFH

5

VDDA

6

PTD1 / ADP9 / ACMP–

PTD0 / ADP8 / ACMP+

PTB7 / ADP7

7

8

9

PTB6 / ADP6

10

11

12

13

14

15

16

PTB5 / KBIP5 / ADP5

PTB4 / KBIP4 / ADP4

PTB3 / SS2 / ADP3

PTB2 / SPSCK2 / ADP2

PTB1 / MOSI2 / ADP1

PTB0 / MISO2 / ADP0

PTA5 / RGPIO5

PTE0 / TXD1

PTE1 / RXD1

PTE2 / TPM1CH0

PTE3 / TPM1CH1

Figure 3. 64-pin QFP and LQFP

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

11

MCF51JM128 Family Configurations

Figure 4 shows the pinout of the 44-pin LQFP.

PTC4

IRQ / TPMCLK

RESET

1

33

32

31

30

29

28

27

26

25

24

23

PTD2 / KBIP2 / ACMPO

VSSA / VREFL

2

3

VDDA / VREFH

PTF0 / TPM1CH2

PTF1 / TPM1CH3

PTF4 / TPM2CH0

PTF5 / TPM2CH1

PTE0 / TXD1

4

PTD1 / ADP9 / ACMP–

PTD0 / ADP8 / ACMP+

PTB5 / KBIP5 / ADP5

PTB4 / KBIP4 / ADP4

PTB3 / SS2 / ADP3

PTB2 / SPSCK2 / ADP2

PTB1 / MOSI2 / ADP1

PTB0 / MISO2 / ADP0

5

6

7

8

PTE1 / RXD1

9

PTE2 / TPM1CH0

PTE3 / TPM1CH1

10

11

Figure 4. 44-pin LQFP

Table 4 shows the package pin assignments.

Table 4. Pin Assignments by Package and Pin Sharing Priority

Pin Number <-- Lowest Priority --> Highest

80

64

44

Port Pin

Alt 1

Alt 2

1

2

1

2

1

2

PTC4

—

IRQ

TPMCLK

3

—

RESET

—

4

PTF0

PTF1

PTF2

PTF3

PTF4

PTC6

PTF7

PTF5

PTF6

PTE0

PTE1

PTE2

TPM1CH2

TPM1CH3

TPM1CH4

TPM1CH5

TPM2CH0

RXCAN

TXCAN

—

5

—

6

—

6

—

7

—

8

BUSCLK_OUT

9

—

7

—

10

11

12

13

14

15

10

11

12

13

14

15

TPM2CH1

—

8

TXD1

9

RXD1

10

TPM1CH0

MCF51JM128 ColdFire Microcontroller, Rev. 4

12

Freescale Semiconductor

MCF51JM128 Family Configurations

Table 4. Pin Assignments by Package and Pin Sharing Priority (continued)

Pin Number <-- Lowest Priority --> Highest

80

64

44

Port Pin

Alt 1

Alt 2

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

16

—

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

—

34

35

36

37

38

39

40

11

—

12

13

14

15

16

17

18

19

20

21

22

—

23

24

25

26

27

28

—

PTE3

PTC7

PTH0

PTH1

PTH2

PTH3

PTH4

PTE4

PTE5

PTE6

PTE7

—

TPM1CH1

—

SDA2

—

SCL2

—

RGPIO8

RGPIO9

RGPIO10

MISO1

MOSI1

SPSCK1

SS1

—

VDD

—

VSS

—

USBDN

—

USBDP

—

VUSB33

USB_ALT_CLK

—

PTG0

PTG1

PTA0

PTA1

PTA2

PTA3

PTA4

PTA5

PTA6

PTA7

PTB0

PTB1

PTB2

PTB3

PTB4

PTB5

PTB6

KBIP0

KBIP1

RGPIO0

RGPIO1

RGPIO2

RGPIO3

RGPIO4

RGPIO5

RGPIO6

RGPIO7

MISO2

MOSI2

SPSCK2

SS2

USB_SESSVLD

USB_SESSEND

USB_VBUSVLD

USB_PULLUP(D+)

USB_DM_DOWN

USB_DP_DOWN

USB_ID

—

ADP0

ADP1

ADP2

ADP3

KBIP4

KBIP5

ADP6

ADP4

ADP5

—

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

13

MCF51JM128 Family Configurations

Table 4. Pin Assignments by Package and Pin Sharing Priority (continued)

Pin Number <-- Lowest Priority --> Highest

80

64

44

Port Pin

Alt 1

Alt 2

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

41

42

43

44

45

46

47

48

—

49

50

51

52

53

54

55

56

57

58

59

—

60

61

62

63

64

—

29

30

31

PTB7

PTD0

PTD1

—

ADP7

ADP8

ADP9

—

ACMP+

ACMP–

VDDA

VREFH

VREFL

VSSA

ACMPO

—

32

—

33

—

34

35

36

37

38

39

—

40

41

42

43

44

PTD2

PTJ0

PTJ1

PTJ2

PTJ3

PTJ4

PTD3

PTD4

PTD5

PTD6

PTD7

PTG2

PTG3

—

KBIP2

RGPIO11

RGPIO12

RGPIO13

RGPIO14

RGPIO15

KBIP3

ADP11

—

ADP10

—

KBIP6

KBIP7

BKGD

XTAL

EXTAL

—

MS

PTG4

PTG5

—

VSS

VDD

—

PTG6

PTG7

PTC0

PTC1

PTC2

PTC3

PTC5

—

SCL1

SDA1

IRO

—

TXD2

RXD2

—

MCF51JM128 ColdFire Microcontroller, Rev. 4

14

Freescale Semiconductor

Preliminary Electrical Characteristics

2

Preliminary Electrical Characteristics

This section contains electrical specification tables and reference timing diagrams for the MCF51JM128 microcontroller,

including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.

The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not

be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for

production silicon. Finalized specifications will be published after complete characterization and device qualifications have

been completed.

NOTE

The parameters specified in this data sheet supersede any values found in the module

specifications.

2.1

Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better

understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 5. Parameter Classifications

P

C

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a

statistically relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from

typical devices under typical conditions unless otherwise noted. All values shown in the

typical column are within this category.

T

D

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled C in the parameter tables where

appropriate.

2.2

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the

limits specified in Table 6 may affect device reliability or cause permanent damage to the device. For functional operating

conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised

that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this

high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for

instance, V or V ).

SS

DD

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

15

Preliminary Electrical Characteristics

Table 6. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply voltage

Input voltage

V

–0.3 to + 5.8

V

DD

V

– 0.3 to V_DD+ 0.3

In

Instantaneous maximum current Single pin limit

(applies to all port pins)¹, ², ³

I_D

I_DD

 25

mA

Maximum current into V

Storage temperature

120

–55 to +150

150

mA

C

DD

T

stg

T_J

Maximum junction temperature

C

1

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive (V_DD) and negative (V_SS) clamp

voltages, then use the larger of the two resistance values.

2

3

All functional non-supply pins are internally clamped to V_SSand V_DD

.

Power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_In> V_DD) is greater than

I_DD, the injection current may flow out of V_DDand could result in external power supply going

out of regulation. Ensure external V_DDload shunt current is greater than maximum injection

current. This is the greatest risk when the MCU is not consuming power. Examples: if no system

clock is present or if the clock rate is low, which would reduce overall power consumption.

2.3

Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power

dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than

being controlled by the MCU design. To take P into account in power calculations, determine the difference between actual

I/O

pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current

SS

DD

(heavy loads), the difference between pin voltage and V or V is small.

SS

DD

Table 7. Thermal Characteristics

Rating

Operating temperature range (packaged)

Thermal resistance ^1,2,3,4

Symbol

Value

Unit

T_A

–40 to +105

C

80-pin LQFP

64-pin LQFP

64-pin QFP

44-pin LQFP

1s

2s2p

52

40

1s

2s2p

65

47

_JA

C/W

1s

2s2p

54

40

1s

2s2p

69

48

1

2

Junction temperature is a function of die size, on-chip power dissipation, package thermal

resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation

of other components on the board, and board thermal resistance.

Junction to Ambient Natural Convection

MCF51JM128 ColdFire Microcontroller, Rev. 4

16

Freescale Semiconductor

Preliminary Electrical Characteristics

3

4

1s - Single Layer Board, one signal layer

2s2p - Four Layer Board, 2 signal and 2 power layers

The average chip-junction temperature (T ) in C can be obtained from:

J

T = T + (P   )

JA

Eqn. 1

J

A

D

where:

T = Ambient temperature, C = Package thermal resistance, junction-to-ambient, C/WP = P P

P

=

A

JA

D

int

I/O int

I

 V , Watts — chip internal powerP = Power dissipation on input and output pins — user determined

DD

DD I/O

For most applications, P  P and can be neglected. An approximate relationship between P and T (if P is neglected)

I/O

int

D

J

I/O

is:

P = K  (T + 273C)

Eqn. 2

D

J

Solving equations 1 and 2 for K gives:

2

K = P  (T + 273C) +   (P )

Eqn. 3

D

A

JA

D

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)

D

for a known T . Using this value of K, the values of P and T can be obtained by solving equations 1 and 2 iteratively for any

A

D

J

value of T .

A

2.4

Electrostatic Discharge (ESD) Protection Characteristics

Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling

precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices

can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits.

(http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.

A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification

requirements. Complete DC parametric and functional testing is performed per the applicable device specification at room

temperature followed by hot temperature, unless specified otherwise in the device specification.

Table 8. ESD and Latch-up Test Conditions

Model

Description

Symbol Value Unit

Series Resistance

R1

C

1500

100

3



Human Body

Storage Capacitance

pF

Number of Pulse per pin

Minimum input voltage limit

Maximum input voltage limit

–

–2.5

7.5

V

Latch-up

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

17

Preliminary Electrical Characteristics

Table 9. ESD and Latch-Up Protection Characteristics

Num

Rating

Symbol

Min

Max

Unit

1

2

3

Human Body Model (HBM)

Charge Device Model (CDM)

Latch-up Current at T_A= 105C

V_HBM

V_CDM

I_LAT

+/– 2000

+/– 500

+/– 100

—

V

mA

2.5

DC Characteristics

This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various

operating modes.

Table 10. DC Characteristics

Num C

Parameter

Symbol

Min

Typ¹

Max

Unit

1

Operating voltage²

2.7

—

5.5

V

Output high voltage — Low Drive (PTxDSn = 0)

5 V, I_Load= –4 mA

V_DD– 1.5

V_DD– 0.8

—

3 V, I_Load= –2 mA

5 V, I_Load= –2 mA

3 V, I_Load= –1 mA

2

P

V_OH

V

Output high voltage — High Drive (PTxDSn = 1)

5 V, I_Load= –15 mA

V

_DD– 1.5

—

3 V, I_Load= –8 mA

5 V, I_Load= –8 mA

3 V, I_Load= –4 mA

V_DD– 1.5

V_DD– 0.8

Output low voltage — Low Drive (PTxDSn = 0)

5 V, I_Load= 4mA

—

1.5

0.8

3 V, I_Load= 2 mA

5 V, I_Load= 2 mA

3 V, I_Load= 1 mA

3

P

V_OL

V

Output low voltage — High Drive (PTxDSn = 1)

5 V, I_Load= 15 mA

—

1.5

0.8

3 V, I_Load= 8 mA

5 V, I_Load= 8 mA

3 V, I_Load= 4 mA

4

5

6

P Output high current — Max total I_OHfor all ports

5V I_OHT

3V

—

100

60

mA

P Output low current — Max total I_OLfor all ports

P Input high voltage; all digital inputs

5V I_OLT

3V

—

100

60

V_IH

V

3.25

2.10

—

V_DD= 5V

V_DD= 3V

MCF51JM128 ColdFire Microcontroller, Rev. 4

18

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 10. DC Characteristics (continued)

Num C

Parameter

Symbol

Min

Typ¹

Max

Unit

7

P Input low voltage; all digital inputs

V_IL

—

V

1.75

1.05

V_DD= 5V

V_DD= 3V

8

9

P Input hysteresis; all digital inputs

V_hys

|I_In|

0.06 x V_DD

mV

A

k

P Input leakage current; input only pins³

—

20

0.1

45

1

10 P High Impedance (off-state) leakage current³

11 P Internal pullup resistors⁴

|I_OZ|

R_PU

R_PD

65

12 P Internal pulldown resistors⁵

45

13

Internal pullup resistor to USBDP (to V_USB33)

k

Idle R_PUPD

900

1425

1300

2400

1575

3090

Transmit

14 C Input Capacitance; all non-supply pins

15 D RAM retention voltage⁶

16 P POR rearm voltage

C_In

—

0.6

1.4

—

8

pF

V

V_RAM

V_POR

t_POR

1.0

2.0

—

0.9

10

V

17 D POR rearm time

s

V

Low-voltage detection threshold —

high range

V_LVD1

18

19

20

P

C

P

V_DDfalling

V_DDrising

3.9

4.0

4.1

4.2

Low-voltage detection threshold —

low range

V_LVD0

V_LVW3

V_LVW2

V_LVW1

V_LVW0

V_hys

V

V_DDfalling

V_DDrising

2.48

2.54

2.56

2.62

2.64

2.70

Low-voltage warning threshold —

high range 1

V_DDfalling

V_DDrising

4.5

4.6

4.7

4.8

Low-voltage warning threshold —

high range 0

V

V_DDfalling

4.2

4.3

4.4

4.5

21

22

V_DDrising

Low-voltage warning threshold

low range 1

V

V_DDfalling

V_DDrising

2.84

2.90

2.92

2.98

3.00

3.06

Low-voltage warning threshold —

low range 0

V

23

24

C

T

V_DDfalling

2.66

2.72

2.74

2.80

2.82

2.88

V_DDrising

Low-voltage inhibit reset/recover hysteresis

mV

5 V

3 V

—

100

60

—

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

19

Preliminary Electrical Characteristics

1

Typical values are based on characterization data at 25C unless otherwise stated.

2

3

4

5

6

Operating voltage with USB enabled can be found in Section 2.14, “USB Electricals.”

Measured with V_In= V_DDor V_SS

Measured with V_In= V_SS

Measured with V_In= V_DD

This is the voltage below which the contents of RAM are not guaranteed to be maintained.

.

Typical V_OLvs. I_OLAT V_DD= 5V

Typical V_OLvs. I_OLAT V_DD= 3V

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

Hot (105°C)

Room (25°C)

Cold (-40°C)

Hot (105°C)

Room (25°C)

Cold (-40°C)

0

1

2

3

4

5

6

7

8

9

10 11 12 13

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

I_OL(mA)

Figure 5. Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1)

Typical V_OLvs. I_OLAT V_DD= 5V

Typical V_OLvs. I_OLAT V_DD= 3V

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

Hot (105°C)

Room (25°C)

Cold (-40°C)

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

Room(25°C)

Cold (-40°C)

0

1

2

3

0

1

2

3

4

5

I_OL(mA)

Figure 6. Typical Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0)

MCF51JM128 ColdFire Microcontroller, Rev. 4

20

Freescale Semiconductor

Preliminary Electrical Characteristics

Typical V_DD- V_OHvs. I_OHAT V_DD= 5V

Typical V_DD- V_OHvs. I_OHAT V_DD=3V

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.8

0.6

0.4

0.2

0.0

Hot (105°C)

Room (25°C)

Cold (-40°C)

Hot (105°C)

Room (25°C)

Cold (-40°C)

0

-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15

0

-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13

I_OH(mA)

Figure 7. Typical High-side Drive (source) characteristics – High Drive (PTxDSn = 1)

Typical V_DD- V_OHvs. I_OHAT V_DD=3V

Typical V_DD- V_OHvs. I_OHAT V_DD= 5V

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Hot (105°C)

Room (25°C)

Cold (-40°C)

Hot (105°C)

Room (25°C)

Cold (-40°C)

0

-1

-2

-3

-4

-5

0

-1

-2

-3

I_OH(mA)

Figure 8. Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0)

2.6

Supply Current Characteristics

Table 11. Supply Current Characteristics

Num

C

Parameter

Symbol

V_DD(V)

Typical¹

4.0

Max²

Unit

1

C

Run supply current³measured at (CPU clock =

2 MHz, f_Bus= 1 MHz)

5

3

7

mA

4.0

2

3

P

C

Run supply current³measured at (CPU clock =

16 MHz, f_Bus= 8 MHz)

5

3

5

3

19

18.7

45

30

70

RI_DD

mA

Run supply current³measured at (CPU clock =

48 MHz, f_Bus= 24 MHz)

44

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

21

Preliminary Electrical Characteristics

Table 11. Supply Current Characteristics

Num

C

Parameter

Symbol

V_DD(V)

Typical¹

2.03

2

Max²

Unit

4

C

Wait mode supply current³measured at (CPU

clock = 2 MHz, f_Bus= 1 MHz)

5

3

mA

5

6

7

C

Wait mode supply current³measured at (CPU

clock = 16 MHz, f_Bus= 8 MHz)

5

3

5

3

7.73

7.7

12

30

WI_DD

mA

Wait mode supply current³measured at (CPU

clock = 48 MHz, f_Bus= 24 MHz)

22

21.9

Stop2 mode supply current

–40 C

25 C

105C

3

35

5

3

1.35

1.25

A

S2I_DD

S3I_DD

S4I_DD

3

35

–40 C

25 C

105 C

A

8

P

Stop3 mode supply current

–40 C

25 C

105 C

3

35

5

3

1.41

1.35

–40 C

25 C

105 C

3

35

A

9

C

Stop4 mode supply current

–40 C

25 C

105 C

5

3

106

96

200

–40 C

25 C

105 C

10

11

P

RTC adder to stop2 or stop3⁴, 25C

5

3

5

3

300

5

—

nA

A

S23I_DDRTC

S23I_DDOSC

Adder to stop3 for oscillator enabled⁵

(ERCLKEN =1 and EREFSTEN = 1)

5

1

2

3

4

5

Typicals are measured at 25C.

Values given here are preliminary estimates prior to completing characterization.

All modules’ clocks are switched on, code runs from flash, in FEI mode, and there are no DC loads on port pins.

Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode.

Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0)

MCF51JM128 ColdFire Microcontroller, Rev. 4

22

Freescale Semiconductor

Preliminary Electrical Characteristics

2.7

Analog Comparator (ACMP) Electricals

Table 12. Analog Comparator Electrical Specifications

Num

C

Rating

Symbol

V_DD

Min

Typical

Max

Unit

1

Supply voltage

2.7

—

5.5

V

I_DDAC

2

3

4

5

Supply current (active)

20

—

35

V_DD

40

A

V

Analog input voltage

V_AIN

V_AIO

V_H

V_SS– 0.3

Analog input offset voltage

Analog Comparator hysteresis

20

6.0

mV

3.0

--

20.0

I_ALKG

t_AINIT

6

7

Analog input leakage current

--

1.0

A

s

Analog Comparator initialization delay

—

Bandgap Voltage Reference

Factory trimmed at V_DD= 3.0 V, Temp = 25C

8

V_BG

1.19

1.20

1.21

V

2.8

ADC Characteristics

Table 13. 5 Volt 12-bit ADC Operating Conditions

Characteristic

Conditions

Symb

Min

Typ¹

Max

Unit

Comment

Supply voltage

Absolute

Delta to V_DD(V_DD-V_DDA

V_DDA

V_DDA

V_SSA

V_REFH

V_REFL

V_ADIN

C_ADIN

2.7

–100

2.7

—

0

5.5

+100

V_DDA

V_SSA

V_REFH

5.5

V

mV

V

2

)

2

Ground voltage Delta to V_SS(V_SS-V_SSA

Ref Voltage High

)

0

V_DDA

V_SSA

—

Ref Voltage Low

V_SSA

V_REFL

—

V

Input Voltage

V

Input

4.5

pF

Capacitance

Input Resistance

R_ADIN

R_AS

—

3

5

k

Analog Source

Resistance

12 bit mode

External to MCU

f_ADCK> 4MHz

—

2

5

f_ADCK< 4MHz

10 bit mode

_ADCK> 4MHz

f_ADCK< 4MHz

f

—

5

10

8 bit mode (all valid f_ADCK

)

—

10

8.0

4.0

ADC Conversion High Speed (ADLPC=0)

f_ADCK

0.4

MHz

Clock Freq.

Low Power (ADLPC=1)

1

2

Typical values assume V_DDA= 5.0V, Temp = 25C, f_ADCK=1.0MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

DC potential difference.

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

23

Preliminary Electrical Characteristics

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Z_ADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

Z_AS

leakage

due to

input

ADC SAR

ENGINE

R_AS

R_ADIN

protection

+

V

ADIN

–

C_AS

V

+

AS

–

R_ADIN

INPUT PIN

C_ADIN

Figure 9. ADC Input Impedance Equivalency Diagram

Table 14. 5 Volt 12-bit ADC Characteristics (V

= V

, V

= V

)

SSA

REFH

DDA

REFL

Max

—

Characteristic

Conditions

C

Symb

Min

Typ¹

Unit

Comment

Supply Current

ADLPC=1

ADLSMP=1

ADCO=1

T

I_DDAD

—

133

218

A

Supply Current

ADLPC=1

ADLSMP=0

ADCO=1

T

P

I_DDAD

—

1

A

Supply Current

ADLPC=0

ADLSMP=1

ADCO=1

327

Supply Current

ADLPC=0

ADLSMP=0

ADCO=1

0.582

mA

Supply Current Stop, Reset, Module Off

I_DDAD

—

2

0.011

3.3

2

1

5

A

ADC

High Speed (ADLPC=0)

Low Power (ADLPC=1)

T

f_ADACK

MHz

t_ADACK

=

Asynchronous

Clock Source

1/f_ADACK

1.25

3.3

MCF51JM128 ColdFire Microcontroller, Rev. 4

24

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 14. 5 Volt 12-bit ADC Characteristics (V

= V

, V

= V

) (continued)

Unit Comment

REFH

DDA

REFL

SSA

Characteristic

Conditions

C

Symb

Min

Typ¹

Max

Conversion Time Short Sample (ADLSMP=0)

T

t_ADC

—

20

40

—

ADCK See Table 9 for

cycles conversion time

variances

(Including

Long Sample (ADLSMP=1)

sample time)

Sample Time

Short Sample (ADLSMP=0)

Long Sample (ADLSMP=1)

T

t_ADS

—

3.5

23.5

3.0

1

—

ADCK

cycles

Total Unadjusted 12 bit mode

Error

T

P

T

P

T

P

T

D

E_TUE

—

LSB²

Includes

quantization

10 bit mode

2.5

1.0

—

8 bit mode

0.5

1.75

0.5

0.3

1.5

0.5

0.3

1.5

0.5

1

Differential

Non-Linearity

12 bit mode

10 bit mode³

8 bit mode³

12 bit mode

10 bit mode

8 bit mode

DNL

INL

E_ZS

E_FS

E_Q

1.0

0.5

—

Integral

Non-Linearity

1.0

0.5

—

Zero-Scale Error 12 bit mode

10 bit mode

V_ADIN= V_SSAD

1.5

0.5

—

8 bit mode

Full-Scale Error 12 bit mode

10 bit mode

V_ADIN= V_DDAD

0.5

1

8 bit mode

0.5

—

Quantization

Error

12 bit mode

10 bit mode

8 bit mode

12 bit mode

10 bit mode

8 bit mode

25^oC

-1 to 0

—

0.5

—

Input Leakage

Error

D

E_IL

1

Pad leakage⁴*

R_AS

0.2

0.1

1.396

2.5

1

Temp Sensor

Voltage

D

V_TEMP25

m

—

V

Temp Sensor

Slope

-40^oC - 25^oC

25^oC - 125^oC

—

3.266

3.638

—

mV/^oC

1

Typical values assume V_DDA= 5.0V, Temp = 25C, f_ADCK=1.0MHz unless otherwise stated. Typical values are for reference only

and are not tested in production.

1 LSB = (V_REFH- V_REFL)/2^N

2

3

4

Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes

Based on input pad leakage current. Refer to pad electricals.

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

25

Preliminary Electrical Characteristics

2.9

External Oscillator (XOSC) Characteristics

Table 15. Oscillator Electrical Specifications (Temperature Range = –40 to 105C Ambient)

Num

C

Rating

Symbol

Min

Typ¹

Max

Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

• Low range (RANGE = 0)

f_lo

32

1

—

38.4

5

16

8

kHz

MHz

• High range (RANGE = 1) FEE or FBE mode ²

• High range (RANGE = 1) PEE or PBE mode ³

• High range (RANGE = 1, HGO = 1) BLPE mode

• High range (RANGE = 1, HGO = 0) BLPE mode

f_hi-fll

1

f_hi-pll

f_hi-hgo

f_hi-lp

C₁

C₂

See crystal or resonator

manufacturer’s recommendation.

2

3

Load capacitors

Feedback resistor

• Low range (32 kHz to 38.4 kHz)

• High range (1 MHz to 16 MHz)

R_F

10

1

M

Series resistor

• Low range, low gain (RANGE = 0, HGO = 0)

• Low range, high gain (RANGE = 0, HGO = 1)

 8 MHz

4 MHz

 MHz

—

0

100

0

—

R_S

4

—

k

• High range, low gain (RANGE = 1, HGO = 0)

• High range, high gain (RANGE = 1, HGO = 1)

 8 MHz

4 MHz

 MHz

—

0

10

20

Crystal start-up time ⁴

t

CSTL-LP

—

200

400

5

—

• Low range, low gain (RANGE = 0, HGO = 0)

• Low range, high gain (RANGE = 0, HGO = 1)

• High range, low gain (RANGE = 1, HG0 = 0)⁵

• High range, high gain (RANGE = 1, HG0 = 1)⁵

t

5

6

T

CSTL-HGO

ms

t

CSTH-LP

15

t

CSTH-HGO

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

• FEE or FBE mode ²

0.03125

—

5

16

40

MHz

f_extal

• PEE or PBE mode ³

1

0

• BLPE mode

1

2

Data in Typical column was characterized at 5.0 V, 25C or is typical recommended value.

When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz

to 39.0625 kHz.

3

4

5

When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz

to 2 MHz.

This parameter is characterized and not tested on each device. Proper PC board-layout procedures must be followed to achieve

specifications.

4 MHz crystal

MCF51JM128 ColdFire Microcontroller, Rev. 4

26

Freescale Semiconductor

Preliminary Electrical Characteristics

2.10 MCG Specifications

Table 16. MCG Frequency Specifications (Temperature Range = –40 to 125C Ambient)

Num C

Rating

Symbol

Min

Typical¹

Max

Unit

Internal reference frequency - factory trimmed at V_DD

= 5 V and temperature = 25 C

1

P

f_{int_ft}

—

32.768

—

kHz

2

3

P Average internal reference frequency – untrimmed

f_{int_ut}

t_irefst

31.25

—

60

39.0625

100

20

kHz

T Internal reference startup time

s

P

Low range (DRS=00)

Mid range (DRS=01)

High range (DRS=10)

Low range (DRS=00)

Mid range (DRS=01)

High range (DRS=10)

16

—

DCO output frequency

4

5

P range - untrimmed ²

f_{dco_ut}

32

—

40

MHz

P

48

—

60

DCO output frequency²

P

P Reference =32768Hz

—

19.92

39.85

59.77

—

f_{dco_DMX32}

—

and DMX32 = 1

P

—

Resolution of trimmed DCO output frequency at fixed

voltage and temperature (using FTRIM)

6

7

8

9

D

f_{dco_res_t}

f_{dco_t}

—

0.1

0.2

0.4

2

%f_dco

Resolution of trimmed DCO output frequency at fixed

voltage and temperature (not using FTRIM)

Total deviation of trimmed DCO output frequency over

voltage and temperature

0.5

–1.0

Total deviation of trimmed DCO output frequency over

fixed voltage and temperature range of 0 – 70 C

10 D FLL acquisition time ³

11 D PLL acquisition time ⁴

f_{dco_t}

0.5

1

t_{fll_acquire}

t_{pll_acquire}

—

1

ms

Long term Jitter of DCO output clock (averaged over

2ms interval) ⁵

12

D

C_Jitter

—

0.02

0.2

%f_dco

13 D VCO operating frequency

f_vco

f_{pll_jitter_625ns}

D_lock

7.0

—

0.566⁵

—

55.0

—

MHz

%f_pll

%

14 D Jitter of PLL output clock measured over 625 ns⁶

15 D Lock entry frequency tolerance ⁷

16 D Lock exit frequency tolerance ⁸

1.49

4.47

2.98

5.97

D_unl

—

%

t_{fll_acquire+}

_1075(1/f_{int_t}

17 D Lock time — FLL

18 D Lock time — PLL

t_{fll_lock}

t_{pll_lock}

f_{loc_low}

—

s

)

t_{pll_acquire+}

_1075(1/f_{pll_r}

ef)

Loss of external clock minimum frequency – RANGE

19 D = 0

(3/5) x f_int

—

kHz

1

2

3

Data in Typical column was characterized at 5.0 V, 25C or is typical recommended value

The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or

changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the

reference, this specification assumes it is already running.

4

This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes

it is already running.

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

27

Preliminary Electrical Characteristics

5

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_BUS

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via V_DDand V_SSand variation in crystal oscillator frequency increase the C_Jitterpercentage for

a given interval.

.

6

625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN

bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge

and the sample point of a bit using 8 time quanta per bit.

7

8

Below D_lockminimum, the MCG is guaranteed to enter lock. Above D_lockmaximum, the MCG will not enter lock. But if the

MCG is already in lock, then the MCG may stay in lock.

Below D_unlminimum, the MCG will not exit lock if already in lock. Above D_unlmaximum, the MCG is guaranteed to exit lock.

2.11 AC Characteristics

This section describes ac timing characteristics for each peripheral system.

2.11.1 Control Timing

Table 17. Control Timing

Num

C

Parameter

Symbol

f_Bus

Min

dc

Typ¹

Max

24

Unit

MHz

s

1

2



Bus frequency (t_cyc= 1/f_Bus

)

Internal low-power oscillator period

External reset pulse width²

—

t_LPO

700

1300

t_extrst

100

—

ns

(t_cyc= 1/f_{Self_reset}

)

4

t_rstdrv

t_MSSU

t_MSH

66 x t_cyc

500

Reset low drive

—

ns

5

Active background debug mode latch setup time

Active background debug mode latch hold time

6

100

IRQ pulse width

Asynchronous path²

Synchronous path³

t_{ILIH, IHIL}

t

100

1.5 x t_cyc

—

ns

7

8

KBIPx pulse width

Asynchronous path²

Synchronous path³

t_{ILIH, IHIL}

t

100

1.5 x t_cyc

Port rise and fall time (load = 50 pF)⁴

Slew rate control disabled (PTxSE = 0) High drive

Slew rate control enabled (PTxSE = 1) High drive

Slew rate control disabled (PTxSE = 0) Low drive

Slew rate control enabled (PTxSE = 1) Low drive

11

35

40

75

t_Rise, t_Fall

9

—

ns

1

2

Typical values are based on characterization data at V_DD= 5.0V, 25C unless otherwise stated.

This is the shortest pulse guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override

reset requests from internal sources.

3

4

This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not

be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.

Timing is shown with respect to 20% V_DDand 80% V_DDlevels. Temperature range –40C to 105C.

MCF51JM128 ColdFire Microcontroller, Rev. 4

28

Freescale Semiconductor

Preliminary Electrical Characteristics

t_extrst

RESET PIN

Figure 10. Reset Timing

t_IHIL

IRQ/KBIPx

t_ILIH

Figure 11. IRQ/KBIPx Timing

2.11.2 Timer/PWM (TPM) Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the

optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 18. TPM Input Timing

NUM

C

—

D

Function

External clock frequency

External clock period

Symbol

f_TPMext

t_TPMext

t_clkh

Min

dc

Max

f_Bus/4

—

Unit

1

2

3

4

5

MHz

t_cyc

4

External clock high time

External clock low time

Input capture pulse width

1.5

—

D

t_clkl

—

D

t_ICPW

—

t_TPMext

t_clkh

TPMxCLK

t_clkl

Figure 12. Timer External Clock

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

29

Preliminary Electrical Characteristics

t_ICPW

TPMxCHn

t_ICPW

Figure 13. Timer Input Capture Pulse

2.11.3 MSCAN

Table 19. MSCAN Wake-up Pulse Characteristics

Num

C

D

Parameter

Symbol

t_WUP

Min

Typ¹

Max

2

Unit

s

1

2

MSCAN Wake-up dominant pulse filtered

MSCAN Wake-up dominant pulse pass

t_WUP

5

s

1

Typical values are based on characterization data at V_DD= 5.0V, 25C unless otherwise stated.

MCF51JM128 ColdFire Microcontroller, Rev. 4

30

Freescale Semiconductor

Preliminary Electrical Characteristics

2.12 SPI Characteristics

Table 20 and Figure 14 through Figure 17 describe the timing requirements for the SPI system.

Table 20. SPI Timing

No.

C

Function

Operating frequency

Symbol

Min

Max

Unit

—

D

Master

Slave

f_op

f_Bus/2048

0

f_Bus/2

f_Bus/4

Hz

SPSCK period

Master

Slave

1

2

3

4

5

6

D

t_SPSCK

t_Lead

t_Lag

2

4

2048

—

t_cyc

Enable lead time

Master

Slave

12

1

—

t_SPSCK

t_cyc

Enable lag time

Master

Slave

12

1

—

t_SPSCK

t_cyc

Clock (SPSCK) high or low time

Master

Slave

t_WSPSCK

t_cyc–30

t_cyc– 30

1024 t_cyc

—

ns

Data setup time (inputs)

Master

Slave

t_SU

15

—

ns

Data hold time (inputs)

Master

Slave

t_HI

0

25

—

ns

Slave access time

—

1

t_cyc

7

8

D

t_a

Slave MISO disable time

—

1

t_cyc

t_dis

Data valid (after SPSCK edge)

9

D

Master

Slave

t_v

—

25

ns

Data hold time (outputs)

Master

Slave

10

11

12

t_HO

0

—

ns

Rise time

Input

Output

t_RI

t_RO

—

t_cyc– 25

25

ns

Fall time

Input

Output

t_FI

t_FO

—

t_cyc– 25

25

ns

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

31

Preliminary Electrical Characteristics

SS¹

(OUTPUT)

1

2

11

12

3

SPSCK

(CPOL = 0)

(OUTPUT)

4

SPSCK

(CPOL = 1)

(OUTPUT)

5

6

MISO

(INPUT)

2

BIT 6 . . . 1

MSB IN

LSB IN

9

10

MOSI

(OUTPUT)

MSB OUT²

BIT 6 . . . 1

LSB OUT

NOTES:

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 14. SPI Master Timing (CPHA = 0)

SS⁽¹⁾

(OUTPUT)

1

11

2

3

12

SPSCK

(CPOL = 0)

(OUTPUT)

4

11

12

SPSCK

(CPOL = 1)

(OUTPUT)

5

6

MISO

(INPUT)

(2)

MSB IN

BIT 6 . . . 1

LSB IN

9

10

MOSI

(OUTPUT)

(2)

PORT DATA

MASTER LSB OUT

PORT DATA

MASTER MSB OUT

NOTES:

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 15. SPI Master Timing (CPHA = 1)

MCF51JM128 ColdFire Microcontroller, Rev. 4

32

Freescale Semiconductor

Preliminary Electrical Characteristics

SS

(INPUT)

11

12

3

1

12

11

SPSCK

(CPOL = 0)

(INPUT)

2

4

SPSCK

(CPOL = 1)

(INPUT)

8

7

10

9

10

MISO

(OUTPUT)

SEE

NOTE

BIT 6 . . . 1

SLAVE LSB OUT

MSB OUT

SLAVE

6

5

MOSI

(INPUT)

BIT 6 . . . 1

MSB IN

LSB IN

NOTE:

1. Not defined but normally MSB of character just received

Figure 16. SPI Slave Timing (CPHA = 0)

SS

(INPUT)

1

3

12

2

11

SPSCK

(CPOL = 0)

(INPUT)

4

11

12

SPSCK

(CPOL = 1)

(INPUT)

9

10

8

MISO

(OUTPUT)

SEE

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

SLAVE

MSB OUT

NOTE

5

6

7

MOSI

(INPUT)

MSB IN

NOTE:

1. Not defined but normally LSB of character just received

Figure 17. SPI Slave Timing (CPHA = 1)

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

33

Preliminary Electrical Characteristics

2.13 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the Flash memory.

Program and erase operations do not require any special power sources other than the normal V supply.

DD

Table 21. Flash Characteristics

Num

C

Characteristic

Symbol

V_prog/erase

V_Read

f_FCLK

Min

2.7

150

5

Typ¹

Max

5.5

Unit

1

2



4

Supply voltage for program/erase

Supply voltage for read operation

V

5.5

V

Internal FCLK frequency²

200

6.67

kHz

s

t_Fcyc

Internal FCLK period (1/FCLK)

Byte program time (random location)⁽²⁾

Byte program time (burst mode)⁽²⁾

Page erase time³

t_prog

t_Fcyc

5

9

4

6

t_Burst

t_Page

7

4000

Mass erase time⁽²⁾

8

t_Mass

20,000

Program/erase endurance⁴

9

C

10,000

—

100,000

—

cycles

years

T_Lto T_H= –40C to + 105C

T = 25C

Data retention⁵

t_{D_ret}

10

15

100

—

1

2

3

Typical values are based on characterization data at V_DD= 5.0 V, 25C unless otherwise stated.

The frequency of this clock is controlled by a software setting.

These values are hardware state machine controlled. User code does not need to count cycles. This information

supplied for calculating approximate time to program and erase.

4

5

Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on

how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical

Endurance for Nonvolatile Memory.

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and

de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines

typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.

2.14 USB Electricals

The USB electricals for the USBOTG module conform to the standards documented by the Universal Serial Bus Implementers

Forum. For the most up-to-date standards, visit http://www.usb.org.

If the Freescale USBOTG implementation requires additional or deviant electrical characteristics, this space would be used to

communicate that information.

MCF51JM128 ColdFire Microcontroller, Rev. 4

34

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 22. Internal USB 3.3V Voltage Regulator Characteristics

Symbol

Unit

Min

Typ

Max

V_regin

V

3.9

—

5.5

Regulator operating voltage

Vreg output

V_regout

V

3

3.3

3.6

V_usb33in

Vusb33 input with internal Vreg

disabled

I_VRQ

mA

—

0.5

—

VREG Quiescent Current

2.15 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board

design and layout, circuit topology choices, location and characteristics of external components as well as MCU software

operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such

as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC

performance.

2.15.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance

with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a

custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller

are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the

evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

35

Mechanical Outline Drawings

3

Mechanical Outline Drawings

3.1

80-pin LQFP

Figure 18. 80-pin LQFP Diagram - I

MCF51JM128 ColdFire Microcontroller, Rev. 4

36

Freescale Semiconductor

Mechanical Outline Drawings

Figure 19. 80-pin LQFP Diagram - II

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

37

Mechanical Outline Drawings

Figure 20. 80-pin LQFP Diagram - III

MCF51JM128 ColdFire Microcontroller, Rev. 4

38

Freescale Semiconductor

Mechanical Outline Drawings

3.2

64-pin LQFP

Figure 21. 64-pin LQFP Diagram - I

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

39

Mechanical Outline Drawings

Figure 22. 64-pin LQFP Diagram - II

MCF51JM128 ColdFire Microcontroller, Rev. 4

40

Freescale Semiconductor

Mechanical Outline Drawings

Figure 23. 64-pin LQFP Diagram - III

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

41

Mechanical Outline Drawings

3.3

64-pin QFP

Figure 24. 64-pin QFP Diagram - I

MCF51JM128 ColdFire Microcontroller, Rev. 4

42

Freescale Semiconductor

Mechanical Outline Drawings

Figure 25. 64-pin QFP Diagram - II

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

43

Mechanical Outline Drawings

Figure 26. 64-pin QFP Diagram - III

MCF51JM128 ColdFire Microcontroller, Rev. 4

44

Freescale Semiconductor

Mechanical Outline Drawings

3.4

44-pin LQFP

Figure 27. 44-pin LQFP Diagram - I

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

45

Mechanical Outline Drawings

Figure 28. 44-pin LQFP Diagram - II

MCF51JM128 ColdFire Microcontroller, Rev. 4

46

Freescale Semiconductor

Mechanical Outline Drawings

Figure 29. 44-pin LQFP Diagram - III

MCF51JM128 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor

47

Revision History

4

Revision History

This section lists major changes between versions of the MCF51JM128 Data Sheet document.

Table 23. Changes Between Revisions

Revision

Description

1

Updated features list

Updated the figures Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1), Typical

Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0), and Typical High-side Drive (source)

characteristics – High Drive (PTxDSn = 1)

Added the figure Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0)

Updated the table Supply Current Characteristics

Updated the table Oscillator Electrical Specifications (Temperature Range = –40 to 105×C Ambient)

Updated the table SPI Electrical Characteristic, DC Characteristics

2

3

Updated the table Orderable Part Number Summary, DC Characteristics, and Supply Current

Characteristics

Updated the table Orderable Part Number Summary, MCG Characteristics, SPI Characteristics, and

Supply Current Characteristics

Changed V_DDADto V_DDA, V_SSADto V_SSA

Updated the table Device comparison

4

Added “RAM retention voltage” parameter in “DC Characteristics” table, alongwith a table note.

Added “Temp sensor voltage” parameter in “5 Volt 12-bit ADC Characteristics (V_REFH= V_DDA, V_REFL

V_SSA)” table.

=

Added “ “Temp sensor slope” parameter in 5 Volt 12-bit ADC Characteristics (V_REFH= V_DDA, V_REFL

V_SSA) table. Also, corrected unit of “Temp sensor voltage” parameter in 5 Volt 12-bit ADC

Characteristics (V_REFH= V_DDA, V_REFL= V_SSA) table.

=

MCF51JM128 ColdFire Microcontroller, Rev. 4

48

Freescale Semiconductor

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

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Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

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Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

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Freescale Semiconductor products are not designed, intended, or authorized

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use, even if such claim alleges that Freescale Semiconductor was negligent

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Freescale™ and the Freescale logo are trademarks of Freescale

Semiconductor, Inc. The described product contains a PowerPC processor

core. The PowerPC name is a trademark of IBM Corp. and used under license.

All other product or service names are the property of their respective owners.

MCF51JM128

Rev. 4

05/2012


型号：	MCF51JM128VLH
厂家：	NXP
描述：	32-BIT, FLASH, 50.33MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64 时钟 CD 微控制器外围集成电路
文件：	总49页 (文件大小：1007K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCF51JM128VLH [NXP]

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