MCF51MM128VLL [NXP]
MCF51MM128VLL;型号: | MCF51MM128VLL |
厂家: | NXP |
描述: | MCF51MM128VLL |
文件: | 总58页 (文件大小:609K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51MM256
Rev. 4, 10/2010
An Energy-Efficient Solution from Freescale
MCF51MM256/128
The MCF51MM256 series devices are members of the
low-cost, low-power, high-performance ColdFire® V1 family of
32-bit microcontrollers (MCUs) designed for handheld
metering devices.
Not all features are available in all devices or packages; see
Table 2 for a comparison of features by device.
80-LQFP
12mm x 12mm
100-LQFP
14mm x 14mm
81-BGA
10mm x 10mm
104-BGA
10mm x 10mm
help save system cost, fully compliant with USB Specification 2.0. Allows
control, bulk, interrupt and isochronous transfers.
32-Bit ColdFire V1 Central Processor Unit (CPU)
• Up to 50.33-MHz ColdFire CPU above 2.4 V and 40 MHz CPU above
2.1 V and 20 MHz CPU above 1.8 V across temperature range of -40°C to
105°C.
• ColdFire Instruction Set Revision C (ISA_C).
• 32-bit multiply and accumulate (MAC) supports signed or unsigned integer
or signed fractional inputs.
•
•
•
•
•
•
•
•
SCIx — Two serial communications interfaces with optional 13-bit break;
option to connect Rx input to PRACMP output on SCI1 and SCI2; High
current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge.
SPI1 — Serial peripheral interface with 64-bit FIFO buffer; 16-bit or 8-bit
data transfers; full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first shifting.
SPI2 — Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first shifting.
On-Chip Memory
• 256 K Flash comprised of two independent 128 K flash arrays;
read/program/erase over full operating voltage and temperature; allows
interrupt processing while programming.
• 32 Kbytes System Random-access memory (RAM).
• Security circuitry to prevent unauthorized access to RAM and Flash
contents.
IIC — Up to 100 kbps with maximum bus loading; Multi-master operation;
Programmable slave address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 11-bit addressing.
CMT — Carrier Modulator timer for remote control communications.
Carrier generator, modulator and driver for dedicated infrared out (IRO).
Can be used as an output compare timer.
TPMx — Two 4-channel Timer/PWM Module; Selectable input capture,
output compare, or buffered edge- or center-aligned PWM on each
channel; external clock input/pulse accumulator.
Mini-FlexBus — Multi-function external bus interface with user
programmable chip selects and the option to multiplex address and data
lines.
PRACMP — Analog comparator with selectable interrupt; compare option
to programmable internal reference voltage; operation in stop3.
Power-Saving Modes
• Two ultra-low power stop modes. Peripheral clock enable register can
disable clocks to unused modules to reduce currents.
• Time of Day (TOD) — Ultra low-power 1/4 sec counter with up to 64s
timeout.
• Ultra-low power external oscillator that can be used in stop modes to
provide accurate clock source to the TOD. 6 usec typical wake up time
from stop3 mode.
Clock Source Options
• Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or
Measurement Engine
ceramic resonator dedicated for TOD operation.
•
ADC16 — 16-bit successive approximation ADC with up to 4 dedicated
• Oscillator (XOSC2) for high frequency crystal input for MCG reference to
be used for system clock and USB operations.
differential channels and 8 single-ended channels; range compare
function; 1.7 mV/C temperature sensor; internal bandgap reference
• Multipurpose Clock Generator (MCG) — PLL and FLL; precision trimming
of internal reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supports CPU frequencies from 4 kHz to
50 MHz.
channel; operation in stop3; fully functional from 3.6 V to 1.8 V,
Configurable hardware trigger for 8 Channel select and result registers.
PDB — Programmable delay block with 16-bit counter and modulus and
prescale to set reference clock to bus divided by 1 to bus divided by 2048;
8 trigger outputs for ADC module provides periodic coordination of ADC
sampling sequence with sequence completion interrupt; Back-to-Back
mode and Timed mode.
•
System Protection
• Watchdog computer operating properly (COP) reset with option to run from
dedicated 1 kHz internal clock source or bus clock.
• Low-voltage detection with reset or interrupt; selectable trip points;
separate low voltage warning with optional interrupt; selectable trip points.
• Illegal opcode and illegal address detection with reset.
• Flash block protection for each array to prevent accidental write/erasure.
• Hardware CRC to support fast cyclic redundancy checks.
•
•
•
DAC — 12-bit resolution; 16-word data buffers with configurable
watermark.
OPAMPx — 2 flexible operational amplifiers configurable for general
operations; Low offset and temperature drift.
TRIAMPx — 2 trans-impedance amplifiers dedicated for converting
current inputs into voltages.
Development Support
• Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM
Input/Output
connection supports same electrical interface used by the S08 family
• Up to 68 GPIOs and 1 output-only pin.
• Voltage Reference output (VREFO).
• Dedicated infrared output pinwith high current
sink capability.
• Up to 16 KBI pins with selectable polarity.
• Up to 16 pins of rapid general purpose I/O.
debug modules.
• Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1
data).
• On-chip trace buffer provides programmable start/stop recording
conditions.
Peripherals
•
USB — Dual-role USB On-The-Go (OTG) device, supports USB in either
device, host or OTG configuration. On-chip transceiver and 3.3V regulator
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Table of Contents
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
List of Topics
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 14.Timer Input Capture Pulse. . . . . . . . . . . . . . . . . . . . . 44
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 46
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 46
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 47
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 47
Figure 19.Typical VREF Output vs. Temperature. . . . . . . . . . . . 51
Figure 20.Typical VREF Output vs. VDD. . . . . . . . . . . . . . . . . . . 51
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pinouts and Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .16
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17
3.4 ESD Protection Characteristics. . . . . . . . . . . . . . . . . . .18
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .23
3.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.8 12-Bit DAC Electricals. . . . . . . . . . . . . . . . . . . . . . . . . .27
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.10 MCG and External Oscillator (XOSC) Characteristics .37
3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .39
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .42
2
3
List of Tables
Table 1. MCF51MM256/128 Features by MCU and Package . . 3
Table 2. MCF51MM256/128 Functional Units. . . . . . . . . . . . . . . 5
Table 3. Package Pin Assignments. . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16
Table 6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 18
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10.Supply Current Characteristics . . . . . . . . . . . . . . . . . . 23
Table 11.Typical Stop Mode Adders. . . . . . . . . . . . . . . . . . . . . . 25
Table 12.PRACMP Electrical Specifications . . . . . . . . . . . . . . . 27
Table 13.DAC 12LV Operating Requirements . . . . . . . . . . . . . . 27
Table 14.DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . . . 27
Table 15.16-Bit ADC Operating Conditions . . . . . . . . . . . . . . . . 29
Table 16.16-Bit SAR ADC Characteristics full operating range
(VREFH = VDDA, > 1.8, VREFL = VSSA 8 MHz, –40 to 85
3.12.2 TPM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .50
3.17 TRIAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .52
3.18 OPAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .53
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .56
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17.16-bit SAR ADC Characteristics full operating range
(VREFH = VDDA, 2.7 V, VREFL = VSSA, fADACK 4 MHz,
4
5
ADHSC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18.MCG (Temperature Range = –40 to 105°C Ambient) . 37
Table 19.XOSC (Temperature Range = –40 to 105°C Ambient) 38
Table 20.Mini-FlexBus AC Timing Specifications. . . . . . . . . . . . 40
Table 21.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24.Flash Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25.Internal USB 3.3 V Voltage Regulator Characteristics 49
Table 26.VREF Electrical Specifications . . . . . . . . . . . . . . . . . 50
Table 27.VREF Limited Range Operating Behaviors . . . . . . . . . 50
Table 28.TRIAMP Characteristics 1.8–3.6 V, –40°C~105°C . . . 52
Table 29.OPAMP Characteristics 1.8–3.6 V. . . . . . . . . . . . . . . . 53
Table 30.Orderable Part Number Summary. . . . . . . . . . . . . . . . 55
Table 31.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 32.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
List of Figures
Figure 1.MCF51MM256/128 Block Diagram. . . . . . . . . . . . . . . . 4
Figure 2.104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3.100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4.81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5.80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6.Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . 26
Figure 7.Offset at Half Scale vs Temperature . . . . . . . . . . . . . . 29
Figure 8.ADC Input Impedance Equivalency Diagram . . . . . . . 31
Figure 9.Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . 40
Figure 10.Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 41
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Features
1
Features
The following table provides a cross-comparison of the features of the MCF51MM256/128 according to
package.
Table 1. MCF51MM256/128 Features by MCU and Package
Feature
MCF51MM256
MCF51MM128
FLASH Size (bytes)
RAM Size (bytes)
Pin Quantity
262144
32K
131072
32K
104
yes
yes
yes
yes
yes
16
100
yes
yes
yes
yes
yes
16
81
80
yes
yes
yes
yes
yes
16
81
yes
yes
yes
yes
yes
16
80
yes
yes
yes
yes
yes
16
Programmable Analog Comparator (PRACMP)
Debug Module (DBG)
yes
yes
yes
yes
yes
16
Multipurpose Clock Generator (MCG)
Inter-Integrated Communication (IIC)
Interrupt Request Pin (IRQ)
Keyboard Interrupt (KBI)
Digital General Purpose I/O1
Dedicated Analog Input Pins
Power and Ground Pins
Time Of Day (TOD)
69
65
48
47
48
47
14
14
14
14
14
14
8
8
8
8
8
8
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
Serial Communications (SCI1)
Serial Communications (SCI2)
Serial Peripheral Interface (SPI1(FIFO))
Serial Peripheral Interface(SPI2)
Carrier Modulator Timer Pin (IRO)
TPM Input Clock Pin (TPMCLK)
TPM1 Channels
TPM2 Channels
4
4
4
4
4
4
XOSC1
yes
yes
yes
yes
16
yes
yes
yes
yes
16
yes
yes
yes
DATA2
9
yes
yes
yes
DATA2
9
yes
yes
yes
DATA2
9
yes
yes
yes
DATA2
9
XOSC2
USB On-the-Go
Mini-FlexBus
Rapid GPIO
MEASUREMENT ENGINE
Programmable Delay Block (PDB)
yes
4
yes
4
yes
4
yes
4
yes
4
yes
4
16-Bit SAR ADC Differential Channels3
16-Bit SAR ADC Single-Ended Channels
DAC Ouput Pin (DACO)
8
8
8
8
8
8
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Voltage Reference Output Pin (VREFO)
General Purpose Operational Amplifier (OPAMP)
Trans-Impedance Amplifier (TRIAMP)
1
2
3
Port I/O count does not include BLMS, BKGD and IRQ. BLMS and BKGD are Output only, IRQ is input only.
The 80/81 pin packages contain the Mini-FlexBus data pins to support an 8-bit data bus interface to external peripherals.
Each differential channel is comprised of 2 pin inputs.
Freescale Semiconductor
3
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Features
Figure 1. MCF51MM256/128 Block Diagram
4
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Features
The following table describes the functional units of the MCF51MM256/128.
Table 2. MCF51MM256/128 Functional Units
Unit
Function
DAC (digital to analog converter) — Used to output voltage levels.
16-BIT SAR ADC (analog-to-digital converter) — Measures analog
voltages at up to 16 bits of resolution. The ADC has up to four differential
and 8 single-ended inputs.
OPAMP — General purpose op amp used for signal filtering or
amplification.
Measurement Engine
TRIAMP —- Transimpedance amplifier optimized for converting small
currents into voltages.
Measurement Engine PDB — The measurement engine PDB is used to
precisely trigger the DAC and the ADC modules to complete sensor
biasing and measuring.
Mini-FlexBus
Provides expansion capability for off-chip memory and peripherals.
Supports the USB On-the-Go dual-role controller.
USB On-the-Go
CMT (Carrier Modulator Timer)
Infrared output used for the Remote Controller operation.
Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources.
MCG (Multipurpose Clock Generator)
BDM (Background Debug Module)
CF1 CORE (V1 ColdFire Core)
Provides single pin debugging interface (part of the V1 ColdFire core).
Executes programs and interrupt handlers.
Analog comparators for comparing external analog signals against
each other, or a variety of reference levels.
PRACMP
COP (Computer Operating Properly)
IRQ (Interrupt Request)
Software Watchdog.
Single-pin high-priority interrupt (part of the V1 ColdFire core).
High-speed CRC calculation.
CRC (Cyclic Redundancy Check)
Provides debugging and emulation capabilities (part of the V1 ColdFire.
core)
DBG (Debug)
FLASH (Flash Memory)
IIC (Inter-integrated Circuits)
INTC (Interrupt Controller)
KBI1 & KBI2
Provides storage for program code, constants, and variables.
Supports standard IIC communications protocol and SMBus.
Controls and prioritizes all device interrupts.
Keyboard Interfaces 1 and 2.
Provides an interrupt to theColdFire V1 CORE in the event that the
supply voltage drops below a critical value. The LVD can also be
programmed to reset the device upon a low voltage event.
LVD (Low-voltage Detect)
VREF (Voltage Reference)
The Voltage Reference output is available for both on- and off-chip use.
Provides stack and variable storage.
RAM (Random-Access Memory)
RGPIO (Rapid General-purpose
Input/output)
Allows for I/O port access at CPU clock speeds. RGPIO is used to
implement GPIO functionality.
Freescale Semiconductor
5
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Features
Table 2. MCF51MM256/128 Functional Units (continued)
Function
Unit
SCI1, SCI2 (Serial Communications
Interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols.
SIM (system integration unit)
SPI1 (FIFO), SPI2 (Serial Peripheral
Interfaces)
SPI1 and SPI2 provide standard master/slave capability. SPI contains a
FIFO buffer in order to increase the throughput for this peripheral.
Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation.
TPM1, TPM2 (Timer/PWM Module)
VREG (Voltage Regulator)
Controls power management across the device.
These devices incorporate redundant crystal oscillators. One is
XOSC1 and XOSC2 (Crystal Oscillators) intended primarily for use by the TOD, and the other by the CPU and
other peripherals.
6
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
2
Pinouts and Pin Assignments
2.1
104-Pin MAPBGA
The following figure shows the 104-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
10
11
PTF6
PTF7
USB_DP USB_DM VUSB33
PTF4
PTF3
FB_AD12
PTJ7
PTJ5
PTJ4
A
B
C
D
E
A
B
C
D
E
F
PTG0
IRO
PTA0
PTG4
PTA4
PTG3
PTA6
VBUS
PTG2
VDD1
PTF5
PTG6
PTJ6
PTG5
VDD2
PTH0
PTG7
PTE5
PTH1
VDD3
PTF0
PTE4
PTA1
PTA2
PTJ2
PTD5
PTD4
PTC2
PTC4
PTF1
PTE6
PTE3
PTJ3
PTJ0
PTD7
PTD3
PTC0
PTC5
PTF2
PTE7
PTE2
PTE1
PTJ1
PTE0
PTD2
PTC1
PTC6
PTA5
PTB1
PTB0
INP2-
OUT2
PTA3
VSSA
PTA7
VREFL
TRIOUT1
VINP1
DADP0
VINP2
INP1-
OUT1
VINN1
DADM0
VINN2
PTG1
PTC7
F
G
G
H
J
H
VSS1
PTH6
PTH5
VSS2
PTH3
PTB7
VSS3
PTD6
PTD1
PTH7
DADP1
PTH4
PTB6
PTH2
PTC3
J
K
L
K
L
TRIOUT2
DACO
DADM1
VREFO
VREFH
VDDA
PTB3
PTB2
PTD0
PTB5
PTB4
1
2
3
4
5
6
7
8
9
10
11
Figure 2. 104-Pin MAPBGA
Freescale Semiconductor
7
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
2.2
100-Pin LQFP
The following figure shows the 100-pin LQFP pinout configuration.
PTE4/CMPP3/TPMCLK/IRQ
PTA0/FB_D2/SS1
IRO
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
2
3
PTG5/FB_RW
4
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
5
6
7
PTH1/FB_D0
PTJ1/FB_AD3
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
8
PTJ0/FB_AD2
PTE0/KBI2P3/FB_ALE/FB_CS1
9
PTD7/USB_PULLUP(D+)/RX1
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTD6/USB_ALTCLK/TX1
PTA5
PTA6
PTA7/INP2+
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
100 LQFP
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTB0
PTB1/BLMS
VSSA
PTD1/CMPP2/RESET
PTD0/BKGD/MS
VREFL
INP1-
OUT1
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
TRIOUT1/DADP2-
VINP1
VINN1/DADM2
INP2-
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE/FB_CS0
OUT2
Figure 3. 100-Pin LQFP
8
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
2.3
81-Pin MAPBGA
The following figure shows the 81-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
IRO
PTG0
PTF6
USB_DP
VBUS
VUSB33
PTF4
PTF3
PTE4
A
B
C
D
E
F
A
B
C
D
E
F
PTF7
PTA4
PTA0
PTA5
PTG1
PTA6
USB_DM
PTA1
PTF5
PTF2
PTE7
PTE6
PTA3
VDD1
VSS1
PTB6
PTC4
PTF1
PTE5
PTD5
PTD2
PTB7
PTC0
PTD0
PTF0
PTE2
PTD7
PTD3
PTC7
PTC1
PTC5
PTE3
PTE1
PTE0
PTD6
PTD4
PTC2
PTC6
INP1-
PTA7
PTB0
PTB1
PTA2
OUT1
VINP1
DADP0
DADM0
VINN1
TRIOUT1
DACO
DADM1
OUT2
VDD2
VSS2
VDD3
VSS3
VREFO
PTC3
INP2-
TRIOUT2
DADP1
VINN2
VINP2
G
H
J
G
H
J
VSSA
VREFL
VREFH
VDDA
PTB2
PTB3
PTD1
PTB4
PTB5
1
2
3
4
5
6
7
8
9
Figure 4. 81-Pin MAPBGA
Freescale Semiconductor
9
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
2.4
80-Pin LQFP
The following figure shows the 80-pin LQFP pinout configuration.
PTA0/FB_D2/SS1
IRO
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
2
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
3
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
4
5
6
PTA5
PTA6
PTA7/INP2+
7
8
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
9
PTB0
PTB1/BLMS
VSSA
10
11
12
13
14
15
16
17
18
19
20
80-Pin LQFP
VREFL
PTD0/BKGD/MS
INP1-
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
OUT1
TRIOUT1/DADP2-
VINP1
VINN1DADM2
INP2-
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
OUT2
Figure 5. 80-Pin LQFP
10
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
2.5
Pin Assignments
Table 3. Package Pin Assignments
Package
Default
Function
Alternate
Alternate Alternate
Composite Pin Name
1
2
3
B2
C1
C6
C5
C7
B7
C8
D9
E9
H3
D2
D1
C3
E2
E3
D3
E1
F1
F2
1
2
B2
A1
—
1
PTA0
IRO
FB_D2
—
SS1
—
—
—
PTA0/FB_D2/SS1
IRO
2
3
—
—
—
—
—
3
PTG5
PTG6
PTG7
PTH0
PTH1
PTA1
FB_RW
FB_AD19
FB_AD18
FB_OE
FB_D0
KBI1P0
KBI1P1
KBI1P2
INP1+
—
—
—
PTG5/FB_RW
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
PTH1/FB_D0
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
PTA5
4
—
—
—
5
—
—
—
6
—
—
—
7
—
—
—
8
C4
D5
D6
C1
C2
C3
D2
D3
D4
J1
TX1
RX1
FB_D6
—
FB_D1
ADP4
ADP5
—
9
4
PTA2
10
11
12
13
14
15
16
17
18
19
5
PTA3
6
PTA4
7
PTA5
—
—
8
PTA6
—
—
—
PTA6
9
PTA7
INP2+
—
—
—
PTA7/INP2+
PTB0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PTB0
PTB1
VSSA
VREFL
INP1-
OUT1
DADP2
VINP1
DADM2
INP2-
OUT2
DACO
DADP3
VINP2
DADM3
—
—
BLMS
—
—
—
PTB1/BLMS
VSSA
—
—
J2
—
—
—
VREFL
D1
E1
F2
F1
E2
F3
E3
G2
G3
H4
G4
—
—
—
INP1-
G2 20
G1 21
—
—
—
OUT1
TRIOUT1
—
—
—
DADP2/TRIOUT1
VINP1
H1
H2
F3
22
23
24
—
—
VINN1
—
—
—
DADM2/VINN1
INP2-
—
—
G3 25
—
—
—
OUT2
L2
L1
K1
K2
26
27
28
29
—
—
—
DACO
TRIOUT2
—
—
—
DADP3/TRIOUT2
VINP2
—
—
VINN2
—
—
DADM3/VINN2
Freescale Semiconductor
11
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
Package
Table 3. Package Pin Assignments (continued)
Default
Function
Alternate
1
Alternate Alternate
Composite Pin Name
2
3
J1
J2
L4
K3
L3
L5
L6
H6
L8
L7
D6
30
31
32
33
34
35
36
37
38
39
40
G1
H1
G5
H3
H2
J3
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
—
—
—
—
—
—
40
41
42
43
44
45
46
47
48
49
DADP0
DADM0
VREFO
DADP1
DADM1
VREFH
VDDA
VSS2
PTB2
PTB3
VDD2
PTB4
PTB5
PTB6
PTB7
PTH2
PTH3
PTH4
PTH5
PTH6
PTH7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTD0
PTD1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DADP0
DADM0
—
VREFO
—
DADP1
—
DADM1
—
VREFH
J4
—
VDDA
F4
J5
—
VSS2
EXTAL1
XTAL1
—
PTB2/EXTAL1
J6
PTB3/XTAL1
E4
J8
VDD2
L11 41
L10 42
EXTAL2
XTAL2
KBI1P3
KBI1P4
RGPIOP2
RGPIOP3
RGPIOP4
RGPIOP5
RGPIOP6
RGPIOP7
MOSI2
MISO2
KBI1P5
KBI1P6
KBI1P7
KBI2P0
KBI2P1
KBI2P2
BKGD
CMPP2
PTB4/EXTAL2
J9
PTB5/XTAL2
K5
K6
J7
J6
J5
K4
J4
J3
43
44
45
46
47
48
49
50
G6
F7
—
RGPIOP0 FB_AD17
RGPIOP1 FB_AD0
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
PTC0/MOSI2/FB_OE/FB_CS0
PTC1/MISO2/FB_D0/FB_AD1
PTC2/KBI1P5/SPSCK2/ADP6
PTC3/KBI1P6/SS2/ADP7
PTC4/KBI1P7/CMPP0/ADP8
PTC5/KBI2P0/CMPP1/ADP9
PTC6/KBI2P1/PRACMPO/ADP10
PTC7/KBI2P2/CLKOUT/ADP11
PTD0/BKGD/MS
FB_D7
FB_D6
FB_D5
FB_D4
FB_D3
FB_D2
FB_OE
FB_D0
SPSCK2
SS2
—
—
—
—
—
—
—
—
—
—
—
J10 51
J11 52
G7
G8
G9
H5
H6
H8
H9
F8
H7
J7
FB_CS0
FB_AD1
ADP6
ADP7
ADP8
ADP9
J9
K7
K9
53
54
55
CMPP0
CMPP1
K10 56
K11 57
PRACMPO ADP10
F8
L9
K8
58
59
60
CLKOUT
MS
ADP11
—
RESET
—
PTD1/CMPP2/RESET
12
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
Table 3. Package Pin Assignments (continued)
Package
Default
Function
Alternate
1
Alternate Alternate
Composite Pin Name
2
3
H11 61
H10 62
E7
E8
50
51
PTD2
PTD3
USB_ALTCLK RGPIOP8 TPM1CH0
USB_PULLUP
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
RGPIOP9 TPM1CH1 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
(D+)
H9
G9 64
J8 65
63
F9
D7
E9
52
53
54
PTD4
PTD5
PTD6
SDA
RGPIOP10 TPM1CH2
RGPIOP11 TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD5/SCL/RGPIOP11/TPM1CH3
PTD6/USB_ALTCLK/TX1
SCL
USB_ALTCLK
TX1
RX1
—
—
USB_PULLUP
(D+)
G10 66
D8
55
PTD7
PTD7/USB_PULLUP(D+) /RX1
G11 67
F10 68
F11 69
D9
—
56
—
—
—
—
57
58
59
60
61
62
PTE0
PTJ0
PTJ1
PTJ2
PTJ3
PTE1
PTE2
PTE3
PTE4
VSS3
VDD3
KBI2P3
FB_AD2
FB_AD3
FB_AD4
RGPIOP12
KBI2P4
KBI2P5
KBI2P6
CMPP3
—
FB_ALE
—
FB_CS1
PTE0/KBI2P3/FB_ALE/FB_CS1
PTJ0/FB_AD2
—
—
—
—
—
—
PTJ1/FB_AD3
F9
70
—
—
PTJ2/FB_AD4
E10 71
E11 72
D11 73
D10 74
—
FB_AD5
PTJ3/RGPIOP12/FB_AD5
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE3/KBI2P6/FB_AD8
PTE4/CMPP3/TPMCLK/IRQ
VSS3
C9
C8
B9
A9
F5
E5
RGPIOP13 FB_AD6
RGPIOP14 FB_AD7
FB_AD8
TPMCLK
—
—
IRQ
—
C9
H8
D8
75
76
77
—
—
—
VDD3
USB_
SESSVLD
B8
78
C7
C6
63
64
PTE5
PTE6
FB_D7
TX2
RX2
PTE5/FB_D7/USB_SESSVLD/TX2
PTE6/FB_RW/USB_SESSEND/RX2
USB_
SESSEND
C10 79
C11 80
FB_RW
USB_
VBUSVLD
B6
B8
B7
65
66
67
PTE7
PTF0
PTF1
TPM2CH3
TPM2CH2
—
—
PTE7/USB_VBUSVLD/TPM2CH3
PTF0/USB_ID/TPM2CH2
B9
81
USB_ID
RX2
USB_DP_D
OWN
B10 82
B11 83
TPM2CH1
PTF1/RX2/USB_DP_DOWN/TPM2CH1
USB_DM_
DOWN
C5
68
PTF2
TX2
TPM2CH0
PTF2/TX2/USB_DM_DOWN/TPM2CH0
A11 84
A10 85
—
—
—
—
—
—
—
—
PTJ4
PTJ5
PTJ6
PTJ7
RGPIOP15
FB_AD15
FB_AD14
FB_AD13
FB_AD16
—
—
—
—
PTJ4/RGPIOP15/FB_AD16
PTJ5/FB_AD15
—
—
—
B6
A9
86
87
PTJ6/FB_AD14
PTJ7/FB_AD13
Freescale Semiconductor
13
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Pinouts and Pin Assignments
Package
Table 3. Package Pin Assignments (continued)
Default
Function
Alternate
1
Alternate Alternate
Composite Pin Name
2
3
A8
A7
A6
B5
A5
A4
A3
B4
H4
D4
A1
A2
88
89
90
91
92
93
94
95
96
97
98
99
—
A8
A7
B5
A6
B4
A4
A5
F6
E6
A3
B1
—
69
70
71
72
FB_AD12
PTF3
—
SCL
SDA
KBI2P7
—
—
FB_D5
FB_D4
FB_D3
—
—
FB_AD12
PTF3/SCL/FB_D5/FB_AD11
PTF4/SDA/FB_D4/FB_AD10
PTF5/KBI2P7/FB_D3/FB_AD9
VUSB33
FB_AD11
PTF4
FB_AD10
PTF5
FB_AD9
VUSB33
—
—
—
—
—
—
—
—
—
73 USB_DM
—
—
USB_DM
74
75
76
77
78
79
80
USB_DP
VBUS
VSS1
VDD1
PTF6
—
—
USB_DP
—
—
VBUS
—
—
VSS1
—
—
VDD1
MOSI1
MISO1
SPSCK1
—
PTF6/MOSI1
PTF7
—
PTF7/MISO1
B1 100 A2
PTG0
—
PTG0/SPSCK1
USB_
SESSEND
F4
C4
—
—
A1
—
—
—
PTG1
PTG2
—
—
—
—
PTG1/USB_SESSEND
PTG2/USB_DM_DOWN
USB_DM_
DOWN
USB_DP_
DOWN
B3
C2
—
—
—
—
—
—
PTG3
PTG4
—
—
—
—
PTG3/USB_DP_DOWN
PTG4/USB_SESSVLD
USB_SESSVLD
14
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3
Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the
MCF51MM256/128 microcontroller, including detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however, be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
3.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 4. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Freescale Semiconductor
15
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
Table 5. Absolute Maximum Ratings
#
Rating
Symbol
Value
Unit
1
2
3
Supply voltage
VDD
IDD
VIn
–0.3 to +3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
4
5
ID
25
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
C
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of
VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current
greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power.
Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either V or V ).
SS
DD
16
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
P
into account in power calculations, determine the difference between actual pin voltage and V or
I/O
SS
V
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
DD
loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 6. Thermal Characteristics
#
Symbol
Rating
Value
Unit
1
TA
Operating temperature range (packaged):
MCF51MM256
C
–40 to 105
–40 to 105
135
MCF51MM128
2
3
TJMAX
Maximum junction temperature
Thermal resistance1,2,3,4 Single-layer board — 1s
104-pin MBGA
C
JA
C/W
67
53
67
53
100-pin LQFP
81-pin MBGA
80-pin LQFP
4
JA
Thermal resistance1, 2, 3, 4 Four-layer board — 2s2p
C/W
104-pin MBGA
39
41
39
39
100-pin LQFP
81-pin MBGA
80-pin LQFP
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Junction to Ambient Natural Convection
2
3
4
1s — Single layer board, one signal layer
2s2p — Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (T ) in C can be obtained from:
J
T = T + (P )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, C
A
= Package thermal resistance, junction-to-ambient, C/W
JA
P = P P
D
int
I/O
P
P
= I V , Watts — chip internal power
DD DD
= Power dissipation on input and output pins — user determined
int
I/O
Freescale Semiconductor
17
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
For most applications, P P and can be neglected. An approximate relationship between P and T
I/O
int
D
J
(if P is neglected) is:
I/O
P = K (T + 273C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
2
K = P (T + 273C) + (P )
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .
A
3.4
ESD Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 7. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Series Resistance
R1
C
1500
100
3
pF
—
Human Body
Storage Capacitance
Number of Pulse per pin
Series Resistance
—
R1
C
0
Machine
Latch-up
Storage Capacitance
200
3
pF
—
V
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
—
—
—
–2.5
7.5
V
Table 8. ESD and Latch-Up Protection Characteristics
#
Rating
Symbol
Min
Max
Unit
C
1
2
Human Body Model (HBM)
Machine Model (MM)
VHBM
VMM
2000
200
—
—
V
V
T
T
18
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 8. ESD and Latch-Up Protection Characteristics (continued)
3
4
Charge Device Model (CDM)
VCDM
ILAT
500
00
—
—
V
T
T
Latch-up Current at TA = 125C
mA
Freescale Semiconductor
19
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.5
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table 9. DC Characteristics
Num Symbol
Characteristic
Condition
Min
Typ1
Max
Unit
C
Operating
Voltage
1
2
—
—
1.82
—
3.6
V
—
Output high
voltage
VOH
All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = –600 A
VDD – 0.5
VDD – 0.5
—
—
V
C
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = –10 mA
—
—
—
—
—
—
V
V
V
P
T
VDD 2.3 V,
ILoad = –6 mA
VDD – 0.5
VDD 1.8V,
ILoad = –3 mA
VDD – 0.5
C
Output high
current
3
4
IOHT
Max total IOH for all ports
—
—
—
—
—
100
0.5
mA
V
D
C
Output low
voltage
VOL
All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = 600 A
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = 10 mA
—
—
—
—
—
—
—
—
0.5
0.5
0.5
100
V
V
P
T
VDD 2.3 V,
ILoad = 6 mA
VDD 1.8 V,
ILoad = 3 mA
V
C
D
Output low
current
Max total IOL
—
5
6
IOLT
VIH
mA
for all ports
Input high voltage all digital inputs
VDD 2.7 V
VDD 1.8 V
0.70 x VDD
0.85 x VDD
—
—
—
—
V
V
P
C
20
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 9. DC Characteristics (continued)
Num Symbol
Characteristic
Condition
Min
Typ1
Max
Unit
C
7
VIL
Input low voltage all digital inputs
0.35 x
VDD
VDD 2.7 V
—
—
V
P
0.30 x
VDD
VDD 1.8 V
—
—
—
V
C
C
8
9
Vhys Input hysteresis
all digital inputs
all input only
—
0.06 x VDD
—
mV
Input leakage
|IIn|
pins VIn = VDD or VSS
(Per pin)
—
—
0.5
A
P
current
all digital
input/output VIn = VDD or VSS
(per pin)
Hi-Z (off-state)
|IOZ|
10
11
12
13
—
0.003
—
0.5
A
k
k
P
P
P
leakage current3
all digital inputs,
when enabled
RPU Pull-up resistors
—
—
17.5
17.5
52.5
52.5
Internal
RPD pull-down
resistors4
—
DC injection
IIC
Single pin limit
current 5, 6, 7
VSS > VIN > VDD
–0.2
—
0.2
mA
D
Total MCU limit, includes sum of all stressed pins
VSS > VIN > VDD
–5
—
—
—
5
8
mA
pF
V
D
C
C
C
D
14
15
16
17
CIn
Input Capacitance, all pins
—
—
—
—
VRAM RAM retention voltage
VPOR POR re-arm voltage8
tPOR POR re-arm time
Low-voltage
—
0.6
1.4
—
1.0
1.79
—
0.9
10
V
s
detection
threshold —
high range
9
18
VLVDH
VDD falling
VDD rising
VDD falling
—
—
2.11
2.16
2.16
2.21
2.22
2.27
V
V
P
P
Low-voltage
detection
19
VLVDL
threshold —
low range9
—
—
1.80
1.86
1.82
1.90
1.91
1.99
V
V
P
P
VDD rising
Freescale Semiconductor
21
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Num Symbol
Table 9. DC Characteristics (continued)
Characteristic
Condition
Min
Typ1
Max
Unit
C
Low-voltage
warning
20
VLVWH
VDD falling
threshold —
high range9
—
—
2.36
2.36
2.46
2.46
2.56
2.56
V
V
P
P
VDD rising
VDD falling
Low-voltage
warning
21
VLVWL
threshold —
low range9
—
2.11
2.16
2.22
V
P
VDD rising
—
—
—
2.16
—
2.21
50
2.27
—
V
mV
V
P
C
P
Low-voltage inhibit
22
23
Vhys
reset/recoverhysteresis10
VBG Bandgap Voltage Reference11
1.110
1.17
1.230
1
2
3
Typical values are measured at 25C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL
Does not include analog module pins. Dedicated analog pins should not be pulled to VDD or VSS and should be left floating when not
used to reduce current leakage.
.
4
5
6
Measured with VIn = VDD
.
All functional non-supply pins are internally clamped to VSS and VDD except PTD1.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions.
If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power
supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which
would reduce overall power consumption).
7
8
Maximum is highest voltage that POR is guaranteed.
9
Run at 1 MHz bus frequency
10
11
Low voltage detection and warning limits measured at 1 MHz bus frequency.
Factory trimmed at VDD = 3.0 V, Temp = 25C
22
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.6
Supply Current Characteristics
Table 10. Supply Current Characteristics
Bus
Freq
Temp
(C)
#
Symbol
Parameter
VDD (V)
Typ1
Max
Unit
C
Run supply
current
1
RIDD
FEI mode; all modules ON2
25.165
MHz
–40 to
25
3
3
3
3
3
44
44
48
48
—
—
—
mA
mA
mA
mA
mA
P
P
T
T
T
25.165
MHz
105
–40 to
105
20 MHz
8 MHz
1 MHz
32.3
16.4
2.9
–40 to
105
–40 to
105
Run supply
current
2
RIDD
FEI mode; all modules OFF3
25.165
–40 to
105
3
29
29.6
—
mA
mA
mA
mA
C
T
T
T
MHz
–40 to
105
20 MHz
3
3
3
25.4
12.7
2.4
–40 to
105
8 MHz
1 MHz
—
–40 to
105
—
Run supply
current
3
4
RIDD
LPS=0; all modules OFF3
16 kHz
FBILP
–40 to
105
3
3
232
231
280
296
A
A
T
T
16 kHz
FBELP
–40 to
105
Run supply
current
LPS=1, all modules OFF3
RIDD
16 kHz
FBELP
3
3
74
74
75
A
A
0 to 70
T
T
16 kHz
FBELP
–40 to
105
120
Freescale Semiconductor
23
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 10. Supply Current Characteristics (continued)
Bus
Temp
(C)
#
Symbol
Parameter
VDD (V)
Typ1
Max
Unit
C
Freq
Wait mode
supply
current
FEI mode, all modules OFF3
25.165
WIDD
5
–40 to
105
3
16.5
10.3
6.6
—
—
—
—
mA
mA
mA
mA
C
T
T
T
MHz
–40 to
105
20 MHz
3
3
3
–40 to
105
8 MHz
1 MHz
–40 to
105
1.7
Low-Power
Wait mode
supply
LPWIDD
6
7
current
–40 to
105
16 KHz
3
3
28
62
µA
µA
T
P
Stop2 mode
supply
current4
S2IDD
–40 to
25
N/A
0.410
1.00
N/A
N/A
N/A
3
3
3
3.7
10
21
10
20
µA
µA
µA
70
85
C
C
P
31.5
105
–40 to
25
N/A
2
0.410
0.640
µA
C
N/A
N/A
N/A
2
2
2
3.4
9.5
20
9
µA
µA
µA
70
85
C
C
C
18
30
105
24
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Temp
Table 10. Supply Current Characteristics (continued)
Bus
#
Symbol
Parameter
VDD (V)
Typ1
Max
Unit
C
Freq
(C)
Stop3 mode
supply
current4
S3IDD
No clocks active
–40 to
25
N/A
3
0.650
1.0
µA
P
N/A
N/A
N/A
3
3
3
8.5
20
53
18
28
63
µA
µA
µA
70
85
C
C
P
8
105
–40 to
25
N/A
2
0.400
0.900
µA
C
N/A
N/A
2
2
8.2
18
16
26
µA
µA
70
85
C
C
N/A
2
47
59
µA
105
C
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
ON = System Clock Gating Control registers turn on system clock to the corresponding modules.
OFF = System Clock Gating Control registers turn off system clock to the corresponding modules.
All digital pins must be configured to a known state to prevent floating pins from adding current. Smaller packages may have some
pins that are not bonded out; however, software must still be configured to the largest pin package available so that all pins are in
a known state. Otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw.
NOTE: I/O pins are configured to output low, input-only pins are configured to pullup enabled. IRO pin connects to ground. FB_AD12
pin is pullup enabled. TRIAMPx, OPAMPx, DACO, and VREFO pins are at reset state and unconnected.
Table 11. Typical Stop Mode Adders
Temperature (°C)
#
Parameter
Condition
Units
C
–40
25
70
85
105
1
2
3
LPO
—
50
600
—
75
650
73
100
750
80
150
850
93
250
1000
125
nA
nA
µA
D
D
T
EREFSTEN RANGE = HGO = 0
IREFSTEN1
—
Does not include clock source
current
4
5
6
TOD
50
116
17
75
117
18
100
126
24
150
132
35
250
172
74
nA
µA
µA
D
T
T
LVD1
LVDSE = 1
Not using the bandgap
(BGBE = 0)
PRACMP1
ADLPC = ADLSMP = 1
Not using the bandgap
(BGBE = 0)
7
ADC1
190
195
210
220
260
µA
T
Freescale Semiconductor
25
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 11. Typical Stop Mode Adders (continued)
Temperature (°C)
Condition
#
Parameter
Units
C
–40
25
70
85
105
High-Power mode; no load on
DACO
DAC1
339
345
346
346
360
µA
T
8
Low-Power mode
High-Power mode
Low-Power mode
High-Power mode
Low-Power mode
41
276
42
43
350
49
43
370
57
44
376
58
50
390
68
µA
µA
µA
µA
µA
T
T
T
T
T
OPAMP1
TRIAMP1
9
420
52
432
52
433
52
438
55
478
60
10
1
Not available in stop2 mode.
Figure 6. Stop IDD versus Temperature
26
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.7
PRACMP Electricals
Table 12. PRACMP Electrical Specifications
#
Characteristic
Supply voltage
Symbol
Min
Typical
Max
Unit
C
1
2
3
VPWR
IDDACT1
IDDACT2
1.8
—
—
—
—
3.6
80
40
V
P
D
D
Supply current (active) (PRG enabled)
Supply current (active) (PRG disabled)
A
A
—
Supply current (ACMP and PRG all
disabled)
4
IDDDIS
—
—
2
nA
D
5
6
7
8
9
Analog input voltage
VAIN
VAIO
VSS – 0.3
—
5
VDD
40
V
mV
mV
nA
s
V
D
D
D
D
D
D
Analog input offset voltage
Analog comparator hysteresis
Analog input leakage current
Analog comparator initialization delay
—
3.0
—
VH
—
—
—
—
20.0
1
IALKG
tAINIT
VIn2 (VDD25
—
1.0
2.75
10 Programmable reference generator inputs
)
1.8
Programmable reference generator setup
delay
11
tPRGST
Vstep
—
1
1
—
1.25
Vin
µs
LSB
V
D
D
P
Programmable reference generator step
size
12
0.75
Programmable reference generator voltage
range
13
Vprgout
VIn/32
—
3.8
12-Bit DAC Electricals
Table 13. DAC 12LV Operating Requirements
#
Characteristic
Supply voltage
Symbol
Min
Max
Unit
C
Notes
1
2
3
VDDA
VDACR
TA
1.8
1.15
–40
3.6
3.6
105
V
V
P
C
C
Reference voltage
Temperature
°C
A small load capaci-
tance (47 pF) can
improve the band-
width performance of
the DAC.
4
5
Output load capacitance
Output load current
CL
—
—
100
1
pF
C
C
IL
mA
Table 14. DAC 12-Bit Operating Behaviors
#
Characteristic
Symbol
Min
Typ
Max
Unit
C
Notes
1
Resolution
N
—
T
12
12
bit
Freescale Semiconductor
27
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors (continued)
#
Characteristic
Symbol
Min
Typ
Max
Unit
C
Notes
µA
2
3
Supply current low-power mode
Supply current high-power mode
IDDA_DACLP
IDDA_DACHP
—
—
50
T
T
100
500
345
µA
µs
• VDDA = 3 V
or 2.2 V
• VREFSEL = 1
• Temperature
= 25°C
Full-scale Settling time
(±1 LSB)
(0x080 to 0xF7F or 0xF7F to
0x080)
4
5
TsFSLP
—
—
—
—
200
T
T
low-power mode
• VDDA = 3 V
or 2.2 V
• VREFSEL = 1
• Temperature
= 25°C
Full-scale Settling time
(±1 LSB)
(0x080 to 0xF7F or 0xF7F to
0x080)
TsFSHP
TsC-CLP
30
µs
µs
high-power mode
• VDDA = 3 V
or 2.2 V
• VREFSEL = 1
• Temperature
= 25°C
Code-to-code Settling time
(±1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
6
7
—
—
—
1
5
T
T
low-power mode
• VDDA = 3 V
or 2.2 V
Code-to-code Settling time
(±1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
• VREFSEL = 1
• Temperature
= 25°C
TsC-CHP
—
µs
high-power mode (3 V at Room
Temperature)
DAC output voltage range low
(high-power mode, no load, DAC
set to 0) (3 V at Room
8
9
Vdacoutl
—
—
T
T
—
100
—
mV
mV
Temperature)
DAC output voltage range high
(high-power mode, no load, DAC
set to 0x0FFF)
Vdacouth
V
DACR
-100
10
11
Integral non-linearity error
INL
—
—
T
T
—
± 8
± 1
LSB
LSB
Differential non-linearity error
VDACR is > 2.4 V
DNL
—
Calculated
by a best fit
curve from
12
13
Offset error
EO
—
—
T
T
±0.4
±0.1
± 3
%FSR
%FSR
V
+
SS
100mV to
V
REFH
–100mV
Calculated
by a best fit
curve from
V
+
SS
Gain error, V
= Vext = VDD
EG
± 0.5
REFH
100mV to
V
REFH
–100mV
28
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors (continued)
#
Characteristic
Symbol
Min
Typ
Max
Unit
C
Notes
Power supply rejection ratio
VDD 2.4 V
14
PSRR
—
—
T
60
dB
See Typical
Drift figure
that follows.
Temperature drift of offset voltage
(DAC set to 0x0800)
15
16
Tco
Ac
—
—
—
—
T
T
2
8
mV
Offset aging coefficient
µV/yr
Figure 7. Offset at Half Scale vs Temperature
3.9
ADC Characteristics
Table 15. 16-Bit ADC Operating Conditions
#
Symb Characteristic
Conditions
Min
Typ1
Max
Unit
C
Comment
1
VDDA Supply voltage Absolute
1.8
—
3.6
V
D
D
Delta to VDD
(VDD–VDDA
2
VDDA
–100
0
0
+100
+100
mV
2
)
Delta to VSS2
3
4
VSSA Ground voltage
–100
1.15
mV
V
D
D
(VSS–VSSA
)
VREFH Ref Voltage High
VDDA VDDA
Freescale Semiconductor
29
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 15. 16-Bit ADC Operating Conditions (continued)
#
Symb Characteristic
Conditions
Min
Typ1
VSSA VSSA
Max
Unit
C
Comment
5
6
VREFL Ref Voltage Low
VADIN Input Voltage
VSSA
V
V
D
D
VREFL
—
VREFH
Input
CADIN
16-bit modes
8/10/12-bit modes
8
4
10
5
7
8
—
—
pF
T
T
Capacitance
RADIN Input Resistance
2
5
k
External to
MCU
Assumes
ADLSMP=0
Analog Source
RAS
9
Resistance
16-bit mode
—
—
0.5
k
T
fADCK > 8 MHz
4 MHz < fADCK < 8
MHz
—
—
—
—
—
—
1
2
1
k
k
k
T
T
T
f
ADCK < 4 MHz
13/12-bit mode
11/10-bit mode
9/8-bit mode
fADCK > 8 MHz
4 MHz < fADCK < 8
MHz
—
—
—
—
—
—
2
5
2
k
k
k
T
T
T
fADCK < 4 MHz
f
ADCK > 8 MHz
4 MHz < fADCK < 8
MHz
—
—
—
—
—
—
—
—
5
10
5
k
k
k
k
T
T
T
T
fADCK < 4 MHz
fADCK > 8 MHz
fADCK < 8 MHz
10
ADC Conversion Clock
Frequency
10
fADCK
ADLPC=0, ADHSC=1
1.0
1.0
—
—
8.0
5.0
MHz
MHz
D
D
ADLPC=0, ADHSC=0
ADLPC=1, ADHSC=0
1.0
—
2.5
MHz
D
1
2
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
DC potential difference.
30
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 8. ADC Input Impedance Equivalency Diagram
Freescale Semiconductor
31
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 16. 16-Bit SAR ADC Characteristics full operating range
(V
= VDDA, > 1.8, V
= VSSA 8 MHz, –40 to 85 °C)
REFH
REFL
#
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
ADLPC=1, ADHSC=0
ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1
Stop, Reset, Module Off
ADLPC=1, ADHSC=0
ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1
—
—
—
—
—
—
—
215
470
610
0.01
2.4
—
—
—
—
—
—
—
ADLSMP
=0
ADCO=1
1
2
3
Supply Current
Supply Current
IDDAD
IDDAD
A
A
T
T
ADC
Asynchronous
Clock Source
5.2
C
tADACK =
1/fADACK
fADACK
MHz
6.2
4
5
Sample Time
See Reference Manual for sample times
See Reference Manual for conversion times
Conversion
Time
32x
Hardware
Averaging
(AVGE =
%1
Total
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode
—
—
16
20
48/ –40
56/ –28
6
TUE
LSB3
T
AVGS =
%11)
13-bit differential mode
12-bit single-ended mode
—
—
1.5
1.75
3.0
3.5
T
T
T
T
T
T
T
11-bit differential mode
10-bit single-ended mode
—
—
0.7
0.8
1.5
1.5
9-bit differential mode
8-bit single-ended mode
—
—
0.5
0.5
1.0
1.0
Differential
Non-Linearity
16-bit differential mode
16-bit single-ended mode
—
—
2.5
2.5
5/–3
+5/–3
7
DNL
LSB2
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
1
1
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
0.75
0.75
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
32
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 16. 16-Bit SAR ADC Characteristics full operating range
(V
= VDDA, > 1.8, V
= VSSA 8 MHz, –40 to 85 °C) (continued)
REFH
REFL
#
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
Integral
Non-Linearity
16-bit differential mode
16-bit single-ended mode
—
—
6.0
10.0
16.0
20.0
8
INL
LSB2
T
13-bit differential mode
12-bit single-ended mode
—
—
1.0
1.0
2.5
2.5
T
T
T
T
T
T
T
T
T
T
T
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.3
0.3
0.5
0.5
Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode
—
—
4.0
4.0
+32/ –24
+24/ –16
VADIN
VSSA
=
9
EZS
EFS
EQ
LSB2
LSB2
LSB2
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
2.5
2.0
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
16-bit differential mode
16-bit single-ended mode
—
—
+10/0
+14/0
+42/–2
+46/–2
VADIN =
VDDA
10 Full-Scale Error
13-bit differential mode
12-bit single-ended mode
—
—
1.0
1.0
3.5
3.5
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.5
1.5
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
Quantization
Error
11
16-bit modes
—
—
–1 to 0
—
—
D
C
<13-bit modes
0.5
16-bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
12.8
12.7
12.6
12.5
11.9
14.2
13.8
13.6
13.3
12.5
—
—
—
—
—
Fin
Fsample/10
0
=
Effective
12
ENOB
SINAD
Bits
dB
Number of Bits
Avg=1
Signal to Noise
13
SINAD = 6.02 ENOB + 1.76
See ENOB
plus Distortion
Freescale Semiconductor
33
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
(V
Table 16. 16-Bit SAR ADC Characteristics full operating range
= VDDA, > 1.8, V
= VSSA 8 MHz, –40 to 85 °C) (continued)
REFH
REFL
#
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
16-bit differential mode
Avg=32
14
C
Fin
Fsample/10
0
=
—
—
–91.5
–85.5
92.2
–74.3
—
Total Harmonic
Distortion
THD
dB
16-bit single-ended mode
Avg=32
D
C
D
16-bit differential mode
Avg=32
15
16
Spurious Free
Dynamic
Range
Fin =
Fsample/10
0
75.0
—
—
SFDR
dB
16-bit single-ended mode
Avg=32
86.2
—
IIn
=
leakage
current
(refer to
DC
Input Leakage
Error
all modes
EIL
IIn * RAS
mV
D
characteri
stics)
17
18
—
—
—
1.646
1.769
718.2
—
—
—
Temp Sensor
Slope
–40C – 25C
25C – 125C
mV/×
C
m
C
C
Temp Sensor
Voltage
VTEMP2
25C
mV
5
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1 LSB = (VREFH – VREFL)/2N
3
34
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 17. 16-bit SAR ADC Characteristics full operating range
(V = V , 2.7 V, V = V , f 4 MHz, ADHSC = 1)
REFH
DDA
REFL
SSA ADACK
#
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
32x
Hardware
Averaging
(AVGE =
%1
Total
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode
—
—
16
20
24/ –24
32/–20
1
TUE
LSB3
T
AVGS =
%11)
13-bit differential mode
12-bit single-ended mode
—
—
1.5
1.75
2.0
2.5
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
11-bit differential mode
10-bit single-ended mode
—
—
0.7
0.8
1.0
1.25
9-bit differential mode
8-bit single-ended mode
—
—
0.5
0.5
1.0
1.0
Differential
Non-Linearity
16-bit differential mode
16-bit single-ended mode
—
—
2.5
2.5
3
3
2
3
4
DNL
LSB2
LSB2
LSB2
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
1
1
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
0.75
0.75
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
Integral
Non-Linearity
16-bit differential mode
16-bit single-ended mode
—
—
6.0
10.0
12.0
16.0
INL
13-bit differential mode
12-bit single-ended mode
—
—
1.0
1.0
2.0
2.0
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.3
0.3
0.5
0.5
Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode
—
—
4.0
4.0
+16/0
+16/-8
VADIN
=
EZS
VSSA
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
2.0 2.0
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
Freescale Semiconductor
35
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 17. 16-bit SAR ADC Characteristics full operating range
= V , 2.7 V, V = V , f 4 MHz, ADHSC = 1) (continued)
(V
REFH
DDA
REFL
SSA ADACK
#
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
16-bit differential mode
16-bit single-ended mode
—
—
+8/0
+12/0
+24/0
+24/0
VADIN
VDDA
=
5
Full-Scale Error
EFS
LSB2
T
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
2.0
2.5
T
T
T
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
Quantization
Error
6
7
16-bit modes
EQ
—
—
–1 to 0
—
—
LSB2
D
C
<13-bit modes
0.5
16-bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
14.3
13.8
13.4
13.1
12.4
14.5
14.0
13.7
13.4
12.6
—
—
—
—
—
Fin
=
Effective
Number of Bits
ENO
B
Bits
Fsample/10
0
Avg=1
Signal to Noise
plus Distortion
SINAD = 6.02 ENOB + 1.76
8
9
See ENOB
SINA
D
dB
dB
16-bit differential mode
Avg=32
C
D
C
D
Fin
Fsample/10
0
=
—
—
–95.8
—
–90.4
—
Total Harmonic
Distortion
THD
16-bit single-ended mode
Avg=32
16-bit differential mode
Avg=32
10
Spurious Free
Dynamic
Range
Fin =
Fsample/10
0
91.0
—
96.5
—
—
SFDR
dB
16-bit single-ended mode
Avg=32
—
IIn
=
leakage
current
(refer to
DC
Input Leakage
Error
11
all modes
EIL
IIn * RAS
mV
D
characteri
stics)
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1 LSB = (VREFH – VREFL)/2N
3
36
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.10 MCG and External Oscillator (XOSC) Characteristics
Table 18. MCG (Temperature Range = –40 to 105°C Ambient)
#
Rating
Symbol
Min
Typical
Max
Unit
C
tirefst
1
Internal reference startup time
—
55
100
s
D
factory trimmed at
VDD=3.0 V and
temp=25C
—
31.25
—
C
Average internal reference
frequency
fint_ft
2
3
kHz
user trimmed
31.25
16
—
—
39.0625
20
C
C
Low range
(DRS=00)
DCO output frequency range —
trimmed
fdco_t
MHz
Mid range
(DRS=01)
High range1
32
40
—
—
40
60
C
C
(DRS=10)
Resolution of trimmed DCO
output frequency at fixed voltage
and temperature
with FTRIM
—
—
0.1
0.2
0.2
0.4
C
C
fdco_res_t
%fdco
4
5
without FTRIM
over voltage and
temperature
—
—
1.0
2
1
P
C
Total deviation of trimmed DCO
output frequency over voltage and
temperature
fdco_t
%fdco
over fixed voltage
and temp range
of 0 – 70 C
0.5
FLL2
PLL3
—
—
—
—
1
1
C
D
tfll_acquire
tpll_acquire
Acquisition time
6
7
ms
Long term Jitter of DCO output clock (averaged over
2mS interval) 4
CJitter
%fdco
—
0.02
0.2
C
fvco
8
9
VCO operating frequency
7.0
1.0
—
—
55.0
2.0
MHz
MHz
D
D
fpll_ref
PLL reference frequency range
Jitter of PLL output clock
Long term
fpll_jitter_625
0.5664
%fpll
%
10
—
—
D
measured over 625ns 5
ns
Entry6
1.49
4.47
—
—
2.98
5.97
D
D
Dlock
Dunl
11 Lock frequency tolerance
Exit7
tfll_acquire+
1075(1/fint_t)
tfll_lock
FLL
—
—
—
D
D
12 Lock time
s
tpll_acquire+
1075(1/fpll_re
f)
tpll_lock
PLL
—
Loss of external clock minimum frequency - RANGE =
0
(3/5) x
fint_t
floc_low
13
14
—
—
—
—
kHz
kHz
D
D
Loss of external clock minimum frequency - RANGE =
1
(16/5) x
fint_t
floc_high
1
This should not exceed the maximum CPU frequency for this device which is 50.33 MHz.
Freescale Semiconductor
37
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
2
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
3
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps CAN Bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the
sample point of a bit using 8 time quanta per bit.
5
6
7
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is
already in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 19. XOSC (Temperature Range = –40 to 105°C Ambient)
#
Characteristic
• Low range (RANGE = 0)
Symbol
Min
Typ1
Max
Unit
C
D
flo
32
1
—
—
38.4
5
kHz
• High range (RANGE = 1),
• FEE or FBE mode 2
fhi-fll
MHz
D
D
• High range (RANGE = 1),
• PEE or PBE mode 3
fhi-pll
1
1
—
—
16
16
MHz
MHz
Oscillator crystal or resonator
(EREFS = 1, ERCLKEN = 1)
1
• High range (RANGE = 1),
• High gain (HGO = 1),
• BLPE mode
fhi-hgo
D
D
• High range (RANGE = 1),
• Low power (HGO = 0),
• BLPE mode
fhi-lp
1
—
8
MHz
C1
C2
See crystal or resonator manufacturer’s
recommendation.
2
3
Load capacitors
D
D
D
• Low range
(32 kHz to 38.4 kHz)
Feedback resistor
RF
—
—
—
—
—
10
1
M
k
• High range
(1 MHz to 16 MHz)
Series resistor — Low range
Series resistor — High range
• Low Gain (HGO = 0)
• High Gain (HGO = 1)
• Low Gain (HGO = 0)
• High Gain (HGO = 1)
8 MHz
—
—
—
0
100
0
—
—
—
D
D
D
D
D
D
D
4
5
RS
RS
—
—
—
0
0
0
0
k
4 MHz
10
20
1 MHz
38
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 19. XOSC (Temperature Range = –40 to 105°C Ambient) (continued)
#
Characteristic
• Low range, low gain (RANGE =
Symbol
Min
Typ1
Max
Unit
C
—
—
D
t
0, HGO = 0)
200
400
CSTL-LP
t
• Low range, high gain
(RANGE = 0, HGO = 1)
CSTL-HG
O
—
—
—
—
D
D
6
Crystal start-up time 4
• High range, low gain
(RANGE = 1, HGO = 0)5
ms
tCSTH-LP
5
• High range, high gain
(RANGE = 1, HGO = 1)5
tCSTH-HG
—
15
—
D
O
1
2
3
4
5
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz.
This parameter is characterized and not tested on each device. Proper PC board layout porcedures must be followed to achieve specifications.
4 MHz crystal.
MCU
EXTAL
XTAL
R
RS
F
C1
C2
Crystal or Resonator
o
3.11 Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to
interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected
to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple
chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect
to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus
frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the
Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.
Freescale Semiconductor
39
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 20. Mini-FlexBus AC Timing Specifications
Num
C
Characteristic
Frequency of Operation
Min
Max
Unit
Notes
—
—
D
D
D
D
D
—
39.73
—
25.1666
MHz
ns
—
MB1
MB2
MB3
MB4
MB5
Clock Period
Output Valid
Output Hold
Input Setup
Input Hold
—
20
—
—
—
—
1
ns
1
2
2
1.0
22
ns
ns
10
ns
1
2
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
Specification is valid for all MB_D[7:0].
S0
S1
S2
S3
S0
FB_CLK
MB1
MB3
FB_A[19:16]
ADDR[19:0]
MB2
ADDR[31:24]
MB5
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
DATA[7:0]
FB_D[7:0]
MB4
ADDR[19:16]
FB_AD[19:16]
FB_AD[15:0]
ADDR[15:0]
DATA[15:0]
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 9. Mini-FlexBus Read Timing
40
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
S0
S1
S2
S3
S0
FB_CLK
MB1
MB3
ADDR[19:8]
FB_AD[19:8]
MB2
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
ADDR[7:0]
FB_AD[7:0]
DATA[7:0]
ADDR[19:16]
FB_AD[19:16]
ADDR[15:0]
DATA[15:0]
FB_AD[15:0]
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 10. Mini-FlexBus Write Timing
Freescale Semiconductor
41
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.12.1 Control Timing
Table 21. Control Timing
#
Symbol
Parameter
Min
Typical1
Max
C
Unit
fBus
1
Bus frequency (tcyc = 1/fBus
)
MHz
VDD 1.8 V
DD > 2.1 V
VDD > 2.4 V
dc
dc
—
—
10
20
D
D
V
25.165
D
P
dc
—
Internal low-power oscillator
period
2
tLPO
700
1000
1300
s
External reset pulse width2
3
4
5
textrst
trstdrv
tMSSU
100
66 x tcyc
500
—
—
—
—
—
—
D
D
D
ns
ns
ns
(tcyc = 1/fSelf_reset
)
Reset low drive
Active background debug
mode latch setup time
Active background debug
mode latch hold time
6
7
tMSH
100
—
—
—
—
—
—
D
D
ns
ns
ns
IRQ pulse width
•
•
Asynchronous path2
Synchronous path3
100
1.5 x tcyc
t
ILIH, tIHIL
KBIPx pulse width
8
•
•
Asynchronous path2
Synchronous path3
100
1.5 x tcyc
D
tILIH, IHIL
t
42
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 21. Control Timing (continued)
#
Symbol
Parameter
Min
Typical1
Max
C
Unit
9
tRise, tFall
Port rise and fall time (load = 50 pF)4, Low Drive
ns
Slew rate
control
disabled
—
—
—
—
11
35
40
75
—
—
—
—
D
D
D
D
(PTxSE = 0)
Slew rate
control
enabled
(PTxSE = 1)
Slew rate
control
disabled
(PTxSE = 0)
Slew rate
control
enabled
(PTxSE = 1)
1
2
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed
to override reset requests from internal sources.
3
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.
textrst
RESET PIN
Figure 11. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 12. IRQ/KBIPx Timing
Freescale Semiconductor
43
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.12.2 TPM Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 22. TPM Input Timing
#
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
—
—
D
External clock frequency
External clock period
fTPMext
tTPMext
tclkh
dc
4
fBus/4
—
MHz
tcyc
tcyc
tcyc
tcyc
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
D
tclkl
—
D
tICPW
—
tTPMext
tclkh
TPMxCLK
tclkl
Figure 13. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 14. Timer Input Capture Pulse
44
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.13 SPI Characteristics
Table 23 and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 23. SPI Timing
No.1
Characteristic2
Operating frequency
Symbol
Min
Max
Unit
C
1
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
D
SPSCK period
2
3
4
5
6
7
Master
Slave
tSPSCK
2
4
2048
—
tcyc
tcyc
D
D
D
D
D
D
Enable lead time
Master
Slave
tLead
12
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
tLag
12
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Master
Slave
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
tSU
tSU
Master
Slave
15
15
—
—
ns
ns
tHI
tHI
Master
Slave
0
25
—
—
ns
ns
8
9
Slave access time3
ta
—
—
1
1
tcyc
tcyc
D
D
Slave MISO disable time4
tdis
Data valid (after SPSCK edge)
10
11
12
13
Master
Slave
tv
—
—
25
25
ns
ns
D
D
D
D
Data hold time (outputs)
Rise time
Master
Slave
tHO
0
0
—
—
ns
ns
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
1
2
Numbers in this column identify elements in Figure 15 through Figure 18.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
3
4
Hold time to high-impedance state.
Freescale Semiconductor
45
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Electrical Characteristics
SS1
(OUTPUT)
2
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
4
5
SCK
(CPOL = 1)
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN2
11
BIT 6 . . . 1
11
LSB IN
12
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
2
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
5
4
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
12
BIT 6 . . . 1
LSB IN
11
MOSI
(OUTPUT)
MSB OUT(2)
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 16. SPI Master Timing (CPHA = 1)
46
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
SS
(INPUT)
3
2
SCK
5
4
(CPOL = 0)
4
5
(INPUT)
2
SCK
(CPOL = 1)
(INPUT)
9
8
12
11
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
7
SLAVE
6
MOSI
(INPUT)
MSB IN
LSB IN
NOTE:
1. Not defined, but normally MSB of character just received
Figure 17. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
2
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
4
5
SCK
(CPOL = 1)
(INPUT)
11
SLAVE MSB OUT
12
9
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
6
7
8
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined, but normally LSB of character just received
Figure 18. SPI Slave Timing (CPHA = 1)
Freescale Semiconductor
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Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.14 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal V supply.
DD
For more detailed information about program/erase operations, see the Memory chapter in the Reference
Manual for this device (MCF51MM256RM).
Table 24. Flash Characteristics
#
Characteristic
Symbol
Min
Typical
Max
Unit
C
Supply voltage for program/erase
–40C to 105C
1
—
D
Vprog/erase
VRead
fFCLK
tFcyc
1.8
1.8
150
5
3.6
3.6
V
2
3
4
5
6
7
8
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
—
—
V
D
D
D
P
P
P
P
200
6.67
kHz
s
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
tBurst
4
tPage
4000
20,000
Mass erase time2
tMass
Program/erase endurance3
TL to TH = –40C to + 105C
T = 25C
9
10,000
—
—
100,000
—
—
C
C
cycles
years
10
Data retention4
tD_ret
15
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating
approximate time to program and erase.
3
4
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the
Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical
Data Retention for Nonvolatile Memory.
48
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.15 USB Electricals
The USB electricals for the USB On-the-Go module conform to the standards documented by the
Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the
standard or require additional information, this space would be used to communicate that information.
Table 25. Internal USB 3.3 V Voltage Regulator Characteristics
#
Characteristic
Symbol
Min
Typ
Max
Unit
C
1
2
Regulator operating voltage
VREG output
Vregin
3.9
3
—
5.5
V
V
C
P
Vregout
3.3
3.75
V
USB33 input with internal VREG
3
4
Vusb33in
IVRQ
3
3.3
0.5
3.6
—
V
C
C
disabled
VREG Quiescent Current
—
mA
Freescale Semiconductor
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Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.16 VREF Electrical Specifications
Table 26. VREF Electrical Specifications
#
Characteristic
Supply voltage
Symbol
Min
Max
Unit
C
1
2
3
4
VDDA
TA
1.80
–40
—
3.6
105
100
10
V
°C
nf
C
C
Temperature
Output Load Capacitance
Maximum Load
CL
D
—
—
mA
—
Voltage Reference Output with Factory
Trim. VDD = 3 V at 25°C.
1.145
1.153
5
Vout
V
P
Temperature Drift (Vmin – Vmax across
the full temperature range)
6
7
8
9
Tdrift
—
—
—
25
60
mV1
µV/year
µA
T
C
C
Aging Coefficient2
Ac
I
Powered down Current (Off Mode,
VREFEN=0, VRSTEN=0)
0.10
Bandgap only (MODE_LV[1:0] = 00)
I
I
—
—
75
µA
µA
T
T
10 Low-Power buffer (MODE_LV[1:0] = 01)
125
Tight-Regulation buffer (MODE_LV[1:0]
= 10)
11
I
—
—
1.1
mA
T
12 Load Regulation MODE_LV = 10
Line Regulation MODE = 1:0, Tight
—
100
µV/mA
C
Regulation VDD < 2.3 V, Delta VDDA
13 100 mV, VREFH = 1.2 V driven
externally with VREFO disabled.
(Power Supply Rejection)
=
DC
70
—
dB
C
1
2
See typical chart that follows (Figure 19).
Linear reliability model (1008 hours stress at 125°C = 10 years operating life) used to calculate Aging µV/year. Vrefo data recorded per
month.
Table 27. VREF Limited Range Operating Behaviors
#
Characteristic
Symbol
Min
Max
Unit
C
Notes
Voltage Reference Output with
Factory Trim (Temperature range
from 0° C to 50° C)
1
Vout
1.149
1.152
mV
T
Temperature Drift (Vmin – Vmax
Temperature range from 0° C to
50° C)
2
Tdrift
—
3
mV1
T
1
See typical chart that follows (Figure 19).
50
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Figure 19. Typical VREF Output vs. Temperature
Figure 20. Typical VREF Output vs. V
DD
Freescale Semiconductor
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Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
3.17 TRIAMP Electrical Parameters
Table 28. TRIAMP Characteristics 1.8–3.6 V, –40°C~105°C
#
Characteristic1
Operating Voltage
Symbol
Min
Typ2
Max
Unit
C
VDD
1
1.8
—
3.6
V
C
Supply Current (IOUT=0mA, CL=0)
Low-power mode
ISUPPLY
2
3
—
—
52
60
A
A
T
T
Supply Current (IOUT=0mA, CL=0)
High-speed mode
ISUPPLY
432
480
VOS
VOS
IOS
4
5
Input Offset Voltage
—
—
—
—
—
0
± 1
600
±120
< 350
3
± 5
—
mV
V
pA
pA
nA
V
T
T
T
T
T
T
T
T
D
D
Input Offset Voltage Temperature Drift
Input Offset Current
6
500
IBIAS
IBIAS
VCML
VCMH
RIN
7
Input Bias Current (0 ~ 50°C)
Input Bias Current (–40 ~ 105°C)
Input Common Mode Voltage Low
Input Common Mode Voltage High
Input Resistance
< ±500
6.55
8
9
—
—
VDD–1.4
10
11
12
13
—
500
—
—
—
V
—
—
5
M
pF
M
CIN
Input Capacitances
—
AC Input Impedance (fIN=100kHz)
1
—
|XIN|
14
15
Input Common Mode Rejection Ratio
Power Supply Rejection Ration
CMRR
PSRR
60
60
70
70
—
—
dB
dB
T
T
Slew Rate (VIN=100mV) Low-power
mode
16
SR
—
0.1
—
V/s
T
Slew Rate (VIN=100mV) High-speed
mode
17
18
19
SR
—
0.15
—
1
—
—
—
V/s
MHz
MHz
T
T
T
Unity Gain Bandwidth (Low-power mode)
50pF
GBW
GBW
0.25
1.6
Unity Gain Bandwidth (High-speed mode)
50pF
AV
20
21
DC Open Loop Voltage Gain
—
—
80
—
—
dB
pF
T
T
Load Capacitance Driving Capability
CL(max)
100
Output Impedance AC Open Loop
(@100 kHz Low-power mode)
ROUT
ROUT
22
23
24
—
—
1.4
184
—
—
—
k
D
D
T
Output Impedance AC Open Loop
(@100 kHz High-speed mode)
VDD
–
Output Voltage Range
triout
IOUT
0.15
V
0.15
25
26
27
Output Drive Capability
Gain Margin
—
20
45
± 1.0
—
—
mA
dB
T
D
T
GM
PM
—
Phase Margin
55
—
deg
52
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 28. TRIAMP Characteristics 1.8–3.6 V, –40°C~105°C (continued)
#
Characteristic1
Symbol
Min
Typ2
Max
Unit
C
28
Input Voltage Noise Density
f= 1 kHz
—
160
—
T
nV/Hz
1
2
All parameters are measured at 3.0 V, CL= 47 pF across temperature –40 to + 105 °C unless specified.
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
3.18 OPAMP Electrical Parameters
Table 29. OPAMP Characteristics 1.8–3.6 V
#
Characteristics1
Operating Voltage
Symbol
Min
Typ2
Max
Unit
C
1
VDD
1.8
—
3.6
V
C
Supply Current (IOUT=0mA, CL=0 Low-Power
mode)
2
3
ISUPPLY
ISUPPLY
—
—
48
80
A
T
T
Supply Current (IOUT=0mA, CL=0 High-Speed
mode)
350
500
A
4
5
Input Offset Voltage
VOS
VOS
IOS
—
—
—
—
—
—
—
—
0.1
—
—
—
2
10
6
—
mV
V/C
nA
nA
nA
nA
nA
nA
V
T
T
T
T
T
T
T
T
T
T
T
D
Input Offset Voltage Temperature Coefficient
Input Offset Current (–40°C to 105°C)
Input Offset Current (–40°C to 50°C)
Positive Input Bias Current (–40°C to 105°C)
Positive Input Bias Current (–40°C to 50°C)
Negative Input Bias Current (–40°C to 105°C)
Negative Input Bias Current (–40°C to 50°C)
Input Common Mode Voltage Low
Input Common Mode Voltage High
Input Resistance
6
2.5
—
250
45
7
IOS
8
IBIAS
IBIAS
IBIAS
IBIAS
VCML
VCMH
RIN
0.8
—
3.5
2
9
10
11
12
13
14
15
2.5
—
250
45
—
—
—
VDD
—
V
500
—
M
pF
Input Capacitances
CIN
10
AC Input Impedance (fIN=100kHz Negative
Channel)
16
17
|XIN|
|XIN|
—
—
52
—
—
k
k
D
D
AC Input Impedance (fIN=100kHz Positive
Channel)
132
18
19
20
21
22
23
24
25
Input Common Mode Rejection Ratio
Power Supply Rejection Ratio
CMRR
PSRR
SR
55
60
0.1
1
65
65
—
—
—
—
90
—
—
—
dB
dB
T
T
T
T
T
T
T
T
Slew Rate (VIN=100mV Low-Power mode)
Slew Rate (VIN=100mV High-Speed mode)
Unity Gain Bandwidth (Low-Power mode)
Unity Gain Bandwidth (High-Speed mode)
DC Open Loop Voltage Gain
—
V/s
V/s
MHz
MHz
dB
SR
—
GBW
GBW
AV
0.2
1
—
—
80
—
—
Load Capacitance Driving Capability
CL(max)
100
pF
Output Impedance AC Open Loop (@100 kHz
Low-Power mode)
26
ROUT
—
4k
—
D
Freescale Semiconductor
53
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Electrical Characteristics
Table 29. OPAMP Characteristics 1.8–3.6 V (continued)
#
Characteristics1
Symbol
Min
Typ2
Max
Unit
C
Output Impedance AC Open Loop (@100 kHz
High-Speed mode)
27
ROUT
—
220
—
D
VDD–0.1
5
28
Output Voltage Range
VOUT
0.15
—
V
T
29
30
31
Output Drive Capability
Gain Margin
IOUT
GM
PM
0.5
20
1.0
—
—
—
—
mA
dB
T
D
T
Phase Margin
45
55
deg
GPAMP startup time (Low-Power mode)
(Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF,
RL = 100k)
32
Tstartup
—
4
—
uS
T
GPAMP startup time (Low-Power mode)
(Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF,
RL = 100k)
33
34
Tstartup
—
—
1
—
—
uS
T
T
Input Voltage Noise Density
f=1 kHz
250
nV/Hz
1
All parameters are measured at 3.3 V, CL =4 7 pF across temperature –40 to + 105°C unless specified.
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2
54
Freescale Semiconductor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Ordering Information
4
Ordering Information
This section contains ordering information for the device numbering system. See Table 2 for feature
summary by package information.
4.1
Part Numbers
Table 30. Orderable Part Number Summary
Freescale Part
Flash / SRAM
Description
(Kbytes)
Package
Temperature
Number
MCF51MM256VML
MCF51MM256VLL
MCF51MM256VMB
MCF51MM256VLK
MCF51MM128VMB
MCF51MM128VLK
MCF51MM256CML
MCF51MM256CLL
MCF51MM256CMB
MCF51MM256CLK
MCF51MM128CMB
MCF51MM128CLK
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
256K/32K
256K/32K
256K/32K
256K/32K
128K/32K
128K/32K
256K/32K
256K/32K
256K/32K
256K/32K
128K/32K
128K/32K
104 MAPBGA
100 LQFP
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
81 MAPBGA
80 LQFP
81 MAPBGA
80 LQFP
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
81 MAPBGA
80 LQFP
4.2
Package Information
Table 31. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
100
80
Low Quad Flat Package
Low Quad Flat Package
MAPBGA Package
LQFP
LQFP
LL
LK
983-03
1418
98ASS23308W
98ASS23174W
98ARH98267A
98ASA10670D
104
81
MAPBGA
MAPBGA
ML
MB
1285-02
1662-01
MAPBGA Package
Freescale Semiconductor
55
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Revision History
4.3
Mechanical Drawings
Table 31 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MCF51MM256/128 Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
•
•
Click on the appropriate link in Table 31, or
Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate
®
document number (from Table 31) in the “Enter Keyword” search box at the top of the page.
5
Revision History
This section lists major changes between versions of the MCF51MM256 Data Sheet.
Table 32. Revision History
Revision
Date
Description
0
March/April 2009 Initial Draft
• Revised to follow standard template.
• Removed extraneous headings from the TOC.
• Corrected units for Monotoncity to be blank in for the DAC specification.
• Updated ADC characteristic tables to include 16-Bit SAR in headings.
1
2
July 2009
July 2009
• Changed MCG (XOSC) Electricals Table - Row 2, Average Internal Reference
Frequency typical value from 32.768 to 31.25.
• Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices.
• Revised the ESD and Latch-Up Protection Characeristic description to read: Latch-up
Current at TA = 125°C.
• Changed Table . DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA
conditions to 1.8 V, ILoad = 600A respectively.
• Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value
to be 1.13 instead of 1.15.
• Updated the ADC electricals.
• Inserted the Mini-FlexBus Timing Specifications.
3
April 2010
• Added a Temp Drift parameter to the VREF Electrical Specifications.
• Removed the S08 Naming Convention diagram.
• Updated the Orderable Part Number Summary to include the Freescale Part Number
suffixes.
• Completed the Package Description table values.
• Changed the 80LQFP package drawing from 98ARL10530D to 98ASS23174W.
Updated electrical characteristic data.
• Updated with the latest characteristic data. Added several figures. Added the ADC
Typical Operation table.
4
October 2010
56
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MCF51MM256
Rev. 4, 10/2010
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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