MCF52223CAF66 [NXP]
MCF5222X 32-bit MCU, ColdFire V2 core, 256KB Flash, 66MHz, QFP 100;
| 型号： | MCF52223CAF66 |
| 厂家： | 
NXP |
| 描述： | MCF5222X 32-bit MCU, ColdFire V2 core, 256KB Flash, 66MHz, QFP 100 时钟 微控制器 外围集成电路 |
| 文件： | 总55页 (文件大小：1107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52223
Rev. 3, 3/2011
MCF52223
LQFP–64
MCF52223 ColdFire
Microcontroller
Supports MCF52223 and
10 mm x 10 mm
MAPBGA–81
10 mm x 10 mm
LQFP–100
14 mm x 14 mm
MCF52221
The MCF52223 microcontroller family is a member of the
• Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)
®
ColdFire family of reduced instruction set computing
(RISC) microprocessors.
• Test access/debug port (JTAG, BDM)
This document provides an overview of the 32-bit MCF52223
microcontroller, focusing on its highly integrated and diverse
feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to
256 Kbytes of flash memory and 32 Kbytes of static random
access memory (SRAM). On-chip modules include:
• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with Multiply
Accumulate (MAC) Unit and hardware divider
• Universal Serial Bus On-The-Go (USBOTG)
• USB Transceiver
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Inter-integrated circuit (I2C™) bus interface module
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter
(ADC)
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM), and pulse accumulation
• Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer
• Two 16-bit periodic interrupt timers (PITs)
• Real-time clock (RTC) module
• Programmable software watchdog timer
• Interrupt controller capable of handling 57 sources
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Table of Contents
1
Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 30
2.4 Flash Memory Characteristics. . . . . . . . . . . . . . . . . . . 31
2.5 EzPort Electrical Specifications. . . . . . . . . . . . . . . . . . 32
2.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7 DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . 33
2.8 Clock Source Electrical Specifications . . . . . . . . . . . . 34
2.9 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 35
2.10 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.11 I2C Input/Output Timing Specifications . . . . . . . . . . . . 36
2.12 Analog-to-Digital Converter (ADC) Parameters. . . . . . 37
2.13 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . . 38
2.14 DMA Timers Timing Specifications . . . . . . . . . . . . . . . 39
2.15 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 39
2.16 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40
2.17 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 64-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 81 MAPBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3 100-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .22
1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .22
1.8 USB On-the-Go. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.9 I2C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.10 UART Module Signals. . . . . . . . . . . . . . . . . . . . . . . . . .23
1.11 DMA Timer Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .24
1.14 Pulse Width Modulator Signals. . . . . . . . . . . . . . . . . . .24
1.15 Debug Support Signals. . . . . . . . . . . . . . . . . . . . . . . . .24
1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .25
1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .26
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .28
3
4
2
MCF52223 ColdFire Microcontroller, Rev. 3
2
Freescale Semiconductor
Family Configurations
1
Family Configurations
Table 1. MCF52223 Family Configurations
Module
52221
52223
ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit)
System Clock
66, 80 MHz
up to 76
Performance (Dhrystone 2.1 MIPS)
Flash / Static RAM (SRAM)
Interrupt Controller (INTC)
128/16 Kbytes
256/32 Kbytes
Fast Analog-to-Digital Converter (ADC)
USB On-The-Go (USB OTG)
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
2
4
3
2
4
3
Programmable Interrupt Timer
Four-Channel General Purpose Timer
32-bit DMA Timers
QSPI
UART(s)
I2C
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port1
Package
64 LQFP
81 MAPBGA
100 LQFP
81 MAPBGA
100 LQFP
1
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is
bonded on smaller packages.
MCF52223 ColdFire Microcontroller, Rev. 3
3
Freescale Semiconductor
Family Configurations
1.1
Block Diagram
Figure 1 shows a top-level block diagram of the device. Package options for this family are described later in this document.
EzPCK
EzPCS
EzPD
EzPQ
EzPort
Arbiter
GPTn
QSPI_DIN,
QSPI_DOUT
Interrupt
Controller
QSPI_CLK,
QSPI_CSn
UTXDn
UART
0
UART
1
UART
2
URXDn
I2C
4 CH DMA
QSPI
URTSn
UCTSn
DTINn/DTOUTn
DTIM
0
DTIM
1
DTIM
2
DTIM
3
SWT
To/From PADI
MUX
PWMn
JTAG_EN
V2 ColdFire CPU
OEP MAC
IFP
PMM
CIM
JTAG
TAP
32 Kbytes
SRAM
256 Kbytes
Flash
(32K16)4
RSTI
PORTS
(GPIO)
AN[7:0]
ADC
RSTO
(4K16)4
VRH VRL
VSTBY
Edge
Port
PLL OCO
CLKGEN
USB OTG
PIT0
PIT1
GPT
PWM
EXTAL XTAL CLKOUT
CLKMOD0 CLKMOD1
To/From Interrupt Controller
Figure 1. Block Diagram
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
4
Family Configurations
1.2
Features
1.2.1
Feature Overview
The MCF52223 family includes the following features:
•
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 1616 32 or 3232 32 operations
— Illegal instruction decode that allows for 68-Kbyte emulation support
System debug support
•
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
2-level trigger
•
•
On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply
support
— 256 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
— Software controlled disable of external clock output for low-power consumption
Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller
— Full-speed / low-speed host controller
•
•
— USB 1.1 and 2.0 compliant full-speed / low speed device controller
— 16 bidirectional end points
— DMA or FIFO data stream interfaces
— Low power consumption
— OTG protocol logic
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
•
I2C module
MCF52223 ColdFire Microcontroller, Rev. 3
5
Freescale Semiconductor
Family Configurations
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
•
•
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 s conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
— Unused analog channels can be used as digital I/O
Four 32-bit timers with DMA support
•
— 12.5 ns resolution at 80 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input capture capability with programmable trigger edge on input pin
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare
Four-channel general purpose timer
•
•
— 16-bit architecture
— Programmable prescaler
— Output pulse-widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel
Pulse-width modulation timer
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
— Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached
(PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
•
Two periodic interrupt timers (PITs)
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
6
Family Configurations
— 16-bit counter
— Selectable as free running or count down
Real-Time Clock (RTC)
•
•
•
— Maintains system time-of-day clock
— Provides stopwatch and alarm interrupt functions
Software watchdog timer
— 32-bit counter
— Low-power mode support
Clock generation features
— Crystal, on-chip trimmed relaxation oscillator, or external oscillator reference options
— Trimmed relaxation oscillator
— Pre-divider capable of dividing the clock source frequency into the PLL reference frequency range
— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
— Low power modes supported
n
— 2 (0 n 15) low-power divider for extremely low frequency operation
•
Interrupt controller
— Uniquely programmable vectors for all interrupt sources
— Fully programmable level and priority for all peripheral interrupt sources
— Seven external interrupt signals with fixed level and priority
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low-power modes
DMA controller
•
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (432-bit)
burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle-steal support
— Software-programmable DMA requests for the UARTs (3) and 32-bit timers (4)
Reset
•
— Separate reset in and reset out signals
— Seven sources of reset:
–
–
–
–
–
–
–
Power-on reset (POR)
External
Software
Watchdog
Loss of clock
Loss of lock
Low-voltage detection (LVD)
— Status flag indication of source of last reset
Chip configuration module (CCM)
•
— System configuration during reset
MCF52223 ColdFire Microcontroller, Rev. 3
7
Freescale Semiconductor
Family Configurations
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
General purpose I/O interface
•
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
•
1.2.2
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer
register and four new instructions to assist in bit processing. Additionally, the core includes the multiply-accumulate (MAC)
unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16x16
bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned
integers, signed fractional operands, and a complete set of instructions to process these data types. The MAC provides support
for execution of DSP operations within the context of a single processor at a minimal hardware cost.
1.2.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator
development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided
on 100-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit
emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
This device implements revision B+ of the ColdFire Debug Architecture.
The processor’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be
serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.
These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining
processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of
the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 100-pin packages. However, every product features the dedicated debug
serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
8
Family Configurations
1.2.4
JTAG
The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action
Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and
three test registers (a 1-bit bypass register, a 112-bit boundary-scan register, and a 32-bit ID register). The boundary scan register
links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device
system logic.
The device implementation can:
•
•
•
•
•
Perform boundary-scan operations to test circuit board electrical continuity
Sample system pins during operation and transparently shift out the result in the boundary scan register
Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
1.2.5
On-Chip Memories
1.2.5.1
SRAM
The dual-ported SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access in a
single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the 4-Gbyte address space. This
memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is
physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or
memory-referencing commands from the debug module.
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing
applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to
maximize system performance.
1.2.5.2
Flash Memory
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local
bus. The CFM is constructed with four banks of 32-Kbyte16-bit flash memory arrays to generate 256 Kbytes of 32-bit flash
memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash
memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring
an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller
that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for
all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be
programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read,
erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips.
1.2.6
Power Management
The device incorporates several low-power modes of operation entered under program control and exited by several external
trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply
voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt
condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the
chip falls below the standby battery voltage.
MCF52223 ColdFire Microcontroller, Rev. 3
9
Freescale Semiconductor
Family Configurations
1.2.7
USB On-The-Go Controller
The device includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller. USB is a popular standard for
connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs.
The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly
to each other without the need for a PC. The dual-mode controller on the device can act as a USB OTG host and as a USB
device. It also supports full-speed and low-speed modes.
1.2.8
UARTs
The device has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock,
eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O
functions.
1.2.9
I2C Bus
The I2C bus is an industry-standard, two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange
and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications
over a short distance between many devices.
1.2.10 QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability.
It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.
1.2.11 Fast ADC
The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding
separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.
The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly
until manually stopped.
The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight
channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a
scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This
configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low
threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.12 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the device. Each
module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to
operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected,
it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual
timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode.
Timer events may optionally cause interrupt requests or DMA transfers.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
10
Family Configurations
1.2.13 General Purpose Timer (GPT)
The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a
seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare.
Additionally, channel three, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
The input capture and output compare functions allow simultaneous input waveform measurements and output waveform
generation. The input capture function can capture the time of a selected transition edge. The output compare function can
generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a
gated time accumulator.
1.2.14 Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal
processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running
down-counter.
1.2.15 Real-Time Clock (RTC)
The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt
functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions
along with an alarm interrupt.
1.2.16 Pulse-Width Modulation (PWM) Timers
The device has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated
counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to
100%. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs.
For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated
to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.
1.2.17 Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running
down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
1.2.18 Phase-Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced
frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL,
crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
1.2.19 Interrupt Controller (INTC)
The device has a single interrupt controller that supports up to 63 interrupt sources. There are 56 programmable sources, 49 of
which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for
software interrupt requests.
MCF52223 ColdFire Microcontroller, Rev. 3
11
Freescale Semiconductor
Family Configurations
1.2.20 DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor
intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered
by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.
1.2.21 Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what
caused the last reset. There are seven sources of reset:
•
•
•
•
•
•
•
External reset input
Power-on reset (POR)
Watchdog timer
Phase locked-loop (PLL) loss of lock
PLL loss of clock
Software
Low-voltage detector (LVD)
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags
indicating the last source of reset and a control bit for software assertion of the RSTO pin.
1.2.22 GPIO
Nearly all pins on the device have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all
eight bits. Each port has registers that configure, monitor, and control the port pin.
1.2.23 Part Numbers and Packaging
This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office for up-to-date RoHS
information.
Table 3. Orderable Part Number Summary
Freescale Part
Number
Speed Flash/SRAM
Temp range
Description
Package
(MHz)
(Kbytes)
(C)
MCF52221CAE66
MCF52221CVM66
MCF52221CAF66
MCF52221CVM80
MCF52221CAF80
MCF52223CVM66
MCF52223CAF66
MCF52223CVM80
MCF52223CAF80
MCF52221 Microcontroller
MCF52221 Microcontroller
MCF52221 Microcontroller
MCF52221 Microcontroller
MCF52221 Microcontroller
MCF52223 Microcontroller
MCF52223 Microcontroller
MCF52223 Microcontroller
MCF52223 Microcontroller
66
66
66
80
80
66
66
80
80
128/16
128/16
128/16
128/16
128/16
128/16
128/16
128/16
128/16
64 LQFP
81 MAPBGA
100 LQFP
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
81 MAPBGA
100 LQFP
81 MAPBGA
100 LQFP
81 MAPBGA
100 LQFP
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
12
Family Configurations
Figure 5 shows the pinout configuration for the 100 LQFP.
V
V
V
V
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DD
SS
DD
DDPLL
V
EXTAL
XTAL
V
SS
URTS1
TEST
SSPLL
UCTS0
URXD0
UTXD0
URTS0
SCL
PST3
PST2
V
V
DD
SS
9
PST1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDA
QSPI_CS3
QSPI_CS2
PST0
PSTCLK
GPT3
100 LQFP
V
V
USB
DD
DD
V
USB_DM
USB_DP
SS
QSPI-DIN
QSPI_DOUT
QSPI_CLK
QSPI_CS1
QSPI_CS0
RCON
V
USB
SS
GPT2
V
DD
V
V
SS
STBY
V
DD
AN4
AN5
AN6
AN7
V
DD
V
SS
V
SS
Figure 2. 100 LQFP Pin Assignments
MCF52223 ColdFire Microcontroller, Rev. 3
13
Freescale Semiconductor
Family Configurations
Figure 4 shows the pinout configuration for the 81 MAPBGA.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS
UTXD1
RSTI
IRQ5
IRQ3
ALLPST
TDO
TMS
VDDPLL
VSSPLL
GPT3
PWM5
VSTBY
AN5
VSS
URTS1
UCTS0
URXD0
SCL
URXD1
TEST
RSTO
UCTS1
URTS0
VDD
IRQ6
IRQ7
VSS
IRQ2
IRQ4
TRST
IRQ1
VSS
TDI
TCLK
PWM7
VDD
EXTAL
XTAL
GPT2
GPT1
AN4
UTXD0
SDA
VDD
VDD
VDD
VDD
QSPI_CS3
QSPI_CS2
QSPI_DIN
RCON
DTIN3
VSS
VDD
VSS
GPT0
AN3
G
H
J
QSPI_DOUT QSPI_CLK
DTIN1
DTIN0
PWM3
CLKMOD0
CLKMOD1
PWM1
AN2
AN1
AN0
AN6
QSPI_CS0
VSS
QSPI_CS1
JTAG_EN
VSSA
VDDA
AN7
DTIN2
VRL
VRH
VSSA
Figure 3. 81 MAPBGA Pin Assignments
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
14
Family Configurations
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS
URTS1
UCTS0
URXD0
SCL
UTXD1
RSTI
IRQ5
IRQ3
ALLPST
TDO
TMS
VSS
URXD1
TEST
RSTO
UCTS1
URTS0
VDD
IRQ6
IRQ7
VSS
IRQ2
IRQ4
TRST
IRQ1
VSS
TDI
TCLK
GPT3
VDD
VDDPLL
VSSPLL
VDDUSB
GPT2
VSTBY
AN5
EXTAL
XTAL
UTXD0
SDA
VDD
USB_DM
USB_DP
AN4
VDD
VDD
VDD
QSPI_CS3
QSPI_CS2
QSPI_DIN
RCON
DTIN3
VSS
VDD
VSS
VSSUSB
AN3
G
H
J
QSPI_DOUT QSPI_CLK
DTIN1
DTIN0
GPT1
CLKMOD0
CLKMOD1
GPT0
AN2
AN1
AN0
AN6
QSPI_CS0
VSS
QSPI_CS1
JTAG_EN
VSSA
VDDA
AN7
DTIN2
VRL
VRH
VSSA
Figure 4. 81 MAPBGA Pin Assignments
MCF52223 ColdFire Microcontroller, Rev. 3
15
Freescale Semiconductor
Table 13 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin.
Table 4. Pin Functions by Primary and Alternate Purpose
Drive
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Function
Quaternary
Function
Slew Rate / Pull-up /
Pin on
Pin on 81
MAPBGA
Pin on 64
LQFP
Strength /
Control1 Pull-down2 100 LQFP
Control1
ADC
AN7
AN6
—
—
—
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
—
Low
Low
FAST
FAST
FAST
FAST
FAST
FAST
FAST
FAST
N/A
—
—
51
H9
G9
G8
F9
33
34
35
36
28
27
26
25
—
—
32
29
31
30
47
46
48
45
55
—
—
8
—
52
AN5
—
—
Low
—
53
AN4
—
—
Low
—
54
AN3
—
—
Low
—
46
G7
G6
H6
J6
AN2
—
—
Low
—
45
AN1
—
—
Low
—
44
AN0
—
—
Low
—
43
SYNCA3
SYNCB3
VDDA
VSSA
VRH
—
—
N/A
—
—
—
—
—
—
N/A
N/A
—
—
—
—
—
—
N/A
N/A
—
50
H8
H7, J9
J8
—
—
—
N/A
N/A
—
47
—
—
—
N/A
N/A
—
49
VRL
—
—
—
N/A
N/A
—
48
J7
Clock
Generation
EXTAL
XTAL
—
—
—
N/A
N/A
—
73
B9
C9
B8
C8
A6
—
—
—
—
N/A
N/A
—
72
VDDPLL
VSSPLL
ALLPST
DDATA[3:0]
PST[3:0]
SCL
—
—
—
N/A
N/A
—
74
—
—
—
—
N/A
N/A
—
71
Debug Data
—
—
High
High
High
PDSR[0]
PDSR[0]
FAST
FAST
FAST
PSRR[0]
PSRR[0]
—
86
84,83,78,77
70,69,66,65
10
—
—
GPIO
GPIO
GPIO
GPIO
—
—
—
—
—
I2C
USB_DMI
USB_DPI
UTXD2
URXD2
pull-up4
pull-up4
E1
E2
SDA
11
9
Table 4. Pin Functions by Primary and Alternate Purpose (continued)
Drive
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Quaternary
Function
Slew Rate / Pull-up /
Pin on
Pin on 81
MAPBGA
Pin on 64
LQFP
Strength /
Function
Control1 Pull-down2 100 LQFP
Control1
Interrupts
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
—
—
—
—
—
—
—
—
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Low
Low
Low
Low
Low
Low
High
FAST
FAST
FAST
FAST
FAST
FAST
FAST
—
—
95
94
91
90
89
88
87
C4
B4
A4
C5
A5
B5
C6
58
—
—
57
—
—
56
—
—
—
—
—
—
—
—
SYNCA
USB_ALT_CL
K
pull-up4
JTAG/BDM
JTAG_EN
—
—
—
—
—
N/A
N/A
pull-down
pull-up5
26
64
J2
17
44
TCLK/
CLKOUT
High
FAST
C7
PSTCLK
TDI/DSI
—
—
—
—
—
—
—
—
—
N/A
High
N/A
N/A
FAST
N/A
pull-up5
—
79
80
76
B7
A7
A8
50
51
49
TDO/DSO
TMS
pull-up5
/BKPT
TRST
—
—
—
N/A
N/A
pull-up5
85
B6
54
/DSCLK
Mode
CLKMOD0
CLKMOD1
—
—
—
—
—
—
—
—
—
N/A
N/A
N/A
N/A
N/A
N/A
pull-down6
pull-down6
pull-up
40
39
21
G5
H5
G3
24
—
16
Selection6
RCON/
EZPCS
Table 4. Pin Functions by Primary and Alternate Purpose (continued)
Drive
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Quaternary
Function
Slew Rate / Pull-up /
Pin on
Pin on 81
MAPBGA
Pin on 64
LQFP
Strength /
Function
Control1 Pull-down2 100 LQFP
Control1
QSPI
QSPI_DIN/
EZPD
—
—
URXD1
UTXD1
URTS1
—
GPIO
GPIO
GPIO
GPIO
GPIO
PDSR[2]
PDSR[1]
PDSR[3]
PDSR[7]
PDSR[6]
PSRR[2]
PSRR[1]
PSRR[3]
—
—
16
17
18
12
13
F3
G1
G2
F1
F2
12
13
14
—
—
QSPI_DOUT/
EZPQ
QSPI_CLK/
EZPCK
SCL
SYNCA
—
pull-up8
QSPI_CS3
PSRR[7] pull-up/pull-
down7
QSPI_CS2
—
PSRR[6] pull-up/pull-
down7
QSPI_CS1
QSPI_CS0
RSTI
—
—
UCTS1
—
GPIO
GPIO
—
PDSR[5]
PDSR[4]
N/A
PSRR[5]
PSRR[4]
N/A
—
pull-up8
pull-up9
—
19
20
96
97
5
H2
H1
A3
B3
C2
—
15
59
60
3
SDA
Reset9
—
RSTO
—
—
—
high
FAST
N/A
Test
TEST
—
—
—
N/A
pull-down
pull-up10
pull-up10
pull-up10
pull-up10
—
Timers, 16-bit
GPT3
—
—
PWM7
PWM5
PWM3
PWM1
PWM6
PWM4
PWM2
PWM0
—
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PDSR[23] PSRR[23]
PDSR[22] PSRR[22]
PDSR[21] PSRR[21]
PDSR[20] PSRR[20]
PDSR[19] PSRR[19]
PDSR[18] PSRR[18]
PDSR[17] PSRR[17]
PDSR[16] PSRR[16]
PDSR[11] PSRR[11]
PDSR[10] PSRR[10]
63
58
33
38
32
31
37
36
6
—
—
—
—
19
18
23
22
4
GPT2
E8
J4
GPT1
—
GPT0
—
J5
Timers, 32-bit
DTIN3
DTIN2
DTIN1
DTIN0
UCTS0
URTS0
URXD0
UTXD0
DTOUT3
DTOUT2
DTOUT1
DTOUT0
—
H3
J3
—
—
G4
H4
C1
D3
D1
D2
—
UART 0
—
—
—
—
9
7
—
—
PDSR[9]
PDSR[8]
PSRR[9]
PSRR[8]
—
7
5
—
—
—
8
6
Table 4. Pin Functions by Primary and Alternate Purpose (continued)
Drive
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Quaternary
Function
Slew Rate / Pull-up /
Pin on
Pin on 81
MAPBGA
Pin on 64
LQFP
Strength /
Function
Control1 Pull-down2 100 LQFP
Control1
UART 1
UCTS1
URTS1
URXD1
UTXD1
UCTS2
URTS2
URXD2
UTXD2
VSTBY
VDDUSB
VSSUSB
USB_DM
USB_DP
VDD
SYNCA
SYNCB
—
URXD2
UTXD2
—
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
—
PDSR[15] PSRR[15]
PDSR[14] PSRR[14]
PDSR[13] PSRR[13]
PDSR[12] PSRR[12]
PDSR[27] PSRR[27]
PDSR[26] PSRR[26]
PDSR[25] PSRR[25]
PDSR[24] PSRR[24]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
98
4
C3
B1
B2
A2
—
61
2
100
99
27
30
28
29
55
62
59
61
60
63
62
—
—
—
—
37
43
40
42
41
—
—
UART 2
—
—
—
—
—
—
—
—
—
—
—
VSTBY
USB
—
—
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
F8
D8
F7
D9
E9
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
—
—
—
1,2,14,22,
23,34,41,
57,68,81,93
D5,E3–E7, 1,10,20,39,5
F5
2
VSS
—
—
—
N/A
N/A
—
3,15,24,25,3 A1,A9,D4,D 11,21,38,
5,42,56,
6,F4,F6,J1
53,64
67,75,82,92
1
The PDSR and PSSR registers are described in the General Purpose I/O chapter. All programmable signals default to 2 mA drive and FAST slew rate in
normal (single-chip) mode.
All signals have a pull-up in GPIO mode.
These signals are multiplexed on other pins.
2
3
4
5
6
7
For primary and GPIO functions only.
Only when JTAG mode is enabled.
CLKMOD0 and CLKMOD1 have internal pull-down resistors; however, the use of external resistors is very strongly recommended.
When these pins are configured for USB signals, they should use the USB transceiver’s internal pull-up/pull-down resistors (see the description of the
OTG_CTRL register). If these pins are not configured for USB signals, each pin should be pulled down externally using a 10 k resistor.
For secondary and GPIO functions only.
RSTI has an internal pull-up resistor; however, the use of an external resistor is very strongly recommended.
8
9
10 For GPIO function. Primary Function has pull-up control within the GPT module.
Family Configurations
1.3
Reset Signals
Table 5 describes signals used to reset the chip or as a reset indication.
Table 5. Reset Signals
Signal Name
Abbreviation
Function
I/O
Reset In
RSTI
Primary reset input to the device. Asserting RSTI for at least 8 CPU
clock cycles immediately resets the CPU and peripherals.
I
Reset Out
RSTO
Driven low for 1024 CPU clocks after the reset source has deasserted.
O
1.4
PLL and Clock Signals
Table 6 describes signals used to support the on-chip clock generation circuitry.
Table 6. PLL and Clock Signals
Signal Name
Abbreviation
Function
I/O
External Clock In
EXTAL
Crystal oscillator or external clock input except when the on-chip
relaxation oscillator is used.
I
Crystal
XTAL
Crystal oscillator output except when CLKMOD0=0, then sampled as
part of the clock mode selection mechanism.
O
O
Clock Out
CLKOUT
This output signal reflects the internal system clock.
1.5
Mode Selection
Table 7 describes signals used in mode selection; Table 8 describes the particular clocking modes.
Table 7. Mode Selection Signals
Signal Name
Abbreviation
Function
I/O
Clock Mode Selection CLKMOD[1:0] Selects the clock boot mode.
I
Reset Configuration
Test
RCON
TEST
The Serial Flash Programming mode is entered by asserting the
RCON pin (with the TEST pin negated) as the chip comes out of
reset. During this mode, the EzPort has access to the flash memory
which can be programmed from an external device.
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of
test functions.
I
Table 8. Clocking Modes
Configure the clock mode.
CLKMOD[1:0]
XTAL
00
00
01
10
10
11
0
1
PLL disabled, clock driven by external oscillator
PLL disabled, clock driven by on-chip oscillator
PLL disabled, clock driven by crystal
N/A
0
PLL in normal mode, clock driven by external oscillator1
Reserved2
1
N/A
PLL in normal mode, clock driven by crystal1
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
21
Family Configurations
1
The PLL pre-divider (CCHR+1) reset value is 6 and the PLL input reference range is 2–10 MHz,
so in order to boot with the PLL enabled, the external clock or crystal frequency needs to be
greater than 12 MHz. MCF5222x devices cannot boot with PLL enabled from an external clock
or crystal oscillator with frequency less than 12 MHz. This constraint does not apply to booting
with PLL disabled.
2
Cannot boot from the Internal 8 MHz Relaxation oscillator with the PLL enabled. Refer Note1.
Thus this mode has been removed from the table.
1.6
External Interrupt Signals
Table 9 describes the external interrupt signals.
Table 9. External Interrupt Signals
Signal Name
Abbreviation
Function
I/O
External Interrupts
IRQ[7:1]
External interrupt sources.
I
1.7
Queued Serial Peripheral Interface (QSPI)
Table 10 describes the QSPI signals.
Table 10. Queued Serial Peripheral Interface (QSPI) Signals
Abbreviation Function
Signal Name
I/O
QSPI Synchronous
Serial Output
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
I
QSPI Serial Clock
QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
O
O
SynchronousPeripheral QSPI_CS[3:0] QSPI peripheral chip select; can be programmed to be active high or
Chip Selects
low.
1.8
USB On-the-Go
This device is compliant with industry standard USB 2.0 specification.
2
1.9
I C I/O Signals
2
Table 11 describes the I C serial interface module signals.
2
Table 11. I C I/O Signals
Function
Signal Name
Abbreviation
I/O
Serial Clock
SCLn
Open-drain clock signal for the for the I2C interface. When the bus is
In master mode, this clock is driven by the I2C module; when the bus
is in slave mode, this clock becomes the clock input.
I/O
Serial Data
SDAn
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
MCF52223 ColdFire Microcontroller, Rev. 3
22
Freescale Semiconductor
Family Configurations
1.10 UART Module Signals
Table 12 describes the UART module signals.
Table 12. UART Module Signals
Function
Signal Name
Abbreviation
I/O
Transmit Serial Data
Output
UTXDn
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, LSB first, on this pin at
the falling edge of the serial clock source.
O
Receive Serial Data
Input
URXDn
Receiver serial data inputs for the UART modules. Data is received on
this pin LSB first. When the UART clock is stopped for power-down
mode, any transition on this pin restarts the clock.
I
Clear-to-Send
UCTSn
URTSn
Indication to the UART modules that they can begin data
transmission.
I
Request-to-Send
Automatic request-to-send outputs from the UART modules. This
signal can also be configured to be asserted and negated as a
function of the RxFIFO level.
O
1.11 DMA Timer Signals
Table 13 describes the signals of the four DMA timer modules.
Table 13. DMA Timer Signals
Function
Signal Name
Abbreviation
I/O
DMA Timer Input
DTIN
Event input to the DMA timer modules.
I
DMA Timer Output
DTOUT
Programmable output from the DMA timer modules.
O
1.12 ADC Signals
Table 14 describes the signals of the Analog-to-Digital Converter.
Table 14. ADC Signals
Signal Name
Abbreviation
Function
I/O
Analog Inputs
AN[7:0]
VRH
Inputs to the analog-to-digital converter.
Reference voltage high and low inputs.
I
I
Analog Reference
VRL
I
Analog Supply
VDDA
VSSA
Isolate the ADC circuitry from power supply noise.
—
—
I
ADC Sync Inputs
SYNCA /
SYNCB
These signals can initiate an analog-to-digital conversion
process.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
23
Family Configurations
1.13 General Purpose Timer Signals
Table 15 describes the general purpose timer signals.
Table 15. GPT Signals
Signal Name
Abbreviation
Function
Inputs to or outputs from the general purpose timer module.
I/O
I/O
General Purpose Timer
Input/Output
GPT[3:0]
1.14 Pulse Width Modulator Signals
Table 16 describes the PWM signals.
Table 16. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channels
PWM[7:0] Pulse width modulated output for PWM channels.
O
1.15 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and the BDM logic.
Table 17. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
JTAG Enable
Test Reset
JTAG_EN
TRST
Select between debug module and JTAG signals at reset.
I
I
This active-low signal is used to initialize the JTAG logic
asynchronously.
Test Clock
TCLK
TMS
Used to synchronize the JTAG logic.
I
I
Test Mode Select
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
BKPT
Development Serial Clock - Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
I
Breakpoint
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the
value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality),
asserting BKPT generates a debug interrupt exception in the
processor.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
24
Family Configurations
Signal Name
Table 17. Debug Support Signals (continued)
Abbreviation
Function
I/O
Development Serial
Input
DSI
Development Serial Input - Internally synchronized input that provides
data input for the serial communication port to the debug module, after
the DSCLK has been seen as high (logic 1).
I
Development Serial
Output
DSO
Development Serial Output - Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
O
O
O
Debug Data
DDATA[3:0] Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
Processor Status Clock
PSTCLK
Processor Status Clock - Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
Processor Status
Outputs
PST[3:0]
ALLPST
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
O
O
All Processor Status
Outputs
Logical AND of PST[3:0]. The CLKOUT signal can be used by the
development system to know when to sample ALLPST.
1.16 EzPort Signal Descriptions
Table 18 contains a list of EzPort external signals.
Table 18. EzPort Signal Descriptions
Abbreviation Function
EZPCK Shift clock for EzPort transfers.
Signal Name
I/O
EzPort Clock
I
I
EzPort Chip Select
EZPCS
EZPD
EZPQ
Chip select for signalling the start and end of
serial transfers.
EzPort Serial Data In
EzPort Serial Data Out
EZPD is sampled on the rising edge of
EZPCK.
I
EZPQ transitions on the falling edge of
EZPCK.
O
MCF52223 ColdFire Microcontroller, Rev. 3
25
Freescale Semiconductor
Family Configurations
1.17 Power and Ground Pins
The pins described in Table 19 provide system power and ground to the chip. Multiple pins are provided for adequate current
capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.
Table 19. Power and Ground Pins
Signal Name
Abbreviation
Function
PLL Analog Supply
VDDPLL,
VSSPLL
Dedicated power supply signals to isolate the sensitive PLL analog
circuitry from the normal levels of noise present on the digital power
supply.
USB Power Supply
USB Ground Supply
Positive Supply
Ground
VDDUSB
This pin supplies power to the USB Module.
V
SSUSB
VDD
This pin is the negative (ground) supply pin for the USB Module.
These pins supply positive power to the core logic.
This pin is the negative supply (ground) to the chip.
VSS
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
26
Electrical Characteristics
2
Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the microcontroller unit, including
detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
2.1
Maximum Ratings
1, 2
Table 20. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
VDDPLL
VSTBY
VDDUSB
VIN
–0.3 to 4.0
–0.3 to 4.0
–0.3 to 4.0
–0.3 to 4.0
–0.3 to 4.0
0 to 3.3
V
V
Clock synthesizer supply voltage
RAM standby supply voltage
USB standby supply voltage
Digital input voltage 3
V
V
V
EXTAL pin voltage
VEXTAL
VXTAL
IDD
V
XTAL pin voltage
0 to 3.3
V
Instantaneous maximum current
25
mA
Single pin limit (applies to all pins)4, 5
Operating temperature range (packaged)
TA
(TL - TH)
–40 to 856
C
C
Storage temperature range
Tstg
–65 to 150
1
2
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond
those listed may affect device reliability or cause permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher
than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic voltage level (VSS or VDD).
3
Input must be current limited to the IDD value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then
use the larger of the two values.
4
5
All functional non-supply pins are internally clamped to VSS and VDD
.
The power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the
injection current may flow out of VDD and could result in the external power supply going out of
regulation. Ensure that the external VDD load shunts current greater than maximum injection current.
This is the greatest risk when the MCU is not consuming power (e.g., no clock).
6
Depending on the packaging; see the orderable part number summary.
MCF52223 ColdFire Microcontroller, Rev. 3
27
Freescale Semiconductor
Electrical Characteristics
2.2
Current Consumption
Table 21, Table 22, and Figure 5 show the typical current consumption in low-power modes.
Table 21. Current Consumption in Low-Power Mode, Code From Flash Memory
1,2,3
Mode
8 MHz (Typ)
16 MHz (Typ)
0.070
2.9
64 MHz (Typ)
80 MHz (Typ)
Units
Stop mode 3 (Stop 11)4
Stop mode 2 (Stop 10)4
Stop mode 1 (Stop 01)4,5
Stop mode 0 (Stop 00)5
Wait / Doze
mA
3.6
3.6
3.9
3.9
6
6
6.7
6.7
13
23
38
44
Run
TBD
TBD
TBD
TBD
1
All values are measured with a 3.30V power supply. Tests performed at room temperature.
2
3
4
5
Refer to the Power Management chapter in the MCF52223 Reference Manual for more information on
low-power modes.
CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 and CFM off before entering
low-power mode. CLKOUT is disabled.
See the description of the Low-Power Control Register (LPCR) in the MCF52223 Reference Manual for
more information on stop modes 0–3.
Results are identical to STOP 00 for typical values because they only differ by CLKOUT power
consumption. CLKOUT is already disabled in this instance prior to entering low-power mode.
1,2,3
Table 22. Current Consumption in Low-Power Mode, Code From SRAM
Mode
8 MHz (Typ)
16 MHz (Typ)
0.010
2.7
64 MHz (Typ)
80 MHz (Typ)
Units
Stop mode 3 (Stop 11)4
Stop mode 2 (Stop 10)4
Stop mode 1 (Stop 01)4,5
Stop mode 0 (Stop 00)5
Wait / Doze
mA
3.4
3.4
6
3.7
3.7
8
5.8
5.8
22
6.5
6.5
27
Run
7
11
33
41
1
2
All values are measured with a 3.30V power supply. Tests performed at room temperature.
Refer to the Power Management chapter in the MCF52223 Reference Manual for more information on
low-power modes.
CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 off before entering low-power
mode. CLKOUT is disabled. Code executed from SRAM with flash memory shut off by writing 0x0 to the
FLASHBAR register.
See the description of the Low-Power Control Register (LPCR) in the MCF52223 Reference Manual for
more information on stop modes 0–3.
3
4
5
Results are identical to STOP 00 for typical values because they only differ by CLKOUT power
consumption. CLKOUT is already disabled in this instance prior to entering low-power mode.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
28
Electrical Characteristics
Figure 5. Plot of Current Consumption in Low-Power Modes
Table 23. Typical Active Current Consumption Specifications
Typical1
Active
(SRAM)
Typical1
Active
(Flash)
Peak2
Active
(Flash)
Characteristic
Symbol
Unit
8 MHz core & I/O
IDD
8
11
19
44
52
18
33
82
98
mA
16 MHz core & I/O
64 MHz core & I/O
80 MHz core & I/O
RAM standby supply current
11
35
43
ISTBY
A
mA
mA
•
•
•
Normal operation: VDD > VSTBY - 0.3 V
Transient condition: VSTBY - 0.3 V > VDD > VSS + 0.5 V
Standby operation: VDD < VSS + 0.5 V
—
—
—
0.4
TBD
16
Analog supply current
• Normal operation
• Standby mode
IDDA
2(see note 3)
13
TBD
0
—
—
• Powered down
USB supply current
PLL supply current
IDDUSB
IDDPLL
—
—
2
6(see note 4) mA
1
2
3
4
Tested at room temperature with CPU polling a status register. All clocks were off except the UART and CFM (when
running from flash memory).
Peak current measured with all modules active, CPU polling a status register, and default drive strength with matching
load.
Tested using Auto Power Down (APD), which powers down the ADC between conversions; ADC running at 4 MHz in
Once Parallel mode with a sample rate of 3 kHz.
Tested with the PLL MFD set to 7 (max value). Setting the MFD to a lower value results in lower current consumption.
MCF52223 ColdFire Microcontroller, Rev. 3
29
Freescale Semiconductor
Electrical Characteristics
2.3
Thermal Characteristics
Table 24 lists thermal resistance values.
Table 24. Thermal Characteristics
Characteristic
Symbol
Value
Unit
100 LQFP Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to ambient, (@200 ft/min)
Junction to ambient, (@200 ft/min)
Junction to board
Single layer board (1s)
JA
JA
JMA
JMA
JB
JC
jt
531,2
391,3
421,3
331,3
254
C/W
C/W
C/W
C/W
C/W
C/W
C/W
oC
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
Junction to case
—
95
Junction to top of package
Natural convection
26
Maximum operating junction temperature
81 MAPBGA Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to ambient, (@200 ft/min)
Junction to ambient, (@200 ft/min)
Junction to board
—
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
Tj
105
611,2
352,3
502,3
312,3
204
JA
JA
JMA
JMA
JB
JC
jt
C/W
C/W
C/W
C/W
C/W
C/W
C/W
oC
Junction to case
—
125
Junction to top of package
Natural convection
—
26
Maximum operating junction temperature
Tj
105
621,2
431,3
501,3
361,3
264
64 LQFP
Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to ambient (@200 ft/min)
Junction to ambient (@200 ft/min)
Junction to board
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
JA
JA
JMA
JMA
JB
JC
jt
C/W
C/W
C/W
C/W
C/W
C/W
C/W
oC
Junction to case
—
95
Junction to top of package
Natural convection
—
26
Maximum operating junction temperature
Tj
105
1
JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of JA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the jt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
2
3
4
Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
30
Electrical Characteristics
6
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
(1)
TJ = TA + PD JMA
Where:
TA
= ambient temperature, C
JA
PD
= package thermal resistance, junction-to-ambient, C/W
= PINT PI/O
PINT
PI/O
= chip internal power, IDD VDD, watts
= power dissipation on input and output pins — user determined, watts
For most applications PI/O PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K TJ + 273C
(2)
Solving equations 1 and 2 for K gives:
K = PD (TA + 273 C) + JMA PD
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for
any value of TA.
2.4
Flash Memory Characteristics
The flash memory characteristics are shown in Table 25 and Table 26.
Table 25. SGFM Flash Program and Erase Characteristics
(VDD = 3.0 to 3.6 V)
Parameter
System clock (read only)
System clock (program/erase)2
Symbol
Min
Typ
Max
Unit
fsys(R)
0
—
—
66.67 or 801
66.67 or 801
MHz
MHz
fsys(P/E)
0.15
1
2
Depending on packaging; see the orderable part number summary.
Refer to the flash memory section for more information
Table 26. SGFM Flash Module Life Characteristics
(VDD = 3.0 to 3.6 V)
Parameter
Symbol
Value
Unit
Maximum number of guaranteed program/erase cycles1 before failure
P/E
10,0002
10
Cycles
Years
Data retention at average operating temperature of 85C
Retention
1
A program/erase cycle is defined as switching the bits from 1 0 1.
Reprogramming of a flash memory array block prior to erase is not required.
2
MCF52223 ColdFire Microcontroller, Rev. 3
31
Freescale Semiconductor
Electrical Characteristics
2.5
EzPort Electrical Specifications
Table 27. EzPort Electrical Specifications
Name
Characteristic
Min
Max
Unit
EP1
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EPCK frequency of operation (all commands except READ)
EPCK frequency of operation (READ command)
EPCS_b negation to next EPCS_b assertion
EPCS_B input valid to EPCK high (setup)
EPCK high to EPCS_B input invalid (hold)
EPD input valid to EPCK high (setup)
—
fsys / 2
MHz
MHz
ns
—
f
sys / 8
—
2 × Tcyc
5
5
—
ns
—
ns
2
—
ns
EPCK high to EPD input invalid (hold)
5
—
ns
EPCK low to EPQ output valid (out setup)
EPCK low to EPQ output invalid (out hold)
EPCS_B negation to EPQ tri-state
—
0
12
—
ns
ns
—
12
ns
2.6
ESD Protection
1, 2
Table 28. ESD Protection Characteristics
Characteristics
Symbol
Value
Units
ESD target for Human Body Model
ESD target for Machine Model
HBM circuit description
HBM
MM
2000
200
1500
100
0
V
V
Rseries
C
Rseries
C
pF
MM circuit description
200
pF
—
Number of pulses per pin (HBM)
• Positive pulses
• Negative pulses
—
—
1
1
Number of pulses per pin (MM)
• Positive pulses
• Negative pulses
—
—
—
3
3
Interval of pulses
—
1
sec
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer
meets the device specification requirements. Complete DC parametric and functional
testing is performed per applicable device specification at room temperature followed by
hot temperature, unless specified otherwise in the device specification.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
32
Electrical Characteristics
2.7
DC Electrical Specifications
1
Table 29. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDD
VSTBY
VIH
3.0
1.8
3.6
3.6
V
V
Standby voltage
Input high voltage
0.7 VDD
VSS – 0.3
0.06 VDD
2.15
4.0
V
Input low voltage
VIL
0.35 VDD
—
V
Input hysteresis2
VHYS
VLVD
VLVDHYS
Iin
mV
V
Low-voltage detect trip voltage (VDD falling)
Low-voltage detect hysteresis (VDD rising)
Input leakage current
2.3
60
120
mV
A
–1.0
1.0
Vin = VDD or VSS, digital pins
Output high voltage (all input/output and all output pins)
IOH = –2.0 mA
VOH
VOL
VOH
VOL
VOH
VOL
VDD – 0.5
—
—
0.5
—
V
V
V
V
V
V
Output low voltage (all input/output and all output pins)
IOL = 2.0mA
Output high voltage (high drive)
IOH = -5 mA
VDD – 0.5
—
Output low voltage (high drive)
IOL = 5 mA
0.5
—
Output high voltage (low drive)
IOH = -2 mA
VDD - 0.5
—
Output low voltage (low drive)
IOL = 2 mA
0.5
–130
Weak internal pull Up device current, tested at VIL Max.3
IAPU
Cin
–10
A
Input Capacitance 4
pF
• All input-only pins
• All input/output (three-state) pins
—
—
7
7
1
Refer to Table 30 for additional PLL specifications.
2
Only for pins: IRQ1, IRQ2. IRQ3, IRQ4, IRQ5, IRQ6. IRQ7, RSTIN_B, RCON_B, PCS0, SCK, I2C_SDA, I2C_SCL,
TCLK, TRST_B
3
4
Refer to Table 13 for pins having internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
MCF52223 ColdFire Microcontroller, Rev. 3
33
Freescale Semiconductor
Electrical Characteristics
2.8
Clock Source Electrical Specifications
Table 30. Oscillator and PLL Electrical Specifications
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Symbol
Min
Max
Unit
Clock Source Frequency Range of EXTAL Frequency Range
MHz
• Crystal
fcrystal
fext
1
0
25.02
66.67 or 80
• External1
PLL reference frequency range
fref_pll
fsys
2
10.0
MHz
MHz
System frequency 3
• External clock mode
• On-chip PLL frequency
0
66.67 or 804
66.67 or 804
f
ref / 32
Loss of reference frequency 5, 7
Self clocked mode frequency 6
Crystal start-up time 7, 8
fLOR
fSCM
tcst
100
1
1000
5
kHz
MHz
ms
—
10
EXTAL input high voltage
• External reference
VIHEXT
V
2.0
3.02
EXTAL input low voltage
• External reference
VILEXT
V
VSS
—
0.8
500
60
PLL lock time4,9
tlpll
tdc
s
Duty cycle of reference 4
Frequency un-LOCK range
Frequency LOCK range
40
% fref
% fref
% fref
fUL
–1.5
–0.75
1.5
fLCK
Cjitter
0.75
CLKOUT period jitter 4, 5, 10 ,11, measured at fSYS Max
• Peak-to-peak (clock edge to clock edge)
• Long term (averaged over 2 ms interval)
—
—
10
.01
% fsys
MHz
On-chip oscillator frequency
foco
7.84
8.16
1
2
3
4
5
6
In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.
This value has been updated.
All internal registers retain data at 0 Hz.
Depending on packaging; see the orderable part number summary.
Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below fLOR with
default MFD/RFD settings.
7
8
9
This parameter is characterized before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage
for a given interval.
11 Based on slow system clock of 40 MHz measured at fsys max.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
34
Electrical Characteristics
2.9
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, Interrupt and USB interfaces. When in GPIO
mode, the timing specification for these pins is given in Table 31 and Figure 6.
The GPIO timing is met under the following load test conditions:
•
•
50 pF / 50 for high drive
25 pF / 25 for low drive
Table 31. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1
G2
G3
G4
CLKOUT High to GPIO Output Valid
CLKOUT High to GPIO Output Invalid
GPIO Input Valid to CLKOUT High
CLKOUT High to GPIO Input Invalid
tCHPOV
tCHPOI
tPVCH
tCHPI
—
1.5
9
10
—
—
—
ns
ns
ns
ns
1.5
CLKOUT
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 6. GPIO Timing
2.10 Reset Timing
Table 32. Reset and Configuration Override Timing
(VDD = 3.0 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM
Characteristic
Symbol
Min
Max
Unit
R1 RSTI input valid to CLKOUT High
R2 CLKOUT High to RSTI Input invalid
R3 RSTI input valid time 2
tRVCH
tCHRI
9
1.5
5
—
—
—
10
ns
ns
tRIVT
tCYC
ns
R4 CLKOUT High to RSTO Valid
tCHROV
—
1
2
All AC timing is shown with respect to 50% VDD levels unless otherwise noted.
During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the
system. Thus, RSTI must be held a minimum of 100 ns.
MCF52223 ColdFire Microcontroller, Rev. 3
35
Freescale Semiconductor
Electrical Characteristics
CLKOUT
RSTI
1R1
R2
R3
R4
R4
RSTO
Figure 7. RSTI and Configuration Override Timing
2
2.11 I C Input/Output Timing Specifications
2
Table 33 lists specifications for the I C input timing parameters shown in Figure 8.
2
Table 33. I C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
11
I2
I3
I4
I5
I6
I7
I8
I9
2 tCYC
8 tCYC
—
—
—
1
ns
ns
ms
ns
ms
ns
ns
ns
ns
Clock low period
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
0
—
1
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4 tCYC
0
—
—
—
—
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
2 tCYC
2 tCYC
2
Table 34 lists specifications for the I C output timing parameters shown in Figure 8.
2
Table 34. I C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
111 Start condition hold time
6 tCYC
10 tCYC
—
—
—
—
ns
ns
s
I21
I32
Clock low period
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
I41
I53
Data hold time
7 tCYC
—
3
ns
ns
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—
I61
I71
I81
Clock high time
Data setup time
10 tCYC
2 tCYC
—
—
—
ns
ns
ns
Start condition setup time (for repeated start
condition only)
20 tCYC
I91
Stop condition setup time
10 tCYC
—
ns
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
36
Electrical Characteristics
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 34. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table 34 are minimum values.
2
3
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
Specified at a nominal 50-pF load.
Figure 8 shows timing for the values in Table 33 and Table 34.
I2
I6
I5
SCL
SDA
I3
I1
I4
I8
I9
I7
2
Figure 8. I C Input/Output Timings
2.12 Analog-to-Digital Converter (ADC) Parameters
Table 35 lists specifications for the analog-to-digital converter.
1
Table 35. ADC Parameters
Name
Characteristic
Low reference voltage
Min
Typical
Max
Unit
VREFL
VREFH
VDDA
VADIN
RES
INL
VSS
VREFL
3.0
—
—
VREFH
VDDA
3.6
V
V
High reference voltage
ADC analog supply voltage
Input voltages
3.3
—
V
VREFL
12
VREFH
12
V
Resolution
—
Bits
LSB3
LSB
LSB
Integral non-linearity (full input signal range)2
Integral non-linearity (10% to 90% input signal range)4
Differential non-linearity
Monotonicity
—
2.5
2.5
3
INL
—
3
DNL
—
–1 < DNL < 1
<1
GUARANTEED
fADIC
RAD
ADC internal clock
0.1
VREFL
—
—
5.0
VREFH
13
MHz
V
Conversion range
—
tADPU
tREC
tADC
tADS
CADI
ADC power-up time5
6
tAIC cycles6
tAIC cycles
tAIC cycles
tAIC cycles
pF
Recovery from auto standby
Conversion time
—
0
1
—
6
—
Sample time
—
1
—
Input capacitance
—
See Figure 9
—
MCF52223 ColdFire Microcontroller, Rev. 3
37
Freescale Semiconductor
Electrical Characteristics
1
Table 35. ADC Parameters (continued)
Name
Characteristic
Min
Typical
Max
Unit
XIN
IADI
Input impedance
—
—
—
—
.99
—
—
—
—
—
9.1
See Figure 9
—
3
W
mA
mA
mV
—
Input injection current7, per pin
—
0
IVREFH VREFH current
—
VOFFSET Offset voltage internal reference
8
15
1.01
9
EGAIN
Gain error (transfer path)
1
VOFFSET Offset voltage external reference
3
mV
dB
SNR
THD
Signal-to-noise ratio
62 to 66
75
—
Total harmonic distortion
Spurious free dynamic range
—
dB
SFDR
67 to 70.3
61 to 63.9
10.6
—
dB
SINAD Signal-to-noise plus distortion
ENOB Effective number of bits
—
dB
—
Bits
1
2
3
4
5
6
7
All measurements are made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground
INL measured from VIN = VREFL to VIN = VREFH
LSB = Least Significant Bit
INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH
Includes power-up of ADC and VREF
ADC clock cycles
Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
2.13 Equivalent Circuit for ADC Inputs
Figure 9 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is
closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2, while
the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function
of the analog input voltage, VREF and the ADC clock frequency.
125W ESD Resistor
8pF noise damping capacitor
3
4
Analog Input
S1
C1
C2
S/H
S3
(VREFH- VREFL)/ 2
S2
2
1
C1 = C2 = 1pF
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
38
Electrical Characteristics
3. Equivalent resistance for the channel select mux; 100 s
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
1
5. Equivalent input impedance, when the input is selected =
(ADC Clock Rate) (1.410-12
)
Figure 9. Equivalent Circuit for A/D Loading
2.14 DMA Timers Timing Specifications
Table 36 lists timer module AC timings.
Table 36. Timer Module AC Timing Specifications
Name
Characteristic1
Min
Max
Unit
T1
T2
DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time
DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width
3 tCYC
1 tCYC
—
—
ns
ns
1
All timing references to CLKOUT are given to its rising edge.
2.15 QSPI Electrical Specifications
Table 37 lists QSPI timings.
Table 37. QSPI Modules AC Timing Specifications
Characteristic
Name
Min
Max
Unit
QS1
QS2
QS3
QS4
QS5
QSPI_CS[3:0] to QSPI_CLK
1
—
2
510
10
—
tCYC
ns
QSPI_CLK high to QSPI_DOUT valid
QSPI_CLK high to QSPI_DOUT invalid (Output hold)
QSPI_DIN to QSPI_CLK (Input setup)
QSPI_DIN to QSPI_CLK (Input hold)
ns
9
—
ns
9
—
ns
The values in Table 37 correspond to Figure 10.
MCF52223 ColdFire Microcontroller, Rev. 3
39
Freescale Semiconductor
Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QSPI_DIN
QS3
QS4
QS5
Figure 10. QSPI Timing
2.16 JTAG and Boundary Scan Timing
Table 38. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK frequency of operation
Symbol
Min
Max
Unit
J1
fJCYC
tJCYC
DC
1/4
—
—
3
fsys/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
J2
TCLK cycle period
4 tCYC
J3
TCLK clock pulse width
tJCW
26
0
J4
TCLK rise and fall times
tJCRF
J5
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI Input data hold time after TCLK rise
TCLK low to TDO data valid
tBSDST
tBSDHT
tBSDV
4
—
—
33
33
—
—
26
8
J6
26
0
J7
J8
tBSDZ
0
J9
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
4
J10
J11
J12
J13
J14
10
0
TCLK low to TDO high Z
0
TRST assert time
100
10
—
—
TRST setup time (negation) to TCLK high
1
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
40
Electrical Characteristics
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 11. Test Clock Input Timing
TCLK
VIL
VIH
J5
J6
Data Inputs
Input Data Valid
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 12. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 13. Test Access Port Timing
TCLK
TRST
14
13
Figure 14. TRST Timing
MCF52223 ColdFire Microcontroller, Rev. 3
41
Freescale Semiconductor
Electrical Characteristics
2.17 Debug AC Timing Specifications
Table 39 lists specifications for the debug AC timing parameters shown in Figure 16.
Table 39. Debug AC Timing Specification
66/80 MHz
Min Max
Num
Characteristic
Units
D1
D2
D3
D41
D5
D6
D7
D8
PST, DDATA to CLKOUT setup
4
1.5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT to PST, DDATA hold
DSI-to-DSCLK setup
1 tCYC
4 tCYC
5 tCYC
4
—
DSCLK-to-DSO hold
—
DSCLK cycle time
—
BKPT input data setup time to CLKOUT rise
BKPT input data hold time to CLKOUT rise
CLKOUT high to BKPT high Z
—
1.5
—
0.0
10.0
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to
the rising edge of CLKOUT.
Figure 15 shows real-time trace timing for the values in Table 39.
CLKOUT
D1
D2
PST[3:0]
DDATA[3:0]
Figure 15. Real-Time Trace AC Timing
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
42
Mechanical Outline Drawings
Figure 16 shows BDM serial port AC timing for the values in Table 39.
CLKOUT
D5
DSCLK
D3
DSI
Current
Past
Next
D4
DSO
Current
Figure 16. BDM Serial Port AC Timing
3
Mechanical Outline Drawings
This section describes the physical properties of the device and its derivatives.
MCF52223 ColdFire Microcontroller, Rev. 3
43
Freescale Semiconductor
Mechanical Outline Drawings
3.1
64-pin LQFP Package
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
44
Mechanical Outline Drawings
MCF52223 ColdFire Microcontroller, Rev. 3
45
Freescale Semiconductor
Mechanical Outline Drawings
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
46
Mechanical Outline Drawings
MCF52223 ColdFire Microcontroller, Rev. 3
47
Freescale Semiconductor
Mechanical Outline Drawings
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
48
Mechanical Outline Drawings
MCF52223 ColdFire Microcontroller, Rev. 3
49
Freescale Semiconductor
Mechanical Outline Drawings
3.2
81 MAPBGA Package
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
50
Mechanical Outline Drawings
MCF52223 ColdFire Microcontroller, Rev. 3
51
Freescale Semiconductor
Mechanical Outline Drawings
3.3
100-pin LQFP Package
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
52
Mechanical Outline Drawings
MCF52223 ColdFire Microcontroller, Rev. 3
53
Freescale Semiconductor
Revision History
4
Revision History
Table 40. Revision History
Description
Revision
2
• Formatting, layout, spelling, and grammar corrections.
• Removed the “Preliminary” label.
• Added missing current consumption data (Section 2.2).
• Added revision history.
• Corrected signal names in block diagram to match those in the signal description table.
• Added an entry for standby voltage (VSTBY) to the “DC electrical specifications” table.
• Deleted the PSTCLK cycle time row in the “Debug AC timing specifications” table.
• Changed the frequency above the “Min” and “Max” column headings in the “Debug AC timing
specifications” table (was 166 MHz, is 66/80 MHz).
• Added the following signals to the “Pin functions by primary and alternate purpose” table (alternates to
IRQ1-6, respectively): USB_ALT_CLK, USB_SESSVLD, USB_SESSEND, USB_PULLUP,
USB_VBUSVLD, and USB_ID.
• Changed the minimum value for SNR, THD, SFDR, and SINAD in the “ADC parameters” table (was
TBD, is “—”).
• Added values for IOH and IOL to the “DC electrical specifications” table.
• Added load test condition information to the “General Purpose I/O Timing” section.
• Synchronized the “Pin Functions by Primary and Alternate Purpose” table in this document and the
reference manual.
• Added a specification for VDDUSB to the “Absolute maximum ratings” table.
• Added specifications for VLVD and VLVDHYS to the “DC electrical specifications” table.
• Deleted entries for the nonexistent 64 QFN package from the “Thermal Resistances” table.
3
4
• Updated Table 7 to reflect orderable part numbers.
• Updated Clock generation features
• Updated Table: Clocking Modes and added appropriate footnote
• In Table: CLock Source Electrical Specifications, updated the following values:
• fcrystal, fext, fref_pll, EXTAL input high voltage (External reference)
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
54
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Document Number: MCF52223
Rev. 3
3/2011
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