MCF54417CMJ250_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF54418

Rev. 8, 06/2012

MCF5441x

MAPBGA–256

MAPBGA–196

12 mm x 12 mm

17mm x 17mm

MCF5441x ColdFire

Microprocessor Data Sheet

•

Version 4 ColdFire Core with EMAC and

MMU

•

Enhanced Secure Digital host controller for

SD, SDHC, SDIO, MMC, and MMCplus

cards

•

Up to 385 Dhrystone 2.1 MIPS @ 250 MHz

8 KB instruction cache and 8 KB data cache

64 KB internal SRAM dual-ported to

processor local bus and other crossbar switch

masters

•

Two ISO7816 smart card interfaces

Two FlexCAN modules

2

Six I C bus interfaces with DMA support in

master mode

•

System boot from NOR, NAND, SPI flash,

EEPROM, or FRAM

Crossbar switch technology (XBS) for

concurrent access to peripherals or RAM

from multiple bus masters

•

Two synchronous serial interfaces

Four 32-bit timers with DMA support

Four programmable interrupt timers

8-channel, 16-bit motor control PWM timer

Dual 12-bit ADCs with shared input channels

and multiple conversion trigger sources

Dual 12-bit DACs with DMA support

1-wire module with DMA support

NAND flash controller

•

64-channel DMA controller

SDRAM controller supporting full-speed

operation from a single x8 DDR2 component

up to 250 MHz

32-bit FlexBus external memory interface for

RAM, ROM, MRAM, and programmable

logic

•

Real-time clock with 32-kHz oscillator, 2 KB

standby SRAM, and battery backup supply

input

•

USB 2.0 host controller

•

Up to four DMA-supported serial peripheral

interfaces (DSPI)

Up to ten UARTs with single-wire mode

support

Up to five external IRQ interrupts and 2

external DMA request/acknowledge pairs

Up to 16 processor local bus Rapid GPIO pins

Up to 87 standard GPIO pins

USB 2.0 host/device/On-the-Go controller

8-bit single data rate ULPI port usable by the

dedicated USB host module or the USB

host/device/OTG module

Dual 10/100 Ethernet MACs with hardware

CRC checking/generation, IEEE 1588-2002

support, and optional Ethernet switch

CPU direct-attached hardware accelerator for

DES, 3DES, AES, MD5, SHA-1, and

SHA-256 algorithms

•

Random number generator

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

Table of Contents

1

2

MCF5441x family comparison . . . . . . . . . . . . . . . . . . . . . . . . .4

4.15.2 eSDHC electrical DC characteristics . . . . . . . . 38

4.16 SIM timing specifications. . . . . . . . . . . . . . . . . . . . . . . 38

4.16.1 General timing requirements . . . . . . . . . . . . . . 39

4.16.2 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . 39

4.16.3 Power-down sequence. . . . . . . . . . . . . . . . . . . 40

4.17 SSI timing specifications . . . . . . . . . . . . . . . . . . . . . . . 41

4.18 12-bit ADC specifications . . . . . . . . . . . . . . . . . . . . . . 43

4.19 12-bit DAC timing specifications . . . . . . . . . . . . . . . . . 44

4.20 mcPWM timing specifications . . . . . . . . . . . . . . . . . . . 45

4.21 I²C timing specifications . . . . . . . . . . . . . . . . . . . . . . . 45

4.22 Ethernet assembly timing specifications . . . . . . . . . . . 46

4.22.1 Receive signal timing specifications. . . . . . . . . 47

4.22.2 Transmit signal timing specifications . . . . . . . . 47

4.22.3 Asynchronous input signal timing

1.1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5

2.1 Power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.2 Supply voltage sequencing . . . . . . . . . . . . . . . . . . . . . . .7

2.2.1 Power-up sequence. . . . . . . . . . . . . . . . . . . . . . .8

2.2.2 Power-down sequence . . . . . . . . . . . . . . . . . . . .8

2.3 Power consumption specifications . . . . . . . . . . . . . . . . .8

Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .9

3.1 Signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.2 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .19

3.3 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .20

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21

4.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .22

4.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.4 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.5 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . .23

4.6 Output pad loading and slew rate . . . . . . . . . . . . . . . . .25

4.7 DDR pad drive strengths. . . . . . . . . . . . . . . . . . . . . . . .26

4.8 Oscillator and PLL electrical characteristics . . . . . . . . .26

4.9 Reset timing specifications . . . . . . . . . . . . . . . . . . . . . .28

4.10 FlexBus timing specifications . . . . . . . . . . . . . . . . . . . .28

4.11 NAND flash controller (NFC) timing specifications . . . .30

4.12 DDR SDRAM controller timing specifications . . . . . . . .33

4.13 USB transceiver timing specifications. . . . . . . . . . . . . .35

4.14 ULPI timing specifications. . . . . . . . . . . . . . . . . . . . . . .35

4.15 eSDHC timing specifications. . . . . . . . . . . . . . . . . . . . .36

4.15.1 eSDHC timing specifications . . . . . . . . . . . . . . .37

3

4

specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.22.4 MDIO serial management timing

specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.23 32-bit timer module timing specifications. . . . . . . . . . . 49

4.24 DSPI timing specifications. . . . . . . . . . . . . . . . . . . . . . 49

4.25 SBF timing specifications . . . . . . . . . . . . . . . . . . . . . . 52

4.26 1-Wire timing specifications. . . . . . . . . . . . . . . . . . . . . 53

4.27 General purpose I/O timing specifications. . . . . . . . . . 53

4.28 Rapid general purpose I/O timing specifications . . . . . 53

4.29 JTAG and boundary scan timing specifications. . . . . . 54

4.30 Debug AC timing specifications. . . . . . . . . . . . . . . . . . 56

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5

6

7

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

2

Freescale Semiconductor

MCF5441x

PLL

Oscillator

JTAG

PLL

Version 4 ColdFire Core

8 KB

Instruction

Cache

2 Ethernet

Controllers

EMAC

BDM

CAU

8 KB

Data

Cache

Hardware

Divide

eDMA

USB Host

L2 Switch

64 KB

SRAM

Serial Boot

Facility

NAND Flash

Controller

MMU

RGPIO

USB OTG

eSDHC

Crossbar Switch (XBS)

Peripheral Bus Controller 0

Peripheral Bus Controller 1

DDR2

Controller

FlexBus

1 Wire

mcPWM

Smart Card

ADC

RNG

2 DACs

RTC & kHz

Oscillator

EPORT

2 DSPIs

GPIO

4 I²Cs

2 SSIs

2 FlexCANs

2 I²Cs

4 PITs

2 DSPIs

6 UARTs

4 DMA

Timers

Note: Each of the crossbar switch masters, the FlexBus

and SDRAM controller have access to peripheral

bus controller 0, which is not shown.

3 INTCs

4 UARTs

ADC

BDM

CAU

– Analog-to-digital converter

– Background debug module

– Cryptography acceleration unit

– Digital-to-analog

INTC

JTAG

– Interrupt controller

– Joint Test Action Group interface

mcPWM – Motor control pulse width modulator

PIT

PLL

RGPIO

RNG

RTC

SSI

DAC

– Programmable interrupt timers

– Phase locked loop module

– Rapid GPIO

– Random number generator

– Real time clock

DSPI

eDMA

eSDHC

EMAC

EPORT

GPIO

I²C

– DMA serial peripheral interface

– Enhanced direct memory access module

– Enhanced Secure Digital host controller

– Enhanced multiply-accumulate unit

– Edge port module

– General purpose input/output module

– Inter-Integrated Circuit

– Synchronous serial interface

USB OTG – Universal Serial Bus On-the-Go controller

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

3

MCF5441x family comparison

1

MCF5441x family comparison

Table 1. MCF5441x family configurations

Module

MCF54410 MCF54415 MCF54416 MCF54417 MCF54418

Version 4 ColdFire core with EMAC (enhanced

multiply-accumulate unit) and MMU (memory

management unit)



Cryptography acceleration unit (CAU)

Core (system) and SDRAM clock

—



—

up to 250 MHz

up to 125 MHz

Peripheral clock

(Core clock  2)

External bus (FlexBus) clock

Performance (Dhrystone 2.1 MIPS)

Static RAM (SRAM)

up to 100 MHz

up to 385

64 KB

Independent data/instruction cache

USB 2.0 Host controller

8 KB each

—



USB 2.0 Host/Device/On-the-Go controller

UTMI+ Low Pin Interface (ULPI) for external

high-speed USB PHY

—

10/100 Mbps Ethernet controller with IEEE 1588

support

1

2

Level 2 IEEE 1588-compliant 3-port Ethernet

switch

—



Enhanced Secure Digital host controller (eSDHC)

Smart card/Subscriber Identity Module (SIM)

UARTs



—

6



2 ports

10

DSPI

3

4

CAN 2.0B controllers

I²C

1

2

4

6

Synchronous serial interface (SSI)

12-bit ADC

1

2

—

4



12-bit DAC

2

32-bit DMA timers

4

Periodic interrupt timers (PIT)

Motor control PWM timer (mcPWM)

64-channel DMA controller

4

—



8 channel



Real-time clock with 2 KB standby RAM and

battery back-up input



DDR2 SDRAM controller



FlexBus external memory controller

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

4

Freescale Semiconductor

Hardware design considerations

Table 1. MCF5441x family configurations (continued)

Module MCF54410 MCF54415 MCF54416 MCF54417 MCF54418

NAND flash controller

1-Wire^®interface

Serial boot facility

Watchdog timer



Interrupt controllers (INTC)

Edge port module (EPORT)

Rapid GPIO pins

3

5 IRQs

16

3

5 IRQs

16

3

5 IRQs

16

3

5 IRQs

16

3 IRQs

9

48



General-purpose I/O (GPIO) pins

JTAG - IEEE^®1149.1 Test Access Port

Package

87



196

MAPBGA

256

MAPBGA

1.1

Ordering information

Table 2. Orderable part numbers

Freescale Part

Number

Description Package

Speed

Temperature

MCF54410CMF250

MCF54415CMJ250

MCF54416CMJ250

MCF54417CMJ250

MCF54418CMJ250

MCF54410 Microprocessor 196 MAPBGA

MCF54415 Microprocessor

MCF54416 Microprocessor

256 MAPBGA

MCF54417 Microprocessor

250 MHz

–40 to +85C

MCF54418 Microprocessor

2

Hardware design considerations

2.1

Power filtering

To further enhance noise isolation, an external filter is strongly recommended for the analog V pins (VDDA_PLL and

DD

VDDA_DAC_ADC). The filter shown in Figure 1 should be connected between the board 3.3 V (nominal) supply and the

analog pins. The resistor and capacitors should be placed as close to the dedicated analog V pin as possible. The 10  resistor

DD

in the given filter is required.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

5

Hardware design considerations

10 

EVDD Pin

VDD_OSC_A_PLL

VSS_OSC

0.1 µF

1 µF

100 MHz

GND

Figure 1. Oscillator/PLL/DAC power filter

Figure 2 shows an example for isolating the ADC power supply from the I/O supply (EVDD) and ground. Note that in this

power supply the 10  resistor is replaced by a 0  resistor. This will reduce the IR drop into the ADC, limiting additional gain

error.

0 

Board 3.3 V

supply

VDDA_ADC

10 µF

0.1 µF

GND

Figure 2. ADC power filter

Figure 3 shows an example for bypassing the internal core digital power supply for the MPU. This bypass should be applied to

as many IVDD signals as routing allows. Each one should be placed as close to the ball as possible.

Board 1.2 V

supply

IVDD

1 µF

0.1 µF

GND

Figure 3. IVDD power filter

Figure 4 shows an example for bypassing the external pad ring digital power supply for the MPU. This bypass should be applied

to as many EVDD signals as routing allows. Each one should be placed as close to the ball as possible.

Board 3.3 V

supply

EVDD

1 µF

0.1 µF

GND

Figure 4. EVDD power filter

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

6

Freescale Semiconductor

Hardware design considerations

Figure 5 shows an example for bypassing the FlexBus power supply for the MPU. This bypass should be applied to as many

FB_VDD signals as routing allows. Each one should be placed as close to the ball as possible.

Board 1.8–3.3 V

supply

FB_VDD

1 µF

0.1 µF

GND

Figure 5. FB_VDD power filter

2.2

Supply voltage sequencing

Figure 6 shows requirements in the sequencing of the I/O V (EV ), FlexBus V (FBV ), SDRAM V (SDV ), PLL

DD

V

(VDD_OSC_A_PLL), and internal logic/core V (IV ).

DD

DD DD

EV_DD/FBV_DD(3.3V)

3.3V

2.5V

Supplies stable

SDV_DD(2.5V — DDR)

1.8V

1.5V

SDV_DD/FBV_DD(1.8V — DDR2)

IV_DD, VDD_OSC_A_PLL

0

Time

Notes:

1

Input voltage must not be greater than the supply voltage (EV_DD, FBV_DD, SDV_DD, IV_DD, or PV_DD) by more

than 0.5V at any time, including during power-up.

2

Use 25 V/millisecond or slower rise time for all supplies.

Figure 6. Supply voltage sequencing and separation cautions

The relationships between FBV , SDV and EV are non-critical during power-up and power-down sequences. FBV

DD

(1.8 – 3.3V), SDV (2.5V or 1.8V) and EV are specified relative to IV .

DD

NOTE

All I/O VDD pins must be powered on when the device is functioning, except when in

standby mode.

In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can be switched off.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

7

Hardware design considerations

2.2.1

Power-up sequence

If EV /FBV /SDV are powered up with the IV at 0 V, the sense circuits in the I/O pads cause all pad output drivers

DD

connected to the EV /FBV /SDV to be in a high impedance state. There is no limit on how long after

DD

EV /FBV /SDV powers up before IV must power up. IV should not lead the EV , FBV , or SDV by more

DD

than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the

power supplies should be slower than 25 V/millisecond to avoid turning on the internal ESD protection clamp diodes.

2.2.2

Power-down sequence

If IV /PV are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.

DD

There is no limit on how long after IV and PV power down before EV , FBV , or SDV must power down. IV

DD

should not lag EV , FBV , or SDV going low by more than 0.4 V during power down or there will be undesired high

DD

current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV /PV to 0 V.

DD

2. Drop EV /FBV /SDV supplies.

DD

2.3

Power consumption specifications

Table 3. Estimated power consumption specifications

Characteristic

Symbol

Typical

Unit

Core operating supply current (nominal 1.2 V)¹

IVDD

Run mode

Wait mode

127

33

mA

Doze mode

Stop00 mode

Stop01 mode

Stop02 mode

Stop03 mode

32

9.3

9.2

3.6

3.4

FlexBus operating supply current

Run mode (application dependent)

Wait mode

FBVDD

SDVDD

80

49

42

40

28

mA

Doze mode

Stop00 mode

Stop01, Stop02, Stop03 mode

SDRAM operating supply current (DDR2 at 1.8 V)

Isys(DQ) [8, 2DQS]

3

Isys(WR) [8, 2DQS]

Isys(RD) [8, 2DQS]

15

SDRAM input reference current

SDVREF

SDVTT

Isys(REF)

SDRAM termination current

Isys(termRD)

1.3

41

75

Total SDIDD MPU side²

Oscillator/PLL operating supply current (nominal 3.3 V)

Run, Wait, Doze, Stop00, Stop01 mode

Stop02 mode

VDD_OSC_A_PLL

10

6

mA

Stop03 mode

1

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

8

Freescale Semiconductor

Pin assignments and reset states

Table 3. Estimated power consumption specifications (continued)

Characteristic

Symbol

Typical

Unit

External I/O pad operating supply current (nominal 3.3 V)

EVDD

3

—

mA

USB operating supply current (nominal 3.3 V)

VDD_USBO,

VDD_USBH

30

ADC operating supply current (nominal 3.3 V)

Speed mode 00

VDDA_ADC

14

22

Speed mode 01

DAC operating supply current (nominal 3.3 V)

VDDA_DAC_ADC

VSTBY_RTC

11

mA

RTC standby supply current

ISTBY

17

A

1

2

Current measured at maximum system clock frequency, all modules active, and default drive

strength with matching load.

DDR2 interface power is estimated from the Micron DDR2 data sheet. The numbers given in this

table do not include the actual power consumption of the memory itself. The current drawn by the

memory needs to be added to the values in this table and may be several hundred mA.

3

EVDD values depend on the application, with the restrictions that any single pin cannot exceed

25 mA and that the total power does not exceed the thermal characteristics.

3

Pin assignments and reset states

3.1

Signal multiplexing

The following table lists all the MCF5441x pins grouped by function. The Dir column is the direction for the primary function

of the pin only. Refer to the following sections for package diagrams. For a more detailed discussion of the MCF5441x signals,

consult the MCF5441x Reference Manual (MCF54418RM).

NOTE

In this table and throughout this document a single signal within a group is designated

without square brackets (i.e., FB_AD23), while designations for multiple signals within a

group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two

bracketed numbers when these numbers are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality. Most pins that

are muxed with GPIO default to their GPIO functionality. See the following table for a list

of the exceptions.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

9

Pin assignments and reset states

Table 4. Special-case default signal functionality

Default signal

FB_CLK, FB_OE, FB_R/W,

FB_BE/BWE[1:0],

FB_CS[5:4]

FB_CLK, FB_OE, FB_R/W,

FB_BE/BWE[1:0], FB_CS[5:4]

FB_ALE

FB_BE/BWE3

FB_BE/BWE2

FB_CS1

FB_ALE or FB_TS

(depending on RCON[3])

Boot from NFC, NF_ALE.

Otherwise, FB_BE/BWE3.

Boot from NFC, NF_CLE.

Otherwise, FB_BE/BWE2.

Boot from NFC, NFC_CE.

Otherwise, GPIO.

FB_CS0

Boot from FlexBus, FB_CS0.

Otherwise, GPIO.

FB_TA

Boot from NFC, NFC_R/B.

Otherwise, FB_TA.

ALLPST, PST[3:0],

DDATA[3:0]

ALLPST, PST[3:0], DDATA[3:0]

NOTE

While most modules and functionalities between the 196 and 256 MAPBGA package are

the same, the following modules have been removed from 196 MAPBGA for pin space:

UART2, UART6, UART9, PWM, SSI1, SIM1, USB HOST, IRQ6, IRQ3, IRQ2,

FLEXCAN1, I2C1, ADC, DAC.

Other modifications to the 196 MAPBGA package are:

•

SDRAMC — One address line, SD_A14, is removed.

SDHC — Number of data lines for eSDHC have been reduced to 4 instead of 8.

MAC — Only MAC0_RMII mode is implemented.

Table 5. MCF5441x Signal information and muxing

Signal name

GPIO

Alternate 1

Alternate 2

Reset

RESET

—

U

I

EVDD

ssr

K14

P12

K15

L16

RSTOUT

—

O

msr

Clock

4

I

EXTAL/

—

EVDD

ae

G14

G16

RMII_REF_CLK

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

10

Freescale Semiconductor

Pin assignments and reset states

Table 5. MCF5441x Signal information and muxing (continued)

Signal name

GPIO

Alternate 1

Alternate 2

XTAL

—

O

I

EVDD

ae

msr

fsr

H14

H16

K5, L5

Mode selection

BOOTMOD[1:0]

—

G5,H5

FlexBus

FB_AD[31:24]/

NFC_IO[15:8]⁵

I/O

FBVDD

A10, A9,

B9, C8, A9,

B9, C9, A8, B8, D8, A8,

B8, C8, A7 D7, B7

FB_AD[23:16]/

NFC_IO[7:0]⁵

fsr

B7, C7, C6, C7, A7, D6,

B6, A6, A5, A6, B6, D5,

B5, A4

C6, A5

6

FB_AD[15:10]

—

fsr

C5, A3, B4, B5, A4, A3,

C4, B3, A2 D4, B4, C5

FB_AD[9:8]

FB_AD[7:0]

—

U⁷

—

I/O

FBVDD

fsr

B2, C3

C4, B3

D4, B1, C2, C3, E4, D3,

D3, C1, D2, E3, A2, B2,

E3, D1

C2, F3

FB_ALE

PA7

PA6

FB_TS

—

O

FBVDD

fsr

E2

D2

FB_OE/

NFC_RE

FB_TBST/

NFC_RE

O

H1

F1

FB_R/W/

NFC_WE

PA5

—

O

FBVDD

fsr

H2

G2

FB_TA

PA4

PA3

—

NFC_R/B

U⁸

—

O

FBVDD

fsr

H3

F3

H3

C1

FB_BE/BWE3

FB_CS3

FB_A1/

NFC_ALE⁹

FB_BE/BWE2

PA2

FB_CS2

FB_A0/

—

O

FBVDD

fsr

E1

E2

NFC_CLE¹⁰

FB_BE/BWE[1:0]

FB_CLK

PA[1:0]

PB7

FB_TSIZ[1:0]

—

O

FBVDD

fsr

F2, F1

G1

D1, F4

G1

—

DACK1

DREQ1

—

FB_CS5

PB6

—

F2

FB_CS4

PB5

—

B1

FB_CS1

PB4

NFC_CE

—

G3

E1

FB_CS0

PB3

—

G2

G3

I²C 0

I2C0_SCL

I2C0_SDA

PB2

PB1

UART8_TXD

UART8_RXD

CAN0_TX

CAN0_RX

—

I/O

EVDD

ssr

H12

G12

G15

G14

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

11

Pin assignments and reset states

Table 5. MCF5441x Signal information and muxing (continued)

Signal name

GPIO

Alternate 1

Alternate 2

FlexCAN 1

CAN1_TX

CAN1_RX

PB0

PC7

UART9_TXD

UART9_RXD

I2C1_SCL

I2C1_SDA

—

I/O

EVDD

ssr

—

D14

D15

SDRAM controller

SD_A14

—

O

SDVDD st_dec

ap

—

P6

SD_A[13:0]

—

SDVDD st_dec P3, M1, M3, R4, R1, R3,

ap

L2, L1, N4, N4, P3, T4,

M2, P2, L3, R2, T2, N3,

L4, N1, N2, P5, P4, N5,

K1, N3

P2, T3

SD_BA[2:0]

SD_CAS

—

O

SDVDD st_dec M6, J4, P4 P7, N6, R5

ap

SDVDD st_dec

ap

K4

N8

SD_CKE

SDVDD st_dec

ap

N6

R7

SD_CLK

SD_CS

—

O

SDVDD st_ck

P6

P7

M5

T5

T6

N7

SDVDD st_dec

ap

SD_D[7:0]

—

I/O

SDVDD st_odt P11, M10,

T12, R11,

T11, R10,

N9, T10,

P9, R9

N10, M9,

P10, M8,

N8, M7

SD_DM

SD_DQS

SD_ODT

—

O

I/O

O

SDVDD st_odt

SDVDD st_dqs

N7

P8

P9

P5

T7

T8

T9

P8

SDVDD st_dec

ap

SD_RAS

SD_WE

—

O

SDVDD st_dec

ap

M4

N5

R6

R8

SDVDD st_dec

ap

SD_VREF

SD_VTT

—

SDVDD st_vref

SDVDD st_vtt

N9

L8

P10

N10

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

12

Freescale Semiconductor

Pin assignments and reset states

Table 5. MCF5441x Signal information and muxing (continued)

Signal name

GPIO

Alternate 1

Alternate 2

External interrupts port

IRQ7

IRQ6

IRQ4

IRQ3

IRQ2

IRQ1

PC6

PC5

PC4

PC3

PC2

PC1

—

I

EVDD

ssr

G10

—

F12

N1

USB_CLKIN¹¹

DREQ0

DSPI0_PCS3

DSPI0_PCS2

—

E11

—

F14

M1

USBH_VBUS_EN

USBH_VBUS_OC

—

12

—

M2

—

E13

F13

USB On-the-Go

USBO_DM

USBO_DP

—

I/O

VDD_

USB0

ae

B13

A13

A14

B14

—

VDD_

USB0

USB host

USBH_DM

USBH_DP

—

I/O

VDD_

USBH

ae

—

A15

B15

—

VDD_

USBH

ADC

ADC_IN7/

DAC1_OUT

—

I

VDDA_

DAC_

ADC

ae

—

K3

ADC_IN[6:4]

—

I

VDDA_

ADC

ae

—

H2, J3, G4

K4

ADC_IN3/

DAC0_OUT

VDDA_

DAC_

ADC

ADC_IN[2:0]

—

I

VDDA_

ADC

ae

—

J2, J1, H1

Real time clock

4

I

RTC_EXTAL

RTC_XTAL

—

VSTBY

ae

B14

C14

B16

C16

O

DSPI0/SBF¹³

DSPI0_PCS1/

SBF_CS

PC0

—

I/O

EVDD

msr

K3

L1

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

13

Pin assignments and reset states

Table 5. MCF5441x Signal information and muxing (continued)

Signal name

GPIO

Alternate 1

Alternate 2

DSPI0_PCS0/SS

PD7

PD6

I2C3_SDA

I2C3_SCL

SDHC_DAT3

SDHC_CLK

—

I/O

EVDD

msr

J1

J3

K2

L2

DSPI0_SCK/

SBF_CK

DSPI0_SIN/

SBF_DI

PD5

PD4

UART3_RXD

UART3_TXD

SDHC_CMD

SDHC_DAT0

U¹⁴

—

I

EVDD

msr

K2

J2

L3

K1

DSPI0_SOUT/

SBF_DO

O

One wire

OW_DAT

RGPIO0/PD3

RGPIO1/PD2

DACK0

T3OUT

—

I/O

I

EVDD

ssr

M11

G13

N11

G13

DMA timers

T3IN/PWM_EXTA3

USBO_VBUS_EN/

ULPI_DIR¹⁵

msr

T2IN/PWM_EXTA2

T1IN/PWM_EXTA1

T0IN/PWM_EXTA0

RGPIO2/PD1

RGPIO3/PD0

RGPIO4/PE7

T2OUT

T1OUT

T0OUT

SDHC_DAT2

SDHC_DAT1

—

I

EVDD

msr

J12

H13

J13

H14

H13

H15

17

USBO_VBUS_OC/

ULPI_NXT¹⁶

—

UART 2

UART2_CTS

UART2_RTS

UART2_RXD

UART2_TXD

RGPIO14/PE6

RGPIO15/PE5

PE4

UART6_TXD

UART6_RXD

PWM_A3

SSI1_BCLK

SSI1_FS

—

I

O

I

EVDD

msr

—

M4

M3

P1

N2

SSI1_RXD

SSI1_TXD

18

PE3

PWM_B3

I/O

UART 1

UART1_CTS

UART1_RTS

UART1_RXD

UART1_TXD

RGPIO7/PE2

RGPIO8/PE1

PE0

UART5_TXD

UART5_RXD

I2C5_SDA

DSPI3_SCK

DSPI3_PCS0

DSPI3_SIN

—

I

O

I

EVDD

msr

D12

D11

B10

C10

D10

C9

18

PF7

I2C5_SCL

DSPI3_SOUT

I/O

D9

UART 0

UART0_CTS

UART0_RTS

UART0_RXD

UART0_TXD

RGPIO5/PF6

RGPIO6/PF5

PF4

UART4_TXD

UART4_RXD

I2C4_SDA

DSPI2_SCK

DSPI2_PCS0

DSPI2_SIN

—

I

O

I

EVDD

msr

E12

C12

C11

B11

E13

B11

B10

D11

18

PF3

I2C4_SCL

DSPI2_SOUT

I/O

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

14

Freescale Semiconductor

Pin assignments and reset states

Table 5. MCF5441x Signal information and muxing (continued)

Signal name

GPIO

Alternate 1

Alternate 2

Enhanced secure digital host controller

SDHC_DAT3

SDHC_DAT2

SDHC_DAT1

SDHC_DAT0

SDHC_CMD

SDHC_CLK

PF2

PF1

PF0

PG7

PG6

PG5

PWM_A1

PWM_B1

PWM_A2

PWM_B2

PWM_B0

PWM_A0

DSPI1_PCS0

DSPI1_PCS2

DSPI1_PCS1

DSPI1_SOUT

DSPI1_SIN

—

I/O EVDD

msr

—

B13

E14

D12

B12

C11

A10

DSPI1_SCK

O

EVDD

Smart card interface 0

SIM0_DATA

SIM0_VEN

SIM0_RST

SIM0_PD

RGPIO13/PG4

RGPIO12/PG3

RGPIO11/PG2

RGPIO10/PG1

RGPIO9/PG0

PWM_FAULT2

SDHC_DAT7

—

I/O EVDD

msr

—

E12

D13

C15

C14

A11

PWM_FAULT0

PWM_FORCE

PWM_SYNC

PWM_FAULT1

O

I

EVDD

SDHC_DAT6

SDHC_DAT5

SDHC_DAT4

SIM0_CLK

O

Synchronous serial interface 0¹⁹

SSI0_RXD

SSI0_TXD

SSI0_FS

PH7

PH6

PH5

PH4

PH3

I2C2_SDA

SIM1_VEN

SIM1_DATA

SIM1_RST

SIM1_CLK

SIM1_PD

—

I

EVDD

msr

B12

A11

C13

A12

D13

C12

C13

E15

A12

A13

I2C2_SCL

UART7_TXD

SSI_CLKIN

UART7_RXD

O

I/O

O

SSI0_MCLK

SSI0_BCLK

I/O

Ethernet subsystem

MII0_MDC

MII0_MDIO

MII0_RXDV

MII0_RXD[1:0]

MII0_RXER

MII0_TXD[1:0]

MII0_TXEN

MII0_COL

PI1

PI0

RMII0_MDC²⁰

—

D²¹

—

O

EVDD

fsr

N14

M14

M13

P13, N13

M12

L12, L11

N12

P16

N16

RMII0_MDIO²⁰

RMII0_CRS_DV²⁰

RMII0_RXD[1:0]²⁰

RMII0_RXER²⁰

RMII0_TXD[1:0]²⁰

RMII0_TXEN²⁰

RMII1_MDC

—

I/O EVDD

PJ7

—

I

EVDD

P14

PJ[6:5]

PJ4

—

R15, T15

N14

I

PJ[3:2]

PJ1

—

O

I

R13, P13

P12

—

PJ0

ULPI_STP

ULPI_DATA4

ULPI_DATA5

ULPI_DATA[1:0]

—

R12

MII0_TXER

MII0_CRS

PK7

RMII1_MDIO

O

I

—

R14

PK6

RMII1_CRS_DV

RMII1_RXD[1:0]

—

P11

MII0_RXD[3:2]

PK[5:4]

I

—

P15, N13

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

15

Pin assignments and reset states

Table 5. MCF5441x Signal information and muxing (continued)

Signal name

GPIO

Alternate 1

Alternate 2

MII0_RXCLK

MII0_TXD[3:2]

MII0_TXCLK

PK3

PK[2:1]

PK0

RMII1_RXER

RMII1_TXD[1:0]

RMII1_TXEN

ULPI_DATA6

ULPI_DATA[3:2]

ULPI_DATA7

—

I

O

I

EVDD

fsr

—

M14

T13, N12

T14

D²¹

BDM/JTAG

ALLPST²²

DDATA[3:2]

DDATA[1:0]

PST[3:0]

PH2

—

O

EVDD

fsr

K12

—

PH[1:0]

PI[7:6]

PI[5:2]

L15, M13

M15, L14

—

J13, J16,

J15, J14

JTAG_EN

PSTCLK

DSI

—

D

—

U

I

EVDD

msr

fsr

N11

L14

L10

L13

K13

L9

N15

M16

L13

K14

K16

K13

TCLK²³

TDI²³

I

msr

DSO

TDO²³

TMS²³

TRST²³

—

U

O

I

BKPT

DSCLK

U

I

Test

(this signal must be grounded)

TEST

IVDD

EVDD

—

Power supplies

—

D

I

EVDD

—

ssr

—

K10

R16

—

D9, D10,

E9,E10,F9,

F10, F12

E9–E11,

F9–F11

—

F4–F7, G6, H8, J7–J10,

G7, H6, H7, K6–K11, L6

J5, J6

FB_VDD

SD_VDD

—

D5–D7,

E4–E7

E5–E7, F5,

F6, G5

K7–K9,

L5–L7

M7–M12

VDD_OSC_A_PLL

VSS_OSC_A_PLL

VDD_USBO

—

vddint

vdde

—

F14

F13

F11

—

F15

F16

G12

H12

H4

VDD_USBH

VDDA_ADC

—

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

16

Freescale Semiconductor

Pin assignments and reset states

Table 5. MCF5441x Signal information and muxing (continued)

Signal name

GPIO

Alternate 1

Alternate 2

VSSA_ADC

VDDA_DAC_ADC

VSSA_DAC_ADC

VSTBY²⁴

—

vssint

vddint

vssint

vddint

—

H5

J4

—

J5

E14

E16

VSS

A1, A14,

D8, D14,

E8, F8, G4,

G8, G9,

A1, A16,

D16, E8,

F7, F8,

G6–G11,

H6, H7,

G11, H4,

H8–11,

H9–H11,

J6, J11,

J12, K12,

J7–11, J14,

K5, K6,

K11, P1, L4, L7–L12,

P14

M5, M6, T1,

T16

1

All pins available with GPIO contain a configurable pull-up/down. This column indicates the pull devices that are enabled

automatically at reset. Pull-ups are generally only enabled on pins with their primary function, except as noted.

2

3

Refers to pin’s primary function.

For details on the available slew rates of the various pad types see section “Output Pad Loading and Slew Rate” of the MCF5441x

Data Sheet or section “Slew Rate Control Registers (SRCR_x)” in chapter “Pin-Multiplexing and Control” of the MCF5441x Reference

Manual.

4

5

Enabled as input only in oscillator bypass mode (internal crystal oscillator is disabled).

These pins are time-division multiplexed between the FlexBus and NFC. An arbitration mechanism determines which module drives

these pins at any point in time.

6

7

8

9

An internal pulldown circuit is enabled during system reset for FB_AD[10].

An internal pullup circuit is enabled when the system is in reset state.

Configurable pull that is enabled and pulled up after reset.

When configured for FB_A1, this pin is time-division multiplexed between the FlexBus and NFC. An arbitration mechanism

determines which module drives the pin at any point in time. When not configured as FB_A1, NFC_ALE cannot be used.

¹⁰When configured for FB_A0, this pin is time-division multiplexed between the FlexBus and NFC. An arbitration mechanism

determines which module drives the pin at any point in time. When not configured as FB_A0, NFC_CLE cannot be used.

¹¹Since USB_CLKIN is a clock signal, it must be dedicated to the USB system. Do not implement this pin as dual-use.

¹²When Alternate 2 is selected, then internal pullup/pulldown control will come from the MISCCR[3] register of CIM.

¹³When booting from serial boot flash, the SBF function is enabled automatically. After the SBF function completes its reset sequence,

the signals are returned to GPIO functionality.

¹⁴Automatic pull-up when SBF controls the pin during reset only. Configurable pull when UART, DSPI, or SDHC control the pin.

¹⁵If ULPI is enabled, ULPI_DIR is available as the Alternate 2 function. If ULPI is disabled, USBO_VBUS_EN is available.

¹⁶If ULPI is enabled, ULPI_NXT is available as the Alternate 2 function. If ULPI is disabled, USBO_VBUS_OC is available.

¹⁷When Alternate 2 is selected, then internal pullup/pulldown control will come from the MISCCR[2] register of CIM.

¹⁸UARTx_TXD pad can act as RXD(input) pad when UART One Wire mode is enabled.

¹⁹The SIM1 signals are available with 256 MAPBGA but are not available with 196 MAPBGA.

²⁰These RMII functions are selected by the mode chosen by the MAC-NET, not by the pin-multiplexing and control (GPIO) module.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

17

Pin assignments and reset states

²¹Configurable pull that is enabled and pulled down after reset.

²²The ALLPST signal is available only on the 196 MAPBGA package and allows limited debug trace functionality compared to the 256

MAPBGA package.

²³If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these

pins.

²⁴VSTBY is for optional standby lithium battery. If not used, connect to EVDD.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

18

Freescale Semiconductor

Pin assignments and reset states

3.2

Pinout—196 MAPBGA

The pinout for the MCF54410 package is shown below.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

FB_

AD10

FB_

AD14

FB_

AD16

FB_

AD18

FB_

AD19

FB_

AD24

FB_

AD27

FB_

AD30

FB_

AD31

SSI0_

TXD

SSI0_

MCLK

USB_

DPLS

A

B

C

D

E

F

GND

A

B

C

D

E

F

FB_

AD6

FB_

AD9

FB_

AD11

FB_

AD13

FB_

AD17

FB_

AD20

FB_

AD23

FB_

AD26

FB_

AD29

U1_

RXD

U0_

TXD

SSI0_

RXD

USB_

DMNS

RTC_

EXTAL

FB_

AD3

FB_

AD5

FB_

AD8

FB_

AD12

FB_

AD15

FB_

AD21

FB_

AD22

FB_

AD25

FB_

AD28

U1_

TXD

U0_

RXD

U0RTS_

B

SSI0_

FS

RTC_

XTAL

FB_

AD2

FB_

AD4

FB_

AD7

U1RTS_ U1CTS_

SSI0_

BCLK

FB_

AD0

FBVDD FBVDD FBVDD

GND

CVDD

GND

CVDD

IRQ7_B

GND

B

FB_BE2

_B

FB_

AD1

U0CTS_

B

FB_ALE

FBVDD FBVDD FBVDD FBVDD

IRQ4_B

IRQ1_B VSTBY

VSS_OS VDD_OS

C_A_PL C_A_PL

FB_BE0 FB_BE1 FB_BE3

VDD_

USBO

EVDD

GND

EVDD

GND

EVDD

GND

CVDD

_B

L

FB_CS0 FB_CS1

_B

BOOT

MOD1

I2C0_

SDA

G

H

J

FB_CLK

GND

T3IN

EXTAL

G

H

J

_B

FB_OE_ FB_RW_ FB_TA_

BOOT

MOD0

I2C0_

SCL

GND

T1IN

T0IN

TMS

XTAL

GND

B

DSPI0_ DSPI0_ DSPI0_

SD_BA1 EVDD

GND

T2IN

PCS0

SOUT

SCK

DSPI0_ DSPI0_ SD_CAS

SIN PCS1 _B

RSTIN_

B

K

L

SD_A1

GND

SDVDD SDVDD SDVDD

TEST

TDI

ALLPST

K

L

RM110_ RM110_

TXD0

SD_A9 SD_A10 SD_A5

SD_A4 SDVDD SDVDD SDVDD SD_VTT TRST_B

TDO

TCLK

TXD1

SD_RAS SD_CS_

RMII0_

RXER CRS_DV MDIO

RMII0_

SD_A7

SD_A2

M

N

P

SD_A12

SD_A3

SD_A11

SD_A0

SD_BA2 SD_D0

SD_D2

SD_D4

SD_D6

SD_D5

OWIO

M

N

P

_B

B

SD_WE_

B

SD_VRE

F

JTAG_E RMII0_

RMII0_

RXD0

RMII0_

MDC

SD_A8

SD_CKE SD_DQM SD_D1

SD_CLK_

N

TXEN

SD_DQS

_B

RSTOUT RMII0_

_B

GND

SD_A6 SD_A13 SD_BA0 SD_ODT SD_CLK

SD_DQS

SD_D3

SD_D7

GND

B

RXD1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Figure 7. MCF54410 Pinout (196 MAPBGA)

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

19

Pin assignments and reset states

3.3

Pinout—256 MAPBGA

The pinout for the MCF54415, MCF54416, MCF54417, and MCF54418 packages are shown below.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

FB_

AD3

FB_

SDHC_ SIM0_

SSI0_

MCLK

SSI0_ USBO_ USBH_

BCLK DM DM

A

B

C

D

VSS

A

B

C

D

AD13

AD14

AD16

AD20

AD22

AD26

AD29

CLK

FB_

CS4

UART0_

RTS

FB_

AD2

FB_

AD8

FB_

AD11

FB_

AD15

FB_

AD19

FB_

AD24

FB_

AD28

FB_

AD31

UART0_

RXD

SDHC_ SDHC_ USBO_ USBH_ RTC_

DAT0

DAT3

DP

EXTAL

UART1_

CTS

FB_BE/

BWE3

FB_

AD1

FB_

AD7

FB_

AD9

FB_

AD10

FB_

AD17

FB_

AD23

FB_

AD30

UART1_

RXD

SDHC_ SSI0_

CMD RXD

SSI0_

TXD

SIM0_

PD

SIM0_

RST

RTC_

XTAL

UART1_

RTS

FB_BE/

BWE1

FB_

ALE

FB_

AD5

FB_

AD12

FB_

AD18

FB_

AD21

FB_

AD25

FB_

AD27

UART1_

TXD

UART0_ SDHC_ SIM0_ CAN1_ CAN1_

TXD

VSS

DAT1

VEN

TX

RX

FB_

BE/BW

E2

FB_

CS1

UART0

_CTS

VSTBY_

RTC

FB_

AD4

FB_

AD6

FB_

VDD

FB_

VDD

FB_

VDD

SIM0_

XMT

SDHC_ SSI0_

IVDD

E

VSS

E

DAT2

FS

VDD_

VSS_

FB_

OE

FB_

CS5

FB_BE/

BWE0

FB_

AD0

FB_

IVDD

VSS

IVDD

VSS

IVDD

VSS

OSC_A OSC_A

F

G

H

J

VSS

IRQ7

IRQ1

T3IN

IRQ4

F

G

H

J

VDD

_PLL

FB_

R/W

FB_

CS0

FB_

CLK

ADC_

IN4

FB_

VDD

VDD_

USBO

I2C0_

SDA

I2C0_

SCL

EXTAL

VSS

FB_

TA

ADC_

IN0

ADC_

IN6

AVDD_ AVSS_

ADC ADC

VDD_

USBH

T1IN

T2IN

PST0

TDO

T0IN

PST1

XTAL

PST2

TMS

VSS

EVDD

VSS

VDDA_ VSSA_

DAC_

ADC

ADC_

IN1

ADC_

IN2

ADC_

IN5

DAC_

ADC

PST3

TRST

TDI

VSS

EVDD

VSS

EVDD

VSS

EVDD

VSS

DSPI0_ DSPI0_ ADC_

SOUT

ADC_

IN3

BOOT

MOD1

K

L

EVDD

VSS

EVDD

VSS

RESET

K

L

PCS0

IN7

RST

OUT

DSPI0_ DSPI0_ DSPI0_

PCS1

BOOT

MOD0

DDATA0 DDATA3

MII0_

VSS

SCK

SIN

UART2_ UART2_

RTS CTS

SD_

VDD

SD_

VDD

SD_

VDD

SD_

VDD

SD_

VDD

SD_

VDD

DDATA2

DDATA1 TCLK

M

N

P

R

T

IRQ3

IRQ2

VSS

M

N

P

R

T

RXCLK

SD_

CAS

UART2_

TXD

OW_

IO

MII0_

TXD2

MII0_

RXD2

MII0_

RXER

JTAG_

EN

MII0_

MDIO

SD_A5 SD_A10 SD_A2 SD_BA1

SD_D3 SD_VTT

IRQ6

SD_CS

UART2_

RXD

SD_

ODT

SD_

SD_D1

MII0_

CRS

MII0_

TXEN

MII0_

TXD0

MII0_

RXDV

MII0_

RXD3

MII0_

MDC

SD_A1 SD_A9 SD_A3 SD_A4 SD_A14 SD_BA2

VREF

SD_

RAS

SD_

CKE

MII0_

COL

MII0_

TXD1

MII0_

TXER

MII0_

RXD1

SD_A12 SD_A7 SD_A11 SD_A13 SD_BA0

SD_D0 SD_D4 SD_D6

SD_

TEST

SD_WE

SD_

CLK

SD_

CLK

SD_

DM

SD_

DQS

MII0_

TXD3

MII0_

TXCLK RXD0

SD_A6 SD_A0 SD_A8

SD_D2 SD_D5 SD_D7

VSS

DQS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Figure 8. MCF54415, MCF54416, MCF54417, and MCF54418 Pinout (256 MAPBGA)

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

20

Freescale Semiconductor

Electrical characteristics

4

Electrical characteristics

This document contains electrical specification tables and reference timing diagrams for the MCF5441x microprocessor. This

section contains detailed information on AC/DC electrical characteristics and AC timing specifications.

NOTE

The specifications for this device in any other document are superseded by the

specifications in this document.

4.1

Absolute maximum ratings

1, 2

Table 6. Absolute maximum ratings

Rating

Symbol

Pin name

EVDD

Value

Units

External I/O pad supply voltage

Internal logic supply voltage

FlexBus I/O pad supply voltage

SDRAM I/O pad supply voltage

PLL supply voltage

EV_DD

IV_DD

–0.3 to +4.0

–0.5 to +2.0

–0.3 to +4.0

–0.3 to +3.6

25

V

IVDD

FB_VDD

FBV_DD

SDV_DD

PV_DD

V

SD_VDD

V

VDD_OSC_A_PLL

VDD_USBO

VDD_USBH

VDDA_ADC

VDDA_DAC_ADC

VSTBY_RTC

V

USB OTG supply voltage

USB host supply voltage

ADC supply voltage

USBV_DD

AV_DD

V

DAC and ADC supply voltage

RTC standby supply voltage

Digital input voltage³

—

V

RTCV_STBY

V_IN

V

—

V

Instantaneous maximum current

I_DD

mA

Single pin limit (applies to all pins) ^{3, 4, 5}

Operating temperature range (packaged)

T_A

(T_L– T_H)

—

–40 to +85

C

Storage temperature range

T_stg

–55 to +150

1

2

Functional operating conditions are given in Table 11. Absolute maximum ratings are stress ratings only, and

functional operation at the maximum is not guaranteed. Continued operation at these levels may affect device

reliability or cause permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it

is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated

voltages to this high-impedance circuit. Immunity to static and electrical fields is enhanced if unused inputs are tied

to an appropriate logic voltage level (e.g., V_SSor EV_DD).

3

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, and then use the larger of the two values.

4

5

All functional non-supply pins are internally clamped to V_SSand EV_DD

.

Power supply must maintain regulation within operating EV_DD, FBV_DD, and SDV_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_in> EV_DD, FBV_DD, or SDV_DD) is greater than

I_DD, the injection current may flow out of EV_DD, FBV_DD, or SDV_DDand could result in external power supply going

out of regulation. Ensure the external EV_DD, FBV_DD, or SDV_DDload shunts current greater than maximum injection

current. This is the greatest risk when the MPU is not consuming power (for example, no clock).

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

21

Electrical characteristics

4.2

Thermal characteristics

Table 7. Thermal characteristics

196

MAPBGA

256

MAPBGA

Characteristic

Symbol

Unit

Junction to ambient, natural convection¹

Junction to ambient (@200 ft/min)^{1, 3}

Single layer

board (1s)²

_JA

58

35

48

32

—

32

—

29

Four layer board

(2s2p)^2,3

C/W

Single layer

board (1s)

_JMA

Four layer board

(2s2p)

C/W

Junction to board⁴

Junction to case⁵

_JB

_JC

_jt

T_j

22

14

3

22

12

2

C/W

^oC

Junction to top of package, natural convection^{1, 6}

Maximum operating junction temperature

105

1



_JAand _jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board,

and board thermal resistance.

2

3

4

Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

5

6

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization

parameter is written in conformance with Psi-JT.

The average chip-junction temperature (T ) in C can be obtained from:

J

T_J= T_A+ P_D _JMA



Eqn. 1

Where:

T_A

= Ambient Temperature, C

Q_JMA

P_D

= Package Thermal Resistance, Junction-to-Ambient, C/W

= P_INT+ P_I/O

P_INT

P_I/O

= I_DD IV_DD, Watts - Chip Internal Power

= Power Dissipation on Input and Output Pins — User Determined

For most applications P < P

and can be ignored. An approximate relationship between P and T (if P is neglected) is:

D J I/O

I/O

INT

K

--------------------------------

P_D

=

Eqn. 2

T_J+ 273C

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

22

Freescale Semiconductor

Electrical characteristics

Solving equations 1 and 2 for K gives:

K = P_D T_A 273C + Q_JMA P²_D

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)

D

for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively

A

D

J

for any value of T .

A

4.3

ESD protection

1, 2

Table 8. ESD protection characteristics

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

HBM

2000

V

1

2

All ESD testing is in conformity with JESD22 Stress Test Qualification.

A device is defined as a failure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

performed per applicable specification at room temperature followed by hot temperature,

unless specified otherwise in the device specifications provided in this document.

4.4

Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

•

A supply over voltage is applied to each power supply pin.

A current injection is applied to each input, output, and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 9. Latch-up results

No.

Symbol

LU

Parameter

Static latch-up class

Conditions

Class

1

CC

T_A= 125 °C conforming to JESD 78

II level A

4.5

DC electrical specifications

Table 10. Power supply specifications

Characteristic

Symbol Pin Name

Min

Max

Units

IVDD

Internal logic supply voltage, nominal 1.2 V

IV_DD

1.14

1.32

V

FB_VDD

FlexBus supply voltage

Nominal 1.8–3.3 V

FBV_DD

1.71

3.63

SD_VDD

SDRAM supply voltage

DDR2 @ 1.8 V

SDV_DD

V

1.71

1.98

SD_VREF

SDRAM input reference voltage

SDV_REF

0.49 x SDV_DD

0.51 x SDV_DD

V

SD_VTT

SDRAM termination supply voltage

SDV_TT

SDV_REF– 0.04 SDV_REF+ 0.04

3.135 3.63

VDD_OSC_

A_PLL

PLL analog operation voltage range, nominal 3.3 V

PV_DD

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

23

Electrical characteristics

Table 10. Power supply specifications (continued)

Characteristic

Symbol Pin Name

Min

Max

Units

EVDD

External I/O pad supply voltage, nominal 3.3 V

USB supply voltage, nominal 3.3 V

EV_DD

3.135

3.63

V

VDD_USBO

VDD_USBH

USBV_DD

VDDA_ADC

ADC supply voltage

DAC supply voltage

AV_DD

3.135

3.63

V

VDDA_DAC_

—

ADC

VSTBY_RTC

RTC standby supply voltage

RTCV_STBY

1.6

EV_DD– 0.2V

V

Table 11. I/O electrical specifications

Characteristic

Symbol

Min

Max

Units

CMOS input high voltage

CMOS input low voltage

CMOS output high voltage

EV_IH

EV_IL

0.65  EV_DD

V_SS– 0.3

EV_DD+ 0.3

0.35  EV_DD

—

V

EV_OH

0.8  EV_DD

I_OH= –2.0 mA

CMOS output low voltage

I_OL= 2.0 mA

EV_OL

—

0.2  EV_DD

V

SDRAM input high voltage

DDR2 @ 1.8V

SDV_IH

SDV_IL

V

SDV_REF+ 0.125

0.3

SDV_DD+ 0.3

SDV_REF 0.125

—

SDRAM input low voltage

DDR2 @ 1.8V

SDRAM output high voltage

DDR2@ 1.8V I_OH= –13.4 mA

SDV_OH

SDV_DD 0.9

SDRAM output low voltage

DDR2@ 1.8V I_OH= 13.4 mA

SDV_OL

V

—

SDV_DD 0.1

FlexBus input high voltage

@ 1.8V–3.3V

FBV_IH

FBV_IL

0.51  FBV_DD

V_SS– 0.3

FBV_DD+ 0.3

0.42  FBV_DD

—

V

FlexBus input low voltage

@ 1.8V–3.3V

FlexBus output high voltage

@ 1.8V–3.3V

FBV_OH

0.8  FBV_DD

I_OH= –5.0 mA for all modes

FlexBus output low voltage

@ 1.8V–3.3V

FBV_OL

—

0.2  FBV_DD

V

I_OL= 5.0 mA for all modes

Input Leakage Current

I_in

–2.5

2.5

A

V_in= V_DDor V_SS, Input-only pins

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

24

Freescale Semiconductor

Electrical characteristics

Table 11. I/O electrical specifications (continued)

Characteristic

Symbol

Min

Max

Units

Weak internal pull-up/pull-down device current¹

I_APU

C_in

10

25

315

150

A

pF

Selectable weak internal pull-up/pull-down device current¹

Input capacitance ²

All input-only pins

All input/output (three-state) pins

—

7

Output loading for CMOS pads (EV_DDand FBV_DDdomains)

C_L

pF

Low drive

High drive

50

200

Output loading for SDRAMC pads (SDV_DDdomain)

Low drive

High drive

5

50

1

Refer to the signals section for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

2

4.6

Output pad loading and slew rate

The output pins on the MCF5441x devices have programmable slew rates. Table 12 lists the rise/fall time for pins based on the

type of pad used for the signal, the value programmed into the appropriate field of the slew rate control registers, and capacitive

loading. Refer to Table 5 for a list of the external signals to pad connections.

NOTE

To allow the I/O interfaces to run at their maximum frequency, set their respective slew rate

select values to 11.

Table 12. Output pad slew rates

Slew rate select

field value

Drive load

(pF)

Rise/fall time

(ns)

Pad type¹

ssr

50

200

50

2.2

6

11

10

01

00

22

200

50

28

42

200

50

210

220

200

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

25

Electrical characteristics

Table 12. Output pad slew rates (continued)

Slew rate select

field value

Drive load

(pF)

Rise/fall time

(ns)

Pad type¹

msr

50

200

50

1.2

6

11

10

01

00

11

10

01

00

9

200

50

14

17

23

110

120

1.1

2.6

2.4

5

200

50

200

50

fsr

200

50

200

50

5

200

50

8

16

21

200

1

The ae pads are used for USB communication and are governed by usb.org

specifications. They are not included in this table.

4.7

DDR pad drive strengths

The DDR pins on the MCF5441x devices have programmable drive strengths. Table 13 lists the drive strengths for pins based

on the value programmed into the appropriate field of the drive strength control register. Refer to Table 5 for a list of the external

signals to pad connections.

NOTE

For a single device drive, this setting should be 00 to enable Half Strength mode. High

strength is intended for multiple device drives (DIMM).

Table 13. DDR pad drive strengths

Drive strength select

Pad type

Drive strength

field value

st

00

01

10

11

Half strength 1.8V DDR2

Full strength 1.8V DDR2

Reserved

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

26

Freescale Semiconductor

Electrical characteristics

4.8

Oscillator and PLL electrical characteristics

Reference Figure 9 for crystal circuits.

Table 14. PLL electrical characteristics

Symbol

Num

Characteristic

Min

Max

Unit

1

PLL Reference Frequency Range¹

Crystal reference

External reference

f_{ref_crystal}

f_{ref_ext}

14¹

50¹

MHz

2

Core frequency

f_sys

f_sys/2

120

60

250

100

MHz

FB_CLK frequency²(MISCCR2[FBHALF] = 0)

3

4

5

6

VCO frequency

f_vco

f_DCC

t_cst

240

300

—

500

10

MHz

ms

DCC frequency³

Crystal start-up time^{4, 5}

EXTAL input high voltage

External and limp modes

V_IHEXT

EV_IH

EVDD

V

7

EXTAL input low voltage

External and limp modes

V_ILEXT

t_lpll

0

—

EV_IL

50

V

ms

%

8

9

PLL lock time ^{4, 6}

Duty cycle of reference ⁴

t_dc

–45%

—

+45%

10

Crystal capacitive load

C_L

From crystal

spec

pF

11

12

13

Feedback resistor

R_F

R_S

10

0

—

200

M



Series resistor

Discrete load capacitance for XTAL

C_{L_XTAL}

—

2  C_L–

pF

C_{S_XTAL}

C_{PCB_XTAL}

–

7

14

15

Discrete load capacitance for EXTAL

C_{L_EXTAL}

—

2  C_L–

C_{S_EXTAL}

C_{PCB_EXTAL}

pF

–

7

FB_CLK period jitter, ^{4, 5, 7, 8,}Measured at f_SYSMax

Peak-to-peak jitter (clock edge to clock edge)

Long term jitter

C_jitter

—

10

0.1

% f_sys/3

1

These reference value ranges are for after a PLL predivider (PREDIV), which can be programmed to 1, 2, 4, 8, or 16.

The PREDIV value can be set while booting from serial flash. In parallel reset configuration, the PREDIV value is set to

one. In this mode, if the input frequency results in an out of range reference frequency, boot the processor in limp

mode, set the proper PREDIV and multiplier settings, and switch to PLL mode.

All internal registers retain data at 0 Hz.

2

3

Required only for DDR2 memory.

4

5

6

7

8

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

This specification is the PLL lock time only and does not include oscillator start-up time.

C_{PCB_EXTAL}and C_{PCB_XTAL}are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_sys

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.

.

Noise injected into the PLL circuitry via PLL V_DD, EV_DD, and V_SSand variation in crystal oscillator frequency increase

the Cjitter percentage for a given interval.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

27

Electrical characteristics

XOSC

EXTAL

XTAL

R_S

R_F

Crystal or Resonator

C

C_L

C₂

1

L

Figure 9. Typical crystal circuit

4.9

Reset timing specifications

Table 15 lists specifications for the reset timing parameters shown in Figure 10.

Table 15. Reset and configuration override timing

Num

Characteristic

Min

Max

Unit

R1¹RESET valid to FB_CLK (setup)

9

1.5

5

—

10

—

1

ns

R2 FB_CLK to RESET invalid (hold)

ns

FB_CLK cycles

ns

R3 RESET valid time²

R4 FB_CLK to RSTOUT valid

—

0

R5 RSTOUT valid to Configuration Override inputs valid

R6 Configuration Override inputs valid to RSTOUT invalid (setup)

R7 Configuration Override inputs invalid after RSTOUT invalid (hold)

R8 RSTOUT invalid to Configuration Override inputs High Impedance

R9 Minimum RSTOUT pulse width

ns

20

0

FB_CLK cycles

ns

—

512

FB_CLK cycles

—

1

2

RESET and configuration override data lines are synchronized internally. Setup and hold times must be met only if

recognition on a particular clock is required.

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously

to the system. Thus, RESET must be held a minimum of 100 ns.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

28

Freescale Semiconductor

Electrical characteristics

FB_CLK

RESET

R1

R2

R3

R4

R9

R6

RSTOUT

R8

R7

R5

BOOTMOD[1:0]

Figure 10. RESET and configuration override timing

4.10 FlexBus timing specifications

All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a

reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider

of that frequency.

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the FlexBus output clock

(FB_CLK). All other timing relationships can be derived from these values.

All FlexBus signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load

1

of 50 pF.

Table 16. FlexBus timing specifications

Num

Characteristic

Frequency of operation

Min

Max

Unit

Notes

—

16

—

62.5

—

MHz

ns

FB1 Clock period

FB2 Output valid

FB3 Output hold

FB4 Input setup

FB5 Input hold

1

2

6.0

—

ns

0.5

5.5

0

ns

—

ns

—

ns

1

2

Specification is valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn,

and FB_TSIZ[1:0].

Specification is valid for all FB_AD[31:0] and FB_TA.

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

29

Electrical characteristics

S0

S1

S2

S3

FB_CLK

FB1

FB3

ADDR[Y:0]

FB_AD[Y:0]

FB2

FB5

ADDR[31:X]

FB_AD[31:X]

DATA

FB4

FB_R/W

FB_ALE

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB4

FB5

FB_TA

TSIZ[1:0]

FB_TSIZ[1:0]

Note:

1

FB2 and FB3 output specifications are valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS,

FB_CSn, FB_OE, FB_BE/BWEn, and FB_TSIZ[1:0].

2

FB4 and FB5 input specifications are valid for all FB_AD[31:0] and FB_TA.

Figure 11. FlexBus read timing

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

30

Freescale Semiconductor

Electrical characteristics

S0

S1

S2

S3

FB_CLK

FB1

FB3

ADDR[Y:0]

FB_AD[Y:0]

FB2

ADDR[31:X]

FB_AD[31:X]

FB_R/W

DATA

FB_ALE

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB4

FB5

FB_TA

TSIZ[1:0]

FB_TSIZ[1:0]

Note:

1

FB2 and FB3 output specifications are valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS,

FB_CSn, FB_OE, FB_BE/BWEn, and FB_TSIZ[1:0].

2

FB4 and FB5 input specifications are valid for all FB_AD[31:0] and FB_TA.

Figure 12. FlexBus write timing

4.11 NAND flash controller (NFC) timing specifications

The NAND flash controller (NFC) implements the interface to standard NAND flash memory devices. This section describes

the timing parameters of the NFC.

All NFC signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of

1

50 pF.

Table 17. NFC timing specifications

Num

Characteristic

Frequency of operation

NF1 Clock period

Symbol

Min

Max

Unit

—

25

40¹

—

MHz

ns

t_NFC

t_CLS

t_CLH

t_CS

NF2 NFC_CLE setup time

NF3 NFC_CLE hold time

NF4 NFC_CE setup time

NF5 NFC_CE hold time

NF6 NFC_WE pulse width

1.5  t_NFC

t_NFC

ns

1.5  t_NFC

t_NFC

ns

t_CH

ns

t_WP

0.5  t_NFC– 0.5

ns

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

31

Electrical characteristics

Num

Table 17. NFC timing specifications (continued)

Characteristic

Symbol

Min

Max

Unit

NF7 NFC_ALE setup time

NF8 NFC_ALE hold time

NF9 Data setup time

t_ALS

t_ALH

t_DS

1.5  t_NFC

t_NFC

—

ns

0.5  t_NFC– 4

0.5  t_NFC– 10

t_NFC

NF10 Data hold time

t_DH

NF11 Write cycle time

t_WC

t_WH

t_RR

NF12 NFC_WE high hold time

NF13 Ready to NFC_RE low

NF14 NFC_RE pulse width

NF15 Read cycle time

0.5  t_NFC– 1

4.5  t_NFC

0.5  t_NFC– 0.5

t_NFC

t_RP

t_RC

NF16 NFC_RE high hold time

NF17 Data in setup time

t_REH

t_DSU

0.5  t_NFC– 1

6

1

50 MHz maximum frequency can only be used if the part is in EDO (enhanced data out) mode.

NFC_CLE

NF2

NF4

NF3

NF5

NFC_CE

NF6

NFC_WE

NFC_ALE

NF7

NF8

NF9

Command

NF10

NFC_IO[7:0]

Figure 13. Command latch cycle timing

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

32

Freescale Semiconductor

Electrical characteristics

NFC_CLE

NFC_CE

NF2

NF4

NF5

NF11

NF6

NF12

NFC_WE

NFC_ALE

NF7

NF8

NF10

NF9

NFC_IO[7:0]

Address

Figure 14. Address latch cycle timing

NF3

NF5

NFC_CLE

NFC_CE

NF11

NF6

NF12

NFC_WE

NFC_ALE

NF7

NF9

NF10

Data to NF

NFC_IO[15:0]

Figure 15. Write data latch timing

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

33

Electrical characteristics

NF5

NFC_CE

NF15

NF14

NF17

NF16

NFC_RE

NF10

NFC_IO[15:0]

NFC_R/B

Data from NF

NF13

Figure 16. Read data latch timing

4.12 DDR SDRAM controller timing specifications

The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing

numbers are relative to the DQS byte lanes.

Table 18. SDRAM timing specifications

Num

Characteristic

Frequency of operation

Symbol

Min

Max

Unit

Notes

100

4.0

250

10.0

MHz

ns

DD1 Clock period

t_SDCK

t_SDCKH

t_SDCKL

t_CMV

1

DD2 Pulse width high

DD3 Pulse width low

0.45

—

0.55

t_SDCK

ns

0.55

3

2

DD4 Address, SD_CKE, SD_CAS, SD_RAS,

SD_WE, SD_CS[1:0] — output valid

0.5  t_SDCK+ 1

DD5 Address, SD_CKE, SD_CAS, SD_RAS,

SD_WE, SD_CS[1:0] — output hold

t_CMH

0.5  t_SDCK– 1

—

ns

DD6 Write command to first DQS latching transition

t_DQSS

t_QS

—

WL + 0.2  t_SDCK

ns

3

4

DD7 Data and data mask output setup (DQDQS)

0.4

—

relative to DQS (DDR write mode)

5

DD8 Data and data mask output hold (DQSDQ)

t_QH

0.4

—

ns

relative to DQS (DDR write mode)

6

7

DD9 Input data skew relative to DQS (input setup)

DD10 Input data hold relative to DQS.

t_IS

t_IH

—

0.5

—

ns

0.375  t_SDCK

1

2

Pulse width high plus pulse width low cannot exceed min and max clock period.

Command output valid should be 1/2 the memory bus clock (t_SDCK) plus some minor adjustments for process, temperature,

and voltage variations.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

34

Freescale Semiconductor

Electrical characteristics

3

This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be

larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.

SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]

4

5

6

The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are

valid for each subsequent DQS edge.

This specification relates to the required hold time of DDR memories.

SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]

Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line

becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other

factors).

7

Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes

invalid.

DD1

DD2

SD_CLK

DD3

DD5

SD_CSn,SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

DD6

SD_A[13:0]

COL

DD7

SD_DM

SD_DQS

SD_D[7:0]

DD8

DD7

WD1 WD2 WD3 WD4

DD8

Figure 17. DDR write timing

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

35

Electrical characteristics

DD1

DD2

SD_CLK

DD3

DD5

CL=2

SD_CSn,SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

CL=2.5

SD_A[13:0]

COL

DD9

DQS Read

Postamble

DQS Read

Preamble

SD_DQS

DD10

SD_D[7:0]

RD1 RD2 RD3 RD4

DQS Read

Preamble

DQS Read

Postamble

SD_DQS

SD_D[7:0]

RD1 RD2 RD3 RD4

Figure 18. DDR read timing

4.13 USB transceiver timing specifications

The MCF5441x device is compliant with industry standard USB 2.0 specification.

4.14 ULPI timing specifications

The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing

requirements for the ULPI pins are given in Table 19. These timings apply to synchronous mode only. All timings are measured

with respect to the clock as seen at the USB_CLKIN pin on the MCF5441x. The ULPI PHY is the source of the 60MHz clock.

NOTE

The USB controller requires a 60-MHz clock, even if using the on-chip FS/LS transceiver

instead of the ULPI interface. In this case, the 60-MHz clock can be generated by the PLL

or input on the USB_CLKIN pin.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

36

Freescale Semiconductor

Electrical characteristics

All ULPI signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of

1

50 pF.

Table 19. ULPI interface timing

Num

Characteristic

Min

Nominal

Max

Units

USB_CLKIN operating frequency

USB_CLKIN duty cycle

—

60

50

—

9.5

—

MHz

%

U1

U2

U3

U4

U5

USB_CLKIN clock period

—

16.67

—

ns

Input setup (control and data)

Input hold (control and data)

Output valid (control and data)

Output hold (control and data)

5.0

1.0

—

ns

—

ns

—

ns

1.0

—

ns

U1

USB_CLKIN

U2

U3

ULPI_DIR / ULPI_NXT

(Control Input)

U2

U3

ULPI_DATA[7:0]

(Data Input)

U4

U5

ULPI_STP

(Control Output)

U5

U4

ULPI_DATA[7:0]

(Data Output)

Figure 19. ULPI timing diagram

4.15 eSDHC timing specifications

This section describes the electrical information of the eSDHC.

All eSDHC signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load

2

of 50 pF.

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

2.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

37

Electrical characteristics

4.15.1 eSDHC timing specifications

Figure 20 depicts the timing of eSDHC, and Table 20 lists the eSDHC timing characteristics.

Table 20. eSDHC interface timing specifications

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1 Clock frequency (low speed)

Clock frequency (SD/SDIO full speed)

Clock frequency (MMC full speed)

Clock frequency (identification mode)

SD2 Clock low time

f_PP

0

400

40

20

400

—

3

kHz

MHz

kHz

ns

2

f_PP

3

f_PP

0

4

f_OD

100

7

t_WL

t_WH

t_TLH

t_THL

SD3 Clock high time

7

ns

SD4 Clock rise time

—

ns

SD5 Clock fall time

3

ns

eSDHC Output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SD6 eSDHC output delay (output valid) t_OD

eSDHC Input / card outputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

–5

5

ns

SD7 eSDHC input setup time

SD8 eSDHC input hold time

t_ISU

t_IH

5

0

—

ns

1

2

3

4

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal data transfer mode for SD/SDIO card, clock frequency can be any value from 0 to 25 MHz.

In normal data transfer mode for MMC card, clock frequency can be any value from 0 to 20 MHz.

In card identification mode, card clock must be 100 kHz– 400 kHz, voltage ranges from 2.7 to 3.6 V.

SD2

SD1

SD4

SD5

SDHC_CLK

SD3

SD6

Output from eSDHC to card

SDHC_CMD

SDHC_DAT[3:0]

SD7

SD8

Input from card to eSDHC

SDHC_CMD

SDHC_DAT[3:0]

Figure 20. eSDHC timing

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

38

Freescale Semiconductor

Electrical characteristics

4.15.2 eSDHC electrical DC characteristics

Table 21 lists the eSDHC electrical DC characteristics.

Table 21. MMC/SD interface electrical specifications

Design

value

Num

Parameter

Min

Max

Unit

Condition/remark

Bus signal line load

7

8

Pull-up resistance

Open drain resistance

47

10

100

NA

k

Internal PU

NA

For MMC cards only

I_OH= –100 µA

I_OL= 2 mA

Open drain signal level

9

Output high voltage

Output low voltage

V_DD– 0.2

V

10

0.3

Bus signal levels

11

12

Output high voltage

0.75 x V_DD

V

I_OH= –100 µA @V_DDmin

I_OL= 100 µA @V_DDmin

Output low voltage

0.125 x V_DD

13

14

Input high voltage

Input low voltage

0.625 x V_DD

V_DD+ 3

V

_SS– 0.3

0.25 x V_DD

4.16 SIM timing specifications

Each SIM card interface consist of a total of 12 pins (two separate ports of six pins each. Mostly one port with 5 pins is used).

The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM

card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work

with CLK equal to 16 times the data rate on TX/RX pins.

There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used

by the SIM card to recover the clock from the data, like a standard UART. All six (or five when a bidirectional TXRX is used)

of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between

the signals in normal mode. However, there are some in reset and power down sequences.

All SIM signals use pad type pad_msr. SIM timing is fairly relaxed compared to other interfaces and can be met at 50 pF loading

1

with any slew rate setting other than 00.

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

39

Electrical characteristics

4.16.1 General timing requirements

Figure 21 shows the timing of the SIM module, and Table 22 lists the timing parameters.

1/Sfreq

SIM_CLK

Sfall

Srise

Figure 21. SIM clock timing diagram

Table 22. SIM timing specification—High Drive strength

Num

Description

Symbol

Min

Max

Unit

1

SIM clock frequency (SIM_CLK)¹

S_freq

0.01

5 (Some new cards

may reach 10)

MHz

2

3

4

SIM_CLK rise time ²

S_rise

S_fall

–

20

25

ns

SIM_CLK fall time ³

SIM input transition time (RX, SIM_PD)

S_trans

1

2

3

50% duty cycle clock

With C = 50pF

4.16.2 Reset sequence

4.16.2.1 Cards with internal reset

The reset sequence for this kind of SIM card is as follows (see Figure 22):

•

After powerup, the clock signal is enabled on SIM_CLK (time T0)

After 200 clock cycles, RX must be high.

The card must send a response on RX acknowledging the reset between 400 and 40,000 clock cycles after T0.

SIM_VEN

SIM_CLK

Response

SIM_RX

1

2

1

2

< 200 clock cycles

T0

400 clock cycles <

< 40,000 clock cycles

Figure 22. Internal-reset card reset sequence

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

40

Freescale Semiconductor

Electrical characteristics

4.16.2.2 Cards with active-low reset

The sequence of reset for this kind of card is as follows (see Figure 23):

1. After powerup, the clock signal is enabled on SIM_CLK (time T0)

2. After 200 clock cycles, RX must be high.

3. SIM_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those

40,000 clock cycles)

4. SIM_RST is set high (time T1)

5. SIM_RST must remain high for at least 40,000 clock cycles after T1 and a response must be received on RX between

400 and 40,000 clock cycles after T1.

SIM_VEN

SIM_RST

SIM_CLK

Response

SIM_RX

2

1

3

T0

T1

< 200 clock cycles

1

2

3

400 clock cycles <

< 40,000 clock cycles

400,000 clock cycles <

Figure 23. Active-low-reset card reset sequence

4.16.3 Power-down sequence

Power down sequence for SIM interface is as follows:

1. SIM_PD port detects the removal of the SIM card

2. SIM_RST goes low

3. SIM_CLK goes low

4. SIM_TX goes low

5. SIM_VEN goes low

Each of these steps is completed in one CKIL period (usually 32 kHz). Power-down may be started in response to a

card-removal detection or launched by the processor. Figure 24 and Table 23 show the usual timing requirements for this

sequence, with Fckil = CKIL frequency value.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

41

Electrical characteristics

Num

Table 23. Timing requirements for power-down sequence

Description

Symbol

Min

Max

Unit

1

2

3

4

SIM reset to SIM clock stop

S_rst2clk

S_rst2dat

S_rst2ven

S_pd2rst

0.9  f_CKIL

1.8  f_CKIL

2.7  f_CKIL

0.9  f_CKIL

0.8

1.2

1.8

25

µs

ns

SIM reset to SIM TX data low

SIM reset to SIM voltage enable low

SIM presence detect to SIM reset low

Spd2rst

SIM_PD

SIM_RST

Srst2clk

SIM_CLK

SIM__TX

Srst2dat

Srst2ven

SIM_VEN

Figure 24. SmartCard interface power-down AC timing

4.17 SSI timing specifications

This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given

for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync

(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings

remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.

All SSI signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50

pF. When the SSI_MCLK output is not used, the maximum SSI bit clock (SSI_BCLK) frequency is such that timing can also

1

be met at slew rate settings 10 and 01.

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

42

Freescale Semiconductor

Electrical characteristics

1

Table 24. SSI timing — master modes

Num

Description

Symbol

Min

Max

Units

Notes

2

S1

S2

S3

S4

S5

S6

S7

S8

S9

SSI_MCLK cycle time

t_MCLK

15.15

45%

80

—

55%

—

ns

t_MCLK

ns

SSI_MCLK pulse width high / low

SSI_BCLK cycle time

3

t_BCLK

SSI_BCLK pulse width

45%

—

55%

15

t_BCLK

ns

SSI_BCLK to SSI_FS output valid

SSI_BCLK to SSI_FS output invalid

SSI_BCLK to SSI_TXD valid

0

—

ns

—

15

ns

SSI_BCLK to SSI_TXD invalid / high impedance

SSI_RXD / SSI_FS input setup before SSI_BCLK

0

—

ns

15

—

ns

S10 SSI_RXD / SSI_FS input hold after SSI_BCLK

0

—

ns

1

2

3

All timings specified with a capacitive load of 25pF.

SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (f_sys).

SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (f_sys).

1

Table 25. SSI timing — slave modes

Num

Description

Symbol

Min

Max

Units

Notes

S11 SSI_BCLK cycle time

t_BCLK

80

45%

10

2

—

55%

—

ns

t_BCLK

ns

S12 SSI_BCLK pulse width high / low

S13 SSI_FS input setup before SSI_BCLK

S14 SSI_FS input hold after SSI_BCLK

S15 SSI_BCLK to SSI_TXD / SSI_FS output valid

—

ns

—

15

ns

S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high

impedance

0

—

ns

S17 SSI_RXD setup before SSI_BCLK

S18 SSI_RXD hold after SSI_BCLK

15

2

—

ns

1

All timings specified with a capacitive load of 25pF.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

43

Electrical characteristics

S1

S2

SSI_MCLK

(Output)

S3

SSI_BCLK

(Output)

S4

S5

S6

SSI_FS

(Output)

S9

S10

SSI_FS

(Input)

S7

S8

S7

S8

SSI_TXD

SSI_RXD

S9

S10

Figure 25. SSI timing — master modes

S11

SSI_BCLK

(Input)

S12

S15

S16

SSI_FS

(Output)

S13

S14

SSI_FS

(Input)

S15

S16

S15

SSI_TXD

SSI_RXD

S17

S18

Figure 26. SSI timing — slave modes

4.18 12-bit ADC specifications

1

Table 26. ADC parameters

Characteristic

Frequency of operation

Name

Min

Typical

Max

Unit

200kHz

8.33

—

3

12MHz

500

ADC clock period

t_ADC

V_REFL

V_REFH

INL

ns

V

Low reference voltage

V_SS

V_REFH

AV_DD

—

High reference voltage

V_REFL

—

V

Integral non-linearity (10% to 90% input signal range)²

lsb

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

44

Freescale Semiconductor

Electrical characteristics

1

Table 26. ADC parameters (continued)

Characteristic

Name

Min

Typical

Max

Unit

Differential non-linearity (10% to 90% input signal

range)³

DNL

—

0.6

—

lsb

Monotonicity

Guaranteed

Conversion time

—

0

6

1

t_ADCcycles

Sample time

t_ADCcycles

ADC power-up time⁴

Recovery from auto standby

Input impedance

t_ADPU

t_REC

13

6

t_ADCcycles⁵

t_ADCcycles

X_IN

2k

—

100

20

12

0.2

57

55

60

9

—

3



mA

nA

Input injection current⁶, per pin

I_ADI

V_REFHcurrent

I_VREFH

V_OFFSET0

—

Offset voltage internal reference (at the y intercept)

LSB

%

Offset voltage internal reference (at the 50% FSR point) V_OFFSET50

Gain error (transfer path)

Spurious free dynamic range

Signal-to-noise plus distortion

Signal-to-noise ratio

E_GAIN

SFDR

SINAD

SNR

dB

Effective number of bits

ENOB

Bits

1

All ADC parameter measurements are preliminary pending full characterization.

These measurements were made at V_DD= 3.3 V, V_REFH= 3.3 V, and V_REFL= ground.

INL measured from V_IN= 0.1V_REFHto V_IN= 0.9V_REFH

Includes power-up of ADC and V_REF

2

3

4

5

6

ADC clock cycles

The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the

ADC

4.19 12-bit DAC timing specifications

Table 27 shows electrical specifications of DAC.

1

Table 27. DAC parameters

Characteristic

Name

Min

Typical

Max

Unit

Range of digital input words: 497 to 3599 (0x1F1–0xE0F)

Monotonicity

LSB

—

806

—

uV

Guaranteed

Conversion time (high-speed)

Conversion time (low-speed)

Conversion rate (high-speed)

Conversion rate (low-speed)

Output swing

1

2

—

us

—

1M

conv/sec

V

500K

AVSS + 0.04

AVDD – 0.04

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

45

Electrical characteristics

1

Table 27. DAC parameters (continued)

Characteristic

Name

Min

Typical

Max

Unit

Integral non-linearity (497 to 3599)

Differential non-linearity (497 to 3599)

Gain error (497 to 3599)

INL

DNL

E_GAIN

ENOB

t_DAPU

R_L

—

9

—

8.0

0.5

—

lsb

%

0.26

—

Effective number of bits

—

bits

us

DAC power-up time

—

3K

—

11

—

Output load resistance

—

Ohm

pF

Output load capacitance

C_L

400

60

—

Power supply ripple rejection

PSRR

—

dB

1

All measurements were made at V_DD= 3.3V, V_REFH= 3.3V, and V_REFL= ground

4.20 mcPWM timing specifications

Table 28. mcPWM timing

Num

Characteristic

Min

Max

Unit

G1 FB_CLK high to output valid

G2 FB_CLK high to output invalid

G3 Input valid to FB_CLK high

G4 FB_CLK high to input invalid

—

1

7

ns

—

3

1

2

4.21 I C timing specifications

2

Table 29 lists specifications for the I C input timing parameters shown in Figure 27.

2

Table 29. I C input timing specifications between SCL and SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1

I2

I3

I4

I5

I6

I7

I8

I9

2

8

—

1

1/f_SYS

ms

Clock low period

I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

—

0

—

1

ns

I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

4

ms

—

1/f_SYS

ns

Data setup time

0

Start condition setup time (for repeated start condition only)

Stop condition setup time

2

1/f_SYS

2

Table 30 lists specifications for the I C output timing parameters shown in Figure 27.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

46

Freescale Semiconductor

Electrical characteristics

Table 30. I C output timing specifications between SCL and SDA

2

Num

Characteristic

Min

Max

Units

I1¹

I2¹

I3²

I4¹

I5³

I6¹

I7¹

I8¹

I9¹

Start condition hold time

Clock low period

6

—

3

1/f_SYS

µs

10

—

7

I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

1/f_SYS

ns

I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

10

2

—

1/f_SYS

Data setup time

Start condition setup time (for repeated start condition only)

Stop condition setup time

20

10

1

Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = 0x20) results in minimum output timings as shown in Table 30. The I²C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed into the IFDR. However, the numbers

given in Table 30 are minimum values.

2

3

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive

low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and

pull-up resistor values.

Specified at a nominal 50-pF load.

I5

I6

I2

I2C_SCL

I2C_SDA

I7

I8

I1

I9

I4

I3

2

Figure 27. I C input/output timings

4.22 Ethernet assembly timing specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing

specs/constraints for the physical interface.

All Ethernet signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load

1

of 50 pF.

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

47

Electrical characteristics

4.22.1 Receive signal timing specifications

The following timing specs meet the requirements for MII and RMII interfaces for a range of transceiver devices.

Table 31. Receive signal timing

MII mode

RMII mode

Num

Characteristic

Unit

Min

Max

Min

Max

—

E1

E2

E3

E4

RXCLK frequency

—

5

25

—

4

50

—

MHz

ns

RXD[n:0], RXDV, RXER to RXCLK setup¹

RXCLK to RXD[n:0], RXDV, RXER hold¹

RXCLK pulse width high

5

—

2

—

ns

35%

65%

35%

65%

RXCLK period

RXCLK pulse width low

1

In MII mode, n = 3; In RMII mode, n = 1

E4

E3

E2

RXCLK (MII) / EXTAL (RMII)

E1

RXD[n:0]

RXDV,

Valid Data

RXER

Figure 28. MII/RMII receive signal timing diagram

4.22.2 Transmit signal timing specifications

Table 32. Transmit signal timing

MII mode

RMII mode

Num

Characteristic

Unit

Min

Max

Min

Max

—

E5

E6

E7

E8

TXCLK frequency

—

4

25

—

5

50

—

MHz

ns

TXCLK to TXD[n:0], TXEN, TXER invalid¹

TXCLK to TXD[n:0], TXEN, TXER valid¹

TXCLK pulse width high

—

25

—

14

ns

35%

65%

35%

65%

t_TXCLK

TXCLK pulse width low

1

In MII mode, n = 3; In RMII mode, n = 1

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

48

Freescale Semiconductor

Electrical characteristics

E8

TXCLK (MII) / EXTAL (RMII)

E7

E5

E6

TXD[n:0]

TXEN,

TXER

Valid Data

Figure 29. MII/RMII transmit signal timing diagram

4.22.3 Asynchronous input signal timing specifications

Table 33. MII/RMII transmit signal timing

Num

Characteristic

CRS, COL minimum pulse width

Min

Max

Unit

E9

1.5

—

TXCLK period

CRS, COL

E9

Figure 30. MII/RMII async inputs timing diagram

4.22.4 MDIO serial management timing specifications

Table 34. MDIO serial management channel signal timing

Num

Characteristic

Symbol

Min

Max

Unit

E10

E11

E12

E13

E14

E15

MDC cycle time

MDC pulse width

t_MDC

400

40

—

25

10

0

—

60

375

—

ns

% t_MDC

ns

MDC to MDIO output valid

MDC to MDIO output invalid

MDIO input to MDC setup

MDIO input to MDC hold

ns

—

ns

—

ns

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

49

Electrical characteristics

E10

E11

MDC (Output)

E11

E12

E13

Valid Data

MDIO (Output)

MDIO (Input)

E14

E15

Valid Data

Figure 31. MDIO serial management channel timing diagram

4.23 32-bit timer module timing specifications

Table 35 lists timer module AC timings.

Table 35. Timer module AC timing specifications

Name

Characteristic

DTnIN cycle time (n = 0:3)

DTnIN pulse width (n = 0:3)

Min

Max

Unit

T1

T2

3

1

—

1/f_SYS/2

4.24 DSPI timing specifications

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the

transfer attributes are programmable. Table 36 provides DSPI timing characteristics for classic SPI timing modes. Refer to the

DSPI chapter of the MCF54418 Reference Manual for information on the modified transfer formats used for communicating

with slower peripheral devices.

All DSPI signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of

1

50 pF.

1

Table 36. DSPI module AC timing specifications

Name

Characteristic

Symbol

Min

Max

Unit

Notes

Master Mode

—

DSPI_SCK frequency

DSPI_SCK cycle time

f_SCK

t_SCK

—

50

—

MHz

ns

2

3

4

5

DS1

DS2

DS3

DS4

DS5

20

DSPI_SCK duty cycle

(t_sck2) – 2.0 (t_sck2) + 2.0

ns

DSPI_PCSn to DSPI_SCK delay

DSPI_SCK to DSPI_PCSn delay

DSPI_SCK to DSPI_SOUT valid

t_CSC

t_ASC

—

(t_sck2) – 2.0

(t_sck2) – 3.0

—

5

ns

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

50

Freescale Semiconductor

Electrical characteristics

1

Table 36. DSPI module AC timing specifications (continued)

Name

Characteristic

Symbol

Min

Max

Unit

Notes

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

–5

6

—

ns

0

Slave Mode

—

DSPI_SCK frequency

DSPI_SCK cycle time

f_SCK

t_SCK

—

f_SYS 8

MHz

ns

DS9

8 f_SYS

—

DS10 DSPI_SCK duty cycle

(t_sck2) – 2.0 (t_sck2) + 2.0

ns

DS11 DSPI_SCK to DSPI_SOUT valid

DS12 DSPI_SCK to DSPI_SOUT invalid

DS13 DSPI_SIN to DSPI_SCK input setup

DS14 DSPI_SCK to DSPI_SIN input hold

DS15 DSPI_SS active to DSPI_SOUT driven

DS16 DSPI_SS inactive to DSPI_SOUT not driven

—

0

12

—

10

ns

—

ns

—

2

ns

—

7

ns

—

ns

—

ns

1

Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin

on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.

2

3

When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].

This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],

DCTARn[CPHA], and DCTARn[PBR].

4

5

The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].

The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

51

Electrical characteristics

DS3

DS4

DSPI_PCSn

DS1

DS2

DSPI_SCK

(DCTARn[CPOL] = 0)

DS2

DSPI_SCK

(DCTARn[CPOL] = 1)

DS7

DS8

DSPI_SIN

Last Data

First Data

Data

DS5

DS6

DSPI_SOUT

First Data

Last Data

Figure 32. DSPI Classic SPI timing — master Mode

DSPI_SS

DS9

DSPI_SCK

DS10

(DCTARn[CPOL] = 0)

DS10

DSPI_SCK

(DCTARn[CPOL] = 1)

DS15

DS11

DS12

Data

DS16

First Data

DSPI_SOUT

DSPI_SIN

Last Data

DS13

DS14

Data

Last Data

First Data

Figure 33. DSPI Classic SPI timing — slave mode

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

52

Freescale Semiconductor

Electrical characteristics

4.25 SBF timing specifications

The Serial boot facility (SBF) provides a means to read configuration information and system boot code from a broad array of

SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 37 provides the AC timing specifications for the SBF.

All SBF signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of

1

50 pF.

Table 37. SBF AC timing specifications

Name

Characteristic

SBF_CK frequency

Symbol

Min

Max

Unit

Notes

—

f_SBFCK

t_SBFCK

—

62.5

—

5

MHz

ns

1

SB1

SB2

SB3

SB4

SB5

SB6

SB7

SB8

SBF_CK cycle time

16.67

SBF_CK high/low time

30%

t_SBFCK

ns

SBF_CS to SBF_CK delay

SBF_CK to SBF_CS delay

SBF_CK to SBF_DO valid

SBF_CK to SBF_DO invalid

SBF_DI to SBF_SCK input setup

SBF_CK to SBF_DI input hold

—

t_SBFCK– 2.0

—

t_SBFCK– 2.0

ns

—

–5

10

0

ns

—

ns

—

ns

—

ns

1

At reset, the SBF_CK cycle time is t_REF 60. The first byte of data read from the serial memory contains a divider value

that is used to set the SBF_CK cycle time for the duration of the serial boot process.

SBF_CS

SB3

SB1

SB4

SB2

SBF_CK

SBF_DI

SB7 SB8

First Data

Last Data

SB6

Data

SB5

First Data

SBF_DO

Last Data

Figure 34. SBF timing

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

53

Electrical characteristics

4.26 1-Wire timing specifications

Specifications for the 1-Wire interface are provided by Maxim Integrated Products, Inc. Please refer to data sheet information

for the appropriate device at www.maxim-ic.com.

4.27 General purpose I/O timing specifications

1

Table 38. GPIO timing

Num

Characteristic

Min

Max

Unit

G1 FB_CLK high to GPIO output valid

G2 FB_CLK high to GPIO output invalid

G3 GPIO input valid to FB_CLK high

G4 FB_CLK high to GPIO input invalid

—

1

9

ns

—

9

1.5

1

These general purpose specifications apply to the following signals: IRQn, all UART signals, all timer

signals, FlexCAN signals, DACKn and DREQn, and all signals configured as GPIO.

FB_CLK

G2

G1

GPIO Outputs

GPIO Inputs

G3

G4

Figure 35. GPIO timing

4.28 Rapid general purpose I/O timing specifications

RGPIO signals use a mix of pad types: pad_fsr, pad_msr, and pad_ssr. The following timing specifications assume a pad slew

rate setting of 11 and a load of 50 pF.

Table 39. RGPIO timing

Num

Characteristic

Min

Max

Unit

RG1 PST_CLK high to RGPIO output valid

RG2 PST_CLK high to RGPIO output Invalid

RG3 RGPIO input valid to PST_CLK high

RG4 PST_CLK high to RGPIO input invalid

—

0.5

6

ns

—

1.5

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

54

Freescale Semiconductor

Electrical characteristics

PST_CLK

RG2

RG1

RGPIO Outputs

RG3

RG4

RGPIO Inputs

Figure 36. RGPIO timing

4.29 JTAG and boundary scan timing specifications

All JTAG signals use pad type pad_msr except for TCLK which use pad type pad_fsr. The following timing specifications

1

assume a pad slew rate setting of 11 and a load of 50 pF.

Table 40. JTAG and boundary scan timing

Num

Characteristics¹

TCLK frequency of operation

Min

Max

Unit

J1

J2

J3

J4

J5

J6

J7

J8

J9

DC

40

20

—

4

25

—

3

MHz

ns

TCLK cycle period

TCLK clock pulse width

TCLK rise and fall times

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

—

13

—

12

0

20

—

4

J10 TMS, TDI input data hold time after TCLK rise

J11 TCLK low to TDO data valid

10

—

32

8

J12 TCLK low to TDO high-Z

J13 TRST assert time

—

J14 TRST setup time (negation) to TCLK high

1

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

55

Electrical characteristics

J2

J3

V_IH

TCLK

(input)

V_IL

J4

Figure 37. Test clock input timing

TCLK

V_IL

V_IH

J5

J6

Data Inputs

Input Data Valid

J7

J8

Data Outputs

Output Data Valid

Data Outputs

J7

Output Data Valid

Figure 38. Boundary scan (JTAG) timing

TCLK

V_IL

V_IH

J9

Input Data Valid

J10

TDI

TMS

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 39. Test access port timing

TCLK

TRST

J14

J13

Figure 40. TRST timing

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

56

Freescale Semiconductor

Electrical characteristics

4.30 Debug AC timing specifications

Table 41 lists specifications for the debug AC timing parameters shown in Figure 41 and Table 42.

All debug signals use pad type pad_msr except for PSTCLK which use pad type pad_fsr. The following timing specifications

1

assume a pad slew rate setting of 11 and a load of 50 pF.

Table 41. Debug AC timing specification

Num

Characteristic

Min

Max

Units

D0

D1

D2

D3

D4¹

D5

D6

PSTCLK cycle time

0.5

—

0.5

1

0.5

3.0

—

1/f_SYS

ns

PSTCLK rising to PSTDDATA valid

PSTCLK rising to PSTDDATA invalid

DSI-to-DSCLK setup

ns

—

PSTCLK

DSCLK-to-DSO hold

4

—

DSCLK cycle time

5

—

BKPT assertion time

1

—

1

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative

to the rising edge of PSTCLK.

D0

PSTCLK

D2

D1

PSTDDATA[7:0]

Figure 41. Real-time trace AC timing

D5

DSCLK

DSI

D3

Current

D4

Past

Current

Figure 42. BDM serial port AC timing

1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting

(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to

increase edge rise and fall times, thus reducing EMI.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

57

Package information

5

Package information

The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire.

Table 42 lists the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest

package outline drawings.

Table 42. Package information

Device

Package type

Case outline numbers

MCF54410

MCF54415

MCF54416

MCF54417

MCF54418

196 MAPBGA

98ASA00321D

256 MAPBGA

98ARH98219A

6

Product documentation

Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution

Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

58

Freescale Semiconductor

Revision history

7

Revision history

Table 43 summarizes revisions to this document.

Table 43. Revision history

Rev. No.

Date

Summary of changes

In Section 2.2, “Supply voltage sequencing” added the following note:

2

10 Jun 2009

NOTE

All I/O VDD pins must be powered on when the device is functioning,

except when in standby mode.

In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can

be switched off.

Added Section 3.2, “Pinout—169 MAPBGA” and Section 3.3, “Pinout—256 MAPBGA” and updated Table 5 with

pin locations.

In Section 4.1, “Absolute maximum ratings”:

• Added USB OTG, USB host, ADC, DAC/ADC, and RTC standby supply voltages

In Section 4.5, “DC electrical specifications”:

• Added RTC standby supply voltage

• Split out Power Supplies and I/O Characteristics to two separate tables

In Section 4.10, “FlexBus timing specifications”:

• Changed maximum frequency to 100MHz and updated specs throughout the table

• Changed FB2 maximum from 5 to 6

• Added notes to Figure 11 and Figure 12

In Section 4.12, “DDR SDRAM controller timing specifications”:

• Changed minimum frequency from 50 to 100

• Changed maximum DD1 from 20 to 10

• Changed DD5 from 2 to 0.5 x t_SDCK– 1

• Changed DD6 from 1.2 x t_SDCKto WL + 0.2 x t_SDCK

• Changed DD7 from 1.5 to 0.7

• Changed DD8 from 1.0 to 0.7

• Changed DD9 from 1.0 to 0.5

• Changed DD10 from 0.25 x t_SDCK+ 0.5 to 0.375 x t_SDCK

In Section 4.17, “SSI timing specifications”:

• Changed S7, S9, S15, and S17 from 10 to 15

In Section 4.22.2, “Transmit signal timing specifications”:

• Changed E5 for MII from 5 to 4

In Section 4.20, “mcPWM timing specifications”:

• Changed G2 from 2 to 1

In Section 4.24, “DSPI timing specifications”:

• Changed DS3 from (2 x 1/fsys) – 2.0 to (t_sck³ 2) – 2.0

• Changed DS4 from (2 x 1/fsys) – 3.0 to (t_sck³ 2) – 3.0

• Changed DS7 from 7 to 6

• Changed DS11 from 4 to 12

In Section 4.25, “SBF timing specifications”:

• Changed SB5 maximum from 5 to 3

• Changed SB6 minimum from –5 to 5

In Section 4.26, “1-Wire timing specifications”:

• Added link to 1-wire specs

In Section 4.27, “General purpose I/O timing specifications”:

• Changed G2 from 1.5 to 1

In Section 4.28, “Rapid general purpose I/O timing specifications”:

• Changed RG1 from 3 to 6

• Changed RG2 from 1.5 to 0.5

• Changed RG3 from 3 to 6

In Section 4.29, “JTAG and boundary scan timing specifications”:

• Changed J9-12 and J14 from TBD

In Section 4.30, “Debug AC timing specifications”:

• Changed D2 from 1.5 to 0.5

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor

59

Revision history

Table 43. Revision history (continued)

Summary of changes

Rev. No.

Date

3

31 July 2009 Changed 169MAPBGA package to 196MAPBGA throughout.

MCF54410 device now supports a single SSI module and one Ethernet controller with IEEE 1588

support

4

17 Aug 2009 Updated MCF5441x Signal Information and Muxing table with 196MAPBGA pin locations

Changed SD_Dn pin locations on 256 MAPBGA package

Added note to Section 4.6, “Output pad loading and slew rate”

5

6

29 Jan 2010 Added orderable part numbers

Swapped locations of RTC_EXTAL and RTC_XTAL pins in Table 5, Figure 7, and Figure 8

Corrected instances of MCF5445x to MCF5441x

Added thermal characteristic s to Table 7

Added case outline numbers to Table 42

Changed PLL supply voltage from “–0.5 to +2.0” to “–0.3 to +4.0” in Table 6

Miscellaneous corrections based on information from shared review comments by team members

7

8

October 2011 • Updated the pinouts in Table 5, “MCF5441x Signal information and muxing”.

• Updated the Figure 7, “MCF54410 Pinout (196 MAPBGA)”.

• Removed the symbol ADC_IN7/DAC1_OUT from Table 9, “Latch-up results”.

• Updated Table 11, “I/O electrical specifications”.

• Updated Table 13, “DDR pad drive strengths”.

June 2012

• In Table 7, added the thermal characteristics for the 196 MAPBGA package.

• In Table 42, updated the case outline number for the 196 MAPBGA package from “98ARH98217”

to “98ASA00321D”.

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8

60

Freescale Semiconductor

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Document Number: MCF54418

Rev. 8

06/2012


型号：	MCF54417CMJ250
厂家：	NXP
描述：	MCF5441x ColdFire Microprocessor Data Sheet
文件：	总61页 (文件大小：1257K)
中文：	中文翻译
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