MCF5445X [NXP]
MCF5445x ColdFire® Microprocessor Data Sheet;
| 型号： | MCF5445X |
| 厂家： | 
NXP |
| 描述： | MCF5445x ColdFire® Microprocessor Data Sheet |
| 文件： | 总49页 (文件大小：541K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
Document Number: MCF54455
Rev. 9, 04/2021
MCF54455
MAPBGA–256
17mm x 17mm
TEPBGA–360
23mm x 23mm
MCF5445x ColdFire®
Microprocessor Data Sheet
Features
®
• Version 4 ColdFire Core with MMU and EMAC
• Up to 410 Dhrystone 2.1 MIPS @ 266 MHz
• 16-KBytes instruction cache and 16-KBytes data cache
• 32-KBytes internal SRAM
• Support for booting from SPI-compatible flash, EEPROM,
and FRAM devices
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• 16-channel DMA controller
• 16-bit 133-MHz DDR/mobile-DDR/DDR2 controller
• USB 2.0 On-the-Go controller with ULPI support
• 32-bit PCI controller @ 66MHz
• ATA/ATAPI controller
• 2 10/100 Ethernet MACs
• Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
• Random number generator
• Synchronous serial interface (SSI)
• 4 periodic interrupt timers (PIT)
• 4 32-bit timers with DMA support
• DMA-supported serial peripheral interface (DSPI)
• 3 UARTs
2
• I C bus interface
NXP reserves the right to change the production detail specifications as may be required to
permit improvements in the design of its products.
Table of Contents
1
2
3
MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
5.9.1 Overshoot and Undershoot . . . . . . . . . . . . . . . 28
5.10 ULPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 29
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 30
5.12 I2C Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . 32
5.13 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 33
5.13.1 Receive Signal Timing Specifications . . . . . . . 33
5.13.2 Transmit Signal Timing Specifications . . . . . . . 34
5.13.3 Asynchronous Input Signal Timing
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5
3.1 Analog Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Oscillator Power Filtering . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . .7
3.3.2 Power-Down Sequence. . . . . . . . . . . . . . . . . . . .7
Pin Assignments and Reset States. . . . . . . . . . . . . . . . . . . . . .7
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3 Pinout—360 TEPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .19
5.5 ClockTiming Specifications . . . . . . . . . . . . . . . . . . . . . .20
5.6 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . .22
5.7 FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .23
5.8 SDRAM AC Timing Characteristics. . . . . . . . . . . . . . . .25
5.9 PCI Bus Timing Specifications . . . . . . . . . . . . . . . . . . .27
4
5
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.13.4 MII Serial Management Timing Specifications . 35
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 35
5.15 ATA Interface Timing Specifications. . . . . . . . . . . . . . . 36
5.16 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 36
5.17 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 38
5.18 General Purpose I/O Timing Specifications. . . . . . . . . 39
5.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40
5.20 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6
7
8
9
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
2
NXP Semiconductors
MCF54455
JTAG
Oscillator
PLL
Version 4 ColdFire Core
16K
Instruction
Cache
16K
Data
Cache
EMAC
BDM
MMU
2 FECs
USB OTG
Hardware
Divide
CAU
32K
SRAM
eDMA
PCI
Serial Boot
Crossbar Switch (XBS)
Peripheral Bridge
I2C
SDRAM
Controller
ATA
FlexBus
DSPI
SSI
RTC
RNG
GPIO
EPORT
4 PITs
Watchdog
2 INTCs
4 DMA
Timers
3 UARTs
LEGEND
ATA
BDM
CAU
DSPI
eDMA
EMAC
EPORT
FEC
– Advanced Technology Attachment Controller
– Background debug module
– Cryptography acceleration unit
– DMA serial peripheral interface
– Enhanced direct memory access
– Enchance multiply-accumulate unit
– Edge port module
– Fast Ethernet controller
– General Purpose Input/Output
– Inter-Intergrated Circuit
INTC
JTAG
MMU
PCI
– Interrupt controller
– Joint Test Action Group interface
– Memory management unit
– Peripheral Component Interconnect
– Programmable interrupt timers
– Phase locked loop module
– Random Number Generator
– Real time clock
PIT
PLL
RNG
RTC
SSI
GPIO
I2C
– Synchronous Serial Interface
USB OTG – Universal Serial Bus On-the-Go controller
Figure 1. MCF54455 Block Diagram
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
3
MCF5445x Family Comparison
1
MCF5445x Family Comparison
The following table compares the various device derivatives available within the MCF5445x family.
Table 1. MCF5445x Family Configurations
Module
MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455
ColdFire Version 4 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
•
•
•
•
•
•
Core (System) Clock
up to 240 MHz
up to 120 MHz
up to 266 MHz
up to 133 MHz
Peripheral Bus Clock
(Core clock 2)
External Bus Clock
(Core clock 4)
up to 60 MHz
up to 370
up to 66 MHz
up to 410
Performance (Dhrystone/2.1 MIPS)
Independent Data/Instruction Cache
Static RAM (SRAM)
16 Kbytes each
32 Kbytes
PCI Controller
—
—
•
—
—
•
•
•
•
—
•
•
•
Cryptography Acceleration Unit (CAU)
ATA Controller
—
—
•
•
—
•
—
•
•
DDR SDRAM Controller
FlexBus External Interface
USB 2.0 On-the-Go
•
•
•
•
•
•
•
•
•
•
•
•
•
•
UTMI+ Low Pin Interface (ULPI)
Synchronous Serial Interface (SSI)
Fast Ethernet Controller (FEC)
UARTs
•
•
•
•
•
•
•
•
•
•
•
•
1
3
•
1
3
•
2
3
•
2
3
•
2
3
•
2
3
•
I2C
DSPI
•
•
•
•
•
•
Real Time Clock
•
•
•
•
•
•
32-bit DMA Timers
4
•
4
•
4
•
4
•
4
•
4
•
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
General Purpose I/O (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
4
•
4
•
4
•
4
•
4
•
4
•
2
•
2
•
2
•
2
•
2
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
256 MAPBGA
360 TEPBGA
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
4
NXP Semiconductors
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Part Number
Description
Package
Speed
Temperature
MCF54450CVM180
MCF54450VM240
MCF54451CVM180
MCF54451VM240
MCF54452CVP200
MCF54452VP266
MCF54453CVP200
MCF54453VP266
MCF54454CVP200
MCF54454VP266
MCF54455CVP200
MCF54455VP266
180 MHz
240 MHz
180 MHz
240 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
–40 to +85 C
0 to +70 C
–40 to +85 C
0 to +70 C
–40 to +85 C
0 to +70 C
–40 to +85 C
0 to +70 C
–40 to +85 C
0 to +70 C
–40 to +85 C
0 to +70 C
MCF54450 Microprocessor
256 MAPBGA
MCF54451 Microprocessor
MCF54452 Microprocessor
MCF54453 Microprocessor
MCF54454 Microprocessor
MCF54455 Microprocessor
360 TEPBGA
3
Hardware Design Considerations
3.1
Analog Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for the analog V pins (VDD_A_PLL,
DD
VDD_RTC). The filter shown in Figure 2 should be connected between the board IV and the analog pins. The resistor and
DD
capacitors should be placed as close to the dedicated analog V pin as possible. The 10- resistor in the given filter is required.
DD
Do not implement the filter circuit using only capacitors. The analog power pins draw very little current. Concerns regarding
voltage loss across the 10-ohm resistor are not valid.
10
Board IVDD
Analog VDD Pin
10 µF
0.1 µF
GND
Figure 2. System Analog V Power Filter
DD
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
5
Hardware Design Considerations
3.2
Oscillator Power Filtering
Figure 3 shows an example for isolating the oscillator power supply from the I/O supply (EVDD) and ground.
10
VDD_OSC
VSS_OSC
EVDD Pin
1 µF
0.1 µF
100 MHz
GND
Figure 3. Oscillator Power Filter
3.3
Supply Voltage Sequencing
Figure 4 shows situations in sequencing the I/O V (EV ), SDRAM V (SDV ), PLL V (PV ), and internal
DD
DD
DD
DD
DD
DD
logic/core V (IV ).
DD
DD
EVDD (3.3V)
3.3V
Supplies Stable
2.5V
SDVDD (2.5V — DDR)
1.8V
1.5V
SDVDD (1.8V — DDR2)
IVDD, PVDD
0
Time
Notes:
1
Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PVDD) by more than 0.5V
at any time, including during power-up.
2
Use 50 V/millisecond or slower rise time for all supplies.
Figure 4. Supply Voltage Sequencing and Separation Cautions
The relationship between SDV and EV is non-critical during power-up and power-down sequences. SDV (2.5V or
DD
DD
DD
1.8V) and EV are specified relative to IV
.
DD
DD
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
6
NXP Semiconductors
Pin Assignments and Reset States
3.3.1
Power-Up Sequence
If EV /SDV are powered up with the IV at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected
DD
DD
DD
to the EV /SDV to be in a high impedance state. There is no limit on how long after EV /SDV powers up before IV
DD
DD
DD
DD
DD
must power up. The rise times on the power supplies should be slower than 50 V/millisecond to avoid turning on the internal
ESD protection clamp diodes.
3.3.2
Power-Down Sequence
If IV /PV are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
DD
DD
There is no limit on how long after IV and PV power down before EV or SDV must power down. There are no
DD
DD
DD
DD
requirements for the fall times of the power supplies.
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams. For a more detailed discussion
of the MCF5445x signals, consult the MCF54455 Reference Manual (MCF54455RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., FB_AD23), while designations for multiple signals within a
group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that
are muxed with GPIO default to their GPIO functionality. See Table 3 for a list of the
exceptions.
Table 3. Special-Case Default Signal Functionality
Pin
256 MAPBGA
360 TEPBGA
FB_AD[31:0]
FB_AD[31:0] except when serial boot selects 0-bit
boot port size.
FB_BE/BWE[3:0]
FB_CS[3:1]
FB_OE
FB_BE/BWE[3:0]
FB_CS[3:1]
FB_OE
FB_R/W
FB_R/W
FB_TA
FB_TA
FB_TS
FB_TS
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
7
Pin Assignments and Reset States
Table 3. Special-Case Default Signal Functionality (continued)
Pin
256 MAPBGA
360 TEPBGA
PCI_GNT[3:0]
PCI_REQ[3:0]
IRQ1
GPIO
GPIO
GPIO
PCI_GNT[3:0]
PCI_REQ[3:0]
PCI_INTA and
configured as an agent.
ATA_RESET
GPIO
ATA reset
Table 4. MCF5445x Signal Information and Muxing
MCF54452
MCF54453
MCF54454
MCF54450
MCF54451
Signal Name
GPIO
Alternate 1
Alternate 2
256 MAPBGA MCF54455
360 TEPBGA
Reset
I
EVDD
EVDD
L4
Y18
B17
RESET
—
—
—
—
—
—
U
O
M15
RSTOUT
—
Clock
I
EVDD
EVDD
M16
L16
A16
A17
EXTAL/PCI_CLK
XTAL
—
—
—
—
—
—
—
U3
O
Mode Selection
I
EVDD
M5, M7
AB17, AB21
BOOTMOD[1:0]
—
—
—
FlexBus
—
—
FB_AD[31:24]
FB_AD[23:16]
PFBADH[7:0]4
FB_D[31:24]
FB_D[23:16]
—
—
I/O
I/O
EVDD
EVDD
A14, A13, D12,
C12, B12, A12,
D11, C11
J2, K4, J1, K1–3,
L1, L4
PFBADMH[7:0]4
—
B11, A11, D10,
C10, B10,A10, D9,
C9
L2, L3, M1–4, N1–
2
PFBADML[7:0]4
PFBADL[7:0]4
FB_D[15:8]
FB_D[7:0]
—
—
—
—
I/O
I/O
EVDD B9,A9, D8, C8, B8, P1–2, R1–3, P4,
A8, D7, C7 T1–2
FB_AD[15:8]
FB_AD[7:0]
EVDD B7,A7, D6, C6, B6, T3–4, U1–3, V1–2,
A6, D5, C5
W1
O
O
O
O
O
O
O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
B5, A5
Y1, W2
FB_BE/BWE[3:2]
FB_BE/BWE[1:0]
FB_CLK
PBE[3:2]
PBE[1:0]
—
FB_TSIZ[1:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U
B4, A4
B13
W3, Y2
—
—
—
—
—
—
—
J3
W5, AA4, AB3
Y4
C2, D4, C3
C4
FB_CS[3:1]
FB_CS0
PCS[3:1]
—
A2
AA1
FB_OE
PFBCTL3
PFBCTL2
PFBCTL1
B2
AA3
FB_R/W
B1
AB2
FB_TA
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
8
NXP Semiconductors
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54452
MCF54453
MCF54454
MCF54450
MCF54451
Signal Name
GPIO
Alternate 1
Alternate 2
256 MAPBGA MCF54455
360 TEPBGA
O
EVDD
EVDD
A3
—
Y3
FB_TS
PFBCTL0
—
FB_ALE
FB_TBST
PCI Controller5
—
—
—
I/O
C11, D11, A10,
B10, J4, G2, G3,
F1, D12, C12, B12,
A11, B11, B9, D9,
D10, A8, B8, A5,
B5, A4, A3, B3, D4,
D3, E3–E1, F3, C2,
D2, C1
PCI_AD[31:0]
FB_A[31:0]
I/O
EVDD
K14–13, J15–13,
H13–15, G15–13,
F14–13, E15–13,
D16, B16, C15,
B15, C14, D15,
C16, D14
—
—
—
FB_A[23:0]
—
—
I/O
O
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
—
—
—
—
G4, E4, D1, B1
PCI_CBE[3:0]
PCI_DEVSEL
PCI_FRAME
PCI_GNT3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F2
B2
—
I/O
O
—
—
B7
PPCI7
PPCI[6:5]
PPCI4
ATA_DMACK
O
C8, C9
A9
PCI_GNT[2:1]
—
—
O
PCI_GNT0/
PCI_EXTREQ
I
I/O
I/O
I/O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
—
—
—
—
—
D5
C3
PCI_IDSEL
PCI_IRDY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C4
PCI_PAR
—
—
B4
PCI_PERR
PCI_REQ3
PCI_REQ[2:1]
—
—
C7
PPCI3
PPCI[2:1]
PPCI0
ATA_INTRQ
I
D7, C5
A2
—
—
I
PCI_REQ0/
PCI_EXTGNT
O
EVDD
EVDD
EVDD
EVDD
—
—
—
—
B6
A6
PCI_RST
PCI_SERR
PCI_STOP
PCI_TRDY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O
I/O
I/O
A7
C10
SDRAM Controller
O
SDVDD R1, P1, N2, P2,
R2, T2, M4, N3,
P3, R3, T3, T4, R4,
N4
V22, U20–22,
T19–22, R20–22,
N19, P20–21
SD_A[13:0]
—
—
—
—
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
9
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54452
MCF54453
MCF54454
MCF54450
MCF54451
Signal Name
GPIO
Alternate 1
Alternate 2
256 MAPBGA MCF54455
360 TEPBGA
O
O
O
O
O
O
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
P4, T5
T6
P22, P19
L19
SD_BA[1:0]
SD_CAS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N5
N22
SD_CKE
T9
L22
SD_CLK
T8
M22
SD_CLK
P6, R6
L20, M20
L21, K22, K21,
SD_CS[1:0]
SD_D[31:16]
I/O SDVDD N6, T7, N7, P7, R7,
R8, P8, N8, N9, K20, J20, J19, J21,
T10, R10, P10, J22, H20, G22,
N10, T11, R11, P11 G21, G20, G19,
F22, F21, F20
O
O
O
I
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
P9, N12
R9, N11
P5
H21, E21
H22, E22
N21
SD_DM[3:2]
SD_DQS[3:2]
SD_RAS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
M8
M21
SD_VREF
SD_WE
O
R5
N20
External Interrupts Port6
I
I
I
I
EVDD
EVDD
EVDD
EVDD
L1
L2
ABB13
ABB13
AB14
C6
IRQ7
IRQ4
IRQ3
IRQ1
PIRQ7
PIRQ4
PIRQ3
PIRQ1
—
—
—
—
SSI_CLKIN
—
—
—
—
—
L3
F15
PCI_INTA
—
FEC0
O
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
F3
F2
E1
F1
G1
G2
AB8
Y7
FEC0_MDC
FEC0_MDIO
FEC0_COL
PFECI2C3
PFECI2C2
PFEC0H4
PFEC0H0
PFEC0H3
PFEC0H2
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O
I
I
I
I
AB7
AA7
AA8
Y8
ULPI_DATA7
ULPI_DATA6
ULPI_DATA1
—
FEC0_CRS
FEC0_RXCLK
FEC0_RXDV
FEC0_RMII_
CRS_DV
I
I
I
I
EVDD
EVDD
EVDD
EVDD
G3, G4
H1
AB9, Y9
W9
FEC0_RXD[3:2]
FEC0_RXD1
FEC0_RXD0
FEC0_RXER
PFEC0L[3:2]
PFEC0L1
PFEC0H1
PFEC0L0
—
ULPI_DATA[5:4]
—
—
—
—
FEC0_RMII_RXD1
FEC0_RMII_RXD0
FEC0_RMII_RXER
—
—
—
H2
AB10
AA10
H3
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
10
NXP Semiconductors
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54452
MCF54453
MCF54454
MCF54450
MCF54451
Signal Name
GPIO
Alternate 1
Alternate 2
256 MAPBGA MCF54455
360 TEPBGA
I
EVDD
H4
Y10
FEC0_TXCLK
PFEC0H7
FEC0_RMII_
REF_CLK
—
—
O
O
O
O
O
EVDD
EVDD
EVDD
EVDD
EVDD
J1, J2
J3
W10, AB11
AA11
FEC0_TXD[3:2]
FEC0_TXD1
FEC0_TXD0
FEC0_TXEN
FEC0_TXER
PFEC0L[7:6]
PFEC0L5
PFEC0H5
PFEC0H6
PFEC0L4
—
ULPI_DATA[3:2]
—
—
—
—
—
FEC0_RMII_TXD1
FEC0_RMII_TXD0
FEC0_RMII_TXEN
—
—
J4
Y11
—
—
K1
W11
K2
AB12
ULPI_DATA0
FEC1
O
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
—
—
—
—
W20
Y22
FEC1_MDC
FEC1_MDIO
FEC1_COL
PFECI2C5
PFECI2C4
PFEC1H4
PFEC1H0
PFEC1H3
PFEC1H2
—
—
—
—
—
ATA_DIOR
ATA_DIOW
ATA_DATA7
ATA_DATA6
ATA_DATA5
ATA_DATA15
—
—
—
—
—
—
I/O
I
I
I
I
AB18
AA18
W14
AB15
FEC1_CRS
FEC1_RXCLK
FEC1_RXDV
FEC1_RMII_
CRS_DV
I
I
I
I
I
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
—
—
—
AA15, Y15
AA17
FEC1_RXD[3:2]
FEC1_RXD1
FEC1_RXD0
FEC1_RXER
FEC1_TXCLK
PFEC1L[3:2]
PFEC1L1
PFEC1H1
PFEC1L0
PFEC1H7
—
ATA_DATA[4:3]
ATA_DATA14
ATA_DATA13
ATA_DATA12
ATA_DATA11
—
—
—
—
—
FEC1_RMII_RXD1
FEC1_RMII_RXD0
FEC1_RMII_RXER
Y17
W17
AB19
FEC1_RMII_
REF_CLK
O
O
O
O
O
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
—
—
—
Y19, W18
AA19
FEC1_TXD[3:2]
FEC1_TXD1
FEC1_TXD0
FEC1_TXEN
FEC1_TXER
PFEC1L[7:6]
PFEC1L5
PFEC1H5
PFEC1H6
PFEC1L4
—
ATA_DATA[2:1]
ATA_DATA10
ATA_DATA9
ATA_DATA8
ATA_DATA0
—
—
—
—
—
FEC1_RMII_TXD1
FEC1_RMII_TXD0
FEC1_RMII_TXEN
—
Y20
AA21
AA22
USB On-the-Go
O
O
O
I
USB
VDD
F16
E16
E5
A14
A15
AA2
V4
USB_DM
USB_DP
—
—
—
—
—
USB
VDD
—
—
USB_PULLUP
—
—
USB
VDD
USB_VBUS_EN
USB_VBUS_OC
PUSB1
PUSB0
ULPI_NXT
ULPI_STP
—
UD7
USB
VDD
B3
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
11
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54452
MCF54453
MCF54454
MCF54450
MCF54451
Signal Name
GPIO
Alternate 1
Alternate 2
256 MAPBGA MCF54455
360 TEPBGA
ATA
O
O
O
O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
—
—
—
—
Y13
W21, W22
V19–21
W13
ATA_BUFFER_EN
ATA_CS[1:0]
ATA_DA[2:0]
ATA_RESET
ATA_DMARQ
ATA_IORDY
PATAH5
PATAH[4:3]
PATAH[2:0]
PATAL2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AA14
PATAL1
I
Y14
PATAL0
Real Time Clock
I
EVDD
EVDD
J16
A13
A12
EXTAL32K
XTAL32K
—
—
—
—
—
—
—
—
O
H16
SSI
O
I/O
I/O
I
EVDD
EVDD
EVDD
EVDD
EVDD
T13
R13
P12
T12
R12
D20
E19
E20
D21
D22
SSI_MCLK
SSI_BCLK
SSI_FS
PSSI4
PSSI3
PSSI2
PSSI1
PSSI0
—
—
—
—
—
—
—
—
U1CTS
U1RTS
U1RXD
U1TXD
—
SSI_RXD
SSI_TXD
UD
UD
O
I2C
I/O
I/O
EVDD
EVDD
K3
K4
AA12
Y12
I2C_SCL
I2C_SDA
PFECI2C1
PFECI2C0
—
—
U2TXD
U2RXD
U
U
DMA
EVDD
EVDD
EVDD
EVDD
M14
P16
N15
N16
C17
C18
A18
B18
O
I
DACK1
DREQ1
DACK0
DREQ0
PDMA3
PDMA2
PDMA1
PDMA0
—
ULPI_DIR
—
U
—
DSPI_PCS3
—
USB_CLKIN
O
I
—
—
—
U
DSPI
O
O
EVDD
EVDD
EVDD
EVDD
EVDD
N14
L13
P14
R16
R15
D18
A19
B20
D17
A20
DSPI_PCS5/PCSS
DSPI_PCS2
PDSPI6
PDSPI5
PDSPI4
PDSPI3
PDSPI2
—
—
—
—
—
—
—
—
—
—
U
O
DSPI_PCS1
SBF_CS
—
I/O
I/O
DSPI_PCS0/SS
DSPI_SCK
SBF_CK
—
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
12
NXP Semiconductors
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54452
MCF54453
MCF54454
MCF54450
MCF54451
Signal Name
GPIO
Alternate 1
Alternate 2
256 MAPBGA MCF54455
360 TEPBGA
8
I
EVDD
EVDD
P15
N13
B19
C20
DSPI_SIN
PDSPI1
PDSPI0
SBF_DI
—
—
O
DSPI_SOUT
SBF_DO
—
UARTs
I
O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
V3
U4
U1CTS
U1RTS
U1RXD
U1TXD
U0CTS
U0RTS
U0RXD
U0TXD
PUART7
PUART6
PUART5
PUART4
PUART3
PUART2
PUART1
PUART0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P3
O
I
—
N3
M3
M2
N1
M1
Y16
AA16
AB16
W15
O
I
O
Note: The UART1 and UART 2 signals are multiplexed on the DMA timers and I2C pins.
DMA Timers
I
I
I
I
EVDD
EVDD
EVDD
EVDD
C13
D13
B14
A15
H2
H1
H3
G1
DT3IN
DT2IN
DT1IN
DT0IN
PTIMER3
PTIMER2
PTIMER1
PTIMER0
DT3OUT
DT2OUT
DT1OUT
DT0OUT
U2RXD
U2TXD
U2CTS
U2RTS
—
—
—
—
BDM/JTAG9
O
EVDD E2, D1, F4, E3, D2,
C1, E4, D3
AA6, AB6, AB5,
W6, Y6, AA5, AB4,
Y5
PSTDDATA[7:0]
—
—
—
—
I
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
M11
P13
T15
T14
R14
M13
C21
C22
C19
A21
B21
B22
JTAG_EN
PSTCLK
DSI
—
—
—
—
—
—
—
—
—
—
—
—
—
D
—
U
TCLK
TDI
I
O
I
DSO
TDO
TMS
TRST
—
U
BKPT
I
DSCLK
U
Test
I
EVDD
EVDD
M6
AB20
D15
TEST
—
—
—
—
—
—
D
O
K16
PLLTEST
—
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
13
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54452
MCF54453
MCF54454
MCF54450
MCF54451
Signal Name
GPIO
Alternate 1
Alternate 2
256 MAPBGA MCF54455
360 TEPBGA
Power Supplies
E6–12, F5, F12
D6, D8, D14, F4,
H4, N4, R4, W4,
W7, W8, W12,
W16, W19
IVDD
—
—
—
—
—
—
—
—
—
—
—
G5, G12, H5, H12,
J5, J12, K5, K12, G11, G14, G16, J7,
D13, D19, G8,
EVDD
—
L5–6, L12
J16, L7, L16, N16,
P7, R16, T8, T12,
T14, T16
L7–11, M9, M10
F19, H19, K19,
M19, R19, U19
SD_VDD
—
—
—
—
—
—
L14
K15
B16
C14
VDD_OSC
VDD_A_PLL
VDD_RTC
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
M12
C13
A1, A16, F6–11,
A1, A22, B14, G7,
G6–11, H6–11, J6– G9–10, G12–13,
11, K6–11, T1, T16 G15, H7, H16, J9–
14, K7, K9–14,
K16, L9–14, M7,
M9–M14, M16, N7,
N9–14, P9–14,
P16, R7, T7, T9–
11, T13, T15, AB1,
AB22
L15
C16
VSS_OSC
—
—
—
—
—
—
1
2
3
4
5
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
Serial boot must select 0-bit boot port size to enable the GPIO mode on these pins.
When the PCI is enabled, all PCI bus pins come up configured as such. This includes the PCI_GNT and PCI_REQ lines, which have
GPIO. The IRQ1/PCI_INTA signal is a special case. It comes up as PCI_INTA when booting as a PCI agent and as GPIO when
booting as a PCI host.
For the 360 TEPBGA, booting with PCI disabled results in all dedicated PCI pins being safe-stated. The PCI_GNT and PCI_REQ
lines and IRQ1/PCI_INTA come up as GPIO.
6
GPIO functionality is determined by the edge port module. The pin multiplexing and control module is only responsible for assigning
the alternate functions.
7
8
9
Depends on programmed polarity of the USB_VBUS_OC signal.
Pull-up when the serial boot facility (SBF) controls the pin
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The pin multiplexing and control module is not
responsible for assigning these pins.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
14
NXP Semiconductors
Pin Assignments and Reset States
4.2
Pinout—256 MAPBGA
The pinout for the MCF54450 and MCF54451 packages are shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FB_BE/ FB_BE/ FB_AD FB_AD FB_AD FB_AD FB_AD FB_AD
BWE0 BWE2 10 14 18 22
FB_AD
26
FB_AD FB_AD
30 31
A
B
VSS
FB_OE FB_TS
USB_
T0IN
VSS
A
B
2
6
FB_BE/ FB_BE/ FB_AD FB_AD FB_AD FB_AD FB_AD FB_AD
BWE1 BWE3 11 15 19 23
FB_AD
27
FB_A
4
FB_A
6
FB_TA FB_R/W VBUS_
OC
FB_CLK T1IN
3
7
PST
DDATA2
FB_AD FB_AD FB_AD FB_AD FB_AD FB_AD FB_AD
FB_AD
28
FB_A
FB_A
5
FB_A
1
C
D
FB_CS3 FB_CS1 FB_CS0
T3IN
3
C
D
0
4
8
12
16
20
24
PST
PST
PST
FB_AD FB_AD FB_AD FB_AD FB_AD FB_AD FB_AD
FB_AD
29
FB_A
FB_A
2
FB_A
7
FB_CS2
T2IN
0
DDATA6 DDATA3 DDATA0
1
5
9
13
17
21
25
USB_
VBUS_
EN
FEC0_
COL
PST
PST
PST
FB_A
8
FB_A
9
FB_A
10
USB_
DP
E
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
E
DDATA7 DDATA4 DDATA1
FEC0_ FEC0_ FEC0_
PST
FB_A
11
FB_A
12
USB_
DM
F
G
H
J
IVDD
EVDD
EVDD
EVDD
EVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
IVDD
EVDD
EVDD
EVDD
EVDD
EVDD
IRQ_1
F
G
H
J
CRS
MDIO
MDC DDATA5
FEC0_ FEC0_ FEC0_ FEC0_
RXCLK RXDV RXD3 RXD2
FB_A
13
FB_A
14
FB_A
15
NC
FEC0_ FEC0_ FEC0_ FEC0_
RXD1 RXD0 RXER TXCLK
FB_A
18
FB_A
17
FB_A
16
XTAL
32K
FEC0_ FEC0_ FEC0_ FEC0_
FB_A
19
FB_A
20
FB_A
21
EXTAL
32K
TXD3
TXD2
TXD1
TXD0
FEC0_ FEC0_
I2C_
SCL
I2C_
SDA
FB_A
22
FB_A
23
VDD_A
_PLL
PLL
TEST
K
L
K
L
TXEN
IRQ_7
TXER
IRQ_4
DSPI_
PCS2
VDD_
OSC
VSS_
OSC
IRQ_3 RESET EVDD
BOOT
EVDD SDVDD SDVDD SDVDD SDVDD SDVDD
XTAL
BOOT
MOD0
SD_
VREF
JTAG_
EN
VDD_
RTC
RST
OUT
M
U0TXD U0RTS U0CTS SD_A7
U0RXD SD_A11 SD_A6 SD_A0
SD_A12 SD_A10 SD_A5 SD_BA1
TEST
SDVDD SDVDD
TRST DACK1
EXTAL
M
N
P
R
T
MOD1
SD_
CKE
SD_
DQS2
DSPI_
SOUT
DSPI_
PCS5
N
P
SD_D31 SD_D29 SD_D24 SD_D23 SD_D19
SD_DM2
DACK0 DREQ0
SD_
RAS
SD_
CS1
SD_
DM3
DSPI_
PCS1
DSPI_
DREQ1
SIN
SD_D28 SD_D25
SD_D27 SD_D26
SD_D20 SD_D16 SSI_FS
SD_D21 SD_D17 SSI_TXD
SD_D22 SD_D18 SSI_RXD
TCLK
SD_
CS0
SD_
DQS3
SSI_
BCLK
DSPI_
SCK
DSPI_
PCS0
R
T
SD_A13 SD_A9 SD_A4 SD_A1 SD_WE
TMS
SD_
CAS
SD_
SD_D30
SD_
CLK
SSI_
MCLK
VSS
SD_A8 SD_A3 SD_A2 SD_BA0
TDO
TDI
VSS
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 5. MCF54450 and MCF54451 Pinout (256 MAPBGA)
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
15
Pin Assignments and Reset States
4.3
Pinout—360 TEPBGA
The pinout for the MCF54452, MCF54453, MCF54454, and MCF54455 packages are shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PCI_
REQ0
PCI_
AD10
PCI_
AD11
PCI_
AD13
PCI_
SERR
PCI_
STOP
PCI_
AD15
PCI_
GNT0
PCI_
AD29
PCI_
AD20
XTAL
32K
EXTAL
32K
USB_
DM
USB_
DP
DSPI_
PCS2
DSPI_
SCK
A
B
C
D
E
F
GND
EXTAL
XTAL
DACK0
TDO
GND
A
B
C
D
E
F
PCI_
CBE0
PCI_
FRAME
PCI_
AD9
PCI_
PERR
PCI_
AD12
PCI_
RST
PCI_
GNT3
PCI_
AD14
PCI_
AD18
PCI_
AD28
PCI_
AD19
PCI_
AD21
VDD_
OSC
RST
OUT
DSPI_
SIN
DSPI_
PCS1
NC
GND
NC
NC
DREQ0
TMS
TRST
TCLK
PCI_
AD0
PCI_
AD2
PCI_
IRDY
PCI_
PAR
PCI_
REQ1
PCI_
REQ3
PCI_
GNT2
PCI_
GNT1
PCI_
TRDY
PCI_
AD31
PCI_
AD22
VDD_
RTC
VDD_
A_PLL
VSS_
OSC
DSPI_
SOUT
JTAG_
EN
IRQ1
IVDD
DACK1 DREQ1
TDI
PCI_
CBE1
PCI_
AD1
PCI_
AD7
PCI_
AD8
PCI_
IDSEL
PCI_
REQ2
PCI_
AD17
PCI_
AD16
PCI_
AD30
PCI_
AD23
PLL
TEST
DSPI_
PCS0
DSPI_
PCS5
SSI_
MCLK
SSI_
RXD
SSI_
TXD
IVDD
EVDD
IVDD
NC
EVDD
PCI_
AD4
PCI_
AD5
PCI_
AD6
PCI_
CBE2
SSI_
BCLK
SD_
DM2
SD_
DQS2
SSI_FS
PCI_
AD24
PCI_DE
VSEL
PCI_
AD3
IVDD
SDVDD SD_D16 SD_D17 SD_D18
SD_D19 SD_D20 SD_D21 SD_D22
PCI_
AD26
PCI_
AD25
PCI_
CBE3
G
H
J
T0IN
T2IN
GND
GND
EVDD
GND
EVDD
GND
GND
EVDD
GND
GND
EVDD
GND
GND
EVDD
GND
GND
EVDD
GND
EVDD
GND
G
H
J
SD_
DM3
SD_
DQS3
T3IN
T1IN
IVDD
SDVDD SD_D23
FB_AD FB_AD
29 31
PCI_
AD27
FB_CLK
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EVDD
GND
SD_D26 SD_D27 SD_D25 SD_D24
SDVDD SD_D28 SD_D29 SD_D30
FB_AD FB_AD FB_AD FB_AD
28 27 26 30
K
L
K
L
FB_AD FB_AD FB_AD FB_AD
25 23 22 24
SD_
CAS
SD_
CS1
SD_
CLK
EVDD
GND
SD_D31
FB_AD FB_AD FB_AD FB_AD
SD_
CS0
SD_
VREF
SD_
CLK
M
N
P
R
T
SDVDD
M
N
P
R
T
21
20
19
18
FB_AD FB_AD
17 16
SD_
RAS
SD_
CKE
U1TXD
IVDD
EVDD
GND
SD_A2 SD_WE
FB_AD FB_AD
15 14
FB_AD
10
SD_
BA0
SD_
BA1
U1RXD
SD_A1 SD_A0
FB_AD FB_AD FB_AD
13 12 11
IVDD
EVDD
EVDD
SDVDD SD_A5 SD_A4 SD_A3
SD_A9 SD_A8 SD_A7 SD_A6
SDVDD SD_A12 SD_A11 SD_A10
FB_AD FB_AD FB_AD FB_AD
EVDD
GND
GND
GND
EVDD
GND
EVDD
GND
9
8
7
6
FB_AD FB_AD FB_AD
U
U1RTS
USB_
U
5
4
3
FB_AD FB_AD
ATA_
DA2
ATA_
DA1
ATA_
DA0
V
W
Y
U1CTS VBUS_
OC
SD_A13
V
W
Y
2
1
FB_AD FB_BE/ FB_BE/
BWE2 BWE1
PST
DDATA4
FEC0_
RXD1
FEC0_
TXD3
FEC0_
TXEN
ATA_
RESET RXCLK
FEC1_
FEC1_
RXER
FEC1_
TXD2
FEC1_
MDC
ATA_
CS1
ATA_
CS0
IVDD
FB_CS3
PST
IVDD
IVDD
IVDD
U0TXD
IVDD
IVDD
0
ATA_BU
ATA_
FB_BE/ FB_BE/
PST
FEC0_
FEC0_
RXDV
FEC0_
RXD2
FEC0_
TXCLK
FEC0_
TXD0
I2C_
SDA
FEC1_
RXD2
FEC1_
RXD0
FEC1_
TXD3
FEC1_
TXD0
FEC1_
MDIO
FB_TS FB_CS0
FFER_
IORDY
EN
U0CTS
RESET
NC
BWE3
BWE0
DDATA0 DDATA3 MDIO
USB_
PST
PST
FEC0_
CRS
FEC0_
RXCLK
FEC0_
RXER
FEC0_
TXD1
I2C_
SCL
ATA_
IRQ4
FEC1_
DMARQ RXD3
FEC1_
RXD1
FEC1_
CRS
FEC1_
TXD1
FEC1_
TXEN
FEC1_
TXER
AA
AB
FB_OE VBUS_ FB_R/W FB_CS2
EN
NC
U0RTS
NC
AA
AB
DDATA2 DDATA7
PST
PST
PST
FEC0_
COL
FEC0_
MDC
FEC0_
RXD3
FEC0_
RXD0
FEC0_
TXD2
FEC0_
TXER
FEC1_
IRQ3
BOOT
MOD1
FEC1_
COL
FEC1_
TXCLK
BOOT
MOD0
GND
FB_TA FB_CS1
IRQ7
U0RXD
TEST
GND
DDATA1 DDATA5 DDATA6
RXDV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 6. MCF54452, MCF54453, MCF54454, and MCF54455 Pinout (360 TEPBGA)
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
16
NXP Semiconductors
Electrical Characteristics
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF54455 microprocessor. This
section contains detailed information on DC/AC electrical characteristics and AC timing specifications.
The electrical specifications are preliminary and from previous designs or design simulations. These specifications may not be
fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications will
be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Absolute Maximum Ratings
1, 2
Table 5. Absolute Maximum Ratings
Rating
Symbol
Pin Name
Value
Units
External I/O pad supply voltage
Internal oscillator supply voltage
Real-time clock supply voltage
Internal logic supply voltage
SDRAM I/O pad supply voltage
PLL supply voltage
EVDD
OSCVDD
RTCVDD
IVDD
EVDD
VDD_OSC
VDD_RTC
IVDD
-0.3 to +4.0
-0.3 to +4.0
-0.5 to +2.0
-0.5 to +2.0
-0.3 to +4.0
-0.5 to +2.0
-0.3 to +3.6
25
V
V
V
V
SDVDD
PVDD
VIN
SD_VDD
VDD_A_PLL
—
V
V
Digital input voltage3
V
Instantaneous maximum current
IDD
—
mA
Single pin limit (applies to all pins) 3, 4, 5
Operating temperature range (packaged)
TA
(TL - TH)
—
—
-40 to +85
C
C
Storage temperature range
Tstg
-55 to +150
1
2
Functional operating conditions are given in Table 8. Absolute maximum ratings are stress ratings only, and functional
operation at the maximum is not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is
advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level
(e.g., VSS or EVDD).
3
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, and then use the larger of the two values.
4
5
All functional non-supply pins are internally clamped to VSS and EVDD
.
Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD
and could result in external power supply going out of regulation. Ensure the external EVDD load shunts current greater
than maximum injection current. This is the greatest risk when the MPU is not consuming power (ex; no clock). The power
supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current
conditions.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
17
Electrical Characteristics
5.2
Thermal Characteristics
Table 6. Thermal Characteristics
256
MAPBGA
360
TEPBGA
Characteristic
Symbol
Unit
Junction to ambient, natural convection
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
JA
291,2
241,2
C/W
Four layer board
(2s2p)
JMA
251,2
211,2
C/W
Junction to board
JB
JC
jt
Tj
183
104
21,5
105
153
114
21,5
105
C/W
C/W
C/W
oC
Junction to case
Junction to top of package
Maximum operating junction temperature
1
JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
NXP recommends the use of JmA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance
to the device junction temperature specification can be verified by physical measurement in the customer’s
system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard
51-2.
2
3
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
4
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written in conformance with Psi-JT.
The average chip-junction temperature (T ) in C can be obtained from:
J
TJ = TA + PD JMA
Eqn. 1
Where:
TA
= Ambient Temperature, C
QJMA
PD
= Package Thermal Resistance, Junction-to-Ambient, C/W
= PINT + PI/O
PINT
PI/O
= IDD IVDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
For most applications P < P
and can be ignored. An approximate relationship between P and T (if P is neglected) is:
D J I/O
I/O
INT
K
--------------------------------
PD
=
Eqn. 2
TJ + 273C
Solving equations 1 and 2 for K gives:
K = PD TA 273C + QJMA P2D
Eqn. 3
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
18
NXP Semiconductors
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
5.3
ESD Protection
1, 2
Table 7. ESD Protection Characteristics
Characteristics
Symbol
Value
Units
ESD Target for Human Body Model
HBM
2000
V
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 8. DC Electrical Specifications
Characteristic
Internal logic supply voltage1
Symbol
Min
Max
Units
IVDD
PVDD
EVDD
OSCVDD
RTCVDD
SDVDD
SDVDD
SDVDD
SDVREF
VIH
1.35
1.35
3.0
1.65
1.65
3.6
V
V
PLL analog operation voltage range 1
External I/O pad supply voltage
Internal oscillator supply voltage
Real-time clock supply voltage
SDRAM I/O pad supply voltage — DDR mode
SDRAM I/O pad supply voltage — DDR2 mode
SDRAM I/O pad supply voltage — Mobile DDR mode
SDRAM input reference voltage
Input High Voltage
V
3.0
3.6
V
1.35
2.25
1.7
1.65
2.75
1.9
V
V
V
1.7
1.9
V
0.49 x SDVDD 0.51 x SDVDD
V
0.7 x EVDD
VSS – 0.3
0.06 x EVDD
–2.5
3.65
0.35 x EVDD
—
V
Input Low Voltage
VIL
V
Input Hysteresis
VHYS
mV
A
Input Leakage Current2
Iin
2.5
Vin = VDD or VSS, Input-only pins
Input Leakage Current3
Iin
–5
–10.0
5
10.0
A
A
V
Vin = VDD or VSS, Input-only pins
High Impedance (Off-State) Leakage Current4
Vin = VDD or VSS, All input/output and output pins
IOZ
Output High Voltage (All input/output and all output pins)
VOH
VOL
0.85 EVDD
__
__
IOH = –5.0 mA
Output Low Voltage (All input/output and all output pins)
0.15 EVDD
V
IOL = 5.0mA
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
19
Electrical Characteristics
Table 8. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Units
Weak Internal Pull Up Device Current, tested at VIL Max.5
IAPU
Cin
–10
–130
A
Input Capacitance 6
pF
All input-only pins
All input/output (three-state) pins
—
—
7
7
Load Capacitance
Low drive strength
High drive strength
pF
CL
IIC
25
50
DC Injection Current 3, 7, 8, 9
mA
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
-1.0
-10
1.0
10
1
IVDD and PVDD should be at the same voltage. PVDD should have a filtered input. Please see the PLL section of this
specification for an example circuit. There are three PVDD inputs, one for each PLL. A filter circuit should used on each
PVDD input.
2
3
4
Valid for all parts, EXCEPT the MCF54452YVR200.
Valid just the MCF54452YVR200 part number.
Worst-case tristate leakage current with only one I/O pin high. Since all I/Os share power when high, the leakage current
is distributed among them. With all I/Os high, this spec reduces to ±2 A min/max.
Refer to the MCF54455 Reference Manual signals description chapter for pins having weak internal pull-up devices.
5
6
7
8
This parameter is characterized before qualification rather than 100% tested.
All functional non-supply pins are internally clamped to VSS and their respective VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
9
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure the external VDD load shunts current greater
than the maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up,
the system clock is not present during the power-up sequence until the PLL has attained lock.
5.5
ClockTiming Specifications
The clock module configures the device for one of several clocking methods. Clocking modes include internal phase-locked
loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier.
The PLL can also be disabled, and an external oscillator can directly clock the device.
The specifications in Table 9 are for the CLKIN input pin (EXTAL input driven by an external clock reference). The duty cycle
specification is based on an acceptable tolerance for the PLL, which yields 50% duty-cycle internal clocks to all on-chip
peripherals. The MCF5445x devices use the input clock signal as its synchronous bus clock for PCI. A poor duty cycle on the
input clock, may affect the overall timing margin to external devices. If negative edge logic is used to interface to PCI, providing
a 50% duty-cycle input clock aids in simplifying overall system design.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
20
NXP Semiconductors
Electrical Characteristics
Unit
Table 9. Input Clock Timing Requirements
Item
Specification
Min
Max
C1
Cycle time
15
25
-
40
66.66
2
ns
MHz
ns
1 / C1 Frequency
C2
C3
C4
Rise time (20% of vdd to 80% of vdd)
Fall time (80% of vdd to 20% of vdd)
Duty cycle (at 50% of vdd)
-
2
ns
40
60
%
C1
Input Clock (CLKIN)
C4
C4
C2
C3
Figure 7. Input Clock Timing Diagram
Table 10. PLL Electrical Characteristics
Min.
Value
Max.
Unit
Num
Characteristic
Symbol
Value
1
PLL Reference Frequency Range
Crystal reference
fref_crystal
fref_ext
16
16
40
66.66
MHz
MHz
External reference
2
Core/System Frequency
fsys
tsys
fvco
tcst
512 Hz1
266.67 MHz
1/fsys
—
ns
Core/System Clock Period
VCO Frequency (fvco = fref PFDR)
Crystal Start-up Time2, 3
—
19
3
300
—
540
MHz
ms
10
4
EXTAL Input High Voltage
Crystal Mode4
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
All other modes (External, Limp)
5
6
EXTAL Input Low Voltage
Crystal Mode4
All other modes (External, Limp)
VILEXT
VILEXT
—
—
VXTAL - 0.4
EVDD/2 - 0.4
V
V
EXTAL Input Rise & Fall Time (20% to 80% EVDD
(External, Limp)
)
1
2
ns
7
8
PLL Lock Time 3, 5
tlpll
tdc
IXTAL
CS_XTAL
—
40
1
50000
60
CLKIN
%
Duty Cycle of reference 3 (External, Limp)
9
XTAL Current
3
mA
pF
10
Total on-chip stray capacitance on XTAL
—
1.5
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
21
Electrical Characteristics
Table 10. PLL Electrical Characteristics (continued)
Min.
Max.
Value
Num
Characteristic
Symbol
Unit
Value
11
12
13
Total on-chip stray capacitance on EXTAL
Crystal capacitive load
CS_EXTAL
CL
—
1.5
pF
See crystal spec
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
—
2 (CL -
CS_XTAL -
pF
CS_EXTAL
-
6
CS_PCB
)
14
15
17
Frequency un-LOCK Range
Frequency LOCK Range
fUL
-4.0
-2.0
4.0
% fsys
% fsys
fLCK
Cjitter
2.0
CLKOUT Period Jitter, 3, 4, 7 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
—
10
% FB_CLK
1
2
The minimum system frequency is the minimum input clock divided by the maximum low-power divider (16 MHz 32,768).
When the PLL is enabled, the minimum system frequency (fsys) is 150 MHz.
This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock
reference only.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL.
3
4
5
6
7
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval.
5.6
Reset Timing Specifications
Table 11 lists specifications for the reset timing parameters shown in Figure 8.
Table 11. Reset and Configuration Override Timing
Num
Characteristic
Min
Max
Unit
R11 RESET valid to CLKIN (setup)
9
1.5
5
—
—
—
10
—
—
—
1
ns
R2 CLKIN to RESET invalid (hold)
ns
CLKIN cycles
ns
R3 RESET valid time2
R4 CLKIN to RSTOUT valid
—
0
R5 RSTOUT valid to Configuration Override inputs valid
R6 Configuration Override inputs valid to RSTOUT invalid (setup)
R7 Configuration Override inputs invalid after RSTOUT invalid (hold)
R8 RSTOUT invalid to Configuration Override inputs High Impedance
ns
20
0
CLKIN cycles
ns
—
CLKIN cycles
1
2
RESET and Configuration Override data lines are synchronized internally. Setup and hold times must be met only if
recognition on a particular clock is required.
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously
to the system. Thus, RESET must be held a minimum of 100 ns.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
22
NXP Semiconductors
Electrical Characteristics
CLKIN
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R7
R5
R6
Configuration Overrides*:
(BOOTMOD[1:0],
Override pins])
Figure 8. RESET and Configuration Override Timing
5.7
FlexBus Timing Specifications
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices, a simple chip-select based interface can be used.
All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a
reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock
(FB_CLK). All other timing relationships can be derived from these values.
Table 12. FlexBus AC Timing Specifications
Num
Characteristic
Frequency of Operation
Min
Max
Unit
Notes
25
15
—
66.66
40
MHz
ns
FB1 Clock Period
FB2 Output Valid
FB3 Output Hold
FB4 Input Setup
FB5 Input Hold
1
7.0
—
ns
1.0
3.0
0
ns
1
2
—
ns
—
ns
2
1
2
Specification is valid for all FB_AD[31:0], FB_BS[3:0], FB_CS[3:0], FB_OE, FB_R/W, FB_TBST,
FB_TSIZ[1:0], and FB_TS.
Specification is valid for all FB_AD[31:0] and FB_TA.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and PCI
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
23
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[Y:0]
FB_AD[Y:0]
Mux’d Bus
FB2
FB5
ADDR[31:X]
FB_AD[31:X]
DATA
FB4
ADDR[31:0]
FB_A[31:0]
Non-Mux’d Bus
FB_D[31:X]
ADDR[31:X]
DATA
FB_R/W
FB_ALE
FB_CSn, FB_OE,
FB_BE/BWEn
FB4
FB5
FB_TA
TSIZ[1:0]
FB_TSIZ[1:0]
Figure 9. FlexBus Read Timing
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[Y:0]
FB_AD[Y:0]
Mux’d Bus
FB2
FB_AD[31:X]
ADDR[31:X]
DATA
ADDR[31:0]
FB_A[31:0]
FB_D[31:X]
FB_R/W
Non-Mux’d Bus
ADDR[31:X]
DATA
FB_ALE
FB_CSn, FB_BE/BWEn
FB_OE
FB4
FB5
FB_TA
TSIZ[1:0]
FB_TSIZ[1:0]
Figure 10. Flexbus Write Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
24
NXP Semiconductors
Electrical Characteristics
5.8
SDRAM AC Timing Characteristics
The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing
numbers are relative to the four DQS byte lanes.
Table 13. SDRAM Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
Notes
1
60
7.5
133.33
16.67
0.55
MHz
ns
DD1 Clock Period
tSDCK
tSDCKH
tSDCKL
tCMV
2
DD2 Pulse Width High
DD3 Pulse Width Low
0.45
0.45
—
tSDCK
tSDCK
ns
0.55
3
3
DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] — Output Valid
(0.5 x tSDCK
)
)
+ 1.0ns
DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] — Output Hold
tCMH
tDQSS
tQS
2.0
—
ns
ns
ns
ns
DD6 Write Command to first DQS Latching Transition
(1.0 x tSDCK
)
(1.0 x tSDCK
+ 0.6ns
- 0.6ns
4
5
DD7 Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
1.0
1.0
—
—
6
DD8 Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tQH
—
7
8
DD9 Input Data Skew Relative to DQS (Input Setup)
DD10 Input Data Hold Relative to DQS.
tIS
tIH
1.0
—
ns
ns
(0.25 x tSDCK
)
+ 0.5ns
1
2
3
The SDRAM interface operates at the same frequency as the internal system bus.
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (tSDCK) plus some minor adjustments for process, temperature, and
voltage variations.
4
This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
5
6
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid
for each subsequent DQS edge.
This specification relates to the required hold time of DDR memories.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
7
8
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes
valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
25
Electrical Characteristics
DD1
DD2
SD_CLK
SD_CLK
DD3
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
DD6
SD_A[13:0]
COL
DD7
SD_DM3/SD_DM2
SD_DQS3/SD_DQS2
DD8
DD7
WD1 WD2 WD3 WD4
DD8
SD_D[31:24]/SD_D[23:16]
Figure 11. DDR Write Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
26
NXP Semiconductors
Electrical Characteristics
DD1
DD2
SD_CLK
SD_CLK
DD3
DD5
CL=2
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
CL=2.5
SD_A[13:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD10
WD1 WD2 WD3 WD4
DQS Read DQS Read
Preamble Postamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 12. DDR Read Timing
5.9
PCI Bus Timing Specifications
The PCI bus on the device is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Refer to the
PCI 2.2 spec for a more detailed timing analysis.
1 2
,
Table 14. PCI Timing Specifications
33 MHz3
66 MHz3
Num
Characteristic
Min
Max
Min
Max
Unit
Frequency of Operation
Clock Period
—
30
33.33 33.33 66.66
MHz
ns
P1
P2
P3
P4
P5
—
—
15
3.0
5.0
0
30
—
Bused PCI signals — input setup
PCI_GNT[3:0]/PCI_REQ[3:0] — input setup
All PCI signals — input hold
7.0
10.0
0
ns
—
—
ns
—
—
ns
Bused PCI signals — output valid
—
11.0
—
6.0
ns
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
27
Electrical Characteristics
1 2
,
Table 14. PCI Timing Specifications (continued)
33 MHz3
66 MHz3
Num
Characteristic
Min
Max
Min
Max
Unit
P6
P7
PCI_REQ[3:0]/PCI_GNT[3:0] — output valid
All PCI signals — output hold
—
12.0
—
—
6.0
—
ns
ns
2.0
1.0
1
2
The PCI bus operates at the CLKIN frequency. All timings are relative to the input clock, CLKIN.
All PCI signals are bused signals except for PCI_GNT[3:0] and PCI_REQ[3:0]. These signals are defined as point-to-point
signals by the PCI Specification.
3
The 66-MHz parameters are only guaranteed when the 66-MHz PCI pad slew rates are selected. Likewise, the 33-MHz
parameters are only guaranteed when the 33-MHz PCI pad slew rates are selected.
P1
CLKIN
P5
P7
P6
Output
Output Valid
Valid/Hold
P2
P3
P4
Input
Setup/Hold
Input Valid
Figure 13. PCI Timing
5.9.1
Overshoot and Undershoot
Figure 14 shows the specification limits for overshoot and undershoot for PCI I/O. To guarantee long term reliability, the
specification limits shown must be followed. Good transmission line design practices should be observed to guarantee the
specification limits.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
28
NXP Semiconductors
Electrical Characteristics
VDD + 0.9V
VDD + 0.5V
VDD
GND
GND - 0.5V
GND - 1.0V
Not to exceed 17%
of PCI Cycle
Figure 14. Overshoot and Undershoot Limits
5.10 ULPI Timing Specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing
requirements for the ULPI pins are given in Table 15. These timings apply to synchronous mode only. All timings are measured
with respect to the clock as seen at the USB_CLKIN pin on the MCF5445x. The ULPI PHY is the source of the 60MHz clock.
NOTE
The USB controller requires a 60-MHz clock, even if using the on-chip FS/LS transceiver
instead of the ULPI interface. In this case, the 60-MHz clock can be generated by the PLL
or input on the USB_CLKIN pin.
Table 15. ULPI Interface Timing
Num
Characteristic
Min
Nominal
Max
Units
USB_CLKIN operating frequency
USB_CLKIN duty cycle
—
—
60
50
—
—
—
—
—
9.5
—
MHz
%
U1
U2
U3
U4
U5
USB_CLKIN clock period
—
16.67
—
ns
Input Setup (control and data)
Input Hold (control and data)
Output Valid (control and data)
Output Hold (control and data)
5.0
1.0
—
ns
—
ns
—
ns
1.0
—
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
29
Electrical Characteristics
U1
USB_CLKIN
U2
U3
ULPI_DIR / ULPI_NXT
(Control Input)
U2
U3
ULPI_DATA[7:0]
(Data Input)
U4
U5
ULPI_STP
(Control Output)
U5
U4
ULPI_DATA[7:0]
(Data Output)
Figure 15. ULPI Timing Diagram
5.11 SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
1
Table 16. SSI Timing — Master Modes
Num
Description
Symbol
Min
Max
Units
Notes
2
S1
S2
S3
S4
S5
S6
S7
S8
S9
SSI_MCLK cycle time
tMCLK 2 tSYS
—
55%
—
ns
tMCLK
ns
SSI_MCLK pulse width high / low
SSI_BCLK cycle time
45%
3
tBCLK 8 tSYS
SSI_BCLK pulse width
45%
—
0
55%
15
tBCLK
ns
SSI_BCLK to SSI_FS output valid
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
—
ns
—
-2
15
ns
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
—
ns
10
0
—
ns
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK
—
ns
1
2
3
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (fsys).
SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (fsys).
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
30
NXP Semiconductors
Electrical Characteristics
1
Table 17. SSI Timing — Slave Modes
Num
Description Symbol
Min
Max
Units
Notes
S11 SSI_BCLK cycle time
tBCLK 8 tSYS
—
55%
—
ns
tBCLK
ns
S12 SSI_BCLK pulse width high / low
S13 SSI_FS input setup before SSI_BCLK
S14 SSI_FS input hold after SSI_BCLK
S15 SSI_BCLK to SSI_TXD / SSI_FS output valid
45%
10
2
—
ns
—
0
15
ns
S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
—
ns
S17 SSI_RXD setup before SSI_BCLK
S18 SSI_RXD hold after SSI_BCLK
10
2
—
—
ns
ns
1
All timings specified with a capactive load of 25pF.
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S8
S7
S8
SSI_TXD
SSI_RXD
S9
S10
Figure 16. SSI Timing — Master Modes
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
31
Electrical Characteristics
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
SSI_RXD
S17
S18
Figure 17. SSI Timing — Slave Modes
2
5.12 I C Timing Specifications
2
Table 18 lists specifications for the I C input timing parameters shown in Figure 18.
2
Table 18. I C Input Timing Specifications between SCL and SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I1
I2
I3
I4
I5
I6
I7
I8
I9
2
8
—
—
1
tSYS
tSYS
ms
Clock low period
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
—
1
ns
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4
ms
—
—
—
—
tSYS
ns
Data setup time
0
Start condition setup time (for repeated start condition only)
Stop condition setup time
2
tSYS
tSYS
2
2
Table 19 lists specifications for the I C output timing parameters shown in Figure 18.
2
Table 19. I C Output Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I11
I21
I32
I41
I53
Start condition hold time
Clock low period
6
10
—
7
—
—
—
—
3
tSYS
tSYS
µs
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
tSYS
ns
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
32
NXP Semiconductors
Electrical Characteristics
Table 19. I C Output Timing Specifications between SCL and SDA (continued)
2
Num
Characteristic
Min
Max
Units
I61
I71
I81
I91
Clock high time
Data setup time
10
2
—
—
—
—
tSYS
tSYS
tSYS
tSYS
Start condition setup time (for repeated start condition only)
Stop condition setup time
20
10
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 19. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR. However, the numbers
given in Table 19 are minimum values.
2
3
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
Specified at a nominal 50-pF load.
I5
I6
I2
I2C_SCL
I2C_SDA
I7
I8
I1
I9
I4
I3
2
Figure 18. I C Input/Output Timings
5.13 Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
5.13.1 Receive Signal Timing Specifications
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
Table 20. Receive Signal Timing
MII Mode
RMII Mode
Num
Characteristic
Unit
Min
Max
Min
Max
—
E1
E2
E3
E4
RXCLK frequency
—
5
25
—
—
4
50
—
MHz
ns
RXD[n:0], RXDV, RXER to RXCLK setup1
RXCLK to RXD[n:0], RXDV, RXER hold1
RXCLK pulse width high
5
—
2
—
ns
35%
35%
65%
65%
35%
35%
65%
65%
RXCLK period
RXCLK period
RXCLK pulse width low
1
In MII mode, n = 3; In RMII mode, n = 1
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
33
Electrical Characteristics
E4
E1
E3
E2
RXCLK (Input)
RXD[n:0]
RXDV,
Valid Data
RXER
Figure 19. MII Receive Signal Timing Diagram
5.13.2 Transmit Signal Timing Specifications
Table 21. Transmit Signal Timing
MII Mode
RMII Mode
Num
Characteristic
Unit
Min
Max
Min
Max
—
E5
E6
E7
E8
TXCLK frequency
—
5
25
—
—
5
50
—
MHz
ns
TXCLK to TXD[n:0], TXEN, TXER invalid1
TXCLK to TXD[n:0], TXEN, TXER valid1
TXCLK pulse width high
—
25
—
14
ns
35%
35%
65%
65%
35%
35%
65%
65%
tTXCLK
tTXCLK
TXCLK pulse width low
1
In MII mode, n = 3; In RMII mode, n = 1
E8
TXCLK (Input)
E7
E5
E6
TXD[n:0]
TXEN,
TXER
Valid Data
Figure 20. MII Transmit Signal Timing Diagram
5.13.3 Asynchronous Input Signal Timing Specifications
Table 22. MII Transmit Signal Timing
Num
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
E9
1.5
—
TXCLK period
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
34
NXP Semiconductors
Electrical Characteristics
CRS, COL
E9
Figure 21. MII Async Inputs Timing Diagram
5.13.4 MII Serial Management Timing Specifications
Table 23. MII Serial Management Channel Signal Timing
Num
Characteristic
Symbol
Min
Max
Unit
E10
E11
E12
E13
E14
E15
MDC cycle time
MDC pulse width
tMDC
400
40
—
25
10
0
—
60
375
—
ns
% tMDC
ns
MDC to MDIO output valid
MDC to MDIO output invalid
MDIO input to MDC setup
MDIO input to MDC hold
ns
—
ns
—
ns
E10
E11
MDC (Output)
MDIO (Output)
MDIO (Input)
E11
E12
E13
Valid Data
E14
E15
Valid Data
Figure 22. MII Serial Management Channel TIming Diagram
5.14 32-Bit Timer Module Timing Specifications
Table 24 lists timer module AC timings.
Table 24. Timer Module AC Timing Specifications
Name
Characteristic
DTnIN cycle time (n = 0:3)
DTnIN pulse width (n = 0:3)
Min
Max
Unit
tsys/2
tsys/2
T1
T2
3
1
—
—
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
35
Electrical Characteristics
5.15 ATA Interface Timing Specifications
The ATA controller is compatible with the ATA/ATAPI-6 industry standard. Refer to the ATA/ATAPI-6 Specficiation and the
ATA controller chapter of the MCF54455 Reference Manual for timing diagrams of the various modes of operation.
The timings of the various ATA data transfer modes are determined by a set of timing equations described in the ATA section
of the MCF54455 Reference Manual. These timing equations must be fulfilled for the ATA host to meet timing. Table 25
provides implementation specific timing parameters necessary to complete the timing equations.
1,2
Table 25. ATA Interface Timing Specifications
Name
Characteristic
Symbol
Min
Max
Unit
Notes
A1
A2
A3
A4
A5
A6
A7
Setup time — ATA_IORDY to SYSCLK falling
Hold time — ATA_IORDY from SYSCLK falling
Setup time — ATA_DATA[15:0] to SYSCLK rising
Propagation delay — SYSCLK rising to all outputs
Output skew
tSUI
tHI
4.0
3.0
4.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
tSU
—
3
3
4
4
tCO
7.0
1.5
—
tSKEW1
tI_DS
tI_DH
—
Setup time — ATA_DATA[15:0] valid to ATA_IORDY
Hold time — ATA_IORDY to ATA_DATA[15:0] invalid
2.0
3.5
—
1
2
3
4
These parameters are guaranteed by design and not testable.
All timings specified with a capacitive load of 40pF.
Applies to ATA_CS[1:0], ATA_DA[2:0], ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA[15:0]
Applies to Ultra DMA data-in burst only
5.16 DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the
transfer attributes are programmable. Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the MCF54455 Reference Manual for information on the modified transfer formats used for communicating
with slower peripheral devices.
1
Table 26. DSPI Module AC Timing Specifications
Name
Characteristic
DSPI_SCK Cycle Time
DSPI_SCK Duty Cycle
Symbol
Min
Max
Unit
Notes
2
DS1
DS2
tSCK
—
4 x tSYS
—
ns
ns
3
(tsck 2) - 2.0 (tsck 2) + 2.0
Master Mode
4
5
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_PCSn to DSPI_SCK delay
tCSC
tASC
—
(2 tSYS) - 1.5
—
—
5
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_PCSn delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(2 tSYS) - 3.0
—
-5
9
—
—
—
—
—
—
0
Slave Mode
DS9 DSPI_SCK to DSPI_SOUT valid
—
—
10
ns
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
36
NXP Semiconductors
Electrical Characteristics
Table 26. DSPI Module AC Timing Specifications (continued)
1
Name
Characteristic
Symbol
Min
Max
Unit
Notes
DS10 DSPI_SCK to DSPI_SOUT invalid
DS11 DSPI_SIN to DSPI_SCK input setup
DS12 DSPI_SCK to DSPI_SIN input hold
DS13 DSPI_SS active to DSPI_SOUT driven
DS14 DSPI_SS inactive to DSPI_SOUT not driven
—
—
—
—
—
0
2
—
—
—
10
10
ns
ns
ns
ns
ns
7
—
—
1
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin
on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
2
3
When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].
This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],
DCTARn[CPHA], and DCTARn[PBR].
4
5
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DS3
DS4
DSPI_PCSn
DS1
DS2
DSPI_SCK
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS7
DS8
DSPI_SIN
Last Data
First Data
Data
Data
DS6
DS5
DSPI_SOUT
First Data
Last Data
Figure 23. DSPI Classic SPI Timing — Master Mode
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
37
Electrical Characteristics
DSPI_SS
DS1
DSPI_SCK
DS2
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS13
DS9
DS10
Data
DS14
First Data
DSPI_SOUT
DSPI_SIN
Last Data
DS11
DS12
Data
Last Data
First Data
Figure 24. DSPI Classic SPI Timing — Slave Mode
5.17 SBF Timing Specifications
The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of
SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 27 provides the AC timing specifications for the SBF.
Table 27. SBF AC Timing Specifications
Name
Characteristic
SBF_CK Cycle Time
Symbol
Min
Max
Unit
Notes
1
SB1
SB2
SB3
SB4
SB5
SB6
SB7
SB8
tSBFCK
—
40
—
—
—
—
—
—
—
—
ns
tSBFCK
ns
SBF_CK High/Low Time
30%
SBF_CS to SBF_CK delay
SBF_CK to SBF_CS delay
SBF_CK to SBF_DO valid
SBF_CK to SBF_DO invalid
SBF_DI to SBF_SCK input setup
SBF_CK to SBF_DI input hold
—
tSBFCK - 2.0
—
tSBFCK - 2.0
ns
—
-5
5
ns
—
ns
—
10
0
ns
—
ns
1
At reset, the SBF_CK cycle time is tREF 67. The first byte of data read from the serial memory contains a divider value
that is used to set the SBF_CK cycle time for the duration of the serial boot process.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
38
NXP Semiconductors
Electrical Characteristics
SBF_CS
SB3
SB1
SB2
SB4
SB2
SBF_CK
SBF_DI
SB7 SB8
First Data
Last Data
SB5
Data
Data
SB6
First Data
SBF_DO
Last Data
Figure 25. SBF Timing
5.18 General Purpose I/O Timing Specifications
1
Table 28. GPIO Timing
Num
Characteristic
Min
Max
Unit
G1 FB_CLK High to GPIO Output Valid
G2 FB_CLK High to GPIO Output Invalid
G3 GPIO Input Valid to FB_CLK High
G4 FB_CLK High to GPIO Input Invalid
—
1.5
9
9
ns
ns
ns
ns
—
—
—
1.5
1
These general purpose specifications apply to the following signals: IRQn, all UART signals, all timer
signals, DACKn and DREQn, and all signals configured as GPIO.
FB_CLK
G2
G1
GPIO Outputs
GPIO Inputs
G3
G4
Figure 26. GPIO Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
39
Electrical Characteristics
5.19 JTAG and Boundary Scan Timing
Table 29. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK Frequency of Operation
Min
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
J9
DC
50
20
—
5
20
—
30
3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLK Cycle Period
TCLK Clock Pulse Width
TCLK Rise and Fall Times
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
—
—
33
33
—
—
11
11
—
—
20
—
—
4
J10 TMS, TDI Input Data Hold Time after TCLK Rise
J11 TCLK Low to TDO Data Valid
10
—
—
50
10
J12 TCLK Low to TDO High Z
J13 TRST Assert Time
J14 TRST Setup Time (Negation) to TCLK High
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 27. Test Clock Input Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
40
NXP Semiconductors
Electrical Characteristics
TCLK
VIL
VIH
J5
Input Data Valid
J6
Data Inputs
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 28. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 29. Test Access Port Timing
TCLK
TRST
J14
J13
Figure 30. TRST Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
41
Electrical Characteristics
5.20 Debug AC Timing Specifications
Table 30 lists specifications for the debug AC timing parameters shown in Figure 31 and Table 32.
Table 30. Debug AC Timing Specification
Num
Characteristic
PSTCLK cycle time
Min
Max
Units
D0
D1
D2
D3
D41
D5
D6
1
—
1.5
1
1
3.0
—
—
—
—
—
tSYS
ns
PSTCLK rising to PSTDDATA valid
PSTCLK rising to PSTDDATA invalid
DSI-to-DSCLK setup
ns
PSTCLK
PSTCLK
PSTCLK
PSTCLK
DSCLK-to-DSO hold
4
DSCLK cycle time
5
BKPT assertion time
1
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 31. Real-Time Trace AC Timing
D5
DSCLK
DSI
D3
Current
D4
Next
DSO
Past
Current
Figure 32. BDM Serial Port AC Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
42
NXP Semiconductors
Power Consumption
6
Power Consumption
All power consumption data is lab data measured on an M54455EVB running the NXP Linux BSP.
1
Table 31. MCF4455 Application Power Consumption
Core
Freq.
MP3
Playback
TFTP
Download
USB HS
File Copy
Idle
Units
IVDD
EVDD
215.6
27.6
288.8
33.6
274.4
32.6
263.7
32.4
mA
mW
mA
266 MHz
200 MHz
SDVDD
142.9
158.2
161.1
158.0
Total Power
672
829
809
787
IVDD
EVDD
163.8
29.9
228.0
34.7
213.8
34.3
207.9
33.8
SDVDD
142.2
158.5
160.0
153.4
Total Power
601
742
722
699
mW
1
All voltage rails at nominal values: IVDD = 1.5 V, EVDD = 3.3 V, and SDVDD = 1.8 V.
850
266 MHz
200 MHz
800
750
700
650
600
550
500
Idle
MP3 Playback
TFTP Download USB HS File Copy
Figure 33. Power Consumption in Various Applications
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
43
Power Consumption
All current consumption data is lab data measured on a single device using an evaluation board. Table 32 shows the typical
power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
1,2
Table 32. Current Consumption in Low-Power Modes
System Frequency
Mode
Voltage Supply
166 (Typ)3 200 (Typ)3 233 (Typ)3 266 (Typ)3 266 (Peak)4
IVDD (mA)
Power (mW)
IVDD (mA)
93.4
140.1
28.0
42.0
17.1
25.7
17.9
26.8
5.7
110.9
166.3
32.7
49.1
19.8
29.7
19.8
29.6
5.7
128.2
192.4
37.5
56.2
22.5
33.7
22.4
33.6
5.7
145.4
218.1
41.1
61.7
25.2
37.8
25.1
37.6
5.7
202.1
303.2
100.2
150.3
25.2
37.8
25.1
37.6
5.7
RUN
WAIT/DOZE
STOP 0
Power (mW)
IVDD (mA)
Power (mW)
IVDD (mA)
STOP 1
Power (mW)
IVDD (mA)
STOP 2
Power (mW)
IVDD (mA)
8.6
8.6
8.6
8.6
8.6
1.8
1.8
1.8
1.8
1.8
STOP 3
Power (mW)
2.6
2.6
2.6
2.6
2.6
1
2
3
4
All values are measured on an M54455EVB with 1.5V IVDD power supply. Tests performed at room
temperature.
Refer to the Power Management chapter in the MCF54455 Reference Manual for more information
on low-power modes.
All peripheral clocks are off except UART0, INTC0, IACK, edge port, reset controller, CCM, PLL, and
FlexBus prior to entering low-power mode.
All peripheral clocks on prior to entering low-power mode.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
44
NXP Semiconductors
Package Information
325.0
300.0
275.0
250.0
225.0
200.0
175.0
150.0
125.0
100.0
75.0
Run
Wait/Doze
Stop 0
Stop 1
Stop 2
Stop 3
50.0
25.0
0.0
166
200
System Frequency (MHz)
Figure 34. IV Power Consumption in Low-Power Modes
233
266
266 (peak)
DD
7
Package Information
The latest package outline drawings are available on the product summary pages on http://www.nxp.com/coldfire. Table 33 lists
the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest package
outline drawings.
Table 33. Package Information
Device
Package Type
Case Outline Numbers
MCF54450
MCF54451
MCF54452
MCF54453
MCF54454
MCF54455
256 MAPBGA
98ARH98219A
360 H PWR
TEPBGA
98ASA01712D
8
Product Documentation
Documentation is available from a local NXP distributor, an NXP sales office, the NXP Literature Distribution Center, or
through the NXP world-wide web address at http://www.nxp.com/coldfire.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
NXP Semiconductors
45
Revision History
9
Revision History
Table 34 summarizes revisions to this document.
Table 34. Revision History
Summary of Changes
Rev. No.
Date
0
1
Sept 17, 2007 Initial public release.
Feb 15, 2008 Corrected VSS pin locations in MCF5445x signal information and muxing table for the 360 TEPBGA
package: changed “...M9, M16, M17...” to “...M9–M14, M16...”
Updated FlexBus read and write timing diagrams and added two notes before them.
Change FB_A[23:0] to FB_A[31:0] in FlexBus read and write timing diagrams.
Added power consumption section.
2
May 1, 2008 In Family Configurations table, added PCI as feature on 256-pin devices. On these devices the
PCI_AD bus is limited to 24-bits.
In Absolute Maximum Ratings table, changed RTCVDD specification from “-0.3 to +4.0” to “-0.5 to
+2.0”.
In DC Electrical Specifications table:
• Changed RTCVDD specification from 3.0–3.6 to 1.35–1.65.
• Changed High Impedance (Off-State) Leakage Current (IOZ) specification from ±1 to ±10A, and
added footnote to this spec: “Worst-case tristate leakage current with only one I/O pin high. Since
all I/Os share power when high, the leakage current is distributed among them. With all I/Os high,
this spec reduces to ±2 A min/max.“
3
4
5
Dec 1, 2008 Changed “360PBGA” heading to “360 TEPBGA” in Table 6.
Changed the following specs in Table 13:
• Minimum frequency of operation from — to 60MHz.
• Maximum clock period from — to 16.67 ns.
Apr 12, 2009 Rescinded previous errata, the 256-pin devices do not contain the PCI bus controller:
• In Table 4, in PCI_ADn signal section, added a separate row for each package, with PCI_ADn
signals shown as — for 256-pin devices.
• In Figure 5, changed the PCI_ADn pins to their alternative function, FB_An.
Apr 27, 2009 In Table 2 changed MCF54450VM180 to MCF54450CVM180 and changed it’s temperature entry
from “0 to +70 C” to “–40 to +85 C”.
6
7
Oct 15, 2009 In Table 8 changed Input Leakage Current (Iin) from ±1.0 to ±2.5A.
Oct 18, 2011 In Table 2, added MCF54452YVR200 part number, with temperature range from –40 to +105 C.
In Table 8, added Input Leakage Current (Iin) values for MCF54452YVR200 part number.
8
9
Jan 18, 2012 In Table 4, added pin N7 in the VSS pin list for the 360 TEPBGA.
April 13, 2021 • Updated instances of “Freescale” to “NXP” throughout the document.
• Updated links referring to freescale.com to nxp.com.
• In Table 2, updated the part numbers for MCF54452, MCF54453, MCF54454, and MCF54455
families.
• In Table 33, updated package type from “360 TEPBGA” to “360 H PWR TEPBGA”.
• In Table 33, updated the case outline number from “98ARE10605D” to “98ASA01712D”.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 9, 04/2021
46
NXP Semiconductors
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Date of release: April, 2021
Document identifier: MCF54455
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