MCIMX27MOP4AR2_技术文档

Freescale Semiconductor

Technical Data

Document Number: MCIMX27EC

Rev. 1.8, 1/2013

i.MX27 and i.MX27L

Package Information

Plastic Package

Case 1816-01

i.MX27 and i.MX27L

Data Sheet

Multimedia Applications

Processor

(MAPBGA–404)

Case 1931-04

(MAPBGA-473)

Ordering Information

See Table 1 on page 4 for ordering information.

Contents

1 Introduction

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . .

2

3

4

The i.MX27 and i.MX27L (MCIMX27/MX27L)

multimedia applications processors represents the next

step in low-power, high-performance application

processors. Unless otherwise specified, the material in

this data sheet is applicable to both the i.MX27 and

i.MX27L processors and referred to singularly

throughout this document as i.MX27.

2. Functional Description and Application Information . . . . 4

2.1. ARM926 Microprocessor Core Platform . . . . . . . .

2.2. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . .

2.3. Module Descriptions . . . . . . . . . . . . . . . . . . . . . . .

4

5

9

3. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1. Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . 35

3.2. EMI Pins Multiplexing . . . . . . . . . . . . . . . . . . . . . 35

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 40

4.1. i.MX27/iMX27L Chip-Level Conditions . . . . . . . . 40

4.2. Module-Level Electrical Specifications . . . . . . . . 43

4.3. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 54

5. Package Information and Pinout . . . . . . . . . . . . . . . . 109

5.1. Full Package Outline Drawing (17 mm × 17 mm) 109

5.2. Pin Assignments (17 mm × 17 mm) . . . . . . . . . 110

5.3. Full Package Outline Drawing (19 mm × 19 mm) 129

5.4. Pin Assignments (19 mm × 19 mm) . . . . . . . . . 130

6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . 150

7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

The i.MX27L does not include the following features:

ATA-6 HDD Interface, Memory Stick Pro, VPU:

MPEG-4/ H.263/H.264 HW encoder/decoder, and

eMMA (PrP processing, CSC, deblock, dering).

Based on an ARM926EJ-S™ microprocessor core, the

i.MX27/27L processor provides the performance with

low power consumption required by modern digital

devices such as the following:

•

Feature-rich cellular phones

Portable media players and mobile gaming

machines

•

Personal digital assistants (PDAs) and wireless

PDAs

Introduction

•

Portable DVD players

Digital cameras

The i.MX27/MX27L processor features the advanced and power-efficient ARM926EJ-S core operating at

speeds up to 400 MHz, and is optimized for minimal power consumption using the most advanced

techniques for power saving (for example, DPTC, power gating, and clock gating). With 90 nm technology

and dual Vt, the i.MX27/MX27L device provides the optimal performance vs. leakage current balance.

The performance of the i.MX27/MX27L processors are both boosted by an on-chip cache system, and

features peripheral devices, such as an MPEG-4, H.263, an H.264 video codec (up to D1—720 x 486—@

30 FPS), LCD, eMMA_lt, and CMOS Sensor Interface controllers.

The i.MX27/MX27L processors supports connections to various types of external memories, such as

266-MHz DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The i.MX27/MX27L devices can be

connected to a variety of external devices using technology, such as high-speed USBOTG 2.0, the

Advanced Technology Attachment (ATA), Multimedia/Secure Data (MMC/SDIO), and CompactFlash.

NOTE

The i.MX27L does not support the ATA-6 HDD interface.

1.1

Features

The MX27/MX27L processors are targeted for video and voice over-IP (V2IP) and smart remote

controllers. It also provides low-power solutions for any high-performance and demanding multimedia

and graphics applications.

The systems include the following features:

•

Multi-standard video codec (i.MX27 only)

— MPEG-4 part-II simple profile encoding/decoding

— H.264/AVC baseline profile encoding/decoding

— H.263 P3 encoding/decoding

— Multi-party call: one stream encoding and two streams decoding simultaneously

— Multi-format: encodes MPEG-4 bitstream, and decodes H.264 bitstream simultaneously

— On-the-fly video processing that reduces system memory load (for example, the

power-efficient viewfinder application with no involvement of either the memory system or the

ARM CPU)

•

Advanced power management (i.MX27/27L)

— Dynamic process and temperature compensation

— Multiple clock and power domains

— Independent gating of power domains

Multiple communication and expansion ports

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

2

Freescale Semiconductor

Introduction

1.2

Block Diagram

Figure 1 shows the i.MX27 simplified interface block diagram.

DDR/

SDRAM

NOR/NAND

Flash

LCD Display

Camera

LCDC

SLCDC

AP Peripherals

M3IF

SDRAMC

AUDMUX

SSI (2)

NFC

WEIM

PCMCIA/CF

CSI

CSPI (3)

I²C (2)

UART (6)

ARM926

Platform

ARM926EJ-S

USBOTG HS

1-Wire

FEC

L1 I/D cache

AITC

VRAM

iROM

ATA

ETM9

SDHC (3)

MSHC

GPIO

eMMA-lt

JTAG

Security

Video Codec

DMA

CRM

SAHARA2

RTIC

PWM

KPP

SCC

IIM

Application Processor Domain (AP)

Timers

WDOG

GPT (6)

RTC

USBOTG

XVR

Access

Conn.

Keypad

Bluetooth

WLAN

MMC/SDIO

Note: The i.MX27L does not support the following:

•

ATA-6 HDD Interface

Memory Stick Pro

VPU: MPEG-4/.263/H.264 HW encoder/decoder

eMMA (PrP processing, CSC, deblock, dering)

Figure 1. i.MX27/MX27L Simplified Interface Block Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

3

Functional Description and Application Information

1.3

Ordering Information

Table 1 provides ordering information for the MAPBGA, lead-free packages.

Table 1. Ordering Information

Device

Temperature

Package

MCIMX27VOP4A

MCIMX27LVOP4A

MCIMX27MOP4A

MCIMX27LMOP4A

MCIMX27VJP4A

MCIMX27LVJP4A

MCIMX27MJP4A

MCIMX27LMJP4A

–20° C to +85° C

–40° C to +85° C

–20° C to +85° C

–40° C to +85° C

1816-01

1931-04

1816-01

1931-04

2 Functional Description and Application Information

2.1

ARM926 Microprocessor Core Platform

The ARM926 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6 × 3 Multi-Layer AHB

crossbar switch (MAX), and a “primary AHB” complex.

•

The instruction bus (I-AHB) of the ARM926EJ-S processor is connected directly to MAX Master

Port 0.

•

The data bus (D-AHB) of the ARM926EJ-S processor is connected directly to MAX Master Port 1.

Four alternate bus master interfaces are connected to MAX Master Ports 2–5. Three slave ports of the

MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB

is internal to the platform and has five slaves connected to it: the AITC interrupt module, the MCTL

memory controller, and two AIPI peripheral interface gaskets. Slave Ports 1 and 2 of the MAX are referred

to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.

The ARM926EJ-S processor supports the 32-bit and 16-bit ARM Thumb instruction sets, enabling the

user to trade off between high performance and high-code density. The ARM926EJ-S processor includes

features for efficient execution of Java byte codes, providing Java performance similar to the just-in-time

(JIT) compiler—which is a type of Java compiler—but without the associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debugging. The ARM926EJ-S processor has a Harvard cached architecture and

provides a complete high-performance processor subsystem, including the following:

•

An ARM9EJ-S integer core

A Memory Management Unit (MMU)

Separate instruction and data AMBA AHB bus interfaces

ETM and JTAG-based debug support

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

4

Freescale Semiconductor

Functional Description and Application Information

The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other

application-specific hardware acceleration to be added. The ARM926EJ-S processor implements ARM

architecture version 5TEJ.

The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports

of the MAX, are designed to support connections to multiple AHB masters external to the platform. An

external arbitration AHB control module is needed if multiple external masters are desired to share an

ARM926 Platform alternate bus master port. However, the alternate bus master ports on the platform

support seamless connection to a single master with no external interface logic required.

A primary AHB MUX (PAHBMUX) module performs address decoding, read data muxing, bus

watchdog, and other miscellaneous functions for the primary AHB within the platform. A clock control

module (CLKCTL) is provided to support a power-conscious design methodology, as well as

implementation of several clock synchronization circuits.

2.1.1

Memory System

The ARM926EJ-S complex includes 16-Kbyte Instruction and 16-Kbyte Data caches. The embedded

45-Kbyte SRAM (VRAM) can be used to avoid external memory accesses or it can be used for

applications. There is also a 24-Kbyte ROM for bootstrap code.

2.2

Module Inventory

Table 2 shows an alphabetical listing of the modules in the i.MX27/MX27L multimedia applications

processors. A cross-reference to each module’s section and page number goes directly to a more detailed

module description for additional information.

Table 2. Digital and Analog Modules

Functional

Grouping

Section/

Page

Block Mnemonic

Block Name

Brief Description

®

1-Wire

1-Wire Interface Connectivity The 1-Wire module provides bi-directional communication

2.3.1/9

Peripheral

between the ARM926EJ-S and the Add-Only-Memory EPROM

(DS2502). The 1-Kbit EPROM is used to hold information

about battery and communicates with the ARM926 Platform

using the IP interface.

AIPI

AITC

AHB-Lite IP

Interface

Module

Bus Control The AIPI acts as an interface between the ARM Advanced

High-performance Bus Lite. (AHB-Lite) and lower bandwidth

peripherals that conforms to the IP Bus specification, Rev 2.0.

2.3.2/10

2.3.3/10

ARM9EJ-S

Interrupt

Controller

Bus Control AITC is connected to the primary AHB as a slave device. It

generates the normal and fast interrupts to the ARM926EJ-S

processor.

ARM926EJS

ATA

ARM926EJ-S

CPU

The ARM926EJ-S (ARM926) is a member of the ARM9 family 2.3.4/10

of general-purpose microprocessors targeted at multi-tasking

applications.

Advanced

Technology(AT)

Attachment

Connectivity The ATA block is an AT attachment host interface. It interfaces 2.3.5/11

Peripheral with IDE hard disc drives and ATAPI optical disc drives.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

5

Functional Description and Application Information

Table 2. Digital and Analog Modules (continued)

Functional

Grouping

Section/

Page

Block Mnemonic

Block Name

Brief Description

AUDMUX

Digital Audio

Multiplexer

Multimedia

Peripheral

The AUDMUX interconnections allow multiple, simultaneous

audio/voice/data flows between the ports in point-to-point or

point-to-multipoint configurations.

2.3.6/11

CRM

CSI

Clock and

The CRM generates clock and reset signals used throughout

2.3.7/12

Reset Module Reset Control the i.MX27/MX27L processors and also for external

peripherals.

CMOS Sensor

Interface

Multimedia

Interface

The CSI is a logic interface which enables the i.MX27/MX27L 2.3.8/12

processors to connect directly to external CMOS sensors and

a CCIR656 video source.

CSPI

Configurable

SerialPeripheral

Interface (x3)

Connectivity The i.MX27/MX27L processors have three CSPI modules.

2.3.9/13

Peripheral

CSPI is equipped with two data FIFOs and is a master/slave

configurable serial peripheral interface module, allowing the

i.MX27/MX27L processors to interface with both external SPI

master and slave devices.

DMAC

eMMA_lt

EMI

Direct Memory

Access

Controller

Standard

System

Resource

The DMAC of the i.MX27/MX27L processors provides 16

channels supporting linear memory, 2D memory, FIFO and

end-of-burst enable FIFO transfers to support a wide variety of

DMA operations.

2.3.10/13

eMMA_lt

H/W

eMMA_lt consists of a PreProcessor and PostProcessor, and 2.3.11/13

Accelerator provides video acceleration. The PrP and PP can be used for

Functions

generic video pre and post processing such as scaling,

resizing, and color space conversions.

External

Memory

Interface

Memory

Interface (EMI)

The EMI includes

—

• Multi-Master Memory Interface (M3IF)

• Enhanced SDRAM/MDDR memory controller (ESDRAMC)

• PCMCIA memory controller (PCMCIA)

• NAND Flash Controller (NFC)

• Wireless External Interface Module (WEIM)

ESDRAMC

FEC

Enhanced

SDRAM

Controller

External

Memory

Interface

The ESDRAMC provides interface and control for synchronous 2.3.12/15

DRAM memories for the system.

Fast Ethernet

Controller

Connectivity The FEC performs the full set of IEEE 802.3/Ethernet

Peripheral

2.3.13/15

CSMA/CD media access control and channel interface

functions. The FEC supports connection and functionality for

the 10/100 Mbps 802.3 media independent interface (MII). It

requires an external transceiver (PHY) to complete the

interface to the media.

GPIO

GPT

General

Purpose I/O

Module

Pins

The GPIO provides 32 bits of bidirectional, general purpose

I/O. This peripheral provides dedicated general-purpose pins

that can be configured as either inputs or outputs.

2.3.14/16

General

Purpose Timer

Timer

Peripheral

The GPT is a multipurpose module used to measure intervals 2.3.15/16

or generate periodic output.

2

I C

Inter IC

Connectivity The I C provides serial interface to control the sensor interface 2.3.16/17

Communication

Peripheral

and other external devices. Data rates of up to 100 Kbits/s are

supported.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

6

Freescale Semiconductor

Functional Description and Application Information

Table 2. Digital and Analog Modules (continued)

Functional

Grouping

Section/

Page

Block Mnemonic

Block Name

Brief Description

IIM

IC Identification

Module

Security

The IIM provides an interface for reading—and in some cases, 2.3.17/17

programming, and overriding identification and control

information stored in on-chip fuse elements.

Contact your Freescale Semiconductor sales office or

distributor for additional information on SCC, RTIC, IIM,

SAHARA2

JTAGC

KPP

JTAG Controller

Keypad Port

Debug

The JTAGC provides debug access to the ARM926 core,

built-in self-test (BIST), and boundary scan test control.

2.3.18/17

Connectivity The KPP is used for key pad matrix scanning or as a general 2.3.19/17

Peripheral

purpose I/O. This peripheral simplifies the software task of

scanning a keypad matrix.

LCDC

M3IF

Liquid Crystal

Display

Controller

Multimedia

Interface

The LCDC provides display data for external gray-scale or

color LCD panels.

2.3.20/17

2.3.21/18

Multi-Master

Memory

Interface

External

Memory

Interface

The M3IF controls memory accesses from one or more

masters through different port interfaces to different external

memory controllers ESDCTL/MDDRC, PCMCIA, NFC, and

WEIM.

MAX

Multi-layer AHB

Crossbar Switch

Bus Control The ARM926EJ-S processor’s instruction and data buses and 2.3.22/18

all alternate bus master interfaces arbitrate for resources via a

6 × 3 MAX. There are six fully functional master ports (M0–M5)

and three fully functional slave ports (S0–S2). The MAX is

uni-directional. All master and slave ports are AHB-Lite

compliant.

MSHC

Memory Stick

Connectivity The MSHC is placed in between the AIPI and the customer

2.3.23/19

Host Controller

Peripheral

memory stick to support data transfer from the i.MX27 device

to the customer memory stick.

Note: The i.MX27L does not support the MSHC feature

NFC

NAND Flash

Controller

External

Memory

Interface

The NFC is a submodule of EMI. The NFC implements the

interface to standard NAND Flash memory devices.

2.3.24/19

PCMCIA

Personal

Computer

Memory Card

International

Association

External

Memory

Interface

The PCMCIA host adapter module provides the control logic 2.3.25/20

for PCMCIA socket interfaces, and requires some additional

external analog power switching logic and buffering.

PLL

Phase Lock

Loop

Clock and

The two DPLLs provide clock generation in digital and mixed 2.3.26/20

Reset Control analog/digital chips designed for wireless communication and

other applications.

PWM

Pulse-Width

Modulator

Timer

Peripheral

The PWM has a 16-bit counter and is optimized to generate

sound from stored sample audio images. It can also generate

tones.

2.3.27/20

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

7

Functional Description and Application Information

Table 2. Digital and Analog Modules (continued)

Functional

Grouping

Section/

Page

Block Mnemonic

Block Name

Brief Description

RTC

Real Time Clock

Timer

Peripheral

The RTC module provides a current stamp of seconds,

minutes, hours, and days. Alarm and timer functions are also

available for programming. The RTC supports dates from the

year 1980 to 2050.

2.3.28/20

RTIC

Run-Time

Integrity

Checkers

Security

The RTIC ensures the integrity of the contents of the peripheral 2.3.29/21

memory and assists with boot authentication.

Contact your Freescale Semiconductor sales office or

distributor for additional information on SCC, RTIC, IIM,

SAHARA2

Symmetric/

Asymmetric

Hashing and

Random

SAHARA2 is a security co-processor which forms part of the 2.3.30/21

Platform Independent Security Architecture (PISA), and can be

used on cell phone baseband processors or wireless PDAs.

Contact your Freescale Semiconductor sales office or

distributor for additional information on SCC, RTIC, IIM,

SAHARA2

Accelerator

SCC

Security

Controller

Module

Security

The SCC is a hardware component composed of two

blocks—the Secure RAM module, and the Security Monitor.

The Secure RAM provides a way of securely storing sensitive

information. The Security Monitor implements the security

policy, checking algorithm sequencing, and controlling the

Secure State.

2.3.31/21

Contact your Freescale Semiconductor sales office or

distributor for additional information on SCC, RTIC, IIM,

SAHARA2

SDHC

SLCDC

SSI

Secured Digital Connectivity The SDHC controls the MMC (MultiMediaCard), SD (Secure 2.3.32/21

Host Controller

Peripheral

Digital) memory, and I/O cards by sending commands to cards

and performing data accesses to and from the cards.

Smart Liquid

Crystal Display

Controller

Multimedia

Interface

The SLCDC module transfers data from the display memory

buffer to the external display device.

2.3.33/22

2.3.34/22

Synchronous

Serial Interface

Multimedia

Peripheral

The SSI is a full-duplex, serial port that allows the chip to

communicate with a variety of serial devices, such as standard

codecs, digital signal processors (DSPs), microprocessors,

peripherals, and popular industry audio codecs that implement

2

the inter-IC sound bus standard (I S) and Intel AC97 standard.

UART

Universal

Asynchronous

Receiver/

Connectivity The UART provides serial communication capability with

2.3.35/23

Peripheral

external devices through an RS-232 cable or through use of

external circuitry that converts infrared signals to electrical

signals (for reception) or transforms electrical signals to signals

that drive an infrared LED (for transmission) to provide low

speed IrDA compatibility.

Transmitter

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

8

Freescale Semiconductor

Functional Description and Application Information

Table 2. Digital and Analog Modules (continued)

Functional

Grouping

Section/

Page

Block Mnemonic

Block Name

Brief Description

USB

Universal Serial Connectivity The i.MX27/MX27L processors provide two USB Host

2.3.36/23

Bus–2 Host

Controllers and

1 OTG

Peripherals controllers and one USBOTG of which:

• USB Host 1 is designed to support transceiverless

connection to the on-board peripherals in Low Speed and

Full Speed mode, and connection to the ULPI

(On-The-Go)

(UTMI+Low-Pin Court) and Legacy Full Speed transceivers

• USB Host 2 is designed to support transceiverless

connection to the Cellular Modem Baseband Processor

• The USBOTG controller offers HS/FS/LS capabilities in Host

mode and HS/FS in device mode. In Host mode, the

controller supports direct connection of a FS/LS device

(without external hub). In device (bypass) mode, the OTG

port functions as gateway between the Host 1 Port and the

OTG transceiver.

Video Codec

WDOG

Video Codec

Hardware

Video Codec module supports full duplex video codec with 25 2.3.39/25

Acceleration fps VGA image resolution, integrates H.264 BP, MPEG-4 SP

and H.263 P3 video processing standard together.

WatchdogTimer

Module

Timer

Peripheral

The WDOG module protects against system failures by

providing a method for the system to recover from unexpected

events or programming errors.

2.3.37/24

WEIM

Wireless

External

Interface

Module

External

Memory

Interface

The Wireless External Module (WEIM) handles the interface to 2.3.38/25

devices external to chip, including generation of chip selects,

clock and control for external peripherals and memory. It

provides asynchronous and synchronous access to devices

with SRAM-like interface.

2.3

Module Descriptions

This section provides a brief text description of all the modules included in the i.MX27/MX27L devices,

arranged in alphabetical order.

2.3.1

1-Wire Module

The 1-Wire module provides bi-directional communication between the ARM926 core and the Add-Only

Memory EPROM, DS2502. The 1-Kbit EPROM holds information about the battery and communicates

with the ARM926 Platform using the IP interface. Through the 1-Wire interface, the ARM926 acts as the

bus master while the DS2502 device is the slave. The 1-Wire peripheral does not trigger interrupts; hence

it is necessary for the ARM926 to poll the 1-Wire to manage the module. The 1-Wire uses an external pin

to connect to the DS2502. Timing requirements are met in hardware with the help of a 1 MHz clock. The

clock divider generates a 1 MHz clock that is used as a time reference by the state machine. Timing

requirements are crucial for proper operation, and the 1-Wire state machine and the internal clock provide

the necessary signal. The clock must be configured to approximately 1 MHz. You can then set the 1-Wire

register to send and receive bits over the 1-Wire bus.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

9

Functional Description and Application Information

2.3.2

AHB-Lite IP Interface Module (AIPI)

The AIPI acts as an interface between the ARM Advanced High-performance Bus Lite. (AHB-Lite) and

lower bandwidth peripherals conforming to the IP bus specification Rev 2.0. There are two AIPI modules

in i.MX27/MX27L processors.

The following list summarizes the key features of the AIPI:

•

All peripheral read transactions require a minimum of two system clocks (R-AHB side) and all

write transactions require a minimum of three system clocks (R-AHB side).

The AIPI supports 8-bit, 16-bit, and 32-bit IP bus peripherals. Byte, half word, and full word reads

and writes are supported.

The AIPI supports multi-cycle accesses by providing 16-bit to 8-bit peripherals operations and

32-bit to both 16-bit and 8-bit peripherals operations.

The AIPI supports 31 external IP bus peripherals each with a 4-Kbyte memory map (a slot).

2.3.3

ARM926EJ-S Interrupt Controller (AITC)

The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral that collects interrupt requests from

up to 64 sources and provides an interface to the ARM926EJ-S core. The AITC includes software

controlled priority levels for normal interrupts.

The AITC performs the following functions:

•

Supports up to 64 interrupt sources

Supports fast and normal interrupts

Selects normal or fast interrupt request for any interrupt source

Indicates pending interrupt sources via a register for normal and fast interrupts

Indicates highest priority interrupt number via register. (Can be used as a table index.)

Independently can enable or disable any interrupt source

Provides a mechanism for software to schedule an interrupt

Supports up to 16 software controlled priority levels for normal interrupts and priority masking

Can single-bit disable all normal interrupts and all fast interrupts. (Used in enabling of secure

operations.)

2.3.4

ARM926EJ-S Platform

The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors

targeted at multi-tasking applications. The ARM926 supports the 32-bit ARM and 16-bit Thumb

instructions sets. The ARM926 includes features for efficient execution of Java byte codes. A JTAG port

is provided to support the ARM Debug Architecture, along with associated signals to support the ETM9

real-time trace module. The ARM926EJ-S is a Harvard cached architecture including an ARM9EJ-S

integer core, a Memory Management Unit (MMU), separate instruction and data AMBA AHB interfaces,

separate instruction and data caches, and separate instruction and data tightly coupled memory (TCM)

interfaces. The ARM926 co-processor, instruction TCM, and data TCM interfaces will be tied off within

the ARM926 Platform and will not be available for external connection.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

10

Freescale Semiconductor

Functional Description and Application Information

The ARM926EJ-S processor is a fully synthesizable macrocell, with a configurable memory system. Both

instruction and data caches will be 16 kbytes on the platform. The cache is virtually accessed and virtually

tagged. The data cached has physical tags as well. The MMU provides virtual memory facilities which are

required to support various platform operating systems such as Symbian OS, Windows CE, and Linux. The

MMU contains eight fully associative TLB entries for lockdown and 64 set associative entries. Refer to

the ARM926EJ-S Technical Reference Manual for more information.

2.3.5

Advanced Technology Attachment (ATA)

The Advanced Technology Attachment (ATA) host controller complies with the ATA/ATAPI-6

specification. The primary use of the ATA host controller is to interface with IDE hard disc drives and

Advanced Technology Attachment Packet Interface (ATAPI) optical disc drives. It interfaces with the ATA

device over a number of ATA signals.

This host controller supports interface protocols as specified in ATA/ATAPI-6 standard, as follows:

•

PIO mode 0, 1, 2, 3, and 4

Multiword DMA mode 0, 1, and 2

Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher

Ultra DMA mode 5 with bus clock of 80 MHz or higher

Before accessing the ATA bus, the host must program the timing parameters to be used on the ATA bus.

The timing parameters control the timing on the ATA bus. Most timing parameters are programmable as a

number of clock cycles (1 to 255). Some are implied. All of the ATA device-internal registers are visible

to users, and they are defined as mirror registers in ATA host controller. As specified in ATA/ATAPI-6

standard, all the features/functions are implemented by reading/writing to the device’s internal registers.

There are basically two protocols that can be active at the same time on the ATA bus, as follows:

•

The first and simplest protocol (PIO mode access) can be started at any time by the ARM926 to

the ATA bus. The PIO mode is a slow protocol, mainly intended to be used to program an ATA disc

drive, but also can be used to transfer data to/from the disc drive.

•

The second protocol is the DMA mode access. DMA mode is started by the ATA interface after

receiving a DMA request from the drive, and only if the ATA interface has been programmed to

accept the DMA request. In DMA mode, either multiword-DMA or ultra-DMA protocol is used

on the ATA bus. All transfers between FIFO and the host IP or DMA IP bus are zero wait states

transfer, so a high-speed transfer between FIFO and DMA/host bus is possible.

2.3.6

Digital Audio MUX (AUDMUX)

The Digital Audio MUX (AUDMUX) provides programmable interconnecting for voice, audio, and

synchronous data routing between host serial interfaces—for example, SSI, SAP, and peripheral serial

interfaces—such as, audio and voice codecs. The AUDMUX allows audio system connectivity to be

modified through programming, as opposed to altering the design of the system into which the chip is

designed. The design of the AUDMUX allows multiple simultaneous audio/voice/data flows between the

ports in point-to-point or point-to-multipoint configurations.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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11

Functional Description and Application Information

Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial

interfaces, and the external ports connect to off-chip audio devices and serial interfaces of other processors.

A desired connectivity is achieved by configuring the appropriate internal and external ports.

The module includes full 6-wire SSI interfaces for asynchronous receive and transmit, as well as a

configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interface. The AUDMUX allows

each host interface to be connected to any other host or peripheral interface in a point-to-point or

point-to-multipoint (network mode).

2.3.7

Clock and Reset Module (CRM)

The Clock and Reset Module (CRM) generates clock and reset signals used throughout the

i.MX27/MX27L processor and for external peripherals. It also enables system software to control,

customize, or read the status of the following functions:

•

Chip ID

Multiplexing of I/O signals

I/O Driving Strength

I/O Pull Enable Control

Well-Bias Control

System boot mode selection

DPTC Control

2.3.8

CMOS Sensor Interface (CSI)

The CMOS Sensor Interface (CSI) is a logic interface that enables the i.MX27/MX27L processors to

connect directly to external CMOS sensors and CCIR656 video source.

The capabilities of the CSI include the following:

•

Configurable interface logic to support popular CMOS sensors in the market

Support traditional sensor timing interface

Support CCIR656 video interface, progressive mode for smart sensor, interlace mode for PAL and

NTSC input

•

8-bit input port for YCC, YUV, Bayer, or RGB data

32 × 32 FIFO storing image data supporting Core data read and DMA data burst transfer to system

memory

•

Full control of 8-bit and 16-bit data to 32-bit FIFO packing

Direct interface to eMMA-lt Pre-Processing block (PrP) - Not available on the i.MX27L

Single interrupt source to interrupt controller from maskable sensor interrupt sources: Start of

Frame, End of Frame, Change of Field, FIFO full

•

Configurable master clock frequency output to sensor

Asynchronous input logic design. Sensor master clock can be driven by either the i.MX27/MX27L

processor or by external clock source.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Freescale Semiconductor

Functional Description and Application Information

•

Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the

camera (for Bayer data only)

2.3.9

Configurable Serial Peripheral Interface (CSPI)

The Configurable Serial Peripheral Interface (CSPI) is used for fast data communication with fewer

software interrupts. There are three CSPI modules in the i.MX27/MX27L processors, which provide a

full-duplex synchronous serial interface, capable of interfacing to the SPI master and slave devices. CSPI1

and CSPI2 are master/slave configurable and include three chip selects to support multiple peripherals.

CSPI3 is only a master and has one chip-select signal. The transfer continuation function of the CSPI

enables unlimited length data transfers using 32-bit wide by 8-entry FIFO for both TX and RX data DMA

support.

The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data communication with

fewer software interrupts. When the CSPI module is configured as a master, it uses a serial link to transfer

data between the CSPI and an external device. A chip-enable signal and a clock signal are used to transfer

data between these two devices. When the CSPI module is configured as a slave, the user can configure

the CSPI Control register to match the external SPI master’s timing.

2.3.10 Direct Memory Access Controller (DMAC)

The Direct Memory Access Controller (DMAC) provides 16 channels to support linear memory, 2D

memory, FIFO, and end-of-burst enable FIFO transfers to support a wide variety of DMA operations.

Features include the following:

•

Support of 16 channels linear memory, 2D memory, and FIFO for both source and destination

Support of 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer

Configurability of DMA burst length of up to a maximum of 16 words, 32 half-words, or 64 bytes

for each channel

•

Bus utilization control for a channel that is not triggered by DMA request

Interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error

DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a

programmed timing period

•

Dedicated external DMA request and grant signal

Support of increment, decrement, and no increment for source and destination addressing

Support of DMA chaining

2.3.11 enhanced MultiMedia Accelerator Light (eMMA_lt)

The enhanced MultiMedia Accelerator Light (eMMA_lt) consists of the video pre-processor (PrP) and

post-processor (PP). In contrast with i.MX21 processor’s components, this eMMA does not include the

video codec. A more powerful video codec is included as a separate module.

NOTE

The i.MX27L does not have a eMMA_lt module.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

13

Functional Description and Application Information

Each module has individual control and configuration registers that are accessed via the IP interface, and

are capable of bus mastering the AMBA bus to independently access system memory without any CPU

intervention. This enables each module to be used independently of each other, and enables the

pre-processor and post-processor modules to provide acceleration features for other software codec

implementations and image processing software. These blocks work together to provide video

acceleration, and to off-load the CPU from computation intensive tasks. The PrP and PP can be used for

generic video pre- and post-processing, such as scaling, resizing, and color space conversions. A

32-bit-to-64-bit AHB gasket is used to convert a PrP AHB bus from a 32-bit to 64-bit protocol. A bypass

function is implemented to bypass this 64-bit gasket if it is not needed.

eMMA_lt supports the following image/video processing features:

•

Pre-processor:

— Data input:

– System memory

– Private DMA between CMOS Sensor Interface module and pre-processor

— Data input formats:

– Arbitrarily formatted RGB pixels (16 or 32 bits)

– YUV 4:2:2 (Pixel interleaved)

– YUV 4:2:0 (IYUV, YV12)

— Input image size: 32 × 32 to 2044 × 2044

— Image scaling:

– Programmable independent CH-1 and CH-2 resizer. Can program to be in cascade or

parallel.

– Each resizer supports downscaling ratios from 1:1 to 8:1 in fractional steps.

— Channel-1 output data format

– Channel 1

– RGB 16 and 32 bpp

– YUV 4:2:2 (YUYV, YVYU, UYVY, VYUY)

— Channel-2 output data format

– YUV 4:2:2 (YUYV)

– YUV 4:4:4

– YUV 4:2:0 (IYUV, YV12)

– RGB data and YUV data format can be generated concurrently

— 32/64-bit AHB bus

•

Post-processor

— Input data:

– From system memory

— Input format:

– YUV 4:2:0 (IYUV, YV12)

— Image Size: 32 × 32 to 2044 × 2044

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Functional Description and Application Information

— Output format:

– YUV 4:2:2 (YUYV)

– RGB16 and RGB32 bpp

— Image Resize

– Upscaling ratios ranging from 1:1 to 1:4 in fractional steps

– Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1

– Ratios provide scaling between QCIF, CIF, QVGA (320 × 240, 240 × 320)

2.3.12 Enhanced Synchronous Dynamic RAM Controller (ESDRAMC)

The Enhanced Synchronous Dynamic RAM Controller (ESDRAMC) provides an interface and control for

synchronous DRAM memories for the system. SDRAM memories use a synchronous interface with all

signals registered on a clock edge. A command protocol is used for initialization, read, write, and refresh

operations to the SDRAM, and is generated on the signals by the controller (when required due to external

or internal requests). It has support for both single data rate RAMs and double data rate SDRAMs. It

supports 64 Mbits, 128 Mbits, 256 Mbits, and 512 Mbits, 1 Gbit, 2 Gbits, four bank synchronous DRAM

by two independent chip selects and with up to 256 Mbytes addressable memory per chip select.

2.3.13 Fast Ethernet Controller (FEC)

The Fast Ethernet Controller (FEC) is designed to support both 10 and 100 Mbps

Ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are

required to complete the interface to the media. The FEC supports the 10/100 Mbps MII and the 10

Mbps-only 7-wire interface, which uses a subset of the MII pins for connection to an external Ethernet

transceiver.

The FEC incorporates the following features:

•

Support for three different Ethernet physical interfaces:

— 100-Mbps IEEE 802.3 MII

— 10-Mbps IEEE 802.3 MII

— 10-Mbps 7-wire interface (industry standard)

IEEE 802.3 full duplex flow control

•

Programmable max frame length supports IEEE Std 802.1™ VLAN tags and priority

Support for full-duplex operation (200 Mbps throughput) with a minimum system clock rate of

50 MHz

•

Support for half-duplex operation (100 Mbps throughput) with a minimum system clock rate of

25 MHz

•

Retransmission from transmit FIFO following a collision (no processor bus utilization)

Automatic internal flushing of the receive FIFO for runts (collision fragments) and address

recognition rejects (no processor bus utilization)

•

Address recognition

— Frames with broadcast address may be always accepted or always rejected

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

15

Functional Description and Application Information

— Exact match for single 48-bit individual (unicast) address

— Hash (64-bit hash) check of individual (unicast) addresses

— Hash (64-bit hash) check of group (multicast) addresses

— Promiscuous mode

•

Independent DMA engine with multiple channels allowing transmit data, transmit descriptor,

receive data, and receive descriptor accesses to provide high performance

Independent RISC-based controller that provides the following functions in the FEC:

— Initialization (those internal registers not initialized by the user or hardware)

— High level control of the DMA channels (initiating DMA transfers)

— Interpreting buffer descriptors

— Address recognition for receive frames

— Random number generation for transmit collision backoff timer

•

The Message Information Block (MIB) in FEC maintains counters for a variety of network events

and statistics. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and

some of the IEEE 802.3 counters.

2.3.14 General Purpose I/O Module (GPIO)

The general-purpose input/output (GPIO) module provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When it is configured as an output, you can write to an internal

register to control the state driven on the output pin. When configured as an input, you can detect the state

of the input by reading the state of an internal register. The GPIO includes all of the general purpose

input/output logic necessary to drive a specific data to the pad and control the direction of the pad using

registers in the GPIO module. The ARM926 is able to sample the status of the corresponding pads by

reading the appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify

interrupt edges as well as generate three active high interrupts.

2.3.15 General Purpose Timer (GPT)

The i.MX27/MX27L processors contains six identical 32-bit General Purpose Timers (GPT) with

programmable prescalers and compare and capture registers. Each timer’s counter value can be captured

using an external event, and can be configured to trigger a capture event on the rising or/and falling edges

of an input pulse. Each GPT can also generate an event on the TOUT pin, and an interrupt when the timer

reaches a programmed value. Each GPT has an 11-bit prescaler that provides a programmable clock

frequency derived from multiple clock sources, including ipg_clk_32k, ipg_clk_perclk, ipg_clk_perclk/4,

and external clock from the TIN pin. The counter has two operation modes: free-run and restart mode. The

GPT can work in low-power mode.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Functional Description and Application Information

2.3.16 Inter IC Communication (I²C)

2

Inter IC Communication (I C) is a two-wire, bidirectional serial bus that provides a simple, efficient

method of data exchange, minimizing the interconnection between devices. This bus is suitable for

applications requiring occasional communications over a short distance between many devices. The

2

flexible I C enables additional devices to be connected to the bus for expansion and system development.

2

The I C operates up to 400 kbps dependent on pad loading and timing. (For pad requirement details, refer

2

to Phillips I C Bus Specification, Version 2.1.) The I C system is a true multiple-master bus, including

arbitration and collision detection that prevents data corruption if multiple devices attempt to control the

bus simultaneously. This feature supports complex applications with multiprocessor control and can be

used for rapid testing and alignment of end products through external connections to an assembly-line

computer.

2.3.17 IC Identification Module (IIM)

The IC Identification Module (IIM) provides an interface for reading and in some cases programming

and/or overriding identification and control information stored in on-chip fuse elements. The module

supports laser fuses (L-Fuses) or electrically-programmable poly fuses (e-Fuses) or both.

Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC,

IIM, SAHARA2

2.3.18 JTAG Controller (JTAGC)

The JTAG Controller (JTAGC) module supports debug access to the ARM926 Platform and tristate enable

of the I/O pads. The overall strategy is to achieve good test and debug features without increasing the pin

count and reducing the complexity of I/O muxing. The JTAG Controller is compatible with

IEEE Std 1149.1™ Standard Test Access Port and Boundary Scan Architecture.

2.3.19 Keypad Port (KPP)

The Keypad Port (KPP) is designed to interface with a keypad matrix with 2-contact or 3-point contact

keys. KPP is designed to simplify the software task of scanning a keypad matrix. With appropriate

software support, the KPP is capable of detecting, debouncing, and decoding one or multiple keys pressed

simultaneously in the keypad. The KPP supports up to 8 × 8 external key pad matrix. Its port pins can be

used as general purpose I/O. Using an open drain design, the KPP includes glitch suppression circuit

design, multiple keys, long key, and standby key detection.

2.3.20 Liquid Crystal Display Controller (LCDC)

The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD

panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive

color or CSTN), and active-matrix color (active color or TFT) LCD panels.

The LCDC provides the following features:

•

Configurable AHB bus width (32-bit/64-bit)

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

17

Functional Description and Application Information

•

Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD

panels

•

16 simultaneous gray-scale levels from a palette of 16 for monochrome display

Support for:

— Maximum resolution of 800 × 600

— Passive color panel:

– 4 (mapped to RGB444)/8 (mapped to RGB444)/12 (RGB444) bits per pixel (bpp)

— TFT panel:

– 4 (mapped to RGB666)/8 (mapped to RGB666)/12 (RGB444)/16 (RGB565)/18 (RGB666)

bpp

— 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp CSTN display,

respectively

— 16 and 256 colors out of a palette of 256 colors for 4 bpp and 8 bpp TFT display, respectively

— True 4096 colors for a 12 bpp display

— True 64-Kbyte colors for 16 bpp

— True 256-Kbyte colors for 18 bpp

— 16-bit AUO TFT LCD Panel

— 24-bit AUO TFT LCD Panel

2.3.21 Multi-Master Memory Interface (M3IF)/M3IF-ESDCTL/MDDRC

Interface

The M3IF-ESDCTL/MDDRC interface is optimized and designed to reduce access latency by generating

multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls the

access to and from the Enhanced SDRAM/MDDR memory controller. For the other port interfaces, the

M3IF only arbitrates and forwards the master requests received through the Master Port Gasket (MPG)

interface and M3IF Arbitration (M3A) module toward the respective memory controller. The masters that

interface with the M3IF include the ARM Platform, FEC, LCDC, H.264, and the USB. The controllers are

the ESDCTL/MDDRC, PCMCIA, NFC, and WEIM.

2.3.22 Multi-Layer AHB Crossbar Switch (MAX)

The ARM926EJ-S processor’s instruction and data buses—and all alternate bus master

interfaces—arbitrate for resources via a 6 × 34 Multi-Layer AHB Crossbar Switch (MAX). There are six

(M0–M5) fully functional master ports and three (S0–S2) fully functional slave ports. The MAX is

uni-directional. All master and slave ports are AHB-Lite compliant.

The design of the crossbar switch enables concurrent transactions to proceed from any master port to any

slave port. That is, it is possible for all three slave ports to be active at the same time as a result of three

independent master requests. If a particular slave port is simultaneously requested by more than one master

port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the

bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration

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Functional Description and Application Information

schemes supported are fixed, programmable fixed, programmable default input port parking, and a round

robin arbitration scheme.

The Crossbar Switch also monitors the ccm_br input (clock control module bus request), which requests

a bus grant from all four slave ports. The priority of ccm_br is programmable and defaults to the highest

priority. Upon receiving bus grants for all four output ports, the ccm_bg output will assert. At this point,

the clock control and reset module (CRM) can turn off hclk and be assured there are no outstanding AHB

transactions in progress. Once the CRM is granted a port, no other master will receive a grant on that port

until the CRM bus request (ccm_br) negates.

2.3.23 Memory Stick Host Controller (MSHC)

The Memory Stick Host Controller (MSHC) is located between the AIPI and the Sony Memory Stick and

provides support for data transfers between the i.MX27 processor and the Memory Stick (MS). The MSHC

consists of two sub-modules; the MSHC gasket and the Sony Memory Stick Host Controller (SMSC). The

SMSC module, which is the actual memory stick host controller, is compatible with Sony Memory Stick

Ver 1.x and Memory Stick PRO. The gasket connects the AIPI IP bus to the SMSC interface to allow

communication and data transfers via the IP Bus.

NOTE

The i.MX27L does not include the MSHC feature.

The MSHC gasket uses a reduced IP Bus interface that supports the IP bus read/write transfers that include

a back-to-back read or write. DMA transfers also take place via the IP Bus interface.

A transfer can be initiated by the DMA or the host (through the AIPI) response to an MSHC DMA request

or interrupt. The SMSC has two DMA address modes—a single address mode and a dual address mode.

The MSHC is set to dual-address mode for transfers with the DMA. In dual-address mode, when the

MSHC requests a transfer with the DMA request (XDRQ), the DMA will initiate a transfer to the MSHC.

NOTE

Details regarding the operation of the MSHC module can be found

separately in Memory Stick/Memory Stick PRO Host Controller IP

Specification 1.3.

2.3.24 NAND Flash Controller (NFC)

NAND Flash Controller (NFC) interfaces standard NAND Flash devices to the i.MX27/MX27L

processors and hides the complexities of accessing the NAND Flash. It provides a glueless interface to

both 8-bit and 16-bit NAND Flash parts with page sizes of 512 Bytes or 2 Kbytes. Its addressing scheme

enables it to access flash devices of almost limitless capacity. The 2-Kbyte RAM buffer of the NAND

Flash is used as the boot RAM during a cold reset (if the i.MX27/MX27L device is configured for a boot

to be carried out from the NAND Flash device). After the boot procedure completes, the RAM is available

as buffer RAM. In addition, the NAND Flash controller provides an X16-bit and X32-bit interface to the

AHB bus on the chip side, and an X8/X16 interface to the NAND Flash device on the external side.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

19

Functional Description and Application Information

2.3.25 Personal Computer Memory Card International Association

(PCMCIA)

The Personal Computer Memory Card International Association (PCMCIA) provides the PCMCIA 2.1

standard, which defines the usage of memory and I/O devices as insertable and exchangeable peripherals

for personal computers or PDAs. Examples of these types of devices include CompactFlash and WLAN

adapters.

The pcmcia_if host adapter module provides the control logic for PCMCIA socket interfaces, and requires

some additional external analog power switching logic and buffering. The additional external buffers

allow the pcmcia_if host adapter module to support one PCMCIA socket. The pcmcia_if shares its chip

level I/O with the external interface to memory (EIM) pins. Additional logic is required to multiplex the

EIM and the pcmcia_if on the same pins.

2.3.26 Digital Phase Lock Loop (DPLL)

Two on-chip Digital Phase Lock Loop (DPLLs) provide clock generation in digital and mixed

analog/digital chips designed for wireless communication and other applications. The DPLLs produce a

high-frequency chip clock signals with a low frequency and phase jitter.

2.3.27 Pulse-Width Modulator (PWM)

The Pulse-Width Modulator (PWM) has a 16-bit counter and is optimized to generate sounds from stored

sample audio images; it can also generate tones. The PWM uses 16-bit resolution and a 4 × 16 data FIFO

to generate sound. The 16-bit up-counter has a source selectable clock with 4 × 16 FIFO to minimize

interrupt overhead. Clock-in frequency is controlled by a 12-bit prescaler for the division of a clock.

Capable of sound and melody generation, the PWM has an active-high or active-low configurable output,

and can be programmed to be active in low-power and debug modes. The PWM can be programmed to

generate interrupts at compare and rollover events.

2.3.28 Real Time Clock (RTC)

The Real Time Clock (RTC) module maintains the system clock, provides stopwatch, alarm, and

interrupt functions, and supports the following features:

•

Full clock—days, hours, minutes, seconds

Minute countdown timer with interrupt

Programmable daily alarm with interrupt

Sampling timer with interrupt

Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts

Operation at 32.768 kHz or 32 kHz, or 38.4 kHz (determined by reference clock crystal)

The prescaler converts the incoming crystal reference clock to a 1 Hz signal, which is used to increment

the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC

interrupts when the TOD settings reach programmed values. The sampling timer generates

fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small

boundaries.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Functional Description and Application Information

2.3.29 Run-TIme Integrity Checker (RTIC)

The Run-Time Integrity Checker (RTIC) is one of the security components in the i.MX27/MX27L

processors. Its purpose is to ensure the integrity of the peripheral memory contents and assist with boot

authentication. The RTIC has the ability to verify the memory contents during system boot and during

run-time execution. If the memory contents at runtime fail to match the hash signature, an error in the

security monitor is triggered.

Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC,

IIM, SAHARA2

2.3.30 Symmetric/Asymmetric Hashing and Random Accelerator

(SAHARA2)

SAHARA2 is a security co-processor, it implements encryption algorithms (AES, DES, and 3DES),

hashing algorithms (MD5, SHA-1, SHA_224, and SHA-256), stream cipher algorithm (ARC4), and a

hardware random number generator.

Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC,

IIM, SAHARA2

2.3.31 Security Controller Module (SCC)

The Security Controller Module (SCC) is a hardware security component. Overall, its primary

functionality is associated with establishing a centralized security state controller and hardware security

state with a hardware configured, unalterable security policy.

Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC,

IIM, and SAHARA2.

2.3.32 Secure Digital Host Controller (SDHC)

The Secure Digital Host Controller (SDHC) controls the MultiMedia Card (MMC), Secure Digital (SD)

memory, and I/O cards by sending commands to cards and performing data accesses to/from the cards. The

Multimedia Card/Secure Digital Host (MMC/SD) module integrates both MMC support along with SD

memory and I/O functions. The SDHC is fully compatible with the MMC System Specification Version

3.0, as well as with the SD Memory Card Specification 1.0, and SD I/O Specification 1.0 with 1/4

channel(s). The maximum data rate in 4-bit mode is 100 Mbps. The SDHC uses a built-in programmable

frequency counter for the SDHC bus, and provides a maskable hardware interrupt for an SDIO interrupt,

internal status, and FIFO status. It has a pair of 32 × 16-bit data FIFO buffers built in.

The MultiMedia Card (MMC) is a universal, low-cost data storage and communication media that is

designed to cover a wide area of applications, including, for example, electronic toys, organizers, PDAs,

and smart phones. The MMC communication is based on an advanced 7-pin serial bus designed to operate

in a low-voltage range.

The Secure Digital Card (SD) is an evolution of MMC technology, with two additional pins in the form

factor. It is specifically designed to meet the security, capacity, performance, and environment

requirements inherent in newly emerging audio and video consumer electronic devices. The physical form

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

21

Functional Description and Application Information

factor, pin assignment, and data transfer protocol are forward-compatible with the MultiMedia Card with

some additions. Under SD, it can be categorized into Memory and I/O. The memory card invokes a

copyright protection mechanism that complies with the security of the SDMI standard, which is faster and

provides the capability for a higher memory capacity. The I/O card provides high-speed data I/O with

low-power consumption for mobile electronic devices.

2.3.33 Smart Liquid Crystal Display Controller Module (SLCDC)

The Smart Liquid Crystal Display Controller (SLCDC) module transfers data from the display memory

buffer to the external display device. Direct Memory Access (DMA) transfers the data transparently with

minimal software intervention. Bus utilization of the DMA is controllable and deterministic.

As cellular phone displays become larger and more colorful, demands on the processor increase. More

CPU power is needed to render and manage the image. The role of the display controller is to reduce the

CPU’s involvement in the transfer of data from memory to the display device so the CPU can concentrate

on image rendering. DMA is used to optimize the transfer. Embedded control information needed by the

display device is automatically read from a second buffer in system memory and inserted into the data

stream at the proper time to completely eliminate the CPU’s role in the transfer.

A typical scenario for a cellular phone display is to have the display image rendered in main system

memory. After the image is complete, the CPU triggers the SLCDC module to transfer the image to the

display device. Image transfer is accomplished by burst DMA, which steals bus cycles from the CPU.

Cycle-stealing behavior is programmable so bus use is kept within predefined bounds. After the transfer

is complete, a maskable interrupt is generated indicating the status. For animated displays, it is suggested

that a two-buffer ping-pong scheme be implemented so that the DMA is fetching data from one buffer

while the next image is rendered into the other.

Several display sizes and types are used in the various products that use the SLCDC. The SLCDC module

has the capability of directly interfacing to the selected display devices. Both serial and parallel interfaces

are supported. The SLCDC module only supports writes to the display controller. SLCDC read operations

from the display controller are not supported.

2.3.34 Synchronous Serial Interface (SSI)

The Synchronous Serial Interface (SSI) is a full-duplex serial port that allows the chip to communicate

with a variety of serial devices. These serial devices can be standard codecs, Digital Signal Processors

(DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC

sound bus standard (I2S) and Intel AC97 standard.

The SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent

transmitter and receiver sections with independent clock generation and frame synchronization.

The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with

separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. The SSI

can work in Normal mode operation using frame sync, and in Network mode operation allowing multiple

devices to share the port with as many as thirty-two time slots.

The SSI provides two sets of Transmit and Receive FIFOs. Each of the four FIFOs is 8 × 24 bits. The two

sets of Tx/RX FIFOs can be used in Network mode to provide two independent channels for transmission

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Functional Description and Application Information

and reception. It also has programmable data interface modes such as I2S, LSB, and MSB aligned and

programmable word lengths. Other program options include frame sync, clock generation, and

programmable I2S modes (Master, Slave, or Normal). Oversampling clock, ccm_ssi_clk is available as

output from SRCK in I2S Master mode.

In addition to AC97 support, the SSI has completely separate clock and frame sync selections for the

receive and transmit sections. In the AC97 standard, the clock is taken from an external source and frame

sync is generated internally. The SSI also has a programmable internal clock divider and Time Slot Mask

registers for reduced CPU overhead (for Tx and RX both).

2.3.35 Universal Asynchronous Receiver/Transmitter (UART)

The i.MX27/MX27L processors contain six UART modules. Each UART module is capable of standard

RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART

provides serial communication capability with external devices through an RS-232 cable or through use

of external circuitry that converts infrared signals to electrical signals (for reception); or it transforms

electrical signals to signals that drive an infrared LED (for transmission) to provide low-speed IrDA

compatibility.

The UART transmits and receives characters that are either 7 or 8 bits in length (program selectable). To

transmit, data is written from the peripheral data bus to a 32-byte transmitter FIFO (TxFIFO). This data is

passed to the shift register and shifted serially out on the transmitter pin (TXD). To receive, data is received

serially from the receiver pin (RXD) and stored in a 32-half-word-deep receiver FIFO (RxFIFO). The

received data is retrieved from the RxFIFO on the peripheral data bus. The RxFIFO and TxFIFO generate

maskable interrupts as well as DMA requests when the data level in each of the FIFO reaches a

programmed threshold level.

The UART generates baud rates based on a programmable divisor and input clock. The UART also

contains programmable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd, even, or no

parity. The receiver detects framing errors, idle conditions, BREAK characters, parity errors, and overrun

errors.

2.3.36 Universal Serial Bus (USB)

The i.MX27/MX27L processors provide three USB ports. The USB module provides high performance

USB On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement,

and the ULPI 1.0 Low Pin Count specification. The module consists of three independent USB cores, each

controlling one USB port.

In addition to the USB cores, the USB module provides for Transceiverless Link (TLL) operation on host

Ports 1 and 2, and provides the ability of routing the OTG transceiver interface to Host Port 1 such that

this transceiver can be used to communicate with a USB peripheral connected to Host Port 1. The USB

module has two connections to the CPU bus—one IP-bus connection for register accesses and one

AHB-bus connection for the DMA transfer of data to and from the FIFOs.

The USB module includes the following features:

•

Full Speed/Low speed Host only core (HOST 1)

Transceiverless Link Logic (TLL) for on board connection to a FS/LS USB peripheral

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23

Functional Description and Application Information

•

Bypass mode to route Host Port 1 signals to OTG I/O port

High Speed /Full Speed/Low Speed Host Only core (Host 2)

Full Speed/Low Speed interface for Serial transceiver

TLL function for direct connection to USB peripheral in FS/LS (serial) operation

High-speed OTG core

The USB module has two main modes of operation: Normal mode and Bypass mode. Furthermore, the

USB interfaces can be configured for high-speed operation (480 Mbps) and/or full/low speed operation

(12/1.5 Mbps). In Normal mode, each USB core controls its corresponding port. In additional to th4e

major operational modes, each port can work in one or more modes, as follows:

PHY mode

In PHY mode, an external serial transceiver is connected to the port. This is used

for off-board USB connections.

TLL mode

In TLL mode, internal logic is enabled to emulate the functionality of two

back-to-back connected transceivers. This mode is typically used for on-board

USB connections to USB-capable peripherals.

Host Port 2 supports ULPI and Serial Transceivers. The OTG port requires a transceiver and is intended

for off-board USB connections.

Serial Interface mode In serial mode, a serial OTG transceiver must be connected. The port does not

support dedicated signals for OTG signaling. Instead, a transceiver with built-in

OTG registers must be used. Typically, the transceiver registers are accessible

over an I2C or SPI interface.

ULPI mode

In this mode, a ULPI transceiver is connected to the port pins to support

high-speed off board USB connection.

Bypass mode

Bypass mode affects the operation of the OTG port and Host Port 1. This mode is

only available when a serial transceiver is used on the OTG port, and the

peripheral device on Port 1 is using a TLL connection. Bypass mode is activated

by setting the bypass bit in the USBCONTROL register. In this mode, the USB

OTG port connections are internally routed to the USB Host 1 port, such that the

transceiver on the OTG port connects to a peripheral USB device on Host Port 1.

The OTG core and the Host 1 core are disconnected from their ports when bypass

is active.

Low Power mode

Each of the three USB cores has an associated power control module that is

controlled by the USB core and clocked on a 32-kHz clock. When a USB bus is

idle, the transceiver can be placed in low-power mode (suspend), after which the

clocks to the USB core can be stopped. The 32-kHz low power clock must remain

active as it is needed for walk-up detection.

2.3.37 Watchdog Timer Module (WDOG)

The Watchdog Timer module (WDOG) protects against system failures by providing a method of escaping

from unexpected events or programming errors. Once the WDOG module is activated, it must be serviced

by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the

WDOG Timer module either asserts the wdog signal or a system reset signal wdog_rst, depending on

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Freescale Semiconductor

Functional Description and Application Information

software configuration. The WDOG Timer module also generates a system reset via a software write to

the Watchdog Control Register (WCR) when there is a detection of a clock monitor event, an external

reset, an external JTAG reset signal, or if a power-on-reset has occurred.

2.3.38 Wireless External Interface Module (WEIM)

The Wireless External Interface Module (WEIM) handles the interface to devices external to the chip,

including generation of chip selects, clocks and controls for external peripherals and memory. It provides

asynchronous and synchronous access to devices with an SRAM-like interface.

The WEIM includes six chip selects for external devices, with two CS signals covering a range of

128 Mbytes, and the other four each covering a range of 32 Mbytes. The 128-Mbyte range can be

increased to 256 Mbytes when combined with the two signals. The WEIM offers selectable protection for

each chip select as well as programmable data port size. There is a programmable wait-state generator for

each chip select and support for Big Endian and Little Endian modes of operation per access.

2.3.39 Video Codec

The Video Codec module is the video processing module in the i.MX27 processor. It supports full duplex

video codec with 25 fps VGA resolution, supports multi-party calls, and integrates multiple video

processing standards, including H.264 BP, MPEG-4 SP, and H.263 P3 (including annex I, J, K, and T), D1

resolution, 30 fps—half-duplex.

NOTE

The Video Codec feature is not available on the i.MX27L

It has three 64-bit AHB-Lite master bus interfaces connecting to the EMI, which includes two read

channels and one write channel. Its 32-bit AHB-Lite master bus is connected to ARM Platform to access

system-internal SRAM.

The Video Codec module contains three major architectural components: video codec processing IP,

AXI-to-AHB bus protocol transfer module, and a 32-bit to 64-bit AHB master bus protocol transfer

module.

The Video Codec module supports following video stream processing features:

•

Multi-standard video codec

— MPEG-4 part-II simple profile encoding/decoding

— H.264/AVC baseline profile encoding/decoding

— H.263 P3 encoding/decoding

— Multi-party call: max processing four image/bitstream encoding and/or decoding

simultaneously

— Multi-format: for example, encodes MPEG-4 bitstream, and decodes H.264 bitstream

simultaneously

•

Coding tools

— High-performance motion estimation

– Single reference frame for both MPEG-4 and H.264 encoding

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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25

Signal Descriptions

– Support 16 reference frame for H.264 decoding

– Quarter-pel and half-pel accuracy motion estimation

– [+/-16, +/-16] Search range

– Unrestricted motion vector

— All variable block sizes are supported (in case of encoding, 8 × 4, 4 × 8, and 4 × 4 block sizes

are not supported).

— MPEG-4 AC/DC prediction and H.264 Intra prediction

— H.263 Annex I, J, K(RS = 0 and ASO =0), and T are supported. In case of encoding, the Annex

I and K(RS=1 or ASO=1) are not supported.

— CIR (Cyclic Intra Refresh)/AIR (Adaptive Intra Refresh)

— Error resilience tools

– MPEG-4 re-synchronize marker and data-partitioning with RVLC (fixed number of

bits/macroblocks between macroblocks)

– H.264/AVC FMO and ASO

– H.263 slice structured mode

— Bit-rate control (CBR and VBR)

Pre/post rotation/mirroring

•

— 8 rotation/mirroring modes for image to be encoded

— 8 rotation/mirroring modes for image to be displayed

Programmability

— Embeds 16-bit DSP processor that is dedicated to processing bitstream and driving codec

hardware

— General purpose registers and interrupt generation for communication between system and

video codec module

3 Signal Descriptions

This section discusses the following:

•

Identifies and defines all device signals in text, tables, and (as appropriate) figures. Signals can be

organized by group, as applicable.

Contains pin-assignment/contact-connection diagrams, if the sequence of information in the data

sheet requires them to be included here.

Table 3 shows the i.MX27/MX27L signal descriptions.

Table 3. i.MX27/MX27L Signal Descriptions

Function/Notes

External Bus/Chip Select (EMI)

Pad Name

A [13:0]

Address bus signals, shared with SDRAM/MDDR, WEIM and PCMCIA, A[10] for

SDRAM/MDDR is not the address but the pre-charge bank select signal.

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Signal Descriptions

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

Pad Name

MA10

Address bus signals for SDRAM/MDDR

Address bus signals, shared with WEIM and PCMCIA

SDRAM/MDDR bank address signals

Data bus signals for SDRAM, MDDR

MDDR data sample strobe signals

A [25:14]

SDBA[1:0]

SD[31:0]

SDQS[3:0]

DQM0–DQM3

EB0

SDRAM data mask strobe signals

Active low external enable byte signal that controls D [15:8], shared with PCMCIA PC_REG.

Active low external enable byte signal that controls D [7:0], shared with PCMCIA PC_IORD.

EB1

OE

Memory Output Enable—Active low output enables external data bus, shared with PCMCIA

PC_IOWR.

CS [5:0]

Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected

by the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default

CSD [1:0] is selected. DTACK is multiplexed with CS4.

CS[5:4] are multiplexed with ETMTRACECLK and ETMTRACESYNC; PF22, 21.

ECB

LBA

Active low input signal sent by flash device to the EIM whenever the flash device must terminate

an on-going burst sequence and initiate a new (long first access) burst sequence.

Active low signal sent by flash device causing external burst device to latch the starting burst

address.

BCLK

RW

Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal

is also shared with the PCMCIA PC_WE.

RAS

SDRAM/MDDR Row Address Select signal

SDRAM/MDDR Column Address Select signal

SDRAM Write Enable signal

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

SDCLK_B

NFWE_B

NFRE_B

NFALE

NFCLE

NFWP_B

NFCE_B

NFRB

SDRAM Clock Enable 0

SDRAM Clock Enable 1

SDRAM Clock

SDRAM Clock_B

NFC Write enable signal, multiplexed with ETMPIPESTAT2; PF6

NFC Read enable signal, multiplexed with ETMPIPESTAT1; PF5

NFC Address latch signal, multiplexed with ETMPIPESTAT0; PF4

NFC Command latch signal, multiplexed with ETMTRACEPKT0; PF1

NFC Write Permit signal, multiplexed with ETMTRACEPKT1; PF2

NFC Chip enable signal, multiplexed with ETMTRACEPKT2; PF3

NFC read Busy signal, multiplexed with ETMTRACEPKT3; PF0

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Signal Descriptions

Pad Name

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

D[15:0]

Data Bus signal, shared with EMI, PCMCIA, and NFC

PC_CD1_B

PC_CD2_B

PC_WAIT_B

PC_READY

PC_PWRON

PC_VS1

PCMCIA card detect signal, multiplexed with ATA ATA_DIOR signal; PF20

PCMCIA card detect signal, multiplexed with ATA ATA_DIOW signal; PF19

PCMCIA WAIT signal, multiplexed with ATA ATA_CS1 signal; PF18

PCMCIA READY/IRQ signal, multiplexed with ATA ATA_CS0 signal; PF17

PCMCIA signal, multiplexed with ATA ATA_DA2 signal; PF16

PCMCIA voltage sense signal, multiplexed with ATA ATA_DA1 signal; PF14

PCMCIA voltage sense signal, multiplexed with ATA ATA_DA0 signal; PF13

PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMARQ signal; PF12

PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMACK signalPF11

PCMCIA card reset signal, multiplexed with ATA ATA_RESET_B signal; PF10

PCMCIA mode signal, multiplexed with ATA ATA_INTRQ signal; PF9

PCMCIA read write signal, multiplexed with ATA ATA_IORDY signal; PF8

PCMCIA output enable signal, multiplexed with ATA ATA_BUFFER_EN signal; PF7

PC_VS2

PC_BVD1

PC_BVD2

PC_RST

IOIS16

PC_RW_B

PC_POE

Clocks and Resets

CLKO

Clock Out signal selected from internal clock signals. Refer to the clock controller for internal

clock selection; PF15.

EXT_60M

This is a special factory test signal. To ensure proper operation, connect this signal to ground.

EXT_266M

OSC26M_TEST

This is a special factory test signal. To ensure proper operation, leave this signal as a no

connect.

RESET_IN

Master Reset—External active low Schmitt trigger input signal. When this signal goes active,

all modules (except the reset module, SDRAMC module, and the clock control module) are

reset.

RESET_OUT

POR

Reset_Out—Output from the internal Hreset_b; and the Hreset can be caused by all reset

source: power on reset, system reset (RESET_IN), and watchdog reset.

Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated

by an external RC circuit designed to detect a power-up event.

XTAL26M

Oscillator output to external crystal

EXTAL26M

Crystal input (26 MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal

oscillator circuit is shut down.

CLKMODE[1:0]

These are special factory test signals. To ensure proper operation, do not connect to these

signals.

EXTAL32K

XTAL32K

Power_cut

32 kHz crystal input (Note: in the RTC power domain)

Oscillator output to 32 kHz crystal (Note: in the RTC power domain)

(Note: in the RTC power domain)

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Signal Descriptions

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

Pad Name

Power_on_reset

(Note: in the RTC power domain)

osc32K_bypass

The signal for osc32k input bypass (Note: in the RTC power domain)

Bootstrap

BOOT [3:0]

System Boot Mode Select—The operational system boot mode of the i.MX27/MX27L processor

upon system reset is determined by the settings of these pins. BOOT[1:0] are also used as

handshake signals to PMIC(VSTBY).

JTAG

JTAG_CTRL

JTAG Controller select signal—JTAG_CTRL is sampled during rising edge of TRST. Must be

pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal

test purposes only.

TRST

TDO

TDI

Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

Serial Output for test instructions and data. Changes on the falling edge of TCK.

Serial Input for test instructions and data. Sampled on the rising edge of TCK.

Test Clock to synchronize test logic and control register access through the JTAG port.

TCK

TMS

Test Mode Select to sequence JTAG test controller’s state machine. Sampled on rising edge of

TCK.

RTCK

JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is

multiplexed with 1-Wire; thus, utilizing 1-Wire will render RTCK unusable and vice versa; PE16.

Secure Digital Interface (X2)

SD1_CMD

SD Command bidirectional signal—If the system designer does not want to make use of the

internal pull-up, via the Pull-up enable register, a 4. 7K–69 K external pull up resistor must be

added. This signal is multiplexed with CSPI3_MOSI; PE22.

SD1_CLK

SD Output Clock. This signal is multiplexed with CSPI3_SCLK; PE23.

SD1_D[3:0]

SD Data bidirectional signals—If the system designer does not want to make use of the internal

pull-up, via the Pull-up enable register, a 50 K–69 K external pull up resistor must be added.

SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO PE21–18.

SD2_CMD

SD2_CLK

SD2_D[3:0]

SD3_CMD

SD3_CLK

SD Command bidirectional signal. This signal is multiplexed with MSHC_BS; through GPIO

multiplexed with SLCDC1_CS; PB8.

SD Output Clock signal. This signal is multiplexed with MSHC_SCLK, through GPIO

multiplexed with SLCDC1_CLK; PB9.

SD Data bidirectional signals. SD2_D[3:0] multiplexed with MSHC_DATA[0:3], also through

GPIO SD2_1:0] multiplexed with SLCDC1_RS and SLDCD1_D0; PB7–PB4.

SD Command bidirectional signal. This signal is through GPIO PD0 multiplexed with

FEC_TXD0.

SD Output Clock signal. This signal is multiplexed with ETMTRACEPKT15 and also through

GPIO PD1 multiplexed with FEC_TXD1.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Signal Descriptions

Pad Name

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

Note: SD3_DATA is multiplexed with ATA_DATA3–0.

UARTs (X6)

UART1_RTS

UART1_CTS

UART1_RXD

UART1_TXD

UART2_RXD

UART2_TXD

UART2_RTS

UART2_CTS

UART3_RTS

UART3_CTS

UART3_RXD

UART3_TXD

Request to Send input signal; PE15

Clear to Send output signal; PE14

Receive Data input signal; PE13

Transmit Data output signal, PE12

Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP; PE7.

Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP; PE6.

Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP; PE4.

Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP; PE3.

Request to Send input signal, PE11

Clear to Send output signal; PE10

Receive Data input signal; PE9

Transmit Data output signal; PE8

Note: UART 4, 5, and 6 are multiplexed with COMS Sensor Interface signals.

Keypad

KP_COL[5:0]

KP_ROW[5:0]

Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and

UART2_TXD respectively. Alternatively, KP_COL6 is also available on the internal factory test

signal TEST_WB2. The Function Multiplexing Control Register in the System Control chapter

must be used in conjunction with programming the GPIO multiplexing (to select the alternate

signal multiplexing) to choose which signal KP_COL6 is available.

Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and

UART2_RXD signals respectively. The Function Multiplexing Control Register in the System

Control chapter must be used in conjunction with programming the GPIO multiplexing (to select

the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are

available.

Note: KP_COL[7:6] and KP_ROW[7:6] are multiplexed with UART2 signals as show above, also see UARTs table.

PWM

PWMO

PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and

TOUT3 of the General Purpose Timer module; PE5.

CSPI (X3)

CSPI1_MOSI

CSPI1_MISO

CSPI1_SS[2:0]

Master Out/Slave In signal, PD31

Master In/Slave Out signal, PD30

Slave Select (Selectable polarity) signal, the CSPI1_SS2 is multiplexed with

USBH2_DATA5/RCV; and CSPI1_SS1 is multiplexed with EXT_DMAGRANT; PD26–28.

CSPI1_SCLK

Serial Clock signal, PD29

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Signal Descriptions

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

Pad Name

CSPI1_RDY

Serial Data Ready signal, shared with Ext_DMAReq_B signal; PD25

Master Out/Slave In signal, multiplexed with USBH2_DATA1/TXDP; PD24

Master In/Slave Out signal, multiplexed with USBH2_DATA2/TXDm; PD23

CSPI2_MOSI

CSPI2_MISO

CSPI2_SS[2:0]

Slave Select (Selectable polarity) signals, multiplexed with USBH2_DATA4/RXDM,

USBH2_DATA3/RXDP, USBH2_DATA6/SPEED; PD19–PD21

CSPI2_SCLK

Serial Clock signal, multiplexed with USBH2_DATA0/OEn; PD22

Note: CSPI3 CSPI3_MOSI, CSPI3_MISO, CSPI3_SS, andCSPI3_SCLK are multiplexed with SD1 signals.

2

I C

2

I2C2_SCL

I2C2_SDA

I2C_CLK

I C2 Clock, through GPIO, multiplexed with SLCDC_data8; PC6

2

I C2 Data, through GPIO, multiplexed with SLCDC_data7; PC5

2

I C1 Clock; PD18

2

I2C_DATA

I C1 Data; PD17

CMOS Sensor Interface

CSI_HSYNC

CSI_VSYNC

CSI_D7

Sensor port horizontal sync, multiplexed with UART5_RTSP; PB21

Sensor port vertical sync, multiplexed with UART5_CTS; PB20

Sensor port data, multiplexed with UART5_RXD; PB19

Sensor port data, multiplexed with UART5_TXD; PB18

Sensor port data; PB17

CSI_D6

CSI_D5

CSI_PIXCLK

CSI_MCLK

CSI_D4

Sensor port data latch clock; PB16

Sensor port master clock, PB15

Sensor port data, PD14

CSI_D3

Sensor port data, multiplexed with UART6_RTS; PB13

Sensor port data, multiplexed with UART6_CTS; PB12

Sensor port data, multiplexed with UART6_RXD; PB11

Sensor port data, multiplexed with UART6_TXD; PB10

CSI_D2

CSI_D1

CSI_D0

Serial Audio Port—SSI (Configurable to I2S Protocol and AC97) (2 to 4)

SSI1_CLK

SSI1_TXD

SSI1_RXD

SSI1_FS

Serial clock signal that is output in master or input in slave; PC23

Transmit serial data; PC22

Receive serial data; PC21

Frame Sync signal that is output in master and input in slave; PC20

Serial clock signal that is output in master or input in slave, multiplexed with GPT4_TIN. PC27

Transmit serial data signal, multiplexed with GPT4_TOUT; PC26

SSI2_CLK

SSI2_TXD

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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31

Signal Descriptions

Pad Name

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

SSI2_RXD

SSI2_FS

Receive serial data, multiplexed with GPT5_TIN; PC25

Frame Sync signal which is output in master and input in slave, multiplexed with GPT5_TOUT:

PC24

SSI3_CLK

SSI3_TXD

SSI3_RXD

SSI3_FS

Serial clock signal which is output in master or input in slave. This signal is multiplexed with

SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31.

Transmit serial data signal which is multiplexed with SLCDC2_CS, through GPIO multiplexed

with PC_READY; PC30

Receive serial data which is multiplexed with SLCDC2_RS; through GPIO multiplexed with

PC_VS1; PC29

Frame Sync signal which is output in master and input in slave. This signal is multiplexed with

SLCDC2_D0; through GPIO multiplexed with PC_VS1; PC28.

SSI4_CLK

Serial clock signal which is output in master or input in slave; through GPIO multiplexed with

PC_BVD1; PC19

SSI4_TXD

SSI4_RXD

SSI4_FS

Transmit serial data; through GPIO multiplexed with PC_BVD2; PC18

Receive serial data; through GPIO multiplexed with IOIS16; PC17

Frame Sync signal which is output in master and input in slave; PC16

General Purpose Timers (X6)

TIN

Timer Input Capture or Timer Input Clock—The signal on this input is applied to GPT 1–3

simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL,

Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15.

TOUT1

Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with

SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply

TOUT, and is also multiplexed with GPT6_TIN; PC14.

Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads.

USB2.0

USBOTG_DIR/TXDM

USBOTG_STP/TXDM

USBOTG_NXT/TXDM

USBOTG_CLK/TXDM

USBOTG_DATA7/SUSPEND

USBH2_STP/TXDM

USB OTG direction/Transmit Data Minus signal, multiplexed with KP_ROW7A; PE2

USB OTG Stop signal/Transmit Data Minus signal, multiplexed with KP_ROW6A; PE1

USB OTG NEXT/Transmit Data Minus signal, multiplexed with KP_COL6A; PE0

USB OTG Clock/Transmit Data Minus signal, PE24

USB OTG Data7/Suspend signal, PE25

USB Host2 Stop signal/Transmit Data Minus signal, PA4

USBH2_NXT/TXDM

USB Host2 NEXT/Transmit Data Minus signal, PA3

USBH2_DATA7/SUSPEND

USBH2_DIR/TXDM

USB Host2 Data7/Suspend signal, PA2

USB Host2 Direction/Transmit Data Minus signal, PA1

USBH2_CLK/TXDM

USB Host2 Clock/Transmit Data Minus signal; PA0

USBOTG_DATA3/RXDP

USB OTG data4/Receive Data Plus signal; multiplexed with SLCDC1_DAT15 through PC13

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

32

Freescale Semiconductor

Signal Descriptions

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

Pad Name

USBOTG_DATA4/RXDM

USBOTG_DATA1/TXDP

USBOTG_DATA2/TXDm

USBOTG_DATA0/Oen

USBOTG_DATA6/SPEED

USB OTG data4/Receive Data Minus signal; multiplexed with SLCDC1_DAT14 through PC12

USB OTG data1/Transmit Data Plus signal; multiplexed with SLCDC1_DAT13 through PC11

USB OTG data2/Transmit Data Minus signal; multiplexed with SLCDC1_DAT12 through PC10

USB OTG data0/Output Enable signal; multiplexed with SLCDC1_DAT11 through PC9

USB OTG data6/Suspend signal; multiplexed with SLCDC1_DAT10 and USBG_TXR_INT_B

through PC8

USBOTG_DATA5/RCV

USBH1_RXDP

USB OTG data5/RCV signal; multiplexed with SLCDC1_DAT9 through PC7

USB Host1 Receive Data Plus signal, multiplexed with UART4_RXD; multiplexed with

SLCDC1_DAT6 and UART4_RTS_ALT through PB31

USBH1_RXDM

USBH1_TXDP

USBH1_TXDM

USB Host1 Receive Data Minus signal; multiplexed with SLCDC1_DAT5 and UART4_CTS

through PB30

USB Host1 Transmit Data Plus signal; multiplexed with UART4_CTS, multiplexed with

SLCDC1_DAT4 and UART4_RXD_ALT through PB29

USB Host1 Transmit Data Minus signal; multiplexed with UART4_TXD, multiplexed with

SLCDC1_DAT3 through PB28

USBH1_OE_B

USBH1_FS

USB Host1 Output Enable signal; multiplexed with SLCDC1_DAT2 through PB27

USB Host1 Full Speed output signal, multiplexed with UART4_RTS, multiplexed with

SLCDC1_DAT1 through PB26

USBH1_RCV

USB_OC_B

USB_PWR

USB Host1 RCV signal; multiplexed with SLCDC1_DAT0 through PB25

USB OC signal. PB24

USB Power signal; PB23

USBH1_SUSP

USB Host1 Suspend signal; PB22

LCD Controller and Smart LCD Controller

OE_ACD

CONTRAST

VSYNC

Alternate Crystal Direction/Output Enable; PA31

This signal is used to control the LCD bias voltage as contrast control; PA30

Frame Sync or Vsync—This signal also serves as the clock signal output for gate;

driver (dedicated signal SPS for Sharp panel HR-TFT); PA29.

HSYNC

Line Pulse or HSync; PA28

SPL_SPR

Sampling start signal for left and right scanning. Through GPIO, this signal is multiplexed with

the SLCDC1_CLK; PA27.

PS

Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed

with the SLCDC1_CS; PA26.

CLS

REV

Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated

signal). This signal is multiplexed with the SLCDC1_RS; PA25.

Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This

signal is multiplexed with SLCDC1_D0; PA24.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

33

Signal Descriptions

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

Pad Name

LD [17:0]

LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. Through GPIO,

LD[15:0] signals are multiplexed with SLCDC1_DAT[15:0], SLCDC. PA23–PA6.

LSCLK

Shift Clock; PA5

Note: SLCDC signals are multiplexed with LCDC signals.

ATA (not available on i.MX27L)

ATA_DATA15–0

ATA Data Bus, [15:0] are multiplexed with

ETMTRACEPKT4–12,

FEC_MDIO,

ETMTRACEPKT13–14

SD3_D3–0;

Through GPIO also are multiplexed with SLCDC 15–0, and FEC signals; PF23, PD16–PD2.

Noisy I/O Supply Pins

N

1–15, A

Noisy Supply for the I/O pins. There are 16 I/O voltage pads, N

Analog Supply Pins

1 through N

15 + A

.

VDD

FPM

Supply for analog blocks

VDD

MPLL

VDD

OSC26

VDD

UPLL

VDD

OSC32

VDD

OSC32VSS

FPMVSS

Quiet GND for analog blocks

MPLLVSS

OSC26VSS

UPLLVSS

Q

Internal Power Supply

VDD

Q

Power supply pins for silicon internal circuitry

GND pins for silicon internal circuitry

VDD

QVSS

FUSE

For Fuse

VDD

RTC

For RTC, SCC power supply

For RTC, SCC GND

VDD

RTCVSS

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

34

Freescale Semiconductor

Signal Descriptions

Table 3. i.MX27/MX27L Signal Descriptions (continued)

Function/Notes

Pad Name

Note: Both 1-Wire and Fast Ethernet Controller signals are multiplexed with other signals. As a result these signal names do not

appear in this list. The signals are listed below with the named signal that they are multiplexed.

1-Wire Signals:

The 1-Wire input and output signal is multiplexed with JTAG RTCK pad, PE16.

Fast Ethernet Controller (FEC) Signals on the i.MX27. The ATA module does not exist on the i.MX27L:

FEC_TX_EN: Transmit enable signal, through GPIO multiplexed with ATA_DATA15 pad; PF23

FEC_TX_ER: Transmit Data Error; through GPIO multiplexed with ATA_DATA14 pad; PD16

FEC_COL: Collision signal; through GPIO multiplexed with ATA_DATA13 pad; PD15

FEC_RX_CLK: Receive Clock signal; through GPIO multiplexed with ATA_DATA12 pad; PD14

FEC_RX_DV: Receive data Valid signal; through GPIO multiplexed with ATA_DATA11 pad; PD13

FEC_RXD0: Receive Data0; through GPIO multiplexed with ATA_DATA10 pad; PD12

FEC_TX_CLK: Transmit Clock signal; through GPIO multiplexed with ATA_DATA9 pad; PD11

FEC_CRS: Carrier Sense enable; through GPIO multiplexed with ATA_DATA8 pad; PD10

FEC_MDC: Management Data Clock; through GPIO multiplexed with ATA_DATA7 pad; PD9

FEC_MDIO: Management Data Input/Output, multiplexed with ATA_DATA6 pad; PD8

FEC_RXD3–1: Receive Data; through GPIO multiplexed with ATA_DATA5–3 pad; PD7–5

FEC_RX_ER: Receive Data Error; through GPIO multiplexed with ATA_DATA2 pad; PD4

FEC_TXD3–2: Transmit Data; through GPIO multiplexed with ATA_DATA1–0; pad; PD3–2

FEC_TXD1: Transmit Data; through GPIO multiplexed with SD3_CLK pad; PD1

FEC_TXD0: Transmit Data; through GPIO multiplexed with SD3_CMD pad; PD0

Note: The Rest ATA signals are multiplexed with PCMCIA Pads.

3.1

Power-Up Sequence

The i.MX27/MX27L processor consists of three major sets for power supply voltage named Q_VDD(core

logic supply), FUSE_VDD(analog supply for FUSEBOX), and N_VDD,VDDA (IO supply). The External

Voltage Regulators and power-on devices must provide the applications processor with a specific sequence

of power and resets to ensure proper operation.

It is important that the applications processor power supplies be powered-up in a certain order to avoid

unintentional fuse blown. Q_VDDshould be powered up before FUSE_VDD. The recommended order is:

1. Q_VDD(1.5 V)

2. FUSE_VDD(1.8 V), N_VDD(1.8/2.775 V), and Analog Supplies (2.775 V). See Table 3 for signal

descriptions.

or

1. Q_VDD(1.5 V), N_VDD(1.8/2.775 V), and Analog Supplies (2.775 V). See Table 3 for signal

descriptions.

2. FUSE_VDD(1.8 V).

3.2

EMI Pins Multiplexing

This section discusses the multiplexing of EMI signals. The EMI signals’ multiplexing is done inside the

EMI. Table 4 lists the i.MX27 pin names, pad types, and the memory devices’ equivalent pin names.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

35

Signal Descriptions

Pin Name

Table 4. EMI Multiplexing

Pad Type

WEIM

SDRAM

PCMCIA

DDR

NFC

A0

A1

regular

ddr

A0

A1

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

—

A0

A1

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

—

A2

A3

A4

A5

A6

A7

A8

A9

A10

MA10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

SDBA1

SDBA0

SD0

SD1

SD2

SD3

SD4

SD5

A10

—

A10

—

MA10

MA11

MA12

MA13

—

MA10

MA11

MA12

MA13

—

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

—

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

CE1

CE2

—

SDBA1

SDBA0

SD0

SD1

SD2

SD3

SD4

SD5

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

36

Freescale Semiconductor

Signal Descriptions

NFC

Table 4. EMI Multiplexing (continued)

Pin Name

Pad Type

WEIM

SDRAM

PCMCIA

DDR

SD6

SD7

ddr

—

SD6

SD7

—

SD8

ddr

—

SD8

—

SD9

ddr

—

SD9

—

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD20

SD21

SD22

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD30

SD31

DQM0

DQM1

DQM2

DQM3

EB0

ddr

—

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD20

SD21

SD22

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD30

SD31

DQM0

DQM1

DQM2

DQM3

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

ddr

—

regular

EB0

EB1

OE

CS0

CS1

REG

IORD

IOWR

—

EB1

—

OE

—

CS0

—

CS1

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

37

Signal Descriptions

Pin Name

Table 4. EMI Multiplexing (continued)

Pad Type

WEIM

SDRAM

PCMCIA

DDR

NFC

CS2

CS3

regular

—

CS2

CS3

CS4

CS5

ECB

LBA

BCLK

RW

—

CSD0

CSD1

—

CS4

—

CS5

—

ECB

—

LBA

—

OE

—

BCLK

RW

—

WE

—

RAS

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

—

CAS

—

SDWE

SDCKE0

SDCKE1

SDCLK

SDQS0

SDQS1

SDQS2

SDQS3

NFWE

NFRE

NFALE

NFCLE

NFWP

NFCE

NFRB

D15

—

ddr

—

SDQS0

SDQS1

SDQS2

SDQS3

—

ddr

—

ddr

—

ddr

—

regular

—

WE

RE

ALE

CLE

WP

CE

R/B

D15

D14

D13

D12

D11

D10

D9

D8

D7

—

D15

D14

D13

D12

D11

D10

D9

D8

D7

—

D15

D14

D13

D12

D11

D10

D9

D8

D7

—

D14

—

D13

—

D12

—

D11

—

D10

—

D9

—

D8

—

D7

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

38

Freescale Semiconductor

Signal Descriptions

NFC

Table 4. EMI Multiplexing (continued)

Pin Name

Pad Type

WEIM

SDRAM

PCMCIA

DDR

D6

D5

regular

D6

D5

D4

D3

D2

D1

D0

—

D6

D5

—

D6

D5

D4

D3

D2

D1

D0

—

D4

D3

D2

D1

D0

PC_CD1

PC_CD2

PC_WAIT

PC_READY

PC_PWRON

PC_VS1

PC_VS2

PC_BVD1

PC_BVD2

PC_RST

IOIS16

CD1

CD2

WAIT

READY

PC_PWRON

VS1

VS2

BVD1

BVD2

RST

IOIS16/WP

RW

PC_RW

PC_POE

M_REQUEST

M_GRANT

POE

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

39

Electrical Characteristics

4 Electrical Characteristics

This section provides the chip-level and module-level electrical characteristics for the i.MX27/iMX27L.

4.1

i.MX27/iMX27L Chip-Level Conditions

This section provides the chip-level electrical characteristics for the IC. See Table 5 for a quick reference

to the individual tables and sections.

Table 5. i.MX27/iMX27L Chip-Level Conditions

For these characteristics…

Table 6, “DC Absolute Maximum Conditions”

Topic appears…

on page 40

on page 42

on page 43

Table 7, “DC Operating Conditions”

Table 9, “Interface Frequency”

Table 10, “Frequency Definition for Power Consumption Measurement”

Table 11, “Current Consumption”

Section 4.1.3, “Test Conditions and Recommended Settings”

Table 6 provides the DC absolute maximum operating conditions.

CAUTION

Stresses beyond those listed under Table 6 may cause permanent damage to

device. These are stress ratings only. Functional operation of device at these

or any other conditions beyond those indicated under “DC operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions

for extended periods may affect device reliability.

Table 6. DC Absolute Maximum Conditions

Ref.

Num

Parameter

Symbol

Min

Max

Units

1

2

3

4

Supply Voltage

V

–0.5

–20

1.52

3.3

V

DDmax

Supply Voltage (Level Shift I/O)

Input Voltage Range

V

DDIOmax

V

NV (1, 5–13) + 0.3

Imax

DD

o

Storage Temperature Range

T

125

C

storage

Table 7 provides the DC recommended operating conditions.

Table 7. DC Operating Conditions

ID

Parameter

Symbol

Min

Typical

Max

Units

1

2

Core Supply Voltage (@266 MHz)

Core Supply Voltage (@400 MHz)

QV

1.2

1.3

1.52

V

DD

1.38

1.45

DD

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

40

Freescale Semiconductor

Electrical Characteristics

Table 7. DC Operating Conditions (continued)

Parameter Symbol Min

RTC

ID

Typical

Max

Units

3

4

5

RTC, SCC separate Supply Voltage

1.2

1.75

1.35

1.7

—

1.52

2.8

V

VDD

1

I/O Supply Voltage, Fast (7, 11, 12, 14, 15)

NV

DD_FAST

DD_SLOW

I/O Supply Voltage, Slow (5, 6, 8, 9, 10, 13, AV

)

NV

—

3.05

3.1

DD

—

2

6

7

8

I/O Supply Voltage, DDR (1, 2, 3, 4)

NV

—

1.9

DD_DDR

Analog Supply Voltage: FPMV , UPLLV , MPLLV

V

DD

1.4

1.875

1.6

DD

Fusebox read Supply Voltage

FUSEV

1.95

DD

(read mode)

9

Fusebox Program Supply Voltage

FUSEV

3.00

3.15

3.30

V

DD

(program mode)

10 OSC32V

11 OSC26V

V

1.1

2.68

–20

–40

—

1.6

2.875

85

V

DD

OSC32

OSC26

o

12 Operating Ambient Temperature (17mm x17mm package)

13 Operating Ambient Temperature (19mm x19mm package)

Note:

T

C

A

o

T

85

C

A

1

Segments 11, 14, 15 are mixture of Fast and Slow GPIO.

Segments 1, 3, 4 are mixture of DDR and Fast GPIO.

2

4.1.1

DPLL Frequency Specification

Table 8 provides the frequency specifications for the DPLL.

Table 8. DPLL FREQUENCY Specifications

Parameter

Min

Typical

Max

Unit

Output Duty Cycle (dpdck)

48.5

—

50.0

—

51.5

80

%

Output Duty Cycle (dpgdck_2)

Frequency Lock Time

µs

(FOL mode or non-integer MF)

Phase Lock Time

—

100

0.2

µs

ns

Cycle-to-Cycle Jitter

1

MPLL Operating Frequency

600

MHz

1

A 600 MHz MPLL frequency equals 1.2 GHz at the 2x clock port (see figure 3-2 in MCIMX27 reference

manual), so by using the DIV3 divider, it results in an ARM clock frequency of 400 MHz.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

41

Electrical Characteristics

Table 9 provides information for interface frequency limits.

Table 9. Interface Frequency

ID

Parameter

Symbol

Min

Typical

Max

Units

1

JTAG: TCK Frequency of Operation

f

DC

5

33.25

MHz

JTAG

4.1.2

Current Consumption

Table 10 defines the frequency settings used for specifying power consumption in Table 11. All power

states are specified. The temperature setting of 25° C is used for specifying the Deep Sleep Mode (DSM)

per the temperature range shown in Table 7.

Table 10. Frequency Definition for Power Consumption Measurement

ID

Parameter

Symbol

Value

Units

1

2

3

4

5

MCU core

f

266

400

MHz

kHz

MCUmeas@266

MCUmeas@400

MCU AHB bus

MCU IP bus

OSC32

f

133

MCU-AHBmeas

f

66

MCU-IPmeas

f

32.768

osc32khzmeas

Table 11 shows the power consumption for the i.MX27/iMX27L device.

Table 11. Current Consumption

ID

Parameter

Conditions

Symbol Typical

Max Units

1

RUN Current RUN Current at 266 MHz

Idd

215

366

11

260

mA

RUN

o

(QV current)

QV = 1.3 V. Ta = 25 C

DD

RUN Current at 400 MHz

Idd

420

RUN

o

QV = 1.45 V, Ta = 25 C

DD

2

Doze Current

• QV = 1.2 V

Idd

13.5

DD

DOZE

• NV = 1.75 V

DD

• ARM is in wait for interrupt mode.

• ARM well bias is enabled.

• MCU PLL is on.

• SPLL is off.

• FPM is on.

• 26MHz oscillator is on.

• 32 kHz oscillator is on.

• Other modules are off.

• T = 25° C.

A

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

42

Freescale Semiconductor

Electrical Characteristics

Max Units

Table 11. Current Consumption (continued)

Conditions Symbol Typical

Idd 0.9

ID

Parameter

Sleep Current • QV = 1.2 V.

3

3.5

mA

DD

SLEEP

• NV = 1.75 V.

DD

• Both PLLs are off.

• FPM is off.

• ARM well bias is enabled.

• 32 kHz oscillator is on.

• 26MHz oscillator is off.

• All the modules are off.

• T = 25° C.

A

4

Power Gate

• NV

is on. See Table 7 for specific values. Idd

50

216

µA

DD13

PG

• RTC

, OSC32

are on. See Table 7 for

VDD

specific values.

• All other V = 0 V

DD

• T = 25° C.

A

4.1.3

Test Conditions and Recommended Settings

Unless specified, AC timing parameters are specified for 15 pF loading on i.MX27/iMX27L pads. Drive

strength has been kept at default/reset values for testing. EMI timing has been verified with high drive

strength setting and 25 pF loads. SDHC timing has also been verified with high drive strength setting.

Unless otherwise noted, AC/DC parameters are guaranteed at operating conditions shown in Table 7.

4.2

Module-Level Electrical Specifications

This section contains the i.MX27/iMX27L electrical information including timing specifications, arranged

in alphabetical order by module name.

4.2.1

Pads IO (PADIO) Electricals

DC Electrical Characteristics

4.2.1.1

The over-operating characteristics appear in Table 12 for GPIO pads and Table 13 for DDR (Double Data

Rate) pads (unless otherwise noted).

Table 12. GPIO Pads DC Electrical Parameters

Parameter

Symbol

Test Conditions

= -1 mA

Min

N -0.15

VDD

Typical

Max

Units

High-level output voltage

V

I

—

V

OH

I

= specified Drive

0.8*N

OH

VDD

Low-level output voltage

V

I

= 1 mA

OL

—

0.15

OL

I

= specified Drive

—

0.2*N

VDD

OL

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

43

Electrical Characteristics

Table 12. GPIO Pads DC Electrical Parameters (continued)

Parameter

Symbol

Test Conditions

Min

Typical

Max

Units

High-level output current, slow slew rate

I

V

= 0.8*N

Normal

High

—

mA

OH_S

OH

VDD

–2

–4

–8

1

Max High

High-level output current, fast slew rate

Low-level output current, slow slew rate

Low-level output current, fast slew rate

I

= 0.8*N

Normal

High

—

mA

OH_F

OH

VDD

–4

–6

–8

1

Max High

I

= 0.2*N

Normal

High

OL_S

OL

VDD

2

4

8

1

Max High

I

= 0.2*N

Normal

High

OL_F

OL

VDD

4

6

8

1

Max High

Input Hysteresis

V

Hysteresis enabled

0.25

—

V

HYS

Schmitt trigger VT+

V +

Hysteresis enabled

0.5*Q

VDD

T

Schmitt trigger VT-

V -

Hysteresis enabled

—

15

30

34

25

—

0.5*Q

VDD

T

Pull-up resistor (22 kΩ PU)

Pull-up resistor (47 kΩ PU)

Pull-up resistor (100 kΩ PU)

Pull-down resistor (100 kΩ PD)

Input current (no PU/PD)

R

—

22

59

128

268

343

1

PU

R

47

PU

kΩ

μA

R

100

0.33

PU

R

PD

I

V = 0

IN

I

V = N

I

VDD

Input current (22 kΩ PU)

Input current (47 kΩ PU)

Input current (100 kΩ PU)

Input current (100 kΩ PD)

Tri-state input leakage current

I

V = 0

—

115

0.1

μA

IN

I

V = N

I

V = 0

53

0.1

μA

IN

I

V = N

I

V = 0

—

25

0.1

μA

IN

I

V = N

I

V = 0

—

0.25

28

μA

IN

I

V = N

I

V = N or 0

VDD

0.33

2

μA

Z

I

I/O = high Z

High Level DC Input Voltage

Low-Level DC Input Voltage

V

0.7*V

—

V

DDIO

V

IH

—

DDIO

V

0

0.3*V

DDIO

IL

Note:

1

Max High strength should be avoided due to excessive overshoot and ringing.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

44

Freescale Semiconductor

Electrical Characteristics

Table 13. DDR (Double Data Rate) I/O Pads DC Electrical Parameters

Parameter

Symbol

Test Conditions

= -1 mA

Min

Typical

Max

Units

High-level output voltage

V

I

NV

—

V

OH

DD_DDR

–0.08

I

= specified Drive 0.8*NV

—

V

OH

DD_

DDR

Low-level output voltage

High-level output current

V

I

= 1 mA

OL

—

0.08

V

OL

I

= specified Drive

0.2*NV

OL

DD_

DDR

I

V

=0.8*NV

DD_DDR

—

mA

OH

Normal

High

Max High

DDR Drive

–3.6

–7.2

–10.8

–14.4

1

Low-level output current

I

V

=0.2*NV

—

mA

OL

OL DD_DDR

Normal

High

Max High

3.6

7.2

10.8

14.4

1

DDR Drive

Low-level input current

High-level input current

Tri-state current

I

V = 0

—

1.7

2

μA

IL

I

V = NV

I DD_DDR

IH

I

V = NV

or 0

DD_DDR

Z

I

I/O = high Z

Note:

1

Max High and DDR Drive strengths should be avoided due to excessive overshoot and ringing.

4.2.1.2

AC Electrical Characteristics

Figure 2 depicts the load circuit for output pads. Figure 3 depicts the output pad transition time waveform.

The range of operating conditions appear in Table 14 for slow general I/O, Table 15 for fast general I/O,

and Table 16 for DDR I/O (unless otherwise noted).

From Output

Under Test

Test Point

CL

CL includes package, probe and jig capacitance

Figure 2. Load Circuit for Output Pad

NVDD

0 V

80%

20%

80%

20%

PA1

Output (at pad)

PA1

Figure 3. Output Pad Transition Time Waveform

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

45

Electrical Characteristics

Table 14. AC Electrical Characteristics of Slow General I/O Pads

ID

Parameter

Symbol Test Condition

Min

Typical

Max

Units

PA1 Output Pad Transition Times (Max High)

tpr

25 pF

50 pF

1.25

1.95

1.9

2.9

3.2

4.75

ns

Output Pad Transition Times (High)

tpr

25 pF

50 pF

1.45

2.6

—

4.8

8.4

ns

Output Pad Transition Times (Standard Drive)

tpr

25 pF

50 pF

2.6

5.1

8.5

16.5

1

—

Maximum Input Transition Times

trm

—

25

Note:

1

Hysteresis mode is recommended for input with transition time greater than 25 ns.

Table 15. AC Electrical Characteristics of Fast General I/O Pads

ID

Parameter

Symbol Test Condition

Min

Typical

Max

Units

PA1

Output Pad Transition Times (Max High)

tpr

25 pF

50 pF

0.9

1.7

1.2

2.4

2.0

4.0

ns

Output Pad Transition Times (High)

Output Pad Transition Times (Normal)

25 pF

50 pF

1.15

2.3

1.6

3.1

2.7

5.3

ns

tpr

25 pF

50 pF

1.7

3.4

2.4

4.7

4.0

8.0

1

—

Maximum Input Transition Times

trm

—

25

Note:

1

Hysteresis mode is recommended for input with transition time greater than 25 ns.

Table 16. AC Electrical Characteristics of DDR I/O Pads

ID

Parameter

Symbol Test Condition

Min

Typical

Max

Units

PA1

Output Pad Transition Times (DDR Drive)

tpr

trm

25 pF

50 pF

0.5

1.0

0.75

1.45

1.2

2.4

ns

Output Pad Transition Times (Max High)

Output Pad Transition Times (High)

Output Pad Transition Times (Normal)

Maximum Input Transition Times

25 pF

50 pF

0.67

1.3

1.0

2.0

1.6

3.1

ns

25 pF

35 pF

1.0

1.95

1.5

2.9

2.4

4.7

25 pF

50 pF

2.0

3.9

2.9

5.9

4.8

8.4

—

5

4.2.2

1-Wire Electrical Specifications

Figure 4 depicts the RPP timing, and Table 17 lists the RPP timing parameters.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

46

Freescale Semiconductor

Electrical Characteristics

1-Wire Tx

“Reset Pulse”

DS2502 Tx

“Presence Pulse”

OW2

One-Wire bus

(BATT_LINE)

OW3

OW1

OW4

Figure 4. Reset and Presence Pulses (RPP) Timing Diagram

Table 17. RPP Sequence Delay Comparisons Timing Parameters

ID

Parameters

Symbol

Min

Typical

Max

Units

OW1

OW2

OW3

OW4

Reset Time Low

Presence Detect High

t

480

15

511

—

µs

—

RSTL

PDH

60

240

—

Presence Detect Low

Reset Time High

60

—

PDL

480

512

RSTH

Figure 5 depicts Write 0 Sequence timing, and Table 18 lists the timing parameters.

OW6

One-Wire bus

(BATT_LINE)

OW5

Figure 5. Write 0 Sequence Timing Diagram

Table 18. WR0 Sequence Timing Parameters

ID

Parameter

Symbol

Min

Typical

Max

Units

OW5

OW6

Write 0 Low Time

Transmission Time Slot

t

60

100

117

120

µs

WR0_low

t

OW5

SLOT

Figure 6 depicts Write 1 Sequence timing, Figure 7 depicts the Read Sequence timing, and Table 19 lists

the timing parameters.

OW8

One-Wire bus

(BATT_LINE)

OW7

Figure 6. Write 1 Sequence Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

47

Electrical Characteristics

OW8

One-Wire bus

(BATT_LINE)

OW7

OW9

Figure 7. Read Sequence Timing Diagram

Table 19. Write 1/Read Timing Parameters

ID

Parameter

Symbol

Min

Typical

Max

Units

OW7

OW8

OW9

Write 1/Read Low Time

Transmission Time Slot

Release Time

t

1

5

15

120

45

µs

LOW1

t

60

15

117

—

SLOT

t

RELEASE

4.2.3

ATA Electrical Specifications

This section describes the electrical information of the Parallel ATA module compliant with ATA/ATAPI-6

specification.

NOTE

The parallel ATA module is not available on the i.MX27L

Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode

has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MB/s. Parallel ATA

module interface consist of a total of 29 pins, Some pins act on different function in different transfer

mode. There are different requirements of timing relationships among the function pins conform with

ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.

Below defines the AC characteristics of all the interface signals on all data transfer modes.

4.2.3.1

General Timing Requirements

These are the general timing requirements for the ATA interface signals.

Table 20. AC Characteristics of All Interface Signals

ID

Parameter

Symbol

Min

Max

Unit

SI1

Rising edge slew rate for any signal on ATA

interface (see note)

S

—

1.25

V/ns

rise

SI2

Falling edge slew rate for any signal on ATA

interface (see note)

S

—

1.25

V/ns

fall

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

48

Freescale Semiconductor

Electrical Characteristics

Table 20. AC Characteristics of All Interface Signals (continued)

ID

Parameter

Symbol

Min

Max

20

Unit

SI3

Host interface signal capacitance at the host

connector

C

—

pF

host

Note: SRISE and SFALL meets this requirement when measured at the sender’s connector from 10–90% of full signal

amplitude with all capacitive loads from 15 pf through 40 pf where all signals have the same capacitive load value.

ATA Interface Signals

SI2

SI1

Figure 8. ATA interface Signals Timing Diagram

4.2.4

Digital Audio Mux (AUDMUX)

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSI, SAP) and external serial interfaces (audio and voice codecs). The AC timing

of AUDMUX external pins is hence governed by SSI and SAP modules. Please refer to their respective

electrical specifications.

4.2.5

CMOS Sensor Interface (CSI)

This section describes the electrical information (AC timing) of the CSI.

4.2.5.1 Gated Clock Mode Timing

VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on

VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC

is high. Figure 9 and Figure 10 depict the gated clock mode timings of CSI, and Table 21 lists the timing

parameters.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

49

Electrical Characteristics

Figure 9 shows sensor output data on the pixel clock falling edge. The CSI latches data on the pixel clock

rising edge.

1

VSYNC

7

HSYNC

2

5

6

PIXCLK

Valid Data

DATA[7:0]

3

4

Figure 9. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Falling Edge, Latch Data at Rising Edge

Figure 10 shows sensor output data on the pixel clock rising edge. The CSI latches data on the pixel clock

falling edge.

1

VSYNC

HSYNC

PIXCLK

DATA[7:0]

7

2

5

6

Valid Data

3

4

Figure 10. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Rising Edge, Latch Data at Falling Edge

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

50

Freescale Semiconductor

Electrical Characteristics

Table 21. Gated Clock Mode Timing Parameters

Number

Parameter

Minimum

Maximum

Unit

1

2

3

4

5

6

7

csi_vsync to csi_hsync

csi_hsync to csi_pixclk

csi_d setup time

9*THCLK

—

(Tp/2)-3

—

ns

3

1

ns

csi_d hold time

—

ns

csi_pixclk high time

csi_pixclk low time

csi_pixclk frequency

THCLK

0

—

ns

—

ns

HCLK/2

MHz

HCLK = AHB System Clock, THCLK = Period for HCLK, Tp = Period of CSI_PIXCLK

The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold

time and setup time based on the following assumptions:

Rising-edge latch data:

max rise time allowed = (positive duty cycle—hold time)

max fall time allowed = (negative duty cycle—setup time)

In most of case, duty cycle is 50/50, therefore:

max rise time = (period/2—hold time)

max fall time = (period/2—setup time)

For example: Given pixel clock period = 10 ns, duty cycle = 50/50, hold time = 1 ns, setup time = 1 ns.

positive duty cycle = 10/2 = 5 ns

max rise time allowed = 5 –1 = 4 ns

negative duty cycle = 10/2 = 5 ns

max fall time allowed = 5 –1 = 4 ns

Falling-edge latch data:

max fall time allowed = (negative duty cycle—hold time)

max rise time allowed = (positive duty cycle—setup time)

4.2.5.2

Non-Gated Clock Mode Timing

In non-gated mode only, the VSYNC, and PIXCLK signals are used; the HSYNC signal is ignored. Figure

3 and Figure 4 show the different clock edge timing of CSI and Sensor in Non-Gated Mode. Table 3 is the

parameter value. Figure 11 and Figure 12 show the non-gated clock mode timings of CSI, and Table 22

lists the timing parameters.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

51

Electrical Characteristics

Figure 11 shows sensor output data on the pixel clock falling edge. The CSI latches data on the pixel clock

rising edge.

1

VSYNC

6

4

5

PIXCLK

Valid Data

DATA[7:0]

2

3

Figure 11. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Falling Edge, Latch Data at Rising

Edge

Figure 12 shows sensor output data on the pixel clock rising edge. The CSI latches data on the pixel clock

falling edge.

1

VSYNC

6

5

4

PIXCLK

Valid Data

3

DATA[7:0]

2

Figure 12. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Rising Edge, Latch Data at Falling

Edge

Table 22. Non-Gated Clock Mode Parameters

Number

Parameter

Minimum

Maximum

Unit

—

csi_vsync to csi_pixclk

csi_d setup time

9*THCLK

1

—

ns

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

52

Freescale Semiconductor

Electrical Characteristics

Table 22. Non-Gated Clock Mode Parameters (continued)

Number

Parameter

csi_d hold time

Minimum

Maximum

Unit

—

1

—

ns

csi_pixclk high time

csi_pixclk low time

csi_pixclk high time

THCLK

0

—

ns

HCLK/2

MHz

HCLK = AHB System Clock, THCLK = Period of HCLK

4.2.6

Configurable Serial Peripheral Interface (CSPI)

This section describes the electrical information of the CSPI.

4.2.6.1 CSPI Timing

Figure 13 and Figure 14 show the master mode and slave mode timings of CSPI, and Table 23 lists the

timing parameters.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

53

Electrical Characteristics

4.3

Timing Diagrams

Figure 13 and Figure 14 depict the master mode and slave mode timing diagrams of the CSPI and Table 23

lists the timing parameters. The values shown in timing diagrams were tested using a worst case core

voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad voltage of 1.65 V.

t7

t5

SSn

(output)

t8

t9

t6

CSPI1_RDY

(input)

t3

t2

t1

SCLK

(output)

t10

t11

t13

t4

MOSI

MISO

t12

Figure 13. CSPI Master Mode Timing Diagram

t7’

t5’

SSn

(Input)

t6’

t3’

t2’

t1’

SCLK

(Input)

t10

t11

t4

MISO

MOSI

t12

t13

Figure 14. CSPI Slave Mode Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

54

Freescale Semiconductor

Electrical Characteristics

Table 23. CSPI Interface Timing Parameters

Parameter Description Symbol Minimum

ID

Num

Maximum

Units

t1

t2

CSPI master SCLK cycle time

CSPI master SCLK high time

CSPI master SCLK low time

CSPI slave SCLK cycle time

CSPI slave SCLK high time

CSPI slave SCLK low time

CSPI SCLK transition time

SSn output pulse width

t

45.12

22.65

22.47

60.2

-

ns

—

clko

t

—

8.5

—

clkoH

t3

t

clkoL

t1’

t2’

t3’

t4

t

clki

t

30.1

clkiH

t

30.1

clkiL

1

t

2.6

pr

2

3

t5

t

2T

+T

wait

Wsso

sclk

4

t5’

t6

SSn input pulse width

t

T

per

Wssi

SSn output asserted to first SCLK edge (SS output

setup time)

t

3T

sclk

Ssso

t6’

t7

SSn input asserted to first SCLK edge (SS input

setup time)

t

T

+ 20 ns

per

—

ns

—

Sssi

CSPI master: Last SCLK edge to SSn deasserted

(SS output hold time)

t

2T

sclk

Hsso

t7’

t8

CSPI slave: Last SCLK edge to SSn deasserted

(SS input hold time)

t

30

Hssi

Srdy

Hrdy

CSPI master: CSPI1_RDY low to SSn asserted

(CSPI1_RDY setup time)

t

2T

5T

per

t9

CSPI master: SSn deasserted to CSPI1_RDY low

Output data setup time

t

0

—

ns

—

t10

t

(t

t

or t

or

Sdatao

clkoL

clkoH

) -

clkiL

clkiH

5

T

ipg

t11

Output data hold time

t

or t

—

Hdatao

clkoL

clkoH

t

or t

clkiL

clkiH

t12

t13

Input data setup time

Input data hold time

t

T

+ 0.5

ipg

—

ns

Sdatai

t

5

Hdatai

Note:

1

2

3

4

5

The output SCLK transition time is tested with 25 pF drive.

= CSPI clock period

T

sclk

T

= Wait time as per the Sample Period Control Register value.

= CSPI reference baud rate clock period (PERCLK2)

= CSPI main clock IPG_CLOCK period

wait

T

per

ipg

T

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

55

Electrical Characteristics

4.3.1

Direct Memory Access Controller (DMAC)

After assertion of External DMA Request the DMA burst will start when the corresponding DMA channel

becomes the current highest priority channel. The External DMA Request should be kept asserted until it

is serviced by the DMAC. One External request will initiate at least one DMA burst.

The output External Grant signal from the DMAC is an active-low signal. This signal will be asserted

during the time when a DMA burst is ongoing for an External DMA Request, when the following

conditions are true:

•

The DMA channel for which the DMA burst is ongoing has requested source as external DMA

Request (as per RSSR settings).

•

REN and CEN bit of this channel are set.

External DMA Request is asserted.

Once the grant is asserted the External DMA Request will not be sampled until completion of the DMA

burst. The priority of the external request will become low, for the next consecutive burst, if another DMA

request signal is asserted.

The waveforms are shown for the worst case—that is, smallest burst (1 byte read/write). Minimum and

maximum timings for the External request and External grant signal are present in the data sheet.

Figure 15 shows the minimum time for which the External Grant signal remains asserted if External DMA

request is de-asserted immediately after sensing grant signal active.

Ext_DMAReq

Ext_DMAGrant

t

min_assert

Figure 15. Assertion of DMA External Grant Signal

Figure 16 shows the safe maximum time for which External DMA request can be kept asserted, after

sensing grant signal active such that a new burst is not initiated.

Ext_DMAReq

Ext_DMAGrant

t

max_req_assert

Data read from

External device

t

max_read

t

Data written to

External device

max_write

NOTE: Assuming worst case that the data is read/written from/to external device as per the above waveform.

Figure 16. Timing Diagram of Safe Maximums for External Request De-Assertion

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

56

Freescale Semiconductor

Electrical Characteristics

Table 24. DMAC Timing Parameters

3.0 V

1.8 V

Unit

WCS BCS

Parameter

Description

WCS

BCS

Tmin_assert

Minimum assertion time of External Grant signal 8hclk+8.6

8hclk+2.74 8hclk+7.17 8hclk+3.25 ns

Tmax_req_assert Maximum External Request assertion time after 9hclk–20.66 9hclk–6.7 9hclk–17.96 9hclk–8.16 ns

assertion of Grant signal

Tmax_read

Maximum External Request assertion time after 8hclk–6.21 8hclk–0.77 8hclk–5.84 8hclk–0.66 ns

first read completion

Tmax_write

Maximum External Request assertion time after 3hclk–5.87 3hclk–8.83 3hclk–15.9 3hclkv91.2 ns

first write completion

4.3.2

Fast Ethernet Controller (FEC)

This section describes the AC timing specifications of the FEC. The MII signals are compatible with

transceivers operating at a voltage of 3.3 V.

4.3.2.1

MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER,

and FEC_RX_CLK)

The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is

no minimum frequency requirement. In addition, the FEC IPG clock frequency must exceed twice the

FEC_RX_CLK frequency.

Figure 17 shows the MII receive signal timings, and Table 25 lists the timing parameters.

M3

FEC_RX_CLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

M1

M2

Figure 17. MII Receive Signal Timing Diagram

Table 25. MII Receive Signal Timing Parameters

1

ID

Parameter

Min

Max

Unit

M1

M2

M3

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

FEC_RX_CLK pulse width high

5

—

ns

35%

65%

FEC_RX_CLK period

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

57

Electrical Characteristics

Table 25. MII Receive Signal Timing Parameters (continued)

1

ID

Parameter

FEC_RX_CLK pulse width low

Min

Max

Unit

M4

35%

65%

FEC_RX_CLK period

Note:

1

FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

4.3.2.2

MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER,

and FEC_TX_CLK)

The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There

is no minimum frequency requirement. In addition, the FEC IPG clock frequency must exceed twice the

FEC_TX_CLK frequency.

Figure 18 shows the MII transmit signal timings, and Table 26 lists the timing parameters.

M7

FEC_TX_CLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

M6

Figure 18. MII Transmit Signal Timing Diagram

Table 26. MII Transmit Signal Timing Parameters

1

ID

M5

Parameter

Min

Max

Unit

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid

FEC_TX_CLK pulse width high

5

—

ns

M6

—

20

ns

M7

35%

65%

FEC_TX_CLK period

M8

FEC_TX_CLK pulse width low

Note:

1

FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

58

Freescale Semiconductor

Electrical Characteristics

4.3.2.3

MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)

Figure 19 shows the MII asynchronous input timings, and Table 27 lists the timing parameters.

FEC_CRS, FEC_COL

M9

Figure 19. MII Asynchronous Inputs Signal Timing Diagram

Table 27. MII Asynchronous Inputs Signal Timing Parameter

ID

Parameter

Min

Max

Unit

1

M9

Note:

FEC_CRS to FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

1

FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

4.3.2.4

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. The MDC frequency should

be equal to or less than 2.5 MHz to be compliant with IEEE 802.3 MII specification. However the FEC

can function correctly with a maximum MDC frequency of 15 MHz.

Figure 20 shows the MII serial management channel timings, and Table 28 lists the timing parameters.

M14

M15

FEC_MDC (output)

M10

FEC_MDIO (output)

M11

FEC_MDIO (input)

M12

Figure 20. MII Serial Management Channel Timing Diagram

M13

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

59

Electrical Characteristics

Table 28. MII Serial Management Channel Timing Parameters

Parameter Min Max

ID

Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

M14 FEC_MDC pulse width high

0

—

18

0

—

5

ns

—

40% 60% FEC_MDC period

M15 FEC_MDC pulse width low

4.3.3

Inter IC Communication (I²C)

2

This section describes the electrical information of the I C module.

4.3.3.1

I²C Module Timing

The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data

Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 21 shows the timing of the

2

I C module. Table 29 lists the I2C module timing parameters.

SDA

IC5

IC3

IC4

SCL

IC2

IC1

IC6

2

Figure 21. I C Bus Timing Diagram

Table 29. I2C Module Timing Parameters

1.8 V +/–0.10 V

3.0 V +/–0.30 V

ID

Parameter

Unit

Min

Max

Min

Max

—

SCL Clock Frequency

Hold time (repeated) START Condition

Data Hold Time

0

100

—

0

100

—

kHz

ns

IC1

IC2

IC3

IC4

IC5

IC6

114.8

0

111.1

0

69.7

—

72.3

—

Data Setup Time

3.1

1.76

68.3

335.1

111.1

HIGH period of the SCL clock

LOW period of the SCL clock

Setup Time for STOP condition

69.7

336.4

110.5

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

60

Freescale Semiconductor

Electrical Characteristics

4.3.4

JTAG Controller (JTAGC)

This section details the electrical characteristics for the JTAGC module. Figure 22 shows the JTAGC test

clock input timing; Figure 23 shows the JTAGC boundary scan timing; Figure 24 shows the JTAGC test

access port; Figure 25 shows the JTAGC TRST timing; and Table 30 lists the JTAGC timing parameters.

J1

J2

Tck

(input)

J3

Figure 22. Test Clock Input Timing Diagram

TCK

(input)

J5

J4

Data

(inputs)

Input Data Valid

J6

Data

(outputs)

Output Data Valid

J7

J6

Data

(outputs)

Data

(outputs)

Output Data Valid

Figure 23. Boundary Scan Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

61

Electrical Characteristics

TCK

(input)

J9

J8

TDI, TMS

(inputs)

Input Data Valid

J10

TD0

(outputs)

Output Data Valid

J11

TD0

(outputs)

J10

TD0

(outputs)

Output Data Valid

Figure 24. Test Access Port (TAP) Diagram

TCK

(input)

J13

TRST

(input)

J12

Figure 25. TRST Timing Diagram

Table 30. JTAGC Timing Parameters

All Frequencies

ID

Parameter

Unit

Min

Max

J1

J2

J3

J4

J5

TCK cycle time in crystal mode

TCK clock pulse width measured at VM

TCK rise and fall times

30.08

15.04

—

ns

1

2.0

—

Boundary scan input data set-up time

Boundary scan input data hold time

3.5

16.0

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

62

Freescale Semiconductor

Electrical Characteristics

Table 30. JTAGC Timing Parameters (continued)

All Frequencies

ID

Parameter

Unit

Min

Max

J6

J7

TCK low to output data valid

—

25.0

—

ns

TCK low to output high impedance

TMS, TDI data set-up time

TMS, TDI data hold time

J8

3.5

20.0

—

J9

—

J10

J11

J12

J13

Note:

TCK low to TDO data valid

TCK low to TDO high impedance

TRST assert time

29.0

—

70.0

2.5.0

TRST set-up time to TCK low

—

1

Midpoint voltage

4.3.5

Liquid Crystal Display Controller Module (LCDC)

Figure 26 and Figure 27 depict the timings of the LCDC, and Table 31 and Table 32 list the timing

parameters.

T5

FLM

Line n

Line 1

Line 2

LP

T2

LP

T1

T3

T6

LSCLK

LD

T4

Figure 26. LCDC Non-TFT Mode Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

63

Electrical Characteristics

Table 31. LCDC Non-TFT Mode Timing Parameters

ID

Description

Min

Max

Unit

T1

T2

T3

T4

T5

T6

Pixel Clock period

22.5

1000

—

ns

1

LP width

1

5

2

1

T

LD setup time

LD hold time

—

ns

—

1

Wait between LP and FLM rising edge

—

T

1

Wait between last data and LP rising edge

—

T

Note:

1

T is pixel clock period.

VSYNC

Line n

Line 1

Line 2

HSYNC

T2

T5

T6

OE

T1

T3

LSCLK

LD

T4

Figure 27. LCDC TFT Mode Timing Diagram

Table 32. LCDC TFT Mode Timing Parameters

ID

Description

Min

Ma

Unit

T1

T2

T3

T4

Pixel Clock period

HSYNC width

LD setup time

LD hold time

22.5

1000

—

ns

1

5

3

1

T

—

ns

—

1

T5

T6

Delay from the end of HSYNC to the beginning of the OE pulse.

Delay from end of OE to the beginning of the HSYNC pulse.

—

T

1

—

T

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

64

Freescale Semiconductor

Electrical Characteristics

1

T is pixel clock period.

4.3.6

Memory Stick Host Controller (MSHC)

Figure 30, Figure 28, and Figure 29 show the MSHC timings. Table 33 and Table 34 list the timing

parameters.

NOTE

The i.MX27L does not contain an MSHC module.

tSCLKc

MSHC_SCLK

tBSsu

tDsu

tBSh

tDh

MSHC_BS

MSHC_DATA

(Output)

tDd

MSHC_DATA

(Input)

Figure 28. Transfer Operation Timing Diagram (Serial)

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

65

Electrical Characteristics

tSCLKc

MSHC_SCLK

tBSsu

tDsu

tBSh

tDh

MSHC_BS

MSHC_DATA

(Output)

tDd

MSHC_DATA

(Input)

Figure 29. Transfer Operation Timing Diagram (Parallel)

tSCLKc

tSCLKwh

tSCLKwl

MSHC_SCLK

tSCLKr

tSCLKf

Figure 30. MSHC_CLK Timing Diagram

Table 33. Serial Interface Timing Parameters

Standards

Signal

Parameter

Symbol

Unit

Min.

Max.

MSHC_SCLK

Cycle

tSCLKc

tSCLKwh

tSCLKwl

tSCLKr

50

15

—

10

ns

H pulse length

L pulse length

Rise time

Fall time

tSCLKf

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

66

Freescale Semiconductor

Electrical Characteristics

Table 33. Serial Interface Timing Parameters (continued)

Standards

Signal

Parameter

Symbol

Unit

Min.

Max.

MSHC_BS

Setup time

tBSsu

tBSh

tDsu

tDh

5

—

15

ns

Hold time

MSHC_DATA

Setup time

Hold time

5

Output delay time

tDd

—

Table 34. Parallel Interface Timing Parameters

Standards

Min Max

Signal

Parameter

Symbol

Unit

MSHC_SCLK

Cycle

tSCLKc

tSCLKwh

tSCLKwl

tSCLKr

tSCLKf

tBSsu

tBSh

25

5

—

10

—

15

ns

H pulse length

L pulse length

Rise time

5

—

8

Fall time

MSHC_BS

Setup time

Hold time

1

MSHC_DATA

Setup time

Hold time

tDsu

8

tDh

1

Output delay time

tDd

—

4.3.7

NAND Flash Controller Interface (NFC)

Figure 31, Figure 32, Figure 33, and Figure 34 show the relative timing requirements among different

signals of the NFC at module level, and Table 35 lists the timing parameters. The NAND Flash Controller

(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,

where time T is the period of the NFC clock in ns. The relationship between the NFC clock and the external

timing parameters of the NFC is provided in Table 35.

Table 35 also provides two examples of external timing parameters with NFC clock frequencies of

22.17 MHz and 33.25 MHz. Assuming a 266 MHz FCLK (CPU clock), NFCDIV should be set to

divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock.

The user should compare the parameters of the selected NAND Flash memory with the NFC external

timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is 66 MHz. It

should also be noted that the default NFC clock on power up is 16.63 MHz.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

67

Electrical Characteristics

NFCLE

NFCE

NF1

NF3

NF2

NF4

NF5

NFWE

NFALE

NF6

NF7

NF9

NF8

command

NFIO[7:0]

Figure 31. Command Latch Cycle Timing Diagram

NFCLE

NFCE

NF1

NF4

NF3

NF5

NFWE

NFALE

NF6

NF7

NF8

NF9

NFIO[7:0]

Address

Time it takes for SW to issue the next address command

Figure 32. Address Latch Cycle Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

68

Freescale Semiconductor

Electrical Characteristics

NFCLE

NFCE

NF1

NF3

NF10

NF11

NF4

NF5

NF8

NFWE

NFALE

NF6

NF9

NFIO[15:0]

Data to Flash

Figure 33. Write Data Latch Timing Diagram

NFCLE

NFCE

NF14

NF3

NF15

NF13

NFRE

NFRB

NF17

NF16

Data from Flash

NFIO[15:0]

NF12

Figure 34. Read Data Latch Timing Diagram

Table 35. NFC Target Timing Parameters

Relationship to NFC NFC clock 22.17 MHz NFC clock 33.25 MHz

clock period (T) T = 45 ns T = 30 ns

ID

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

NF1

NF2

NF3

NF4

NF5

NFCLE Setup Time

NFCLE Hold Time

NFCE Setup Time

NFCE Hold Time

tCLS

tCLH

tCS

T

—

45

—

30

—

ns

tCH

NF_WP Pulse Width

tWP

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

69

Electrical Characteristics

Table 35. NFC Target Timing Parameters (continued)

Relationship to NFC NFC clock 22.17 MHz NFC clock 33.25 MHz

clock period (T)

T = 45 ns

T = 30 ns

ID

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

NF6

NF7

NF8

NF9

NFALE Setup Time

NFALE Hold Time

Data Setup Time

Data Hold Time

tALS

tALH

tDS

T

—

45

—

30

60

30

120

45

60

15

0

—

ns

T

45

tDH

T

45

NF10 Write Cycle Time

NF11 NFWE Hold Time

NF12 Ready to NFRE Low

NF13 NFRE Pulse Width

NF14 READ Cycle Time

NF15 NFRE High Hold Time

NF16 Data Setup on READ

NF17 Data Hold on READ

tWC

tWH

tRR

2T

T

90

45

4T

1.5T

2T

0.5T

15

0

180

67.5

90

tRP

tRC

tREH

tDSR

tDHR

22.5

15

0

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal

value. All timings are listed according to this NFC clock frequency

(multiples of NFC clock period) except NF16, which is not NFC clock

related.

The read data is generated by the NAND Flash device and sampled with the

internal NFC clock.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

70

Freescale Semiconductor

Electrical Characteristics

4.3.8

Personal Computer Memory Card International Association

(PCMCIA)

Figure 35 and Figure 36 show the timings pertaining to the PCMCIA module, each of which is an example

of one clock of strobe setup time and one clock of strobe hold time. Table 36 lists the timing parameters.

HCLK

ADDR 1

HADDR

CONTROL

HWDATA

HREADY

HRESP

CONTROL 1

DATA write 1

OKAY

ADDR 1

A[25:0]

DATA write 1

D[15:0]

WAIT

REG

OE/WE/IORD/IOWR

CE1/CE2

RD/WR

POE

PSHT

PSST

PSL

Figure 35. Write Accesses Timing Diagram—PSHT=1, PSST=1

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

71

Electrical Characteristics

HCLK

HADDR

ADDR 1

CONTROL 1

CONTROL

RWDATA

HREADY

HRESP

DATA read 1

OKAY

ADDR 1

A[25:0]

D[15:0]

WAIT

REG

OE/WE/IORD/IOWR

CE1/CE2

RD/WR

POE

PSST

PSHT

PSL

Figure 36. Read Accesses Timing Diagram—PSHT=1, PSST=1

Table 36. PCMCIA Write and Read Timing Parameters

Symbol

Parameter

Min

Max

Unit

PSHT

PSST

PSL

PCMCIA strobe hold time

0

1

63

clock

PCMCIA strobe set up time

PCMCIA strobe length

128

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

72

Freescale Semiconductor

Electrical Characteristics

4.3.9

SDRAM (DDR and SDR) Memory Controller

Figure 37, Figure 38, Figure 39, Figure 40, Figure 41, and Figure 42 depict the timings pertaining to the

ESDCTL module, which interfaces Mobile DDR or SDR SDRAM. Table 37, Table 38, Table 39, Table 40,

Table 41, and Table 42 list the timing parameters.

SD1

SDCLK

SD2

SD3

SD4

CS

RAS

CAS

SD5

SD4

SD5

SD4

SD5

WE

ADDR

DQ

SD6

SD7

ROW/BA

COL/BA

SD8

SD10

SD9

Data

SD4

DQM

Note: CKE is high during the read/write cycle.

Figure 37. SDRAM Read Cycle Timing Diagram

Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters

SD5

ID

Parameter

Symbol

Min

Max

Unit

SD1

SD2

SD3

SD4

SD5

SDRAM clock high-level width

tCH

tCL

3.4

7.5

2.0

1.8

4.1

—

ns

SDRAM clock low-level width

SDRAM clock cycle time

tCK

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

tCMS

tCMH

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

73

Electrical Characteristics

Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

ID

Parameter

Symbol

Min

Max

Unit

SD6

SD7

SD8

SD9

SD10

Address setup time

Address hold time

SDRAM access time

tAS

tAH

tAC

tOH

tRC

2.0

1.8

—

ns

6.47

—

ns

1

Data out hold time

1.8

10

ns

Active to read/write command period

—

clock

Note:

1

Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see

Table 41 and Table 42.

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 37indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

74

Freescale Semiconductor

Electrical Characteristics

SD1

SDCLK

SD2

SD4

SD3

CS

SD5

RAS

CAS

SD11

SD4

SD5

SD4

WE

SD5

SD12

SD7

SD6

BA

ADDR

COL/BA

DATA

ROW / BA

SD13

SD14

DQ

DQM

Figure 38. SDR SDRAM Write Cycle Timing Diagram

Table 38. SDR SDRAM Write Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD11

SD12

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

tCH

tCL

3.4

7.5

2.0

1.8

2.0

1.8

1

4.1

—

4

ns

tCK

ns

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Address setup time

tCMS

tCMH

tAS

ns

Address hold time

tAH

ns

1

Precharge cycle period

tRP

clock

1

Active to read/write command delay

tRCD

1

8

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

75

Electrical Characteristics

Table 38. SDR SDRAM Write Timing Parameters (continued)

ID

Parameter

Symbol

Min

Max

Unit

SD13

SD14

Data setup time

Data hold time

tDS

tDH

2.0

1.3

—

ns

Note:

1

SD11 and SD12 are determined by SDRAM controller register settings.

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 38indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

SD1

SDCLK

SD2

SD3

CS

RAS

CAS

SD11

SD10

WE

SD7

SD6

BA

ADDR

ROW/BA

Figure 39. SDRAM Refresh Timing Diagram

Table 39. SDRAM Refresh Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

SD1

SD2

SDRAM clock high-level width

SDRAM clock low-level width

tCH

tCL

3.4

4.1

ns

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

76

Freescale Semiconductor

Electrical Characteristics

Table 39. SDRAM Refresh Timing Parameters (continued)

ID

Parameter

SDRAM clock cycle time

Symbol

Min

Max

Unit

SD3

SD6

tCK

tAS

tAH

tRP

tRC

7.5

1.8

1

—

4

ns

Address setup time

Address hold time

SD7

ns

1

SD10

SD11

Precharge cycle period

clock

1

Auto precharge command period

2

20

Note:

1

SD10 and SD11 are determined by SDRAM controller register settings.

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 39indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

77

Electrical Characteristics

SDCLK

CS

RAS

CAS

WE

ADDR

CKE

BA

SD16

Don’t care

Figure 40. SDRAM Self-Refresh Cycle Timing Diagram

NOTE

The clock continues to run unless both CKEs are low. Then the clock is

stopped in low state.

Table 40. SDRAM Self-Refresh Cycle Timing Parameters

ID

Parameter

CKE output delay time

Symbol

Min

Max

Unit

SD16

tCKS

1.8

—

ns

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

78

Freescale Semiconductor

Electrical Characteristics

SDCLK

SD20

SD19

DQS (output)

DQ (output)

SD18

Data

SD17

Data

SD17

SD18

Data

DM

Data

DM

Data

DM

Data

DM

DQM (output)

DM

SD17

SD18

Figure 41. Mobile DDR SDRAM Write Cycle Timing Diagram

Table 41. Mobile DDR SDRAM Write Cycle Timing Parameters

1

ID

Parameter

Symbol

Min

Max Unit

SD17 DQ and DQM setup time to DQS

SD18 DQ and DQM hold time to DQS

tDS

tDH

0.95

1.8

—

ns

SD19 Write cycle DQS falling edge to SDCLK output delay time.

SD20 Write cycle DQS falling edge to SDCLK output hold time.

Note:

tDSS

tDSH

1.8

1

Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is

defined as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 41indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

79

Electrical Characteristics

SDCLK

SD23

DQS (input)

DQ (input)

SD22

Data

SD21

Data

Figure 42. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 42. Mobile DDR SDRAM Read Cycle Timing Parameters

ID

Parameter

Symbol Min Max Unit

SD21 DQS–DQ Skew (defines the Data valid window in read cycles related to DQS).

SD22 DQS DQ HOLD time from DQS

tDQSQ

tQH

—

2.3

—

0.85 ns

—

ns

SD23 DQS output access time from SDCLK posedge

tDQSCK

6.7

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is

defined as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 42indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

4.3.9.1

SDHC Electrical DC Characteristics

Table 43 lists the SDHC electrical DC characteristics.

Table 43. SDHC Electrical DC Characteristics

ID

Parameter

Min

Max

Unit

Comments

General

SD10 Peak Voltage on All Lines

All Inputs

–0.3

–10

V

+ 0.3

V

—

DD

SD11 Input Leakage Current

All Outputs

10

μA

SD12 Output Leakage Current

Power Supply

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

80

Freescale Semiconductor

Electrical Characteristics

Table 43. SDHC Electrical DC Characteristics

ID

Parameter

Min

Max

Unit

Comments

SD13 Supply Voltage (low voltage)

SD14 Supply Voltage (high voltage)

SD15 Power Up Time

1.65

2.7

—

1.95

3.6

250

—

V

1.95 ~2.7 V is not supported.

ms

mA

—

SD16 Supply Current

100

Bus Signal Line Load

SD17 Pull-up Resistance

SD18 Open Drain Resistance

Open Drain Signal Level

10

100

NA

kΩ

Internal PU

For MMC cards only

—

NA

SD19 Output High Voltage

SD20 Output Low Voltage

Push-Pull Signal Levels (High Voltage)

SD21 Output HIGH Voltage

SD22 Output LOW Voltage

SD23 Input HIGH Voltage

SD24 Input LOW Voltage

Push-Pull Signal Levels (Low Voltage)

SD25 Output HIGH Voltage

SD26 Output LOW Voltage

SD27 Input HIGH Voltage

SD28 Input LOW Voltage

V

– 0.2

—

V

I

=-100 mA

OH

DD

—

0.3

I

= 2 mA

OL

0.75 x V

—

V

I

=-100 mA @V min

DD

OH DD

0.125 x V

I

=100 mA @V min

DD

OL

DD

0.625 x V

V

+ 0.3

—

DD

V

– 0.3

0.25 x V

SS

DD

V

– 0.2

—

V

I

=-100 mA @V min

OH DD

—

0.2

I

=100 mA @V min

OL

DD

0.7 x V

V

+ 0.3

DD

—

DD

V

– 0.3

0.3 x V

DD

SS

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

81

Electrical Characteristics

4.3.10 Smart Liquid Crystal Display Controller (SLCDC)

Figure 43 and Figure 44 show the timings of the SLCDC, and Table 44 and Table 45 list the timing

parameters.

tcsh

tcss

tcyc

LCD_CS

tcl

tch

tdh

LCD_CLK (LCD_DATA[6])

trsh

LSB

tds

SDATA (LCD_DATA[7])

RS

MSB

trss

RS=0 => command data, RS=1=> display data

This diagram illustrates the timing when the SCKPOL = 1, CSPOL = 0

tcss

tcsh

tcyc

LCD_CS

tcl

tch

tdh

LCD_CLK (LCD_DATA[6])

trsh

LSB

tds

SDATA (LCD_DATA[7])

RS

MSB

trss

RS=0 => command data, RS=1=> display data

This diagram illustrates the timing when the SCKPOL = 0, CSPOL = 0

tcss

tcsh

tcyc

LCD_CS

tcl

tch

tdh

LCD_CLK (LCD_DATA[6])

trsh

LSB

tds

SDATA (LCD_DATA[7])

RS

MSB

trss

RS=0 => command data, RS=1=> display data

This diagram illustrates the timing when the SCKPOL = 1, CSPOL = 1

tcss

tcsh

tcyc

LCD_CS

tcl

tch

tdh

LCD_CLK (LCD_DATA[6])

trsh

LSB

tds

SDATA (LCD_DATA[7])

RS

MSB

trss

RS=0 => command data, RS=1=> display data

This diagram illustrates the timing when the SCKPOL = 0, CSPOL = 1

Figure 43. SLCDC Timing Diagram—Serial Transfers to LCD Device

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

82

Freescale Semiconductor

Electrical Characteristics

Table 44. SLCDC Serial Interface Timing Parameters

Symbol

Parameter

Min

Typical

Max

Units

t

Chip select setup time

Chip select hold time

Serial clock cycle time

Serial clock low pulse

Serial clock high pulse

Data setup time

(t

/ 2) ( ) t

—

ns

css

csh

cyc

prop

/ 2) ( ) t

39 ( ) t

2641

—

prop

t

18 ( ) t

cl

t

—

ch

ds

dh

t

(t

/ 2) ( ) t

—

cyc

prop

t

Data hold time

/ 2) ( ) t

—

t

Register select setup time

Register select hold time

(15 * t

/ 2) ( ) t

prop

—

rss

rsh

cyc

(t

/ 2) ( ) t

—

cyc

prop

LCD_CLK

trss

trsh

LCD_RS

LCD_CS

tcyc

tds

tdh

command data

display data

LCD_DATA[15:0]

LCD_CLK

This diagram illustrates the timing when CSPOL=0

trsh

trss

LCD_RS

LCD_CS

tcyc

tds

tdh

command data

display data

LCD_DATA[15:0]

This diagram illustrates the timing when CSPOL=1

Figure 44. SLCDC Timing Diagram—Parallel Transfers to LCD Device

Table 45. SLCDC Parallel Interface Timing Parameters

Symbol

Parameter

Min

Typical

Max

Units

t

Parallel clock cycle time

Data setup time

78 ( ) t

—

4923

—

cyc

prop

t

(t

/ 2) ( ) t

ds

cyc

prop

t

Data hold time

/ 2) ( ) t

—

dh

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

83

Electrical Characteristics

Symbol

Table 45. SLCDC Parallel Interface Timing Parameters (continued)

Parameter

Min

Typical

Max

Units

t

Register select setup time

Register select hold time

(t

/ 2) ( ) t

—

rss

cyc

prop

t

/ 2) ( ) t

rsh

prop

4.3.11 Synchronous Serial Interface (SSI)

This section describes the electrical information of SSI.

4.3.11.1 SSI Transmitter Timing with Internal Clock

Figure 45 and Figure 46 show the SSI transmitter timing with internal clock, and Table 46 lists the timing

parameters.

SS1

SS5

SS4

SS3

SS2

AD1_TXC

(Output)

SS8

SS6

AD1_TXFS (bl)

(Output)

SS10

SS12

AD1_TXFS (wl)

(Output)

SS14

SS17

SS15

SS16

SS18

AD1_TXD

(Output)

SS43

SS42

SS19

AD1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

Figure 45. SSI Transmitter with Internal Clock Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

84

Freescale Semiconductor

Electrical Characteristics

SS1

SS3

SS5

SS4

SS2

DAM1_T_CLK

(Output)

SS8

SS6

DAM1_T_FS (bl)

(Output)

SS10

SS12

DAM1_T_FS (wl)

(Output)

SS14

SS17

SS15

SS18

SS16

DAM1_TXD

(Output)

SS43

SS42

SS19

DAM1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

Figure 46. SSI Transmitter with Internal Clock Timing Diagram

Table 46. SSI Transmitter with Internal Clock Timing Parameters

ID

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

SS2

SS3

SS4

SS5

SS6

SS8

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

81.4

36.0

—

ns

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

6

36.0

—

6

—

15.0

6

—

SS10 (Tx) CK high to FS (wl) high

SS12 (Tx) CK high to FS (wl) low

—

SS14 (Tx/Rx) Internal FS rise time

SS15 (Tx/Rx) Internal FS fall time

SS16 (Tx) CK high to STXD valid from high impedance

SS17 (Tx) CK high to STXD high/low

SS18 (Tx) CK high to STXD high impedance

SS19 STXD rise/fall time

—

6

—

15.0

6

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

85

Electrical Characteristics

Table 46. SSI Transmitter with Internal Clock Timing Parameters (continued)

ID

Parameter

Min

Max

Unit

Synchronous Internal Clock Operation

SS42 SRXD setup before (Tx) CK falling

SS43 SRXD hold after (Tx) CK falling

SS52 Loading

10.0

0

—

25

ns

pF

—

•

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)

and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync

have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or

the frame sync STFS/SRFS shown in the tables and in the figures.

•

All timings are on AUDMUX pads when SSI is being used for data transfer.

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx

Data (for example, during AC97 mode of operation).

4.3.11.2 SSI Receiver Timing with Internal Clock

Figure 47 and Figure 48 show the SSI receiver timing with internal clock, and Table 47 lists the timing

parameters.

SS1

SS3

SS5

SS4

SS2

AD1_TXC

(Output)

SS9

SS7

AD1_TXFS (bl)

(Output)

SS11

SS13

AD1_TXFS (wl)

(Output)

SS20

SS21

AD1_RXD

(Input)

SS51

SS50

SS47

SS49

SS48

AD1_RXC

(Output)

Figure 47. SSI Receiver with Internal Clock Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

86

Freescale Semiconductor

Electrical Characteristics

SS1

SS7

SS3

SS5

SS4

SS2

DAM1_T_CLK

(Output)

SS9

DAM1_T_FS (bl)

(Output)

SS11

SS13

DAM1_T_FS (wl)

(Output)

SS20

SS21

DAM1_RXD

(Input)

SS47

SS51

SS50

SS49

SS48

DAM1_R_CLK

(Output)

Figure 48. SSI Receiver with Internal Clock Timing Diagram

Table 47. SSI Receiver with Internal Clock Timing Parameters

ID

Parameter

Internal Clock Operation

(Tx/Rx) CK clock period

Min

Max

Unit

SS1

SS2

SS3

SS4

SS5

SS7

SS9

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

6

36.0

—

6

—

15.0

—

SS11 (Rx) CK high to FS (wl) high

SS13 (Rx) CK high to FS (wl) low

—

SS20 SRXD setup time before (Rx) CK low

SS21 SRXD hold time after (Rx) CK low

10.0

0

—

Oversampling Clock Operation

SS47 Oversampling clock period

15.04

6

—

ns

SS48 Oversampling clock high period

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

87

Electrical Characteristics

Table 47. SSI Receiver with Internal Clock Timing Parameters (continued)

ID

Parameter

Min

Max

Unit

SS49 Oversampling clock rise time

SS50 Oversampling clock low period

SS51 Oversampling clock fall time

—

6

3

—

3

ns

—

NOTE

All the timings for the SSI are given for a non-inverted serial clock polarity

(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the

polarity of the clock and/or the frame sync have been inverted, all the timing

remains valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS shown in the tables and in the figures.

All timings are on AUDMUX pads when SSI is being used for data transfer.

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

For internal Frame Sync operation using external clock, the FS timing is the

same as that of Tx Data, for example, during the AC97 mode of operation.

4.3.11.3 SSI Transmitter Timing with External Clock

Figure 49 and Figure 50 show the SSI transmitter timing with external clock, and Table 48 lists the timing

parameters.

SS22

SS23

SS25

SS26

SS24

AD1_TXC

(Input)

SS27

SS29

AD1_TXFS (bl)

(Input)

SS33

SS31

AD1_TXFS (wl)

(Input)

SS39

SS37

SS38

AD1_TXD

(Output)

SS45

SS44

AD1_RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

Figure 49. SSI Transmitter with External Clock Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

88

Freescale Semiconductor

Electrical Characteristics

SS22

SS26

SS25

SS24

SS23

DAM1_T_CLK

(Input)

SS29

SS27

DAM1_T_FS (bl)

(Input)

SS33

SS39

SS31

DAM1_T_FS (wl)

(Input)

SS37

SS38

DAM1_TXD

(Output)

SS45

SS44

DAM1_RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

Figure 50. SSI Transmitter with External Clock Timing Diagram

Table 48. SSI Transmitter with External Clock Timing Parameters

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22 (Tx/Rx) CK clock period

81.4

36.0

—

ns

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

6.0

—

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

36.0

—

6.0

15.0

—

SS27 (Tx) CK high to FS (bl) high

SS29 (Tx) CK high to FS (bl) low

–10.0

10.0

–10.0

10.0

—

SS31 (Tx) CK high to FS (wl) high

SS33 (Tx) CK high to FS (wl) low

SS37 (Tx) CK high to STXD valid from high impedance

SS38 (Tx) CK high to STXD high/low

SS39 (Tx) CK high to STXD high impedance

15.0

—

15.0

—

Synchronous External Clock Operation

SS44 SRXD setup before (Tx) CK falling

10.0

2.0

—

ns

SS45 SRXD hold after (Tx) CK falling

SS46 SRXD rise/fall time

6.0

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

89

Electrical Characteristics

NOTE

All the timings for the SSI are given for a non-inverted serial clock polarity

(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the

polarity of the clock and/or the frame sync have been inverted, all the timing

remains valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS shown in the tables and in the figures.

All timings are on AUDMUX pads when the SSI is being used for data

transfer.

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

For internal Frame Sync operation using external clock, the FS timing will

be same as that of Tx Data, for example, during the AC97 mode of

operation.

4.3.11.4 SSI Receiver Timing with External Clock

Figure 51 and Figure 52 show the SSI receiver timing with external clock, and Table 49 lists the timing

parameters.

SS22

SS26

SS25

SS24

SS23

AD1_TXC

(Input)

SS30

SS28

AD1_TXFS (bl)

(Input)

SS32

SS35

SS34

AD1_TXFS (wl)

(Input)

SS41

SS36

SS40

AD1_RXD

(Input)

Figure 51. SSI Receiver with External Clock Timing Diagram

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

90

Freescale Semiconductor

Electrical Characteristics

SS22

SS24

SS26

SS25

SS23

DAM1_T_CLK

(Input)

SS30

SS28

DAM1_T_FS (bl)

(Input)

SS32

SS35

SS34

DAM1_T_FS (wl)

(Input)

SS41

SS36

SS40

DAM1_RXD

(Input)

Figure 52. SSI Receiver with External Clock Timing Diagram

Table 49. SSI Receiver with External Clock Timing Parameters

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22 (Tx/Rx) CK clock period

81.4

36.0

—

ns

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

SS28 (Rx) CK high to FS (bl) high

SS30 (Rx) CK high to FS (bl) low

SS32 (Rx) CK high to FS (wl) high

SS34 (Rx) CK high to FS (wl) low

SS35 (Tx/Rx) External FS rise time

SS36 (Tx/Rx) External FS fall time

SS40 SRXD setup time before (Rx) CK low

SS41 SRXD hold time after (Rx) CK low

6.0

—

36.0

—

6.0

15.0

—

–10.0

10.0

–10.0

10.0

—

15.0

—

6.0

—

10.0

2.0

—

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

91

Electrical Characteristics

NOTE

All the timings for the SSI are given for a non-inverted serial clock polarity

(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the

polarity of the clock and/or the frame sync have been inverted, all the timing

remains valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS shown in the tables and in the figures.

All timings are on AUDMUX pads when the SSI is being used for data

transfer.

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

For internal Frame Sync operation using external clock, the FS timing will

be same as that of Tx Data, for example, during the AC97 mode of

operation.

4.3.12 Wireless External Interface Module (WEIM)

All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising

edge or falling edge according to corresponding assertion/negation control fields. Address always begins

related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according

to control register configuration. Output data begins related to BCLK rising edge except in muxed mode

where both rising and falling edge may be used according to control register configuration. Input data,

ECB and DTACK all captured according to BCLK rising edge time. Figure 53 shows the timing of the

WEIM module, and Table 50 lists the timing parameters.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

92

Freescale Semiconductor

Electrical Characteristics

WEIM Outputs Timing

WE22

WE23

WE21

BCLK (for rising edge timing)

BCLK (for falling edge timing)

...

WE1

WE2

WE4

WE6

Address

CS[x]

WE3

WE5

RW

WE7

WE9

WE8

OE

WE10

EB[x]

WE11

WE13

WE12

WE14

LBA

Output Data

WEIM Inputs Timing

WE16

BCLK (for rising edge timing)

Input Data

WE15

WE18

WE20

ECB

WE17

WE19

DTACK

Figure 53. WEIM Bus Timing Diagram

Table 50. WEIM Bus Timing Parameters

Parameter

1.8 V

ID

Unit

Min

Max

WE1 Clock fall to address valid

WE2 Clock rise/fall to address invalid

WE3 Clock rise/fall to CS[x] valid

WE4 Clock rise/fall to CS[x] invalid

0.68

0.45

2.05

2.49

2.25

ns

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

93

Electrical Characteristics

Table 50. WEIM Bus Timing Parameters (continued)

1.8 V

ID

Parameter

Unit

Min

Max

WE5 Clock rise/fall to RW Valid

0.90

1.17

0.73

1.03

1.04

2.60

3.57

2.43

2.84

4.01

—

ns

WE6 Clock rise/fall to RW Invalid

WE7 Clock rise/fall to OE Valid

WE8 Clock rise/fall to OE Invalid

WE9 Clock rise/fall to EB[x] Valid

WE10 Clock rise/fall to EB[x] Invalid

WE11 Clock rise/fall to LBA Valid

WE12 Clock rise/fall to LBA Invalid

WE13 Clock rise/fall to Output Data Valid

WE14 Clock rise to Output Data Invalid

WE15 Input Data Valid to Clock rise, FCE=0 (in the case there is

ECB_B asserted during access)

1/2BCLK

+3.6

WE15 Input Data Valid to Clock rise, FCE=0 (in the case there is NO

ECB_B asserted during access)

6.95

—

ns

WE16 Cloc/k rise to Input Data Invalid, FCE=0

WE17 Input Data Valid to Clock rise, FCE=1

WE18 Clock rise to Input Data Invalid, FCE=1

WE19 ECB setup time, FCE=0

WE20 ECB hold time, FCE=0

2.35

1.24

0.23

7.23

2.93

1.08

0

—

ns

WE21 ECB setup time, FCE=1

WE22 ECB hold time, FCE=1

WE23 DTACK setup time

5.35

3.19

3.0

WE24 DTACK hold time

1

WE25 BCLK High Level Width

1

WE26 BCLK Low Level Width

3.0

1

WE27 BCLK Cycle time

7.5

Note:

1

BCLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal

value and low is defined as 50% of signal value.

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal

value.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

94

Freescale Semiconductor

Electrical Characteristics

Test conditions: pad voltage, 1.7–1.95 V; pad capacitance, 25 pF.

Recommended drive strength for all controls, address, and BCLK is Max

High.

Figure 54, Figure 55, Figure 34, Figure 57, Figure 58, and Figure 59 show examples of basic WEIM

accesses to external memory devices with the timing parameters mentioned in Table 50 for specific control

parameter settings.

BCLK

WE2

WE1

WE3

V1

Next Address

WE4

Last Valid Address

ADDR

CS[x]

RW

WE11

WE12

WE8

LBA

WE7

WE9

OE

WE10

WE16

EB[y]

V1

WE15

DATA

Figure 54. Asynchronous Memory Timing Diagram for

Read Access—WSC=1

BCLK

WE2

WE1

Last Valid Address

ADDR

CS[x]

Next Address

V1

WE3

WE5

WE4

WE6

RW

LBA

OE

WE11

WE12

WE10

WE9

EB[y]

DATA

WE14

V1

WE13

Figure 55. Asynchronous Memory Timing Diagram for

Write Access—WSC=1, EBWA=1, EBWN=1, LBN=1

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

95

Electrical Characteristics

BCLK

WE1

WE2

Last Valid Addr

WE3

Address V1

Address V2

ADDR

CS[x]

WE4

RW

WE11

WE7

WE12

LBA

WE8

OE

WE10

WE9

EB[y]

WE18

WE17

ECB

WE17

V1+2

WE16

V1

WE16

WE15

V2

Halfword

V2+2

Halfword

DATA

Halfword Halfword

WE15

Figure 56. Synchronous Memory Timing Diagram for Two Non-Sequential

Read Accesses: WSC=2, SYNC=1, DOL=0

BCLK

ADDR

WE2

WE4

WE6

WE1

Last Valid Addr

Address V1

WE3

CS[x]

RW

WE5

WE12

WE11

LBA

OE

WE10

WE9

EB[y]

WE18

ECB

WE17

V1

WE14

WE13

V1+4 V1+8 V1+12

DATA

WE13

Figure 57. Synchronous Memory TIming Diagram for Burst

Write Access—BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

96

Freescale Semiconductor

Electrical Characteristics

BCLK

WE1

WE14

WE2

ADDR/

M_DATA

Last Valid Addr

Write Data

Address V1

WE13

WE4

WE6

WE3

CS[x]

RW

WE5

Write

WE11

WE12

LBA

OE

WE9

WE10

EB[y]

Figure 58. Muxed A/D Mode Timing Diagram for Asynchronous

Write Access—WSC=7, LBA=1, LBN=1, LAH=1

BCLK

WE16

WE2

WE1

Last Valid Addr

WE3

ADDR/

M_DATA

Address V1

Read Data

WE15

CS[x]

WE4

RW

WE11

WE12

LBA

WE7

WE8

OE

WE9

WE10

EB[y]

Figure 59. Muxed A/D Mode Timing Diagram for Asynchronous

Read Access—WSC=7, LBA=1, LBN=1, LAH=1, OEA=7

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

97

Electrical Characteristics

4.3.12.1 WEIM Synchronous Mode Sample Point

Figure 60 shows the AHB first sample point is the time marker A.

A

B

C

D

HCLK

NONSEQ

SEQ

HTRANS

HWRITE

V1

HADDR

HREADY

WORD1

WORD2

RDATA

BCLK

Addr0

ADDR

CS0

Last Valid Addr

OEA

LBA

RW

EB

RD0

RD1

RD3

DATA_IN

ECB

RD2

Figure 60. FCE=0,SYNC=1,BCD=1,WSC=4,BCS=0,CSA=0,OEA=0

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

98

Freescale Semiconductor

Electrical Characteristics

Figure 61 AHB first sample point is the time marker A

B

A

C

D

HCLK

NONSEQ

SEQ

HTRANS

HWRITE

V1

HADDR

HREADY

WORD1

WORD2

RDATA

BCLK

Addr0

Last Valid Addr

ADDR

CS0

OEA

LBA

RW

EB

RD0

RD1

RD3

DATA_IN

ECB

RD2

Figure 61. FCE=0,SYNC=1,BCD=1,WSC=6,BCS=0,CSA=0,OEA=0

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

99

Electrical Characteristics

Figure 62 AHB first sample point is the time marker A.

B

A

C

D

HCLK

NONSEQ

SEQ

HTRANS

HWRITE

V1

HADDR

HREADY

WORD1

WOR

RDATA

BCLK

Addr0

Last Valid Addr

ADDR

CS0

OEA

LBA

RW

EB

RD0

RD1

RD3

DATA_IN

ECB

RD2

Figure 62. FCE=0,SYNC=1,BCD=1,WSC=8,BCS=0,CSA=0,OEA=0

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

100

Freescale Semiconductor

Electrical Characteristics

Figure 63 AHB first sample point is the time marker A, If ECB is asserted during access, the sample point

will be changed to the negative of the BCLK(just like the sample point C&D).

B

A

C

D

HCLK

NONSEQ

SEQ

HTRANS

HWRITE

V1

HADDR

HREADY

WORD2

WORD1

RDATA

BCLK

Addr0

ADDR

CS0

Last Valid Addr

OEA

LBA

RW

EB

RD0

RD1

RD3

DATA_IN

ECB

RD2

Figure 63. FCE=0,SYNC=1,BCD=1,WSC=4,BCS=0,CSA=0, OEA=0

4.3.13 USBOTG Electricals

This section describes the electrical information of the USB OTG port and host ports.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

101

Electrical Characteristics

4.3.14 Serial Interface

In order to support four serial different interfaces, the USBOTG transceiver can be configured to operate

in one of the following modes:

•

DAT_SE0 bidirectional, 3-wire mode

DAT_SE0 unidirectional, 6-wire mode

VP_VM bidirectional, 4-wire mode

•

VP_VM unidirectional, 6-wire mode

4.3.14.1 DAT_SE0 Bidirectional Mode

Table 51. Signal Definitions—DAT_SE0 Bidirectional Mode

Name

Direction

Signal Description

• Transmit enable, active low

USB_TXOE_B

USB_DAT_VP

Out

In

• TX data when USB_TXOE_B is low

• Differential RX data when USB_TXOE_B is high

USB_SE0_VM

Out

In

• SE0 drive when USB_TXOE_B is low

• SE0 RX indicator when USB_TXOE_B is high

USB_DAT_VP

USB_SE0_VM

Figure 64. USB Transmit Waveform in DAT_SE0 Bidirectional Mode

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Figure 65. USB Receive Waveform in DAT_SE0 Bidirectional Mode

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

102

Freescale Semiconductor

Electrical Characteristics

Table 52. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode

Conditions/

Reference Signal

Parameter

Signal Name

Direction

Min

Max

Unit

TX Rise/Fall Time

TX Duty Cycle

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

Out

In

—

5.0

ns

%

50 pF

—

5.0

50 pF

49.0

—

51.0

8.0

—

USB_DAT_VP

USB_SE0_VM

ns

USB_TXOE_B

Enable Delay

Disable Delay

USB_DAT_VP

USB_SE0_VM

In

—

10.0

ns

USB_TXOE_B

RX Rise/Fall Time

USB_DAT_VP

USB_SE0_VM

In

—

3.0

ns

35 pF

4.3.14.2 DAT_SE0 Unidirectional Mode

Table 53. Signal Definitions—DAT_SE0 Unidirectional Mode

Name

Direction

Signal Description

Transmit enable, active low

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

Out

In

TX data when USB_TXOE_B is low.

SE0 drive when USB_TXOE_B is low.

Buffered data on DP when USB_TXOE_B is high.

Buffered data on DM when USB_TXOE_B is high.

Differential RX data when USB_TXOE_B is high.

USB_VM1

In

USB_RCV

In

USB_DAT_VP

USB_SE0_VM

Figure 66. USB Transmit Waveform in DAT_SE0 Unidirectional Mode

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

103

Electrical Characteristics

USB_DAT_VP/

USB_SE0_VM

VP, VM,

RCV

Figure 67. USB Receive Waveform in DAT_SE0 Unidirectional Mode

Table 54. OTG Port Timing Specification in DAT_SE0 Unidirectional Mode

Condition/

Reference Signal

Parameter

Signal Name

Signal Source

Min

Max

Unit

TX Rise/Fall Time

TX Duty Cycle

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

Out

In

—

5.0

ns

%

50 pF

—

5.0

50 pF

49.0

—

51.0

8.0

—

USB_DAT_VP

USB_SE0_VM

ns

USB_TXOE_B

Enable Delay

Disable Delay

USB_DAT_VP

USB_SE0_VM

In

—

10.0

ns

USB_TXOE_B

RX Rise/Fall Time

USB_VP1

USB_VM1

USB_RCV

In

—

3.0

ns

35 pF

4.3.14.3 VP_VM Bidirectional Mode

Table 55. Signal Definitions—VP_VM Bidirectional Mode

Name

Direction

Signal Description

• Transmit enable, active low

USB_TXOE_B

USB_DAT_VP

Out

Out (Tx)

In (Rx)

• TX VP data when USB_TXOE_B is low

• RX VP data when USB_TXOE_B is high

USB_SE0_VM

USB_RCV

Out (Tx)

In (Rx)

• TX VM data when USB_TXOE_B low

• RX VM data when USB_TXOE_B high

In

• Differential RX data

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

104

Freescale Semiconductor

Electrical Characteristics

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Figure 68. USB Transmit Waveform in VP_VM Bidirectional Mode

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Figure 69. USB Receive Waveform in VP_VM Bidirectional Mode

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

105

Electrical Characteristics

Table 56. OTG Port Timing Specification in VP_VM Bidirectional Mode

Condition/

Reference Signal

Parameter

Signal Name

Direction

Min

Max

Unit

TX Rise/Fall Time

TX Duty Cycle

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Out

In

—

5.0

51.0

—

ns

%

50 pF

—

50 pF

49.0

0.0

—

TX High Overlap

TX Low Overlap

ns

USB_DAT_VP

USB_TXOE_B

0.0

8.0

USB_DAT_VP

USB_SE0_VM

—

Enable Delay

Disable Delay

USB_DAT_VP

USB_SE0_VM

In

—

10.0

ns

USB_TXOE_B

RX Rise/Fall Time

RX Skew

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_RCV

In

—

3.0

ns

35 pF

Out

–4.0

–6.0

+4.0

+2.0

USB_SE0_VM

USB_DAT_VP

RX Skew

4.3.14.4 VP_VM Unidirectional Mode

Table 57. Signal Definitions—VP_VM Unidirectional Mode

Name

Direction

Signal Description

Transmit enable, active low

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

Out

In

TX VP data when USB_TXOE_B is low

TX VM data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

RX VM data when USB_TXOE_B is high

Differential RX data

USB_VM1

In

USB_RCV

In

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

106

Freescale Semiconductor

Electrical Characteristics

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Figure 70. USB Transmit Waveform in VP_VM Unidirectional Mode

USB_TXOE_B

USB_VP1

USB_VM1

UH1_RXD

Figure 71. USB Receive Waveform in VP_VM Unidirectional Mode

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

107

Electrical Characteristics

Parameter

Table 58. USB Timing Specification in VP_VM Unidirectional Mode

Conditions/

Reference Signal

Signal

Direction

Min

Max

Unit

TX Rise/Fall Time

TX Duty Cycle

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Out

In

—

5.0

51.0

—

ns

%

50 pF

—

50 pF

49.0

0.0

—

TX High Overlap

TX Low Overlap

ns

USB_DAT_VP

USB_TXOE_B

0.0

8.0

USB_DAT_VP

USB_SE0_VM

—

Enable Delay

Disable Delay

USB_DAT_VP

USB_SE0_VM

In

—

10.0

ns

USB_TXOE_B

RX Rise/Fall Time

RX Skew

USB_VP1

USB_VM1

USB_VP1

USB_RCV

In

—

3.0

ns

35 pF

Out

–4.0

–6.0

+4.0

+2.0

USB_SE0_VM

USB_DAT_VP

RX Skew

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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Freescale Semiconductor

Package Information and Pinout

5 Package Information and Pinout

The i.MX27/MX27L processor is available in a 17 mm × 17 mm, 0.65 mm pitch, 404-pin MAPBGA

package and a 19 mm × 19 mm, 0.8 mm pitch, 473-pin MAPBGA package.

5.1

Full Package Outline Drawing (17 mm × 17 mm)

Figure 72 shows the package drawings and dimensions of the production package.

Figure 72. i.MX27/MX27L 17 mm × 17 mm Full Package MAPBGA: Mechanical Drawing

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

109

Package Information and Pinout

5.2

Pin Assignments (17 mm × 17 mm)

Table 59 on page 111 shows the i.MX27 full 17 × 17 mm package MAPBGA pin assignments.

Table 60 on page 116 identifies the pin assignments for the ball grid array (BGA) for full package. The

list is sorted alphabetically by the name of the contact. The connections of these pins depend solely upon

the user application, however there are a few factory test signals that are not used in a normal application.

Following is a list of these signals and how they are to be terminated for proper operation of the

i.MX27/MX27L processor:

•

CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.

OSC26M_TEST: To ensure proper operation, leave this signal as no connect.

EXT_60M: To ensure proper operation, connect this signal to ground.

EXT_266M: To ensure proper operation, connect this signal to ground.

Most of the signals shown in Table 59 are multiplexed with other signals. For ease of reference, all

of the signals at a particular pad are shown in the form of a compound signal name. Please refer to

Table 3 for complete information on the signal multiplexing schemes of these signals.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

110

Freescale Semiconductor

Package Information and Pinout

Table 60 shows the device pin list, sorted by signal identification, including pad locations for ground and

power supply voltages.

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing

Contact Name

Location

A0

Y1

T6

A1

A10

AC12

U2

A11

A12

P6

A13

U1

A14

AB9

Y11

W11

AC7

AC6

V8

A15

A16

A17

A18

A19

A2

W2

Y6

A20

A21

AB4

AC3

AB1

AA2

U6

A22

A23

A24

A25

A3

U3

A4

W1

R5

A5

A6

V2

A7

R6

A8

V1

A9

P5

ATA_DATA0_SD3_D0_PD2

ATA_DATA1_SD3_D1_PD3

ATA_DATA10_ETMTRACEPKT9_PD12

ATA_DATA11_ETMTRACEPKT8_PD13

ATA_DATA12_ETMTRACEPKT7_PD14

R23

R24

R20

W23

U23

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

116

Freescale Semiconductor

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

ATA_DATA13_ETMTRACEPKT6_PD15

ATA_DATA14_ETMTRACEPKT5_PD16

ATA_DATA15_ETMTRACEPKT4_PF23

ATA_DATA2_SD3_D2_PD4

ATA_DATA3_SD3_D3_PD5

ATA_DATA4_ETMTRACEPKT14_PD6

ATA_DATA5_ETMTRACEPKT13_PD7

ATA_DATA6_FEC_MDIO_PD8

ATA_DATA7_ETMTRACEPKT12_PD9

ATA_DATA8_ETMTRACEPKT11_PD10

ATA_DATA9_ETMTRACEPKT10_PD11

AVDD

W24

T20

Y24

P20

T24

T22

T23

P19

U24

U22

V24

U18

T19

AB17

V23

Y23

U19

Y22

AC13

AB20

AB21

AD17

G6

AVSS

BCLK

BOOT0

BOOT1

BOOT2

BOOT3

CAS_B

CLKMODE0

CLKMODE1

CLKO_PF15

CLS_PA25

CONTRAST_PA30

C2

CS0_B

AD16

AB16

Y15

W14

AD15

W15

C4

CS1_B

CS2_B

CS3_B

CS4_B_ETMTRACESYNC_PF21

CS5_B_ETMTRACECLK_PF22

CSI_D0_UART6_TXD_PB10

CSI_D1_UART6_RXD_PB11

CSI_D2_UART6_CTS_PB12

B4

E6

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

117

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

CSI_D3_UART6_RTS_PB13

A5

F6

CSI_D4_PB14

CSI_D5_PB17

A6

CSI_D6_UART5_TXD_PB18

F7

CSI_D7_UART5_RXD_PB19

B6

CSI_HSYNC_UART5_RTS_PB21

A7

CSI_MCLK_PB15

B5

CSI_PIXCLK_PB16

E7

CSI_VSYNC_UART5_CTS_PB20

G7

CSPI1_MISO_PD30

A22

C21

B21

F18

B22

C20

E22

G20

E23

D23

F20

C23

D22

T2

CSPI1_MOSI_PD31

CSPI1_RDY_PD25

CSPI1_SCLK_PD29

CSPI1_SS0_PD28

CSPI1_SS1_PD27

CSPI1_SS2_USBH2_DATA5_PD26

CSPI2_MISO_USBH2_DATA2_PD23

CSPI2_MOSI_USBH2_DATA1_PD24

CSPI2_SCLK_USBH2_DATA0_PD22

CSPI2_SS0_USBH2_DATA6_PD21

CSPI2_SS1_USBH2_DATA3_PD20

CSPI2_SS2_USBH2_DATA4_PD19

D0

D1

N6

D10

D11

D12

D13

D14

D15

D2

P1

M3

N1

M5

M1

M2

T1

D3

N5

D4

R2

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

118

Freescale Semiconductor

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

D5

D6

N3

R1

D7

N2

D8

P2

D9

M6

DQM0

DQM1

DQM2

DQM3

EB0_B

EB1_B

ECB_B

EXT_266M

EXT_60M

EXTAL26M

EXTAL32K

FPMVDD

FPMVSS

FUSEVDD

FUSEVSS

GND

AD12

W12

Y13

AD11

W16

AC17

AC16

AD18

W17

AB24

M24

M18

P15

R18

R19

A1

GND

A2

GND

A23

A24

AC1

AC2

AC23

AC24

AD1

AD2

AD23

AD24

B1

GND

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

119

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

GND

B2

B23

B24

K10

K11

K12

K13

K14

K15

L10

L11

L12

L13

L14

L15

M10

M11

M12

M13

M14

N10

N11

N12

N13

N14

N15

P10

P11

P12

P13

P14

R10

R11

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

120

Freescale Semiconductor

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

GND

R12

R13

R14

D1

GND

HSYNC_PA28

I2C_CLK_PD18

I2C_DATA_PD17

I2C2_SCL_PC6

I2C2_SDA_PC5

IOIS16_ATA_INTRQ_PF9

JTAG_CTRL

KP_COL0

B13

F12

F24

J22

U20

AC18

B14

F13

A15

E13

B15

F14

F11

A12

C12

B12

E11

A13

Y16

J2

KP_COL1

KP_COL2

KP_COL3

KP_COL4

KP_COL5

KP_ROW0

KP_ROW1

KP_ROW2

KP_ROW3

KP_ROW4

KP_ROW5

LBA_B

LD0_PA6

LD1_PA7

K6

LD10_PA16

LD11_PA17

LD12_PA18

LD13_PA19

LD14_PA20

LD15_PA21

LD16_PA22

LD17_PA23

F2

J7

H3

H5

F1

H6

E2

G5

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

121

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

LD2_PA8

J3

K5

LD3_PA9

LD4_PA10

H2

J6

LD5_PA11

LD6_PA12

G2

J5

LD7_PA13

LD8_PA14

G1

K7

LD9_PA15

LSCLK_PA5

K2

MA10

T3

MPLLVDD

T18

R15

K1

MPLLVSS

NFALE_ETMPIPESTAT0_PF4

NFCE_B_ETMTRACEPKT2_PF3

L2

NFCLE_ETMTRACEPKT0_PF1

L6

NFRB_ETMTRACEPKT3_PF0

H1

L5

NFRE_B_ETMPIPESTAT1_PF5

NFWE_B_ETMPIPESTAT2_PF6

L1

NFWP_B_ETMTRACEPKT1_PF2

J1

NVDD1

NVDD10

NVDD11

NVDD12

NVDD13

NVDD14

NVDD15

NVDD2

NVDD3

M7

N7

G11

G10

L7

M19

H18

H7

R7

T7

U7

V10

V9

V11

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

122

Freescale Semiconductor

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

NVDD3

NVDD4

V12

V13

NVDD5

V17

NVDD5

V18

NVDD6

N18

P18

NVDD6

NVDD7

L18

NVDD7

L19

NVDD8

G15

G14

D3

NVDD9

OE_ACD_PA31

OE_B

Y17

OSC26M_TEST

V19

OSC26VDD

AA23

AB23

L24

OSC26VSS

OSC32K_BYPASS

OSC32VDD

M23

N23

AD20

W20

W18

AC19

V20

OSC32VSS

PC_BVD1_ATA_DMARQ_PF12

PC_BVD2_ATA_DMACK_PF11

PC_CD1_B_ATA_DIOR_PF20

PC_CD2_B_ATA_DIOW_PF19

PC_POE_ATA_BUFFER_EN_PF7

PC_PWRON_ATA_DA2_PF16

PC_READY_ATA_CS0_PF17

PC_RST_ATA_RESET_B_PF10

PC_RW_B_ATA_IORDY_PF8

PC_VS1_ATA_DA1_PF14

PC_VS2_ATA_DA0_PF13

PC_WAIT_B_ATA_CS1_PF18

POR_B

Y19

AD19

AC21

AD21

AC20

W19

Y18

AD22

N22

N19

POWER_CUT

POWER_ON_RESET

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

123

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

PS_PA26

D2

C13

G12

G13

G16

P7

PWMO_PE5

QVDD

V14

V15

V16

AB13

AC22

AA22

E1

QVDD

RAS_B

RESET_IN_B

RESET_OUT_B_PE17

REV_PA24

RTCK_OWIRE_PE16

A19

K19

K18

AC15

AB12

AC11

G17

A21

A20

E17

B20

E18

AB8

AD7

Y9

RTCVDD

RTCVSS

RW_B

SD0

SD1

SD1_CLK_CSPI3_SCLK_PE23

SD1_CMD_CSPI3_MOSI_PE22

SD1_D0_CSPI3_MISO_PE18

SD1_D1_PE19

SD1_D2_PE20

SD1_D3_CSPI3_SS_PE21

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

W9

AD6

Y8

AD5

AC5

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

124

Freescale Semiconductor

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

SD18

Y7

AD4

Y12

A4

SD19

SD2

SD2_CLK_MSHC_SCLK_PB9

SD2_CMD_MSHC_BS_PB8

C5

SD2_D0_MSHC_DATA0_PB4

C1

SD2_D1_MSHC_DATA1_PB5

E3

SD2_D2_MSHC_DATA2_PB6

C8

SD2_D3_MSHC_DATA3_PB7

A3

SD20

AC4

AB5

AD3

W5

SD21

SD22

SD23

SD24

AB2

W7

SD25

SD26

V5

SD27

AA3

V6

SD28

SD29

V7

SD3

AD10

P24

P23

AA1

U5

SD3_CLK_ETMTRACEPKT15_PD1

SD3_CMD_PD0

SD30

SD31

SD4

AC10

AC9

W10

AD8

Y10

AC8

Y2

SD5

SD6

SD7

SD8

SD9

SDBA0

SDBA1

SDCKE0

T5

AC14

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

125

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

SDCKE1

SDCLK

Y14

AD13

AD14

AD9

W8

W6

Y3

SDCLK_B

SDQS0

SDQS1

SDQS2

SDQS3

SDWE_B

W13

B3

SPL_SPR_PA27

SSI1_CLK_PC23

SSI1_FS_PC20

SSI1_RXDAT_PC21

SSI1_TXDAT_PC22

SSI2_CLK_GPT4_TIN_PC27

SSI2_FS_GPT5_TOUT_PC24

SSI2_RXDAT_GPT5_TIN_PC25

SSI2_TXDAT_GPT4_TOUT_PC26

SSI3_CLK_SLCDC2_CLK_PC31

SSI3_FS_SLCDC2_D0_PC28

SSI3_RXDAT_SLCDC2_RS_PC29

SSI3_TXDAT_SLCDC2_CS_PC30

SSI4_CLK_PC19

SSI4_FS_PC16

SSI4_RXDAT_PC17

SSI4_TXDAT_PC18

TCK

B9

F9

A9

E9

B10

G9

A10

F10

B11

E10

A11

C9

B8

F8

A8

G8

F17

B18

E16

B7

TDI

TDO

TIN_PC15

TMS

B19

E8

TOUT_PC14

TRST_B

C17

A18

UART1_CTS_PE14

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

126

Freescale Semiconductor

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

UART1_RTS_PE15

UART1_RXD_PE13

C16

F16

B17

E12

A14

E14

A16

A17

E15

F15

B16

J18

M15

H20

F23

E19

C24

H22

J20

E24

G19

F19

D24

H23

J24

K23

L20

J23

K24

J19

G18

G23

K20

UART1_TXD_PE12

UART2_CTS_KP_COL7_PE3

UART2_RTS_KP_ROW7_PE4

UART2_RXD_KP_ROW6_PE7

UART2_TXD_KP_COL6_PE6

UART3_CTS_PE10

UART3_RTS_PE11

UART3_RXD_PE9

UART3_TXD_PE8

UPLLVDD

UPLLVSS

USB_OC_B_PB24

USB_PWR_PB23

USBH1_FS_UART4_RTS_PB26

USBH1_OE_B_PB27

USBH1_RCV_PB25

USBH1_RXDM_PB30

USBH1_RXDP_UART4_RXD_PB31

USBH1_SUSP_PB22

USBH1_TXDM_UART4_TXD_PB28

USBH1_TXDP_UART4_CTS_PB29

USBH2_CLK_PA0

USBH2_DATA7_PA2

USBH2_DIR_PA1

USBH2_NXT_PA3

USBH2_STP_PA4

USBOTG_CLK_PE24

USBOTG_DATA0_PC9

USBOTG_DATA1_PC11

USBOTG_DATA2_PC10

USBOTG_DATA3_PC13

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

127

Package Information and Pinout

Table 60. i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing (continued)

Contact Name

Location

USBOTG_DATA4_PC12

USBOTG_DATA5_PC7

USBOTG_DATA6_PC8

USBOTG_DATA7_PE25

USBOTG_DIR_KP_ROW7A_PE2

USBOTG_NXT_KP_COL6A_PE0

USBOTG_STP_KP_ROW6A_PE1

VSYNC_PA29

H24

H19

G24

M22

N20

M20

L23

F5

XTAL26M

AA24

N24

XTAL32K

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

128

Freescale Semiconductor

Package Information and Pinout

5.3

Full Package Outline Drawing (19 mm × 19 mm)

Figure 73 shows the package drawings and dimensions of the production package.

Figure 73. i.MX27/MX27L 19 × 19 mm Full Package MAPBGA: Mechanical Drawing

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

129

Package Information and Pinout

5.4

Pin Assignments (19 mm × 19 mm)

Table 61 shows the i.MX27 full 19 × 19 mm package MAPBGA pin assignment.

Table 62 identifies the pin assignments for the ball grid array (BGA) for full package. The connections of

these pins depend solely upon the user application, however there are a few factory test signals that are

not used in a normal application. Following is a list of these signals and how they are to be terminated for

proper operation of the i.MX27/MX27L processor:

•

CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.

OSC26M_TEST: To ensure proper operation, leave this signal as no connect.

EXT_60M: To ensure proper operation, connect this signal to ground.

EXT_266M: To ensure proper operation, connect this signal to ground.

Most of the signals shown in Table 62 are multiplexed with other signals. For ease of reference, all

of the signals at a particular pad are shown in the form of a compound signal name. Refer to Table 3

for complete information on the signal multiplexing schemes of these signals.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

130

Freescale Semiconductor

Package Information and Pinout

Table 62 shows the device pin list, sorted by location.

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing

Contact Name

Location

A0

V2

T6

A1

A10

AB12

T1

A11

A12

R4

A13

R3

A14

AC10

AA10

AC9

AC7

AC6

Y7

A15

A16

A17

A18

A19

A2

V1

A20

AA5

AC4

V6

A21

A22

A23

AA2

Y2

A24

A25

W2

U4

A3

A4

U3

A5

U2

A6

U1

A7

T4

A8

T3

A9

T2

ATA_DATA0_SD3_D0_PD2

ATA_DATA1_SD3_D1_PD3

ATA_DATA10_ETMTRACEPKT9_PD12

ATA_DATA11_ETMTRACEPKT8_PD13

ATA_DATA12_ETMTRACEPKT7_PD14

ATA_DATA13_ETMTRACEPKT6_PD15

P20

P21

U23

U22

U21

U20

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

136

Freescale Semiconductor

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

ATA_DATA14_ETMTRACEPKT5_PD16

ATA_DATA15_ETMTRACEPKT4_PF23

ATA_DATA2_SD3_D2_PD4

ATA_DATA3_SD3_D3_PD5

ATA_DATA4_ETMTRACEPKT14_PD6

ATA_DATA5_ETMTRACEPKT13_PD7

ATA_DATA6_FEC_MDIO_PD8

ATA_DATA7_ETMTRACEPKT12_PD9

ATA_DATA8_ETMTRACEPKT11_PD10

ATA_DATA9_ETMTRACEPKT10_PD11

AVDD

V23

V22

R23

R22

R21

R20

T23

T22

T20

T21

U17

U18

AC16

V21

V20

T18

W23

AC13

AA22

Y22

AC17

E4

AVSS

BCLK

BOOT0

BOOT1

BOOT2

BOOT3

CAS_B

CLKMODE0

CLKMODE1

CLKO_PF15

CLS_PA25

CONTRAST_PA30

C2

CS0_B

Y15

AA15

AB14

AC14

Y14

V14

C5

CS1_B

CS2_B

CS3_B

CS4_B_ETMTRACESYNC_PF21

CS5_B_ETMTRACECLK_PF22

CSI_D0_UART6_TXD_PB10

CSI_D1_UART6_RXD_PB11

CSI_D2_UART6_CTS_PB12

CSI_D3_UART6_RTS_PB13

A4

B5

D6

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

137

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

CSI_D4_PB14

C6

A6

CSI_D5_PB17

CSI_D6_UART5_TXD_PB18

D7

CSI_D7_UART5_RXD_PB19

C7

CSI_HSYNC_UART5_RTS_PB21

B7

CSI_MCLK_PB15

A5

CSI_PIXCLK_PB16

B6

CSI_VSYNC_UART5_CTS_PB20

F8

CSPI1_MISO_PD30

A21

C20

B20

D19

B21

C21

D20

E20

D23

D22

C23

C22

D21

N7

CSPI1_MOSI_PD31

CSPI1_RDY_PD25

CSPI1_SCLK_PD29

CSPI1_SS0_PD28

CSPI1_SS1_PD27

CSPI1_SS2_USBH2_DATA5_PD26

CSPI2_MISO_USBH2_DATA2_PD23

CSPI2_MOSI_USBH2_DATA1_PD24

CSPI2_SCLK_USBH2_DATA0_PD22

CSPI2_SS0_USBH2_DATA6_PD21

CSPI2_SS1_USBH2_DATA3_PD20

CSPI2_SS2_USBH2_DATA4_PD19

D0

D1

R2

D10

D11

D12

D13

D14

D15

D2

N1

M6

M3

M4

M2

M1

R1

D3

P3

D4

P2

D5

N3

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

138

Freescale Semiconductor

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

D6

D7

P1

N6

D8

N4

D9

N2

DQM0

DQM1

DQM2

DQM3

EB0_B

EB1_B

ECB_B

EXT_266M

EXT_60M

EXTAL26M

EXTAL32K

FPMVDD

FPMVSS

FUSEVDD

FUSEVSS

GND

AA12

V12

AC12

Y11

AA16

AB16

AB15

AC18

AA17

Y23

N23

N18

N17

R18

R17

A1

GND

A2

GND

A22

A23

AB1

AB2

AB22

AB23

AC1

AC2

AC22

AC23

B1

GND

B2

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

139

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

GND

B22

B23

F6

F7

F18

G7

J9

J10

J11

J12

J13

J14

J15

K9

K10

K11

K12

K13

K14

K15

L9

L10

L11

L12

L13

L14

L15

M9

M10

M11

M12

M13

M14

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

140

Freescale Semiconductor

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

GND

M15

N9

GND

N10

N11

N12

N13

N14

N15

P9

GND

P10

P11

P12

P13

P14

P15

R9

GND

R10

R11

R12

R13

R14

R15

V7

GND

V8

GND

V18

D1

HSYNC_PA28

I2C_CLK_PD18

I2C_DATA_PD17

I2C2_SCL_PC6

I2C2_SDA_PC5

IOIS16_ATA_INTRQ_PF9

JTAG_CTRL

KP_COL0

B13

F12

G23

G22

AA20

AB17

D13

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

141

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

KP_COL1

KP_COL2

KP_COL3

KP_COL4

KP_COL5

KP_ROW0

KP_ROW1

KP_ROW2

KP_ROW3

KP_ROW4

KP_ROW5

LBA_B

F13

B14

C14

A15

B15

F11

D11

B12

A12

C12

D12

AC15

J1

LD0_PA6

LD1_PA7

J2

LD10_PA16

LD11_PA17

LD12_PA18

LD13_PA19

LD14_PA20

LD15_PA21

LD16_PA22

LD17_PA23

LD2_PA8

G3

G4

F2

F1

F3

E1

E2

E3

J3

LD3_PA9

H1

LD4_PA10

LD5_PA11

LD6_PA12

LD7_PA13

LD8_PA14

LD9_PA15

LSCLK_PA5

MA10

J4

H2

H3

G2

G1

H4

K4

P6

MPLLVDD

V17

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

142

Freescale Semiconductor

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

MPLLVSS

T17

P4

NC_P4_1

NFALE_ETMPIPESTAT0_PF4

L2

NFCE_B_ETMTRACEPKT2_PF3

K3

NFCLE_ETMTRACEPKT0_PF1

L4

NFRB_ETMTRACEPKT3_PF0

K2

NFRE_B_ETMPIPESTAT1_PF5

L3

NFWE_B_ETMPIPESTAT2_PF6

L1

NFWP_B_ETMTRACEPKT1_PF2

NVDD1

K1

K6

NVDD1

K7

NVDD1

L6

NVDD1

L7

NVDD10

NVDD11

NVDD12

NVDD13

NVDD14

NVDD15

NVDD2

G11

G12

G8

G9

G10

J6

J7

L18

H18

J17

G6

H6

P7

NVDD2

R6

R7

T7

NVDD2

U7

U8

U9

U11

NVDD2

NVDD3

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

143

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

NVDD3

NVDD4

U12

U14

U15

U16

V15

NVDD4

NVDD5

V16

NVDD6

P17

NVDD6

P18

NVDD7

J18

NVDD7

K18

NVDD8

G15

G16

G13

G14

C3

NVDD8

NVDD9

OE_ACD_PA31

OE_B

Y16

OSC26M_TEST

OSC26VDD

W20

W22

W21

M21

N21

N22

AA19

AB20

AB18

Y17

OSC26VSS

OSC32K_BYPASS

OSC32VDD

OSC32VSS

PC_BVD1_ATA_DMARQ_PF12

PC_BVD2_ATA_DMACK_PF11

PC_CD1_B_ATA_DIOR_PF20

PC_CD2_B_ATA_DIOW_PF19

PC_POE_ATA_BUFFER_EN_PF7

PC_PWRON_ATA_DA2_PF16

PC_READY_ATA_CS0_PF17

PC_RST_ATA_RESET_B_PF10

PC_RW_B_ATA_IORDY_PF8

PC_VS1_ATA_DA1_PF14

PC_VS2_ATA_DA0_PF13

Y20

AC19

AB19

Y19

AB21

Y18

AC20

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

144

Freescale Semiconductor

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

PC_WAIT_B_ATA_CS1_PF18

POR_B

POWER_CUT

POWER_ON_RESET

PS_PA26

PWMO_PE5

QVDD

AA18

Y21

M23

M22

D2

A14

F17

G17

H7

QVDD

H8

QVDD

H9

QVDD

H10

H11

H12

H13

H14

H15

H16

H17

J8

QVDD

J16

K8

QVDD

K16

L8

QVDD

L16

M7

QVDD

M8

QVDD

M16

N8

QVDD

N16

P8

QVDD

P16

R8

QVDD

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

145

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

QVDD

R16

T8

QVDD

T9

QVDD

T10

T11

T12

T13

T14

T15

T16

U10

Y12

AA21

AC21

F4

QVDD

RAS_B

RESET_IN_B

RESET_OUT_B_PE17

REV_PA24

RTCK_OWIRE_PE16

A18

M18

M17

AA14

AA11

AB11

C19

A20

B18

A19

B19

D18

AB8

AA8

V9

RTCVDD

RTCVSS

RW_B

SD0

SD1

SD1_CLK_CSPI3_SCLK_PE23

SD1_CMD_CSPI3_MOSI_PE22

SD1_D0_CSPI3_MISO_PE18

SD1_D1_PE19

SD1_D2_PE20

SD1_D3_CSPI3_SS_PE21

SD10

SD11

SD12

SD13

SD14

SD15

Y8

AB7

AA7

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

146

Freescale Semiconductor

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

SD16

AA6

Y6

SD17

SD18

AC5

AB5

V11

D5

SD19

SD2

SD2_CLK_MSHC_SCLK_PB9

SD2_CMD_MSHC_BS_PB8

B4

SD2_D0_MSHC_DATA0_PB4

C1

SD2_D1_MSHC_DATA1_PB5

B3

SD2_D2_MSHC_DATA2_PB6

C4

SD2_D3_MSHC_DATA3_PB7

A3

SD20

Y5

SD21

AB4

AA4

AC3

AA3

AA1

Y4

SD22

SD23

SD24

SD25

SD26

SD27

W4

Y3

SD28

SD29

U6

SD3

AC11

P22

N20

Y1

SD3_CLK_ETMTRACEPKT15_PD1

SD3_CMD_PD0

SD30

SD31

SD4

V4

AB10

AB9

V10

AA9

AC8

Y9

SD5

SD6

SD7

SD8

SD9

SDBA0

V3

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

147

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

SDBA1

SDCKE0

W1

V13

U13

AA13

Y13

Y10

AB6

AB3

W3

AB13

D3

SDCKE1

SDCLK

SDCLK_B

SDQS0

SDQS1

SDQS2

SDQS3

SDWE_B

SPL_SPR_PA27

SSI1_CLK_PC23

SSI1_FS_PC20

SSI1_RXDAT_PC21

SSI1_TXDAT_PC22

SSI2_CLK_GPT4_TIN_PC27

SSI2_FS_GPT5_TOUT_PC24

SSI2_RXDAT_GPT5_TIN_PC25

SSI2_TXDAT_GPT4_TOUT_PC26

SSI3_CLK_SLCDC2_CLK_PC31

SSI3_FS_SLCDC2_D0_PC28

SSI3_RXDAT_SLCDC2_RS_PC29

SSI3_TXDAT_SLCDC2_CS_PC30

SSI4_CLK_PC19

SSI4_FS_PC16

SSI4_RXDAT_PC17

SSI4_TXDAT_PC18

TCK

A9

C9

D9

B9

D10

C10

B10

F10

A11

A10

B11

C11

A8

D8

B8

F9

F15

D17

D16

C8

TDI

TDO

TIN_PC15

TMS

C18

A7

TOUT_PC14

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

148

Freescale Semiconductor

Package Information and Pinout

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

TRST_B

UART1_CTS_PE14

F16

B17

C17

A17

D15

A13

C13

C15

D14

B16

C16

F14

A16

K17

L17

E22

E21

F20

F21

E23

G20

G21

G18

F22

F23

J23

UART1_RTS_PE15

UART1_RXD_PE13

UART1_TXD_PE12

UART2_CTS_KP_COL7_PE3

UART2_RTS_KP_ROW7_PE4

UART2_RXD_KP_ROW6_PE7

UART2_TXD_KP_COL6_PE6

UART3_CTS_PE10

UART3_RTS_PE11

UART3_RXD_PE9

UART3_TXD_PE8

UPLLVDD

UPLLVSS

USB_OC_B_PB24

USB_PWR_PB23

USBH1_FS_UART4_RTS_PB26

USBH1_OE_B_PB27

USBH1_RCV_PB25

USBH1_RXDM_PB30

USBH1_RXDP_UART4_RXD_PB31

USBH1_SUSP_PB22

USBH1_TXDM_UART4_TXD_PB28

USBH1_TXDP_UART4_CTS_PB29

USBH2_CLK_PA0

USBH2_DATA7_PA2

USBH2_DIR_PA1

K21

K20

K22

K23

L22

H22

J20

USBH2_NXT_PA3

USBH2_STP_PA4

USBOTG_CLK_PE24

USBOTG_DATA0_PC9

USBOTG_DATA1_PC11

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

149

Product Documentation

Table 62. i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing (continued)

Contact Name

Location

USBOTG_DATA2_PC10

USBOTG_DATA3_PC13

USBOTG_DATA4_PC12

USBOTG_DATA5_PC7

USBOTG_DATA6_PC8

USBOTG_DATA7_PE25

USBOTG_DIR_KP_ROW7A_PE2

USBOTG_NXT_KP_COL6A_PE0

USBOTG_STP_KP_ROW6A_PE1

VSYNC_PA29

H23

J22

J21

H20

H21

L20

M20

L21

L23

D4

XTAL26M

AA23

P23

XTAL32K

6 Product Documentation

This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data.

Definitions of these types are available at: http://www.freescale.com.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

150

Freescale Semiconductor

Revision History

7 Revision History

Table 63 summarizes revisions to this document since the previous release.

Table 63. Document Revision History

Rev. No.

Date

Significant Change(s)

1.8

12/2012

• In Table 3, “i.MX27/MX27L Signal Descriptions,” updated Function/Notes column for SD3_CMD

and SD3_CLK.

• In Table 11, “Current Consumption,” for parameter 4, Power Gate, updated maximum power to

216 μA.

1.7

1.6

05/2011 In Table 8, “DPLL FREQUENCY Specifications,” added the MPLL row along with a footnote.

08/2010

• Added a new section- Section 4.3.12.1, “WEIM Synchronous Mode Sample Point.”

• Updated ID WE15 in Table 50.

1.5

1.4

12/2009

5/2009

• Updated Table 1, “Ordering Information,” to include new part numbers and table footnote.

• In Table 11, “Current Consumption,” a column for Max value was added.

• In Table 59, “i.MX27 Full 17 × 17 mm Package MAPBGA Pin Assignment,” inaccurate pin list

information was corrected and the table reformatted.

• In Table 60, “i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing,” inaccurate pin list

information was corrected and the table was reformatted.

• Reformatted Table 62, “i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing.”

1.3

11/2008

• In Table 3, “i.MX27/MX27L Signal Descriptions,” switched FEC_TXD0 and FEC_TXD1 for

SD3_CMD and SD3_CLK.

• In Table 23, “CSPI Interface Timing Parameters,” updated t6’ and t13, and removed t14.

• In Table 60, “i.MX27 BGA (17 mm × 17 mm)— Contact Name Listing,” changed “RW” to “RW_B.”

• Added Table 59, “i.MX27 Full 17 × 17 mm Package MAPBGA Pin Assignment.”

• Updated Table 62, “i.MX27 BGA (19 mm × 19 mm)—Contact Name Listing.”

1.2

1.1

7/2008

Corrected part number in Section 1.3, “Ordering Information,” on p. 4. Part number previously listed

as MCIMX27FVOP4A has been corrected to read MCIMX27VOP4A.

Formatting and template work.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

151

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

How to Reach Us:

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Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for each

customer application by customer’s technical experts. Freescale does not convey any

license under its patent rights nor the rights of others. Freescale sells products pursuant

to standard terms and conditions of sale, which can be found at the following address:

freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. ARM is the registered trademark of ARM Limited.

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are the property of their respective owners.

Document Number: MCIMX27EC

Rev. 1.8

1/2013


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描述：	BONO 19X19 R2 时钟外围集成电路
文件：	总152页 (文件大小：2334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCIMX27MOP4AR2 [NXP]

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