MCIMX280CVM4B_技术文档

Document Number: IMX28CEC

Rev. 3, 07/2012

Freescale Semiconductor

Data Sheet: Technical Data

i.MX28

i.MX28 Applications

Processors for Consumer

Products

Package Information

Plastic package

Case MAPBGA-289, 14 x 14 mm, 0.8 mm pitch

Silicon Version 1.2

Ordering Information

See Table 1 on page 3 for ordering information.

Contents

1 Introduction

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Ordering Information and Functional Part Differences

3

The i.MX28 is a low-power, high-performance

applications processor optimized for the general

embedded industrial and consumer markets. The core of

the i.MX28 is Freescale's fast, power-efficient

implementation of the ARM926EJ-S™ core, with

speeds of up to 454 MHz.

1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1. Special Signal Considerations . . . . . . . . . . . . . . . 11

3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1. i.MX28 Device-Level Conditions . . . . . . . . . . . . . . 11

3.2. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 18

3.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4. I/O AC Timing and Parameters . . . . . . . . . . . . . . 23

3.5. Module Timing and Electrical Parameters . . . . . . 27

4. Package Information and Contact Assignments . . . . . . 59

4.1. Case MAPBGA-289, 14 x 14 mm, 0.8 mm Pitch . 59

4.2. Ground, Power, Sense, and Reference Contact

Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.3. Signal Contact Assignments . . . . . . . . . . . . . . . . 61

4.4. i.MX280 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.5. i.MX283 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.6. i.MX286 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.7. i.MX287 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 69

5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

The device is suitable for a wide range of applications,

including the following:

•

Human-machine interface (HMI) panels:

industrial, home

•

Industrial drive, PLC, I/O control display, factory

robotics display, graphical remote controls

•

Handheld scanners and printers

Patient-monitoring, portable medical devices

Smart energy meters, energy gateways

Media phones, media gateways

The integrated power management unit (PMU) on the

i.MX28 is composed of a triple output DC-DC switching

converter and multiple linear regulators. These provide

power sequencing for the device and its I/O peripherals

Introduction

such as memories and SD cards, as well as provide battery charging capability for Li-Ion batteries.

The i.MX28 processor includes an additional 128-Kbyte on-chip SRAM to make the device ideal for

eliminating external RAM in applications with small footprint RTOS.

The i.MX28 supports connections to various types of external memories, such as mobile DDR, DDR2 and

LV-DDR2, SLC and MLC NAND Flash.

The i.MX28 can be connected to a variety of external devices such as high-speed USB2.0 OTG, CAN,

10/100 Ethernet, and SD/SDIO/MMC.

1.1

Device Features

The following lists the features of the i.MX28:

•

ARM926EJ-S CPU running at 454 MHz:

— 16-Kbyte instruction cache and 32-Kbyte data cache

— ARM embedded trace macrocell (CoreSight™ ETM9™)

— Parallel JTAG interface

•

128 KBytes of integrated low-power on-chip SRAM

128 KBytes of integrated mask-programmable on-chip ROM

1280 bits of on-chip one-time-programmable (OCOTP) ROM

16-bit mobile DDR (mDDR) (1.8 V), DDR2 (1.8 V) and LV-DDR2 (1.5 V), up to 205 MHz DDR

clock frequency with voltage overdrive

•

Support for up to eight NAND Flash memory devices with up to 20-bit BCH ECC

Four synchronous serial ports (SSP) for SDIO/MMC/MS/SPI: SSP0, SSP1, SSP2, and SSP3. SSP0

and SSP1 can support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only

1-bit and 4-bit modes.

•

10/100-Mbps Ethernet MAC compatible with IEEE Std 802.3™:

— Single 10/100 Ethernet with GMII/RMII or Dual 10/100 Ethernet with RMII interface

— Supporting IEEE Std 1588™-compatible hardware timestamp

— Supporting 50-MHz/25-MHz clock output for external Ethernet PHY

Two 2.0B protocol-compatible Controller Area Network (CAN) interfaces

One USB2.0 OTG device/host controller and PHY

•

One USB2.0 host controller and PHY

LCD controller, up to 24-bit RGB (DOTCK) modes and 24-bit system-mode

Pixel-processing pipeline (PXP) supports full path from color-space conversion, scaling,

alpha-blending to rotation without intermediate memory access.

•

SPDIF transmitter

Dual serial audio interface (SAIF) to support full-duplex transmit and receive operations; each

SAIF supports three stereo pairs

•

Five application Universal Asynchronous Receiver-Transmitters (UARTs), up to 3.25 Mbps with

hardware flow control

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Introduction

•

One debug UART operating at up to 115 Kb/s using programmed I/O

2

Two I C master/slave interfaces, up to 400 kbps

Four 32-bit timers and a rotary decoder

Eight Pulse Width Modulators (PWMs)

Real-time clock (RTC)

GPIO with interrupt capability

Power Management Unit (PMU) supports a triple output DC-DC switching converter, multiple

linear regulators, battery charger, and detector.

•

16-channel Low-Resolution A/D Converter (LRADC). There are 16 physical channels but they can

only be mapped to 8 virtual channels at a time.

•

Single channel High Speed A/D Converter (HSADC), up to 2 Msps data rate

4/5-wire touchscreen controller

Up to 8X8 keypad matrix with button-detect circuit

Security features:

— Read-only unique ID for Digital Rights Management (DRM) algorithms

— Secure boot using 128-bit AES hardware decryption

— SHA-1 and SHA256 hashing hardware

— High assurance boot (HAB4)

•

Offered in 289-pin Ball Grid Array (BGA)

1.2

Ordering Information and Functional Part Differences

Table 1 provides the ordering information for the i.MX28.

Table 1. Ordering Information

Part Number

Projected Temperature Range (°C)

Package

MCIMX280DVM4B

MCIMX280CVM4B

MCIMX283DVM4B

MCIMX283CVM4B

MCIMX286DVM4B

MCIMX286CVM4B

MCIMX287CVM4B

–20 to +70

–40 to +85

–20 to +70

–40 to +85

–20 to +70

–40 to +85

14 x 14 mm, 0.8mm pitch, MAPBGA-289

14 x 14 mm, 0.8 mm pitch, MAPBGA-289

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

3

Introduction

Table 2 provides the functional differences between the i.MX280, i.MX283, i.MX286, and i.MX287.

Table 2. i.MX28 Functional Differences

Function

i.MX280

i.MX283

i.MX286

i.MX287

Application UART

Debug UART

CAN

x5

x1

—

x1

—

x8

—

x4

Yes

x4

—

x5

x1

x5

x1

—

x2

Ethernet

x1

x2

High-speed ADC

L2 Switch

x1

—

Yes

x8

LCD Interface

Yes

x8

1

LRADC

x8

PWM

x8

S/PDIF Tx

—

Yes

x4

Yes

x4

2

SD/SDIO/MMC

x4

Sec ur ity

SPI

Yes

x4

Yes

x4

Yes

Touch Screen

USB 2.0

Yes

OTG HS with

HS PHY x1

OTG HS with HS PHY x1

OTG HS with HS PHY x1 OTG HS with HS PHY x1

HS Host with

HS PHY x1

HS Host with HS PHY x1

HS Host with HS PHY x1 HS Host with HS PHY x1

1

There are 16 physical channels but they can only be mapped to 8 virtual channels at a time.

2

For SD/SDIO/MMC, four synchronous serial ports (SSP) are available: SSP0, SSP1, SSP2, and SSP3. SSP0 and SSP1 can

support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only 1-bit and 4-bit modes.

i.MX28 Applications Processors for Consumer Products, Rev. 3

4

Freescale Semiconductor

Introduction

1.3

Block Diagram

Figure 1 shows the simplified interface block diagram.

Figure 1. i.MX28 Simplified Interface Block Diagram

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

5

Features

2 Features

Table 3 shows the device functions.

Table 3. i.MX28 Functions

Function

BGA289

External Memory Interface (EMI)

Yes

(1.5 V LV-DDR2, 1.8 V DDR2, 1.8 V LP-DDR1)

General-Purpose Media Interface (GPMI):

• NAND data width

8-bit

• Number of external NANDs supported

4 dedicated / 8 with muxing

Pulse Width Modulator (PWM)

5 dedicated / 8 with muxing

4 dedicated / 5 with muxing

Application UART (AUART): Interfaces supported

Synchronous Serial Port (SSP): Supported through dedicated pins 3 dedicated / 4 with muxing

2

I C

1 dedicated / 2 with muxing

SPDIF

1

SAIF

2

FlexCAN

2

LCD interface

24 bits

High-speed ADC

LRADC (touchscreen, keypad...)

Ethernet MAC and switch

Universal Serial Bus (USB)

Yes

Up to 2 MACs with switch

2

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Features

Table 4 describes the digital and analog modules of the device.

Table 4. i.MX28 Digital and Analog Modules

Subsystem Brief Description

AHB to APBH System control The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for

Block

Mnemonic

Block Name

APBHDMA

Bridge with

DMA

memory-mapped I/O to the APB devices, as well a central DMA facility for

devices on this bus. The bridge provides a peripheral attachment bus running

on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous

to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.)

The DMA controller transfers read and write data to and from each peripheral

on APBH bridge.

APBXDMA

AHB to APBX System control The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for

Bridge with

DMA

memory-mapped I/O to the APB devices, as well a central DMA facility for

devices on this bus. The AHB-to-APBX bridge provides a peripheral

attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that

the APBX runs on a crystal-derived clock, as compared to APBH, which is

synchronous to HCLK.) The DMA controller transfers read and write data to

and from each peripheral on APBX bridge.

®

ARM9 or

ARM926

ARM926EJ-S ARM

CPU

The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM

real-time debug modules. It contains the 16-Kbyte L1 instruction cache,

32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.

AUART(5)

Application

UART

Connectivity

peripherals

Each of the UART modules supports the following serial data

transmit/receive protocols and configurations:

interface

• 7- or 8-bit data words, one or two stop bits, programmable parity (even,

odd, or none)

• Programmable baud rates up to 3.25 MHz. This is a higher maximum

baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard

and previous Freescale UART modules. 16-byte FIFO on Tx and 16-byte

FIFO on Rx supporting auto-baud detection

BCH

Bit-correcting Connectivity

The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder

module is capable of correcting from 2 to 20 single bit errors within a block of

data no larger than about 900 bytes (512 bytes is typical) in applications such

as protecting data and resources stored on modern NAND Flash devices.

ECC

peripherals

accelerator

BSI

Boundary

Scan Interface peripherals

Connectivity

The boundary scan interface is provided to enable board level testing.

There are five pins on the device which is used to implement the IEEE Std

1149.1™ boundary scan protocol.

CLKCTRL

Clock control Clocks

module

The clock control module, or CLKCTRL, generates the clock domains for all

components in the i.MX28 system. The crystal clock or PLL clock are the two

fundamental sources used to produce most of the clock domains. For lower

performance and reduced power consumption, the crystal clock is selected.

The PLL is selected for higher performance requirements but requires

increased power consumption. In most cases, when the PLL is used as the

source, a Phase Fractional Divider (PFD) can be programmed to reduce the

PLL clock frequency by up to a factor of 2.

DCP

Data

co-processor

Security

This module provides support for general encryption and hashing functions

typically used for security functions. Because its basic job is moving data

from memory to memory, it also incorporates a memory-copy (memcopy)

function for both debugging and as a more efficient method of copying data

between memory blocks than the DMA-based approach.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

7

Features

Table 4. i.MX28 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

DFLPT

Default

first-levelpage

table

System control The DFLPT provides a unique method of implementing the ARM MMU

first-level page table (L1PT) using a hardware-based approach.

DIGCTL

DUART

EMI

Digital control System control The digital control module includes sections for controlling the SRAM, the

and on-chip

RAM

performance monitors, high-entropy pseudo-random number seed,

free-running microseconds counter, and other chip control functions.

Debug UART Connectivity

peripherals

The Debug UART performs the following data conversions:

• Serial-to-parallel conversion on data received from a peripheral device

• Parallel-to-serial conversion on data transmitted to the peripheral device

External

memory

interface

Connectivity

peripherals

The i.MX28 supports off-chip DRAM storage through the EMI controller,

which is connected to the four internal AHB/AXI busses. The EMI supports

multiple external memory types, including:

• 1.8-V Mobile DDR1 (LP-DDR1)

• Standard 1.8-V DDR2

• Low Voltage 1.5-V DDR2 (LV-DDR2)

ENET

Ethernet MAC Connectivity

Ethernet MAC controller connected to the uDMA (unified DMA). Supports

10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also

supports RMII or MII connectivity.

Controller

peripherals

FlexCAN(2)

Controller

area network peripherals

module

Connectivity

The Controller Area Network (CAN) protocol is a message based protocol

used for serial data. It was designed specifically for automotive but is also

used in industrial control and medical applications. The serial data bus runs

at 1 Mbps.

GPMI

General-pur- Connectivity

The General-Purpose Media Interface (GPMI) controller is a flexible NAND

Flash controller with 8-bit data width, up to 50-MBps I/O speed and individual

chip select and DMA channels for up to 8 NAND devices. It also provides a

interface to 20-bit BCH for ECC.

pose media

interface

peripherals

HSADC

High-speed

ADC

Connectivity

peripherals

The high-speed ADC block is designed to sample an analog input with 12-bit

resolution and a sample rate of up to 2 Msps. The output of the HSADC block

can be moved to the external memory through APBH-DMA. A typical user

case of the HSADC is to work with the PWM block to drive an external linear

image scanner sensor.

2

I C(2)

I C module

Connectivity

peripherals

The I C is a standard two-wire serial interface used to connect the chip with

2

peripherals or host controllers. The I C operates up to 400 kbps in either I C

2

master or I C slave mode. Each I C has a dedicated DMA channel and can

also controlled by CPU in PIO or PIO queue modes. It supports both 7-bit and

10-bit device address in master mode, and has programmable 7-bit address

in slave mode.

ICOLL

Interrupt

Collector

System control The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. The interrupt

collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or

IRQ line of the ARM9 CPU.

L2 Switch

3-Port L2

Switch

Network Control Programmable 3-Port Ethernet Switch with QOS

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Features

Table 4. i.MX28 Digital and Analog Modules (continued)

Block Name Subsystem Brief Description

Block

Mnemonic

LCDIF

LCD Interface Multimedia

peripherals

The LCDIF provides display data for external LCD panels from simple

text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF

supports all of these different interfaces by providing fully programmable

functionality and sharing register space, FIFOs, and ALU resources at the

same time. The LCDIF supports RGB (DOTCLK) modes as well as system

mode including both VSYNC and WSYNC modes.

LRADC

Lowresolution Connectivity

ADC module peripherals

The sixteen-channel 12-bit low-resolution ADC (LRADC) block is used for

voltage measurement. Channels 0 – 6 measure the voltage on the seven

application-dependent LRADC pins. The auxiliary channels can be used for

a variety of uses, including a resistor-divider-based wired remote control,

external temperature sensing, touch-screen, and other measurement

functions.

OCOTP

Controller

On-chip OTP Security

controller

The on-chip one-time-programmable (OCOTP) ROM serves the functions of

hardware and software capability bits, Freescale operations and unique-ID,

the customer-programmable cryptography key, and storage of various ROM

configuration bits.

PINCTRL

PMU

Pin control

and GPIO

System control Used for general purpose input/output to external ICs. Each GPIO bank

peripherals

supports 32 bits of I/O.

Power

The i.MX28 integrates a comprehensive power supply subsystem, including

the following features:

management management

Unit (DC-DC) system

• One integrated DC-DC converter that supports Li-Ion battery.

• Four linear regulators directly power the supply rails from 5-V.

• Linear battery charger for Li-Ion cells.

• Battery voltage and brownout detection monitoring for VDDD, VDDA,

VDDIO, VDD4P2 and 5-V supplies.

• Integrated current limiter from 5-V power source.

• Reset controller.

• System monitors for temperature and speed.

• Generates USB-Host 5-V from Li-Ion battery (using PWM).

• Support for on-the-fly transitioning between 5-V and battery power.

• VDD4P2, a nominal 4.2-V supply, is available when the i.MX28 is

connected to a 5-V source and allows the DCDC to run from a 5-V source

with a depleted battery.

• The 4.2-V regulated output also allows for programmable current limits:

–Battery Charge current + DCDC input current < the 5-V current limit

–DCDC input current (which ultimately provides current to the on-chip

and off-chip loads) as the priority and battery charge current is

automatically reduced if the 5-V current limit is reached

PWM(8)

Pulse width

modulation

Connectivity

peripherals

There are eight PWM output controllers that can be used in place of GPIO

pins. Applications include HSADC driving signals and LED & backlight

brightness control. Independent output control of each phase allows 0, 1, or

high-impedance to be independently selected for the active and inactive

phases. Individual outputs can be run in lock step with guaranteed

non-overlapping portions for differential drive applications.

PXP

Pixel Pipeline Multimedia

The pixel pipeline (PXP) is used to perform alpha blending of graphic or video

buffers with graphics data before sending to an LCD display. The PXP also

supports image rotation for hand-held devices that require both portrait and

landscape image support.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

9

Features

Table 4. i.MX28 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Clocks

Brief Description

RTC

Real-time

clock, alarm,

watchdog

The real-time clock (RTC) and alarm share a one-second pulse time domain.

The watchdog reset and millisecond counter run on a one-millisecond time

domain. The RTC, alarm, and persistent bits reside in a special power

domain (crystal domain) that remains powered up even when the rest of the

chip is in its powered-down state.

SAIF(2)

Serial audio

interface

Connectivity

peripherals

SAIF provides a half-duplex serial port for communication with a variety of

serial devices, including industry-standard codecs and DSPs. It supports a

continuous range of sample rates from 8 kHz–192 kHz using a

high-resolution fractional divider driven by the PLL. Samples are transferred

to/from the FIFO through the APBX DMA interface, a FIFO service interrupt,

or software polling.

SPDIF

SSP(4)

SPDIF

Connectivity

peripherals

The Sony-Philips Digital Interface Format (SPDIF) transmitter module

transmits data according to the SPDIF digital audio interface standard

(IEC-60958).

Synchronous Connectivity

serial port

The synchronous serial port is a flexible interface for inter-IC and removable

media control and communication. The SSP supports master operation of

SPI, Texas Instruments SSI; 1-bit, 4-bit, and 8-bit SD/SDIO/MMC and 1-bit

and 4-bit MS modes.

peripherals

The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI

master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP

also supports slave operation for the SPI and SSI modes. The SSP has a

dedicated DMA channel in the bridge and can also be controlled directly by

the CPU through PIO registers. Each of the four SSP modules is

independent of the other and can have separate SSPCLK frequencies.

TIMROT

Timers and

Rotary

Decoder

Timer

peripherals

This module implements four timers and a rotary decoder. The timers and

decoder can take their inputs from any of the pins defined for PWM, rotary

encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM

pins can be inputs or outputs, depending on the application.

USBOTG

USBHOST

High-speed

USB

on-the-go

Connectivity

peripherals

The USB module provides high-performance USB On-The-Go (OTG) and

host functionality (up to 480 Mbps), compliant with the USB 2.0 specification

and the OTG supplement. The module has DMA capabilities for handling

data transfer between internal buffers and system memory.

When the OTG controller works in device mode, it can only work in FS or HS

mode. Two USB2.0 PHYs are also integrated (one for the OTG port, another

for the host port.)

USBPHY

Integrated

USB PHY

Connectivity

peripherals

The integrated USB 2.0 PHY macrocells are capable of connecting to USB

host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed

(FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps.

The integrated PHYs provide a standard UTM interface. The USB_DP and

USB_DN pins connect directly to a USB connector.

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Electrical Characteristics

2.1

Special Signal Considerations

Special signal considerations are listed in Table 5. The package contact assignment is found in Section 4,

“Package Information and Contact Assignments.” Signal descriptions are provided in the reference

manual.

Table 5. Signal Considerations

Signal

Descriptions

PSWITCH

The pin is used for chip power on or recovery. VDDIO can be applied to PSWITCH through a 10 kΩ

resistor. This is necessary in order to enter the chip’s firmware recovery. The on-chip circuitry

prevents the actual voltage on the pin from exceeding acceptable levels.

VDDXTAL

BATTERY

This pin is an output of i.MX28. Should be coupled to ground with a 0.1 uF capacitor. User should

not supply external power to this pin.

This pin should be connected to the battery with minimal resistance. It provides charging current to

the battery.

See the “Power Supply” section of the reference manual for details.

DCDC_BATTERY

This pin is an input of i.MX28 that provides supply to the DCDC converter. It should be connected

to the battery with minimal resistance. See the “Power Supply” section of the reference manual for

details.

XTALI

XTALO

These analog pins are connected to an external 24 MHz crystal circuit. This crystal provides the

clock source for on-chip PLLs.

RTC_XTALO

RTC_XTALI

These analog pins are connected to an external 32.768/32.0 kHz crystal circuit. This crystal

provides clock source to the on-chip real-time counter circuits.

RESETN

This pin resets the chip if it is low. This pin is pulled up to VDDIO33 with an internal 10 kΩ resistor.

No external pull up resistors are needed.

DEBUG

This pin is used for JTAG interface.

DEBUG=0: JTAG interface works for boundary scan.

DEBUG=1: JTAG interface works for ARM debugging.

TESTMODE

For Freescale factory use only. Must be externally connected to GND for normal operation.

3 Electrical Characteristics

This section provides the device-level and module-level electrical characteristics for the i.MX28.

3.1

i.MX28 Device-Level Conditions

This section provides the device-level electrical characteristics for the IC.

3.1.1

DC Absolute Maximum Ratings

Table 6 provides the DC absolute maximum operating conditions.

CAUTION

•

Stresses beyond those listed under Table 6 may cause permanent

damage to the device.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

11

Electrical Characteristics

•

Exposure to absolute-maximum-rated conditions for extended periods

may affect device reliability.

Table 6 gives stress ratings only—functional operation of the device is

not implied beyond the conditions indicated in Table 8.

Table 6. DC Absolute Maximum Ratings

Parameter

Symbol

BATT, V

Min.

Max.

Unit

Battery Pin

–0.3

4.242

7.00

V

DD4P2V

5-Volt Source Pin - transient, t<30ms, duty cycle <0.05%

5 Volt Source Pin - static

V

DD5V

6.00

Analog Supply Voltage

V

2.10

DDA

DDD

DDIO

Digital Core Supply Voltage

Non-EMI Digital I/O Supply

V

1.575

V

3.63

EMI Digital I/O Supply

V

3.63

DDIO.EMI

1

DC-DC Converter

DCDC_BATT

BATT

Input Voltage on Any Digital I/O Pin Relative to Ground

—

VDDIO+0.3

3.63

2

Input Voltage on USB_DP and USB_DN Pins Relative to Ground

Analog I/O absolute maximum ratings (exceptions: XTALI, XTALO,

RTC_XTALI, RTC_XTALO)

VDDIO+0.3

Storage Temperature

—

–40

125

°C

1

Application should include a Schottky diode between BATT and VDD4P2.

2

USB_DN and USB_DP can tolerate 5V for up to 24 hours. Note that while 5V is applied to USB_DN or USB_DP, LRADC

readings can be corrupted.

Table 7 shows the electrostatic discharge immunity.

Table 7. Electrostatic Discharge Immunity

289-Pin BGA Package

Tested Level

1

Human Body Model (HBM)

2 kV

1

Charge Device Model (CDM)

500 V

1

HBM and CDM pass ESD testing per AEC-Q100.

i.MX28 Applications Processors for Consumer Products, Rev. 3

12

Freescale Semiconductor

Electrical Characteristics

3.1.2

DC Operating Conditions

Table 8 provides the DC recommended operating conditions.

Table 8. Recommended Power Supply Operating Conditions

Parameter

Analog Core Supply Voltage

Symbol

Min

Typ

Max

Unit

V

1.62

1.35

—

2.10

1.55

V

DDA

Digital Core Supply Voltage

Specification dependent on frequency.

V

DDD

1, 2

Digital Supply Voltages:

• VDDIO33/VDDIO33_EMI

• VDDIO18

V

/V

V

DDIO33 DDIO33_EMI DDI

O18

3.0

1.7

—

3.6

1.9

EMI Digital I/O Supply Voltage:

• DDR2/mDDR

• LVDDR2

V

/V

DDIO.EMI DDIO_EMIQ

1.7

1.425

1.8

1.5

1.9

1.625

3

Battery / DCDC Input Voltage—BATT, DCDC_BATT

BATT

DCDC_BATT

3.10

—

4.242

V

VDD5V Supply Voltage

—

4.75

5.00

5.25

4

Offstate Current:

• 32-kHz RTC off, BATT = 4.2 V

• 32-kHz RTC on, BATT = 4.2 V

—

21

23

47

51

µA

1

For optimum USB jitter performance, V

= 1.35 V or greater.

DDD

2

3

V

supply minimum voltage includes 75 mV guardband.

DDD

Tested with only the i.MX28 processor loading the MX28 PMU output rails during start up. With external loadings (for example,

one DDR2 device and SD Card/NAND Flash), MX28 PMU was tested at BATT/DCDC_BATT > 3.30 V.

4

When the real-time clock is enabled, the chip consumes additional current in the OFF state to keep the crystal oscillator and

the real-time clock running.

Table 9 provides the DC operating temperature conditions.

Table 9. Operating Temperature Conditions

1, 2, 3

Parameter

Symbol

Min

Typ

Max

Unit

Commercial Ambient Operating Temperature Range

Commercial Junction Temperature Range

Industrial Ambient Operating Temperature Range

Industrial Junction Temperature Range

T

–20

–40

—

70

85

°C

A

T

J

T

85

A

T

105

J

1

In most portable systems designs, battery and display specifications limits the operating range to well within these

specifications. Most battery manufacturers recommend enabling battery charge only when the ambient temperature is

between 0°C and 40°C. To ensure that battery charging does not occur outside the recommended temperature range, the

system ambient temperature may be monitored by connecting a thermistor to the LRADC0 or LRADC6 pin on the i.MX28.

2

For applications powered by external 5V only, the Maximum Ambient Operating Temperature specified in Table 9 may not be

achieved. Application developers need to do the worst-case power consumption estimation, and then calculate the Total

On-chip Power Dissipation based on the equations specified in note 3 below.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

13

Electrical Characteristics

3

Maximum Ambient Operating Temperature may be limited due to on-chip power dissipation. T

≤ T - (Θ x P ) where:

J JA D

A (MAX)

T = Maximum Junction Temperature

J

Θ

D

= Package Thermal Resistance. See Section 3.2, “Thermal Characteristics.”

P = Total On-chip Power Dissipation =PVDD4P2 + PBatteryCharger + PDCDC + PLinearRegulators + PInternal. Depending

JA

on the application, some of these power dissipation terms may not apply.

PVDD4P2 = VDD4P2 On-Chip Power Dissipation = (VDD5V - VDD4P2) x IDD4P2

PBatteryCharger = Battery Charger On-Chip Power Dissipation = (VDD5V - BATT) x ICHARGE

PDCDC = DC-DC Converter On-Chip Power Dissipation = (BATT x DCDC Input Current) x (1 - efficiency)

PLinearRegulators = Linear Regulator On-Chip Power Dissipation = (VDD5V - VDDIO) x (IDDIO + IDDA + IDDD + IDD1P5) +

(VDDIO - VDDA) x (IDDA + IDDD) + (VDDA - VDDD) x IDDD + (VDDA - VDD1P5) x IDD1P5

PInternal = Internal Digital On-Chip Power Dissipation = ~VDDD x IDDD

Table 10 provides the recommended analog operating conditions.

Table 10. Recommended Analog Operating Conditions

Parameter

Min

Typ

Max

Unit

Low Resolution ADC Input Impedance (CH0 - CH5)

>1

—

MΩ

Table 11 shows the PSWITCH input characteristics. See the reference schematics for the recommended

PSWITCH button circuitry.

Table 11. PSWITCH Input Characteristics

Parameter

PSWITCH LOW LEVEL

HW_PWR_STS_PSWITCH

Min

Max

Unit

0x00

0x01

0x11

0.00

0.65

0.30

1.50

2.45

V

1

PSWITCH MID LEVEL & STARTUP

2

PSWITCH HIGH LEVEL

(1.1 * VDDXTAL) +

0.58

1

2

A MID LEVEL PSWITCH state can be generated by connecting the VDDXTAL output of the SoC to PSWITCH through a

switch.

PSWITCH acts like a high impedance input (>300 kΩ) when the voltage applied to it is less than 1.5V. However, above 1.5V

it becomes lower impedance. To simplify design, it is recommended that a 10 kΩ resistor to VDDIO be applied to PSWITCH

to set the HIGH LEVEL state (the PSWITCH input can tolerate voltages greater than 2.45 V as long as there is a 10 kΩ resistor

in series to limit the current).

Table 12 shows a test case example for Run IDD.

,

Table 12. Run IDD Test Case^{1 2}

Power Rail

Conditions

Min

Typ

Max

Unit

VDDD

1.57 V

3.62 V

2.12 V

1.92 V

—

150

31

188

34

mA

μA

VDDIO33

VDDA

1.11

1.01

0.61

1.17

1.08

2.97

VDDIO_EMI

VDDIO18

1

2

CPUCLK = 300 MHz, AHBCLK = 150 MHz

Continuous read / write to the cache memory

i.MX28 Applications Processors for Consumer Products, Rev. 3

14

Freescale Semiconductor

Electrical Characteristics

Table 13 illustrates the power supply characteristics.

Table 13. Power Supply Characteristics

Parameter

Min

Typ

Max

Unit

Linear Regulators

1

Output Voltage Accuracy (V

, V

)

–3

—

+3

—

%

DDIO DDA DDM

DDD

2, 3

V

Maximum Output Current (V

= 3.30 V, V = 4.75 V)

DD5V

270

160

225

200

mA

DDIO

DDM

DDA

DDD

DDIO

DDM

2

Maximum Output Current (V

= 1.5 V)

2, 3

= 1.8 V)

= 1.2 V)

DDA

2, 3

Maximum Output Current (V

DDD

DCDC Converters

Output Voltage Accuracy (DCDC_VDDIO, DCDC_VDDA,

DCDC_VDDD)

–3

—

+3

%

1

4, 5

DCDC_VDDD Maximum Output Current (V

= 1.55 V)

250

200

250

—

mA

DDD

4, 5

DCDC_VDDA Maximum Output Current (V

= 1.8 V)

= 3.15 V, 3.3 V < BATT

DDA

DCDC_VDDIO Maximum Output Current (V

DDIO

4, 5, 6

< 4.242 V)

VDD4P2 Regulated Output

1

VDD4P2 Output Voltage Accuracy (TARGET=4.2V)

–3

—

+3

%

VDD4P2 Output Current Limit Accuracy (VDD5V = 4.75 V,

ILIMIT=480 mA)

480

500

520

mA

7

VDD4P2 Output Current Limit Accuracy (VDD5V=4.75 V,

ILIMIT=100 mA)

100

120

140

mA

7

Battery Charger

Final Charge Voltage Accuracy (TARGET=4.2 V)

-2

—

+1

%

1

No load.

2

3

Maximum output current measured when output voltage droops 100 mV from the programmed target voltage with no load

present.

Because the internal linear regulators are cascaded, it is not possible to simultaneously operate the V

, V

, and

DDM

DDIO DDA

V

linear regulators at the maximum specified load current. For example, the V

linear regulator provides current to both

DDD

DDIO

the V

3.3 V supply rail as well as the V

and V

linear regulator inputs. Likewise, the V

linear regulator provides

DDA

DDIO

DDM

DDA

current to both the 1.8 V supply rail as well as the V

following two conditions are met:

linear regulator input. The application designer should ensure the

DDD

(V

Load Current + V

Load Current) < V

Maximum Output Current

DDIO

DDA

DDM

DDA

Load Current + V

DDD

4

5

DCDC Double FETs Enabled, Inductor Value = 15 μH.

The DCDC Converter is a triple output buck converter. The maximum output current capability of each output of the converter

is dependent on the loads on the other two outputs. For a given output, it may be possible to achieve a maximum output current

higher than that specified by ensuring the load on the other outputs is well below the maximum.

6

7

Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 mA@1.8 V.

Untuned.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

15

Electrical Characteristics

3.1.2.1

Recommended Operating Conditions for Specific Clock Targets

Table 14 through Table 17 provide the recommended operating conditions for specific clock targets.

Table 14. Recommended Operating States—289-Pin BGA Package

HW_

CLKCTRL

HW_

DIGCTRL

CPUCLK

/ clk_p

HW_

CLKCTRL

AHBCLK

/ clk_h

HW_

CLKCTRL

EMICLK

/ clk_emi

HW_

VDDD

Brown-out

(V)

CLKCTRL CLKCTRL

VDDD

(V)

Supported

DRAM

FRAC_

CPUFRC

/ PFD

ARMCACH Frequency CPU_DIV_CP

Frequency HBUS_DI Frequency

EMI_

FRAC_

E¹

(MHz)

U

(MHz)

V

(MHz)

DIV_EMI EMIFRAC

1.300

1.350

1.450

1.550

1.200

1.250

1.350

1.450

00

64

5

27

33

24

22

19

64

1

130.91

2

33

27

21

DDR2

mDDR

00

261.81

360

1

130.91

120.00

130.91

151.57

2

3

130.91

160.00

205.71

DDR2

mDDR

DDR2

mDDR

392.72

454.73

DDR2

mDDR

DDR2

mDDR

1

All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.

Table 15. Recommended Operating Conditions—CPU Clock (clk_p)

HW_DIGCTRL

ARMCACHE

HW_CLKCTRL

FRAC_CPUFRC / PFD Frequency max (MHz)

CPUCLK / clk_p

VDDD (V)

VDDD

(V)

Brown-out

1

1.350

1.450

1.550

1.250

1.350

1.450

00

18 - 35

360

392.72

454.73

1

All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.

Table 16. Recommended Operating Conditions—AHB Clock (clk_h)

HW_DIGCTRL

ARMCACHE

HW_CLKCTRL

FRAC_CPUFRC / PFD Frequency max (MHz)

AHBCLK / clk_h

VDDD (V)

VDDD

(V)

Brown-out

1

1.350

1.450

1.550

1.250

1.350

1.45

00

18 - 35

160

196

206

1

All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.

i.MX28 Applications Processors for Consumer Products, Rev. 3

16

Freescale Semiconductor

Electrical Characteristics

Table 17. Frequency vs. Voltage for EMICLK—289-Pin BGA Package

EMICLK Fmax (MHz)

VDDD (V)

VDDD

(V)

Brownout

DDR2

mDDR

1.550

1.450

1.350

1.450

1.350

1.250

205.71

196.36

205.71

196.36

3.1.3

Fusebox Supply Current Parameters

Table 18 lists the fusebox supply current parameters.

Table 18. Fusebox Supply Current Parameters

Parameter Symbol Min

Typ

Max

Unit

1

eFuse Program Current

I

21.39

—

25.05

33.54

mA

program

Current to program one eFuse bit

efuse_vddq=2.5V

2

eFuse Read Current

I

—

4.07

mA

read

Current to read an 8-bit eFuse word

vdd_fusebox = 3.3 V

1

The current I

is during program time.

program

2

is present for approximately 10 ns of the read access to the 8-bit word.

read

3.1.4

Interface Frequency Limits

Table 19 provides information for interface frequency limits.

Table 19. Interface Frequency Limits

Parameter

Min.

Typ.

Max.

Unit

JTAG: TCK Frequency of Operation

OSC24M_XTAL Oscillator

—

10

—

MHz

kHz

24.000

OSC32K_XTAL Oscillator

32.768/32.0

3.1.5

Power Modes

Table 20 describes the core, clock, and module settings for the different power modes of the processor.

Table 20. Power Mode Settings

Core/Clock/Module

ARM Core

Offstate

Standby

Run

Off

On

USB0 PLL (System PLL)

OSC24M

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

17

Electrical Characteristics

Table 20. Power Mode Settings (continued)

Core/Clock/Module

Offstate

Standby

Run

OSC32K

DCDC

On

Off

On

Off

On

RTC

On

Other Modules

On/Off

3.1.6

Supply Power-Up/Power-Down Requirements

There is no special power-up sequence. After applying 5 V or battery in any order, the rest of the power

supplies are internally generated and automatically come up in a safe way.

There is no special power-down sequence. 5 V or the battery can be removed at any time.

3.1.7

Reset Timing

Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing

requirement on external pins.

The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting

RESETN.

If the reset occurs while the device is only powered by the battery, then the reset kills all of the power

supplies and the system reboots on the assertion of PSWITCH. If auto-restart is set up ahead of time, the

system reboots immediately.

If the chip is powered by 5 V, then the reset serves to reset the digital sections of the chip. If the DCDC is

operating at the time of the reset, then power switches back to the default linear regulators powered by 5 V.

RESETN

At least 100ms

Figure 2. RESETN Timing

3.2

Thermal Characteristics

The thermal resistance characteristics for the device are given in Table 21. These values are measured

under the following conditions:

•

Two layer Substrate

Substrate solder mask thickness: 0.025 mm

Substrate metal thicknesses: 0.016 mm

Substrate core thickness: 0.160 mm

i.MX28 Applications Processors for Consumer Products, Rev. 3

18

Freescale Semiconductor

Electrical Characteristics

•

Core via I.D: 0.068 mm, Core via plating 0.016 mm

Flag: trace style with ground balls under the die connected to the flag

Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K

Mold Compound: generic mold compound, k = 0.9 W/m K

Table 21. Thermal Resistance Data

Rating

Value

62

Unit

°C/W

1

Junction to ambient natural convection

Single layer board

(1s)

R

θ

JA

1

Junction to ambient natural convection

Four layer board (2s2p)

36

53

33

°C/W

JA

1

Junction to ambient (@200 ft/min)

Single layer board

(1s)

R

JMA

θ

1

Junction to ambient (@200 ft/min)

Four layer board

(2s2p)

R

2

Junction to boards

R

24

15

3

°C/W

JB

θ

3

Junction to case (top)

R

JCtop

θ

4

Junction to package top

Natural Convection

Ψ

JT

1

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-2 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

2

3

4

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification

for the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

3.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

DDR I/O: Mobile DDR (LPDDR1), standard 1.8 V DDR2, and low-voltage 1.5 V DDR2

(LVDDR2)

General purpose I/O (GPIO)

3.3.1

DDR I/O DC Parameters

Table 22 shows the EMI digital pin DC characteristics.

NOTE

The current values and the I-V curves of the I/O DC characteristics are

estimated based on an overly conservative device model. They are updated

upon the measurement results of the first silicon.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

19

Electrical Characteristics

Parameter

Table 22. EMI Digital Pin DC Characteristics

Symbol

Min.

Max.

Unit

Input voltage high (dc)

Input voltage low (dc)

Output voltage high (dc)

Output voltage low (dc)

VIH

VIL

VREF + 0.125

VDDIO_EMI + 0.3

V

0.3

VREF – 0.125

V

VOH

0.8 * VDDIO_EMI

—

V

VOL

-

0.2 * VDDIO_EMI

V

1

Output source current (dc)

LVDDR2 Mode

IOH —Low

IOH—Medium

IOH—High

-6.2

-7.2

-9.7

5.7

—

mA

2

Output sink current (dc)

LVDDR2 Mode

IOL —Low

IOL—Medium

IOL—High

IOH—Low

IOH—High

IOL—Low

7.3

10.0

-5.7

-7.5

5.4

Output source current (dc)

mDDR, DDR2 Mode

Output sink current (dc)

mDDR, DDR2 Mode

IOL—High

8.8

1

IOH is the output current at which the VOH specification is met.

IOL is the output current at which the VOL specification is met.

2

Table 23 shows the ON impedance of EMI drivers for different drive strengths.

1

Table 23. ON Impedance of EMI Drivers for Different Drive Strengths

Mode

Drive

Min. (Ω)

Typ. (Ω)

Max. (Ω)

1.5

LVDDR2

Low

Medium

High

26

17

15

36

17

16

38

25

20

53

27

19

58

36

27

78

42

28

1.8

Low

DDR2/mDDR

Medium

High

1

ON impedance of the EMI drivers are guaranteed by design and are not tested during production.

i.MX28 Applications Processors for Consumer Products, Rev. 3

20

Freescale Semiconductor

Electrical Characteristics

Table 24 shows the external devices supported by the EMI.

Table 24. External Devices Supported by the EMI

1, 2

DRAM Device

Max Load

Pad Voltage

DDR2

mDDR

15 pF

1.8 V

1.5 V

LVDDR2

1

2

Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading.

Setting is for worst case. Freescale’s EMI interface uses less powerful drivers than those typically used in mDDR devices. A

possible transmission-line effect on the PC board must be suppressed by minimizing the trace length combined with

Freescale’s slower edge-rate drivers. The i.MX28 provides up to 16 mA programmable drive strength. However, the 16-mA

mode is an experimental mode. With the 16-mA mode, the EMI function may be impaired by Simultaneous Switching Output

(SSO) noise. In general, the stronger the driver mode, the noisier the on-chip power supply. Freescale recommends not using

a stronger driver mode than is required. Because on-chip power and ground noise is proportional to the inductance of its return

path, users should make their best effort to reduce inductance between the EMI power and ground balls and the PC board

power and ground planes.

3.3.2

GPIO I/O DC Parameters

Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. For the

internal pull up setting of each pad, see the “Pin Control and GPIO” section of the reference manual.

Table 25 shows the digital pin DC characteristics for GPIO in 3.3-V mode. Measurements are valid for

eight pins loaded using the 4mA driver, four pins loaded using the 8mA driver, and two pins loaded using

either the 12mA or 16mA driver.

Table 25. Digital Pin DC Characteristics for GPIO in 3.3-V Mode

Parameter

Symbol

Min

Max

Unit

Input voltage high (dc)

Input voltage low (dc)

Output voltage high (dc)

Output voltage low (dc)

VIH

VIL

2

—

VDDIO

0.8

—

V

VOH

0.8 × VDDIO

—

V

VOL

0.4

—

V

1

Output source current (dc)

IOH – Low

IOH – Medium

IOH – High

IOL – Low

IOL – Medium

IOL – High

IOH – Low

IOH – High

IOL – Low

IOL – High

-5.0

mA

gpio

-9.5

—

-11.4

3.8

—

Output sink current (dc)

gpio

—

7.7

—

9.0

—

Output source current (dc)

gpio_clk

-9.2

—

-15.2

7.6

—

Output sink current (dc)

gpio_clk

—

12.0

—

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

21

Electrical Characteristics

Table 25. Digital Pin DC Characteristics for GPIO in 3.3-V Mode (continued)

Parameter

Symbol

Min

Max

Unit

2

10-K pull-up resistance

47-K pull-up resistance

Rpu10k

Rpu47k

8

12

56

kΩ

39

1

The conditions of the current measurements for all different drives are as follows:

IOL: at 0.4 V

IOH: at VDDIO * 0.8 V

Maximum corner for 3.3 V mode: 3.6 V, -40°C, fast process.

Minimum corner for 3.3 V mode: 3.0 V, 105°C, slow process.

8 gpio pins (LCD_D0-D7) and 2 gpio_clk pins (LCD_DOTCLK and LCD_WR_RWN) simultaneously loaded.

2

See the i.MX28 reference manual for detailed pull-up configuration of each I/O.

Table 26 shows the digital pin DC characteristics for GPIO in 1.8 V mode.

Table 26. Digital Pin DC Characteristics for GPIO in 1.8 V Mode

Symbol

Min

Max

Unit

Input voltage high (DC)

Input voltage low (DC)

Output voltage high (DC)

Output voltage low (DC)

VIH

VIL

0.7 × VDDIO18

VDDIO18

V

—

0.3 × VDDIO18

V

VOH

0.8 * VDDIO18

—

V

VOL

—

0.2 × VDDIO18

V

1

Output source current

IOH – low

IOH – medium

IOH – high

IOL – low

IOL – medium

IOL – high

IOH – low

IOH – high

-2.2

-3.5

-4.0

3.3

—

mA

(DC)

gpio

Output sink current (DC)

gpio

7.0

7.5

Output source current

(DC)

-4.2

-6.0

gpio_clk

Output sink current (DC)

gpio_clk

IOL – low

IOL – high

Rpu10k

6.8

11.5

8

—

12

56

mA

kΩ

2

10-K pull-up resistance

47-K pull-up resistance

Rpu47k

39

kΩ

1

2

The condition of the current measurements for all different drives are as follows:

Maximum corner for 1.8 V mode: 1.9 V, -40°C, Fast process.

Minimum corner for 1.8 V mode: 1.7 V, 105°C, Slow process.

1 gpio pin (GPMI_D0) and 1 gpio_clk pin (GPMI_WRN) simultaneously loaded.

See the i.MX28 reference manual for detailed pull-up configuration of each I/O.

i.MX28 Applications Processors for Consumer Products, Rev. 3

22

Freescale Semiconductor

Electrical Characteristics

3.4

I/O AC Timing and Parameters

Figure 3 and Figure 4 show the Driver Used for AC Simulation Testpoint and the Output Pad Transition

Waveform.

Driver Used for AC simulation

Testpoint

Figure 3. Driver Used for AC Simulation Testpoint

Output Pad Transition Waveform

VDDIO

80%

20%

Figure 4. Output Pad Transition Waveform

Table 27 shows the base GPIO AC timing and parameters.

Table 27. Base GPIO

Min

Parameters

Symbol

Test Voltage Test Capacitance

MaxRise/Fall

Unit

Notes

Rise/Fall

Duty cycle

Fduty

tpr

—

%

—

Output pad transition

times (maximum drive)

1.7~1.9V

3.0~3.6V

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

0.82 0.91 1.93 1.97

1.18 1.22 2.69 2.71

2.11 2.03 4.62 4.44

1.04 1.08 2.46 2.18

ns

1.42

1.5

3.29

3

2.46 2.61 5.34 5.12

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

23

Electrical Characteristics

Table 27. Base GPIO (continued)

Min

Rise/Fall

Parameters

Symbol

Test Voltage Test Capacitance

MaxRise/Fall

Unit

Notes

Output pad transition

times (medium drive)

tpr

tps

tih

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

1.7 V–1.9 V

3.0 V–3.6 V

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

—

1.02 1.08 2.34 2.38

1.51 1.5 3.34 3.28

2.91 2.62 6.24 5.67

ns

—

1.26 1.29

2.9

4

2.6

1.8

3.3

1.88

3.67

3.46 6.91 6.64

Output pad transition

times (low drive)

1.62 1.68 3.65 3.68

2.55 2.45 5.59 5.37

5.42 4.62 11.46 10.01

1.95 2.12 4.43 4.25

2.96 3.21 6.36 6.25

5.89 6.39 12.02 12.18

1.39 1.25 0.53 0.52

0.97 0.93 0.38 0.38

0.54 0.56 0.22 0.23

2.08 2.00 0.73 0.83

1.52 1.44 0.55 0.60

0.88 0.83 0.34 0.35

1.12 1.06 0.44 0.43

0.75 0.76 0.31 0.31

0.39 0.44 0.16 0.18

1.71 1.67 0.62 0.69

1.20 1.15 0.45 0.49

0.65 0.62 0.26 0.27

1.17 1.13 0.47 0.46

0.75 0.78 0.30 0.32

0.35 0.41 0.15 0.17

1.11 1.02 0.41 0.42

0.73 0.67 0.28 0.29

0.37 0.34 0.15 0.15

ns

Output pad slew rate

(maximum drive)

V/ns

mV

Output pad slew rate

(medium drive)

Output pad slew rate

(low drive)

Input pad average

hysteresis

100

75

50

—

i.MX28 Applications Processors for Consumer Products, Rev. 3

24

Freescale Semiconductor

Electrical Characteristics

Table 28 shows the F-type GPIO AC timing and parameters.

Table 28. F-type GPIO

Parameters

Symbol Test Voltage Test Capacitance Min Rise/Fall Max Rise/Fall

Unit

Notes

Duty cycle

Fduty

tpr

—

%

—

Output pad transition

times (maximum

drive)

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

0.58 0.61

0.89 0.88

1.83 1.59

0.71 0.68

1.02 1.04

1.98 2.09

0.76 0.76

1.23 1.13

2.66 2.18

1.29

1.94

3.88

1.47

2.11

3.97

1.68

2.63

5.61

1.84

2.76

5.59

2.88

4.84

1.33

1.88

3.39

1.34

1.99

3.96

1.61

2.38

4.6

ns

Output pad transition

times (medium drive)

tpr

tps

ns

0.9

0.88

1.4

1.7

1.36

2.67

5.67

2.72

4.23

8.8

2.85 3.02

1.32 1.26

2.27 1.98

Output pad transition

times (low drive)

5.23 4.13 10.95

1.46 1.55

2.46 2.62

3.05

4.92

3

5.02

5.56 5.96 10.78 11.22

Output pad slew rate

(maximum drive)

1.97 1.87

1.28 1.30

0.62 0.72

3.04 3.18

2.12 2.08

1.09 1.03

0.79

0.53

0.26

1.22

0.85

0.45

0.77

0.54

0.30

1.34

0.90

0.45

Output pad slew rate

(medium drive)

1.7~1.9V

10 pF

20 pF

1.50 1.50

0.93 1.01

0.61

0.39

0.63

0.43

—

1.7~1.9V

3.0~3.6V

50 pF

10 pF

20 pF

50 pF

0.43 0.52

2.40 2.45

1.59 1.54

0.76 0.72

0.18

0.98

0.65

0.32

0.22

1.06

0.67

0.32

—

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

25

Electrical Characteristics

Table 28. F-type GPIO (continued)

Symbol Test Voltage Test Capacitance Min Rise/Fall Max Rise/Fall

Parameters

Unit

Notes

Output pad slew rate

(low drive)

tps

1.7~1.9V

10 pF

20 pF

1.44 1.51

0.84 0.96

0.59

0.35

0.63

0.40

ns

—

1.7~1.9V

3.0~3.6V

50 pF

10 pF

20 pF

50 pF

—

0.36 0.46

1.48 1.39

0.88 0.82

0.39 0.36

100

0.16

0.59

0.37

0.17

0.19

0.60

0.36

0.16

—

3.0~3.6V

Input pad average

hysteresis

tih

1.7 V–1.9 V

3.0 V–3.6 V

75

50

mV

—

100

Table 29 shows the CLK-type GPIO AC timing and parameters.

Table 29. CLK-Type GPIO

Parameters

Symbol Test Voltage Test Capacitance

Min Rise/Fall

Max Rise/Fall

units Notes

Duty cycle

Fduty

tpr

—

%

—

Output pad transition

times (maximum

drive)

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

1.7~1.9V

3.0~3.6V

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

0.48

0.72

1.41

0.61

0.85

1.56

0.76

1.22

2.66

0.9

0.52

0.74

1.28

0.57

0.85

1.63

0.76

1.14

2.2

1.08

1.56

3.04

1.25

1.73

3.13

1.67

2.64

5.61

1.83

2.77

5.59

0.94

0.65

0.34

1.44

1.04

0.58

1.12

1.56

2.7

ns

1.12

1.63

3.08

1.62

2.41

4.62

1.72

2.69

5.72

0.91

0.65

0.38

1.61

1.10

0.58

Output pad transition

times (medium drive)

tpr

ns

0.89

1.41

3.03

2.19

1.54

0.89

3.79

2.54

1.33

1.37

2.85

2.38

1.58

0.81

3.54

2.54

1.38

Output pad slew rate

(maximum drive)

tps

ns

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Electrical Characteristics

Table 29. CLK-Type GPIO (continued)

Symbol Test Voltage Test Capacitance Min Rise/Fall

Parameters

Max Rise/Fall

units Notes

Output pad slew rate

(medium drive)

tps

1.7~1.9V

3.0~3.6V

1.7 V–1.9 V

3.0 V–3.6 V

10 pF

20 pF

50 pF

10 pF

20 pF

50 pF

—

1.50

0.93

0.43

2.40

1.58

0.76

1.50

1.00

0.52

2.43

1.53

0.71

0.61

0.39

0.18

0.98

0.65

0.32

0.63

0.42

0.22

1.05

0.67

0.31

ns

—

Input pad average

hysteresis

tih

100

75

50

mV

—

3.5

Module Timing and Electrical Parameters

ADC Electrical Specifications

3.5.1

This section describes the electrical specifications, including DC and AC information, of Low-Resolution

ADC (LRADC) and High-Speed ADC (HSADC).

3.5.1.1

LRADC Electrical Specifications

Table 30 shows the electrical specifications for the LRADC.

Table 30. LRADC Electrical Specifications

Conditions Min.

Parameter

Typ.

Max.

Unit

AC Electrical Specification

No pin/pad capacitance included

Input capacitance (C )

—

0.5

12

—

pF

bits

kHz

p

Resolution

—

1

Maximum sampling rate

(fs)

428

2

Power-up time

—

1

sample

cycles

DC Electrical Specification

DC input voltage

0

1.85

—

V

3

Current consumption

VDDA

—

10

—

μA

Touchscreen Interface

Expected plate resistance

—

200

50000

Ω

1

2

There is no sample and hold circuit in LRADC, so it is only for DC input voltage or ones with very small slope.

This comprises only the required initial dummy conversion cycle, NOT including the Analog part power-up time.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

27

Electrical Characteristics

3

This value only includes the ADC and the driver switches, but it does not take into account the current consumption in the

touchscreen plate. For example, if the plate resistance is 200 ohm, the total current consumption is about 11 mA.

3.5.1.2

HSADC Electrical Specification

Table 31 shows the electrical specifications for the HSADC

Table 31. HSADC Electrical Specification

Parameter

Conditions

Min.

Typ.

Max.

Unit

AC Electrical Specification

Input sampling

No pin/pad capacitance included

—

0.5

—

pF

capacitance (C )

s

Resolution

—

12

—

bits

Maximum sampling rate

(fs)

—

2

MHz

Power-up time

—

1

sample

cycles

DC Electrical Specification

DC input voltage

—

0.5

—

10

VDDA-0.5

—

V

Current Consumption

VDDA

μA

DNL

INL

fin = 1 kHz

fin = 1kHz

—

0.5

1.2

LSB

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Electrical Characteristics

3.5.2

DPLL Electrical Specifications

This section includes descriptions of the USB PLL electrical specifications and Ethernet PLL electrical

specifications.

3.5.2.1

USB PLL Electrical Specifications

The i.MX28 integrates a high-frequency USB PLL that provides the 480-MHz clock for the USB and other

system blocks.

Table 32 lists the USB PLL output electrical specifications.

Table 32. USB PLL Specifications

Parameter

PLL lock time

Test Conditions

Min

Typ

Max

Unit

—

10

µs

3.5.2.2

Ethernet PLL Electrical Specifications

i.MX28 provides a 50-MHz/25-MHz output clock, called the Ethernet PLL output.

Table 33 lists the Ethernet PLL output electrical specifications.

Table 33. Ethernet PLL Specifications

Parameter

Output Duty Cycle

Test Conditions

Min

Typ

Max

Unit

—

45

—

50

—

25

—

55

10

%

µs

PLL lock time

Cycle to cycle jitter

—

ps

1

Clock output frequency tolerance

+/-20

ppm

1

This Ethernet output clock tolerance specification is the contribution from the PLL only and assumes a perfect 24 MHz

clock/crystal source with 0 ppm deviation. The 24 MHz crystal frequency tolerance/deviation should be added to this number

for the total Ethernet clock output frequency tolerance.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

29

Electrical Characteristics

3.5.3

EMI AC Timing

This section includes descriptions of the electrical specifications of EMI module which interfaces

external DDR2 and Mobile-DDR1 (LP-DDR1) memory devices.

3.5.3.1

EMI Command and Address AC Timing

Figure 5 and Table 34 specify the timing related to the address and command pins that interfaces DDR2

and Mobile-DDR1 memory devices.

DDR2

DDR3

EMI_CLKN

EMI_CLK

DDR1

EMI_CE0N

EMI_RASN

EMI_CASN

EMI_WEN

DDR4

DDR5

DDR4

DDR5

DDR4

EMI_ADDR

bank

row

bank

column

Figure 5. EMI Command/Address AC Timing

Table 34. EMI Command/Address AC Timing

ID

Description

CK cycle time

Symbol

Min.

Max.

Unit

DDR1

tCK

tCH

4.86

—

ns

0.5 tCK

–0.5

0.5 tCK

+ 0.5

DDR2

DDR3

CK high level width

CK low level width

tCL

0.5 tCK

–0.5

0.5 tCK

+ 0.5

ns

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Electrical Characteristics

Table 34. EMI Command/Address AC Timing (continued)

ID

Description

Symbol

Min.

Max.

Unit

tIS

0.5 tCK – 1

0.5 tCK

+ 0.5

ns

DDR4

Address and control output setup time

tIH

0.5 tCK – 1

0.5 tCK

+ 0.5

ns

DDR5

Address and control output hold time

3.5.3.2

DDR Output AC Timing

Figure 6 and Table 35 show the DDR output AC timing defined for all DDR types: LPDDR1, standard

DDR2 (1.8 V), and LVDDR2 (1.5 V)

EMI_CLKN

EMI_CLK

DDR10

DDR11

DDR12

EMI_DQSN

EMI_DQS

DDR13

DDR14

EMI_DQ & EMI_DQM

d0 d1 d2 d3

DDR15

DDR16

Figure 6. DDR Output AC Timing

Table 35. DDR Output AC Timing

ID

Description

Symbol

Min

Max

Unit

DDR10

DDR11

Positive DQS latching edge to associated CK edge

DQS falling edge from CK rising edge—hold time

tDQSS

tDSH

–0.5

0.5

ns

0.5 tCK

–0.5

0.5 tCK

+ 0.5

DDR12

DDR13

DDR14

DQS falling edge to CK rising edge—setup time

DQS output high pulse width

tDSS

0.5 tCK

–0.5

0.5 tCK

+ 0.5

ns

tDQSH

tDQSL

0.5 tCK

–0.5

0.5 tCK

+ 0.5

DQS output low pulse width

0.5 tCK

–0.5

0.5 tCK

+ 0.5

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

31

Electrical Characteristics

Table 35. DDR Output AC Timing (continued)

Description Symbol

tDS

ID

Min

Max

Unit

DDR15

DDR16

DQ & DQM output setup time relative to DQS

DQ & DQM output hold time relative to DQS

1/4 tCK

–0.8

1/4 tCK

–0.5

ns

tDH

1/4 tCK

–0.8

1/4 tCK

–0.5

3.5.3.3

DDR2 Input AC Timing

Figure 7 and Table 36 show input AC timing for standard DDR2 and LVDDR2.

EMI_CLKN

EMI_CLK

DDR20

EMI_DQSN

EMI_DQS

DDR22

DDR21

EMI_DQ

d0 d1 d2 d3

Figure 7. DDR2 Input AC Timing

Table 36. DDR2 Input AC Timing

ID

Description

Symbol

Min

–0.5

Max

Unit

DDR20

DDR21

Positive DQS latching edge to associated CK edge

tDQSCK

tDQSQ

0.5

ns

0.25 tCK

–0.85

0.25 tCK

–0.5

DQS to DQ input skew

DDR22

DQS to DQ input hold time

tQH

0.25 tCK

+0.75

0.25 tCK

+ 1

ns

i.MX28 Applications Processors for Consumer Products, Rev. 3

32

Freescale Semiconductor

Electrical Characteristics

3.5.3.4

LPDDR1 Input AC Timing

Figure 8 and Table 37 show input AC timing for LPDDR1.

EMI_CLKN

EMI_CLK

DDR20

EMI_DQSN

EMI_DQS

DDR22

DDR21

EMI_DQ

d0 d1 d2 d3

Figure 8. LPDDR1 Input AC Timing

Table 37. DDR2 Input AC Timing

ID

Description

Symbol

Min

Max

Unit

DDR20

DDR21

Positive DQS latching edge to associated CK edge

DQS to DQ input skew

tDQSCK

tDQSQ

2

6

ns

0.25 tCK

–0.85

0.25 tCK

–0.5

DDR22

DQS to DQ input hold time

tQH

0.25 tCK

+0.75

0.25 tCK

+ 1

ns

3.5.4

Ethernet MAC Controller (ENET) Timing

The ENET is designed to support both 10- and 100-Mbps Ethernet networks compliant with IEEE 802.3.

An external transceiver interface and transceiver function are required to complete the interface to the

media. The ENET supports 10/100-Mbps MII (18 pins altogether), 10/100-Mbps RMII (10 pins, including

serial management interface), for connection to an external Ethernet transceiver. All signals are compatible

with transceivers operating at a voltage of 3.3 V.

The following subsections describe the timing for MII and RMII modes.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

33

Electrical Characteristics

3.5.4.1

ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

3.5.4.1.1

MII Receive Signal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER,

and ENET0_RX_CLK)

The receiver functions correctly up to an ENET0_RX_CLK maximum frequency of 25 MHz + 1%. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET0_RX_CLK frequency.

Figure 9 shows MII receive signal timings. Table 38 describes the timing parameters (M1–M4) shown in

the figure.

M3

ENET0_RX_CLK (input)

M4

ENET0_RXD[3:0] (inputs)

ENET0_RX_DV

ENET0_RX_ER

M1

M2

Figure 9. MII Receive Signal Timing Diagram

Table 38. MII Receive Signal Timing

1

ID

Characteristic

Min.

Max.

Unit

M1

M2

M3

M4

ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER to

ENET0_RX_CLK setup

5

—

ns

ENET0_RX_CLK to ENET0_RXD[3:0], ENET0_RX_DV,

ENET0_RX_ER hold

5

—

ns

ENET0_RX_CLK pulse width high

35%

65%

ENET0_RX_CLK

period

ENET0_RX_CLK pulse width low

ENET0_RX_CLK

period

1

ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

3.5.4.1.2

MII Transmit Signal Timing (ENET0_TXD[3:0], ENET0_TX_EN, ENET0_TX_ER,

and ENET0_TX_CLK)

The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%.

There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed

twice the ENET0_TX_CLK frequency.

i.MX28 Applications Processors for Consumer Products, Rev. 3

34

Freescale Semiconductor

Electrical Characteristics

Figure 10 shows MII transmit signal timings. Table 39 describes the timing parameters (M5–M8) shown

in the figure.

M7

ENET0_TX_CLK (input)

M5

M8

ENET0_TXD[3:0] (outputs)

ENET0_TX_EN

ENET0_TX_ER

M6

Figure 10. MII Transmit Signal Timing Diagram

Table 39. MII Transmit Signal Timing

1

ID

Characteristic

Min.

Max.

Unit

M5

M6

M7

M8

ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN,

ENET0_TX_ER invalid

5

—

ns

ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN,

ENET0_TX_ER valid

—

20

ns

ENET0_TX_CLK pulse width high

35%

65%

ENET0_TX_CLK

period

ENET0_TX_CLK pulse width low

ENET0_TX_CLK

period

1

ENET0_TX_EN, ENET0_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

3.5.4.1.3

MII Asynchronous Inputs Signal Timing (ENET0_CRS and ENET0_COL)

Figure 11 shows MII asynchronous input timings. Table 40 describes the timing parameter (M9) shown in

the figure.

ENET0_CRS, ENET0_COL

M9

Figure 11. MII Async Inputs Timing Diagram

Table 40. MII Asynchronous Inputs Signal Timing

ID

Characteristic

Min.

Max.

Unit

1

M9

ENET0_CRS to ENET0_COL minimum pulse width

1.5

—

ENET0_TX_CLK period

1

ENET0_COL has the same timing in 10-Mbit 7-wire interface mode.

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

35

Electrical Characteristics

3.5.4.1.4

MII Serial Management Channel Timing (ENET0_MDIO and ENET0_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 12 shows MII asynchronous input timings. Table 41 describes the timing parameters (M10–M15)

shown in the figure.

M14

M15

ENET0_MDC (output)

M10

ENET0_MDIO (output)

M11

ENET0_MDIO (input)

M12

M13

Figure 12. MII Serial Management Channel Timing Diagram

Table 41. MII Serial Management Channel Timing

ID

M10

Characteristic

Min.

Max.

Unit

ENET0_MDC falling edge to ENET0_MDIO output invalid (min.

propagation delay)

0

—

ns

M11

ENET0_MDC falling edge to ENET0_MDIO output valid (max.

propagation delay)

—

5

ns

M12

M13

M14

M15

ENET0_MDIO (input) to ENET0_MDC rising edge setup

ENET0_MDIO (input) to ENET0_MDC rising edge hold

ENET0_MDC pulse width high

18

0

—

ns

40%

60%

ENET0_MDC period

ENET0_MDC pulse width low

3.5.4.2

RMII Mode Timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz 50 ppm continuous reference

clock. ENET0_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include

ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER.

i.MX28 Applications Processors for Consumer Products, Rev. 3

36

Freescale Semiconductor

Electrical Characteristics

Figure 13 shows RMII mode timings. Table 42 describes the timing parameters (M16–M21) shown in the

figure.

M16

M17

ENET_CLK (input)

M18

ENET0_TXD[1:0] (output)

ENET0_TX_EN

M19

CRS_DV (input)

ENET0_RXD[1:0]

ENET0_RX_ER

M20

M21

Figure 13. RMII Mode Signal Timing Diagram

Table 42. RMII Signal Timing

ID

M16

Characteristic

Min.

Max.

Unit

ENET_CLK pulse width high

ENET_CLK pulse width low

35%

3

65%

—

ENET_CLK period

M17

M18

M19

M20

ENET_CLK period

ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN invalid

ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN valid

ns

—

12

ENET0_RXD[1:0], CRS_DV(ENET0_RX_DV), ENET0_RX_ER to

ENET_CLK setup

2

—

M21

ENET_CLK to ENET0_RXD[1:0], ENET0_RX_DV, ENET0_RX_ER hold

2

—

ns

3.5.5

Coresight ETM9 AC Interface Timing

The following timing specifications are given as a guide for a TPA that supports TRACECLK

(ETM_TCLK) frequencies up to 80 MHz. TRACECLK is the ETM_TCLK signal which can be made

functional by using some IOMUX configurations. See the reference manual for detailed information.

3.5.5.1

TRACECLK Timing

This section describes TRACECLK timings.

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37

Electrical Characteristics

Figure 14 shows TRACECLK signal timings. Table 43 describes the timing parameters shown in the

figure.

Figure 14. TRACECLK Signal Timing Diagram

Table 43. TRACECLK Signal Timing

1

ID

Characteristic

Clock and data raise time

Min.

Max.

Unit

Tr

Tf

3

—

ns

Clock and data fall time

High pulse wide

Low pulse wide

Clock period

Twh

Twl

Tcyc

2

12.5

3.5.5.2

Trace Data Signal Timing

Figure 15 shows the setup and hold requirements of the trace data pins with respect to TRACECLK.

Table 44 describes the timing parameters shown in the figure.

Figure 15. Trace Data Signal Timing Diagram

Table 44. Trace Data Signal Timing

1

ID

Characteristic

Min.

Max.

Unit

Ts

Th

Data setup

Data hold

2

—

ns

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Electrical Characteristics

3.5.6

FlexCAN AC Timing

Table 45 and Table 46 show voltage requirements for the FlexCAN transceiver Tx and Rx pins.

Table 45. Tx Pin Characteristics

Parameter

Symbol

Min.

Typ.

Max.

Unit

1

High-level output voltage

Low-level output voltage

VOH

VOL

2

—

Vcc + 0.3

V

—

0.8

—

1

Vcc = +3.3 V 5%

Table 46. Rx Pin Characteristics

Parameter

Symbol

Min.

Typ.

Max.

Unit

1

High-level input voltage

Low-level input voltage

VIH

VIL

0.8 × Vcc

—

Vcc

V

—

0.4

—

1

Vcc = +3.3 V 5%

Figure 16 through Figure 19 show the FlexCAN timing, including timing of the standby and shutdown

signals.

TXD

t

V

/2

V

/2

CC

t

OFFTXD

ONTXD

0.9V

V

DIFF

0.5V

t

OFFRXD

ONRXD

RXD

V

/2

V

/2

CC

Figure 16. FlexCAN Timing Diagram

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39

Electrical Characteristics

V

x 0.75

CC

RS

Bus Externally

Driven

1.1V

V

DIFF

t

SBRXDL

t

DRXDL

RXD

V

/2

V

/2

CC

Figure 17. Timing Diagram for FlexCAN Standby Signal

V

/2

V

/2

CC

SHDN

CC

t

ONSHDN

OFFSHDN

V

DIFF

Bus Externally

Driven

0.5V

V

/2

RXD

CC

Figure 18. Timing Diagram for FlexCAN Shutdown Signal

SHDN

RS

V

/2

CC

t

SHDNSB

0.75 x V

CC

Figure 19. Timing Diagram for FlexCAN Shutdown-to-Standby Signal

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Freescale Semiconductor

Electrical Characteristics

3.5.7

General-Purpose Media Interface (GPMI) Timing

The i.MX28 GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to

50MB/s I/O speed and individual chip select.

It supports normal timing mode, using two Flash clock cycles for one access of RE and WE. AC timings

are provided as multiplications of the clock cycle and fixed delay. Figure 20, Figure 21, Figure 22 and

Figure 23 depict the relative timing between GPMI signals at the module level for different operations

under normal mode. Table 47 describes the timing parameters (NF1–NF17) that are shown in the figures.

CLE

NF2

NF1

NF3

NF4

CEn

NF5

WE

NF6

NF7

ALE

NF8

NF9

Command

IO[7:0]

Figure 20. Command Latch Cycle Timing Diagram

CLE

CEn

NF1

NF4

NF3

NF10

NF11

NF5

NF8

WE

NF7

NF9

NF6

ALE

IO[7:0]

Address

Figure 21. Address Latch Cycle Timing Diagram

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41

Electrical Characteristics

CLE

NF1

NF3

CEn

NF10

NF11

NF5

NF8

WE

NF7

NF6

ALE

NF9

IO[7:0]

Data to NF

Figure 22. Write Data Latch Cycle Timing Diagram

CLE

CEn

NF14

NF15

NF13

RE

RB

NF17

NF16

NF12

IO[7:0]

Data from NF

Figure 23. Read Data Latch Cycle Timing Diagram

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Freescale Semiconductor

Electrical Characteristics

1

Table 47. NFC Timing Parameters

Example Timing for

Timing

^{GPMI Clock}≈ 100MHz

T = GPMI Clock Cycle

Symbol

ID

Parameter

Unit

T = 10ns

Min.

Max.

Min.

Max.

NF1

NF2

CLE setup time

tCLS

tCLH

tCS

(AS+1)*T

(DH+1)*T

(AS+1)*T

(DH+1)*T

—

10

20

10

20

—

ns

CLE hold time

NF3

CEn setup time

CE hold time

NF4

tCH

NF5

WE pulse width

ALE setup time

ALE hold time

tWP

tALS

tALH

tDS

DS*T

10

NF6

(AS+1)*T

(DH+1)*T

DS*T

—

10

20

10

—

NF7

NF8

Data setup time

Data hold time

Write cycle time

WE hold time

NF9

tDH

DH*T

NF10

NF11

NF12

NF13

NF14

NF15

NF16

NF17

tWC

tWH

tRR

(DS+DH)*T

DH*T

20

10

Ready to RE low

RE pulse width

READ cycle time

RE high hold time

Data setup on read

Data hold on read

(AS+1)*T

—

10

20

10

—

tRP

DS*T

tRC

(DS+DH)*T

tREH

tDSR

tDHR

DH*T

N/A

1

The Flash clock maximum frequency is 100 MHz.

2)GPMI’s output timing could be controlled by module’s internal register, say

HW_GPMI_TIMING0_ADDRESS_SETUP,HW_GPMI_TIMING0_DATA_SETUP,HW_GPMI_TIMING0_DATA_HOLD, this AC

timing depends on these registers’ setting. In the above table we use AS/DS/DH representing these settings each.

3)AS minimum value could be 0, while DS/DH minimum value is 1.

i.MX28 Applications Processors for Consumer Products, Rev. 3

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43

Electrical Characteristics

3.5.8

LCD AC Output Electrical Specifications

Figure 24 depicts the AC output timing for the LCD module. Table 48 lists the LCD module timing

parameters.

T

PAD_LCD_DOTCK

Falling edge capture

tSF

tSR

tHF

tHR

PAD_LCD_DOTCK

Rising edge capture

tDW

PAD_LCD_D[17:0],

PAD_LCD_VSYNC, etc

DATA/CTRL

Notes:

T = LCD interface clock period

I/O Drive Strength = 4mA

I/O Voltage = 3.3V

Cck = Capacitance load on DOTCK pad

Cd = Capacitance load on DATA/CTRL pad

Figure 24. LCD AC Output Timing Diagram

Table 48. LCD AC Output Timing Parameters

ID

Parameter

Description

tSF

tHF

tSR

tHR

tDW

Data setup for falling edge

Data hold for falling edge

Data setup for rising edge

Data hold for rising edge

Data valid window

DOTCK = T/2 – 1.97ns + 0.15*Cck – 0.19*Cd

DOTCK = T/2 + 0.29ns + 0.09*Cd – 0.10*Cck

DOTCK = T/2 – 2.09ns + 0.18*Cck – 0.19*Cd

DOTCK = T/2 + 0.40ns + 0.09*Cd – 0.10*Cck

tDW = T – 1.45ns

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Freescale Semiconductor

Electrical Characteristics

3.5.9

Inter IC (I²C) Timing

2

The I C module is designed to support up to 400-Kbps I C connection compliant with I C bus protocol.

The following section describes I C SDA and SCL signal timings.

2

Figure 25 shows the timing of the I C module. Table 49 describes the I C module timing parameters

(IC1–IC11) shown in the figure.

IC11

IC9

IC10

I2C_SDA

I2C_SCL

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

2

Figure 25. I C Module Timing Diagram

2

Table 49. I C Module Timing Parameters: 1.8 V – 3.6 V

Standard Mode

Parameter

Fast Mode

Min. Max.

ID

Unit

Min.

Max.

IC1

IC2

I2C_SCL cycle time

10

4.0

—

2.5

0.6

—

μs

ns

μs

ns

pF

Hold time (repeated) START condition

Set-up time for STOP condition

IC3

1

2

1

2

IC4

Data hold time

0

3.45

0

0.9

—

IC5

HIGH Period of I2C_SCL clock

4.0

4.7

250

4.7

—

0.6

1.3

0.6

IC6

LOW Period of the I2C_SCL clock

Set-up time for a repeated START condition

Data set-up time

—

IC7

—

3

IC8

100

1.3

—

IC9

Bus free time between a STOP and START condition

Rise time of both I2C_SDA and I2C_SCL signals

Fall time of both I2C_SDA and I2C_SCL signals

—

4

IC10

IC11

IC12

1000 20+0.1C

300

400

b

—

300

400

20+0.1C

—

Capacitive load for each bus line (C )

—

b

1

A device must internally provide a hold time of at least 300 ns for the I2C_SDA signal in order to bridge the undefined region

of the falling edge of I2C_SCL.

2

3

The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal.

2

A fast-mode I2C bus device can be used in a standard-mode I C bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal.

If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line

2

max_rise_time (ID No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I C bus

specification) before the I2C_SCL line is released.

4

C = total capacitance of one bus line in pF.

b

i.MX28 Applications Processors for Consumer Products, Rev. 3

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45

Electrical Characteristics

3.5.10 JTAG Interface Timing

Figure 26 through Figure 29 show respectively the test clock input, boundary scan, test access port, and

TRST timings for the SJC. Table 50 describes the SJC timing parameters (SJ1–SJ13) indicated in the

figures.

SJ1

SJ2

VM

SJ2

VM

TCK

(Input)

VIH

VIL

SJ3

Figure 26. Test Clock Input Timing Diagram

TCK

(Input)

VIH

VIL

SJ5

SJ4

Input Data Valid

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

Data

Outputs

SJ6

Data

Outputs

Output Data Valid

Figure 27. Boundary Scan (JTAG) Timing Diagram

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Freescale Semiconductor

Electrical Characteristics

TCK

(Input)

VIH

VIL

SJ8

SJ9

TDI

TMS

Input Data Valid

(Input)

SJ10

SJ11

SJ10

TDO

(Output)

Output Data Valid

TDO

(Output)

TDO

(Output)

Output Data Valid

Figure 28. Test Access Port Timing Diagram

TCK

(Input)

SJ13

TRST

(Input)

SJ12

Figure 29. TRST Timing Diagram

Table 50. SJC Timing Parameters

All Frequencies

ID

Parameter

Unit

Min.

Max.

SJ1

SJ2

SJ3

SJ4

SJ5

SJ6

SJ7

SJ8

SJ9

TCK cycle time

100

40

—

3

ns

1

TCK clock pulse width measured at V_M

TCK rise and fall times

Boundary scan input data set-up time

Boundary scan input data hold time

TCK low to output data valid

10

50

—

50

—

TCK low to output high impedance

TMS, TDI data set-up time

—

10

50

TMS, TDI data hold time

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

47

Electrical Characteristics

Table 50. SJC Timing Parameters (continued)

All Frequencies

ID

Parameter

Unit

Min.

Max.

SJ10 TCK low to TDO data valid

SJ11 TCK low to TDO high impedance

SJ12 TRST assert time

—

44

—

ns

100

40

SJ13 TRST set-up time to TCK low

V_{M –}mid point voltage

1

3.5.11 Pulse Width Modulator (PWM) Timing

Figure 30 depicts the timing of the PWM, and Table 51 lists the PWM timing characteristics.

The PWM can be programmed to select one of two clock signals as its source frequency: xtal clock or

hsadc clock. The selected clock signal is passed through a prescaler before being input to the counter. The

output is available at the pulse width modulator output (PWMO) external pin.

PWM also supports MATT mode. In this mode, it can be programmed to select one of two clock signals

as its source frequency, 24-MHz or 32-kHz crystal clock. For a 32-kHz source clock input, the PWM

outputs the 32-kHz clock directly to PAD.

1

2a

3b

PWM Source Clock

2b

4b

3a

4a

PWM Output

Figure 30. PWM Timing

Table 51. PWM Output Timing Parameter: Xtal clock

Ref No.

Parameter

Minimum

Maximum

Unit

1

System CLK frequency

Clock high time

Clock low time

0

21

24MHz

—

MHz

ns

2a

2b

21

—

ns

3a

Clock fall time

—

0.3

ns

3b

Clock rise time

—

0.3

ns

4a

Output delay time

Output setup time

—

15.08

—

ns

4b

15.77

ns

1

CL of PWMO = 30 pF

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Electrical Characteristics

1

2a

3b

PWM Source Clock

2b

4b

3a

4a

PWM Output

Figure 31. PWM Timing

Table 52. PWM Output Timing Parameter: HSADC clock

Ref No.

Parameter

Minimum

Maximum

Unit

1

System CLK frequency

Clock high time

Clock low time

0

6.813

24.432

—

32

—

MHz

ns

2a

2b

—

ns

3a

Clock fall time

0.3

14.93

—

ns

3b

Clock rise time

—

ns

4a

Output delay time

Output setup time

—

ns

4b

15.71

ns

1

CL of PWMO = 30 pF

2a

3b

2b

3a

PWM Source Clock

4b

4a

PWM Output

Figure 32. PWM Timing

i.MX28 Applications Processors for Consumer Products, Rev. 3

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49

Electrical Characteristics

Table 53. PWM Output Timing Parameter: MATT Mode 24 MHz Crystal Clock

Ref No.

Parameter

Minimum

Maximum

Unit

1

System CLK frequency

Clock high time

Clock low time

24

20.99

21.01

—

24

—

MHz

ns

2a

2b

—

ns

3a

Clock fall time

0.3

15.23

—

ns

3b

Clock rise time

—

ns

4a

Output delay time

Output setup time

—

ns

4b

15.92

ns

1

CL of PWMO = 30 pF

3.5.12 Serial Audio Interface (SAIF) AC Timing

The following subsections describe SAIF timing in two cases:

•

Transmitter

Receiver

3.5.12.1 SAIF Transmitter Timing

Figure 33 shows the timing for SAIF transmitter with internal clock, and Table 54 describes the timing

parameters (SS1–SS13).

SS1

SS5

SS4

SS3

SS2

BITCLK

SS6

SS7

LRCLK

SS11

SS8

SS9

SS10

SS12

SS13

SDATA0-2

Figure 33. SAIF Transmitter Timing Diagram

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Electrical Characteristics

Table 54. SAIF Transmitter Timing

Parameter

ID

Min.

Max.

Unit

SS1

SS2

BITCLK period

81.4

36.0

—

ns

BITCLK high period

BITCLK rise time

SS3

6.0

SS4

BITCLK low period

BITCLK fall time

36.0

—

SS5

6.0

SS6

BITCLK high to LRCLK high

BITCLK high to LRCLK low

LRCLK rise time

—

15.0

6.0

SS7

—

SS8

—

SS9

LRCLK fall time

—

6.0

SS10

SS11

SS12

SS13

BITCLK high to SDATA valid from high impedance

BITCLK high to SDATA high/low

—

15.0

6.0

—

BITCLK high to SDATA high impedance

SDATA rise/fall time

—

3.5.12.2 SAIF Receiver Timing

Figure 34 shows the timing for the SAIF receiver with internal clock. Table 55 describes the timing

parameters (SS1–SS17) shown in the figure.

SS1

SS3

SS5

SS4

SS2

BITCLK

SS14

SS15

LRCLK

SS16

SS17

SDATA0-2

Figure 34. SAIF Receiver Timing Diagram

i.MX28 Applications Processors for Consumer Products, Rev. 3

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51

Electrical Characteristics

Table 55. SAIF Receiver Timing with Internal Clock

ID

Parameter

Min.

Max.

Unit

SS1

SS2

BITCLK period

81.4

36.0

—

ns

BITCLK high period

BITCLK rise time

BITCLK low period

BITCLK fall time

SS3

6.0

—

SS4

36.0

—

SS5

6.0

15.0

—

SS14

SS15

SS16

SS17

BITCLK high to LRCLK high

—

BITCLK high to LRCLK low

—

SDATA setup time before BITCLK high

SDATA hold time after BITCLK high

10.0

0.0

—

3.5.13 SPDIF AC Timing

SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by

a clock that is twice the bit rate of the data signal.

The following Table 56 shows SPDIF timing parameters, including the timing of the modulating Tx clock

(spdif_clk) in SPDIF transmitter as shown in the Figure 35.

Table 56. SPDIF Timing

Timing Parameter Range

Characteristics

Symbol

Unit

Min

Max

SPDIFOUT output (Load = 30pf)

• Skew

• Transition Rising

• Transition Falling

—

ns

—

1.5

13.6

18.0

Modulating Tx clock (spdif_clk) period

spdif_clk high period

spclkp

spclkph

spclkpl

81.4

65.1

—

ns

spdif_clk low period

spclkp

spclkpl

spclkph

spdif_clk

(Input)

Figure 35. spdif_clk Timing

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Electrical Characteristics

3.5.14 Synchronous Serial Port (SSP) AC Timing

This section describes the electrical information of the SSP, which includes SD/MMC4.3 (Single Data

Rate) timing, MMC4.4 (Dual Date Rate) timing, MS (Memory Stick) timing, and SPI timing.

3.5.14.1 SD/MMC4.3 (Single Data Rate) AC Timing

Figure 36 depicts the timing of SD/MMC4.3, and Table 57 lists the SD/MMC4.3 timing characteristics.

SD4

SD2

SD1

SD5

SCK

SD3

CMD

DAT0

DAT1

SD6

output from SSP to card

......

DAT7

SD7

SD8

CMD

DAT0

DAT1

......

input from card to SSP

DAT7

Figure 36. SD/MMC4.3 Timing

Table 57. SD/MMC4.3 Interface Timing Specification

ID

Card Input Clock

Parameter

Symbols

Min

Max

Unit

1

SD1

Clock Frequency (Low Speed)

f

0

400

kHz

PP

2

Clock Frequency (SD/SDIO Full Speed/High

Speed)

25/50

MHz

PP

3

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

Clock Low Time

f

0

100

7

20/52

400

—

MHz

kHz

ns

PP

f

OD

SD2

SD3

SD4

SD5

t

WL

Clock High Time

t

7

—

ns

WH

TLH

THL

Clock Rise Time

t

—

3

ns

Clock Fall Time

3

ns

SSP Output / Card Inputs CMD, DAT (Reference to CLK)

SD6 SSP Output Delay

SSP Input / Card Outputs CMD, DAT (Reference to CLK)

t

-5

5

ns

OD

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53

Electrical Characteristics

Table 57. SD/MMC4.3 Interface Timing Specification (continued)

ID

Parameter

Symbols

Min

Max

Unit

SD7

SD8

SSP Input Setup Time

SSP Input Hold Time

t

2.5

—

ns

ISU

4

t

IH

1

2

In low speed mode, the card clock must be lower than 400 kHz, and the voltage ranges from 2.7 to 3.6 V.

In normal speed mode for the SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In high speed mode,

clock frequency can be any value between 0 ~ 50 MHz.

3

4

In normal speed mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In high speed mode, clock

frequency can be any value between 0 ~ 52MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns.

3.5.14.2 MMC4.4 (Dual Data Rate) AC Timing

Figure 37 depicts the timing of MMC4.4, and Table 58 lists the MMC4.4 timing characteristics. Be aware

that only DATA0–DATA7 are sampled on both edges of the clock (not applicable to CMD).

SD1

SCK

SD2

DAT0

DAT1

output from SSP to card

input from card to SSP

......

DAT7

SD3

SD4

DAT0

DAT1

......

DAT7

Figure 37. MMC4.4 Timing

Table 58. MMC4.4 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency (MMC Full Speed/High Speed)

SSP Output / Card Inputs CMD, DAT (Reference to CLK)

SD2 SSP Output Delay

SSP Input / Card Outputs CMD, DAT (Reference to CLK)

f

0

52

5

MHz

ns

PP

t

–5

OD

SD3

SD4

SSP Input Setup Time

SSP Input Hold Time

t

2.5

—

ns

ISU

t

IH

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Electrical Characteristics

3.5.14.3 MS (Memory Stick) AC Timing

The SSP module, which also has the function of a memory stick host controller, is compatible with the

Sony Memory Stick version 1.x and Memory Stick PRO.

Figure 38, Figure 39 and Table 40 show the timing of the Memory Stick. Table 59 and Table 60 list the

Memory Stick timing characteristics.

MS1

80%

50%

20%

80%

50%

20%

80%

50%

20%

SCK

MS2

MS3

MS5

MS4

Figure 38. MS Clock Time Waveforms

MS1

SCK

BS(CMD)

MS6

MS8

MS7

MS9

DATA

(Output)

MS10

DATA

(Input)

Figure 39. MS Serial Transfer Mode Timing Diagram

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Freescale Semiconductor

55

Electrical Characteristics

MS1

SCK

BS(CMD)

MS11

MS13

MS12

MS14

DATA

(Output)

MS15

DATA

(Input)

Figure 40. MS Parallel Transfer Mode Timing Diagram

Table 59. MS Serial Transfer Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

MS1

MS2

MS3

MS4

MS5

MS6

MS7

MS8

MS9

MS10

SCK Cycle Time

SCK High Pulse Time

SCK Low Pulse Time

SCK Rise Time

tCLKc

tCLKwh

tCLKwl

tCLKr

tCLKf

tBSsu

tBSh

50

15

—

5

—

10

—

15

ns

SCK Fall Time

BS Setup Time

BS Hold Time

5

DATA Setup Time

DATA Hold Time

DATA Input Delay Time

tDsu

5

tDh

5

tDd

—

Table 60. MS Parallel Transfer Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

MS1

MS2

MS3

MS4

SCK Cycle Time

SCK High Pulse Time

SCK Low Pulse Time

SCK Rise Time

tCLKc

tCLKwh

tCLKwl

tCLKr

25

5

—

10

ns

5

—

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Electrical Characteristics

Table 60. MS Parallel Transfer Timing Parameters (continued)

ID

Parameter

Symbol

Min

Max

Unit

MS5

MS11

MS12

MS13

MS14

MS15

SCK Fall Time

BS Setup Time

tCLKf

tBSsu

tBSh

tDsu

tDh

—

8

10

—

15

ns

BS Hold Time

1

DATA Setup Time

DATA Hold Time

DATA Input Delay Time

8

1

tDd

—

3.5.14.4 SPI AC Timing

Figure 41 depicts the master mode and slave mode timings of the SPI, and Table 61 lists the timing

parameters.

SSn

CS1

CS5

CS3

CS2

CS6

CS4

SCK

CS3

CS2

CS9

CS7

CS10

MISO

CS8

MOSI

Figure 41. SPI Interface Timing Diagram

Table 61. SPI Interface Timing Parameters

Parameter Symbol

ID

Min.

Max.

Unit

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

SCK cycle time

t

50

25

—

25

5

—

7.6

—

ns

clk

SCK high or low time

SCK rise or fall

t

SW

RISE/FALL

t

SSn pulse width

t

CSLH

SSn lead time (CS setup time)

SSn lag time (CS hold time)

MOSI setup time

t

SCS

HCS

t

Smosi

Hmosi

Smiso

Hmiso

MOSI hold time

5

MISO setup time

5

MISO hold time

5

i.MX28 Applications Processors for Consumer Products, Rev. 3

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57

Electrical Characteristics

3.5.15 UART (UARTAPP and DebugUART) AC Timing

This section describes the UART module AC timing which is applicable to both UARTAPP and

DebugUART.

3.5.15.1 UART Transmit Timing

Figure 39 shows the UART transmit timing, showing only eight data bits and one stop bit. Table 62

describes the timing parameter (UA1) shown in the figure.

Possible

UA1

Parity

Bit

Start

Bit

TXD

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 42. UART Transmit Timing Diagram

Table 62. UART Transmit Timing Parameters

ID

Parameter

Symbol

Min.

Max.

+ T

ref_clk

Unit

1

2

UA1

Transmit Bit Time

t

1/F

– T

1/F

—

Tbit

baud_rate

ref_clk

baud_rate

1

2

F

: Baud rate frequency. The maximum baud rate the UARTAPP can support is 3.25 Mbps. The maximum baud rate of

baud_rate

DebugUART is 115.2 kbps.

T

: The period of UART reference clock ref_clk (which is APBX clock = 24 MHz).

ref_clk

3.5.15.2 UART Receive Timing

Figure 43 shows the UART receive timing, showing only eight data bits and one stop bit. Table 63

describes the timing parameter (UA2) shown in the figure.

–

Possible

UA2

Parity

Bit

UA2

Bit

Start

Bit

RXD

(input)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 43. UART Receive Timing Diagram

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Package Information and Contact Assignments

Table 63. UART Receive Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Unit

1

2

UA2

Receive bit time

t

1/F

– 1/(16 1/F

)

+ 1/(16

)

baud_rate

—

Rbit

baud_rate

× F

baud_rate

× F

baud_rate

1

2

The UART receiver can tolerate 1/(16 × F

) tolerance in each bit. But accumulation tolerance in one frame must not

baud_rate

exceed 3/(16 × F

).

baud_rate

F

: Baud rate frequency. The maximum baud rate the UARTAPP can support is 3.25 Mbps. The maximum baud rate of

baud_rate

DebugUART is 115 kbps.

4 Package Information and Contact Assignments

4.1

Case MAPBGA-289, 14 x 14 mm, 0.8 mm Pitch

The following notes apply to Figure 44:

•

All dimensions are in millimeters.

Dimensioning and tolerancing per ASME Y14.5M-1994.

Maximum solder bump diameter measured parallel to datum A.

Datum A, the seating plane, is determined by the spherical crowns of the solder bumps.

Parallelism measurement excludes any effect of mark on top surface of package.

i.MX28 Applications Processors for Consumer Products, Rev. 3

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59

Package Information and Contact Assignments

Figure 44 shows the i.MX28 production package.

Figure 44. zzxzi.MX28 Production Package

4.2

Ground, Power, Sense, and Reference Contact Assignments

Table 64 shows power and ground contact assignments for the MAPBGA package.

Table 64. MAPBGA Power and Ground Contact Assignments

Contact Name

VDDA1

Contact Assignment

C13

VDDD

G12,G11,F10,F11,K12,F12,G10

G8,F9,F8,G9

VDDIO18

VDDIO33

VDDIO33_EMI

VDDIO_EMI

H8,J8,N3,G3,E6,J9,J10,A7,E16

N17

P11,R13,N13,N15,G17,M12,M10,G13,M11,L13,G15

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Package Information and Contact Assignments

Table 64. MAPBGA Power and Ground Contact Assignments (continued)

Contact Name Contact Assignment

VDDIO_EMIQ

K15,J13,R15

C12

VDDXTAL

VSS

E15,L11,A1,K10,K11,J11,M14,H11,U1,H9,H12,H3,K9,C16,L10,H16,J12,H10,B7,E5,J15,A9,N4

VSSA1

B13

VSSA2

B11

VSSIO_EMI

F16,R10,H14,M16,F14,L12,P16,U17,T14,P14,R12

4.3

Signal Contact Assignments

Table 65 lists the i.MX287 MAPBGA package signal contact assignments.

Table 65. i.MX287 MAPBGA Contact Assignments

Contact

Assignment

Contact

Assignment

Contact

Assignment

Signal Name

AUART0_CTS

AUART0_RTS

AUART0_RX

AUART0_TX

AUART1_CTS

AUART1_RTS

AUART1_RX

AUART1_TX

AUART2_CTS

AUART2_RTS

AUART2_RX

AUART2_TX

AUART3_CTS

AUART3_RTS

AUART3_RX

AUART3_TX

BATTERY

J6

J7

EMI_DQS1N

EMI_ODT0

J16

LCD_D17

R3

R17

T17

R16

R14

K13

T15

J4

LCD_D18

U4

T4

G5

H5

K5

EMI_ODT1

LCD_D19

EMI_RASN

LCD_D20

R4

U5

T5

EMI_VREF0

EMI_VREF1

EMI_WEN

LCD_D21

J5

LCD_D22

L4

LCD_D23

R5

N1

N5

M1

P4

M6

M4

L1

K4

ENET0_COL

EN ET0_CRS

ENET0_MDC

ENET0_MDIO

ENET0_RXD0

ENET0_RXD1

EN ET0_RXD2

ENET0_RXD3

LCD_DOTCLK

LCD_ENABLE

LCD_HSYNC

LCD_RD_E

LCD_RESET

LCD_RS

H6

H7

F6

J3

G4

H4

F5

H1

L6

H2

K6

J1

LCD_VSYNC

M5

L5

J2

LCD_WR_RWN K1

ENET0_RX_CLK F3

ENET0_RX_EN E4

LRADC0

LRADC1

LRADC2

LRADC3

LRADC4

LRADC5

C15

A15

B15

A17

B17

A16

C9

DCDC_BATT

DCDC_GND

DCDC_LN1

ENET0_TXD0

ENET0_TXD1

ENET0_TXD2

ENET0_TXD3

F1

F2

G1

G2

C8

D9

D13

D15

DCDC_LP

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Package Information and Contact Assignments

Table 65. i.MX287 MAPBGA Contact Assignments (continued)

Contact

Assignment

Contact

Assignment

Contact

Assignment

Signal Name

DCDC_VDDA

DCDC_VDDD

DCDC_VDDIO

DEBUG

B16

ENET0_TX_CLK E3

ENET0_TX_EN F4

LRADC6

C14

D17

C17

B9

PSWITCH

A11

K7

ENET_CLK

GPMI_ALE

GPMI_CE0N

GPMI_CE1N

GPMI_CE2N

GPMI_CE3N

GPMI_CLE

GPMI_D00

GPMI_D01

GPMI_D02

GPMI_D03

GPMI_D04

GPMI_D05

GPMI_D06

GPMI_D07

GPMI_RDN

GPMI_RDY0

GPMI_RDY1

GPMI_RDY2

GPMI_RDY3

E2

PWM0

P6

N7

N9

M7

M9

P7

U8

T8

R8

U7

T7

R7

U6

T6

R6

N6

N8

M8

L8

PWM1

L7

EMI_A00

EMI_A01

EMI_A02

EMI_A03

EMI_A04

EMI_A05

EMI_A06

EMI_A07

EMI_A08

EMI_A09

EMI_A10

EMI_A11

EMI_A12

EMI_A13

EMI_A14

EMI_BA0

EMI_BA1

EMI_BA2

EMI_CASN

EMI_CE0N

EMI_CE1N

EMI_CKE

EMI_CLK

EMI_CLKN

EMI_D00

EMI_D01

EMI_D02

EMI_D03

U15

U12

U14

T11

U10

R11

R9

PWM2

K8

PWM3

E9

PWM4

E10

A14

D11

C11

F7

RESETN

RTC_XTALI

RTC_XTALO

SAIF0_BITCLK

SAIF0_LRCLK

SAIF0_MCLK

SAIF0_SDATA0

SAIF1_SDATA0

SPDIF

N11

U9

G6

G7

E7

P10

U13

T10

U11

T9

E8

D7

A4

SSP0_CMD

SSP0_DATA0

SSP0_DATA1

SSP0_DATA2

SSP0_DATA3

SSP0_DATA4

SSP0_DATA5

SSP0_DATA6

SSP0_DATA7

B6

N10

T16

T12

N12

U16

P12

P9

C6

D6

A5

B5

GPMI_RESETN L9

C5

D5

B4

GPMI_WRN

HSADC0

P8

B14

C7

T13

L17

L16

N16

M13

P15

N14

I2C0_SCL

I2C0_SDA

JTAG_RTCK

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

SSP0_DETECT D10

D8

SSP0_SCK

SSP1_CMD

SSP1_DATA0

SSP1_DATA3

SSP1_SCK

SSP2_MISO

A6

C1

D1

E1

B1

B3

E14

E11

E12

E13

D12

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Package Information and Contact Assignments

Table 65. i.MX287 MAPBGA Contact Assignments (continued)

Contact

Assignment

Contact

Assignment

Contact

Assignment

Signal Name

EMI_D04

EMI_D05

EMI_D06

EMI_D07

EMI_D08

EMI_D09

EMI_D10

EMI_D11

EMI_D12

EMI_D13

EMI_D14

EMI_D15

P13

JTAG_TRST

LCD_CS

D14

SSP2_MOSI

SSP2_SCK

SSP2_SS0

SSP2_SS1

SSP2_SS2

SSP3_MISO

SSP3_MOSI

SSP3_SCK

SSP3_SS0

TESTMODE

USB0DM

C3

P17

L14

M17

G16

H15

G14

J14

P5

K2

K3

L2

A3

LCD_D00

LCD_D01

LCD_D02

LCD_D03

LCD_D04

LCD_D05

LCD_D06

LCD_D07

LCD_D08

LCD_D09

LCD_D10

C4

D3

D4

B2

L3

M2

M3

N2

P1

P2

P3

R1

C2

A2

H13

H17

F13

F17

D2

C10

A10

B10

B8

USB0DP

EMI_DDR_OPE K14

N

USB1DM

EMI_DDR_OPE L15

N_FB

LCD_D11

R2

USB1DP

A8

EMI_DQM0

EMI_DQM1

EMI_DQS0

EMI_DQS0N

EMI_DQS1

M15

F15

K17

K16

J17

LCD_D12

LCD_D13

LCD_D14

LCD_D15

LCD_D16

T1

T2

U2

U3

T3

VDD1P5

VDD4P2

VDD5V

XTALI

D16

A13

E17

A12

B12

XTALO

4.4

i.MX280 Ball Map

Table 66 shows the i.MX280 MAPBGA ball map.

Table 66. 289-Pin i.MX280 MAPBGA Ball Map

i.MX28 Applications Processors for Consumer Products, Rev. 3

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63

Package Information and Contact Assignments

Table 66. 289-Pin i.MX280 MAPBGA Ball Map (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Package Information and Contact Assignments

Table 66. 289-Pin i.MX280 MAPBGA Ball Map (continued)

4.5

i.MX283 Ball Map

Table 67 shows the i.MX283 MAPBGA ball map.

Table 67. 289-Pin i.MX283 MAPBGA Ball Map

i.MX28 Applications Processors for Consumer Products, Rev. 3

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65

Package Information and Contact Assignments

Table 67. 289-Pin i.MX283 MAPBGA Ball Map (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Package Information and Contact Assignments

Table 67. 289-Pin i.MX283 MAPBGA Ball Map (continued)

4.6

i.MX286 Ball Map

Table 68 shows the i.MX286 MAPBGA ball map.

Table 68. 289-Pin i.MX286 MAPBGA Ball Map

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

67

Package Information and Contact Assignments

Table 68. 289-Pin i.MX286 MAPBGA Ball Map (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 3

68

Freescale Semiconductor

Package Information and Contact Assignments

Table 68. 289-Pin i.MX286 MAPBGA Ball Map (continued)

4.7

i.MX287 Ball Map

Table 69 shows the i.MX287 MAPBGA Ball Map.

Table 69. 289-Pin i.MX287 MAPBGA Ball Map

i.MX28 Applications Processors for Consumer Products, Rev. 3

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69

Package Information and Contact Assignments

Table 69. 289-Pin i.MX287 MAPBGA Ball Map (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Freescale Semiconductor

Package Information and Contact Assignments

Table 69. 289-Pin i.MX287 MAPBGA Ball Map (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 3

Freescale Semiconductor

71

Revision History

5 Revision History

Table 70 summarizes revisions to this document.

Table 70. Document Revision History

Substantive Change(s)

Rev.

Number

Date

,

Rev. 3 07/2012 • Removed the Power Consumption table, and added Table 12, "Run IDD Test Case ," on page 14.

• Updated Table 23, "ON Impedance of EMI Drivers for Different Drive Strengths," on page 20.

Rev. 2 03/2012 • In Section 1.1, “Device Features:”

—Updated synchronous serial ports (SSP) support for the i.MX28

—Updated Ethernet support for the i.MX28

—Updated Low-Resolution A/D Converter (LRADC) support for the i.MX28

• Updated Table 2, "i.MX28 Functional Differences," on page 4.

• In Table 6, "DC Absolute Maximum Ratings," on page 12, removed the PSWITCH parameter as this

paramater is explained in detail in Table 11.

• In Table 8, "Recommended Power Supply Operating Conditions," on page 13:

—Updated two parameters: “VDD5V Supply Voltage” and “Offstate Current”

—Updated the third footnote

• In Table 9, "Operating Temperature Conditions," on page 13, added a new footnote in the “Parameter”

column.

• In Table 13, "Power Supply Characteristics," on page 15, updated the “VDD4P2 Output Current Limit

Accuracy” parameter.

• In Section 3.1.2.1, “Recommended Operating Conditions for Specific Clock Targets:”

—Removed the “System Clocks” table

—Updated two TBD values in the first row of Table 14

—Removed the first row in Table 15

—Removed the first row in Table 16

• In Table 20, "Power Mode Settings," on page 17, changed the second column name from “Deep Sleep”

to “Offstate.”

• Updated Table 22, "EMI Digital Pin DC Characteristics," on page 20.

• In Table 30, "LRADC Electrical Specifications," on page 27, updated the “DC Electrical Specification”

section.

• In Table 31, "HSADC Electrical Specification," on page 28, updated the “DC Electrical Specification”

section.

• In Section 3.5.5, “Coresight ETM9 AC Interface Timing,” updated the first paragraph.

• In Section 3.5.5.1, “TRACECLK Timing,” corrected the title of Table 43.

• In Section 3.5.5.2, “Trace Data Signal Timing,” corrected the titles of Figure 15 and Table 44.

Rev. 1 04/2011 • Updated Section 1.1, “Device Features.”

• Added Section 3.2, “Thermal Characteristics.”

• In Table 1, "Ordering Information," on page 3, added two rows.

• Updated Table 2, "i.MX28 Functional Differences," on page 4.

• Updated Table 4, "i.MX28 Digital and Analog Modules," on page 7.

• In Table 8, "Recommended Power Supply Operating Conditions," on page 13, updated BATT row.

• Updated Table 9, "Operating Temperature Conditions," on page 13.

• Replaced the term “DC Characteristics” with “Power Consumption” in the title and introduction of the

Power Consumption table. Also changed Dissipation to Consumption in first row.

• Updated Table 25, "Digital Pin DC Characteristics for GPIO in 3.3-V Mode," on page 21.

• Updated Table 26, "Digital Pin DC Characteristics for GPIO in 1.8 V Mode," on page 22.

• Updated and added a footnote to Table 33, "Ethernet PLL Specifications," on page 29.

• Updated DDR1 row of Table 34, "EMI Command/Address AC Timing," on page 30.

• Added Section 4.4, “i.MX280 Ball Map.”

• In Section 4.5, “i.MX283 Ball Map,” updated Figure 67.

i.MX28 Applications Processors for Consumer Products, Rev. 3

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Revision History

Table 70. Document Revision History (continued)

Substantive Change(s)

Rev.

Number

Date

Rev. 0 09/2010 Initial release.

i.MX28 Applications Processors for Consumer Products, Rev. 3

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73

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Document Number: IMX28CEC

Rev. 3

07/2012


型号：	MCIMX280CVM4B
厂家：	NXP
描述：	i.MX28 32-bit MPU, ARM926EJ-S core, 454MHz, MAPBGA 289 时钟外围集成电路
文件：	总74页 (文件大小：820K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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