MCIMX6S1AVM10AB_技术文档

Document Number: IMX6SDLCEC

Rev. 9, 11/2018

NXP Semiconductors

Data Sheet: Technical Data

MCIMX6SxExxxxxB MCIMX6SxDxxxxxB

MCIMX6SxExxxxxC MCIMX6SxDxxxxxC

MCIMX6SxExxxxxD MCIMX6SxDxxxxxD

MCIMX6UxExxxxxB MCIMX6UxDxxxxxB

MCIMX6UxExxxxxC MCIMX6UxDxxxxxC

MCIMX6UxExxxxxD MCIMX6UxDxxxxxD

i.MX 6Solo/6DualLite

Applications Processors

for Consumer Products

Package Information

Plastic Package

BGA Case 2240 21 x 21 mm, 0.8 mm pitch

Ordering Information

See Table 1 on page 3

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.3 Updated Signal Naming Convention . . . . . . . . . . . .9

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Modules List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1 Special Signal Considerations . . . . . . . . . . . . . . . .21

3.2 Recommended Connections for Unused Analog

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

1 Introduction

The i.MX 6Solo/6DualLite processors represent the

latest achievement in integrated multimedia-focused

products offering high performance processing with

lower cost, as well as optimization for low power

consumption.

2

3

4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .23

4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .23

4.2 Power Supplies Requirements and Restrictions . .33

4.3 Integrated LDO Voltage Regulator Parameters . . .34

4.4 PLL’s Electrical Characteristics . . . . . . . . . . . . . . .36

4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .38

4.6 I/O DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . .39

4.7 I/O AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . .44

4.8 Output Buffer Impedance Parameters . . . . . . . . . .49

4.9 System Modules Timing. . . . . . . . . . . . . . . . . . . . .52

4.10 General-Purpose Media Interface (GPMI) Timing .64

4.11 External Peripheral Interface Parameters . . . . . . .72

Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .134

5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .134

5.2 Boot Device Interface Allocation . . . . . . . . . . . . .135

Package Information and Contact Assignments . . . . . .136

6.1 Updated Signal Naming Convention . . . . . . . . . .136

6.2 21x21 mm Package Information. . . . . . . . . . . . . .137

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

The processors feature advanced implementation of

®

single/dual Arm Cortex -A9 core, which operates at

speeds of up to 1 GHz. They include 2D and 3D graphics

processors, 1080p video processing, and integrated

power management. Each processor provides a 32/64-bit

DDR3/DDR3L/LPDDR2-800 memory interface and a

number of other interfaces for connecting peripherals,

®

such as WLAN, Bluetooth , GPS, hard drive, displays,

and camera sensors.

5

6

7

The i.MX 6Solo/6DualLite processors are specifically

useful for applications such as:

•

Web and multimedia tablets

NXP Reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products

Introduction

•

Color eReaders

IPTV

Human Machine Interfaces (HMI)

Portable medical

IP phones

Home energy management systems

The i.MX 6Solo/6DualLite applications processors feature:

•

Applications processors—The processors enhance the capabilities of high-tier portable

applications by fulfilling the ever increasing MIPS requirements of operating systems and games.

The Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction,

allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks, such as

audio decode.

Multilevel memory system—The multilevel memory system of each processor is based on the L1

instruction and data caches, L2 cache, and internal and external memory. The processors support

many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash,

PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND,

including eMMC up to rev 4.4/4.41.

Smart speed technology—The processors have power management throughout the IC that enables

the rich suite of multimedia features and peripherals to consume minimum power in both active

and various low power modes. Smart speed technology enables the designer to deliver a

feature-rich product, requiring levels of power far lower than industry expectations.

•

Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices

by scaling the voltage and frequency to optimize performance.

Multimedia powerhouse—The multimedia performance of each processor is enhanced by a

multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, a multi-standard

hardware video codec, an image processing unit (IPU), a programmable smart DMA (SDMA)

controller, and an asynchronous sample rate converter.

•

Powerful graphics acceleration—Each processor provides two independent, integrated graphics

processing units: an OpenGL ES 2.0 3D graphics accelerator with a shader and a 2D graphics

accelerator.

®

Interface flexibility—Each processor supports connections to a variety of interfaces: LCD

controller for up to two displays (including parallel display, HDMI1.4, MIPI display, and LVDS

display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with

PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host

and other), 10/100/1000 Mbps Gigabit Ethernet controller two CAN ports, ESAI audio interface,

2

and a variety of other popular interfaces (such as UART, I C, and I S serial audio, and PCIe-II).

•

Eink Panel Display Controller—The processors integrate EPD controller that supports E-INK

color and monochrome with up to 1650x2332 resolution and 5-bit grayscale (32-levels per color

channel).

Advanced security—The processors deliver hardware-enabled security features that enable secure

e-commerce, digital rights management (DRM), information encryption, secure boot, and secure

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

2

NXP Semiconductors

Introduction

software downloads. The security features are discussed in detail in the i.MX 6Solo/6DualLite

Security Reference Manual (IMX6DQ6SDLSRM).

•

Integrated power management—The processors integrate linear regulators and internally generate

voltage levels for different domains. This significantly simplifies system power management

structure.

1.1

Ordering Information

Table 1 provides examples of orderable part numbers covered by this data sheet. Table 1 does not include

all possible orderable part numbers. The latest part numbers are available on the web page

nxp.com/imx6series. If the desired part number is not listed in Table 1, go to nxp.com/imx6series or

contact a NXP representative for details.

Table 1. Example Orderable Part Numbers

i.MX6 CPU

Solo/

DualLite

Speed Temperature

Part Number

Options

Package

Grade¹

Grade

MCIMX6U8DVM10AB DualLite With VPU, GPU, EPDC, MLB

2x Arm Cortex-A9 64-bit DDR

1 GHz

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

MCIMX6U8DVM10AC DualLite With VPU, GPU, EPDC, MLB

2x Arm Cortex-A9 64-bit DDR

1 GHz

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

MCIMX6U8DVM10AD DualLite With VPU, GPU, EPDC, MLB

2x Arm Cortex-A9 64-bit DDR

Commercial 21 mm x 21 mm, 0.8 mm

pitch, MAPBGA

MCIMX6U5DVM10AB DualLite With VPU, GPU, MLB, no EPDC

2x Arm Cortex-A9 64-bit DDR

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

MCIMX6U5DVM10AC DualLite With VPU, GPU, MLB, no EPDC

2x Arm Cortex-A9 64-bit DDR

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

MCIMX6U5DVM10AD DualLite With VPU, GPU, MLB, no EPDC

2x Arm Cortex-A9 64-bit DDR

Commercial 21 mm x 21 mm, 0.8 mm

pitch, MAPBGA

SCIMX6U5DVM10CB DualLite HDCP enabled with VPU, GPU, MLB, no

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

EPDC

2x Arm Cortex-A9 64-bit DDR

SCIMX6U5DVM10CC DualLite HDCP enabled with VPU, GPU, MLB, no

1 GHz

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

EPDC

2x Arm Cortex-A9 64-bit DDR

SCIMX6U5DVM10CD DualLite HDCP enabled with VPU, GPU, MLB, no

Commercial 21 mm x 21 mm, 0.8 mm

pitch, MAPBGA

EPDC

2x Arm Cortex-A9 64-bit DDR

MCIMX6U5EVM10AB DualLite With VPU, GPU, MLB, no EPDC

2x Arm Cortex-A9 64-bit DDR

1 GHz

Extended 21 mm x 21 mm,

Commercial 0.8 mm pitch, MAPBGA

MCIMX6U5EVM10AC DualLite With VPU, GPU, MLB, no EPDC

2x Arm Cortex-A9 64-bit DDR

Extended 21 mm x 21 mm,

Commercial 0.8 mm pitch, MAPBGA

MCIMX6U5EVM10AD DualLite With VPU, GPU, MLB, no EPDC

2x Arm Cortex-A9 64-bit DDR

Extended 21 mm x 21 mm, 0.8 mm

Commercial pitch, MAPBGA

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

3

Introduction

Table 1. Example Orderable Part Numbers (continued)

i.MX6 CPU

Solo/

DualLite

Speed Temperature

Part Number

Options

Package

Grade¹

Grade

MCIMX6S8DVM10AB

MCIMX6S8DVM10AC

MCIMX6S8DVM10AD

MCIMX6S5DVM10AB

MCIMX6S5DVM10AC

MCIMX6S5DVM10AD

SCIMX6S5DVM10CB

Solo

With VPU, GPU, MLB, EPDC

1x Arm Cortex-A9 32-bit DDR

1 GHz

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

With VPU, GPU, MLB, EPDC

1x Arm Cortex-A9 32-bit DDR

1 GHz

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

With VPU, GPU, MLB, EPDC

1x Arm Cortex-A9 32-bit DDR

Commercial 21 mm x 21 mm, 0.8 mm

pitch, MAPBGA

With VPU, GPU, MLB, no EPDC

1x Arm Cortex-A9 32-bit DDR

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

With VPU, GPU, MLB, no EPDC

1x Arm Cortex-A9 32-bit DDR

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

With VPU, GPU, MLB, no EPDC

1x Arm Cortex-A9 32-bit DDR

Commercial 21 mm x 21 mm, 0.8 mm

pitch, MAPBGA

HDCP enabled with VPU, GPU, MLB, no

EPDC

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

1x Arm Cortex-A9 32-bit DDR

SCIMX6S5DVM10CC

SCIMX6S5DVM10CD

Solo

HDCP enabled with VPU, GPU, MLB, no

EPDC

1x Arm Cortex-A9 32-bit DDR

1 GHz

Commercial 21 mm x 21 mm,

0.8 mm pitch, MAPBGA

HDCP enabled with VPU, GPU, MLB, no

EPDC

Commercial 21 mm x 21 mm, 0.8 mm

pitch, MAPBGA

1x Arm Cortex-A9 32-bit DDR

MCIMX6S5EVM10AB

MCIMX6S5EVM10AC

MCIMX6S5EVM10AD

Solo

With VPU, GPU, MLB, no EPDC

1x Arm Cortex-A9 32-bit DDR

1 GHz

Extended 21 mm x 21 mm,

Commercial 0.8 mm pitch, MAPBGA

With VPU, GPU, MLB, no EPDC

1x Arm Cortex-A9 32-bit DDR

Extended 21 mm x 21 mm,

Commercial 0.8 mm pitch, MAPBGA

With VPU, GPU, MLB, no EPDC

1x Arm Cortex-A9 32-bit DDR

Extended 21 mm x 21 mm, 0.8 mm

Commercial pitch, MAPBGA

1

If a 24 MHz input clock is used (required for USB), then the maximum SoC speed is limited to 996 MHz.

Figure 1 describes the part number nomenclature to identify the characteristics of a specific part number

(for example, cores, frequency, temperature grade, fuse options, and silicon revision).

The primary characteristic that differentiates which data sheet applies to a specific part is the temperature

grade (junction) field. The following list describes the correct data sheet to use for a specific part:

•

The i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors data sheet

(IMX6SDLAEC) covers parts listed with an “A (Automotive temp)”

•

The i.MX 6Solo/6DualLite Applications Processors for Consumer Products data sheet

(IMX6SDLCEC) covers parts listed with a “D (Commercial temp)” or “E (Extended Commercial

temp)”

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

4

NXP Semiconductors

Introduction

•

The i.MX 6Solo/6DualLite Applications Processors for Industrial Products data sheet

(IMX6SDLIEC) covers parts listed with “C (Industrial temp)”

For more information go to nxp.com/imx6series or contact a NXP representative for details.

MC

IMX6 X @

+

VV

$$ % A

Silicon revision¹

A

B

Qualification level

MC

Rev 1.1

Prototype Samples

Mass Production

Special

PC

MC

SC

Rev 1.2 (Maskset ID: 2N81E)

Rev 1.3 (Maskset ID: 3N81E)

C

Rev 1.4 (Maskset ID: 4N81E)

D

Fusing

%

A

Part # series

X

Default settings

HDCP enabled

i.MX 6DualLite

2x ARM Cortex-A9, 64-bit DDR

U

C

i.MX 6Solo

S

Frequency

$$

1x ARM Cortex-A9, 32-bit DDR

800 MHz²

1 GHz³

08

10

Part differentiator

@

RoHS

Package type

Consumer

Industrial

VPU

–

GPU

–

EPDC

MLB

–

8

7

6

5

4

1

MAPBGA 21 x 21 0.8mm

VM

Temperature Tj

+

–

Commercial: 0 to + 95^°C

D

Automotive

Consumer

Automotive

MLB

Extended commercial: -20 to + 105^°C

Industrial: -40 to +105^°C

E

C

A

Automotive: -40 to + 125^°C

–

1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.

2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.

3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.

Figure 1. Part Number Nomenclature—i.MX 6Solo and 6DualLite

Figure 2. Example Part Marking

1.2

Features

The i.MX 6Solo/6DualLite processors are based on Arm Cortex-A9 MPCore Platform, which has the

following features:

•

The i.MX 6Solo supports single Arm Cortex-A9 MPCore (with TrustZone)

The i.MX 6DualLite supports dual Arm Cortex-A9 MPCore (with TrustZone)

The core configuration is symmetric, where each core includes:

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

5

Introduction

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

The Arm Cortex-A9 MPCore complex includes:

•

General Interrupt Controller (GIC) with 128 interrupt support

Global Timer

Snoop Control Unit (SCU)

512 KB unified I/D L2 cache:

— Used by one core in i.MX 6Solo

— Shared by two cores in i.MX 6DualLite

Two Master AXI bus interfaces output of L2 cache

Frequency of the core (including NEON and L1 cache), as per Table 8.

NEON MPE coprocessor

•

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)

— Secure/non-secure RAM (16 KB)

•

External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume,

cost effective handheld DRAM, NOR, and NAND Flash memory standards.

— 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and DDR3L-800 in i.MX 6Solo; 16/32/64-bit

LP-DDR2-800, 16/32/64-bit DDR3-800 and DDR3L-800, supporting DDR interleaving mode

for 2x32 LPDDR2-800 in i.MX 6DualLite

— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,

BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.

— 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces.

— 16/32-bit PSRAM, Cellular RAM

Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them

are muxed and not available simultaneously):

•

Displays—Total of five interfaces available. Total raw pixel rate of all interfaces is up to 450

Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel (excluding EPDC).

— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual

HD1080 and WXGA at 60 Hz)

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

6

NXP Semiconductors

Introduction

— LVDS serial ports—One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example,

WUXGA at 60 Hz) each

— HDMI 1.4 port

— MIPI/DSI, two lanes at 1 Gbps

— EPDC, Color, and monochrome E-INK, up to 1650x2332 resolution and 5-bit grayscale

Camera sensors:

•

— Two parallel Camera ports (up to 20 bit and up to 240 MHz peak)

— MIPI CSI-2 Serial port, supporting from 80 Mbps to 1 Gbps speed per data lane. The CSI-2

Receiver core can manage one clock lane and up to two data lanes. Each i.MX 6Solo/6DualLite

processor has two lanes.

Expansion cards:

— Four MMC/SD/SDIO card ports all supporting:

– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104

mode (104 MB/s max)

– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR

and DDR modes (104 MB/s max)

•

USB^:

— One high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy

— Three USB 2.0 (480 Mbps) hosts:

– One HS host with integrated High Speed Phy

– Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) Phy

Expansion PCI Express port (PCIe) v2.0 one lane

•

— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint

operations. Uses x1 PHY configuration.

Miscellaneous IPs and interfaces:

— SSI block is capable of supporting audio sample frequencies up to 192 kHz stereo inputs and

2

outputs with I S mode

2

— ESAI is capable of supporting audio sample frequencies up to 260 kHz in I S mode with 7.1

multi channel outputs

— Five UARTs, up to 5.0 Mbps each:

– Providing RS232 interface

– Supporting 9-bit RS485 multidrop mode

– One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is

due to the SoC IOMUX limitation, since all UART IPs are identical.

— Four eCSPI (Enhanced CSPI)

2

— Four I C, supporting 400 kbps

1

— Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/1000 Mbps

1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus

throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the

ERR004512 erratum in the i.MX 6Solo/6DualLite errata document (IMX6SDLCE).

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NXP Semiconductors

7

Introduction

— Four Pulse Width Modulators (PWM)

— System JTAG Controller (SJC)

— GPIO with interrupt capabilities

— 8x8 Key Pad Port (KPP)

— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx

— Two Controller Area Network (FlexCAN), 1 Mbps each

— Two Watchdog timers (WDOG)

— Audio MUX (AUDMUX)

— MLB (MediaLB) provides interface to MOST Networks (MOST25, MOST50, MOST150)

with the option of DTCP cipher accelerator

The i.MX 6Solo/6DualLite processors integrate advanced power management unit and controllers:

•

Provide PMU, including LDO supplies, for on-chip resources

Use Temperature Sensor for monitoring the die temperature

Support DVFS techniques for low power modes

Use SW State Retention and Power Gating for Arm and MPE

Support various levels of system power modes

Use flexible clock gating control scheme

The i.MX 6Solo/6DualLite processors use dedicated hardware accelerators to meet the targeted

multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance

at low power consumption numbers, while having the CPU core relatively free for performing other tasks.

The i.MX 6Solo/6DualLite processors incorporate the following hardware accelerators:

•

VPU—Video Processing Unit

IPUv3H—Image Processing Unit version 3H

GPU3Dv5—3D Graphics Processing Unit (OpenGL ES 2.0) version 5

GPU2Dv2—2D Graphics Processing Unit (BitBlt)

PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to

support the EPD display applications.

•

ASRC—Asynchronous Sample Rate Converter

Security functions are enabled and accelerated by the following hardware:

•

Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)

SJC—SystemJTAGController. ProtectingJTAGfromdebugportattacks by regulating or blocking

the access to the system debug features.

•

CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash

engines, 16 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified).

•

SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock

CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be

configured during boot and by eFUSEs and will determine the security level operation mode as

well as the TZ policy.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

8

NXP Semiconductors

Introduction

•

A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.

NOTE

The actual feature set depends on the part numbers as described in Table 1,

"Example Orderable Part Numbers," on page 3. Functions, such as video

hardware acceleration, and 2D and 3D hardware graphics acceleration may

not be enabled for specific part numbers.

1.3

Updated Signal Naming Convention

The signal names of the i.MX6 series of products have been standardized to better align the signal names

within the family and across the documentation. Some of the benefits of these changes are as follows:

•

The names are unique within the scope of an SoC and within the series of products

Searches will return all occurrences of the named signal

The names are consistent between i.MX 6 series products implementing the same modules

The module instance is incorporated into the signal name

This change applies only to signal names. The original ball names have been preserved to prevent the need

to change schematics, BSDL models, IBIS models, etc.

Throughout this document, the updated signal names are used except where referenced as a ball name

(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal

name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to

map the signal names used in older documentation to the new standardized naming conventions.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

9

Architectural Overview

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX 6Solo/6DualLite processor

system.

2.1

Block Diagram

Figure 3 shows the functional modules in the i.MX 6Solo/6DualLite processor system.

MIPI

Raw / ONFI 2.2

NAND Flash

LPDDR2/DDR3

400 MHz (DDR800)

NOR Flash

PSRAM

Battery Ctrl

Device

2x Camera

1 / 2 LVDS

1 / 2 LCD

Displays

HDMI 1.4

Display

Parallel/MIPI (WUXGA+)

Application Processor

Domain (AP)

CSI2/MIPI LDB

HDMI

DSI/MIPI

External

Memory I/F

Digital

Audio

GPMI

MMDC

EIM

Internal

RAM

(144 KB)

E-INK

Display

Image Processing

Subsystem

1

EPDC

PxP

IPUv3H

Boot

ROM

(96 KB)

2xCAN i/f

PCIe Bus

Arm Cortex A9

MPCore Platform

Smart DMA

(SDMA)

Debug

DAP

TPIU

CTIs

SJC

1x/2x A9-Core

L1 I/D Cache

Timer, WDOG

SPBA

MMC/SD

eMMC/eSD

AP Peripherals

uSDHC (4)

512K L2 cache

SCU, Timer

MMC/SD

SDXC

AUDMUX

Shared Peripherals

PTM’s CTI’s

GPS

2

I C(4)

Security

Video

Proc. Unit

(VPU + Cache)

eCSPI (4)

ESAI

SSI (3)

PWM (4)

OCOTP_CTRL

IOMUXC

KPP

CAAM

(16KB Ram)

5xFast-UART

SPDIF Rx/Tx

Modem IC

SNVS

(SRTC)

ASRC

Audio,

Power

Mngmnt.

3D Graphics

Proc. Unit

(GPU3D)

CSU

Power Management

GPIO

Fuse Box

Unit (LDOs)

CAN(2)

Keypad

1-Gbps ENET

MLB 150

DTCP

Clock and Reset

2D Graphics

Proc. Unit

(GPU2D)

Timers/Control

WDOG (2)

GPT

PLL (8)

CCM

Crystals

& Clock sources

GPC

HSI/MIPI

Ethernet

10/100/1000

Mbps

EPIT (2)

SRC

Temp Monitor

USB OTG +

3 HS Ports

XTALOSC

OSC32K

OTG PHY1

Host PHY2

2xHSIC

PHY

USB OTG

(dev/host)

JTAG

(IEEE1149.6)

MLB/Most

Network

Bluetooth

WLAN

1

2

144 KB RAM including 16 KB RAM inside the CAAM.

For i.MX 6Solo, there is only one A9-core platform in the chip; for i.MX 6DualLite, there are two A9-core platforms.

Figure 3. i.MX 6Solo/6DualLite System Block Diagram

NOTE

The numbers in brackets indicate number of module instances. For example,

PWM (4) indicates four separate PWM peripherals.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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NXP Semiconductors

Modules List

3 Modules List

The i.MX 6Solo/6DualLite processors contain a variety of digital and analog modules. Table 2 describes

these modules in alphabetical order.

Table 2. i.MX 6Solo/6DualLite Modules List

Block Mnemonic

Block Name

Subsystem

Brief Description

APBH-DMA

NAND Flash and BCH

ECC DMA controller

System Control

Peripherals

DMA controller used for GPMI2 operation

Arm

Arm Platform

Arm

The Arm Core Platform includes 1x (Solo) Cortex-A9

core for i.MX 6Solo and 2x (Dual) Cortex-A9 cores for

i.MX 6DualLite. It also includes associated sub-blocks,

such as the Level 2 Cache Controller, SCU (Snoop

Control Unit), GIC (General Interrupt Controller), private

timers, watchdog, and CoreSight debug modules.

ASRC

Asynchronous Sample

Rate Converter

Multimedia

Peripherals

The Asynchronous Sample Rate Converter (ASRC)

converts the sampling rate of a signal associated to an

input clock into a signal associated to a different output

clock. The ASRC supports concurrent sample rate

conversion of up to 10 channels of about -120dB

THD+N. The sample rate conversion of each channel is

associated to a pair of incoming and outgoing sampling

rates. The ASRC supports up to three sampling rate

pairs.

AUDMUX

Digital Audio Mux

Multimedia

Peripherals

The AUDMUX is a programmable interconnect for voice,

audio, and synchronous data routing between host

serial interfaces (for example, SSI1, SSI2, and SSI3)

and peripheral serial interfaces (audio and voice

codecs). The AUDMUX has seven ports with identical

functionality and programming models. A desired

connectivity is achieved by configuring two or more

AUDMUX ports.

BCH40

CAAM

Binary-BCH ECC

Processor

System Control

Peripherals

The BCH40 module provides up to 40-bit ECC for

NAND Flash controller (GPMI)

Cryptographic

accelerator and

assurance module

Security

CAAM is a cryptographic accelerator and assurance

module. CAAM implements several encryption and

hashing functions, a run-time integrity checker, and a

Pseudo Random Number Generator (PRNG). The

pseudo random number generator is certified by

Cryptographic Algorithm Validation Program (CAVP) of

National Institute of Standards and Technology (NIST).

Its DRBG validation number is 94 and its SHS validation

number is 1455.

CAAM also implements a Secure Memory mechanism.

In i.MX 6Solo/6DualLite processors, the security

memory provided is 16 KB.

CCM

GPC

SRC

Clock Control Module,

GeneralPowerController,

System Reset Controller

Clocks, Resets, and These modules are responsible for clock and reset

Power Control

distribution in the system, and also for the system power

management.

CSI

MIPI CSI-2 i/f

Multimedia

Peripherals

The CSI IP provides MIPI CSI-2 standard camera

interface port. The CSI-2 interface supports from 80

Mbps to 1 Gbps speed per data lane.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

CSU

Central Security Unit

Security

The Central Security Unit (CSU) is responsible for

setting comprehensive security policy within the i.MX

6Solo/6DualLite platform.

CTI-0

CTI-1

CTI-2

CTI-3

CTI-4

Cross Trigger Interfaces

Debug / Trace

Cross Trigger Interfaces allows cross-triggering based

on inputs from masters attached to CTIs. The CTI

module is internal to the Cortex-A9 Core Platform.

CTM

Cross Trigger Matrix

Debug Access Port

Cross Trigger Matrix IP is used to route triggering events

between CTIs. The CTM module is internal to the

Cortex-A9 Core Platform.

DAP

System Control

Peripherals

The DAP provides real-time access for the debugger

without halting the core to:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan

chains. The DAP module is internal to the Cortex-A9

Core Platform.

DCIC-0

DCIC-1

Display Content Integrity

Checker

Automotive IP

The DCIC provides integrity check on portion(s) of the

display. Each i.MX 6Solo/6DualLite processor has two

such modules.

DSI

DTCP

MIPI DSI i/f

DTCP

Multimedia

Peripherals

The MIPI DSI IP provides DSI standard display port

interface. The DSI interface support 80 Mbps to 1 Gbps

speed per data lane.

Multimedia

Peripherals

Provides encryption function according to Digital

Transmission Content Protection standard for traffic

over MLB150.

eCSPI1-4

ENET

Configurable SPI

Ethernet Controller

Connectivity

Peripherals

Full-duplex enhanced Synchronous Serial Interface. It is

configurable to support Master/Slave modes, four chip

selects to support multiple peripherals.

Connectivity

Peripherals

The Ethernet Media Access Controller (MAC) is

designed to support 10/100/1000 Mbps Ethernet/IEEE

802.3 networks. An external transceiver interface and

transceiver function are required to complete the

interface to the media. The module has dedicated

hardware to support the IEEE 1588 standard. See the

ENET chapter of the reference manual for details.

Note: The theoretical maximum performance of 1 Gbps

ENET is limited to 470 Mbps (total for Tx and Rx) due to

internal bus throughput limitations. The actual

measured performance in optimized environment is up

to 400 Mbps. For details, see the ERR004512 erratum

in the i.MX 6Solo/6DualLite errata document

(IMX6SDLCE).

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

The EPDC is a feature-rich, low power, and

high-performance direct-drive, active matrix EPD

^{controller. It is specifically designed to drive E-INK}™

EPD panels, supporting a wide variety of TFT

backplanes. It is available in both i.MX 6DualLite and

i.MX 6Solo.

EPDC

Electrophoretic Display

Controller

Peripherals

EPIT-1

EPIT-2

Enhanced Periodic

Interrupt Timer

Timer Peripherals

Each EPIT is a 32-bit “set and forget” timer that starts

counting after the EPIT is enabled by software. It is

capable of providing precise interrupts at regular

intervals with minimal processor intervention. It has a

12-bit prescaler for division of input clock frequency to

get the required time setting for the interrupts to occur,

and counter value can be programmed on the fly.

ESAI

Enhanced Serial Audio

Interface

Connectivity

Peripherals

The Enhanced Serial Audio Interface (ESAI) provides a

full-duplex serial port for serial communication with a

variety of serial devices, including industry-standard

codecs, SPDIF transceivers, and other processors.

The ESAI consists of independent transmitter and

receiver sections, each section with its own clock

generator. All serial transfers are synchronized to a

clock. Additional synchronization signals are used to

delineate the word frames. The normal mode of

operation is used to transfer data at a periodic rate, one

word per period. The network mode is also intended for

periodic transfers; however, it supports up to 32 words

(time slots) per period. This mode can be used to build

time division multiplexed (TDM) networks. In contrast,

the on-demand mode is intended for non-periodic

transfers of data and to transfer data serially at high

speed when the data becomes available.

The ESAI has 12 pins for data and clocking connection

to external devices.

FlexCAN-1

FlexCAN-2

Flexible Controller Area

Network

Connectivity

Peripherals

The CAN protocol was primarily, but not only, designed

to be used as a vehicle serial data bus, meeting the

specific requirements of this field: real-time processing,

reliable operation in the Electromagnetic interference

(EMI) environment of a vehicle, cost-effectiveness and

required bandwidth. The FlexCAN module is a full

implementation of the CAN protocol specification,

Version 2.0 B, which supports both standard and

extended message frames.

512x8 Fuse Box

Electrical Fuse Array

Security

Electrical Fuse Array. Enables to setup Boot Modes,

Security Levels, Security Keys, and many other system

parameters.

The i.MX 6Solo/6DualLite processors consist of

512x8-bit fuse fox accessible through OCOTP_CTRL

interface.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

GPIO-1

GPIO-2

GPIO-3

GPIO-4

GPIO-5

GPIO-6

GPIO-7

General Purpose I/O

Modules

System Control

Peripherals

Used for general purpose input/output to external ICs.

Each GPIO module supports 32 bits of I/O.

GPMI

General Purpose

Media Interface

Connectivity

Peripherals

The GPMI module supports up to 8x NAND devices.

40-bit ECC encryption/decryption for NAND Flash

controller (GPMI2). The GPMI supports separate DMA

channels per NAND device.

GPT

General Purpose Timer

Timer Peripherals

Each GPT is a 32-bit “free-running” or “set and forget”

mode timer with programmable prescaler and compare

and capture register. A timer counter value can be

captured using an external event and can be configured

to trigger a capture event on either the leading or trailing

edges of an input pulse. When the timer is configured to

operate in “set and forget” mode, it is capable of

providing precise interrupts at regular intervals with

minimal processor intervention. The counter has output

compare logic to provide the status and interrupt at

comparison. This timer can be configured to run either

on an external clock or on an internal clock.

GPU3Dv5

GPU2Dv2

Graphics Processing

Unit, ver.5

Multimedia

Peripherals

The GPU3Dv5 provides hardware acceleration for 3D

graphics algorithms with sufficient processor power to

run desktop quality interactive graphics applications on

displays up to HD1080 resolution. The GPU3D provides

OpenGL ES 2.0, including extensions, OpenGL ES 1.1,

and OpenVG 1.1

Graphics Processing

Unit-2D, ver 2

Multimedia

Peripherals

The GPU2Dv2 provides hardware acceleration for 2D

graphics algorithms, such as Bit BLT, stretch BLT, and

many other 2D functions.

HDMI Tx

HSI

HDMI Tx i/f

MIPI HSI i/f

I²C Interface

Multimedia

Peripherals

The HDMI module provides HDMI standard i/f port to an

HDMI 1.4 compliant display.

Connectivity

Peripherals

The MIPI HSI provides a standard MIPI interface to the

applications processor.

I²C provide serial interface for external devices. Data

rates of up to 400 kbps are supported.

I²C-1

I²C-2

I²C-3

I²C-4

Connectivity

Peripherals

IOMUXC

IOMUX Control

System Control

Peripherals

This module enables flexible IO multiplexing. Each IO

pad has default and several alternate functions. The

alternate functions are software configurable.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

IPUv3H enables connectivity to displays and video

sources, relevant processing and synchronization and

control capabilities, allowing autonomous operation.

The IPUv3H supports concurrent output to two display

ports and concurrent input from two camera ports,

through the following interfaces:

IPUv3H

Image Processing Unit,

ver.3H

Multimedia

Peripherals

• Parallel Interfaces for both display and camera

• Single/dual channel LVDS display interface

• HDMI transmitter

• MIPI/DSI transmitter

• MIPI/CSI-2 receiver

The processing includes:

• Image conversions: resizing, rotation, inversion, and

color space conversion

• A high-quality de-interlacing filter

• Video/graphics combining

• Image enhancement: color adjustment and gamut

mapping, gamma correction, and contrast

enhancement

• Support for display backlight reduction

KPP

LDB

Key Pad Port

Connectivity

Peripherals

KPP Supports 8x8 external key pad matrix. KPP

features are:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

LVDS Display Bridge

Connectivity

Peripherals

LVDS Display Bridge is used to connect the IPU (Image

Processing Unit) to External LVDS Display Interface.

LDB supports two channels; each channel has following

signals:

• One clock pair

• Four data pairs

Each signal pair contains LVDS special differential pad

(PadP, PadM).

MLB150

MMDC

MediaLB

Connectivity /

Multimedia

Peripherals

The MLB interface module provides a link to a MOST^®

data network, using the standardized MediaLB protocol

(up to 6144 fs).

The module is backward compatible to MLB-50.

Multi-Mode DDR

Controller

Connectivity

Peripherals

DDR Controller has the following features:

• Supports 16/32-bit DDR3-800 (LV) or LPDDR2-800

in i.MX 6Solo

• Supports 16/32/64-bit DDR3-800 (LV) or

LPDDR2-800 in i.MX 6DualLite

• Supports 2x32 LPDDR2-800 in i.MX 6DualLite

• Supports up to 4 GByte DDR memory space

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

OCOTP_CTRL

OTP Controller

Security

The On-Chip OTP controller (OCOTP_CTRL) provides

an interface for reading, programming, and/or overriding

identification and control information stored in on-chip

fuse elements. The module supports

electrically-programmable poly fuses (eFUSEs). The

OCOTP_CTRL also provides a set of volatile

software-accessible signals that can be used for

software control of hardware elements, not requiring

non-volatility. The OCOTP_CTRL provides the primary

user-visible mechanism for interfacing with on-chip fuse

elements. Among the uses for the fuses are unique chip

identifiers, mask revision numbers, cryptographic keys,

JTAG secure mode, boot characteristics, and various

control signals, requiring permanent non-volatility.

OCRAM

On-Chip Memory

controller

Data Path

Clocking

The On-Chip Memory controller (OCRAM) module is

designed as an interface between system’s AXI bus and

internal (on-chip) SRAM memory module.

In i.MX 6Solo/6DualLite processors, the OCRAM is

used for controlling the 128 KB multimedia RAM through

a 64-bit AXI bus.

OSC32KHz

PCIe

OSC32KHz

Generates 32.768 KHz clock from external crystal.

The PCIe IP provides PCI Express Gen 2.0 functionality.

PCI Express 2.0

Connectivity

Peripherals

PMU

Power-Management

functions

Data Path

Integrated power management unit. Used to provide

power to various SoC domains.

PWM-1

PWM-2

PWM-3

PWM-4

Pulse Width Modulation

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter

and is optimized to generate sound from stored sample

audio images and it can also generate tones. It uses

16-bit resolution and a 4x16 data FIFO to generate

sound.

PXP

PiXel Processing Pipeline Display Peripherals A high-performance pixel processor capable of 1

pixel/clock performance for combined operations, such

as color-space conversion, alpha blending,

gamma-mapping, and rotation. The PXP is enhanced

with features specifically for gray scale applications. In

addition, the PXP supports traditional pixel/frame

processing paths for still-image and video processing

applications, allowing it to interface with the integrated

EPD.

RAM

128 KB

Internal RAM

Secure/non-secure RAM

Boot ROM

Internal Memory

Internal RAM, which is accessed through OCRAM

memory controller.

RAM

16 KB

Secured Internal

Memory

Secure/non-secure Internal RAM, interfaced through

the CAAM.

ROM

96KB

Internal Memory

Supports secure and regular Boot Modes. Includes read

protection on 4K region for content protection.

ROMCP

ROM Controller with

Patch

Data Path

ROM Controller with ROM Patch support

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

The SDMA is multi-channel flexible DMA engine. It

helps in maximizing system performance by off-loading

the various cores in dynamic data routing. It has the

following features:

SDMA

Smart Direct Memory

Access

System Control

Peripherals

• Powered by a 16-bit Instruction-Set micro-RISC

engine

• Multi-channel DMA supporting up to 32 time-division

multiplexed DMA channels

• 48 events with total flexibility to trigger any

combination of channels

• Memory accesses including linear, FIFO, and 2D

addressing

• Shared peripherals between Arm and SDMA

• Very fast Context-Switching with 2-level priority

based preemptive multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers

(increment, decrement, and no address changes on

source and destination address)

• DMA ports can handle unit-directional and

bi-directional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers

• Support of byte-swapping and CRC calculations

• Library of Scripts and API is available

SJC

System JTAG Controller

System Control

Peripherals

The SJC provides JTAG interface, which complies with

JTAG TAP standards, to internal logic. The i.MX

6Solo/6DualLite processors use JTAG port for

production, testing, and system debugging. In addition,

the SJC provides BSR (Boundary Scan Register)

standard support, which complies with IEEE1149.1 and

IEEE1149.6 standards.

The JTAG port must be accessible during platform initial

laboratory bring-up, for manufacturing tests and

troubleshooting, as well as for software debugging by

authorized entities. The i.MX 6Solo/6DualLite SJC

incorporates three security modes for protecting against

unauthorized accesses. Modes are selected through

eFUSE configuration.

SNVS

SPDIF

Secure Non-Volatile

Storage

Security

Secure Non-Volatile Storage, including Secure Real

Time Clock, Security State Machine, Master Key

Control, and Violation/Tamper Detection and reporting.

Sony Philips Digital

Interconnect Format

Multimedia

Peripherals

A standard audio file transfer format, developed jointly

by the Sony and Phillips corporations. Has Transmitter

and Receiver functionality.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

17

Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

I2S/SSI/AC97 Interface

Subsystem

Brief Description

SSI-1

SSI-2

SSI-3

Connectivity

Peripherals

The SSI is a full-duplex synchronous interface, which is

used on the AP to provide connectivity with off-chip

audio peripherals. The SSI supports a wide variety of

protocols (SSI normal, SSI network, I2S, and AC-97), bit

depths (up to 24 bits per word), and clock / frame sync

options.

The SSI has two pairs of 8x24 FIFOs and hardware

support for an external DMA controller in order to

minimize its impact on system performance. The

second pair of FIFOs provides hardware interleaving of

a second audio stream that reduces CPU overhead in

use cases where two time slots are being used

simultaneously.

TEMPMON

Temperature Monitor

System Control

Peripherals

The Temperature sensor IP is used for detecting die

temperature. The temperature read out does not reflect

case or ambient temperature. It reflects the temperature

in proximity of the sensor location on the die.

Temperature distribution may not be uniformly

distributed, therefore the read out value may not be the

reflection of the temperature value of the entire die.

TZASC

Trust-Zone Address

Space Controller

Security

The TZASC (TZC-380 by Arm) provides security

address region control functions required for intended

application. It is used on the path to the DRAM

controller.

UART-1

UART-2

UART-3

UART-4

UART-5

UART Interface

Connectivity

Peripherals

Each of the UARTv2 modules support the following

serial data transmit/receive protocols and

configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 5 Mbps.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx

supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USBOH3

USB 2.0 High Speed

OTG and 3x HS Hosts

Connectivity

Peripherals

USBOH3 contains:

• One high-speed OTG module with integrated HS

USB PHY

• One high-speed Host module with integrated HS

USB PHY

• Two identical high-speed Host modules connected to

HSIC USB ports.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

i.MX 6Solo/6DualLite specific SoC characteristics:

All four MMC/SD/SDIO controller IPs are identical and

are based on the uSDHC IP. They are:

• Conforms to the SD Host Controller Standard

Specification version 3.0.

uSDHC-1

uSDHC-2

uSDHC-3

uSDHC-4

SD/MMC and SDXC

Enhanced Multi-Media

Card / Secure Digital Host

Controller

Connectivity

Peripherals

• Fully compliant with MMC command/response sets

and Physical Layer as defined in the Multimedia Card

System Specification, v4.2/4.3/4.4/4.41 including

high-capacity (size > 2 GB) cards HC MMC.

• Fully compliant with SD command/response sets and

Physical Layer as defined in the SD Memory Card

Specifications, v3.0 including high-capacity SDHC

cards up to 32 GB and SDXC cards up to 2 TB.

• Fully compliant with SDIO command/response sets

and interrupt/read-wait mode as defined in the SDIO

Card Specification, Part E1, v3.0

All four ports support:

• 1-bit or 4-bit transfer mode specifications for SD and

SDIO cards up to UHS-I SDR104 mode (104 MB/s

max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for

MMC cards up to 52 MHz in both SDR and DDR

modes (104 MB/s max)

However, the SoC level integration and I/O muxing logic

restrict the functionality to the following:

• Instances #1 and #2 are primarily intended to serve

as external slots or interfaces to on-board SDIO

devices. These ports are equipped with “Card

detection” and “Write Protection” pads and do not

support hardware reset.

• Instances #3 and #4 are primarily intended to serve

interfaces to embedded MMC memory or interfaces

to on-board SDIO devices. These ports do not have

“Card detection” and “Write Protection” pads and do

support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There

are two completely independent I/O power domains

for Ports #1 and #2 in four bit configuration (SD

interface). Port #3 is placed in his own independent

power domain and port #4 shares power domain with

some other interfaces.

VDOA

VPU

VDOA

Multimedia

Peripherals

Video Data Order Adapter (VDOA): used to re-order

video data from the “tiled” order used by the VPU to the

conventional raster-scan order needed by the IPU.

Video Processing Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU), which

covers many SD-level and HD-level video decoders and

SD-level encoders as a multi-standard video codec

engine as well as several important video processing,

such as rotation and mirroring.

See the i.MX 6Solo/6DualLite Reference Manual

(IMX6SDLRM) for complete list of VPU’s

decoding/encoding capabilities.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Modules List

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

WDOG-1

Watch Dog

Timer Peripherals

The Watch Dog Timer supports two comparison points

during each counting period. Each of the comparison

points is configurable to evoke an interrupt to the Arm

core, and a second point evokes an external event on

the WDOG line.

WDOG-2

(TZ)

Watch Dog (TrustZone)

Timer Peripherals

The TrustZone Watchdog (TZ WDOG) timer module

protects against TrustZone starvation by providing a

method of escaping normal mode and forcing a switch

to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such

situation is undesirable as it can compromise the

system’s security. Once the TZ WDOG module is

activated, it must be serviced by TZ software on a

periodic basis. If servicing does not take place, the timer

times out. Upon a time-out, the TZ WDOG asserts a TZ

mapped interrupt that forces switching to the TZ mode.

If it is still not served, the TZ WDOG asserts a security

violation signal to the CSU. The TZ WDOG module

cannot be programmed or deactivated by a normal

mode SW.

WEIM

NOR-Flash /PSRAM

interface

Connectivity

Peripherals

The WEIM NOR-FLASH / PSRAM provides:

• Support 16-bit (in muxed IO mode only) PSRAM

memories (sync and async operating modes), at slow

frequency

• Support 16-bit (in muxed IO mode only) NOR-Flash

memories, at slow frequency

• Multiple chip selects

XTALOSC

Crystal Oscillator I/F

Clocks, Resets, and The XTALOSC module enables connectivity to external

Power Control

crystal oscillator device. In a typical application

use-case, it is used for 24 MHz oscillator to provide USB

required frequency.

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Modules List

3.1

Special Signal Considerations

Table 3 lists special signal considerations for the i.MX 6Solo/6DualLite processors. The signal names are

listed in alphabetical order.

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are provided in the i.MX 6Solo/6DualLite Reference Manual

(IMX6SDLRM).

Table 3. Special Signal Considerations

Signal Name

Remarks

CLK1_P/CLK1_N

CLK2_P/CLK2_N

Two general purpose differential high speed clock Input/outputs are provided.

Any or both of them could be used:

• To feed external reference clock to the PLLs and further to the modules inside SoC, for example

as alternate reference clock for PCIe, Video/Audio interfaces, etc.

• To output internal SoC clock to be used outside the SoC as either reference clock or as a

functional clock for peripherals, for example it could be used as an output of the PCIe master

clock (root complex use)

See the i.MX 6Solo/6DualLite reference manual for details on the respective clock trees.

The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the

maximum frequency range supported is 0...600 MHz.

Alternatively one may use single ended signal to drive CLKx_P input. In this case corresponding

CLKx_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.

Termination should be provided in case of high frequency signals.

See LVDS pad electrical specification for further details.

After initialization, the CLKx inputs/outputs could be disabled (if not used). If unused any or both of

the CLKx_N/P pairs may remain unconnected.

XTALOSC_RTC_XTALI/ If the user wishes to configure XTALOSC_RTC_XTALI and RTC_XTALO as an RTC oscillator, a

RTC_XTALO

32.768 kHz crystal, (≤100 kΩ ESR, 10 pF load) should be connected between

XTALOSC_RTC_XTALI and RTC_XTALO. Remember that the capacitors implemented on either

side of the crystal are about twice the crystal load capacitor. To hit the exact oscillation frequency,

the board capacitors need to be reduced to account for board and chip parasitics. The integrated

oscillation amplifier is self biasing, but relatively weak. Care must be taken to limit parasitic leakage

from XTALOSC_RTC_XTALI and RTC_XTALO to either power or ground (>100 MΩ). This will

debias the amplifier and cause a reduction of startup margin. Typically XTALOSC_RTC_XTALI and

RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into XTALOSC_RTC_XTALI the RTC_XTALO

pin must remain unconnected or driven with a complimentary signal. The logic level of this forcing

clock must not exceed VDD_SNVS_CAP level and the frequency must be <100 kHz under typical

conditions.

XTALI/XTALO

• A 24.0 MHz crystal should be connected between XTALI and XTALO level and the frequency

should be <32 MHz under typical conditions. See the Hardware Development Guide

(IMX6DQ6SDLHDG), Design Checklist chapter, for details on crystal selection.

• NXP BSP (board support package) software requires 24 MHz on XTALI/XTALO.

• The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this

case, XTALI must be directly driven by the external oscillator and XTALO remains unconnected.

• The XTALI signal level must swing from ~0.8 x NVCC_PLL_OUT to ~0.2 V. If this clock is used

as a reference for USB and PCIe, then there are strict frequency tolerance and jitter

requirements. See OSC24M chapter and relevant interface specifications chapters for details.

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Modules List

Table 3. Special Signal Considerations (continued)

Remarks

Signal Name

DRAM_VREF

When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the

NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use a

1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt each resistor with a

closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the 2% DDR_VREF tolerance (per the DDR3 specification) is

maintained when four DDR3 ICs plus the i.MX 6Solo/6DualLite are drawing current on the resistor

divider.

It is recommended to use regulated power supply for “big” memory configurations (more that eight

devices).

ZQPAD

DRAM calibration resistor 240 Ω 1% used as reference during DRAM output buffer driver

calibration should be connected between this pad and GND.

NVCC_LVDS_2P5

The DDR pre-drivers share the NVCC_LVDS_2P5 ball with the LVDS interface. This ball can be

shorted to VDD_HIGH_CAP on the circuit board.

VDD_FA

FA_ANA

These signals are reserved for NXP manufacturing use only. User must tie both connections to

GND.

GPANAIO

Analog output for NXP use only. This output must remain unconnected.

JTAG_nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated

if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

must be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX 6Solo/6DualLite reference manual. Both

names refer to the same signal. JTAG_MOD must be externally connected to GND for normal

operation. Termination to GND through an external pull-down resistor (such as 1 kΩ) is allowed.

JTAG_MOD set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard.

JTAG_MOD set to low configures the JTAG interface for common SW debug adding all the system

TAPs to the chain.

NC

These signals are not functional and must remain unconnected by the user.

This cold reset negative logic input resets all modules and logic in the IC.

SRC_POR_B

ONOFF

In normal mode may be connected to ON/OFF button (De-bouncing provided at this input).

Internally this pad is pulled up. Short connection to GND in OFF mode causes internal power

management state machine to change state to ON. In ON mode short connection to GND

generates interrupt (intended to SW controllable power down). Long above ~5s connection to GND

causes “forced” OFF.

TEST_MODE

PCIE_REXT

TEST_MODE is for NXP factory use. This signal is internally connected to an on-chip pull-down

device. This signal must either be tied to Vss or remain unconnected.

The impedance calibration process requires connection of reference resistor 200 Ω 1% precision

resistor on PCIE_REXT pad to ground.

CSI_REXT

DSI_REXT

MIPI CSI PHY reference resistor. Use 6.04 KΩ 1% resistor connected between this pad and GND

MIPI DSI PHY reference resistor. Use 6.04 KΩ 1% resistor connected between this pad and GND

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Electrical Characteristics

Table 4. JTAG Controller Interface Summary

I/O Type

JTAG

On-Chip Termination

JTAG_TCK

JTAG_TMS

JTAG_TDI

Input

47 kΩ pull-up

Keeper

Input

JTAG_TDO

JTAG_TRSTB

JTAG_MOD

3-state output

Input

47 kΩ pull-up

100 kΩ pull-up

Input

3.2

Recommended Connections for Unused Analog Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused analog

interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of

Applications Processors (IMX6DQ6SDLHDG).

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX 6Solo/6DualLite

processors.

4.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 5 for a quick reference

to the individual tables and sections.

Table 5. i.MX 6Solo/6DualLite Chip-Level Conditions

For these characteristics, …

Absolute Maximum Ratings

Topic appears …

on page 24

on page 25

on page 26

on page 28

on page 29

on page 30

on page 32

BGA Case 2240 Package Thermal Resistance

Operating Ranges

External Clock Sources

Maximum Supply Currents

Low Power Mode Supply Currents

USB PHY Current Consumption

PCIe 2.0 Power Consumption

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Electrical Characteristics

4.1.1

Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 6 may cause permanent damage to

the device. These are stress ratings only. Functional operation of the device

at these or any other conditions beyond those indicated under

“recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device

reliability.

Table 6 shows the absolute maximum operating ratings.

Table 6. Absolute Maximum Ratings

Parameter Description

Symbol

Min

Max

Unit

Core supply input voltage (LDO enabled)

VDD_ARM_IN

VDD_SOC_IN

-0.3

1.6

V

Core supply input voltage (LDO bypass)

Core supply output voltage (LDO enabled)

VDD_ARM_IN

VDD_SOC_IN

-0.3

1.4

V

VDD_ARM_CAP

VDD_SOC_CAP

VDD_PU_CAP

VDD_HIGH_IN supply voltage (LDO enabled)

VDD_HIGH_CAP supply output voltage

DDR I/O supply voltage

VDD_HIGH_IN

VDD_HIGH_CAP

NVCC_DRAM

-0.3

-0.4

3.7

2.85

1.975 ^{(See note 1)}

V

GPIO I/O supply voltage

NVCC_CSI

NVCC_EIM

NVCC_ENET

NVCC_GPIO

NVCC_LCD

NVCC_NAND

NVCC_SD

-0.5

3.7

V

NVCC_JTAG

HDMI and PCIe high PHY VPH supply voltage

HDMI and PCIe low PHY VP supply voltage

LVDS and MIPI I/O supply voltage (2.5V supply)

HDMI_VPH

PCIE_VPH

-0.3

2.85

1.4

V

HDMI_VP

PCIE_VP

NVCC_LVDS_2P5

NVCC_MIPI

2.85

PCIe PHY supply voltage

RGMII I/O supply voltage

PCIE_VPTX

NVCC_RGMII

VDD_SNVS_IN

-0.3

-0.5

-0.3

1.4

2.725

3.4

V

SNVS IN supply voltage

(Secure Non-Volatile Storage and Real Time Clock)

USB I/O supply voltage

USB_H1_DN

USB_H1_DP

USB_OTG_DN

USB_OTG_DP

USB_OTG_CHD_B

-0.3

3.73

V

USB VBUS supply voltage

USB_H1_VBUS

USB_OTG_VBUS

—

5.35

V

V_in/V_outinput/output voltage range (non-DDR pins)

V_in/V_out

-0.5

OVDD+0.3 ^{(See note 2)}

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Electrical Characteristics

Table 6. Absolute Maximum Ratings (continued)

Parameter Description

Symbol

Min

Max

Unit

V_in/V_outinput/output voltage range (DDR pins)

ESD immunity (HBM)

V_in/V_out

V_{esd_HBM}

V_{esd_CDM}

T_storage

-0.5 OVDD+0.4 ^{(See notes 1 & 2)}

V

—

2000

500

ESD immunity (CDM)

V

Storage temperature range

-40

150

°C

1

The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the

allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V.

2

OVDD is the I/O supply voltage.

4.1.2

Thermal Resistance

NOTE

Per JEDEC JESD51-2, the intent of thermal resistance measurements is

solely for a thermal performance comparison of one package to another in a

standardized environment. This methodology is not meant to and will not

predict the performance of a package in an application-specific

environment.

4.1.2.1

BGA Case 2240 Package Thermal Resistance

Table 7 displays the thermal resistance data.

Table 7. Thermal Resistance Data

Rating

Test Conditions

Symbol

Value

Unit

Junction to Ambient¹

Single-layer board (1s); natural convection²

Four-layer board (2s2p); natural convection²

R_θJA

38

23

^oC/W

Junction to Ambient¹

Single-layer board (1s); airflow 200 ft/min^2,3

Four-layer board (2s2p); airflow 200 ft/min^2,3

R_θJA

30

20

^oC/W

Junction to Board^1,4

—

R_θJB

R_θJC

Ψ_JT

14

6

^oC/W

Junction to Case^1,5

Junction to Package Top^1,6

Natural convection

2

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2

Per JEDEC JESD51-2 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified

package.

3

4

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5

6

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

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Electrical Characteristics

4.1.3

Operating Ranges

Table 8 provides the operating ranges of the i.MX 6Solo/6DualLite processors. For details on the chip's

power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 6Solo/6DualLite Reference

Manual (IMX6SDLRM).

Table 8. Operating Ranges

Parameter

Description

Symbol

Min

Typ

Max¹

Unit

Comment²

Run mode: LDO

enabled

VDD_ARM_IN

1.350³

—

1.5

V

LDO Output Set Point (VDD_ARM_CAP) =

1.225 V minimum for operation up to 996MHz.

1.275³

1.25³

—

1.5

V

LDO Output Set Point (VDD_ARM_CAP) =

1.150 V minimum for operation up to 792MHz.

LDO Output Set Point (VDD_ARM_CAP) =

1.125 V minimum for operation up to 396MHz.

VDD_SOC_IN

VDD_ARM_IN

1.275^3,4

VPU ≤ 328 MHz, VDD_SOC and VDD_PU

LDO outputs (VDD_SOC_CAP and

VDD_PU_CAP) = 1.225 V⁶maximum and

1.15 V minimum.

Run mode: LDO

bypassed

1.250

1.150

1.125

1.150⁵

0.9

—

1.3

V

LDO bypassed for operation up to 996 MHz

LDO bypassed for operation up to 792 MHz

LDO bypassed for operation up to 396 MHz

LDO bypassed for operation VPU ≤ 328 MHz

1.3

1.21⁶

VDD_SOC_IN

VDD_ARM_IN

Standby/DSM mode

1.3

Refer to Table 11, "Stop Mode Current and

Power Consumption," on page 30.

VDD_SOC_IN

VDD_HIGH_IN

0.9

2.8

—

1.225⁶

3.3

V

—

VDD_HIGH internal

regulator

Must match the range of voltages that the

rechargeable backup battery supports.

Backupbatterysupply

range

VDD_SNVS_IN⁷

2.9

—

3.3

V

Should be supplied from the same supply as

VDD_HIGH_IN if the system does not require

keeping real time and other data on OFF

state.

USB supply voltages

USB_OTG_VBUS

USB_H1_VBUS

NVCC_DRAM

4.4

—

5.25

1.3

V

—

DDR I/O supply

voltage

1.14

1.425

1.283

1.15

1.2

1.5

1.35

—

LPDDR2

1.575

1.45

2.625

DDR3

DDR3L

Supply for RGMII I/O

power group⁸

NVCC_RGMII

1.15 V–1.30 V in HSIC 1.2 V mode

1.43 V–1.58 V in RGMII 1.5 V mode

1.70 V–1.90 V in RGMII 1.8 V mode

2.25 V–2.625 V in RGMII 2.5 V mode

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Electrical Characteristics

Table 8. Operating Ranges (continued)

Parameter

Description

Symbol

Min

Typ

Max¹

Unit

Comment²

GPIO supply

NVCC_CSI,

NVCC_EIM,

NVCC_ENET,

NVCC_GPIO,

NVCC_LCD,

NVCC_NANDF,

NVCC_SD1,

NVCC_SD2,

NVCC_SD3,

NVCC_JTAG

1.65

1.8,

2.8,

3.3

3.6

V

—

voltages⁸

NVCC_LVDS_2P5⁹

NVCC_MIPI

2.25

2.5

2.75

V

—

HDMI supply voltages

PCIe supply voltages

HDMI_VP

HDMI_VPH

PCIE_VP

0.99

2.25

1.1

2.5

1.1

2.5

1.1

—

1.3

V

—

2.75

1.21

2.75

1.21

105

1.023

2.325

1.023

-20

PCIE_VPH

PCIE_VPTX

T

Junction temperature

Extended commercial

^oC See i.MX 6Solo/6DualLite Product Lifetime

Usage Estimates Application Note, AN4725,

for information on product lifetime for this

processor.

J

T

J

Junction temperature

Standard commercial

0

—

95

^oC See i.MX 6Solo/6DualLite Product Lifetime

Usage Estimates Application Note, AN4725,

for information on product lifetime for this

processor.

1

2

Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set

point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.

See the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG) for bypass capacitors requirements for each of the *_CAP supply outputs.

3

4

VDD_ARM_IN and VDD_SOC_IN must be 125 mV higher than the LDO Output Set Point for correct regulator supply voltage.

In LDO enabled mode, the internal LDO output set points must be configured such that the:

• VDD_ARM LDO output set point does not exceed the VDD_SOC LDO output set point by more than 100 mV.

• VDD_SOC LDO output set point is equal to the VDD_PU LDO output set point.

The VDD_ARM LDO output set point can be lower than the VDD_SOC LDO output set point, however, the minimum output set

points shown in this table must be maintained.

5

6

In LDO bypassed mode, the external power supply must ensure that VDD_ARM_IN does not exceed VDD_SOC_IN by more

than 100 mV. The VDD_ARM_IN supply voltage can be lower than the VDD_SOC_IN supply voltage. The minimum voltages

shown in this table must be maintained.

When using VDD_SOC_CAP to supply the PCIE_VP and PCIE_VPTX, the maximum setting is 1.175V. If VDD_SOC_CAP

requires setting to 1.2V or higher, the PCIE_VP and PCIE_VPTX must use an external supply to guarantee not to exceed the

1.21V maximum operating voltage.

7

8

9

While setting VDD_SNVS_IN voltage with respect to Charging Currents and RTC, refer to Hardware Development Guide for i.MX

6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).

All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or not

and associated IO pins need to have a pull-up or pull-down resistor applied to limit any non-connected gate current.

This supply also powers the pre-drivers of the DDR IO pins, hence, it must be always provided, even when LVDS is not used.

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Electrical Characteristics

4.1.4

External Clock Sources

Each i.MX 6Solo/6DualLite processor has two external input system clocks: a low frequency

(RTC_XTALI) and a high frequency (XTALI).

The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,

power-down real time clock operation, and slow system and watch-dog counters. The clock input can be

connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is

an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.

NOTE

The internal RTC oscillator does not provide an accurate frequency and is

affected by process, voltage, and temperature variations. NXP strongly

recommends using an external crystal as the RTC_XTALI reference. If the

internal oscillator is used instead, careful consideration must be given to the

timing implications on all of the SoC modules dependent on this clock.

The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either external oscillator or a crystal using internal

oscillator amplifier.

Table 9 shows the interface frequency requirements.

Table 9. External Input Clock Frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator^1,2

XTALI Oscillator^2,4

f_ckil

f_xtal

—

32.768³/32.0

24

—

kHz

MHz

1

External oscillator or a crystal with internal oscillator amplifier.

2

The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware

Development Guide for i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).

3

4

Recommended nominal frequency 32.768 kHz.

External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

The typical values shown in Table 9 are required for use with NXP BSPs to ensure precise time keeping

and USB operation. For XTALOSC_RTC_XTALI operation, two clock sources are available.

•

On-chip 40 kHz ring oscillator—this clock source has the following characteristics:

— Approximately 25 µA more Idd than crystal oscillator

— Approximately 50ꢀ tolerance

— No external component required

— Starts up quicker than 32 kHz crystal oscillator

External crystal oscillator with on-chip support circuit:

— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit

switches over to the crystal oscillator automatically.

— Higher accuracy than ring oscillator

— If no external crystal is present, then the ring oscillator is used

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NXP Semiconductors

Electrical Characteristics

The choice of a clock source must be based on real-time clock use and precision timeout.

4.1.5

Maximum Supply Currents

The Power Virus numbers shown in Table 10 represent a use case designed specifically to show the

maximum current consumption possible. All cores are running at the defined maximum frequency and are

limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a

very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention

was to specifically show the worst case power consumption.

The NXP power management IC, MMPF0100xxxx, which is targeted for the i.MX 6 series processor

family, supports the power consumption shown in Table 10, however a robust thermal design is required

for the increased system power dissipation.

See the i.MX 6Solo/6DualLite Power Consumption Measurement Application Note (AN4576) for more

details on typical power consumption under various use case definitions.

Table 10. Maximum Supply Currents

Power Line

VDD_ARM_IN

Conditions

Max Current

Unit

i.MX 6DualLite: 996 MHz Arm clock based on

Power Virus operation

2200

mA

i.MX 6Solo: 996 MHz Arm clock based on Power

Virus operation

1320

mA

VDD_SOC_IN

VDD_HIGH_IN

VDD_SNVS_IN

996 MHz Arm clock

1260

125¹

275²

25³

mA

μA

—

USB_OTG_VBUS/

mA

USB_H1_VBUS (LDO 3P0)

Primary Interface (IO) Supplies

4

NVCC_DRAM

NVCC_ENET

NVCC_LCD

NVCC_GPIO

NVCC_CSI

—

N=10

N=29

N=24

N=20

N=53

N=6

Use maximum IO equation⁵

NVCC_EIM

NVCC_JTAG

NVCC_RGMII

NVCC_SD1

NVCC_SD2

NVCC_SD3

NVCC_NANDF

N=6

N=11

N=26

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Electrical Characteristics

Table 10. Maximum Supply Currents (continued)

Conditions

Power Line

Max Current

Unit

NVCC_LVDS2P5⁶

—

NVCC_LVDS2P5 is connected to

VDD_HIGH_CAP at the board level.

VDD_HIGH_CAP is capable of

handing the current required by

NVCC_LVDS2P5.

—

MISC

DDR_VREF

—

1

mA

1

The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the

VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or

HDMI and PCIe VPH supplies).

2

Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown in Table 10. The maximum

VDD_SNVS_IN current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal

to 00, or use of the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of

sourcing that current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.

3

4

This is the maximum current per active USB physical interface.

The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power calculators

are typically available from the memory vendors. They take in account factors, such as signal termination. See the i.MX

6Solo/DualLite Power Consumption Measurement Application Note (AN4576) for examples of DRAM power consumption

during specific use case scenarios.

5

General equation for estimated, maximum power consumption of an IO power supply:

Imax = N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

6

NVCC_LVDS2P5 is supplied by VDD_HIGH_CAP (by external connection) so the maximum supply current is included in the

current shown for VDD_HIGH_IN. The maximum supply current for NVCC_LVDS2P5 has not been characterized separately.

4.1.6

Low Power Mode Supply Currents

Table 11 shows the current core consumption (not including I/O) of i.MX 6Solo/6DualLite processors in

selected low power modes.

Table 11. Stop Mode Current and Power Consumption

Mode

Test Conditions

Supply

Typical¹

Units

WAIT

• Arm, SoC, and PU LDOs are set to 1.225

• HIGH LDO set to 2.5 V

• Clocks are gated.

• DDR is in self refresh.

• PLLs are active in bypass (24MHz)

• Supply Voltages remain ON

VDD_ARM_IN (1.4V)

VDD_SOC_IN (1.4V)

VDD_HIGH_IN (3.0V)

Total

4.5

23

mA

13.5

79

mW

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Table 11. Stop Mode Current and Power Consumption (continued)

Mode

STOP_ON

Test Conditions

• Arm LDO set to 0.9V

• SoC and PU LDOs set to 1.225 V

• HIGH LDO set to 2.5 V

• PLLs disabled

Supply

Typical¹

Units

VDD_ARM_IN (1.4V)

VDD_SOC_IN (1.4V)

VDD_HIGH_IN (3.0V)

Total

4

22

mA

mW

mA

8.5

61.9

4

• DDR is in self refresh.

STOP_OFF

STANDBY

• Arm LDO set to 0.9V

• SoC LDO set to: 1.225 V

• PU LDO is power gated

• HIGH LDO set to 2.5 V

• PLLs disabled

VDD_ARM_IN (1.4V)

VDD_SOC_IN (1.4V)

VDD_HIGH_IN (3.0V)

Total

13.5

7.5

47

mW

mA

• DDR is in self refresh

• Arm and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5V

• PLLs are disabled

• Low Voltage

• Well Bias ON

VDD_ARM_IN (0.9V)

VDD_SOC_IN (0.9V)

VDD_HIGH_IN (3.0V)

Total

0.1

5

19.6

mW

• Crystal oscillator is enabled

Deep Sleep Mode

(DSM)

• Arm and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5V

• PLLs are disabled

• Low Voltage

• Well Bias ON

VDD_ARM_IN (0.9V)

VDD_SOC_IN (0.9V)

VDD_HIGH_IN (3.0V)

Total

0.1

2

mA

0.5

3.4

mW

• Crystal oscillator and bandgap are disabled

SNVS only

• VDD_SNVS_IN powered

• All other supplies off

• SRTC running

VDD_SNVS_IN (2.8V)

Total

41

μA

115

mW

1

The typical values shown here are for information only and are not guaranteed. These values are average values measured

on a typical wafer at 25°C.

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4.1.7

USB PHY Current Consumption

4.1.7.1

Power Down Mode

In power down mode, everything is powered down, including the USB_VBUS valid detectors in typical

condition. Table 12 shows the USB interface current consumption in power down mode.

Table 12. USB PHY Current Consumption in Power Down Mode

VDD_USB_CAP (3.0 V)

VDD_HIGH_CAP (2.5 V)

NVCC_PLL_OUT (1.1 V)

Current

5.1 μA

1.7 μA

<0.5 μA

NOTE

The currents on the VDD_HIGH_CAP and VDD_USB_CAP were

identified to be the voltage divider circuits in the USB-specific level shifters.

4.1.8

PCIe 2.0 Power Consumption

Table 13 provides PCIe PHY currents under certain Tx operating modes.

Table 13. PCIe PHY Current Drain

Mode

Test Conditions

Supply

Max Current

Unit

P0: Normal Operation

5G Operations

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

40

20

mA

21

2.5G Operations

5G Operations

2.5G Operations

—

27

20

P0s: Low Recovery Time

Latency, Power Saving State

30

mA

2.4

18

20

2.4

18

P1: Longer Recovery Time

Latency, Lower Power State

12

mA

2.4

12

Power Down

—

1.3

0.18

0.36

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4.1.9

HDMI Power Consumption

Table 14 provides HDMI PHY currents for both Active 3D Tx with LFSR15 data and power-down modes.

Table 14. HDMI PHY Current Drain

Mode

Test Conditions

Supply

Max Current

Unit

Active

Bit rate 251.75 Mbps

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

14

4.1

14

mA

μA

Bit rate 279.27 Mbps

Bit rate 742.5 Mbps

Bit rate 1.485 Gbps

Bit rate 2.275 Gbps

Bit rate 2.97 Gbps

—

4.2

17

7.5

17

12

16

17

19

22

Power-down

49

1100

μA

4.2

Power Supplies Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the processor (worst-case scenario)

4.2.1

Power-Up Sequence

The restrictions that follow must be observed:

•

VDD_SNVS_IN supply must be turned on before any other power supply or be connected

(shorted) with VDD_HIGH_IN supply.

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

The SRC_POR_B signal controls the processor POR and must be immediately asserted at

power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP

supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no

restrictions.

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NOTE

Ensure that there is no back voltage (leakage) from any supply on the board

towards the 3.3 V supply (for example, from the external components that

use both the 1.8 V and 3.3 V supplies).

NOTE

USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply

sequence and may be powered at any time.

4.2.2

Power-Down Sequence

No special restrictions for i.MX 6Solo/6DualLite IC.

4.2.3

Power Supplies Usage

All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.

This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O

power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package Information

and Contact Assignments.”

NOTE

When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and

PCIE_VPTX supplies must be powered or grounded. The input and output

supplies for the remaining ports (PCIE_REXT, PCIE_RX_N, PCIE_RX_P,

PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is

recommended not to turn the PCIE_VPH supply OFF while the PCIE_VP

supply is ON, as it may lead to excessive power consumption. If boundary

scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must remain

powered.

4.3

Integrated LDO Voltage Regulator Parameters

Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins

named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use

only and should not be used to power any external circuitry. See the i.MX 6Solo/6DualLite Reference

Manual (IMX6SDLRM) for details on the power tree scheme.

NOTE

The *_CAP signals must not be powered externally. These signals are

intended for internal LDO or LDO bypass operation only.

4.3.1

Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)

There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because

of their construction). The advantages of the regulators are to reduce the input supply variation because of

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their input supply ripple rejection and their on-die trimming. This translates into more stable voltage for

the on-chip logics.

These regulators have three basic modes:

•

Bypass. The regulation FET is switched fully on passing the external voltage, to the load unaltered.

The analog part of the regulator is powered down in this state, removing any loss other than the IR

drop through the power grid and FET.

•

Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.

The analog part of the regulator is powered down here limiting the power consumption.

Analog regulation mode. The regulation FET is controlled such that the output voltage of the

regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV

steps.

For additional information, see the i.MX 6Solo/6DualLite reference manual.

4.3.2

Regulators for Analog Modules

LDO_1P1

4.3.2.1

The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 8 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V

to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, LVDS Phy, HDMI

Phy, MIPI Phy, and PLLs. A programmable brown-out detector is included in the regulator that can be used

by the system to determine when the load capability of the regulator is being exceeded to take the necessary

steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.

Active-pull-down can also be enabled for systems requiring this feature.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

For additional information, see the i.MX 6Solo/6DualLite reference manual (IMX6SDLRM).

4.3.2.2

LDO_2P5

The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 8 for minimum and maximum input requirements). Typical Programming Operating Range is

2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB Phy, LVDS Phy,

HDMI Phy, MIPI Phy, E-fuse module, and PLLs. A programmable brown-out detector is included in the

regulator that can be used by the system to determine when the load capability of the regulator is being

exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current

requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this

feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for

applications needing to keep the output voltage alive during low-power modes where the main regulator

driver and its associated global bandgap reference module are disabled. The output of the weak-regulator

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is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V

input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 Ω.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

For additional information, see the i.MX 6Solo/6DualLite reference manual.

4.3.2.3

LDO_USB

The LDO_USB module implements a programmable linear-regulator function from the

USB_OTG_VBUS and USB_H1_VBUS voltages (4.4 V–5.25 V) to produce a nominal 3.0 V output

voltage. A programmable brown-out detector is included in the regulator that can be used by the system to

determine when the load capability of the regulator is being exceeded, to take the necessary steps. This

regulator has a built in power-mux that allows the user to select to run the regulator from either

USB_VBUS supply, when both are present. If only one of the USB_VBUS voltages is present, then, the

regulator automatically selects this supply. Current limit is also included to help the system meet in-rush

current targets.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

For additional information, see the i.MX 6Solo/6DualLite reference manual.

4.4

PLL’s Electrical Characteristics

4.4.1

Audio/Video PLL’s Electrical Parameters

Table 15. Audio/Video PLL’s Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

650 MHz ~1.3 GHz

24 MHz

<11250 reference cycles

4.4.2

528 MHz PLL

Table 16. 528 MHz PLL’s Electrical Parameters

Parameter

Value

Clock output range

528 MHz PLL output

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Table 16. 528 MHz PLL’s Electrical Parameters (continued)

Parameter

Value

Reference clock

Lock time

24 MHz

<11250 reference cycles

4.4.3

4.4.4

4.4.5

Ethernet PLL

Table 17. Ethernet PLL’s Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

500 MHz

24 MHz

<11250 reference cycles

480 MHz PLL

Table 18. 480 MHz PLL’s Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

480 MHz PLL output

24 MHz

<383 reference cycles

MLB PLL

The MediaLB PLL is necessary in the MediaLB 6-Pin implementation to phase align the internal and

external clock edges, effectively tuning out the delay of the differential clock receiver and is also

responsible for generating the higher speed internal clock, when the internal-to-external clock ratio is

not 1:1.

Table 19. MLB PLL’s Electrical Parameters

Parameter

Value

Lock time

<1 ms

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4.4.6

Arm PLL

Table 20. Arm PLL’s Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

650 MHz ~ 1.3 GHz

24 MHz

<2250 reference cycles

4.5

On-Chip Oscillators

OSC24M

4.5.1

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT.

The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight

forward biased-inverter implementation is used.

4.5.2

OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements a low power oscillator. It also implements a power mux such that it can be powered

from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes

power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when

VDD_HIGH_IN is lost.

In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz

clock will automatically switch to the internal ring oscillator.

CAUTION

The internal RTC oscillator does not provide an accurate frequency and is

affected by process, voltage, and temperature variations. NXP strongly

recommends using an external crystal as the RTC_XTALI reference. If the

internal oscillator is used instead, careful consideration must be given to the

timing implications on all of the SoC modules dependent on this clock.

The OSC32k runs from VDD_SNVS_CAP supply, which comes from VDD_HIGH_IN/VDD_SNVS_IN.

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Table 21. OSC32K Main Characteristics

Characteristic

Min

Typ

Max

Comments

Fosc

—

32.768 KHz

—

This frequency is nominal and determined mainly by the crystal selected.

32.0 K will work as well.

Current consumption

—

4 μA

—

The 4 μA is the consumption of the oscillator alone (OSC32k). Total supply

consumption will depend on what the digital portion of the RTC consumes.

The ring oscillator consumes 1 μA when ring oscillator is inactive, 20 μA

when the ring oscillator is running. Another 1.5 μA is drawn from vdd_rtc

in the power_detect block. So, the total current is 6.5 μA on vdd_rtc when

the ring oscillator is not running.

Bias resistor

—

14 MΩ

This the integrated bias resistor that sets the amplifier into a high gain

state. Any leakage through the ESD network, external board leakage, or

even a scope probe that is significant relative to this value will debias the

amp. The debiasing will result in low gain, and will impact the circuit's ability

to start up and maintain oscillations.

Crystal Properties

Cload

ESR

—

10 pF

—

Usually crystals can be purchased tuned for different Cloads. This Cload

value is typically 1/2 of the capacitances realized on the PCB on either side

of the quartz. A higher Cload will decrease oscillation margin, but

increases current oscillating through the crystal.

50 kΩ

100 kΩ Equivalent series resistance of the crystal. Choosing a crystal with a higher

value will decrease the oscillating margin.

4.6

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2 and DDR3 modes

LVDS I/O

MLB I/O

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output.

ovdd

pmos (Rpu)

Voh min

1

Vol max

or

0

pdat

pad

Predriver

nmos (Rpd)

ovss

Figure 4. Circuit for Parameters Voh and Vol for I/O Cells

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4.6.1

XTALI and RTC_XTALI (Clock Inputs) DC Parameters

Table 22 shows the DC parameters for the clock inputs.

Table 22. XTALI and RTC_XTALI DC Parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

XTALI high-level DC input voltage

XTALI low-level DC input voltage

RTC_XTALI high-level DC input voltage

RTC_XTALI low-level DC input voltage

Input capacitance

Vih

Vil

—

0.8 x NVCC_PLL

—

5

NVCC_PLL

0.2V

1.1¹

V

—

0

0.8

0

Vih

Vil

—

V

0.2

V

C_IN

Simulated data

—

pF

μA

XTALI input leakage current at startup I_{XTALI_STARTUP}

Power-on startup for

0.15msec with a driven

24 MHz clock at 1.1 V.²

—

600

DC input current

I_{XTALI_DC}

—

2.5

μA

1

2

This voltage specification must not be exceeded and, as such, is an absolute maximum specification.

This current draw is present even if an external clock source directly drives XTALI. The 24 MHz oscillator cell is powered from

NVCC_PLL_OUT.

NOTE

The Vil and Vih specifications only apply when an external clock source is

used. If a crystal is used, Vil and Vih do not apply.

4.6.2

General Purpose I/O (GPIO) DC Parameters

Table 23 shows DC parameters for GPIO pads. The parameters in Table 23 are guaranteed per the

operating ranges in Table 8, unless otherwise noted.

Table 23. GPIO DC Parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage¹

V_OH

Ioh= -0.1mA (DSE=001,010)

Ioh= -1mA

OVDD - 0.15

—

V

(DSE=011,100,101,110,111)

Low-level output voltage¹

VOL

Iol= 0.1mA (DSE=001,010)

Iol= 1mA

—

0.15

V

(DSE=011,100,101,110,111)

High-Level input voltage^1,2

Low-Level input voltage^1,2

VIH

VIL

—

0.7 × OVDD

OVDD

V

0

0.3 × OVDD

V

Input Hysteresis (OVDD= 1.8V) VHYS_LowVDD

OVDD=1.8V

OVDD=3.3V

—

250

—

mV

Input Hysteresis (OVDD=3.3V

Schmitt trigger VT+^2,3

VHYS_HighVDD

VTH+

250

0.5 × OVDD

Schmitt trigger VT-^2,3

VTH-

—

0.5 × OVDD mV

Pull-up resistor (22_kΩ PU)

Pull-up resistor (47_kΩ PU)

RPU_22K

RPU_47K

Vin=0V

Vin=OVDD

Vin=0V

212

1

uA

100

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Table 23. GPIO DC Parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Pull-up resistor (47_kΩ PU)

Pull-up resistor (100_kΩ PU)

Pull-down resistor (100_kΩ PD)

Input current (no PU/PD)

RPU_47K

RPU_100K

RPD_100K

IIN

Vin=OVDD

Vin=0V

—

1

48

1

uA

kΩ

Vin=OVDD

—

Vin=OVDD

—

48

1

Vin=0V

—

VI = 0, VI = OVDD

VI = 0.3 × OVDD, VI = 0.7 × OVDD

-1

1

Keeper Circuit Resistance

R_Keeper

105

175

1

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2

3

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.6.3

DDR I/O DC Parameters

The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.

4.6.3.1 LPDDR2 Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller

(MMDC).

1

Table 24. LPDDR2 I/O DC Electrical Parameters

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage

Low-level output voltage

VOH

VOL

Ioh= -0.1mA

0.9 × OVDD

—

0.1 × OVDD

0.51 × OVDD

OVDD

Vref-0.13

Note²

V

Iol= 0.1mA

Input Reference Voltage

Vref

—

0.49 × OVDD

Vref+0.13

OVSS

0.26

DC High-Level input voltage

DC Low-Level input voltage

Differential Input Logic High

Differential Input Logic Low

Pull-up/Pull-down Impedance Mismatch

240 Ω unit calibration resolution

Keeper Circuit Resistance

Vih_DC

Vil_DC

Vih_diff

Vil_diff

Mmpupd

Rres

—

Note³

-15

-0.26

—

15

%

Ω

—

10

Rkeep

Iin

110

175

kΩ

μA

Input current (no pull-up/down)

VI = 0, VI = OVDD

-2.5

2.5

1

2

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

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3

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

4.6.3.2

DDR3/DDR3L Mode I/O DC Parameters

The parameters in Table 25 are guaranteed per the operating ranges in Table 8, unless otherwise noted. For

details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller

(MMDC).

1

Table 25. DDR3/DDR3L I/O DC Electrical Characteristics

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage

VOH

Ioh= -0.1mA

Voh (for DSE=001)

0.8 × OVDD²

—

V

Low-level output voltage

High-level output voltage

Low-level output voltage

VOL

VOH

VOL

Iol= 0.1mA

Vol (for DSE=001)

—

0.8 × OVDD

—

0.2 × OVDD

—

V

Ioh= -1mA

Voh (for all except DSE=001)

Iol= 1mA

Vol (for all except DSE=001)

0.2 × OVDD

Input Reference Voltage

DC High-Level input voltage

DC Low-Level input voltage

Differential Input Logic High

Differential Input Logic Low

Termination Voltage

Vref

Vih_DC

Vil_DC

Vih_diff

Vil_diff

Vtt

—

0.49 × OVDD 0.51 × OVDD

V

—

Vref³+0.1

OVDD

Vref-0.1

See Note⁴

-0.2

—

OVSS

V

—

0.2

V

—

See Note³

V

Vtt tracking OVDD/2

0.49 × OVDD 0.51 × OVDD

V

Pull-up/Pull-down Impedance Mismatch Mmpupd

—

-10

—

10

%

Ω

240 Ω unit calibration resolution

Keeper Circuit Resistance

Rres

Rkeep

Iin

—

105

-2.9

165

2.9

kΩ

μA

Input current (no pull-up/down)

VI = 0,VI = OVDD

1

2

3

4

Note that the JEDEC DDR3 specification (JESD79_3D) supersedes any specification in this document.

OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L)

Vref – DDR3/DDR3L external reference voltage.

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

4.6.4

RGMII I/O 2.5V I/O DC Electrical Parameters

The RGMII interface complies with the RGMII standard version 1.3. The parameters in Table 26 are

guaranteed per the operating ranges in Table 8, unless otherwise noted.

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Table 26. RGMII I/O 1.8V and 2.5V mode DC Electrical Characteristics

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level Output Voltage¹

V_OH

Ioh= -0.1mA (DSE=001,010)

OVDD-0.15

—

V

Ioh= -1mA (DSE=011,100,101,110,111)

Low-level Output Voltage¹

V_OL

Iol= 0.1mA (DSE=001,010)

—

0.15

V

Iol= 1mA (DSE=011,100,101,110,111)

Input Reference Voltage

High-Level Input Voltage^{2 3}

Low-Level Input Voltage^{2 3}

V_ref

V_IH

—

0.49 × OVDD 0.51 × OVDD

V

—

0.7 × OVDD

OVDD

0.3 × OVDD

—

V_IL

0

V

Input Hysteresis

(OVDD=1.8V)

V_{HYS_HighVDD}

OVDD=1.8V

250

mV

Input Hysteresis

(OVDD=2.5V)

V_{HYS_HighVDD}

OVDD=2.5V

250

—

mV

+

Schmitt Trigger VT+^{3 4}

Schmitt Trigger VT-^{3 4}

V_TH

—

0.5 × OVDD

—

mV

μA

-

V_TH

—

-—

—

0.5 × OVDD

Pull-up Resistor (22 kΩ PU)

Pull-up Resistor (47 kΩ PU)

Pull-up Resistor (100 kΩ PU)

R_{PU_22K}

R_{PU_47K}

R_{PU_100K}

R_{PD_100K}

Vin=0V

212

1

Vin=OVDD

Vin=0V

100

1

Vin=OVDD

Vin=0V

48

1

Vin=OVDD

Pull-down Resistor (100 kΩ

48

PD)

Pull-down Resistor (100 kΩ

R_{PD_100K}

Vin=0V

—

1

μA

PD)

Keeper Circuit Resistance

R_keep

I_in

105

-2.9

165

2.9

kΩ

μA

Input Current (no

pull-up/down)

VI = 0, VI = OVDD

1

Input Mode Selection "SW_PAD_CTL_GRP_DDR_TYPE_RGMII"='10' (1.8V Mode)

"SW_PAD_CTL_GRP_DDR_TYPE_RGMII"='11' (2.5V Mode).

2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6

V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

3

4

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, V_ILor V_IH. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled (register

IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0).

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4.6.5

LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 27 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.

Table 27. LVDS I/O DC Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Differential Voltage

Output High Voltage

Output Low Voltage

Offset Voltage

VOD

VOH

VOL

VOS

Rload-100 Ω Diff

IOH = 0 mA

IOL = 0 mA

—

250

1.25

0.9

350

1.375

1.025

1.2

450

1.6

mV

V

1.25

1.375

V

1.125

V

4.6.6

MLB I/O DC Parameters

The MLB interface complies with Analog Interface of 6-pin differential Media Local Bus specification

version 4.1. See 6-pin differential MLB specification v4.1, “MediaLB 6-pin interface Electrical

Characteristics” for details.

NOTE

The MLB 6-pin interface does not support speed mode 8192 fs.

Table 28 shows the Media Local Bus (MLB) I/O DC parameters.

Table 28. MLB I/O DC Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Unit

Output Differential Voltage

Output High Voltage

Output Low Voltage

VOD

VOH

VOL

Rload-50Ω Diff

300

1.25

0.75

1

500

1.75

1.25

1.5

mV

V

Common-mode output voltage

((Vpadp*+Vpadn*)/2)

Vocm

V

Differential output impedance

Zo

—

1.6

—

kΩ

4.7

I/O AC Parameters

This section includes the AC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes

LVDS I/O

MLB I/O

The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 5 and

Figure 6.

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From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 5. Load Circuit for Output

OVDD

80%

20%

0 V

20%

tr

Output (at pad)

tf

Figure 6. Output Transition Time Waveform

4.7.1

General Purpose I/O AC Parameters

The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 29 and Table 30,

respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the

IOMUXC control registers.

Table 29. General Purpose I/O AC Parameters 1.8 V Mode

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, DSE=111)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.72/2.79

1.51/1.54

—

Output Pad Transition Times, rise/fall

(High Drive, DSE=101)

tr, tf

trm

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.20/3.36

1.96/2.07

—

ns

Output Pad Transition Times, rise/fall

(Medium Drive, DSE=100)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.64/3.88

2.27/2.53

Output Pad Transition Times, rise/fall

(Low Drive. DSE=011)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

4.32/4.50

3.16/3.17

—

Input Transition Times¹

—

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

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Parameter

Table 30. General Purpose I/O AC Parameters 3.3 V Mode

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, DSE=101)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

1.70/1.79

1.06/1.15

—

Output Pad Transition Times, rise/fall

(High Drive, DSE=011)

tr, tf

trm

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.35/2.43

1.74/1.77

—

ns

Output Pad Transition Times, rise/fall

(Medium Drive, DSE=010)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.13/3.29

2.46/2.60

Output Pad Transition Times, rise/fall

(Low Drive. DSE=001)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

5.14/5.57

4.77/5.15

—

Input Transition Times¹

—

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

4.7.2

DDR I/O AC Parameters

Table 31 shows the AC parameters for DDR I/O operating in LPDDR2 mode. For details on supported

DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller (MMDC).

1

Table 31. DDR I/O LPDDR2 Mode AC Parameters

Parameter

AC input logic high

Symbol

Test Condition

Min

Max

Unit

Vih(ac)

Vil(ac)

—

Vref + 0.22

OVDD

Vref - 0.22

—

V

AC input logic low

—

0

0.44

—

AC differential input high voltage²

AC differential input low voltage

Input AC differential cross point voltage³

Over/undershoot peak

Vidh(ac)

Vidl(ac)

Vix(ac)

Vpeak

—

V

—

Relative to Vref

—

0.44

V

-0.12

—

0.12

V

0.35

V

Over/undershoot area (above OVDD

or below OVSS)

Varea

400 MHz

—

0.3

V-ns

tsr

50 Ω to Vref.

5 pF load.

Drive impedance = 40 Ω

30%

1.5

1

3.5

2.5

0.1

Single output slew rate, measured between

Vol(ac) and Voh(ac)

V/ns

ns

50 Ω to Vref.

5pF load.Drive

impedance = 60 Ω

30%

Skew between pad rise/fall asymmetry + skew

caused by SSN

t_SKD

clk = 400 MHz

—

1

2

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp

is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

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3

The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Table 32 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.

1

Table 32. DDR I/O DDR3/DDR3L Mode AC Parameters

Parameter

AC input logic high

Symbol

Test Condition

Min

Typ

Max

Unit

Vih(ac)

Vil(ac)

Vid(ac)

Vix(ac)

Vpeak

Varea

—

Vref + 0.175

—

OVDD

Vref - 0.175

—

V

AC input logic low

—

0

0.35

AC differential input voltage²

Input AC differential cross point voltage^{3, 4}

Over/undershoot peak

—

Relative to Vref

—

V

Vref - 0.15

—

Vref + 0.15

0.4

V

Over/undershoot area (above OVDD

or below OVSS)

400 MHz

—

0.5

V-ns

Single output slew rate, measured between

Vol(ac) and Voh(ac)

tsr

Driver impedance = 34 Ω

2.5

—

5

V/ns

ns

Skew between pad rise/fall asymmetry + skew

caused by SSN

t_SKD

clk = 400 MHz

0.1

—

1

2

Note that the JEDEC JESD79_3C specification supersedes any specification in this document.

Vid(ac) specifies the input differential voltage | Vtr-Vcp | required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

3

4

The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Extended range for Vix is only allowed for the clock and when the single-ended clock input signals CK and CK# are:

• monotonic with a single-ended swing VSEL/VSEH of at least VDD/2 250 mV, and

• the differential slew rate of CK - CK# is larger than 3 V/ns

4.7.3

LVDS I/O AC Parameters

The differential output transition time waveform is shown in Figure 7.

padp

V

OH

0V

0V (Differential)

padn

V

OL

80%

0V

VDIFF

VDIFF = {padp} - {padn}

20%

t

THL

TLH

Figure 7. Differential LVDS Driver Transition Time Waveform

Table 33 shows the AC parameters for LVDS I/O.

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Parameter

Table 33. I/O AC Parameters of LVDS Pad

Symbol Test Condition

Min

Typ

Max

Unit

Differential pulse skew¹

Transition Low to High Time²

Transition High to Low Time²

Operating Frequency

t_SKD

—

0.25

0.5

Rload = 100 Ω,

t_TLH

ns

Cload = 2 pF

t_THL

—

0.5

f

—

600

—

800

150

MHz

mV

Offset voltage imbalance

Vos

1

t_SKD= | t_PHLD- t_PLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

2

Measurement levels are 20-80% from output voltage.

4.7.4

MLB I/O AC Parameters

The differential output transition time waveform is shown in Figure 8.

padp

V

OH

0V

0V (Differential)

padn

V

OL

80%

0V

VDIFF

VDIFF = {padp} - {padn}

20%

t

THL

TLH

Figure 8. Differential MLB Driver Transition Time Waveform

A 4-stage pipeline is utilized in the MLB 6-pin implementation in order to facilitate design, maximize

throughput, and allow for reasonable PCB trace lengths. Each cycle is one ipp_clk_in* (internal clock from

MLB PLL) clock period. Cycles 2, 3, and 4 are MLB PHY related. Cycle 2 includes clock-to-output delay

of Signal/Data sampling flip-flop and Transmitter, Cycle 3 includes clock-to-output delay of Signal/Data

clocked receiver, Cycle 4 includes clock-to-output delay of Signal/Data sampling flip-flop.

MLB 6-pin pipeline diagram is shown in Figure 9.

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Figure 9. MLB 6-Pin Pipeline Diagram

Table 34 shows the AC parameters for MLB I/O.

4.8

Output Buffer Impedance Parameters

Table 34. I/O AC Parameters of MLB PHY

Parameter

Symbol Test Condition Min

Typ

Max

Unit

Differential pulse skew¹

t_SKD

t_TLH

—

0.1

1

Rload = 50 Ω

between padp

and padn

Transition Low to High Time²

ns

Transition High to Low Time

t_THL

1

MLB external clock Operating Frequency

MLB PLL clock Operating Frequency

fclk_ext

fclk_pll

—

102.4

307.2

MHz

1

t_SKD= | t_PHLD- t_PLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

2

Measurement levels are 20-80% from output voltage.

This section defines the I/O impedance parameters of the i.MX 6Solo/6DualLite processors for the

following I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2, and DDR3/DDR3L modes

LVDS I/O

MLB I/O

NOTE

GPIO and DDR I/O output driver impedance is measured with “long”

transmission line of impedance Ztl attached to I/O pad and incident wave

launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that

defines specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 10).

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OVDD

PMOS (Rpu)

Ztl Ω, L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

Vin (do)

t,(ns)

0

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

0

Vovdd – Vref1

Vref1

Rpu =

Rpd =

× Ztl

Vref2

Vovdd – Vref2

Figure 10. Impedance Matching Load for Measurement

4.8.1

GPIO Output Buffer Impedance

Table 35 shows the GPIO output buffer impedance (OVDD 1.8 V).

Table 35. GPIO Output Buffer Average Impedance (OVDD 1.8 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

001

010

011

100

101

110

111

260

130

90

60

50

Output Driver

Impedance

Rdrv

Ω

40

33

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Table 36 shows the GPIO output buffer impedance (OVDD 3.3 V).

Table 36. GPIO Output Buffer Average Impedance (OVDD 3.3 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

001

010

011

100

101

110

111

150

75

50

37

30

25

20

Output Driver

Impedance

Rdrv

Ω

4.8.2

DDR I/O Output Buffer Impedance

For details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller

(MMDC).

Table 37 shows DDR I/O output buffer impedance of i.MX 6Solo/6DualLite processors.

Table 37. DDR I/O Output Buffer Impedance

Typical

Test Conditions DSE

NVCC_DRAM=1.5 V

(DDR3)

NVCC_DRAM=1.2 V

(LPDDR2)

Parameter

Symbol

Unit

(Drive Strength)

DDR_SEL=11

DDR_SEL=10

000

001

010

011

100

101

110

111

Hi-Z

240

120

80

60

48

Hi-Z

240

120

80

60

48

Output Driver

Impedance

Rdrv

Ω

40

34

40

34

Note:

1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2. Calibration is done against 240 Ω external reference resistor.

3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.

4.8.3

LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

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4.8.4

MLB I/O Differential Output Impedance

Table 38 shows MLB I/O differential output impedance of the i.MX 6Solo/6DualLite processors.

Table 38. MLB I/O Differential Output Impedance

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Differential Output Impedance

Zo

—

1.6

—

kΩ

4.9

System Modules Timing

This section contains the timing and electrical parameters for the modules in each i.MX 6Solo/6DualLite

processor.

4.9.1

Reset Timings Parameters

Figure 11 shows the reset timing and Table 39 lists the timing parameters.

SRC_POR_B

(Input)

CC1

Figure 11. Reset Timing Diagram

Table 39. Reset Timing Parameters

ID

Parameter

Min Max

Unit

CC1

Duration of SRC_POR_B to be qualified as valid.

1

—

XTALOSC_RTC_XTALI cycle

4.9.2

WDOG Reset Timing Parameters

Figure 12 shows the WDOG reset timing and Table 40 lists the timing parameters.

WDOG1_B

(Output)

CC3

Figure 12. WDOG1_B Timing Diagram

Table 40. WDOG1_B Timing Parameters

ID

Parameter

Duration of WDOG1_B Assertion

Min

Max

Unit

CC3

1

—

XTALOSC_RTC_XTALI cycle

NOTE

XTALOSC_RTC_XTALI is approximately 32 kHz.

XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs.

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NOTE

WDOG1_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the

IOMUXC chapter of the i.MX 6Solo/6DualLite Reference Manual

(IMX6SDLRM).

4.9.3

External Interface Module (EIM)

The following subsections provide information on the EIM. Maximum operating frequency for EIM data

transfer is 104 MHz. Two system clocks are used with the EIM:

•

ACLK_EIM_SLOW_CLK_ROOT is used to clock the EIM module.

The maximum frequency for CLK_EIM_SLOW_CLK_ROOT is 132 MHz.

•

ACLK_EXSC is also used when the EIM is in synchronous mode.

The maximum frequency for ACLK_EXSC is 104 MHz.

Timing parameters in this section that are given as a function of register settings.

4.9.3.1 EIM Interface Pads Allocation

EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.

Table 41 provides EIM interface pads allocation in different modes.

1

Table 41. EIM Internal Module Multiplexing

Multiplexed

Non Multiplexed Address/Data Mode

Address/Data mode

Setup

8 Bit

16 Bit

32 Bit

16 Bit

32 Bit

MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 1, MUM = 1,

DSZ = 100 DSZ = 101 DSZ = 110 DSZ = 111 DSZ = 001 DSZ = 010 DSZ = 011 DSZ = 001 DSZ = 011

EIM_ADDR

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_DATA

[25:16]

EIM_DATA EIM_AD

[07:00] [07:00]

[25:16]

[09:00]

EIM_DATA EIM_DATA

[07:00],

EIM_EB0_B

—

EIM_DATA

[07:00]

—

EIM_AD

[07:00]

—

EIM_DATA

[15:08],

EIM_EB1_B

EIM_DATA

[15:08]

—

EIM_DATA

[15:08]

—

EIM_DATA EIM_AD

EIM_AD

[15:08]

EIM_DATA

[23:16],

EIM_EB2_B

—

EIM_DATA

[23:16]

—

EIM_DATA EIM_DATA

[23:16] [23:16]

—

EIM_DATA

[07:00]

EIM_DATA

[31:24],

—

EIM_DATA

[31:24]

EIM_DATA EIM_DATA

[31:24] [31:24]

—

EIM_DATA

[15:08]

EIM_EB3_B

1

For more information on configuration ports mentioned in this table, see the i.MX 6Solo/6DualLite reference manual.

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4.9.3.2

General EIM Timing-Synchronous Mode

Figure 13, Figure 14, and Table 42 specify the timings related to the EIM module. All EIM output control

signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge

according to corresponding assertion/negation control fields.

,

WE2

...

WE3

EIM_BCLK

WE1

WE4

WE6

WE5

WE7

WE9

EIM_ADDRxx

EIM_CSx_B

WE8

WE10

WE12

EIM_WE_B

EIM_OE_B

EIM_EBx_B

WE11

WE13

WE15

WE17

WE14

WE16

EIM_LBA_B

Output Data

Figure 13. EIM Outputs Timing Diagram

EIM_BCLK

WE18

Input Data

WE19

WE20

EIM_WAIT_B

WE21

Figure 14. EIM Inputs Timing Diagram

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Electrical Characteristics

4.9.3.3

Examples of EIM Synchronous Accesses

1

Table 42. EIM Bus Timing Parameters

BCD = 0

BCD = 1

BCD = 2

Max

BCD = 3

ID

Parameter

Min

Max

Min

Max

Min

Max

WE1 EIM_BCLK Cycle

time²

t

—

2 x t

—

3 x t

—

4 x t

—

WE2 EIM_BCLK Low

Level Width

0.4 x t

—

0.8 x t

—

1.2 x t

1.6 x t

—

WE3 EIM_BCLK High

Level Width

WE4 Clock rise to

address valid³

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE5 Clock rise to

address invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE6 Clock rise to

EIM_CSx_B valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE7 Clock rise to

EIM_CSx_B invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE8 Clock rise to

EIM_WE_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE9 Clock rise to

EIM_WE_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE10 Clock rise to

EIM_OE_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE11 Clock rise to

EIM_OE_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE12 Clock rise to

EIM_EBx_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE13 Clock rise to

EIM_EBx_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE14 Clock rise to

EIM_LBA_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE15 Clock rise to

EIM_LBA_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE16 Clock rise to Output -0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

Data Valid 1.25 1.25

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE17 Clock rise to Output 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

Data Invalid

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE18 Input Data setup

time to Clock rise

2

—

4

2

4

2

—

WE19 Input Data hold time

from Clock rise

WE20 EIM_WAIT_B setup

time to Clock rise

WE21 EIM_WAIT_B hold

time from Clock rise

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1

t is the maximum EIM logic (ACLK_EXSC) cycle time. The maximum allowed axi_clk frequency depends on the fixed/non-fixed

latency configuration, whereas the maximum allowed EIM_BCLK frequency is:

—Fixed latency for both read and write is 104 MHz.

—Variable latency for read only is 104 MHz.

—Variable latency for write only is 52 MHz.

In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz.Write BCD = 1 and

104 MHz ACLK_EXSC, will result in a EIM_BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other

buses are impacted which are clocked from this source. See the CCM chapter of the i.MX 6Solo/6DualLite Reference Manual

(IMX6SDLRM) for a detailed clock tree description.

2

EIM_BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is

defined as 50% as signal value.

3

For signal measurements, “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

Figure 15 to Figure 18 provide few examples of basic EIM accesses to external memory devices with the

timing parameters mentioned previously for specific control parameters settings.

EIM_BCLK

WE4

WE6

WE5

WE7

EIM_ADDRxx

Address v1

Last Valid Address

EIM_CSx_B

EIM_WE_B

EIM_LBA_B

WE14

WE10

WE12

WE15

WE18

WE11

WE13

EIM_OE_B

EIM_EBx_B

EIM_DATAxx

D(v1)

WE19

Figure 15. Synchronous Memory Read Access, WSC=1

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EIM_BCLK

WE5

WE4

EIM_ADDRxx

Last Valid Address

Address V1

WE7

WE6

WE8

EIM_CSx_B

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE9

WE14

WE15

WE13

WE12

WE16

EIM_EBx_B

WE17

EIM_DATAxx

D(V1)

Figure 16. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0

EIM_BCLK

WE16

WE17

WE5

WE4

EIM_ADDRxx/

EIM_ADxx

Write Data

Last Valid Address

Address V1

WE6

WE7

WE9

EIM_CSx_B

EIM_WE_B

WE8

WE14

WE15

EIM_LBA_B

EIM_OE_B

WE10

WE11

EIM_EBx_B

Figure 17. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6,ADVA=0, ADVN=1, and

ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the

data bus.

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EIM_BCLK

WE4

Valid Address

WE6

WE5

Address V1

WE19

WE18

EIM_ADDRxx/

EIM_ADxx

Last

Data

EIM_CSx_B

EIM_WE_B

WE7

WE15

WE10

WE14

WE12

EIM_LBA_B

EIM_OE_B

WE11

WE13

EIM_EBx_B

Figure 18. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0

4.9.3.4

General EIM Timing-Asynchronous Mode

Figure 19 through Figure 23, and Table 43 help you determine timing parameters relative to the chip

select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the

timing parameters mentioned above.

Asynchronous read & write access length in cycles may vary from what is shown in Figure 19 through

Figure 22 as RWSC, OEN and CSN is configured differently. See the i.MX 6Solo/6DualLite Reference

Manual (IMX6SDLRM) for the EIM programming model.

end of

access

start of

access

INT_CLK

MAXCSO

EIM_CSx_B

EIM_ADDRxx/

EIM_ADxx

WE31

WE32

Next Address

Last Valid Address

Address V1

EIM_WE_B

EIM_LBA_B

WE39

WE40

WE36

WE38

WE35

WE37

EIM_OE_B

EIM_EBx_B

WE44

MAXCO

EIM_DATAxx[7:0]

D(V1)

WE43

MAXDI

Figure 19. Asynchronous Memory Read Access (RWSC = 5)

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end of

access

start of

access

INT_CLK

MAXCSO

EIM_CSx_B

MAXDI

WE31

EIM_ADDRxx/

EIM_ADxx

D(V1)

Addr. V1

WE32A

WE44

EIM_WE_B

EIM_LBA_B

WE40A

WE39

WE35A

WE37

WE36

WE38

EIM_OE_B

EIM_EBx_B

MAXCO

Figure 20. Asynchronous A/D Muxed Read Access (RWSC = 5)

EIM_CSx_B

EIM_ADDRxx

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE31

Last Valid Address

WE33

WE32

WE34

WE40

Next Address

Address V1

WE39

WE45

WE41

WE46

EIM_EBx_B

WE42

EIM_DATAxx

D(V1)

Figure 21. Asynchronous Memory Write Access

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Electrical Characteristics

EIM_CSx_B

WE41A

WE31

EIM_ADDRxx/

EIM_DATAxx

D(V1)

Addr. V1

WE32A

WE42

WE33

WE39

WE34

EIM_WE_B

WE40A

EIM_LBA_B

EIM_OE_B

WE45

WE46

EIM_EBx_B

Figure 22. Asynchronous A/D Muxed Write Access

EIM_CSx_B

WE31

WE32

EIM_ADDRxx

Next Address

Last Valid Address

Address V1

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE39

WE35

WE37

WE40

WE36

WE38

EIM_EBx_B

WE44

D(V1)

EIM_DATAxx[7:0]

EIM_DTACK_B

WE43

WE48

WE47

Figure 23. DTACK Mode Read Access (DAP=0)

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EIM_CSx_B

WE31

WE32

WE34

WE40

EIM_ADDRxx

EIM_WE_B

Next Address

Last Valid Address

Address V1

WE33

WE39

EIM_LBA_B

EIM_OE_B

EIM_EBx_B

WE45

WE41

WE46

WE42

EIM_DATAxx

D(V1)

WE48

EIM_DTACK_B

WE47

Figure 24. DTACK Mode Write Access (DAP=0)

Table 43. EIM Asynchronous Timing Parameters Table Relative Chip to Select

Determination by

Ref No.

Parameter

Synchronous measured

Min

Max

Unit

parameters¹

WE31

WE32

EIM_CSx_B valid to

Address Valid

WE4 - WE6 - CSA²

WE7 - WE5 - CSN³

—

3 - CSA

3 - CSN

ns

Address Invalid to

EIM_CSx_B invalid

WE32A EIM_CSx_B valid to

(muxed A/D Address Invalid

t⁴+ WE4 - WE7 + (ADVN⁵+

ADVA⁶+ 1 - CSA)

-3 + (ADVN +

ADVA + 1 - CSA)

—

WE33

WE34

WE35

EIM_CSx_B Valid to

EIM_WE_B Valid

WE8 - WE6 + (WEA - WCSA)

WE7 - WE9 + (WEN - WCSN)

WE10 - WE6 + (OEA - RCSA)

WE10 - WE6 + (OEA + RADVN

—

3 + (WEA - WCSA)

3 - (WEN_WCSN)

3 + (OEA - RCSA)

3 + (OEA +

EIM_WE_B Invalid to

EIM_CSx_B Invalid

—

EIM_CSx_B Valid to

EIM_OE_B Valid

WE35A EIM_CSx_B Valid to

(muxed A/D) EIM_OE_B Valid

-3 + (OEA +

+ RADVA + ADH + 1 - RCSA) RADVN+RADVA+ RADVN+RADVA+ADH

ADH+1-RCSA)

+1-RCSA)

WE36

WE37

EIM_OE_B Invalid to

EIM_CSx_B Invalid

WE7 - WE11 + (OEN - RCSN)

WE12 - WE6 + (RBEA - RCSA)

—

3 - (OEN - RCSN)

ns

EIM_CSx_B Valid to

EIM_EBx_B Valid

(Read access)

—

3 + (RBEA - RCSA)

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Table 43. EIM Asynchronous Timing Parameters Table Relative Chip to Select (continued)

Determination by

Synchronous measured

parameters¹

Ref No.

Parameter

Min

Max

Unit

WE38

EIM_EBx_B Invalid to

EIM_CSx_B Invalid (Read

access)

WE7 - WE13 + (RBEN - RCSN)

—

3 - (RBEN- RCSN)

ns

WE39

WE40

EIM_CSx_B Valid to

EIM_LBA_B Valid

WE14 - WE6 + (ADVA - CSA)

WE7 - WE15 - CSN

—

3 + (ADVA - CSA)

3 - CSN

ns

EIM_LBA_B Invalid to

EIM_CSx_B Invalid (ADVL is

asserted)

WE40A EIM_CSx_B Valid to

(muxed A/D) EIM_LBA_B Invalid

WE14 - WE6 + (ADVN + ADVA +

1 - CSA)

-3 + (ADVN + 3 + (ADVN + ADVA + 1 ns

ADVA + 1 - CSA)

- CSA)

WE41

EIM_CSx_B Valid to Output

Data Valid

WE16 - WE6 - WCSA

—

3 - WCSA

ns

WE41A EIM_CSx_B Valid to Output

(muxed A/D) Data Valid

WE16 - WE6 + (WADVN +

WADVA + ADH + 1 - WCSA)

—

3+(WADVN+WADVA ns

+ ADH + 1 - WCSA)

WE42

Output Data Invalid to

EIM_CSx_B Invalid

WE17 - WE7 - CSN

3 - CSN

ns

MAXCO Output maximum delay from

internal driving

10

—

ns

EIM_ADDRxx/control FFs to

chip outputs

MAXCSO Output maximum delay from

CSx internal driving FFs to CSx

out

10

5

—

ns

MAXDI EIM_DATAxx maximum delay

from chip input data to its

internal FF

WE43

Input Data Valid to EIM_CSx_B MAXCO - MAXCSO + MAXDI

Invalid

MAXCO -

MAXCSO +

MAXDI

WE44

WE45

EIM_CSx_B Invalid to Input

Data invalid

0

—

ns

EIM_CSx_B Valid to

EIM_EBx_B Valid (Write

access)

WE12 - WE6 + (WBEA - WCSA)

—

3 + (WBEA - WCSA)

WE46

EIM_EBx_B Invalid to

EIM_CSx_B Invalid (Write

access)

WE7 - WE13 + (WBEN - WCSN)

10

—

-3 + (WBEN - WCSN) ns

MAXDTI MAXIMUM delay from

EIM_DTACK_B to its internal FF

+ 2 cycles for synchronization

—

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Table 43. EIM Asynchronous Timing Parameters Table Relative Chip to Select (continued)

Determination by

Synchronous measured

parameters¹

Ref No.

Parameter

Min

Max

Unit

WE47

EIM_DTACK_B Active to

EIM_CSx_B Invalid

MAXCO - MAXCSO + MAXDTI

MAXCO -

MAXCSO +

MAXDTI

—

ns

WE48

EIM_CSx_B Invalid to

EIM_DTACK_B Invalid

0

—

ns

1

2

3

4

5

6

For more information on configuration parameters mentioned in this table, see the i.MX 6Solo/6DualLite reference manual.

In this table, CSA means WCSA when write operation or RCSA when read operation.

In this table, CSN means WCSN when write operation or RCSN when read operation.

t is ACLK_EIM_SLOW_CLK_ROOT cycle time.

In this table, ADVN means WADVN when write operation or RADVN when read operation.

In this table, ADVA means WADVA when write operation or RADVA when read operation.

4.9.4

Multi-Mode DDR Controller (MMDC)

The Multi-Mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.

4.9.4.1

MMDC Compatibility with JEDEC-compliant SDRAMs

The i.MX 6Solo/6DualLite MMDC supports the following memory types:

•

LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009

DDR3/DDR3L SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008

MMDC operation with the standards stated above is contingent upon the board DDR design adherence to

the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6Quad,

6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

4.9.4.2

MMDC Supported DDR3/DDR3L/LPDDR2 Configurations

Table 44 and Table 45 show the supported DDR3/DDR3L/LPDDR2 configurations.

Table 44. i.MX 6Solo Supported DDR3/DDR3L/LPDDR2 Configurations

Parameter

LPDDR2

DDR3

DDR3L

Clock frequency

Bus width

400 MHz

16/32-bit

Single

2

400 MHz

16/32-bit

Single

2

400 MHz

16/32-bit

Single

2

Channel

Chip selects

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Parameter

Table 45. i.MX 6DualLite Supported DDR3/DDR3L/LPDDR2 Configurations

LPDDR2

DDR3

DDR3L

(Dual channel)

(Single channel)

Clock frequency

Bus width

400 MHz

32-bit per channel

Dual

400 MHz

16/32-bit

Single

2

400 MHz

16/32/64-bit

Single

400 MHz

16/32/64-bit

Single

Channel

Chip selects

2 per channel

2

4.10 General-Purpose Media Interface (GPMI) Timing

The i.MX 6Solo/6DualLite GPMI controller is a flexible interface NAND Flash controller with 8-bit data

width, up to 200 MB/s I/O speed and individual chip select.

It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing

mode separately described in the following subsections.

4.10.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 25 through Figure 28

depicts the relative timing between GPMI signals at the module level for different operations under

asynchronous mode. Table 46 describes the timing parameters (NF1–NF17) that are shown in the figures.

NF2

NF1

.!.$?#,%

NF3

NF4

.!.$?#%ꢀ?"

.!.$?7%?"

NF5

.!.$?!,%

NF6

NF8

Command

NF7

NF9

.!.$?$!4!XX

Figure 25. Command Latch Cycle Timing Diagram

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Electrical Characteristics

NF1

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

.!.$?!,%

NF6

NF8

Address

NF9

NAND_DATAxx

Figure 26. Address Latch Cycle Timing Diagram

NF1

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

NF6

.!.$?!,%

NF8

Data to NF

NF9

.!.$?$!4!XX

Figure 27. Write Data Latch Cycle Timing Diagram

.!.$?#,%

.!.$?#%ꢀ?"

NF14

NF15

NF13

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF16

NF17

Data from NF

.!.$?$!4!XX

Figure 28. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)

.!.$?#,%

.!.$?#%ꢀ?"

NF14

NF13

NF15

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF17

NF16

NAND_DATAxx

Data from NF

Figure 29. Read Data Latch Cycle Timing Diagram (EDO Mode)

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1

Table 46. Asynchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

NF1

NF2

NF3

NF4

NF5

NF6

NF7

NF8

NF9

NAND_CLE setup time

NAND_CLE hold time

NAND_CE0_B setup time

NAND_CE0_B hold time

NAND_WE_B pulse width

NAND_ALE setup time

NAND_ALE hold time

Data setup time

tCLS

tCLH

tCS

(AS + DS) × T - 0.12 [see ^2,3

DH × T - 0.72 [see ²]

]

ns

(AS + DS + 1) × T [see ^3,2

(DH+1) × T - 1 [see ²]

DS × T [see ²]

]

tCH

tWP

tALS

tALH

tDS

(AS + DS) × T - 0.49 [see ^3,2

(DH × T - 0.42 [see ²]

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

]

Data hold time

tDH

NF10 Write cycle time

tWC

tWH

tRR⁴

tRP

NF11 NAND_WE_B hold time

NF12 Ready to NAND_RE_B low

NF13 NAND_RE_B pulse width

NF14 READ cycle time

(AS + 2) × T [see ^3,2

]

—

DS × T [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

tRC

NF15 NAND_RE_B high hold time

NF16 Data setup on read

NF17 Data hold on read

tREH

tDSR

tDHR

—

(DS × T -0.67)/18.38 [see ^5,6

]

0.82/11.83 [see ^5,6

]

—

1

GPMI’s Async Mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

5

6

AS minimum value can be 0, while DS/DH minimum value is 1.

T = GPMI clock period -0.075ns (half of maximum p-p jitter).

NF12 is guaranteed by the design.

Non-EDO mode.

EDO mode, GPMI clock ≈ 100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

In EDO mode (Figure 28), NF16/NF17 are different from the definition in non-EDO mode (Figure 27).

They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical value for them

are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will

sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay

value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX

6Solo/6DualLite reference manual). The typical value of this control register is 0x8 at 50 MT/s EDO mode.

But if the board delay is big enough and cannot be ignored, the delay value should be made larger to

compensate the board delay.

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4.10.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible)

Figure 30 to Figure 32 show the write and read timing of Source Synchronous Mode.

NF19

NF18

.!.$?#%?"

NF23

NAND_CLE

NF26

NF25

NF24

NAND_ALE

NF25 NF26

NAND_WE/RE_B

NF22

NAND_CLK

NAND_DQS

Output enable

NF20

NF21

CMD

ADD

NAND_DATA[7:0]

Output enable

Figure 30. Source Synchronous Mode Command and Address Timing Diagram

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Electrical Characteristics

NF19

NF18

.!.$?#%ꢀ?"

.!.$?#,%

NF23

NF24

NF25

NF26

.!.$?!,%

NAND_WE/RE_B

NF22

.!.$?#,+

.!.$?$13

NF27

.!.$?$13

Output enable

NF29

.!.$?$1;ꢁꢂꢀ=

NF28

.!.$?$1;ꢁꢂꢀ=

Output enable

Figure 31. Source Synchronous Mode Data Write Timing Diagram

NF18

NF19

.!.$?#%?"

.!.$?#,%

NF24

NF23

NF26

NF25

NAND_ALE

NF25

.!.$?7%ꢃ2%

NF25

NF22

NF26

.!.$?#,+

.!.$?$13

/UTPUT ENABLE

.!.$?$!4!;ꢁꢂꢀ=

/UTPUT ENABLE

Figure 32. Source Synchronous Mode Data Read Timing Diagram

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Electrical Characteristics

.!.$?$13

NF30

.!.$?$!4!;ꢁꢂꢀ=

D0

D1

D2

D3

NF30

NF31

Figure 33. NAND_DQS/NAND_DQ Read Valid Window

1

Table 47. Source Synchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

2

NF18 NAND_CE0_B access time

NF19 NAND_CE0_B hold time

tCE

tCH

CE_DELAY × T - 0.79 [see ]

0.5 × tCK - 0.63 [see ²]

0.5 × tCK - 0.05

ns

NF20 Command/address NAND_DATAxx setup time

NF21 Command/address NAND_DATAxx hold time

NF22 clock period

tCAS

tCAH

tCK

0.5 × tCK - 1.23

—

NF23 preamble delay

tPRE

tPOST

tCALS

tCALH

tDQSS

—

PRE_DELAY × T - 0.29 [see ²]

POST_DELAY × T - 0.78 [see ²]

0.5 × tCK - 0.86

NF24 postamble delay

NF25 NAND_CLE and NAND_ALE setup time

NF26 NAND_CLE and NAND_ALE hold time

NF27 NAND_CLK to first NAND_DQS latching transition

NF28 Data write setup

0.5 × tCK - 0.37

T - 0.41 [see ²]

0.25 × tCK - 0.35

NF29 Data write hold

—

0.25 × tCK - 0.85

NF30 NAND_DQS/NAND_DQ read setup skew

—

2.06

1.95

NF31 NAND_DQS/NAND_DQ read hold skew

—

1

2

GPMI’s source synchronous mode output timing can be controlled by the module’s internal registers

GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends

on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.

T = tCK(GPMI clock period) -0.075ns (half of maximum p-p jitter).

For DDR Source sync mode, Figure 33 shows the timing diagram of NAND_DQS/NAND_DATAxx read

valid window. The typical value of tDQSQ is 0.85ns (max) and 1ns (max) for tQHS at 200MB/s. GPMI

will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which

can be provided by an internal DPLL. The delay value can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX

6Solo/6DualLite reference manual). Generally, the typical delay value of this register is equal to 0x7 which

means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay

value should be made larger to compensate the board delay.

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4.10.3 Samsung Toggle Mode AC Timing

4.10.3.1 Command and Address Timing

NOTE

Samsung Toggle Mode command and address timing is the same as ONFI

1.0 compatible Async mode AC timing. See Section 4.10.1, “Asynchronous

Mode AC Timing (ONFI 1.0 Compatible),” for details.

4.10.3.2 Read and Write Timing

DEV?CLK

ꢀ

.!.$?#%X?"

.!.$?#,%

.!.$?!,%

ꢀ

ꢄ

.!.$?7%?"

.!.$?2%?"

.!.$?$13

.&ꢇꢉ

.&ꢇꢈ

ꢀꢅꢆ T#+

.!.$?$!4!;ꢁꢂꢀ=

Figure 34. Samsung Toggle Mode Data Write Timing

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Electrical Characteristics

DEV?CLK

.!.$?#%X?"

.& ꢄꢊ

.!.$?#,%

.!.$?!,%

ꢄ T #+

ꢄ

.&ꢇꢉ

.!.$?7%?"

.!.$?2%?"

ꢄ T #+

.& ꢇꢈ

ꢄ T #+

.!.$?$13

.!.$?$!4!;ꢁꢂꢀ=

Figure 35. Samsung Toggle Mode Data Read Timing

1

Table 48. Samsung Toggle Mode Timing Parameters

Timing

T = GPMI Clock Cycle

Min

ID

Parameter

Symbol

Unit

Max

NF1 NAND_CLE setup time

NF2 NAND_CLE hold time

NF3 NAND_CE0_B setup time

NF4 NAND_CE0_B hold time

NF5 NAND_WE_B pulse width

NF6 NAND_ALE setup time

NF7 NAND_ALE hold time

tCLS

tCLH

tCS

(AS + DS) × T - 0.12 [see ^2,3

DH × T - 0.72 [see ²]

(AS + DS) × T - 0.58 [see ^3,2

DH × T - 1 [see ²]

]

tCH

tWP

tALS

tALH

DS × T [see ²]

(AS + DS) × T - 0.49 [see ^3,2

DH × T - 0.42 [see ²]

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

]

NF8 Command/address NAND_DATAxx setup time tCAS

NF9 Command/address NAND_DATAxx hold time

NF18 NAND_CEx_B access time

NF22 clock period

tCAH

tCE

CE_DELAY × T [see ^4,2

]

—

ns

tCK

—

NF23 preamble delay

tPRE

PRE_DELAY × T [see ^5,2

]

NF24 postamble delay

tPOST POST_DELAY × T +0.43 [see ²]

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1

Table 48. Samsung Toggle Mode Timing Parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

NF28 Data write setup

NF29 Data write hold

tDS⁶

tDH⁶

0.25 × tCK - 0.32

—

ns

0.25 × tCK - 0.79

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

tDQSQ⁷

tQHS⁷

—

3.18

3.27

1

The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

AS minimum value can be 0, while DS/DH minimum value is 1.

T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started

with enough time of ALE/CLE assertion to low level.

5

6

7

PRE_DELAY+1) ≥ (AS+DS).

Shown in Figure 34, Samsung Toggle Mode Data Write Timing diagram.

Shown in Figure 33, NAND_DQS/NAND_DQ Read Valid Window.

For DDR Toggle mode, Figure 33 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid

window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will

sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is

provided by an internal DPLL. The delay value of this register can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX

6Solo/6DualLite reference manual). Generally, the typical delay value is equal to 0x7 which means 1/4

clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value

should be made larger to compensate the board delay.

4.11 External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.11.1 AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.11.2 ECSPI Timing Parameters

This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing

parameters for master and slave modes.

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4.11.2.1 ECSPI Master Mode Timing

Figure 36 depicts the timing of ECSPI in master mode. Table 49 lists the ECSPI master mode timing

characteristics.

ECSPIx_RDY_B

ECSPIx_SS_B

CS10

CS5

CS2

CS6

CS3

CS1

CS4

ECSPIx_SCLK

ECSPIx_MOSI

ECSPIx_MISO

CS2

CS3

CS7

CS9

CS8

Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be

connected between a single master and a single slave.

Figure 36. ECSPI Master Mode Timing Diagram

Table 49. ECSPI Master Mode Timing Parameters

ID

Parameter

Symbol

Min

Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read

ECSPIx_SCLK Cycle Time–Write

t_clk

43

15

—

ns

CS2 ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

t_SW

21.5

7

CS3 ECSPIx_SCLK Rise or Fall¹

t_RISE/FALL

t_CSLH

—

1

ns

CS4 ECSPIx_SS_B pulse width

Half ECSPIx_SCLK period

CS5 ECSPIx_SS_B Lead Time (CS setup time)

CS6 ECSPIx_SS_B Lag Time (CS hold time)

CS7 ECSPIx_MOSI Propagation Delay (C_LOAD= 20 pF)

t_SCS

Half ECSPIx_SCLK period - 4

t_HCS

Half ECSPIx_SCLK period - 2

t_PDmosi

t_Smiso

-1

CS8 ECSPIx_MISO Setup Time

•

18

—

CS9 ECSPIx_MISO Hold Time

t_Hmiso

t_SDRY

0

5

—

ns

CS10 RDY to ECSPIx_SS_B Time²

1

2

See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

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4.11.2.2 ECSPI Slave Mode Timing

Figure 37 depicts the timing of ECSPI in slave mode. Table 50 lists the ECSPI slave mode timing

characteristics.

ECSPIx_SS_B

CS5

CS6

CS2

CS1

CS4

ECSPIx_SCLK

ECSPIx_MISO

CS2

CS9

CS8

CS7

ECSPIx_MOSI

Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be con-

nected between a single master and a single slave.

Figure 37. ECSPI Slave Mode Timing Diagram

Table 50. ECSPI Slave Mode Timing Parameters

ID

Parameter

Symbol

Min

Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read

ECSPIx_SCLK Cycle Time–Write

t_clk

43

15

—

ns

CS2 ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

t_SW

21.5

7

CS4 ECSPIx_SS_B pulse width

t_CSLH

t_SCS

Half ECSPIx_SCLK period

—

19

ns

CS5 ECSPIx_SS_B Lead Time (CS setup time)

CS6 ECSPIx_SS_B Lag Time (CS hold time)

CS7 ECSPIx_MOSI Setup Time

5

4

t_HCS

t_Smosi

t_Hmosi

t_PDmiso

CS8 ECSPIx_MOSI Hold Time

CS9 ECSPIx_MISO Propagation Delay (C_LOAD= 20 pF)

•

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4.11.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 51 shows the interface timing values. The number field in the table refers to timing

signals found in Figure 38 and Figure 39.

Table 51. Enhanced Serial Audio Interface (ESAI) Timing Parameters

No.

Characteristics^1,2

Symbol Expression²Min

Max Condition³Unit

62 Clock cycle⁴

t_SSICC

4 × T

30.0

—

i ck

ns

c

63 Clock high period:

ns

• For internal clock

• For external clock

—

2 × T − 9.0

6

15

—

c

2 × T

c

64 Clock low period:

• For internal clock

• For external clock

ns

—

2 × T − 9.0

6

15

—

c

2 × T

c

65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high

—

17.0

7.0

x ck

i ck a

ns

66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low

—

17.0

7.0

x ck

i ck a

67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)

high⁵

—

19.0

9.0

x ck

i ck a

68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low⁵

69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high

70 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) low

—

19.0

9.0

x ck

i ck a

—

16.0

6.0

x ck

i ck a

—

17.0

7.0

x ck

i ck a

71 Data in setup time before ESAI_RX_CLK (SCK in

synchronous mode) falling edge

—

12.0

19.0

—

x ck

i ck

72 Data in hold time after ESAI_RX_CLK falling edge

—

3.5

9.0

—

x ck

i ck

73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK

falling edge⁵

—

2.0

12.0

—

x ck

i ck a

74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK

falling edge

—

2.0

12.0

—

x ck

i ck a

75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling

edge

—

2.5

8.5

—

x ck

i ck a

78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high

—

18.0

8.0

x ck

i ck

79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low

—

20.0

10.0

x ck

i ck

80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)

high⁵

—

20.0

10.0

x ck

i ck

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Table 51. Enhanced Serial Audio Interface (ESAI) Timing Parameters (continued)

Characteristics^1,2Symbol Expression²Min Max Condition³Unit

No.

81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low⁵

82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high

83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low

—

22.0

12.0

x ck

i ck

ns

—

19.0

9.0

x ck

i ck

—

20.0

10.0

x ck

i ck

84 ESAI_TX_CLK rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

86 ESAI_TX_CLK rising edge to data out valid

—

18.0

13.0

x ck

i ck

87 ESAI_TX_CLK rising edge to data out high impedance ⁶⁷

—

21.0

16.0

x ck

i ck

89 ESAI_TX_FS input (bl, wr) setup time before

ESAI_TX_CLK falling edge⁵

—

2.0

18.0

—

x ck

i ck

90 ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK

falling edge

—

2.0

18.0

—

x ck

i ck

91 ESAI_TX_FS input hold time after ESAI_TX_CLK falling

edge

—

4.0

5.0

—

x ck

i ck

95 ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle

—

2 x T_C

—

15

—

ns

96 ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK

output

18.0

97 ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK

output

—

18.0

—

ns

1

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)

2

3

bl = bit length

wl = word length

wr = word length relative

ESAI_TX_CLK(SCKT pin) = transmit clock

ESAI_RX_CLK(SCKR pin) = receive clock

ESAI_TX_FS(FST pin) = transmit frame sync

ESAI_RX_FS(FSR pin) = receive frame sync

ESAI_TX_HF_CLK(HCKT pin) = transmit high frequency clock

ESAI_RX_HF_CLK(HCKR pin) = receive high frequency clock

4

5

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the

second-to-last bit clock of the first word in the frame.

6

Periodically sampled and not 100% tested.

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62

63

64

ESAI_TX_CLK

(Input/Output)

78

79

ESAI_TX_FS

(Bit)

82

83

Out

ESAI_TX_FS

(Word)

86

84

86

Out

87

First Bit

Last Bit

Data Out

89

91

ESAI_TX_FS

(Bit) In

91

90

ESAI_TX_FS

(Word) In

Figure 38. ESAI Transmitter Timing

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Electrical Characteristics

62

63

64

ESAI_RX_CLK

(Input/Output)

65

66

ESAI_RX_FS

(Bit)

Out

69

70

ESAI_RX_FS

(Word)

Out

72

71

Data In

Last Bit

First Bit

75

73

ESAI_RX_FS

(Bit)

In

74

75

ESAI_RX_FS

(Word)

In

Figure 39. ESAI Receiver Timing

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4.11.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

Timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single

Data Rate) timing, eMMC4.4/4.41 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.

4.11.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 40 depicts the timing of SD/eMMC4.3, and Table 52 lists the SD/eMMC4.3 timing characteristics.

SD4

SD2

SD1

SD5

SDx_CLK

SD3

SD6

Output from uSDHC to card

SDx_DATA[7:0]

SD7

SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 40. SD/eMMC4.3 Timing

Table 52. SD/eMMC4.3 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1 Clock Frequency (Low Speed)

f_PP

0

400

25/50

20/52

400

—

kHz

MHz

kHz

ns

2

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

f_PP

3

f_PP

0

f_OD

t_WL

100

7

SD2 Clock Low Time

SD3 Clock High Time

SD4 Clock Rise Time

SD5 Clock Fall Time

t_WH

t_TLH

t_THL

7

—

ns

—

3

ns

3

ns

uSDHC Output/Card Inputs SDx_CMD, SDx_DATAx (Reference to CLK)

SD6 uSDHC Output Delay t_OD-6.6

3.6

ns

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Table 52. SD/eMMC4.3 Interface Timing Specification (continued)

Parameter Symbols Min

uSDHC Input/Card Outputs SDx_CMD, SDx_DATAx (Reference to CLK)

ID

Max

Unit

SD7 uSDHC Input Setup Time

SD8 uSDHC Input Hold Time⁴

t_ISU

t_IH

2.5

1.5

—

ns

1

2

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

3

4

In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.11.4.2 eMMC4.4/4.41 (Dual Data Rate) AC Timing

Figure 41 depicts the timing of eMMC4.4/4.41. Table 53 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

SD1

SDx_CLK

SD2

Output from eSDHCv3 to card

SDx_DATA[7:0]

......

SD3

SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

Figure 41. eMMC4.4/4.41 Timing

Table 53. eMMC4.4/4.41 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock¹

SD1 Clock Frequency (eMMC4.4/4.41 DDR)

SD1 Clock Frequency (SD3.0 DDR)

f_PP

0

52

50

MHz

uSDHC Output / Card Inputs SDx_CMD, SDx_DATAx (Reference to CLK)

SD2 uSDHC Output Delay t_OD2.8 6.8

uSDHC Input / Card Outputs SDx_CMD, SDx_DATAx (Reference to CLK)

ns

SD3 uSDHC Input Setup Time

t_ISU

t_IH

1.7

1.5

—

ns

SD4 uSDHC Input Hold Time

1

1 Clock duty cycle will be in the range of 47% to 53%.

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Electrical Characteristics

4.11.4.3 SDR50/SDR104 AC Timing

Figure 42 depicts the timing of SDR50/SDR104, and Table 54 lists the SDR50/SDR104 timing

characteristics.

Figure 42. SDR50/SDR104 Timing

Table 54. SDR50/SDR104 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

4.8

—

ns

0.46 × t_CLK

0.54 × t_CLK

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SDx_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4 uSDHC Output Delay t_OD–3

uSDHC Output/Card Inputs SDx_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5 uSDHC Output Delay t_OD–1.6 0.74

uSDHC Input/Card Outputs SDx_CMD, SDx_DATAx in SDR50 (Reference to CLK)

1

ns

SD6 uSDHC Input Setup Time

SD7 uSDHC Input Hold Time

t_ISU

t_IH

2.5

1.5

—

ns

uSDHC Input/Card Outputs SDx_CMD, SDx_DATAx in SDR104 (Reference to CLK)¹

SD8 Card Output Data Window

t_ODW

0.5 × t_CLK

—

ns

¹Data window in SDR100 mode is variable.

4.11.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50

mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are

identical to those shown in Table 23, "GPIO DC Parameters," on page 40.

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4.11.5 Ethernet Controller (ENET) AC Electrical Specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive

at timing specs/constraints for the physical interface.

4.11.5.1 ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

4.11.5.1.1 MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1ꢀ. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET_RX_CLK frequency.

Figure 43 shows MII receive signal timings. Table 55 describes the timing parameters (M1–M4) shown in

the figure.

M3

ENET_RX_CLK (input)

M4

ENET_RX_DATA3,2,1,0

(inputs)

ENET_RX_EN

ENET_RX_ER

M1

M2

Figure 43. MII Receive Signal Timing Diagram

Table 55. MII Receive Signal Timing

ID

Characteristic¹

Min

Max

Unit

M1

M2

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

5

—

ns

ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER hold

5

—

ns

M3

M4

ENET_RX_CLK pulse width high

ENET_RX_CLK pulse width low

35%

65%

ENET_RX_CLK period

¹ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

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4.11.5.1.2 MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER, and ENET_TX_CLK)

The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1ꢀ.

There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed

twice the ENET_TX_CLK frequency.

Figure 44 shows MII transmit signal timings. Table 56 describes the timing parameters (M5–M8) shown

in the figure.

M7

ENET_TX_CLK (input)

M5

M8

ENET_TX_DATA3,2,1,0

(outputs)

ENET_TX_EN

ENET_TX_ER

M6

Figure 44. MII Transmit Signal Timing Diagram

Table 56. MII Transmit Signal Timing

ID

Characteristic¹

Min

Max

Unit

M5

M6

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER invalid

5

—

ns

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER valid

—

20

ns

M7

M8

ENET_TX_CLK pulse width high

ENET_TX_CLK pulse width low

35%

65%

ENET_TX_CLK period

¹ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.11.5.1.3 MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)

Figure 45 shows MII asynchronous input timings. Table 57 describes the timing parameter (M9) shown in

the figure.

ENET_CRS, ENET_COL

M9

Figure 45. MII Async Inputs Timing Diagram

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Table 57. MII Asynchronous Inputs Signal Timing

ID

M9¹

Characteristic

ENET_CRS to ENET_COL minimum pulse width

Min

Max

Unit

1.5

—

ENET_TX_CLK period

¹ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

4.11.5.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 46 shows MII asynchronous input timings. Table 58 describes the timing parameters (M10–M15)

shown in the figure.

M14

M15

ENET_MDC (output)

M10

ENET_MDIO (output)

M11

ENET_MDIO (input)

M12

M13

Figure 46. MII Serial Management Channel Timing Diagram

Table 58. MII Serial Management Channel Timing

ID

M10

Characteristic

Min

Max

Unit

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

0

—

ns

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—

5

ns

M12

M13

M14

M15

ENET_MDIO (input) to ENET_MDC rising edge setup

ENET_MDIO (input) to ENET_MDC rising edge hold

ENET_MDC pulse width high

18

0

—

ns

40%

60%

ENET_MDC period

ENET_MDC pulse width low

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4.11.5.2 RMII Mode Timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz 50 ppm continuous reference

clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include

ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.

Figure 47 shows RMII mode timings. Table 59 describes the timing parameters (M16–M21) shown in the

figure.

M16

M17

ENET_CLK (input)

M18

ENET_TX_DATA (output)

ENET_TX_EN

M19

ENET_RX_EN (input)

ENET_RX_DATA[1:0]

ENET_RX_ER

M20

M21

Figure 47. RMII Mode Signal Timing Diagram

Table 59. RMII Signal Timing

ID

M16

Characteristic

Min

Max

Unit

ENET_CLK pulse width high

ENET_CLK pulse width low

35%

4

65%

—

ENET_CLK period

M17

M18

M19

M20

ENET_CLK period

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

ns

—

15

ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to

ENET_CLK setup

4

—

M21

ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold

2

—

ns

4.11.5.3 Signal Switching Specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver

devices.

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1

Table 60. RGMII Signal Switching Specifications

Symbol

Description

Min

Max

Unit

2

T_cyc

Clock cycle duration

7.2

-500

1

8.8

500

2.6

55

ns

ps

ns

%

3

T_skewT

Data to clock output skew at transmitter

Data to clock input skew at receiver

Duty cycle for Gigabit

T_skewR

Duty_G⁴

Duty_T⁴

Tr/Tf

45

Duty cycle for 10/100T

40

60

%

Rise/fall time (20–80%)

—

0.75

ns

1

The timings assume the following configuration:

DDR_SEL = (11)b

DSE (drive-strength) = (111)b

2

3

For 10 Mbps and 100 Mbps, T_cycwill scale to 400 ns 40 ns and 40 ns 4 ns respectively.

For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional

trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value

is unspecified.

4

Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long

as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned

between.

2'-))?48# ꢋAT TRANSMITTERꢌ

4SKEW4

2'-))?48$N ꢋN ꢍ ꢀ TO ꢈ ꢌ

2'-))?48?#4,

48%.

48%22

4SKEW2

2'-))?48# ꢋAT RECEIVERꢌ

Figure 48. RGMII Transmit Signal Timing Diagram Original

2'-))?28# ꢋAT TRANSMITTERꢌ

4SKEW4

2'-))?28$N ꢋN ꢍ ꢀ TO ꢈ ꢌ

2'-))?28?#4,

28$6

28%22

4SKEW2

2'-))?28# ꢋAT RECEIVERꢌ

Figure 49. RGMII Receive Signal Timing Diagram Original

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Electrical Characteristics

)NTERNAL DELAY

2'-))?28# ꢋSOURCE OF DATAꢌ

2'-))?28$N ꢋN ꢍ ꢀ TO ꢈ ꢌ

4SETUP 4

4 HOLD 4

28$6

28%22

2'-))?28?#4,

4 SETUP 2

4 HOLD 2

2'-))?28# ꢋAT RECEIVERꢌ

Figure 50. RGMII Receive Signal Timing Diagram with Internal Delay

4.11.6 Flexible Controller Area Network (FLEXCAN) AC Electrical

Specifications

The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing

the CAN protocol according to the CAN 2.0B protocol specification. The processor has two CAN modules

available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See

the IOMUXC chapter of the i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM) to see which pins

expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively.

4.11.7 HDMI Module Timing Parameters

4.11.7.1 Latencies and Timing Information

Power-up time (time between TX_PWRON assertion and TX_READY assertion) for the HDMI 3D Tx

PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms.

Power-up time for the HDMI 3D Tx PHY while operating with the fastest input reference clock supported

(340 MHz) is 133 μs.

4.11.7.2 Electrical Characteristics

The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures

illustrate various definitions and measurement conditions specified in the table below.

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Figure 51. Driver Measuring Conditions

Figure 52. Driver Definitions

($-)?48?$!4!;ꢇꢂꢀ=?0

($-)?48?#,+?0

($-)?48?$!4!;ꢇꢂꢀ=?.

($-)?48?#,+?.

Figure 53. Source Termination

Table 61. Electrical Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Operating conditions for HDMI

avddtmds Termination supply voltage

—

3.15

45

3.3

50

3.45

55

V

R_T

Termination resistance

Ω

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Electrical Characteristics

Table 61. Electrical Characteristics (continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

TMDS drivers DC specifications

V_OFF

Single-ended standby voltage RT = 50 Ω

avddtmds 10 mV

—

mV

For measurement conditions

and definitions, see the first

two figures above.

V_SWINGSingle-ended output swing

voltage

400

600

Compliance point TP1 as

defined in the HDMI

specification, version 1.3a,

section 4.2.4.

V_H

Single-ended output high

voltage

For definition, see the second

figure above

If attached sink supports

TMDSCLK < or = 165 MHz

avddtmds 10 mV

mV

Ω

If attached sink supports

TMDSCLK > 165 MHz

avddtmds

- 200 mV

—

avddtmds

+ 10 mV

V_L

Single-ended output low

voltage

For definition, see the second

figure above

If attached sink supports

TMDSCLK < or = 165 MHz

avddtmds

- 600 mV

avddtmds

- 400mV

If attached sink supports

TMDSCLK > 165 MHz

avddtmds

- 700 mV

avddtmds

- 400 mV

R_TERM

Differential source termination

load (inside HDMI 3D Tx PHY)

Although the HDMI 3D Tx

PHY includes differential

source termination, the

—

50

200

user-defined value is set for

each single line (for

illustration, see Figure 53).

Note: R_TERMcan also be

configured to be open and not

present on TMDS channels.

Hot plug detect specifications

HPD^VHHot plug detect high range

VHPD

—

2.0

0

—

5.3

0.8

—

V

Hot plug detect low range

VL

HPD

Hot plug detect input

10

kΩ

Z

impedance

HPD

Hot plug detect time delay

—

100

µs

t

4.11.8 Switching Characteristics

Table 62 describes switching characteristics for the HDMI 3D Tx PHY. Figure 54 to Figure 58 illustrate

various parameters specified in table.

NOTE

All dynamic parameters related to the TMDS line drivers’ performance

imply the use of assembly guidelines.

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P

HDMI_TX_CLK

0

ꢆꢀꢎ

T_#0,

T_#0(

Figure 54. TMDS Clock Signal Definitions

Figure 55. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1

4-$3$!4!0

^ꢄꢃ_ꢇ

6_37).'

AVDDTMDS ꢏ

ꢋTYPꢌ

4-$3$!4!.

T _{3+ ꢋPꢌ}

)NTRAꢏPAIR SKEW

Figure 56. Intra-Pair Skew Definition

0REVIOUS CYCLE ;Nꢏꢄ=

#URRENT CYCLE ;N=

Bꢀ;N= Bꢄ;N=

Bꢐ;Nꢏꢄ=

Bꢊ;Nꢏꢄ=

Bꢁ;Nꢏꢄ=

4-$3$!4!;ꢀ=

4-$3$!4!;ꢄ=

Bꢄ;N=

Bꢀ;N=

4-$3$!4!;ꢇ=

Bꢊ;Nꢏꢄ=

Bꢁ;Nꢏꢄ=

Bꢐ;Nꢏꢄ=

T_{3+ ꢋPPꢌ}

)NTERꢏPAIR SKEW

Figure 57. Inter-Pair Skew Definition

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Electrical Characteristics

Figure 58. TMDS Output Signals Rise and Fall Time Definition

Table 62. Switching Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TMDS Drivers Specifications

—

Maximum serial data rate

TMDSCLK frequency

TMDSCLK period

—

25

—

3.4

340

40

Gbps

MHz

ns

F

On TMDSCLKP/N outputs

TMDSCLK

P

RL = 50 Ω

See Figure 54.

2.94

t

= t

/ P

t

TMDSCLK duty cycle

40

50

60

%

CDC

CPH

TMDSCLK

CDC

RL = 50 Ω

See Figure 54.

t

TMDSCLK high time

TMDSCLK low time

RL = 50 Ω

4

5

6

UI¹

CPH

See Figure 54.

t

RL = 50 Ω

See Figure 54.

CPL

—

TMDSCLK jitter²

RL = 50 Ω

—

0.25

0.15

UI¹

t

Intra-pair (pulse) skew

RL = 50 Ω

See Figure 56.

SK(p)

t

Inter-pair skew

RL = 50 Ω

—

1

UI¹

ps

SK(pp)

See Figure 57.

t_R

Differential output signal rise

time

20–80%

RL = 50 Ω

See Figure 58.

75

0.4 UI

t_F

Differential output signal fall time

20–80%

RL = 50 Ω

See Figure 58.

75

—

0.4 UI

ps

—

Differential signal overshoot

Differential signal undershoot

Referred to 2x V_SWING

—

15

25

%

1

2

UI means TMDS clock unit.

Relative to ideal recovery clock, as specified in the HDMI specification, version 1.4a, section 4.2.3.

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4.11.9 I²C Module Timing Parameters

2

This section describes the timing parameters of the I C module. Figure 59 depicts the timing of I C

2

module, and Table 63 lists the I C module timing characteristics.

IC11

IC9

IC10

I2Cx_SDA

I2Cx_SCL

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

2

Figure 59. I C Bus Timing

2

Table 63. I C Module Timing Parameters

Standard Mode

Fast Mode

ID

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

I2Cx_SCL cycle time

10

4.0

0¹

—

2.5

0.6

0¹

—

µs

Hold time (repeated) START condition

Set-up time for STOP condition

IC3

—

IC4

Data hold time

3.45²

—

0.9²µs

IC5

HIGH Period of I2Cx_SCL Clock

LOW Period of the I2Cx_SCL Clock

Set-up time for a repeated START condition

Data set-up time

4.0

4.7

250

4.7

—

0.6

1.3

0.6

100³

1.3

—

µs

ns

µs

IC6

—

IC7

—

IC8

—

IC9

Bus free time between a STOP and START condition

Rise time of both I2Cx_SDA and I2Cx_SCL signals

Fall time of both I2Cx_SDA and I2Cx_SCL signals

Capacitive load for each bus line (C_b)

—

4

IC10

IC11

IC12

1000

300

400

20 + 0.1C_b300 ns

4

—

20 + 0.1C_b300 ns

—

400 pF

1

A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling

edge of I2Cx_SCL.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.

A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.

If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-bus specification)

before the I2Cx_SCL line is released.

4

C_b= total capacitance of one bus line in pF.

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4.11.10 Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor

and/or to a display device. This support covers all aspects of these activities:

•

Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.

Related image processing and manipulation: sensor image signal processing, display processing,

image conversions, and other related functions.

•

Synchronization and control capabilities, such as avoidance of tearing artifacts.

4.11.10.1 IPU Sensor Interface Signal Mapping

The IPU supports a number of sensor input formats. Table 64 defines the mapping of the Sensor Interface

Pins used for various supported interface formats.

Table 64. Camera Input Signal Cross Reference, Format, and Bits Per Cycle

RGB565

8 bits

2 cycles

RGB565²

8 bits

3 cycles

RGB666³RGB888

YCbCr⁴RGB565⁵YCbCr⁶

YCbCr⁷

16 bits

1 cycle

YCbCr⁸

20 bits

1 cycle

Signal

Name¹

8 bits

16 bits

1 cycle

16 bits

1 cycle

3 cycles

3 cycles 2 cycles

IPUx_CSIx_

DATA00

—

0

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

C[8]

C[9]

Y[0]

Y[1]

Y[2]

IPUx_CSIx_

DATA01

—

0

IPUx_CSIx_

DATA02

—

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

0

IPUx_CSIx_

DATA03

—

IPUx_CSIx_

DATA04

—

B[0]

B[1]

B[2]

B[3]

B[4]

G[0]

G[1]

G[2]

G[3]

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

Y[0]

IPUx_CSIx_

DATA05

—

IPUx_CSIx_

DATA06

—

IPUx_CSIx_

DATA07

—

IPUx_CSIx_

DATA08

—

IPUx_CSIx_

DATA09

—

IPUx_CSIx_

DATA10

—

IPUx_CSIx_

DATA11

—

0

IPUx_CSIx_ B[0], G[3] R[2],G[4],B[2] R/G/B[4]

DATA12

R/G/B[0]

Y/C[0]

Y[0]

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Table 64. Camera Input Signal Cross Reference, Format, and Bits Per Cycle (continued)

RGB565

8 bits

2 cycles

RGB565²

8 bits

3 cycles

RGB666³RGB888

YCbCr⁴RGB565⁵YCbCr⁶

YCbCr⁷

16 bits

1 cycle

YCbCr⁸

20 bits

1 cycle

Signal

Name¹

8 bits

16 bits

1 cycle

16 bits

1 cycle

3 cycles

3 cycles 2 cycles

IPUx_CSIx_ B[1], G[4] R[3],G[5],B[3] R/G/B[5]

DATA13

R/G/B[1]

R/G/B[2]

R/G/B[3]

R/G/B[4]

R/G/B[5]

R/G/B[6]

R/G/B[7]

Y/C[1]

Y/C[2]

Y/C[3]

Y/C[4]

Y/C[5]

Y/C[6]

Y/C[7]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

Y[9]

IPUx_CSIx_ B[2], G[5] R[4],G[0],B[4] R/G/B[0]

DATA14

IPUx_CSIx_

DATA15

B[3], R[0] R[0],G[1],B[0] R/G/B[1]

IPUx_CSIx_

DATA16

B[4], R[1] R[1],G[2],B[1] R/G/B[2]

IPUx_CSIx_ G[0], R[2] R[2],G[3],B[2] R/G/B[3]

DATA17

IPUx_CSIx_ G[1], R[3] R[3],G[4],B[3] R/G/B[4]

DATA18

IPUx_CSIx_ G[2], R[4] R[4],G[5],B[4] R/G/B[5]

DATA19

1

IPUx_CSIx stands for IPUx_CSI0 or IPUx_CSI1.

2

3

4

5

The MSB bits are duplicated on LSB bits implementing color extension.

The two MSB bits are duplicated on LSB bits implementing color extension.

YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).

RGB 16 bits—Supported in two ways: (1) As a “generic data” input, with no on-the-fly processing; (2) With on-the-fly

processing, but only under some restrictions on the control protocol.

6

7

8

YCbCr 16 bits—Supported as a “generic-data” input, with no on-the-fly processing.

YCbCr 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).

YCbCr, 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).

4.11.10.2 Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.11.10.2.1 BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the IPUx_CSIx_VSYNC and IPUx_CSIx_HSYNC signals. The

timing syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is IPUx_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the

data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital

blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding

from the data stream, thus recovering IPUx_CSIx_VSYNC and IPUx_CSIx_HSYNC signals for internal

use. On BT.656 one component per cycle is received over the IPUx_CSIx_DATA_EN bus. On BT.1120

two components per cycle are received over the IPUx_CSIx_DATA_EN bus.

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4.11.10.2.2 Gated Clock Mode

The IPUx_CSIx_VSYNC, IPUx_CSIx_HSYNC, and IPUx_CSIx_PIX_CLK signals are used in this

mode. See Figure 60.

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Figure 60. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on IPUx_CSIx_VSYNC (all the timings correspond to straight polarity

of the corresponding signals). Then IPUx_CSIx_HSYNC goes to high and hold for the entire line. Pixel

clock is valid as long as IPUx_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel

clocks. IPUx_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI

stops receiving data from the stream. For the next line, the IPUx_CSIx_HSYNC timing repeats. For the

next frame, the IPUx_CSIx_VSYNC timing repeats.

4.11.10.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.11.10.2.2, “Gated Clock Mode,”)

except for the IPUx_CSIx_HSYNC signal, which is not used (see Figure 61). All incoming pixel clocks

are valid and cause data to be latched into the input FIFO. The IPUx_CSIx_PIX_CLK signal is inactive

(states low) until valid data is going to be transmitted over the bus.

Start of Frame

n+1th frame

nth frame

IPUx_CSIx_VSYNC

IPUx_CSIx_PIX_CLK

invalid

IPUx_CSIx_DATA_EN[19:0]

1st byte

Figure 61. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 61 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered

IPUx_CSIx_VSYNC; active-high/low IPUx_CSIx_HSYNC; and rising/falling-edge triggered

IPUx_CSIx_PIX_CLK.

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4.11.10.3 Electrical Characteristics

Figure 62 depicts the sensor interface timing. IPUx_CSIx_PIX_CLK signal described here is not

generated by the IPU. Table 65 lists the sensor interface timing characteristics.

IPUx_CSIx_PIX_CLK

(Sensor Output)

1/IP1

IP2

IP3

IPUx_CSIx_DATA_EN,

IPUx_CSIx_VSYNC,

IPUx_CSIx_HSYNC

Figure 62. Sensor Interface Timing Diagram

Table 65. Sensor Interface Timing Characteristics

ID

Parameter

Symbol

Fpck

Min

Max

Unit

MHz

IP1

IP2

IP3

Sensor output (pixel) clock frequency

Data and control setup time

0.01

2

180

—

Tsu

Thd

ns

Data and control holdup time

1

—

4.11.10.4 IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats. Table 66 defines the mapping of the Display

Interface Pins used during various supported video interface formats.

Table 66. Video Signal Cross-Reference

i.MX 6Solo/6DualLite

LCD

RGB/TV Signal Allocation (Example)

Comment^1,2

RGB,

Signal

Name

Port Name

(x=0, 1)

16-bit 18-bit 24 Bit

8-bit

16-bit 20-bit

RGB RGB RGB YCrCb³YCrCb YCrCb

(General)

IPUx_DISPx_DAT00

IPUx_DISPx_DAT01

IPUx_DISPx_DAT02

IPUx_DISPx_DAT03

IPUx_DISPx_DAT04

IPUx_DISPx_DAT05

IPUx_DISPx_DAT06

DAT[0]

DAT[1]

DAT[2]

DAT[3]

DAT[4]

DAT[5]

DAT[6]

B[0]

B[1]

B[2]

B[3]

B[4]

G[0]

G[1]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

G[0]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

Y/C[0]

Y/C[1]

Y/C[2]

Y/C[3]

Y/C[4]

Y/C[5]

Y/C[6]

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

—

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Table 66. Video Signal Cross-Reference (continued)

i.MX 6Solo/6DualLite

LCD

RGB/TV Signal Allocation (Example)

Comment^1,2

RGB,

Port Name

(x=0, 1)

Signal

Name

(General)

16-bit 18-bit 24 Bit

8-bit

16-bit 20-bit

RGB RGB RGB YCrCb³YCrCb YCrCb

IPUx_DISPx_DAT07

IPUx_DISPx_DAT08

IPUx_DISPx_DAT09

IPUx_DISPx_DAT10

IPUx_DISPx_DAT11

IPUx_DISPx_DAT12

IPUx_DISPx_DAT13

IPUx_DISPx_DAT14

IPUx_DISPx_DAT15

IPUx_DISPx_DAT16

IPUx_DISPx_DAT17

IPUx_DISPx_DAT18

IPUx_DISPx_DAT19

IPUx_DISPx_DAT20

IPUx_DISPx_DAT21

IPUx_DISPx_DAT22

IPUx_DISPx_DAT23

DIx_DISP_CLK

DAT[7]

DAT[8]

G[2]

G[3]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

—

G[1]

G[2]

G[3]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

—

B[7]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

G[6]

G[7]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

R[6]

R[7]

PixCLK

Y/C[7]

—

C[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

—

C[7]

C[8]

C[9]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

Y[9]

—

DAT[9]

—

DAT[10]

DAT[11]

DAT[12]

DAT[13]

DAT[14]

DAT[15]

DAT[16]

DAT[17]

DAT[18]

DAT[19]

DAT[20]

DAT[21]

DAT[22]

DAT[23]

—

DIx_PIN1

DIx_PIN2

DIx_PIN3

—

May be required for anti-tearing

HSYNC

VSYNC

—

VSYNC out

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i.MX 6Solo/6DualLite

Table 66. Video Signal Cross-Reference (continued)

LCD

RGB/TV Signal Allocation (Example)

Comment^1,2

RGB,

Port Name

(x=0, 1)

Signal

Name

(General)

16-bit 18-bit 24 Bit

8-bit

16-bit 20-bit

RGB RGB RGB YCrCb³YCrCb YCrCb

DIx_PIN4

DIx_PIN5

DIx_PIN6

DIx_PIN7

DIx_PIN8

DIx_D0_CS

DIx_D1_CS

—

Additional frame/row synchronous

signals with programmable timing

—

Alternate mode of PWM output for

contrast or brightness control

DIx_PIN11

DIx_PIN12

DIx_PIN13

DIx_PIN14

DIx_PIN15

DIx_PIN16

DIx_PIN17

—

Register select signal

Optional RS2

—

DRDY/DV

Data validation/blank, data enable

—

Q

Additional data synchronous

signals with programmable

features/timing

1

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

2

Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:

• A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.

• The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit.

This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line

start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data

during blanking intervals is not supported.

3

NOTE

Table 66 provides information for both the DISP0 and DISP1 ports.

However, DISP1 port has reduced pinout depending on IOMUXC

configuration and therefore may not support all the above configurations.

See the IOMUXC chapter of the i.MX 6Solo/6DualLite Reference Manual

(IMX6SDLRM).

4.11.10.5 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There

are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

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4.11.10.5.1 Synchronous Controls

The synchronous control changes its value as a function of a system or of an external clock. This control

has a permanent period and a permanent wave form.

There are special physical outputs to provide synchronous controls:

•

The IPP_DISP_CLK is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

•

The IPUx_DIx_PIN01—IPUx_DIx_PIN07 are general purpose synchronous pins, that can be used

to provide HSYNC, VSYNC, DRDY or any other independent signal to a display.

The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC)

calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control

starts from the local start point with predefined UP and DOWN values to calculate control’s changing

points with half DI_CLK resolution. A full description of the counters system can be found in the IPU

chapter of the i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM).

4.11.10.5.2 Asynchronous Controls

The asynchronous control is a data-oriented signal that changes its value with an output data according to

additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

•

The IPUx_DIx_D0_CS and IPUx_DIx_D1_CS pins are dedicated to provide chip select signals to

two displays.

•

The IPUx_DIx_PIN11—IPUx_DIx_PIN17 are general purpose asynchronous pins, that can be

used to provide WR. RD, RS or any other data oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals

toggling. When a DI decides to put a new asynchronous data in the bus, a

new internal start (local start point) is generated. The signals generators

calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

4.11.10.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.11.10.6.1 IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

•

IPP_DISP_CLK—Clock to display

HSYNC—Horizontal synchronization

VSYNC—Vertical synchronization

DRDY—Active data

All synchronous display controls are generated on the base of an internally generated “local start point”.

The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.

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The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved

relative to the local start point. The data bus of the synchronous interface is output direction only.

4.11.10.6.2 LCD Interface Functional Description

Figure 63 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,

signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

•

DI_CLK internal DI clock is used for calculation of other controls.

IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).

In active mode, IPP_DISP_CLK runs continuously.

•

HSYNC causes the panel to start a new line. (Usually IPUx_DIx_PIN02 is used as HSYNC.)

VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPUx_DIx_PIN03 is used as VSYNC.)

•

DRDY acts like an output enable signal to the CRT display. This output enables the data to be

shifted onto the display. When disabled, the data is invalid and the trace is off.

(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

VSYNC

HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1 LINE n

HSYNC

DRDY

1

2

3

m-1

m

IPP_DISP_CLK

IPP_DATA

Figure 63. Interface Timing Diagram for TFT (Active Matrix) Panels

4.11.10.6.3 TFT Panel Sync Pulse Timing Diagrams

Figure 64 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All the parameters shown in the figure are programmable. All controls are started by

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corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of

the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.

IP13o

IP7

IP5

IP5o

IP8o

IP8

DI clock

IPP_DISP_ CLK

VSYNC

HSYNC

DRDY

IPP_DATA

Dn

D0

D1

IP9o

IP10

IP9

IP6

Figure 64. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 65 depicts the vertical timing (timing of one frame). All parameters shown in the figure are

programmable.

End of frame

Start of frame

IP13

VSYNC

HSYNC

DRDY

IP11

IP15

IP14

IP12

Figure 65. TFT Panels Timing Diagram—Vertical Sync Pulse

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Table 67 shows timing characteristics of signals presented in Figure 64 and Figure 65.

Table 67. Synchronous Display Interface Timing Characteristics (Pixel Level)

ID

IP5

IP6

Parameter

Display interface clock period Tdicp

Display pixel clock period

Symbol

Value

Description

Unit

(¹)

Display interface clock. IPP_DISP_CLK

ns

Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display,

× Tdicp

DISP_CLK_PER_PIXEL—number of pixel

components in one pixel (1.n). The

DISP_CLK_PER_PIXEL is virtual

parameter to define Display pixel clock

period.

TheDISP_CLK_PER_PIXELisreceivedby

DC/DI one access division to n

components.

IP7

Screen width time

Tsw

(SCREEN_WIDTH)

SCREEN_WIDTH—screen width in,

interface clocks. horizontal blanking

included.

ns

× Tdicp

The SCREEN_WIDTH should be built by

suitable DI’s counter².

IP8

IP9

HSYNC width time

Thsw

Thbi1

(HSYNC_WIDTH)

HSYNC_WIDTH—Hsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter.

ns

Horizontal blank interval 1

^BGXP× Tdicp

BGXP—width of a horizontal blanking

before a first active data in a line (in

interface clocks). The BGXP should be built

by suitable DI’s counter.

IP10 Horizontal blank interval 2

IP12 Screen height

Thbi2

Tsh

(SCREEN_WIDTH -

^{BGXP - FW)}× Tdicp

Width a horizontal blanking after a last

active data in a line (in interface clocks)

FW—with of active line in interface clocks.

The FW should be built by suitable DI’s

counter.

ns

(SCREEN_HEIGHT)

SCREEN_HEIGHT—screenheight in lines ns

with blanking.

The SCREEN_HEIGHT is a distance

between 2 VSYNCs.

× Tsw

The SCREEN_HEIGHT should be built by

suitable DI’s counter.

IP13 VSYNC width

Tvsw

Tvbi1

Tvbi2

Todicp

VSYNC_WIDTH

VSYNC_WIDTH—Vsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter

ns

IP14 Vertical blank interval 1

IP15 Vertical blank interval 2

IP5o Offset of IPP_DISP_CLK

^BGYP× Tsw

BGYP—width of first Vertical

blanking interval in line. The BGYP should

be built by suitable DI’s counter.

(SCREEN_HEIGHT -

^{BGYP - FH)}× Tsw

Width of second Vertical

blanking interval in line. The FH should be

built by suitable DI’s counter.

^DISP_×^CLT^Kd^_ic^Olk^FFSET

DISP_CLK_OFFSET—offset of

IPP_DISP_CLK edges from local start

^{point, in DI_CLK}×2

(0.5 DI_CLK Resolution).

Defined by DISP_CLK counter

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Table 67. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

ID

Parameter

Symbol

Value

Description

Unit

IP13o Offset of VSYNC

IP8o Offset of HSYNC

IP9o Offset of DRDY

Tovs

VSYNC_OFFSET

VSYNC_OFFSET—offset of Vsync edges

from a local start point, when a Vsync

^{should be active, in DI_CLK}×2

(0.5 DI_CLK Resolution). The

VSYNC_OFFSET should be built by

suitable DI’s counter.

ns

× Tdiclk

Tohs

HSYNC_OFFSET

HSYNC_OFFSET—offset of Hsync edges

from a local start point, when a Hsync

^{should be active, in DI_CLK}×2

(0.5 DI_CLK Resolution). The

HSYNC_OFFSET should be built by

suitable DI’s counter.

ns

× Tdiclk

Todrdy

DRDY_OFFSET

DRDY_OFFSET—offset of DRDY edges

from a suitable local start point, when a

corresponding data has been set on the

bus, in DI_CLK×2

× Tdiclk

(0.5 DI_CLK Resolution).

The DRDY_OFFSET should be built by

suitable DI’s counter.

1

Display interface clock period immediate value.









DISP_CLK_PERIOD

----------------------------------------------------

DISP_CLK_PERIOD

DI_CLK_PERIOD

T

×

,

for integer ----------------------------------------------------

diclk

DI_CLK_PERIOD

Tdicp =

DISP_CLK_PERIOD

----------------------------------------------------

DISP_CLK_PERIOD





T

floor

+ 0.5 0.5 ,

for fractional ----------------------------------------------------

 diclk





DI_CLK_PERIOD



DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.

DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency

Display interface clock period average value.

DISP_CLK_PERIOD

----------------------------------------------------

Tdicp = T

×

DI_CLK_PERIOD

diclk

2

DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the

counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by

corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance

between HSYNCs is a SCREEN_WIDTH.

The maximum accuracy of UP/DOWN edge of controls is:

Accuracy = (0.5 × T

) 0.62ns

diclk

The maximum accuracy of UP/DOWN edge of IPP_DATA is:

Accuracy = T

0.62ns

diclk

The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed through the registers.

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Figure 66 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and

DISP_CLK_UP parameters are set through the Register. Table 68 lists the synchronous display interface

timing characteristics.

IP20o IP20

VSYNC

HSYNC

DRDY

other controls

IPP_DISP_CLK

Tdicd

Tdicu

IP18

IPP_DATA

IP16

IP17

IP19

local start point

Figure 66. Synchronous Display Interface Timing Diagram—Access Level

Table 68. Synchronous Display Interface Timing Characteristics (Access Level)

ID

Parameter

Symbol

Min

Typ¹

Max

Unit

IP16

Display interface clock low Tckl

time

Tdicd-Tdicu-1.24

Tdicd²-Tdicu³

Tdicd-Tdicu+1.24

ns

IP17

Display interface clock

high time

Tckh

Tdicp-Tdicd+Tdicu-1.24 Tdicp-Tdicd+Tdicu Tdicp-Tdicd+Tdicu+1.2

ns

IP18

IP19

IP20o

Data setup time

Data holdup time

Tdsu

Tdhd

Tocsu

Tdicd-1.24

Tdicu

—

ns

Tdicp-Tdicd-1.24

Tocsu-1.24

Tdicp-Tdicu

Tocsu

Control signals offset

Tocsu+1.24

times (defines for each pin)

IP20

Control signals setup time Tcsu

to display interface clock

(defines for each pin)

Tdicd-1.24-Tocsu%Tdicp Tdicu

—

ns

¹The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

2

Display interface clock down time

2 × DISP_CLK_DOWN

1

2







-----------------------------------------------------------

Tdicd = -- T

 diclk

× ceil

DI_CLK_PERIOD

3

Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

2 × DISP_CLK_UP

1

2







------------------------------------------------

Tdicu = -- T

 diclk

× ceil

DI_CLK_PERIOD

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4.11.11 LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD

644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.

Table 69. LVDS Display Bridge (LDB) Electrical Specification

Parameter

Symbol

Test Condition

100 Ω Differential load

Min

Max

Units

Differential Voltage Output Voltage

Output Voltage High

V_OD

Voh

250

450

1.6

mV

V

100 Ω differential load (0 V Diff—Output High

Voltage static)

1.25

Output Voltage Low

Offset Static Voltage

Vol

100 Ω differential load (0 V Diff—Output Low

0.9

1.25

V

Voltage static)

V_OS

Two 49.9 Ω resistors in series between N-P

terminal, with output in either Zero or One state, the

voltage measured between the 2 resistors.

1.15

1.375

VOS Differential

V_OSDIFFDifference in V_OSbetween a One and a Zero state

ISA ISB With the output common shorted to GND

-50

-24

247

50

24

mV

mA

mV

Output short circuited to GND

VT Full Load Test

VTLoad 100 Ω Differential load with a 3.74 kΩ load between

454

GND and IO Supply Voltage

4.11.12 MIPI D-PHY Timing Parameters

This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0,

D-PHY specification Rev. 1.0 (for MIPI sensor port x2 lanes) and MIPI DSI Version 1.01, and D-PHY

specification Rev. 1.0 (and also DPI version 2.0, DBI version 2.0, DSC version 1.0a at protocol layer) (for

MIPI display port x2 lanes).

4.11.12.1 Electrical and Timing Information

Table 70. Electrical and Timing Information

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

Input DC Specifications - Apply to DSI_CLK_P/DSI_CLK_N and DSI_DATA_P/DSI_DATA_N inputs

V_I

Input signal voltage range

Input leakage current

Transient voltage range is

limited from -300 mV to

1600 mV

-50

-10

—

1350

10

mV

mA

V_LEAK

VGNDSH(min) = VI =

VGNDSH(max) +

VOH(absmax)

Lane module in LP Receive

Mode

V_GNDSH

Ground Shift

—

-50

—

50

mV

V

V_OH(absmax)

Maximum transient output

voltage level

1.45

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Electrical Characteristics

Symbol

Table 70. Electrical and Timing Information (continued)

Parameters

Test Conditions

Min

Typ

Max

Unit

t_voh(absmax)

Maximum transient time

above VOH(absmax)

—

20

ns

HS Line Drivers DC Specifications

|V_OD

|

HS Transmit Differential

output voltage magnitude

80 Ω<= RL< = 125 Ω

140

—

200

—

270

10

mV

Δ|V_OD

|

Change in Differential output

voltage magnitude between

logic states

80 Ω<= RL< = 125 Ω

V_CMTX

Steady-state common-mode

output voltage.

80 Ω<= RL< = 125 Ω

150

—

200

—

250

5

mV

ΔV_CMTX(1,0)

Changes in steady-state

common-modeoutputvoltage

between logic states

V_OHHS

Z_OS

HS output high voltage

80 Ω<= RL< = 125 Ω

—

360

mV

Single-ended output

impedance.

—

40

50

62.5

Ω

ΔZ_OS

Single-ended output

impedance mismatch.

—

10

%

LP Line Drivers DC Specifications

V_OL

Output low-level SE voltage

—

-50

1.1

50

1.3

—

mV

V

V_OH

Z_OLP

Output high-level SE voltage

1.2

—

Single-ended output

impedance.

110

Ω

ΔZ_OLP(01-10)

Single-ended output

impedance mismatch driving

opposite level

—

20

5

%

ΔZ_OLP(0-11)

Single-ended output

impedance mismatch driving

same level

HS Line Receiver DC Specifications

V_IDTH

Differential input high voltage

threshold

—

-70

—

70

—

mV

V_IDTL

Differential input low voltage

threshold

V_IHHS

Single ended input high

voltage

460

—

V_ILHS

Single ended input low

voltage

-40

70

V_CMRXDC

Input common mode voltage

330

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Electrical Characteristics

Table 70. Electrical and Timing Information (continued)

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

Z_ID

Differential input impedance

—

80

—

125

Ω

LP Line Receiver DC Specifications

V_IL

V_IH

Input low voltage

Input high voltage

Input hysteresis

—

920

25

—

550

—

mV

V_HYST

—

Contention Line Receiver DC Specifications

Input low fault threshold 200

V_ILF

—

450

mV

4.11.12.2 MIPI D-PHY Signaling Levels

The signal levels are different for differential HS mode and single-ended LP mode. Figure 67 shows both

the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below

the LP low-level input threshold such that LP receiver always detects low on HS signals.

V_OH,MAX

LP

V_OL

V_OH,MIN

V_IH

LP

V_IH

LP Threshold

Region

V_IL

V_OHHS

Max V_OD

V_CMTX,MAX

LP V_IL

HS Vout

Range

HS Vcm

Range

V_GNDSH,MA

V_CMTX,MIN

V_OLHS

Min V_OD

X

LP V_OL

GND

V_GNDSH,MIN

HS Differential Signaling

LP Single-ended Signaling

Figure 67. D-PHY Signaling Levels

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Electrical Characteristics

4.11.12.3 MIPI HS Line Driver Characteristics

Ideal Single-Ended High Speed Signals

V_DN

V_CMTX= (V_{DP +}V_DN)/2

V_OD(0)

V_OD(1)

V_DP

Ideal Differential High Speed Signals

V_OD(1)

0V

(Differential)

V_OD(0)

V_OD= V_DP- V_DN

Figure 68. Ideal Single-ended and Resulting Differential HS Signals

4.11.12.4 Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

V_OD/2

Δ

V

_OD(SE HS Signals)

Δ

V_DN

V_{OD (1)}

V_{CM TX}

V_OD(0)

V_DP

V_OD/2

Δ

Static V_CMTX(SE HS Signals)

V_DN

Δ

V_CMTX

V_DP

V_OD(0)

Dynamic V_CMTX(SE HS Signals)

Δ

V_DN

V_{CM TX}

V_DP

Figure 69. Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

4.11.12.5 MIPI D-PHY Switching Characteristics

Table 71. Electrical and Timing Information

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

HS Line Drivers AC Specifications

—

Maximum serial data rate (forward

direction)

On DATAP/N outputs.

80 Ω <= RL <= 125 Ω

80

—

1000

Mbps

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Electrical Characteristics

Table 71. Electrical and Timing Information (continued)

Symbol

Parameters

DDR CLK frequency

Test Conditions

Min

Typ

Max

Unit

F_DDRCLK

P_DDRCLK

t_CDC

On DATAP/N outputs.

40

2

—

500

25

MHz

ns

DDR CLK period

80 Ω<= RL< = 125 Ω

DDR CLK duty cycle

t_CDC= t_CPH/ P_DDRCLK

—

50

1

—

%

t_CPH

DDR CLK high time

—

UI

t_CPL

DDR CLK low time

—

1

—

UI

—

DDR CLK / DATA Jitter

Intra-Pair (Pulse) skew

Data to Clock Skew

—

75

0.075

—

ps pk–pk

UI

t_SKEW[PN]

t_SKEW[TX]

t_r

—

0.350

150

—

0.650

0.3UI

15

UI

Differential output signal rise time

Differential output signal fall time

20% to 80%, RL = 50 Ω

—

ps

t_f

—

ps

ΔV_CMTX(HF)

ΔV_CMTX(LF)

Common level variation above 450 MHz 80 Ω<= RL< = 125 Ω

—

mV_rms

mV_p

Common level variation between 50

MHz and 450 MHz.

80 Ω<= RL< = 125 Ω

—

25

LP Line Drivers AC Specifications

t_{rlp, flp}

t

Single ended output rise/fall time

15% to 85%, C_L<70 pF

30% to 85%, C_L<70 pF

15% to 85%, C_L<70 pF

—

0

—

25

35

ns

t_reo

δV/δt_SR

C_L

Signal slew rate

120

70

mV/ns

pF

Load capacitance

HS Line Receiver AC Specifications

t_SETUP[RX]

t_HOLD[RX]

Data to Clock Receiver Setup time

Clock to Data Receiver Hold time

—

0.15

—

UI

ΔV_CMRX(HF)

Common mode interference beyond

450 MHz

200

mVpp

ΔV_CMRX(LF)

Common mode interference between

50 MHz and 450 MHz.

—

-50

—

50

60

mVpp

pF

C_CM

Common mode termination

LP Line Receiver AC Specifications

e_SPIKE

T_MIN

V_INT

f_INT

Input pulse rejection

—

300

Vps

ns

Minimum pulse response

Pk-to-Pk interference voltage

Interference frequency

50

—

400

—

mV

MHz

450

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Electrical Characteristics

Symbol

Table 71. Electrical and Timing Information (continued)

Parameters Test Conditions Min

Model Parameters used for Driver Load switching performance evaluation

Typ

Max

Unit

C_PAD

Equivalent Single ended I/O PAD

capacitance.

—

1

2

pF

C_PIN

Equivalent Single ended Package +

PCB capacitance.

—

L_S

R_S

R_L

Equivalent wire bond series inductance

Equivalent wire bond series resistance

Load resistance

—

80

—

1.5

0.15

125

nH

Ω

100

Ω

4.11.12.6 High-Speed Clock Timing

#,+P

#,+N

ꢄ$ATA "IT 4IME ꢍ ꢄ5)

5)_).34ꢋꢄꢌ

5)_).34ꢋꢇꢌ

5)_).34ꢋꢄꢌ ꢑ 5)_).34ꢋꢇꢌ

ꢄ $$2 #LOCK 0ERIOD ꢍ

Figure 70. DDR Clock Definition

4.11.12.7 Forward High-Speed Data Transmission Timing

The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in

Figure 71:

2EFERENCE 4IME

4_3%450

4_(/,$

ꢑ

ꢀꢅꢆ5)_).34

4_3+%7

#,+P

#,+N

ꢄ 5)_).34

4_#,+P

Figure 71. Data to Clock Timing Definitions

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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110

Electrical Characteristics

4.11.12.8 Reverse High-Speed Data Transmission Timing

4

4$

.2: $ATA

#,+?.

#,+?0

#LOCK TO $ATA

3KEW

ꢇ5)

Figure 72. Reverse High-Speed Data Transmission Timing at Slave Side

4.11.12.9 Low-Power Receiver Timing

2*T_LPX

e_SPIKE

V_IH

V_IL

Input

e_SPIKE

T_MIN-RX

Output

Figure 73. Input Glitch Rejection of Low-Power Receivers

4.11.13 HSI Host Controller Timing Parameters

This section describes the timing parameters of the HSI Host Controller which are compliant with

High-speed Synchronous Serial Interface (HSI) Physical Layer specification version1.01.

4.11.13.1 Synchronous Data Flow

&IRST BIT OF

FRAME

,AST BIT OF

FRAME

,AST BIT OF

FRAME

&IRST BIT OF

FRAME

T_.OM"IT

(3)?$!4!

(3)?&,!'

.ꢏBITS &RAME

(3)?2%!$9

2ECEIVER HAS

DETECTED THE START

OF THE &RAME

2ECEIVER HAS CAPTURED

AND STORED A COMPLETE &RAME

Figure 74. Synchronized Data Flow READY Signal Timing (Frame and Stream Transmission)

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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111

Electrical Characteristics

4.11.13.2 Pipelined Data Flow

&IRST BIT OF

FRAME

,AST BIT OF &IRST BIT OF

FRAME FRAME

,AST BIT OF

FRAME

,AST BIT OF

FRAME

T _.OM"IT

$!4!

&,!'

.ꢏBITS &RAME

2%!$9

"ꢅ 2EADY SHALL NOT

CHANGE TO ZERO

!ꢅ 2EADY CAN CHANGE

#ꢅ 2EADY CAN CHANGE

$ꢅ 2EADYꢒ SHALL

%ꢅ 2EADY &ꢅ2EADY

'ꢅ2EADY

CAN

SHALL

CAN CHANGE

MAINTAIN ZERO IF

RECEIVER DOES NOT

HAVE FREE SPACE

CHANGE MAINTAIN

ITS VALUE

Figure 75. Pipelined Data Flow Ready Signal Timing (Frame Transmission Mode)

4.11.13.3 Receiver Real-Time Data Flow

&IRST BIT OF

FRAME

,AST BIT OF

FRAME

&IRST BIT OF

FRAME

,AST BIT OF

FRAME

T_.OM"IT

$!4!

&,!'

.ꢏBITS &RAME

2%!$9

2ECEIVER HAS CAPTURED A

COMPLETE &RAME

2ECEIVER HAS DETECTED THE

START OF THE &RAME

Figure 76. Receiver Real-Time Data Flow READY Signal Timing

4.11.13.4 Synchronized Data Flow Transmission with Wake

"

#

$

!

48 STATE

0(9 &RAME

$!4!

&,!'

ꢈꢅ &IRST BIT

RECEIVED

2%!$9

ꢉꢅ 2ECEIVED

FRAME STORED

ꢇꢅ2ECEIVER IN ACTIVE

ꢓꢅ 2ECEIVER CAN NO

LONGER RECEIVE DATE

START STATE

ꢆꢅ TRANSMITTER HAS

NO MORE DATA TO

TRANSMIT

7!+%

ꢄꢅ4RANSMITTER HAS

DATA TO TRANSMIT

"

!

#

$

!

28 STATE

!ꢂ 3LEEP STATE

"ꢂ 7AKEꢏUP STATE

#ꢂ !CTIVE STATE

$ꢂ $ISABLE 3TATE

ꢋ.O COMMUNICATION ABILITYꢌ

ꢋNONꢏOPERATIONALꢌ

ꢋFULL OPERATIONALꢌ

Figure 77. Synchronized Data Flow Transmission with WAKE

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

112

Electrical Characteristics

4.11.13.5 Stream Transmission Mode Frame Transfer

#HANNEL

$ESCRIPTION

BITS

0AYLOAD $ATA "ITS

$!4!

&,!'

#OMPLETE .ꢏBITS &RAME

2%!$9

Figure 78. Stream Transmission Mode Frame Transfer (Synchronized Data Flow)

4.11.13.6 Frame Transmission Mode (Synchronized Data Flow)

&RAME

#HANNEL

$ESCRIPTION

BITS

START BIT

0AYLOAD $ATA "ITS

$!4!

&,!'

#OMPLETE .ꢏBITS &RAME

2%!$9

Figure 79. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow)

4.11.13.7 Frame Transmission Mode (Pipelined Data Flow)

&RAME

START BIT

#HANNEL

$ESCRIPTION

BITS

0AYLOAD

$ATA "ITS

$!4!

&,!'

#OMPLETE .ꢏBITS &RAME

2%!$9

Figure 80. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow)

4.11.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load

Table 72. DATA and FLAG Timing

Parameter

Description

1 Mbit/s

100 Mbit/s 200 Mbit/s

t_{Bit, nom}

Nominal bit time

Minimum allowed rise and fall time

1000 ns

2.00 ns

10.0 ns

2.00 ns

5.00 ns

1.00 ns

t_{Rise, min}and

t_{Fall, min}

t_{TxToRxSkew, maxfq}Maximum skew between transmitter and receiver package pins

50.0 ns

0.5.0 ns

0.25 ns

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113

Electrical Characteristics

Parameter

Table 72. DATA and FLAG Timing (continued)

Description 1 Mbit/s

100 Mbit/s 200 Mbit/s

t_{EageSepTx, min}

Minimum allowed separation of signal transitions at transmitter

package pins, including all timing defects, for example, jitter

and skew, inside the transmitter.

400 ns

4.00 ns

2.00 ns

t_{EageSepRx, min}

Minimum separation of signal transitions, measured at the

receiver package pins, including all timing defects, for example,

jitter and skew, inside the receiver.

350 ns

3.5 ns

1.75 ns

T_%DGE3EP4X

ꢊꢀꢎ

ꢆꢀꢎ

.OTE ꢄ

ꢆꢀꢎ

$!4!

ꢋ48ꢌ

T_2ISE

.OTE ꢇ

ꢊꢀꢎ

ꢇꢀꢎ

ꢊꢀꢎ

ꢆꢀꢎ

&,!'

ꢋ48ꢌ

ꢇꢀꢎ

T_"IT

T_&ALL

T_%DGE3EP2X

T_4X4O2X3KEW

ꢆꢀꢎ

ꢊꢀꢎ

ꢆꢀꢎ

.OTE ꢄ

$!4!

ꢋ28ꢌ

.OTE ꢇ

ꢆꢀꢎ

&,!'

ꢋ28ꢌ

ꢇꢀꢎ

1

This case shows that the DATA signal has slowed down more compared to the FLAG signal

This case shows that the FLAG signal has slowed down more compared to the DATA signal.

2

Figure 81. DATA and FLAG Signal Timing

4.11.14 MediaLB (MLB) Characteristics

4.11.14.1 MediaLB (MLB) DC Characteristics

Table 73 lists the MediaLB 3-pin interface electrical characteristics.

Table 73. MediaLB 3-Pin Interface Electrical DC Specifications

Parameter

Symbol

Test Conditions

Min

Max

Unit

Maximum input voltage

Low level input threshold

High level input threshold

Low level output threshold

High level output threshold

Input leakage current

—

V_IL

V_IH

V_OL

V_OH

I_L

—

3.6

0.7

—

V

—

See Note¹

I_OL= 6 mA

I_OH= -6 mA

0 < V_in< VDD

1.8

—

V

0.4

—

V

2.0

—

V

10

μA

1

Higher V_IHthresholds can be used; however, the risks associated with less noise margin in the system must be

evaluated and assumed by the customer.

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114

NXP Semiconductors

Electrical Characteristics

Table 74 lists the MediaLB 6-pin interface electrical characteristics.

Table 74. MediaLB 6-Pin Interface Electrical DC Specifications

Parameter

Symbol

Test Conditions

Min

Max

Unit

Driver Characteristics

Differential output voltage

(steady-state):

V_OD

See Note¹

300

-50

500

50

mV

I V_O+- V_O-

I

Difference in differential output

voltage between (high/low)

steady-states:

ΔV_OD

—

I V_{OD, high}- V_{OD, low}

I

Common-mode output voltage:

(V_O+- V_O-) / 2

V_OCM

—

1.0

-50

1.5

50

V

Difference in common-mode

output between (high/low)

steady-states:

ΔV_OCM

mV

I V_{OCM, high}- V_{OCM, low}

I

Variations on common-mode

output during a logic state

transitions

V_CMV

See Note²

—

150

mVpp

Short circuit current

|I_OS

|

See Note³

—

43

—

mA

Differential output impedance

Z_O

1.6

kΩ

Receiver Characteristics

Differential clock input:

• logic low steady-state

• logic high steady-state

• hysteresis

See Note⁴

V_ILC

V_IHC

V_HSC

—

50

-25

-50

—

25

mV

Differential signal/data input:

• logic low steady-state

• logic high steady-state

—

V_ILS

V_IHS

—

50

-50

—

mV

Signal-ended input voltage

(steady-state):

• MLB_SIG_P, MLB_DATA_P

• MLB_SIG_N, MLB_DATA_N

V_IN+

V_IN-

0.5

2.0

V

1

2

The signal-ended output voltage of a driver is defined as V_O+on MLB_CLK_P, MLB_SIG_P, and MLB_DATA_P. The

signal-ended output voltage of a driver is defined as V_O-on MLB_CLK_N, MLB_SIG_N, and MLB_DATA_N.

Variations in the common-mode voltage can occur between logic states (for example, during state transitions) as a result of

differences in the transition rate of V_O+and V_O-

.

3

4

Short circuit current is applicable when V_O+and V_O-are shorted together and/or shorted to ground.

The logic state of the receiver is undefined when -50 mV < V_ID< 50 mV.

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115

Electrical Characteristics

4.11.14.2 MediaLB (MLB) Controller AC Timing Electrical Specifications

This section describes the timing electrical information of the MediaLB module. Figure 82 show the

timing of MediaLB 3-pin interface, and Table 75 and Table 76 lists the MediaLB 3-pin interface timing

characteristics.

-,"?3)'ꢀ

-,"?$!4!

VALID

ꢋRECEIVERꢌ

T_PROP

T_DHMCF

T_MCKF

T_DSMCF

T_MCKR

T_MCKH

T_MCKL

-,"?#,+

-,"?3)'ꢀ

T_DELAY

T_MCFDZ

VALID

-,"?$!4!

ꢋTRANSMITTERꢌ

T_MDZH

-,"?3)'ꢀ

-,"?$!4!

ꢋBUS STATEꢌ

VALID

Figure 82. MediaLB 3-Pin Timing

Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing

parameters specified from the valid voltage threshold as listed below; unless otherwise noted.

Table 75. MLB 256/512 Fs Timing Parameters

Parameter

Symbol

Min

Max

Unit

Comment

MLB_CLK operating frequency¹

f_mck

11.264

MHz

256xFs at 44.0 kHz

512xFs at 50.0 kHz

25.6

MLB_CLK rise time

MLB_CLK fall time

MLB_CLK low time²

t_mckr

t_mckf

t_mckl

—

3

ns

V_ILTO V_IH

V_IHTO V_IL

30

14

—

256xFs

512xFs

MLB_CLK high time

t_mckh

t_dsmcf

t_dhmcf

t_mcfdz

t_mdzh

30

14

—

ns

256xFs

512xFs

MLB_SIG/MLB_DATA receiver input valid to

MLB_CLK falling

1

t_mdzh

0

—

MLB_SIG/MLB_DATA receiver input hold

from MLB_CLK low

—

3

MLB_SIG/MLB_DATAoutputhighimpedance

from MLB_CLK low

t_mckl

Bus Hold from MLB_CLK low

4

—

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Electrical Characteristics

Table 75. MLB 256/512 Fs Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

Comment

MLB_SIG/MLB_DATA output valid from

transition of MLB_CLK (low to high)

t_delay

—

10

ns

—

Transmitter MLBSIG (MLBDAT) output valid

from transition of MLBCLK (low-to-high)

t_delay

—

10.75

ns

—

1

The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a runt

pulse can occur on MLB_CLK.

2

3

MLB_CLK low/high time includes the pulse width variation.

The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the

final driven bit on the line must remain on the bus for t_mdzh. Therefore, coupling must be minimized while meeting the maximum

load capacitance listed.

Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing

parameters specified from the valid voltage threshold as listed in Table 76; unless otherwise noted.

Table 76. MLB 1024 Fs Timing Parameters

Parameter

Symbol

Min

Max

Unit

Comment

MLB_CLK Operating Frequency¹

f_mck

45.056

51.2

MHz

1024xfs at 44.0 kHz

1024xfs at 50.0 kHz

MLB_CLK rise time

MLB_CLK fall time

MLB_CLK low time

MLB_CLK high time

t_mckr

t_mckf

t_mckl

—

1

ns

V_ILTO V_IH

1

V_IHTO V_IL

2

6.1

9.3

1

—

t_mckh

t_dsmcf

—

MLB_SIG/MLB_DATA receiver input valid to

MLB_CLK falling

MLB_SIG/MLB_DATA receiver input hold

from MLB_CLK low

t_dhmcf

t_mcfdz

t_mdzh

0

—

ns

—

3

MLB_SIG/MLB_DATA output high

impedance from MLB_CLK low

t_mckl

Bus Hold from MLB_CLK low

t_mdzh

t_delay

2

—

7

ns

—

MLB_SIG/MLB_DATA output valid from

transition of MLB_CLK (low to high)

—

Transmitter MLBSIG (MLBDAT) output valid

from transition of MLBCLK (low-to-high)

t_delay

—

6

ns

—

1

The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a

runt pulse can occur on MLB_CLK.

2

3

MLB_CLK low/high time includes the pulse width variation.

The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the

final driven bit on the line must remain on the bus for t_mdzh. Therefore, coupling must be minimized while meeting the maximum

load capacitance listed.

Table 77 lists the MediaLB 6-pin interface timing characteristics, and Figure 83 shows the MLB 6-pin

delay, setup, and hold times.

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Electrical Characteristics

Table 77. MLB 6-Pin Interface Timing Parameters

Parameter

Symbol Min

Max

Unit

Comment

Cycle-to-cycle system jitter

t_jitter

—

600

1.3

ps

ns

—

Transmitter MLB_SIG_P/_N (MLB_DATA_P/_N) output valid

from transition of MLB_CLK_P/_N (low-to-high)¹

t_delay

0.6

Disable turnaround time from transition of MLB_CLK_P/_N

(low-to-high)

t_phz

t_plz

t_su

0.6

3.5

5.6

—

ns

—

Enable turnaround time from transition of MLB_CLK_P/_N

(low-to-high)

MLB_SIG_P/_N (MLB_DATA_P/_N) valid to transition of

MLB_CLK_P/_N (low-to-high)

0.05

0.6

MLB_SIG_P/_N (MLB_DATA_P/_N) hold from transition of

MLB_CLK_P/_N (low-to-high)²

t_hd

1

t_delay, t_phz, t_plz, t_su, and t_hdmay also be referenced from a low-to-high transition of the recovered clock for 2:1 and 4:1 recov-

ered-to-external clock ratios.

2

The transmitting device must ensure valid data on MLB_SIG_P/_N (MLB_DATA_P/_N) for at least t_hd(min)following the rising

edge of MLB_CLK_P/N; receivers must latch MLB_SIG_P/_N (MLB_DATA_P/_N) data within t_hd(min)of the rising edge of ML-

B_CLK_P/_N.

0HYSICAL #HANNEL

BOUNDARY

-,"?#,+?0ꢃ.

2ECOVERED

CLOCK ꢋꢉꢂꢄꢌ

ꢈX4_ꢉꢂꢄ

ꢇX4_ꢉꢂꢄ

4_ꢉꢂꢄ

T_DELAY

ꢈX4_ꢉꢂꢄ

T_DELAY

#MD

T_DELAY

#MD

T_DELAY

#MD

T_DELAY

#MD

-,"?3)'?0ꢃ.

ꢋTRANSMITTERꢌ

#MD

;ꢓ=

#MD

;ꢇ=

#!;ꢀ=

;ꢁ=

;ꢆ=

;ꢉ=

;ꢈ=

#ONTROLLERꢂ #HANNELꢃ!DDRESS

4X $EVICEꢂ #OMMAND

T_PROP

TRANSMITTER ENABLEDꢒ

$ATA NOT VALID

T_HD

T_SU

T_SUT_HD

-,"?3)'?0ꢃ.

ꢋRECEIVERꢌ

#MD

;ꢁ=

#MD

;ꢓ=

#MD

;ꢆ=

#MD

;ꢉ=

#MD

;ꢈ=

#MD

;ꢇ=

#!;ꢀ=

#ONTROLLERꢂ #HANNELꢃ!DDRESS

4X $EVICEꢂ #OMMAND

Figure 83. MLB 6-Pin Delay, Setup, and Hold Times

4.11.15 PCIe PHY Parameters

The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0

standard.

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Electrical Characteristics

4.11.15.1 PCIE_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 200 Ω. 1ꢀ precision resistor

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.11.16 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 84 depicts the timing of the PWM, and Table 78 lists the PWM timing parameters.

0ꢄ

0ꢇ

07-N?/54

Figure 84. PWM Timing

Table 78. PWM Output Timing Parameters

ID

Parameter

Min

Max

Unit

PWM Module Clock Frequency

PWM output pulse width high

PWM output pulse width low

0

ipg_clk

—

MHz

ns

P1

P2

15

—

ns

4.11.17 SCAN JTAG Controller (SJC) Timing Parameters

Figure 85 depicts the SJC test clock input timing. Figure 86 depicts the SJC boundary scan timing.

Figure 87 depicts the SJC test access port. Signal parameters are listed in Table 79.

SJ1

SJ2

JTAG_TCK

(Input)

VM

VIH

VIL

SJ3

Figure 85. Test Clock Input Timing Diagram

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Electrical Characteristics

JTAG_TCK

(Input)

VIH

SJ5

VIL

SJ4

Input Data Valid

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 86. Boundary Scan (JTAG) Timing Diagram

JTAG_TCK

(Input)

VIH

VIL

SJ8

Input Data Valid

SJ9

JTAG_TDI

JTAG_TMS

(Input)

SJ10

SJ11

SJ10

JTAG_TDO

(Output)

Output Data Valid

JTAG_TDO

(Output)

JTAG_TDO

(Output)

Output Data Valid

Figure 87. Test Access Port Timing Diagram

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Electrical Characteristics

JTAG_TCK

(Input)

SJ13

JTAG_TRST_B

(Input)

SJ12

Figure 88. JTAG_TRST_B Timing Diagram

Table 79. JTAG Timing

All Frequencies

ID

Parameter^1,2

Unit

Min

Max

1

SJ0

SJ1

JTAG_TCK frequency of operation 1/(3•T_DC

)

0.001

45

22.5

—

22

—

3

MHz

ns

JTAG_TCK cycle time in crystal mode

2

SJ2

JTAG_TCK clock pulse width measured at V_M

JTAG_TCK rise and fall times

SJ3

SJ4

Boundary scan input data set-up time

Boundary scan input data hold time

JTAG_TCK low to output data valid

JTAG_TCK low to output high impedance

JTAG_TMS, JTAG_TDI data set-up time

JTAG_TMS, JTAG_TDI data hold time

JTAG_TCK low to JTAG_TDO data valid

5

—

40

—

44

—

SJ5

24

—

SJ6

SJ7

—

SJ8

5

SJ9

25

—

SJ10

SJ11

SJ12

SJ13

JTAG_TCK low to JTAG_TDO high impedance

JTAG_TRST_B assert time

—

100

40

JTAG_TRST_B set-up time to JTAG_TCK low

1

2

T

= target frequency of SJC

DC

V_M= mid-point voltage

4.11.18 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 80 and Figure 89 and Figure 90 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

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Table 80. SPDIF Timing Parameters

Symbol

Timing Parameter Range

Characteristics

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

ns

SPDIF_OUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

ns

SPDIF_OUT output (Load = 30pf)

—

1.5

13.6

18.0

• Skew

• Transition rising

• Transition falling

Modulating Rx clock (SPDIF_SR_CLK) period

SPDIF_SR_CLK high period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SPDIF_SR_CLK low period

Modulating Tx clock (SPDIF_ST_CLK) period

SPDIF_ST_CLK high period

SPDIF_ST_CLK low period

srckp

srckpl

srckph

V_M

SPDIF_SR_CLK

V_M

(Output)

Figure 89. SPDIF_SR_CLK Timing Diagram

stclkp

stclkpl

V_M

stclkph

V_M

SPDIF_ST_CLK

(Input)

Figure 90. SPDIF_ST_CLK Timing Diagram

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4.11.19 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 81.

Table 81. AUDMUX Port Allocation

Port

Signal Nomenclature

Type and Access

AUDMUX port 1

AUDMUX port 2

AUDMUX port 3

AUDMUX port 4

AUDMUX port 5

AUDMUX port 6

AUDMUX port 7

SSI 1

SSI 2

AUD3

AUD4

AUD5

AUD6

SSI 3

Internal

External—AUD3 I/O

External—EIM or CSPI1 I/O through IOMUXC

External—EIM or SD1 I/O through IOMUXC

External—EIM or DISP2 through IOMUXC

Internal

NOTE

The terms WL and BL used in the timing diagrams and tables refer to

Word Length (WL) and Bit Length (BL).

4.11.19.1 SSI Transmitter Timing with Internal Clock

Figure 91 depicts the SSI transmitter internal clock timing and Table 82 lists the timing parameters for

the SSI transmitter internal clock.

.

SS1

SS5

SS4

SS3

SS2

AUDx_TXC

(Output)

SS8

SS6

AUDx_TXFS (bl)

(Output)

SS10

SS12

AUDx_TXFS (wl)

(Output)

SS14

SS17

SS15

SS16

SS18

AUDx_TXD

(Output)

SS43

SS42

SS19

AUDx_RXD

(Input)

Note: AUDx_RXD input in synchronous mode only

Figure 91. SSI Transmitter Internal Clock Timing Diagram

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Electrical Characteristics

Table 82. SSI Transmitter Timing with Internal Clock

ID

Parameter

Internal Clock Operation

Min

Max

Unit

SS1

SS2

AUDx_TXC/AUDxRXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDxRXC clock high period

AUDx_TXC/AUDxRXC clock low period

—

SS4

—

SS6

AUDx_TXC high to AUDx_TXFS (bl) high

AUDx_TXC high to AUDx_TXFS (bl) low

AUDx_TXC high to AUDx_TXFS (wl) high

AUDx_TXC high to AUDx_TXFS (wl) low

AUDx_TXC/AUDxRXC Internal AUDx_TXFS rise time

AUDx_TXC/AUDxRXC Internal AUDx_TXFS fall time

AUDx_TXC high to AUDx_TXD valid from high impedance

AUDx_TXC high to AUDx_TXD high/low

15.0

6.0

SS8

—

SS10

SS12

SS14

SS15

SS16

SS17

SS18

—

6.0

—

15.0

—

AUDx_TXC high to AUDx_TXD high impedance

—

Synchronous Internal Clock Operation

SS42

SS43

AUDx_RXD setup before AUDx_TXC falling

AUDx_RXD hold after AUDx_TXC falling

10.0

0.0

—

ns

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

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4.11.19.2 SSI Receiver Timing with Internal Clock

Figure 92 depicts the SSI receiver internal clock timing and Table 83 lists the timing parameters for the

receiver timing with the internal clock.

SS1

SS3

SS5

SS4

SS2

AUDx_TXC

(Output)

SS9

SS7

AUDx_TXFS (bl)

(Output)

SS11

SS13

AUDx_TXFS (wl)

(Output)

SS20

SS21

AUDx_RXD

(Input)

SS51

SS50

SS47

SS49

SS48

AUDx_RXC

(Output)

Figure 92. SSI Receiver Internal Clock Timing Diagram

Table 83. SSI Receiver Timing with Internal Clock

ID

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

SS2

AUDx_TXC/AUDx_RXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

AUDx_RXC high to AUDx_TXFS (bl) high

AUDx_RXC high to AUDx_TXFS (bl) low

AUDx_RXC high to AUDx_TXFS (wl) high

AUDx_RXC high to AUDx_TXFS (wl) low

AUDx_RXD setup time before AUDx_RXC low

AUDx_RXD hold time after AUDx_RXC low

SS3

6.0

—

SS4

36.0

—

SS5

6.0

15.0

—

SS7

—

SS9

—

SS11

SS13

SS20

SS21

—

10.0

0.0

—

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Electrical Characteristics

Table 83. SSI Receiver Timing with Internal Clock (continued)

ID

Parameter

Min

Max

Unit

Oversampling Clock Operation

SS47

SS48

SS49

SS50

SS51

Oversampling clock period

Oversampling clock high period

15.04

6.0

—

ns

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

3.0

—

6.0

—

3.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

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4.11.19.3 SSI Transmitter Timing with External Clock

Figure 93 depicts the SSI transmitter external clock timing and Table 84 lists the timing parameters for

the transmitter timing with the external clock.

SS22

SS23

SS25

SS26

SS24

AUDx_TXC

(Input)

SS27

SS29

AUDx_TXFS (bl)

(Input)

SS33

SS31

AUDx_TXFS (wl)

(Input)

SS39

SS37

SS38

AUDx_TXD

(Output)

SS45

SS44

AUDx_RXD

(Input)

SS46

Note: AUDx_RXD Input in Synchronous mode only

Figure 93. SSI Transmitter External Clock Timing Diagram

Table 84. SSI Transmitter Timing with External Clock

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22

SS23

SS24

SS25

SS26

SS27

SS29

SS31

SS33

SS37

SS38

SS39

AUDx_TXC/AUDx_RXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

6.0

—

36.0

—

6.0

15.0

—

AUDx_TXC high to AUDx_TXFS (bl) high

AUDx_TXC high to AUDx_TXFS (bl) low

AUDx_TXC high to AUDx_TXFS (wl) high

AUDx_TXC high to AUDx_TXFS (wl) low

AUDx_TXC high to AUDx_TXD valid from high impedance

AUDx_TXC high to AUDx_TXD high/low

AUDx_TXC high to AUDx_TXD high impedance

-10.0

10.0

-10.0

10.0

—

15.0

—

15.0

—

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Electrical Characteristics

Table 84. SSI Transmitter Timing with External Clock (continued)

ID

Parameter

Min

Max

Unit

Synchronous External Clock Operation

SS44

SS45

SS46

AUDx_RXD setup before AUDx_TXC falling

10.0

2.0

—

ns

AUDx_RXD hold after AUDx_TXC falling

AUDx_RXD rise/fall time

6.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

4.11.19.4 SSI Receiver Timing with External Clock

Figure 94 depicts the SSI receiver external clock timing and Table 85 lists the timing parameters for the

receiver timing with the external clock.

SS22

SS26

SS25

SS24

SS23

AUDx_TXC

(Input)

SS30

SS28

AUDx_TXFS (bl)

(Input)

SS32

SS35

SS34

AUDx_TXFS (wl)

(Input)

SS41

SS36

SS40

AUDx_RXD

(Input)

Figure 94. SSI Receiver External Clock Timing Diagram

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Electrical Characteristics

Table 85. SSI Receiver Timing with External Clock

ID

Parameter

Min

Max

Unit

External Clock Operation

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

AUDx_TXC/AUDx_RXC clock period

81.4

36

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

6.0

—

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

36

—

6.0

15.0

—

AUDx_RXC high to AUDx_TXFS (bl) high

AUDx_RXC high to AUDx_TXFS (bl) low

AUDx_RXC high to AUDx_TXFS (wl) high

AUDx_RXC high to AUDx_TXFS (wl) low

AUDx_TXC/AUDx_RXC External AUDx_TXFS rise time

AUDx_TXC/AUDx_RXC External AUDx_TXFS fall time

AUDx_RXD setup time before AUDx_RXC low

AUDx_RXD hold time after AUDx_RXC low

-10

10

-10

10

—

15.0

—

6.0

—

10

2

—

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

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4.11.20 UART I/O Configuration and Timing Parameters

4.11.20.1 UART RS-232 I/O Configuration in Different Modes

The i.MX 6Solo/6DualLite UART interfaces can serve both as DTE or DCE device. This can be

configured by the DCEDTE control bit (default 0—DCE mode). Table 86 shows the UART I/O

configuration based on the enabled mode.

Table 86. UART I/O Configuration vs. Mode

DTE Mode

Description

DCE Mode

Description

Port

Direction

UARTx_RTS_B

UARTx_CTS_B

UARTx_DTR_B

UARTx_DSR_B

UARTx_DCD_ B

UARTx_RI_B

Output

Input

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

Input

Output

Input

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

Output

Input

Output

Input

UARTx_TX_DATA

UARTx_RX_DATA

Input

Output

4.11.20.2 UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

4.11.20.2.1 UART Transmitter

Figure 95 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit

format. Table 87 lists the UART RS-232 serial mode transmit timing characteristics.

Possible

UA1

Parity

Bit

Start

Bit

UARTx_TX_DATA

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 95. UART RS-232 Serial Mode Transmit Timing Diagram

Table 87. RS-232 Serial Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

2

UA1 Transmit Bit Time

t_Tbit

1/F_{baud_rate}¹- T_{ref_clk}

—

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

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Electrical Characteristics

4.11.20.2.2 UART Receiver

Figure 96 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 88 lists

serial mode receive timing characteristics.

Possible

Parity

Bit

UA2

Bit 3

Bit

Start

Bit

UARTx_RX_DATA

(input)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 96. UART RS-232 Serial Mode Receive Timing Diagram

Table 88. RS-232 Serial Mode Receive Timing Parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}+ 1/(16 x F_{baud_rate}

Unit

UA2

Receive Bit Time¹

t_Rbit

1/F_{baud_rate}²- 1/(16 x F_{baud_rate}

)

—

1

2

The UART receiver can tolerate 1/(16 x F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x F_{baud_rate}).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

4.11.20.2.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

UART IrDA Mode Transmitter

Figure 97 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 89 lists

the transmit timing characteristics.

UA3

UA4

UA3

UARTx_TX_DATA

(output)

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 97. UART IrDA Mode Transmit Timing Diagram

Table 89. IrDA Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

2

UA3 Transmit Bit Time in IrDA mode

UA4 Transmit IR Pulse Duration

t_TIRbit

1/F_{baud_rate}¹- T_{ref_clk}

1/F_{baud_rate}+ T_{ref_clk}

—

t_TIRpulse(3/16) x (1/F_{baud_rate}) - T_{ref_clk}

(3/16) x (1/F_{baud_rate}) + T_{ref_clk}

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

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UART IrDA Mode Receiver

Figure 98 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 90 lists

the receive timing characteristics.

UA5

UA6

UA5

UARTx_RX_DATA

(input)

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 98. UART IrDA Mode Receive Timing Diagram

Table 90. IrDA Mode Receive Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

UA5 Receive Bit Time¹in IrDA mode

UA6 Receive IR Pulse Duration

t_RIRbit

1/F_{baud_rate}²- 1/(16 x F_{baud_rate}

)

1/F_{baud_rate}+ 1/(16 x F_{baud_rate}

)

—

t_RIRpulse

1.41 μs

(5/16) x (1/F_{baud_rate}

)

1

The UART receiver can tolerate 1/(16 x F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x F_{baud_rate}).

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

4.11.21 USB HSIC Timings

This section describes the electrical information of the USB HSIC port.

NOTE

HSIC is DDR signal, following timing spec is for both rising and falling

edge.

4.11.21.1 Transmit Timing

Tstrobe

USB_H_STROBE

Todelay

USB_H_DATA

Figure 99. USB HSIC Transmit Waveform

Table 91. USB HSIC Transmit Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

4.166

550

4.167

1350

2

ns

ps

—

Todelay data output delay time

Measured at 50% point

Averaged from 30% – 70% points

Tslew

strobe/data rising/falling time

0.7

V/ns

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4.11.21.2 Receive Timing

Tstrobe

USB_H_STROBE

USB_H_DATA

Thold

Tsetup

Figure 100. USB HSIC Receive Waveform

1

Table 92. USB HSIC Receive Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

4.166

300

365

0.7

4.167

—

ns

ps

—

Thold

Tsetup

Tslew

data hold time

Measured at 50% point

data setup time

—

ps

Measured at 50% point

strobe/data rising/falling time

2

V/ns

Averaged from 30% – 70% points

1

The timings in the table are guaranteed when:

—AC I/O voltage is between 0.9x to 1x of the I/O supply

—DDR_SEL configuration bits of the I/O are set to (10)b

4.11.22 USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters.

The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision

2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB

Revision 2.0 Specification is not applicable to Host port).

•

USB ENGINEERING CHANGE NOTICE

— Title: 5V Short Circuit Withstand Requirement Change

— Applies to: Universal Serial Bus Specification, Revision 2.0

Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000

USB ENGINEERING CHANGE NOTICE

•

— Title: Pull-up/Pull-down resistors

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

•

— Title: Suspend Current Limit Changes

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

— Title: USB 2.0 Phase Locked SOFs

— Applies to: Universal Serial Bus Specification, Revision 2.0

On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification

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Boot Mode Configuration

— Revision 2.0 plus errata and ecn June 4, 2010

•

Battery Charging Specification (available from USB-IF)

— Revision 1.2, December 7, 2010

— Portable device only

5 Boot Mode Configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot Mode Configuration Pins

Table 93 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX

6Solo/6DualLite Fuse Map document and the System Boot chapter in i.MX 6Solo/6DualLite Reference

Manual (IMX6SDLRM).

Table 93. Fuses and Associated Pins Used for Boot

Direction at Reset

eFuse Name

Boot Mode Selection

BOOT_MODE1

BOOT_MODE0

Input

N/A

Boot Options¹

EIM_DA0

EIM_DA1

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

Input

BOOT_CFG1[0]

BOOT_CFG1[1]

BOOT_CFG1[2]

BOOT_CFG1[3]

BOOT_CFG1[4]

BOOT_CFG1[5]

BOOT_CFG1[6]

BOOT_CFG1[7]

BOOT_CFG2[0]

BOOT_CFG2[1]

BOOT_CFG2[2]

BOOT_CFG2[3]

BOOT_CFG2[4]

BOOT_CFG2[5]

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Table 93. Fuses and Associated Pins Used for Boot (continued)

Direction at Reset

eFuse Name

EIM_DA14

EIM_DA15

EIM_A16

EIM_A17

EIM_A18

EIM_A19

EIM_A20

EIM_A21

EIM_A22

EIM_A23

EIM_A24

EIM_WAIT

EIM_LBA

EIM_EB0

EIM_EB1

EIM_RW

EIM_EB2

EIM_EB3

Input

BOOT_CFG2[6]

BOOT_CFG2[7]

BOOT_CFG3[0]

BOOT_CFG3[1]

BOOT_CFG3[2]

BOOT_CFG3[3]

BOOT_CFG3[4]

BOOT_CFG3[5]

BOOT_CFG3[6]

BOOT_CFG3[7]

BOOT_CFG4[0]

BOOT_CFG4[1]

BOOT_CFG4[2]

BOOT_CFG4[3]

BOOT_CFG4[4]

BOOT_CFG4[5]

BOOT_CFG4[6]

BOOT_CFG4[7]

1

Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input at Power

Up. These are special I/O lines that control the boot up configuration during product development. In production,

the boot configuration can be controlled by fuses.

5.2

Boot Device Interface Allocation

Table 94 lists the interfaces that can be used by the boot process in accordance with the specific boot

mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,

which are configured during boot when appropriate.

Table 94. Interface Allocation During Boot

Interface

IP Instance

Allocated Pads During Boot

Comment

SPI

ECSPI-1

EIM_D17, EIM_D18, EIM_D16, EIM_EB2, EIM_D19,

EIM_D24, EIM_D25

—

SPI

ECSPI-2

ECSPI-3

CSI0_DAT10, CSI0_DAT9, CSI0_DAT8, CSI0_DAT11,

EIM_LBA, EIM_D24, EIM_D25

—

DISP0_DAT2, DISP0_DAT1, DISP0_DAT0,

DISP0_DAT3,DISP0_DAT4,DISP0_DAT5,DISP0_DAT6

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Table 94. Interface Allocation During Boot (continued)

Interface

IP Instance

Allocated Pads During Boot

Comment

SPI

ECSPI-4

EIM_D22, EIM_D28, EIM_D21, EIM_D20, EIM_A25,

EIM_D24, EIM_D25

—

EIM

EIM_DA[15:0], EIM_D[31:16], CSI0_DAT[19:4],

CSI0_DATA_EN, CSI0_VSYNC

Used for NOR, OneNAND boot

Only CS0 is supported

NAND Flash

GPMI

NANDF_CLE, NANDF_ALE, NANDF_WP_B,

SD4_CMD, SD4_CLK, NANDF_RB0, SD4_DAT0,

NANDF_CS0, NANDF_CS1, NANDF_CS2,

NANDF_CS3, NANDF_D[7:0]

8 bit

Only CS0 is supported

SD/MMC

USDHC-1

USDHC-2

USDHC-3

USDHC-4

SD1_CLK, SD1_CMD, SD1_DAT0, SD1_DAT1,

SD1_DAT2, SD1_DAT3, GPIO_1, NANDF_D0,

NANDF_D1, NANDF_D2, NANDF_D3, KEY_COL1

1, 4, or 8 bit

SD2_CLK, SD2_CMD, SD2_DAT0, SD2_DAT1,

SD2_DAT2, SD2_DAT3, GPIO_4, NANDF_D4,

NANDF_D5, NANDF_D6, NANDF_D7, KEY_ROW1

SD3_CLK, SD3_CMD, SD3_DAT0, SD3_DAT1,

SD3_DAT2, SD3_DAT3, SD3_DAT4, SD3_DAT5,

SD3_DAT6, SD3_DAT7, SD3_RST, GPIO_18

SD4_CLK, SD4_CMD, SD4_DAT0, SD4_DAT1,

SD4_DAT2, SD4_DAT3, SD4_DAT4, SD4_DAT5,

SD4_DAT6, SD4_DAT7, NANDF_ALE, NANDF_CS1

I²C

I²C-1

I²C-2

I²C-3

EIM_D28, EIM_D21

EIM_D16, EIM_EB2

EIM_D18, EIM_D17

—

I²C

USB

USB-OTG

PHY

USB_OTG_DP

USB_OTG_DN

USB_OTG_VBUS

6 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

6.1

Updated Signal Naming Convention

The signal names of the i.MX6 series of products have been standardized to better align the signal names

within the family and across the documentation. Some of the benefits of these changes are as follows:

•

The names are unique within the scope of an SoC and within the series of products

Searches will return all occurrences of the named signal

The names are consistent between i.MX 6 series products implementing the same modules

The module instance is incorporated into the signal name

This change applies only to signal names. The original ball names have been preserved to prevent the need

to change schematics, BSDL models, IBIS models, etc.

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Package Information and Contact Assignments

Throughout this document, the updated signal names are used except where referenced as a ball name

(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal

name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to

map the signal names used in older documentation to the new standardized naming conventions.

6.2

21x21 mm Package Information

6.2.1

Case 2240, 21 x 21 mm, 0.8 mm Pitch, 25 x 25 Ball Matrix

Figure 101 shows the top, bottom, and side views of the 21×21 mm BGA package.

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Figure 101. 21 x 21 mm BGA, Case 2240 Package Top, Bottom, and Side Views

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Table 95 shows the 21 × 21 mm BGA package details.

Table 95. 21 x 21, 0.8 mm BGA Package Details

Common Dimensions

Parameter

Symbol

Minimum

Normal

Maximum

Total Thickness

Stand Off

A

A1

A2

A3

D

—

1.6

0.36

0.46

Substrate Thickness

Mold Thickness

Body Size

0.26 REF

0.7 REF

21 BSC

0.5

E

Ball Diameter

Ball Opening

—

0.4

Ball Width

b

0.44

—

0.64

Ball Pitch

e

0.8 BSC

624

Ball Count

n

Edge Ball Center to Center

D1

E1

SD

SE

aaa

bbb

ddd

eee

fff

19.2 BSC

—

Body Center to Contact Ball

—

Package Edge Tolerance

Mold Flatness

0.1

0.2

Coplanarity

0.15

Ball Offset (Package)

Ball Offset (Ball)

0.15

0.08

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6.2.2

21 x 21 mm Supplies Contact Assignments and Functional Contact

Assignments

Table 96 shows supplies contact assignments for the 21 x 21 mm package.

Table 96. 21 x 21 mm Supplies Contact Assignments

Supply Rail Name

Ball(s) Position(s)

Remark

CSI_REXT

DRAM_VREF

DSI_REXT

GND

D4

—

AC2

G4

A4, A8, A13, A25, B4, C1, C4, C6, C10, D3, D6, D8, E5,

E6, E7, F5, F6, F7, F8, G3, G10, G19, H8, H12, H15,

H18, J2, J8, J12, J15, J18, K8, K10, K12, K15, K18, L2,

L5, L8, L10, L12, L15, L18, M8, M10, M12, M15, M18,

N8, N10, N15, N18, P8, P10, P12, P15, P18, R8, R12,

R15, R17, T8, T11, T12, T15, T17, T19, U8, U11, U12,

U15, U17, U19, V8, V19, W3, W7, W8, W9, W10, W11,

W12, W13, W15, W16, W17, W18, W19, Y5, Y24, AA7,

AA10, AA13, AA16, AA19, AA22, AB3, AB24, AD4,

AD7, AD10, AD13, AD16, AD19, AD22, AE1, AE25

HDMI_REF

HDMI_VP

J1

—

L7

M7

N7

—

HDMI_VPH

NVCC_CSI

NVCC_DRAM

—

Supply of the camera sensor interface

R18, T18, U18, V9, V10, V11, V12, V13, V14, V15, V16, Supply of the DDR interface

V17, V18

NVCC_EIM

NVCC_ENET

NVCC_GPIO

NVCC_JTAG

NVCC_LCD

K19, L19, M19

Supply of the EIM interface

R19

P7

Supply of the ENET interface

Supply of the GPIO interface

Supply of the JTAG tap controller interface

Supply of the LCD interface

J7

P19

V7

NVCC_LVDS2P5

Supply of the LVDS display interface and DDR

pre-drivers

NVCC_MIPI

K7

Supply of the MIPI interface

NVCC_NANDF

G15

Supply of the raw NAND Flash memories

interface

NVCC_PLL_OUT

NVCC_RGMII

NVCC_SD1

E8

—

G18

G16

G17

G14

Supply of the ENET interface

Supply of the SD card interface

NVCC_SD2

NVCC_SD3

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Table 96. 21 x 21 mm Supplies Contact Assignments (continued)

Supply Rail Name

Ball(s) Position(s)

Remark

PCIE_REXT

PCIE_VP

A2

H7

G7

G8

G9

—

PCIE_VPH

PCI PHY supply

PCIE_VPTX

VDD_SNVS_CAP

Secondary supply for the SNVS (internal

regulator output—requires capacitor if internal

regulator is used)

VDD_SNVS_IN

VDDARM_CAP

G11

Primary supply for the SNVS regulator

H11, H13, J11, J13, K11, K13, L11, L13, M11, M13,

N11, N13, P11, P13, R11, R13

Secondary supply for core (internal regulator

output—requires capacitor if internal regulator

is used)

VDDARM_IN

H14, J14, K9, K14, L9, L14, M9, M14, N9, N14, P9,

P14, R9, R14, T9, U9

Primary supply for the Arm core’s regulator

VDDHIGH_CAP

H10, J10

Secondary supply for the 2.5 V domain

(internal regulator output—requires capacitor

if internal regulator is used)

VDDHIGH_IN

VDDPU_CAP

H9, J9

Primary supply for the 2.5 V regulator

H17, J17, K17, L17, M17, N17, P17

Secondary supply for VPU and GPUs

(internal regulator output—requires capacitor

if internal regulator is used)

VDDSOC_CAP

R10, T10, T13, T14, U10, U13, U14

Secondary supply for SoC and PU regulators

(internal regulator output—requires capacitor

if internal regulator is used)

VDDSOC_IN

H16, J16, K16, L16, M16, N16, P16, R16, T16, U16

F9

Primary supply for SoC and PU regulators

VDDUSB_CAP

Secondary supply for the 3 V Domain (internal

regulator output—requires capacitor if internal

regulator is used)

USB_H1_VBUS

USB_OTG_VBUS

HDMI_DDCCEC

D10

E9

Primary supply for the 3 V regulator

K2

Analog Ground (Ground reference for the Hot

Plug Detect signal)

FA_ANA

A5

C8

—

GPANAIO

Analog output for NXP use only. This output

must remain unconnected.

VDD_FA

B5

—

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Table 96. 21 x 21 mm Supplies Contact Assignments (continued)

Supply Rail Name

Ball(s) Position(s)

Remark

ZQPAD

AE17

Connect ZQPAD to an external 240 Ω 1%

resistor to GND. This is a reference used

during DRAM output buffer driver calibration.

NC

For i.MX 6DualLite:

A12, A14, B12, B14, C14, E1, E2, F1, F2, G12, G13,

N12

These signals are not functional and must

remain unconnected by the user.

For i.MX 6Solo:

A12, A14, B12, B14, C14, E1, E2, F1, F2, G12, G13,

N12, W25, Y17, Y18, Y19, Y20, Y21, Y22, Y23, Y25,

AA17, AA18, AA20, AA21, AA23, AA24, AA25, AB18,

AB19, AB20, AB21, AB22, AB23, AB25, AC18, AC19,

AC20, AC21, AC22, AC23, AC24, AC25, AD18, AD20,

AD21, AD23, AD24, AD25, AE18, AE19, AE20, AE21,

AE22, AE23, AE24

Table 97 shows an alpha-sorted list of functional contact assignments for the 21 x 21 mm package.

Table 97. 21 x 21 mm Functional Contact Assignments

Out of Reset Condition¹

Default

Ball Name

Ball

Power Group

Ball Type

Mode

(Reset

Mode)

Input/

Output

Default Function

Value²

BOOT_MODE0

BOOT_MODE1

CLK1_N

C12

F12

C7

D7

C5

D5

F4

VDD_SNVS_IN

VDDHIGH_CAP

NVCC_MIPI

NVCC_CSI

GPIO

ALT0

—

SRC_BOOT_MODE0

SRC_BOOT_MODE1

CLK1_N

Input 100 kΩ pull-down

—

CLK1_P

—

CLK1_P

—

CLK2_N

—

CLK2_N

—

CLK2_P

—

CLK2_P

—

CSI_CLK0M

CSI_CLK0P

CSI_D0M

ANALOG

GPIO

—

CSI_CLK_N

CSI_CLK_P

CSI_DATA0_N

CSI_DATA0_P

CSI_DATA1_N

CSI_DATA1_P

GPIO5_IO28

GPIO5_IO29

GPIO5_IO30

GPIO5_IO31

GPIO6_IO00

GPIO6_IO01

GPIO6_IO02

—

F3

—

E4

E3

D1

D2

M1

M3

M2

L1

—

CSI_D0P

—

CSI_D1M

—

CSI_D1P

—

CSI0_DAT10

CSI0_DAT11

CSI0_DAT12

CSI0_DAT13

CSI0_DAT14

CSI0_DAT15

CSI0_DAT16

ALT5

Input

100 kΩ pull-up

NVCC_CSI

GPIO

NVCC_CSI

GPIO

NVCC_CSI

GPIO

M4

M5

L4

NVCC_CSI

GPIO

NVCC_CSI

GPIO

NVCC_CSI

GPIO

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Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

CSI0_DAT17

CSI0_DAT18

CSI0_DAT19

CSI0_DAT4

L3

M6

NVCC_CSI

NVCC_LCD

GPIO

ALT5

GPIO6_IO03

GPIO6_IO04

GPIO6_IO05

GPIO5_IO22

GPIO5_IO23

GPIO5_IO24

GPIO5_IO25

GPIO5_IO26

GPIO5_IO27

GPIO5_IO20

GPIO5_IO19

GPIO5_IO18

GPIO5_IO21

GPIO4_IO16

GPIO4_IO17

GPIO4_IO18

GPIO4_IO19

GPIO4_IO20

GPIO4_IO21

GPIO4_IO22

GPIO4_IO31

GPIO5_IO05

GPIO5_IO06

GPIO5_IO07

GPIO5_IO08

GPIO5_IO09

GPIO5_IO10

GPIO5_IO11

GPIO5_IO12

GPIO5_IO13

GPIO4_IO23

GPIO5_IO14

GPIO5_IO15

GPIO5_IO16

GPIO5_IO17

GPIO4_IO24

Input

100 kΩ pull-up

L6

N1

CSI0_DAT5

P2

CSI0_DAT6

N4

CSI0_DAT7

N3

CSI0_DAT8

N6

CSI0_DAT9

N5

CSI0_DATA_EN

CSI0_MCLK

CSI0_PIXCLK

CSI0_VSYNC

DI0_DISP_CLK

DI0_PIN15

P3

P4

P1

N2

N19

N21

N25

N20

P25

P24

P22

R21

T23

T24

R20

U25

T22

T21

U24

V25

U23

P23

U22

T20

V24

W24

P21

DI0_PIN2

DI0_PIN3

DI0_PIN4

DISP0_DAT0

DISP0_DAT1

DISP0_DAT10

DISP0_DAT11

DISP0_DAT12

DISP0_DAT13

DISP0_DAT14

DISP0_DAT15

DISP0_DAT16

DISP0_DAT17

DISP0_DAT18

DISP0_DAT19

DISP0_DAT2

DISP0_DAT20

DISP0_DAT21

DISP0_DAT22

DISP0_DAT23

DISP0_DAT3

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Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

DISP0_DAT4

DISP0_DAT5

DISP0_DAT6

DISP0_DAT7

DISP0_DAT8

DISP0_DAT9

DRAM_A0

P20

R25

NVCC_LCD

GPIO

DDR

ALT5

ALT0

GPIO4_IO25

GPIO4_IO26

Input

100 kΩ pull-up

Low

R23

NVCC_LCD

GPIO4_IO27

Input

R24

NVCC_LCD

GPIO4_IO28

Input

R22

NVCC_LCD

GPIO4_IO29

Input

T25

NVCC_LCD

GPIO4_IO30

Input

AC14

AB14

AA15

AC12

AD12

AC17

AA12

Y12

NVCC_DRAM

DRAM_ADDR00

DRAM_ADDR01

DRAM_ADDR10

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

DRAM_ADDR14

DRAM_ADDR15

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_CAS

Output

Input

DRAM_A1

Low

DRAM_A10

DRAM_A11

DRAM_A12

DRAM_A13

DRAM_A14

DRAM_A15

DRAM_A2

Low

AA14

Y14

Low

DRAM_A3

Low

DRAM_A4

W14

AE13

AC13

Y13

Low

DRAM_A5

Low

DRAM_A6

Low

DRAM_A7

Low

DRAM_A8

AB13

AE12

AE16

Y16

Low

DRAM_A9

Low

DRAM_CAS

DRAM_CS0

DRAM_CS1

DRAM_D0

DRAM_D1

DRAM_D10

DRAM_D11

DRAM_D12

DRAM_D13

DRAM_D14

DRAM_D15

DRAM_D16

DRAM_D17

DRAM_D18

Low

DRAM_CS0

Low

AD17

AD2

AE2

DRAM_CS1

Low

DRAM_DATA00

DRAM_DATA01

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

100 kΩ pull-up

Input

AA6

Input

AE7

Input

AB5

Input

AC5

AB6

Input

AC7

AB7

Input

AA8

Input

AB9

Input

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

DRAM_D19

DRAM_D2

Y9

AC4

Y7

NVCC_DRAM

DDR

ALT0

DRAM_DATA19

DRAM_DATA02

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA03

DRAM_DATA30

DRAM_DATA31

Input

100 kΩ pull-up

DRAM_D20

DRAM_D21

DRAM_D22

DRAM_D23

DRAM_D24

DRAM_D25

DRAM_D26

DRAM_D27

DRAM_D28

DRAM_D29

DRAM_D3

Y8

AC8

AA9

AE9

Y10

AE11

AB11

AC9

AD9

AA5

AD11

AC11

DRAM_D30

DRAM_D31

Note: DRAM_D32 to DRAM_D63 are only available for i.MX 6DualLite chip; for i.MX 6Solo chip, these pins are NC.

DRAM_D32

DRAM_D33

DRAM_D34

DRAM_D35

DRAM_D36

DRAM_D37

DRAM_D38

DRAM_D39

DRAM_D40

DRAM_D41

DRAM_D42

DRAM_D43

DRAM_D44

DRAM_D45

DRAM_D46

DRAM_D47

DRAM_D48

DRAM_D49

DRAM_D50

DRAM_D51

AA17

AA18

AC18

AE19

Y17

NVCC_DRAM

DDR

ALT0

DRAM_DATA32

DRAM_DATA33

DRAM_DATA34

DRAM_DATA35

DRAM_DATA36

DRAM_DATA37

DRAM_DATA38

DRAM_DATA39

DRAM_DATA40

DRAM_DATA41

DRAM_DATA42

DRAM_DATA43

DRAM_DATA44

DRAM_DATA45

DRAM_DATA46

DRAM_DATA47

DRAM_DATA48

DRAM_DATA49

DRAM_DATA50

DRAM_DATA51

Input

100 kΩ pull-up

Y18

AB19

AC19

Y19

AB20

AB21

AD21

Y20

AA20

AE21

AC21

AC22

AE22

AE24

AC24

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

DRAM_D52

DRAM_D53

DRAM_D54

DRAM_D55

DRAM_D56

DRAM_D57

DRAM_D58

DRAM_D59

DRAM_D60

DRAM_D61

DRAM_D62

DRAM_D63

DRAM_D4

AB22

AC23

AD25

AC25

AB25

AA21

Y25

NVCC_DRAM

DDR

DDRCLK

—

ALT0

—

DRAM_DATA52

DRAM_DATA53

DRAM_DATA54

DRAM_DATA55

DRAM_DATA56

DRAM_DATA57

DRAM_DATA58

DRAM_DATA59

DRAM_DATA60

DRAM_DATA61

DRAM_DATA62

DRAM_DATA63

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DQM0

Input

100 kΩ pull-up

Low

Input

Y22

Input

AB23

AA23

Y23

Input

W25

AC1

Input

DRAM_D5

AD1

Input

DRAM_D6

AB4

Input

DRAM_D7

AE4

Input

DRAM_D8

AD5

Input

DRAM_D9

AE5

Input

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_DQM4

DRAM_DQM5

DRAM_DQM6

DRAM_DQM7

DRAM_RAS

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_SDCKE1

AC3

Output

—

AC6

DRAM_DQM1

Low

AB8

DRAM_DQM2

Low

AE10

AB18

AC20

AD24

Y21

DRAM_DQM3

Low

DRAM_DQM4

Low

DRAM_DQM5

Low

DRAM_DQM6

Low

DRAM_DQM7

Low

AB15

Y6

DRAM_RAS

Low

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_SDCKE1

DRAM_SDCLK0_P

DRAM_SDCLK0_N

DRAM_SDCLK1_P

Low

AC15

Y15

Low

AB12

Y11

Low

AA11

Low

DRAM_SDCLK_0 AD15

DRAM_SDCLK_0_B AE15

DRAM_SDCLK_1 AD14

Low

—

DDRCLK

ALT0

Output

Low

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

DRAM_SDCLK_1_B AE14

NVCC_DRAM

NVCC_MIPI

NVCC_EIM

—

DDR

—

ALT0

—

DRAM_SDCLK1_N

DRAM_ODT0

—

Output

Input

—

Low

Hi-Z

—

DRAM_SDODT0

DRAM_SDODT1

DRAM_SDQS0

DRAM_SDQS0_B

DRAM_SDQS1

DRAM_SDQS1_B

DRAM_SDQS2

DRAM_SDQS2_B

DRAM_SDQS3

AC16

AB17

AE3

DDR

DRAM_ODT1

DDRCLK

—

DRAM_SDQS0_P

DRAM_SDQS0_N

DRAM_SDQS1_P

DRAM_SDQS1_N

DRAM_SDQS2_P

DRAM_SDQS2_N

DRAM_SDQS3_P

DRAM_SDQS3_N

DRAM_SDQS4_P

DRAM_SDQS4_N

DRAM_SDQS5_P

DRAM_SDQS5_N

DRAM_SDQS6_P

DRAM_SDQS6_N

DRAM_SDQS7_P

DRAM_SDQS7_N

DRAM_SDWE

AD3

AD6

AE6

DDRCLK

—

ALT0

—

Input

—

Hi-Z

—

AD8

AE8

DDRCLK

—

ALT0

—

Input

—

Hi-Z

—

AC10

DDRCLK

—

ALT0

—

Input

—

Hi-Z

—

DRAM_SDQS3_B AB10

DRAM_SDQS4 AD18

DRAM_SDQS4_B AE18

DRAM_SDQS5 AD20

DRAM_SDQS5_B AE20

DRAM_SDQS6 AD23

DRAM_SDQS6_B AE23

DRAM_SDQS7 AA25

DRAM_SDQS7_B AA24

DDRCLK

—

ALT0

—

Input

—

Hi-Z

—

DDRCLK

—

ALT0

—

Input

—

Hi-Z

—

DDRCLK

—

ALT0

—

Input

—

Hi-Z

—

DDRCLK

—

ALT0

—

Input

—

Hi-Z

—

DRAM_SDWE

DSI_CLK0M

DSI_CLK0P

DSI_D0M

DSI_D0P

DSI_D1M

DSI_D1P

EIM_A16

EIM_A17

EIM_A18

EIM_A19

EIM_A20

EIM_A21

EIM_A22

EIM_A23

EIM_A24

EIM_A25

AB16

H3

DDR

ALT0

—

Output

—

Low

—

ANALOG

GPIO

DSI_CLK_N

H4

—

DSI_CLK_P

—

G2

—

DSI_DATA0_N

DSI_DATA0_P

DSI_DATA1_N

DSI_DATA1_P

EIM_ADDR16

—

G1

—

H2

—

H1

—

H25

G24

J22

G25

H22

H23

F24

J21

F25

H19

ALT0

Output

Low

NVCC_EIM

GPIO

EIM_ADDR17

NVCC_EIM

GPIO

EIM_ADDR18

NVCC_EIM

GPIO

EIM_ADDR19

NVCC_EIM

GPIO

EIM_ADDR20

NVCC_EIM

GPIO

EIM_ADDR21

NVCC_EIM

GPIO

EIM_ADDR22

NVCC_EIM

GPIO

EIM_ADDR23

NVCC_EIM

GPIO

EIM_ADDR24

NVCC_EIM

GPIO

EIM_ADDR25

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

EIM_BCLK

EIM_CS0

EIM_CS1

EIM_D16

EIM_D17

EIM_D18

EIM_D19

EIM_D20

EIM_D21

EIM_D22

EIM_D23

EIM_D24

EIM_D25

EIM_D26

EIM_D27

EIM_D28

EIM_D29

EIM_D30

EIM_D31

EIM_DA0

EIM_DA1

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_EB0

N22

H24

J23

NVCC_EIM

GPIO

ALT0

ALT5

ALT0

EIM_BCLK

EIM_CS0

Output

Input

Low

High

EIM_CS1

High

C25

F21

D24

G21

G20

H20

E23

D25

F22

G22

E24

E25

G23

J19

GPIO3_IO16

GPIO3_IO17

GPIO3_IO18

GPIO3_IO19

GPIO3_IO20

GPIO3_IO21

GPIO3_IO22

GPIO3_IO23

GPIO3_IO24

GPIO3_IO25

GPIO3_IO26

GPIO3_IO27

GPIO3_IO28

GPIO3_IO29

GPIO3_IO30

GPIO3_IO31

EIM_AD00

EIM_AD01

EIM_AD10

EIM_AD11

EIM_AD12

EIM_AD13

EIM_AD14

EIM_AD15

EIM_AD02

EIM_AD03

EIM_AD04

EIM_AD05

EIM_AD06

EIM_AD07

EIM_AD08

EIM_AD09

EIM_EB0

100 kΩ pull-up

Input

Input 100 kΩ pull-down

Input

100 kΩ pull-up

J20

H21

L20

J25

Input 100 kΩ pull-down

Input

Output

100 kΩ pull-up

High

M22

M20

M24

M23

N23

N24

L21

K24

L22

L23

K25

L25

L24

M21

K21

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

EIM_EB1

EIM_EB2

K23

E22

F23

K22

J24

K20

M25

U21

V20

V23

V22

W23

W21

W22

V21

U20

W20

T5

NVCC_EIM

NVCC_ENET

NVCC_GPIO

HDMI

GPIO

—

ALT0

ALT5

ALT0

ALT5

—

EIM_EB1

GPIO2_IO30

GPIO2_IO31

EIM_LBA

Output

Input

Output

Input

High

100 kΩ pull-up

High

EIM_EB3

EIM_LBA

EIM_OE

High

EIM_RW

High

EIM_WAIT

ENET_CRS_DV

ENET_MDC

ENET_MDIO

ENET_REF_CLK³

ENET_RX_ER

ENET_RXD0

ENET_RXD1

ENET_TX_EN

ENET_TXD0

ENET_TXD1

GPIO_0

EIM_WAIT

100 kΩ pull-up

GPIO1_IO25

GPIO1_IO31

GPIO1_IO22

GPIO1_IO23

GPIO1_IO24

GPIO1_IO27

GPIO1_IO26

GPIO1_IO28

GPIO1_IO30

GPIO1_IO29

GPIO1_IO00

GPIO1_IO01

GPIO7_IO11

GPIO7_IO12

GPIO7_IO13

GPIO4_IO05

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

HDMI_TX_CLK_N

HDMI_TX_CLK_P

HDMI_TX_DATA0_N

HDMI_TX_DATA0_P

HDMI_TX_DATA1_N

Input 100 kΩ pull-down

GPIO_1

T4

Input

—

100 kΩ pull-up

—

GPIO_16

R2

GPIO_17

R1

GPIO_18

P6

GPIO_19

P5

GPIO_2

T1

GPIO_3

R7

GPIO_4

R6

GPIO_5

R4

GPIO_6

T3

GPIO_7

R3

GPIO_8

R5

GPIO_9

T2

HDMI_CLKM

HDMI_CLKP

HDMI_D0M

HDMI_D0P

HDMI_D1M

J5

J6

HDMI

—

K5

HDMI

—

K6

HDMI

—

J3

HDMI

—

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

HDMI_D1P

HDMI_D2M

J4

K3

K4

K1

H6

H5

G5

G6

C3

C2

W5

U7

W6

U5

T6

HDMI

—

HDMI_TX_DATA1_P

HDMI_TX_DATA2_N

HDMI_TX_DATA2_P

HDMI_TX_HPD

JTAG_MODE

JTAG_TCK

—

HDMI

—

HDMI_D2P

HDMI

—

HDMI_HPD

HDMI

—

JTAG_MOD

NVCC_JTAG

NVCC_GPIO

NVCC_LVDS2P5

GPIO

—

ALT0

ALT5

—

Input

Output

Input

100 kΩ pull-up

47 kΩ pull-up

Low

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

47 kΩ pull-up

100 kΩ pull-up

JTAG_TRSTB

KEY_COL0

JTAG_TRSTB

GPIO4_IO06

KEY_COL1

GPIO4_IO08

KEY_COL2

GPIO4_IO10

KEY_COL3

GPIO4_IO12

KEY_COL4

GPIO4_IO14

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

LVDS0_CLK_N

LVDS0_CLK_P

LVDS0_TX0_N

LVDS0_TX0_P

LVDS0_TX1_N

LVDS0_TX1_P

LVDS0_TX2_N

LVDS0_TX2_P

LVDS0_TX3_N

LVDS0_TX3_P

LVDS1_CLK_N

LVDS1_CLK_P

LVDS1_TX0_N

LVDS1_TX0_P

LVDS1_TX1_N

LVDS1_TX1_P

V6

U6

W4

T7

GPIO4_IO07

GPIO4_IO09

GPIO4_IO11

GPIO4_IO13

V5

V4

V3

U2

U1

U4

U3

V2

V1

W2

W1

Y3

Y4

Y1

Y2

GPIO4_IO15

Input 100 kΩ pull-down

LVDS0_CLK_N

LVDS0_CLK_P

LVDS0_TX0_N

LVDS0_TX0_P

LVDS0_TX1_N

LVDS0_TX1_P

LVDS0_TX2_N

LVDS0_TX2_P

LVDS0_TX3_N

LVDS0_TX3_P

LVDS1_CLK_N

LVDS1_CLK_P

LVDS1_TX0_N

LVDS1_TX0_P

LVDS1_TX1_N

LVDS1_TX1_P

—

Input

—

Keeper

—

ALT0

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

AA2 NVCC_LVDS2P5

AA1 NVCC_LVDS2P5

—

ALT0

Input

Keeper

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

LVDS1_TX2_N

LVDS1_TX2_P

LVDS1_TX3_N

LVDS1_TX3_P

MLB_CN

AB1 NVCC_LVDS2P5

AB2 NVCC_LVDS2P5

AA3 NVCC_LVDS2P5

AA4 NVCC_LVDS2P5

—

LVDS1_TX2_N

LVDS1_TX2_P

LVDS1_TX3_N

LVDS1_TX3_P

MLB_CLK_N

MLB_CLK_P

MLB_DATA_N

MLB_DATA_P

MLB_SIG_N

MLB_SIG_P

GPIO6_IO08

GPIO6_IO07

GPIO6_IO11

GPIO6_IO14

GPIO6_IO15

GPIO6_IO16

GPIO2_IO00

GPIO2_IO01

GPIO2_IO02

GPIO2_IO03

GPIO2_IO04

GPIO2_IO05

GPIO2_IO06

GPIO2_IO07

GPIO6_IO10

GPIO6_IO09

SRC_ONOFF

PCIE_RX_N

PCIE_RX_P

PCIE_TX_N

PCIE_TX_P

—

Input

—

ALT0

—

Keeper

—

ALT0

—

Input

—

Keeper

A11

B11

B10

A10

A9

VDDHIGH_CAP

NVCC_NANDF

VDD_SNVS_IN

PCIE_VPH

—

MLB_CP

—

MLB_DN

—

MLB_DP

—

MLB_SN

—

MLB_SP

B9

—

NANDF_ALE

NANDF_CLE

NANDF_CS0

NANDF_CS1

NANDF_CS2

NANDF_CS3

NANDF_D0

NANDF_D1

NANDF_D2

NANDF_D3

NANDF_D4

NANDF_D5

NANDF_D6

NANDF_D7

NANDF_RB0

NANDF_WP_B

ONOFF

A16

C15

F15

C16

A17

D16

A18

C17

F16

D17

A19

B18

E17

C18

B16

E15

D12

B1

GPIO

—

ALT5

ALT0

—

Input

—

100 kΩ pull-up

—

PCIE_RXM

PCIE_RXP

PCIE_TXM

PCIE_TXP

B2

PCIE_VPH

—

A3

PCIE_VPH

—

B3

PCIE_VPH

—

PMIC_ON_REQ

D11

VDD_SNVS_IN

GPIO

ALT0

SNVS_PMIC_ON_REQ Output Open drain with

PU(100K) enable

PMIC_STBY_REQ F11

VDD_SNVS_IN

NVCC_RGMII

GPIO

DDR

ALT0

ALT5

CCM_PMIC_STBY_REQ Output

Low

POR_B

C11

C24

SRC_POR_B

GPIO6_IO25

Input

100 kΩ pull-up

RGMII_RD0

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

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Package Information and Contact Assignments

Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

RGMII_RD1

RGMII_RD2

RGMII_RD3

RGMII_RX_CTL

RGMII_RXC

RGMII_TD0

RGMII_TD1

RGMII_TD2

RGMII_TD3

RGMII_TX_CTL

RGMII_TXC

RTC_XTALI

RTC_XTALO

SD1_CLK

B23

B24

D23

D22

B25

C22

F20

E21

A24

C23

D21

D9

NVCC_RGMII

VDD_SNVS_CAP

NVCC_SD1

NVCC_SD2

NVCC_SD3

DDR

—

ALT5

—

GPIO6_IO27

GPIO6_IO28

GPIO6_IO29

GPIO6_IO24

GPIO6_IO30

GPIO6_IO20

GPIO6_IO21

GPIO6_IO22

GPIO6_IO23

GPIO6_IO26

GPIO6_IO19

RTC_XTALI

RTC_XTALO

GPIO1_IO20

GPIO1_IO18

GPIO1_IO16

GPIO1_IO17

GPIO1_IO19

GPIO1_IO21

GPIO1_IO10

GPIO1_IO11

GPIO1_IO15

GPIO1_IO14

GPIO1_IO13

GPIO1_IO12

GPIO7_IO03

GPIO7_IO02

GPIO7_IO04

GPIO7_IO05

GPIO7_IO06

GPIO7_IO07

GPIO7_IO01

GPIO7_IO00

GPIO6_IO18

GPIO6_IO17

GPIO7_IO08

Input

100 kΩ pull-up

Input 100 kΩ pull-down

Input

100 kΩ pull-up

Input 100 kΩ pull-down

—

C9

—

D20

B21

A21

C20

E19

F18

C21

F19

A22

E20

A23

B22

D14

B13

E14

F14

A15

B15

D13

C13

E13

F13

D15

GPIO

ALT5

Input

100 kΩ pull-up

SD1_CMD

SD1_DAT0

SD1_DAT1

SD1_DAT2

SD1_DAT3

SD2_CLK

SD2_CMD

SD2_DAT0

SD2_DAT1

SD2_DAT2

SD2_DAT3

SD3_CLK

SD3_CMD

SD3_DAT0

SD3_DAT1

SD3_DAT2

SD3_DAT3

SD3_DAT4

SD3_DAT5

SD3_DAT6

SD3_DAT7

SD3_RST

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Table 97. 21 x 21 mm Functional Contact Assignments (continued)

Out of Reset Condition¹

Default

Mode

(Reset

Mode)

Ball Name

Ball

Power Group

Ball Type

Input/

Default Function

Output

Value²

SD4_CLK

SD4_CMD

E16

B17

D18

B19

F17

A20

E18

C19

B20

D19

E11

E12

F10

E10

B8

NVCC_NANDF

VDD_SNVS_IN

VDDUSB_CAP

NVCC_PLL_OUT

GPIO

—

ALT5

ALT0

—

GPIO7_IO10

GPIO7_IO09

GPIO2_IO08

GPIO2_IO09

GPIO2_IO10

GPIO2_IO11

GPIO2_IO12

GPIO2_IO13

GPIO2_IO14

GPIO2_IO15

SNVS_TAMPER

TCU_TEST_MODE

USB_H1_DN

USB_H1_DP

USB_OTG_CHD_B

USB_OTG_DN

USB_OTG_DP

XTALI

Input

100 kΩ pull-up

SD4_DAT0

SD4_DAT1

SD4_DAT2

SD4_DAT3

SD4_DAT4

SD4_DAT5

SD4_DAT6

SD4_DAT7

TAMPER

Input 100 kΩ pull-down

TEST_MODE

USB_H1_DN

USB_H1_DP

USB_OTG_CHD_B

USB_OTG_DN

USB_OTG_DP

XTALI

—

B6

—

A6

—

A7

—

XTALO

B7

—

XTALO

1

2

The state immediately after reset and before ROM firmware or software has executed.

Variance of the pull-up and pull-down strengths are shown in the tables as follows:

• Table 23, "GPIO DC Parameters," on page 40

• Table 24, "LPDDR2 I/O DC Electrical Parameters," on page 41

• Table 25, "DDR3/DDR3L I/O DC Electrical Characteristics," on page 42

3

ENET_REF_CLK is used as a clock source for MII and RGMII modes only. RGMII mode uses either GPIO_16 or

RGMII_TX_CTL as a clock source. For more information on these clocks, see the device Reference Manual and the Hardware

Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

Table 98. Signals with Differing Before Reset and After Reset States

Before Reset State

Ball Name

Input/Output

Value

EIM_A16

EIM_A17

EIM_A18

EIM_A19

Input

PD (100K)

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Table 98. Signals with Differing Before Reset and After Reset States (continued)

Before Reset State

Ball Name

Input/Output

Value

EIM_A20

EIM_A21

EIM_A22

EIM_A23

EIM_A24

EIM_A25

EIM_DA0

EIM_DA1

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_EB0

EIM_EB1

EIM_EB2

EIM_EB3

EIM_LBA

EIM_RW

EIM_WAIT

GPIO_17

Input

Output

PD (100K)

Drive state unknown (x)

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Table 98. Signals with Differing Before Reset and After Reset States (continued)

Before Reset State

Ball Name

Input/Output

Value

GPIO_19

Output

Drive state unknown (x)

KEY_COL0

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6.2.3

21 x 21 mm, 0.8 mm Pitch Ball Map

Table 99 shows the 21 x 21 mm, 0.8 mm pitch ball map for the i.MX 6Solo.

Table 99. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6Solo

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Table 99. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6Solo (continued)

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Table 99. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6Solo (continued)

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Table 99. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6Solo (continued)

Table 100 shows the 21 x 21 mm, 0.8 mm pitch ball map for the i.MX 6DualLite.

Table 100. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6DualLite

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Table 100. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6DualLite (continued)

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Table 100. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6DualLite (continued)

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Table 100. 21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6DualLite (continued)

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Revision History

7 Revision History

Table 101 provides the current revision history for this data sheet. Table 102 provides a revision history for

previous revisions.

Table 101. i.MX 6Solo/6DualLite Data Sheet Document Rev. 9 History

Rev.

Number

Date

Substantive Changes

9

10/2018 Changes to Revision 9 include the following:

• Table 3, "Special Signal Considerations," on page 21: Corrected,

– Row: NC, from “These signals are No Connected …” to read, “These signals are not functional and

must remain unconnected by the user.”

• Table 8, "Operating Ranges," on page 26: Corrected footnote 6:

– Changed from: “When VDD_SOC_IN does not supply… then maximum setting can be 1.3V.”

– Changed to: “When using VDD_SOC_CAP to supply the PCIE_VP and PCIE_VPTX, the maximum

setting is 1.175V. …”

• Table 53, "eMMC4.4/4.41 Interface Timing Specification," on page 80,

– Row: SD2, uSDHC Output Delay: Changed t_ODfrom 2.5ns minimum to 2.8ns and 7.1ns maximum to

6.8ns.

• Table 96, "21 x 21 mm Supplies Contact Assignments," on page 140: Corrected,

– Last row: NC, from “—” to read, These signals are not functional and must remain unconnected by the

user.

8

09/2017 • Replaced ipp_dse with DSE throughout.

• Section 1, “Introduction: Replaced text “low voltage DDR3” with “DDR3L” in the features list of i.MX

6Solo/6DualLite applications processors.

• Table 1, "Example Orderable Part Numbers," on page 3: Added orderable part numbers.

• Figure 1: Updated to include Rev 1.4 in Silicon Revision section.

• Section 2.1, “Block Diagram: Updated WEIM with EIM in the block diagram.

• Table 2, "i.MX 6Solo/6DualLite Modules List," on page 11: Rearranged alphabetically.

• Table 6, "Absolute Maximum Ratings," on page 24:

– Removed VDD_HIGH_IN supply voltage (LDO bypass) parameter.

– Max. value of VDD_HIGH_CAP supply output voltage corrected to 2.85V.

• Table 22: Updated test condition of “XTALI input leakage current at startup” parameter; replaced 32KHz RTC

with 24MHz.

• Added Section 4.6.4, “RGMII I/O 2.5V I/O DC Electrical Parameters.

• Section 4.8.2, “DDR I/O Output Buffer Impedance: Modified introductory text.

• Corrected Figure 22, "Asynchronous A/D Muxed Write Access," on page 60.

• Table 53, "eMMC4.4/4.41 Interface Timing Specification," on page 80:

– Added the following footnote to Card Input Clock section: 1 Clock duty cycle will be in the range of 47% to

53%.

– Min. value of uSDHC Input Setup Time reduced to 1.7ns.

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Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories

Date Substantive Changes

Rev.

Number

7

10/2016 • Figure 1, "Part Number Nomenclature—i.MX 6Solo and 6DualLite," on page 5: Added to Silicon

Revision block: Revision 1.2 and 1.3 and associated Mask ID.

• Table 6, "Absolute Maximum Ratings," on page 24:

– NVCC_DRAM maximum value changed to 1.975 V.

– Included footnote to NVCC_DRAM maximum value regarding maximum voltage allowance.

– Added row to Vin/Vout I/O supply voltage, separating DDR pins and non-DDR pins and included

footnote regarding maximum voltage allowance.

• Table 8, "Operating Ranges," on page 26: Added footnotes within the Comments column for the Run

Mode, LDO Enabled row; VDD_SOC_IN maximum values.

• Section 4.6.3, “DDR I/O DC Parameters: Added reference for more DDR details to see the MMDC

section.

Moved JEDEC standard information to footnote.

• Section 4.7.2, “DDR I/O AC Parameters: Added reference for more DDR details to see the MMDC

section.

Moved JEDEC standard information to footnote.

• Table 44, "i.MX 6Solo Supported DDR3/DDR3L/LPDDR2 Configurations," on page 63: Changed

LPDDR2 Channel column from “Dual” to “Single.”

• Table 45, "i.MX 6DualLite Supported DDR3/DDR3L/LPDDR2 Configurations," on page 64: Added

LPDDR2 Dual Channel column.

• Table 95, "21 x 21, 0.8 mm BGA Package Details," on page 139: Correction to package total thickness.

• Table 97, "21 x 21 mm Functional Contact Assignments," on page 142: DRAM_SDCKLn rows, reverted

to “Low” rather than “0” in the Value column.

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Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories (continued)

Rev.

Number

Date

Substantive Changes

6

8/2016 • Changed throughout:

- LVDDR3 to DDR3L

- Changed terminology from “floating” to “not connected”.

• Table 2, "i.MX 6Solo/6DualLite Modules List," on page 11:

- uSDHC1–4, SD/MMC and SDXC Enhanced Multi-Media Card/Secure Digital Host Controller row:

Added new bullet at top: “Conforms to the SD Host Controller…”.

- eCSPI1-4 row: removed from the Brief Description column, “with data rate up to 52Mbit/s.”

- BCH row, removed from Brief Description column, “encryption/decryption”.

• Table 3, "Special Signal Considerations," on page 21:

- GPANAIO row, modified remarks to be NXP use only.

- SRC_POR_B row: removed reference to internal POR which is not supported on device.

- TEST_MODE row: modified remarks to be NXP use only and added tie to Vss or remain unconnected.

• Table 6, "Absolute Maximum Ratings," on page 24” throughout table: clarified parameter descriptions

including adding LDO state. Clarified symbol names.

- Added row, RGMII I/O supply voltage.

- Added VDD_HIGH_CAP supply voltage row for LDO output.

- Added to USB supply voltage row: USB_OTG_CHD_B.

- All maximum voltages increased (improved).

• Section 4.1.2, “Thermal Resistance: added NOTE.

• Table 8, "Operating Ranges," on page 26: Changed minimum parameter of Run mode: LDO enabled

from 1.175 to 1.25 V.

• Section 4.2.1, “Power-Up Sequence”: Removed references to the internal POR function. Internal POR

is not supported. Removed fourth and fifth bullets.

• Section 4.2.3, “Power Supplies Usage”: Added NOTE, “When the PCIE interface is not used…”.

• Section 4.5.2, “OSC32K”: Removed battery resistor (coin cell) calculation.

• Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters”:

- Added 3 rows: Input capacitance; Startup current; and DC input current.

- Added footnote to RTC_XTALI high-level DC input voltage at the Max parameter.

- Added NOTE following table: “The Vil and Vih only apply when external clock source is used…”.

• Section 4.9.4, “Multi-Mode DDR Controller (MMDC)”: this new section added, replacing the original

section 4.9.4 “DDR SRAM Specific Parameters (DDR3/DDR3L and LPDDR2)”.

• Figure 36, "ECSPI Master Mode Timing Diagram," on page 73: Added note, “ECSPI_MOSI always…”.

• Figure 37, "ECSPI Slave Mode Timing Diagram," on page 74: Added note, “ECSPI_MOSI always

driven…”.

• Figure 42, "SDR50/SDR104 Timing," on page 81: Aligned SD4 and SD5.

• Table 54, "SDR50/SDR104 Interface Timing Specification," on page 81:

- Corrected Clock High Time ID to SD3.

- Changed SD2 and SD3 Min and max values to 0.46 and 0.54.

- Changed SD5 Max to 0.74.

• Table 64, "Camera Input Signal Cross Reference, Format, and Bits Per Cycle," on page 93: Changed

RGB565 column heading from 2 to 1 cycle.

• Table 97, "21 x 21 mm Functional Contact Assignments," on page 142:

- Table row: DRAM_SDCLK0 and DRAM_SDCLK1 changed Out of Reset Condition from Low to 0.

- Added to ZQPAD row: requirement to add resistor to GND.

5

6/2015 • Table 8, “Operating Ranges,” Run mode: LDO enabled row; Changed comments for VDD_ARM_IN,

from “1.05V minimum for operation up to 396MHz” to “1.125V minimum for operation up to 396MHz”.

• Table 3, “Special Signal Considerations,” XTALI/XTALO row: Changed from “The crystal must be

rated...”, to “See Hardware Development Guide”.

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Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories (continued)

Rev.

Number

Date

Substantive Changes

Rev. 4 12/2014 • Table 1, "Example Orderable Part Numbers," on page 3: Speed Grade footnote added as follows:

If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.

• Table 1, "Example Orderable Part Numbers," on page 3: Added (4) devices; SCIMX6U5DVM10BC/CC

and SCIMX6S5DVM10BC/CC.

• Figure 1, “Part Number Nomenclature—i.MX 6Solo and 6DualLite”: Added Silicon Rev 1.3. to diagram

• Table 2, Modules List, UART 1–5 Description changed: baud rate up from 5MHz to 5Mbps.

• Added Figure 2, "Example Part Marking," on page 5.

• Section 1.2, “Features”: under, Miscellaneous IPs and interfaces: Changed UARTs bullet, from “up to

4.0 Mbps”, to “up to 5.0 Mbps”.

• Table 8, “Operating Ranges,” on page 29:

— Changed Run mode: VDD_ARM_IN minimum value from 1.05 to 1.125V; for operation up to 396

MHz. and changed LDO bypassed maximum value from 1.225V to 1.21V; for VDD_SOC_IN.

— Changed PCIe supply voltages; PCIE_VP/PCIE_VPTX maximum value from 1.225V to 1.21V

• Table 10, "Maximum Supply Currents," on page 29;

— Changed VDD_ARM_IN from single condition to include DualLite and Solo conditions with Maximum

current values of 2200 and 1320 mA, respectively.

— Added footnote for NVCC_LVDS2P5 supply.

• Table 38, “Reset Timing Parameters”: Removed footnote regarding SRC_POR_B rise and fall times.

• Section 4.9.3, “External Interface Module (EIM)”: Changed first paragraph to describe two systems

clocks used with EIM: ACLK_EIM_SLOW_CLK_ROOT and ACLK_EXSC (for synchronous mode).

• Table 31, “DDR I/O DDR3/DDR3L Mode AC Parameters”; Added footnote about extended range for Vix.

• Table 48, “DDR3/DDR3L Timing Parameter Table,” on page 76; Added DDR0, tCK(avg) and parameter

values. Changed symbol names DDR1 through DDR7 to include avg or base; changed minimum

parameter values for DDR4–DDR7. Added footnote about tIS and tIH base values.

• Figure 25, “DDR3 Command and Address Timing Parameters,” on page 76; Added DDR0.

• Table 49, “DDR3/DDR3L Write Cycle,” on page 77; Changed symbol names of DDR17 and DDR18 to

include base(AC150/DC100); Changed Units from tCK to tCK(avg).

• Table 46, “LPDDR2 Write Cycle,” on page 64; Changed LP21 min/max parameter values from

-0.25/+0.25 to 0.75/1.25.

• Table 42, "EIM Bus Timing Parameters," on page 55: Changed footnotes regarding the system clocks

used with EIM: from axi_clk to ACLK_EXSC or ACLK_EIM_SLOW_CLK_ROOT.

• Table 49, “DDR3/DDR3L Write Cycle,” on page 77: Changed DDR17 minimum value from 420 ps to

125 ps and DDR18 from 345 ps to 150 ps.

• Table 49, “DDR3/DDR3L Write Cycle,” on page 77: Added footnote 4.

• Table 69, "LVDS Display Bridge (LDB) Electrical Specification," on page 105: Corrected Units for Output

Voltage High and Output Voltage Low from mV to V.

• Table 71, "Electrical and Timing Information," on page 108: Moved rows tSETUP[RX] and tHOLD[RX]

to be directly under HS Line Receiver AC Specifications heading row.

• Table 96, "21 x 21 mm Supplies Contact Assignments," on page 140: Removed A1 pin.

• Table 97, "21 x 21 mm Functional Contact Assignments," on page 142: Moved rows DRAM_4,

DRAM_5, and DRAM_6 out of the i.MX 6DualLite section (shaded gray) to the i.MX 6Solo section above

DRAM_7 and (unshaded).

• Table 99, "21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6Solo," on page 156: Removed “NC” from A1 pin

location.

• Table 100, "21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6DualLite," on page 159: Removed “NC” from A1

pin location.

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Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories (continued)

Rev.

Number

Date

Substantive Changes

Rev. 3 02/2014 • Updates throughout for Silicon revision C, including:

- Figure 1 Part number nomenclature diagram

- Table 1 Example Orderable Part Numbers

• Feature descriptions updated for:

- Camera sensors: updated from one to two ports at up to 240 MHz peak.

- Miscellaneous IPs and interfaces; SSI and ESAI.

• Table 2, Modules List, uSDHC 1–4 description change: including SDXC cards up to 2 TB.

• Table 2, Modules List, UART 1–5 description change: programmable baud rate up to 5 MHz.

• Table 3, Special Signal Considerations: XTALOSC_RTC_XTALI/RTC_XTALO: ending paragraph

removed. Was: “In case when high accuracy real time clock are not required system may use internal

low frequency ring oscillator. It is recommended to connect XTALOSC_RTC_XTALI to GND and keep

RTC_XTALO floating.”

• Table 8, Operating Ranges for Run mode LDO bypassed: Added footnote regarding alternate maximum

voltage on VDD_SOC_IN … this maximum can be 1.3V.

• Table 8, Operating Ranges Standby/DSM mode: Added footnote regarding alternate maximum voltage

on VDD_SOC_IN … this maximum can be 1.3V.

• Table 8, Operating Ranges GPIO supply voltages: Corrected supply name to NVCC_NANDF

• Table 8, Operating ranges: updated table footnotes for clarity.

• Removed table “On-Chip LDOs and their On-Chip Loads.”

• Section 4.1.4, External Clock Sources; added Note, “The internal RTC oscillator does not...”.

• Section 4.1.5, Maximum Supply Currents: Reworded second paragraph about the power management

IC to explain that a robust thermal design is required for the increased system power dissipation.

• Table 10, Maximum Supply Currents: NVCC_RGMII Condition value corrected to N=6.

• Table 10, Maximum Supply Currents: Corrected supply name NVCC_NANDF.

• Table 10, Maximum Supply currents: Added row NVCC_LVDS2P5

• Section 4.2.1, Power-Up Sequence: Clarified wording of third bulleted item regarding POR control.

• Section 4.2.1, Power-Up Sequence: Removed Note.

• Section 4.2.1, Power-Up Sequence: Corrected bullet regarding VDD_ARM_CAP / VDD_SOC_CAP

difference from 50 mV to 100 mV.

• Section 4.5.2, OSC32K, second paragraph reworded to describe OSC32K automatic switching.

• Section 4.5.2, OSC32K, added Note following second paragraph to caution use of internal oscillator.

• Table 23, XTALI and RTC_XTALI DC parameters; changed RTC_XTALI Vih minimum value to 0.8.

• Table 23, XTALI and RTC_XTALI DC parameters; changed RTC_XTALI Vih maximum value to 1.1.

• Table 39, Reset Timing Parameters; removed rise/fall time requirement

• Section 4.9.3, External Interface Module; enhanced wording to first paragraph to describe operating

frequency for data transfers, and to explain register settings are valid for entire range of frequencies.

Rev. 3

continued

2/2014 • Table 42, EIM Bus Timing Parameters; reworded footnotes for clarity.

• Table 42, EIM Asynchronous Timing Parameters; removed comment from the Max heading cell.

• Figure 60, Gated Clock Mode Timing Diagram: Corrected HSYNC trace behavior

• Table 66, Video Signal Cross-Reference: Corrected naming of HSYNC and VSYNC

• Section 4.11.22, USB PHY Parameters: Updated Battery Charging Specification bullet

• Table 95, BGA Package Details: Corrected to read “21 x 21, 0.8 mm”.

• Table 96, Supplies Contact Assignments: Corrected supply name NVCC_NANDF

• Table 96, Supplies Contact Assignments: Updated NC rows to show i.MX 6DualLite vs. i.MX 6Solo

• Table 97, Functional Contact Assignments: ALT5 Default function signal names corrected

• Table 97, Functional Contact Assignments: PMIC_ON_REQ Out of Reset value corrected to “Open

Drain with PU (100K) enabled”

• Table 97, Functional Contact Assignments: TEST_MODE row included

• Table 97, Functional Contact Assignments: VDD_ARM_IN and ZQPAD row removed

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Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories (continued)

Rev.

Number

Date

Substantive Changes

Rev. 2.2 8/2013 • 21x21 functional contact table: changed from NAND to NANDF

• System Timing Parameters Table 39, Reset timing parameter, CC1 description, change from:

“Duration of SRC_POR_B to be qualified as valid (<= 5 ns)” to:

“Duration of SRC_POR_B to be qualified as valid”

and added a footnote to the parameter with the following text:

“SRC_POR_B rise and fall times must be 5 ns or less.”

Rev. 2.1 5/2013 Substantive changes throughout this document are as follows:

• Incorporated standardized signal names. This change is extensive throughout.

• Added reference to EB792, i.MX Signal Name Mapping.

• Figures updated to align to standardized signal names.

• Updated references to eMMC standard to include 4.41.

• Added MediaLB (MLB) feature and DTCP module to the commercial temperature grade version.

• Figure 1 Part Number Nomenclature: Updates to Part differentiator section to align with Table 1.

• Table 1 “Orderable Part Numbers,” added Arm core information to the Options column:

2x “Arm Cortex-A9” 64-bit to 6DualLite

1x “Arm Cortex -A9” 32-bit to 6Solo

• Table 2 Changed reference to Global Power Controller to read General Power Controller.

• Table 8 “Operating Ranges,” added reference for information on product lifetime: i.MX 6Dual/6Quad

Product Usage Lifetime Estimates Application Note, AN4725.

• Table 10 “Maximum Supply Currents,” updated footnote 2.

• Table 11 Stop Mode Current and Power Consumption: Added SNVS Only mode.

• Table 60 RGMII parameter TskewT minimum and maximum values corrected.

• Table 60 RGMII parameter TskewR units corrected.

• Table 97 Clarification of ENET_REF_CLK naming.

• Added Table 98, "Signals with Differing Before Reset and After Reset States," on page 153.

• Removed section, EIM Signal Cross Reference. Signal names are now aligned with reference manual.

• Removed table from Section 3.2, “Recommended Connections for Unused Analog Interfaces and

referenced the Hardware Development Guide.

• Section 1.2, “Features added bulleted item regarding the SOC-level memory system.

• Section 1.2, “Features Camera sensors: Changed Camera port to be up to 180 MHz peak.

• Added Section 1.3, “Updated Signal Naming Convention

• Section 4.2.1, “Power-Up Sequence” updated wording.

• Section 4.3.2, “Regulators for Analog Modules” section updates.

• Added Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters.”

• Section 4.10, “General-Purpose Media Interface (GPMI) Timing” figures replaced, tables revised.

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

168

NXP Semiconductors

Information in this document is provided solely to enable system and software implementers to

use NXP products. There are no express or implied copyright licenses granted hereunder to

design or fabricate any integrated circuits based on the information in this document. NXP

reserves the right to make changes without further notice to any products herein.

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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for

any particular purpose, nor does NXP assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data

sheets and/or specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be validated for each

customer application by customer’s technical experts. NXP does not convey any license under

its patent rights nor the rights of others. NXP sells products pursuant to standard terms and

conditions of sale, which can be found at the following address:

nxp.com/SalesTermsandConditions.

While NXP has implemented advanced security features, all products may be subject to

unidentified vulnerabilities. Customers are responsible for the design and operation of their

applications and products to reduce the effect of these vulnerabilities on customer’s applications

and products, and NXP accepts no liability for any vulnerability that is discovered. Customers

should implement appropriate design and operating safeguards to minimize the risks associated

with their applications and products.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,

EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE

CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,

MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,

TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C?5, CodeTEST, CodeWarrior,

ColdFire, ColdFire+, C?Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,

mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play,

SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit,

BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower,

TurboLink, and UMEMS are trademarks of NXP B.V. All other product or service names are the

property of their respective owners. Arm, AMBA, Artisan, Cortex, Jazelle, Keil, SecurCore,

Thumb, TrustZone, and µVision are registered trademarks of Arm Limited (or its subsidiaries) in

the EU and/or elsewhere. Arm7, Arm9, Arm11, big.LITTLE, CoreLink, CoreSight, DesignStart,

Mali, Mbed, NEON, POP, Sensinode, Socrates, ULINK and Versatile are trademarks of Arm

registered trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word

marks and the Power and Power.org logos and related marks are trademarks and service marks

licensed by Power.org.

Document Number: IMX6SDLCEC

Rev. 9

11/2018


型号：	MCIMX6S1AVM10AB
厂家：	NXP
描述：	i.MX 6Solo/6DualLite Applications Processors for Consumer Products
文件：	总169页 (文件大小：3175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCIMX6S1AVM10AB [NXP]

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