MCM6949YJ8R [NXP]
IC,SRAM,1MX4,BICMOS-TTL,SOJ,32PIN,PLASTIC;
| 型号： | MCM6949YJ8R |
| 厂家： | 
NXP |
| 描述： | IC,SRAM,1MX4,BICMOS-TTL,SOJ,32PIN,PLASTIC 输入元件 信息通信管理 静态存储器 光电二极管 输出元件 内存集成电路 |
| 文件： | 总8页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6949/D
MCM6949
1M x 4 Bit Static Random
Access Memory
The MCM6949 is a 4,194,304–bit static random access memory organized as
1,048,576 words of 4 bits. Static design eliminates the need for external clocks
or timing strobes.
YJ PACKAGE
400 MIL SOJ
CASE 857A–02
The MCM6949 is equipped with chip enable (E) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.
TheMCM6949isavailableina400mil, 32–leadsurface–mountSOJpackage.
PIN NAMES
•
•
•
•
•
•
Single 3.3 V – 5%, + 10% Power Supply
Fast Access Time: 8/10/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
A0 – A19 . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . . . . . No Connection
Power Operation: 195/165/160/155 mA Maximum, Active AC
V
DD
V
SS
. . . . . . . . . . . . . . + 3.3 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 9
5/20/99
Motorola, Inc. 1999
For More Information On This Product,
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Freescale Semiconductor, Inc.
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
A
ROW
MEMORY MATRIX
DECODER
COLUMN I/O
DQ
DQ
E
INPUT
DATA
CONTROL
COLUMN DECODER
A
A
A
A
A
A
A
A
A
A
DQ
DQ
W
G
PIN ASSIGNMENT
A
A
A
A
A
1
2
3
4
5
32
31
30
29
28
A
A
A
A
A
E
6
7
8
9
27
26
25
24
G
DQ
DQ
V
V
DD
SS
DD
V
V
SS
DQ
W
10
11
12
13
14
15
16
23
22
21
20
19
18
17
DQ
A
A
A
A
A
A
A
A
A
A
NC
MCM6949
2
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TRUTH TABLE (X = Don’t Care)
E
H
L
G
X
H
L
W
X
H
H
L
Mode
Not Selected
Output Disabled
Read
I/O Pin
High–Z
High–Z
Cycle
—
Current
, I
I
SB1 SB2
—
I
I
I
DDA
DDA
DDA
L
D
Read
Write
out
L
X
Write
High–Z
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
Rating
Symbol
Value
– 0.5 to + 5.0
– 0.5 to V + 0.5
Unit
Power Supply Voltage Relative to V
V
DD
V
V
SS
Voltage Relative to V
for Any Pin
V , V
in out
SS
DD
Except V
DD
Output Current (per I/O)
I
mA
± 20
1.0
out
Power Dissipation
P
D
W
°C
°C
°C
Temperature Under Bias
Operating Temperature
T
bias
– 10 to + 85
0 to + 70
T
A
Storage Temperature — Plastic
T
stg
– 55 to + 150
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.V – 5%, + 10%, T = 0 to + 70°C, Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
3.135
2.2
Typ
3.3
—
Max
Unit
V
Supply Voltage (Operating Voltage Range)
Input High Voltage
V
DD
3.63
V
IH
V
+ 0.3
V
DD
Input Low Voltage
V
IL
—
0.8
V
– 0.5*
* V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).
IL IL
DC CHARACTERISTICS
Parameter
Symbol
Min
—
Max
± 1.0
± 1.0
0.4
Unit
µA
µA
V
Input Leakage Current (All Inputs, V = 0 to V
)
I
lkg(I)
in
DD
Output Leakage Current (E = V , V
= 0 to V
)
I
lkg(O)
—
IH out
DD
Output Low Voltage (I
= + 8.0 mA)
V
OL
—
OL
Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
—
V
OH
POWER SUPPLY CURRENTS
Parameter
Symbol
0 to + 70°C
Unit
AC Active Supply Current
MCM6949–8: t
= 8 ns
I
195
165
160
155
mA
AVAV
DD
(I
out
= 0 mA, V
= Max)
MCM6949–10: t
MCM6949–12: t
MCM6949–15: t
= 10 ns
= 12 ns
= 15 ns
DD
AVAV
AVAV
AVAV
AC Standby Current (V
DD
= Max, E = V
,
MCM6949–8: t
AVAV
= 8 ns
I
55
50
50
45
mA
mA
IH
No Other Restrictions on Other Inputs)
SB1
MCM6949–10: t
MCM6949–12: t
MCM6949–15: t
= 10 ns
= 12 ns
= 15 ns
AVAV
AVAV
AVAV
CMOS Standby Current (E ≥ V
– 0.2 V, V ≤ V
in
+ 0.2 V or ≥ V – 0.2 V)
DD
I
20
DD
SS
SB2
(V
DD
= Max, f = 0 MHz)
MCM6949
3
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CAPACITANCE (f = 1.0 MHz, dV = 3.3 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
All Inputs Except Clocks and DQs
E, G, W
C
4
5
6
8
pF
in
C
ck
Input/Output Capacitance
DQ
C
5
8
pF
I/O
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V – 5%, + 10%, T = 0 to + 70°C, Unless Otherwise Noted)
DD
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1 and 2)
MCM6949–8 MCM6949–10 MCM6949–12 MCM6949–15
Parameter
Read Cycle Time
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
8
Max
—
8
Min
10
—
—
—
2
Max
—
10
10
5
Mn
12
—
—
—
2
Max
—
12
12
6
Min
15
—
—
—
2
Max
—
15
15
7
t
3
AVAV
Address Access Time
t
—
—
—
2
AVQV
Enable Access Time
t
8
4
ELQV
GLQV
AXQX
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Output Enable High to Output High–Z
t
t
4
—
—
—
4
—
—
—
5
—
—
—
6
—
—
—
7
t
3
3
3
3
5, 6, 7
5, 6, 7
5, 6, 7
5, 6, 7
ELQX
LQX
EHQZ
GHQZ
t
t
0
0
0
0
0
0
0
0
t
0
4
0
5
0
6
0
7
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, t
to device.
max
t
min, and t
max
t min, both for a given device and from device
GLQX
EHQZ
ELQX
GHQZ
6. Transition is measured ± 200 mV from steady–state voltage.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E ≤ V , G ≤ V ).
IL IL
TIMING LIMITS
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a mini-
mum since the system must supply at least that much
time. On the other hand, responses from the memory
are specified from the device point of view. Thus, the
access time is shown as a maximum since the device
never provides data later than that time.
R
= 50 Ω
L
OUTPUT
Z
= 50 Ω
0
V
= 1.5 V
L
Figure 1. AC Test Load
MCM6949
4
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READ CYCLE 1 (See Note 8)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Note 4)
t
AVAV
A (ADDRESS)
t
ELQV
E (CHIP ENABLE)
t
t
EHQZ
t
t
ELQX
G (OUTPUT ENABLE)
Q (DATA OUT)
t
GLQV
GHQZ
t
GLQX
HIGH–Z
DATA VALID
AVQV
I
DD
SUPPLY CURRENT
I
SB
MCM6949
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WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
MCM6949–8 MCM6949–10 MCM6949–12 MCM6949–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
8
Max
—
Min
10
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
4
AVAV
Address Setup Time
t
0
—
—
—
—
ns
AVWL
Address Valid to End of Write
Address Valid to End of Write (G High)
Write Pulse Width
t
8
—
9
—
10
9
—
12
10
12
—
ns
AVWH
AVWH
t
7
—
8
—
—
—
ns
t
t
8
—
9
—
10
—
—
ns
WLWH
t
WLEH
Write Pulse Width (G High)
7
—
8
—
9
—
10
—
ns
WLWH
t
WLEH
DVWH
WHDX
Data Valid to End of Write
Data Hold Time
t
t
5
0
0
3
0
—
—
4
5
0
0
3
0
—
—
5
6
0
0
3
0
—
—
6
7
0
0
3
0
—
—
7
ns
ns
ns
ns
ns
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
NOTES:
t
5, 6, 7
5, 6, 7
WLQZ
t
—
—
—
—
—
—
—
—
WHQX
t
WHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the lasvalid address to the first transitioning address.
5. Transition is measured ± 200 mV from steady–state voltage.
6. This parameter is sampled and not 100% tested.
7. At any given voltage and temperaturt
max < t
min, both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLWH
t
WLEH
W (WRITE ENABLE)
D (DATA IN)
t
t
t
WHDX
AVWL
DVWH
DATA VALID
t
t
WLQZ
WHQX
HIGH–Z
HIGH–Z
Q (DATA OUT)
MCM6949
6
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WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
MCM6949–8 MCM6949–10 MCM6949–12 MCM6949–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
8
Max
—
Min
10
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
4
AVAV
Address Setup Time
t
0
—
—
—
—
ns
AVEL
Address Valid to End of Write
Address Valid to End of Write (G High)
Enable Pulse Width
t
t
8
—
9
—
10
9
—
12
10
12
—
ns
AVEH
7
—
8
—
—
—
ns
AVEH
t
t
8
—
9
—
10
—
—
ns
5, 6
5, 6
ELEH,
ELWH
Enable Pulse Width (G High)
t
t
7
—
8
—
9
—
10
—
ns
ELEH,
ELWH
Data Valid to End of Write
Data Hold Time
t
t
5
0
0
—
—
—
5
0
0
—
—
—
6
0
0
—
—
—
7
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
Write Recovery Time
NOTES:
t
EHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
6. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
t
AVAV
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
t
AVEH
t
ELEH
t
t
t
EHAX
AVEL
ELWH
t
DVEH
DATA VALID
D (DATA IN)
t
EHDX
HIGH–Z
Q (DATA OUT)
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6949 XX XX XX
Motorola Memory Prefix
Shipping Method (R = Tape and Reel, Blank = Rails)
Part Number
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns,
15 = 15 ns)
Package (YJ = 400 mil SOJ)
Full Part Numbers — MCM6949YJ8
MCM6949YJ8R
MCM6949YJ10
MCM6949YJ10R
MCM6949YJ12
MCM6949YJ12R
MCM6949YJ15
MCM6949YJ15R
MCM6949
7
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PACKAGE DIMENSIONS
YJ PACKAGE
400 MIL SOJ
CASE 857A–02
F 32 PL
NOTES:
32
1
17
16
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
S
S
0.17 (0.007)
T
B
A
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE –T–.
4. DIMENSION A AND D DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
N
D 32 PL
5. DIMENSION A AND B INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT THE PARTING LINE.
S
S
S
NOTE 3
0.17 (0.007)
T
B
A
DETAIL Z
INCHES
MILLIMETERS
DIM
B
C
D
E
MIN
MAX
0.830
0.405
0.148
0.020
0.098
0.032
MIN
20.83
10.03
3.26
0.41
2.24
0.67
1.27 BSC
0.89
0.64 BSC
MAX
21.08
10.29
3.75
0.50
2.48
0.820
0.395
0.128
0.016
0.088
0.026
0.050 BSC
0.035
0.025 BSC
0.030
0.435
0.365
0.030
P
–A–
S
S
S
0.17 (0.007)
T
A
B
L
–B–
G
F
0.81
G
K
L
N
P
0.045
1.14
C
E
0.045
0.445
0.375
0.040
0.76
11.05
9.27
1.14
11.30
9.52
0.10 (0.040)
K
–T–
R
S
SEATING PLANE
R
DETAIL Z
S
RADIUS
0.77
1.01
S
S
S
0.25 (0.010)
T
A
B
NOTE 3
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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