MCM69L736CZP7.5 [NXP]
128KX36 LATE-WRITE SRAM, 7.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119;型号: | MCM69L736CZP7.5 |
厂家: | NXP |
描述: | 128KX36 LATE-WRITE SRAM, 7.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 信息通信管理 静态存储器 内存集成电路 |
文件: | 总20页 (文件大小:1590K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69L736C/D
MCM69L736C
MCM69L818C
4M Late Write HSTL
The MCM69L736C/818C is a 4M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69L818C
(organized as 256K words by 18 bits) and the MCM69L736C (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control
signals. Read data is available at the falling edge of CK.
ZP PACKAGE
PBGA
CASE 999–02
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V
)
ref
and output voltage (V
) gives the system designer greater flexibility in
DDQ
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or
the entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
•
•
•
•
•
•
•
•
•
•
•
Byte Write Control
Single 3.3 V +10%, –5% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Latch Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69L736C/818C–5.5 = 5..5 ns
MCM69L736C/818C–6.5 = 6.5 ns
MCM69L736C/818C–7.5 = 7.5 ns
MCM69L736C/818C–8.5 = 8.5 ns
•
•
Sleep Mode Operation (ZZ Pin)
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
REV 1
8/10/99
Motorola, Inc. 1999
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
FUNCTIONAL BLOCK DIAGRAM
DATA IN
REGISTER
ADDRESS
REGISTERS
MEMORY
ARRAY
SA
DQ
DATA OUT
LATCH
SW
SW
REGISTERS
CONTROL
LOGIC
SBx
CK
G
SS
SS
REGISTERS
PIN ASSIGNMENTS
TOP VIEW
MCM69L736C
MCM69L818C
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
A
B
C
D
E
V
SA
NC
SA
SA
SA
NC
NC
SA
SA
SA
SA
NC
SA
V
V
SA
NC
SA
SA
SA
SA
NC
NC
SA
SA
SA
SA
NC
V
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
SA
V
NC
NC
V
SA
NC
NC
DD
DD
DQc
DQc
DQc
DQc
DQc
V
ZQ
V
DQb DQb
DQb DQb
DQb
NC
NC
DQb
NC
V
ZQ
SS
G
V
DQa
NC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
SS
G
V
V
V
V
V
V
V
V
DQa
F
F
V
DQb
V
V
DQa
NC
V
DDQ
DDQ
DDQ
DDQ
G
G
DQc
DQc SBc
DQc
NC
NC
SBb
DQb DQb
DQb DQb
NC
DQb SBb
NC
NC
DQa
H
H
DQc
V
V
DQb
NC
V
DQa
NC
SS
SS
SS
J
K
L
J
K
L
V
V
V
V
V
V
V
DDQ
DD
DQd
DQd SBd
ref
DD
ref
DD DDQ
V
V
V
V
V
V V
DD DDQ
DDQ
DD
ref
SS
SS
SS
SS
SS
DD
ref
DQd
V
CK
V
DQa DQa
DQa DQa
NC
DQb
V
V
V
V
V
CK
CK
SW
SA
SA
V
NC
DQa
NC
SS
SS
SS
DQb
NC
DQb
NC
SBa
DQa
NC
DQd
CK
SW
SA
SA
SBa
M
N
P
M
N
P
V
DQd
DQd
DQd
V
V
V
V
V
V
DQa
V
V
V
V
V
V
DDQ
SS
SS
SS
SS
SS
SS
DDQ
DDQ
SS
SS
SS
DDQ
DQd
DQa DQa
DQa DQa
DQb
DQa
NC
NC
DQd
NC
NC
NC
DQb
DQa
NC
ZZ
R
T
R
T
NC
NC
SA
NC
V
V
V
SA
NC
NC
NC
ZZ
SA
SA
V
V
V
SA
SA
NC
DD
DD
SS
DD
DD
NC
TCK
SS
SA
TDO
SA
SA
SA
SA
U
U
V
TMS
TDI
TCK
TDO
V
V
TMS
TDI
V
DDQ
DDQ
DDQ
DDQ
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
2
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
MCM69L736C PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
CK
Type
Input
Input
I/O
Description
4K
4L
Address, data in, and control input register clock. Active high.
Address, data in, and control input register clock. Active low.
Synchronous Data I/O.
CK
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx
4F
G
Input
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C,
4N, 4P, 2R, 6R, 3T, 4T, 5T
SA
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 5G, 3G, 3L
(a), (b), (c), (d)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
TDI
TDO
TMS
ZQ
Input
Input
Test Clock (JTAG).
Test Data In (JTAG).
3U
5U
Output Test Data Out (JTAG).
2U
Input
Input
Input
Test Mode Select (JTAG).
4D
Programmable Output Impedance: Programming pin.
Enables sleep mode, active high.
7T
4C, 2J, 4J, 6J, 4R, 3R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3J, 5J
ZZ
V
DD
Supply Core Power Supply.
V
DDQ
Supply Output Power Supply: Provides operating power for output buffers.
Supply Input Reference: Provides reference voltage for input buffers.
Supply Ground.
V
ref
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K,
3M, 5M, 3N, 5N, 3P, 5P, 5R
V
SS
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4G, 4H,
1R, 7R, 1T, 2T, 6T, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
3
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
MCM69L818C PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
CK
Type
Input
Input
I/O
Description
4K
4L
Address, data in, and control input register clock. Active high.
Address, data in, and control input register clock. Active low.
Synchronous Data I/O.
CK
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
4F
G
Input
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C,
4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
SA
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 3G
(a), (b)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
TDI
TDO
TMS
ZQ
Input
Input
Test Clock (JTAG).
Test Data In (JTAG).
3U
5U
Output Test Data Out (JTAG).
2U
Input
Input
Input
Test Mode Select (JTAG).
4D
Programmable Output Impedance: Programming pin.
Enables sleep mode, active high.
7T
4C, 2J, 4J, 6J, 4R, 3R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3J, 5J
ZZ
V
DD
Supply Core Power Supply.
V
DDQ
Supply Output Power Supply: Provides operating power for output buffers.
Supply Input Reference: Provides reference voltage for input buffers.
Supply Ground.
V
ref
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R
V
SS
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 2D, 7D,
1E, 6E, 2F, 1G, 4G, 6G, 2H, 4H, 7H, 1K,
6K, 2L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 7R,
1T, 4T, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
4
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V , See Note)
SS
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
Rating
Core Supply Voltage
Symbol
Value
Unit
V
V
DD
–0.5 to 4.6
Output Supply Voltage
Voltage On Any Pin
V
– 0.5 to V
+ 0.5
V
DDQ
DD
V
in
– 0.5 to V
+ 0.5
V
DD
Input Current (per I/O)
Output Current (per I/O)
Operating Temperature
Temperature Under Bias
Storage Temperature
I
±50
mA
mA
°C
°C
°C
in
I
±70
out
T
0 to 70
A
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
T
–10 to 85
bias
T
stg
–55 to 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
53
38
22
14
5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1, 2
Junction to Ambient (Still Air)
R
θJA
R
θJA
R
θJA
R
θJB
R
θJC
Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)
Junction to Board (Bottom)
Junction to Case (Top)
Single–Layer Board
Four–Layer Board
1, 2
3
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K, CLK
L – H
L – H
L – H
L – H
L – H
L – H
L – H
L – H
X
ZZ
L
SS
L
SW
H
L
SBa
X
SBb
X
SBc
X
SBd
X
DQ (n)
DQ (n+1)
Mode
D
0 – 35
X
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
out
L
L
L
H
H
H
High–Z
D
0 – 8
In
L
L
L
H
L
H
H
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
D
9 – 17
In
L
L
L
H
H
L
H
D
18 – 26
27 – 35
0 – 35
In
In
L
L
L
H
H
H
L
D
L
L
L
L
L
L
L
D
In
L
L
L
H
H
H
H
High–Z
X
L
H
X
X
X
X
X
X
X
H
X
X
X
X
High–Z
Sleep Mode
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
5
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Max
Max
–6.5
Max
–7.5
Max
–8.5
–5.5
Parameter
Symbol
Min
3.135
1.4
Max
3.6
2.0
—
Unit
V
Notes
Core Power Supply Voltage
V
DD
—
—
—
—
—
—
—
Output Driver Supply Voltage
V
—
V
DDQ
DD1
Active Power Supply Current (Device Selected,
All Outputs Open, Freq = Max, V = Max,
= Max). Includes Supply Currents
I
—
795
775
750
750
mA
5
6
DD
V
DDQ
for V
.
DD
Quiescent Active Power Supply Current
(Device Selected, All Outputs Open, Freq = 0,
I
—
540
540
540
540
—
mA
DD2
V
= Max, V
= Max). Includes Supply
DD
Currents for V
DDQ
.
DD
Active Standby Power Supply Current
(Device Deselected, Freq = Max, V
I
I
—
—
400
390
400
390
400
390
400
390
—
—
mA
mA
7
SB1
= Max,
DD
V
= Max)
DDQ
CMOS Standby Supply Current (Device
Deselected, Freq = 0, V = Max,
6, 7
SB2
DD
= Max, All Inputs Static at
V
DDQ
CMOS Levels)
Sleep Mode Current (ZZ = V , Freq = Max,
IH
I
—
100
—
100
—
100
—
100
—
—
mA
V
6
8
ZZ
V
= Max, V
= Max)
DD
DDQ
Input Reference DC Voltage
V
(dc)
0.6
1.1
ref
NOTES:
1. All data sheet parameters specified to full range of V
bumps.
unless otherwise noted. All voltages are referenced to voltage applied to V
SS
DD
2. Supply voltage applied to V
3. Supply voltage applied to V
connections.
DD
connections.
DDQ
4. All power supply currents measured with outputs open or deselected.
5. All inputs are zero.
6. CMOS levels for I/Os are V ≤ V
+ 0.2 V or ≥ V
– 0.2 V. CMOS levels for other inputs are V ≤ V
+ 0.2 V or ≥ V – 0.2 V.
DD
IC SS
DDQ
in SS
7. Device deselected as defined by the Clock Truth Table.
8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of V is supported, the peak–to–peak ac compo-
ref
nent superimposed on V may not exceed 5% of the dc component of V
ref
.
ref
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
+ 0.1
Max
+ 0.3
DD
Unit
V
Notes
DC Input Logic High
DC Input Logic Low
V
(dc)
(dc)
V
ref
V
IH
V
–0.5
—
V
ref
– 0.1
V
IL
Input Leakage Current
Clock Input Signal Voltage
I
±5
µA
V
1
lkg(1)
V
in
–0.3
0.1
V
V
+ 0.3
+ 0.6
DD
Clock Input Differential Voltage (See Figure 3)
Clock Input Common Mode Voltage Range (See Figure 3)
NOTES:
V
DIF
V
CM
(dc)
(dc)
V
2
3
DD
0.6
1.1
V
1. 0 V ≤ V ≤ V
for all pins.
in DD
2. Minimum instantaneous differential input voltage required for differential input clock operation.
3. Maximum rejectable common mode input voltage variation.
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
6
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
DC OUTPUT BUFFER CHARACTERISTICS — PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(V
DD
= 3.3 V, V
= 1.5 V, T = 70°C, See Notes 1 and 2)
DDQ
A
Parameter
Symbol
Min
/2) /
Max
/2) /
Unit
Notes
Output Logic Low
Output Logic High
I
(V
DDQ
(V
DDQ
A
3
OL
[(RQ/5) + 30%]
[(RQ/5) – 15%]
I
(V /2) /
DDQ
[(RQ/5) + 30%]
(V /2) /
[(RQ/5) – 15%]
A
4
OH
DDQ
Light Load Output Logic Low
Light Load Output Logic High
NOTES:
V
1
V
0.2
V
V
5
6
OL
SS
V
OH
1
V
– 0.2
V
DDQ
DDQ
1. The impedance controlled mode is expected to be used in point–to–point applications, driving high–impedance inputs.
2. The ZQ pin is connected through RQ to V for the controlled impedance mode.
SS
3. V
4. V
5. I
OL
6. | I
= V
/2.
OL
OH
DDQ
= V
/2.
DDQ
≤ 100 µA.
| ≤ 100 µA.
OH
DC OUTPUT BUFFER CHARACTERISTICS — MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(0°C ≤ T ≤ 70°C, ZQ = V , See Notes 1 and 2)
A
DD
Parameter
Symbol
Min
Max
Unit
V
Notes
Output Logic Low
Output Logic High
V 2
OL
V
SS
0.4
3
4
5
6
V
OH
2
V
V
– 0.4
V
DDQ
V
DDQ
Light Load Output Logic Low
Light Load Output Logic High
NOTES:
V 3
OL
V
SS
0.2
V
V
OH
3
– 0.2
V
DDQ
V
DDQ
1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC
Standard JESD8–6 Class I.
2. The ZQ pin is connected to V
to enable the minimum impedance mode.
DD
3. I
4. I
5. I
6.
≥ – 8 mA .
≥ 8 mA.
≥ 100 µA.
OL
OH
OL
I
≥ 100 µA.
OH
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0°C ≤ T ≤ 70°C, Periodically Sampled Rather Than 100% Tested)
A
Characteristic
Symbol
Typ
4
Max
Unit
pF
Input Capacitance
C
5
7
7
in
Input/Output Capacitance
CK, CK Capacitance
C
C
7
pF
I/O
4
pF
CK
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
7
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 to 1.25 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 0.75 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 V
ZQ for 50 Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ω
R
Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
θJA
READ/WRITE CYCLE TIMING
69L736C–5.5
69L818C–5.5
69L736C–6.5
69L818C–6.5
69L736C–7.5
69L818C–7.5
69L736C–8.5
69L818C–8.5
Parameter
Cycle Time
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
5.5
2.2
2.2
—
Max
—
Min
6
Max
—
Min
7
Max
—
—
—
7.5
3
Min
8
Max
—
t
KHKH
Clock High Pulse Width
Clock Low Pulse Width
t
—
2.4
2.4
—
—
0.7
1
—
2.8
2.8
—
—
0.7
1
3.2
3.2
—
—
0.7
1
—
KHKL
KLKH
KHQV
t
—
—
—
Clock High to Output Valid
Clock Low to Output Valid
Clock Low to Output Hold
Clock Low to Output Low–Z
Clock High to Output High–Z
t
5.5
2.5
—
6.5
2.5
—
8.5
3.5
—
t
—
KLQV
KLQX
t
0.7
0.7
0.7
0.5
—
—
3
1
t
—
—
—
1, 2
1, 2
KLQX1
t
2.5
—
1
2.5
—
1
1
3.5
—
KHQZ
GLQX
Output Enable Low to Output
Low–Z
t
0.5
0.5
—
0.5
Output Enable Low to Output
Valid
t
—
2.3
—
2.5
—
3
—
3.5
ns
GLQV
Output Enable to Output Hold
t
0.5
—
—
0.5
—
—
0.5
—
—
3
0.5
—
—
ns
ns
GHQX
Output Enable High to Output
High–Z
t
2.3
2.5
2.3
1, 2
GHQZ
ZZ High to Sleep Mode
ZZ Low to Recovery
t
—
200
0.5
50
—
—
—
200
0.5
50
—
—
—
200
0.5
50
—
—
—
200
0.5
50
—
—
ns
ns
ns
ZZE
t
ZZR
Setup Times:
Hold Times:
NOTES:
Address
t
AVKH
t
DVKH
SVKH
Data In
Chip Select
Write Enable
t
t
WVKH
Address
Data In
t
t
1
—
1
—
1
—
1
—
ns
KHAX
KHDX
t
KHSX
Chip Select
Write Enable
t
KHWX
1. This parameter is sampled and not 100% tested.
2. Measured at ± 200 mV from steady state.
TIMING LIMITS
The table of timing values shows either a mini-
mum or a maximum limit for each parameter. Input
requirementsare specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
0.75 V
V
/2
DDQ
V
ref
50
Ω
DEVICE
UNDER
TEST
50
Ω
250
Ω
ZQ
Figure 1. AC Test Load
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
AC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Notes
AC Input Logic High (See Figure 4)
AC Input Logic Low (See Figures 2 and 4)
Input Reference Peak–to–Peak AC Voltage
Clock Input Differential Voltage
NOTES:
V
(ac)
(ac)
(ac)
(ac)
V
ref
+ 200 mV
—
1
2
3
4
IH
V
—
—
V
– 200 mV
IL
ref
V
ref
5% V (dc)
ref
V
dif
400 mV
V
DDQ
+ 600 mV
1. Inputs may overshoot to V
DD
– 1 V for 30% t
and V
+ 1.5 V peak overshoot.
KHKH
– 1 V for 30% t
DD
and V – 1.5 V peak undershoot.
SS
2. Inputs may undershoot to V
SS
KHKH
3. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of V is supported, the peak–to–peak ac compo-
ref
nent superimposed on V may not exceed 5% of the dc component of V
.
ref ref
4. Minimum instantaneous differential input voltage required for differential input clock operation.
V
OH
V
SS
50%
100%
20% t
KHKH
Figure 2. Undershoot Voltage
V
DDQ
V
TR
CROSSING POINT
V
DIF
V
*
V
CM
CP
V
SS
* V , the Common Mode Input Voltage, equalsV
CM
– [(V
TR
– V )/2].
CP
TR
Figure 3. Differential Inputs/Common Mode Input Voltage
V (ac)
IH
V
ref
V (ac)
IL
Figure 4. AC Input Conditions
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
REGISTER LATCH READ–WRITE–READ CYCLES
t
t
KHKH
KHKL
CK
SA
t
t
AVKH
KLKH
t
KHAX
A1
A0
A2
A3
A4
t
SVKH
t
KHSX
SS
t
WVKH
t
KHWX
SW
SBx
G
t
KLQX
Q1
t
t
KHQV
KHQZ
t
t
DVKH
t
t
KLQV
t
KHQZ
KLQX1
Q4
t
KHDX
KLQX1
DQ
Q0
READ
D2
WRITE
Q3
READ
READ
READ
DESELECT (HIGH–Z)
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
10
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
REGISTER LATCH READ–WRITE–READ CYCLES
(G Controlled)
CK
SA
A0
A1
A2
A3
A4
SS
SW
SBx
G
t
GLQV
t
t
GHQX
GLQX
t
GHQZ
DQ
Q0
READ
Q1
READ
D2
WRITE
Q3
READ DESELECT (HIGH–Z)
Q4
READ
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
11
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MCM69L736C•MCM69L818C
12
MOTOROLA FAST SRAM
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
occur, but the outputs will be deselected as in a normal write
cycle.
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
LATE WRITE
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
falling edge of the current cycle, the output latch becomes
transparent and data is available. The output data is latched
on the rising edge of the next clock. The output data is avail-
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to ensure coherent
operation. This occurs in all cases, whether there is a byte
write or a full word is written.
able at the output at t
or t
, whichever is later.
KLQV
is the internal latency of the device. During this same
KHQV
t
KHQV
cycle, a new read address can be applied to the address
pins.
A write cycle can occur on the next cycle as long as
PROGRAMMABLE IMPEDANCE OPERATION
t
and t
are met. Read cycles may follow write
KHQZ
cycles immediately.
DVKH
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to V
through a precision
SS
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of the CK clock has its effect on
the output drivers immediately. SW low deselects the output
drivers immediately (on the same cycle). Output selecting via
a low on SS and high on SW at a rising CK clock has its
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, a 250 Ω resistor will give an out-
put impedance of 50 Ω.
Impedance updates occur continuously and the frequency
of the update is based on the subdivided CK clock. Note that
if the K clock stops, so does the impedance update.
The actual change in the impedance occurs in small incre-
ments and is monotonic. There are no significant distur-
bances that occur on the output because of this smooth
update method.
The impedance update is not related to any particular type
of cycle because the impedance is updated continuously and
is based on the CK clock. Updates occur regardless of
whether the device is performing a read, write, or a deselect
cycle and does not depend on the state of G.
At power up or recovery from sleep mode, the output
impedance defaults to approximately 50 Ω. It will take 4,000
to 16,000 cycles for the impedance to be completely updated
if the programmed impedance is much higher or lower than
50 Ω.
effect on the output drivers at t
. Output drive is also
KLQX
controlled directly by output enable (G). G is an asynchro-
nous input. No clock edges are required to enable or disable
the output with G.
Output data will be valid at t
, t , or t
GLQV KHQV KLQV,
which is even later. Outputs will begin driving at t
Outputs will hold previous data until t
t
.
KLQX1
, or
or t
KLQX
in the case of a write following a read.
GHQX
KHQZ
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing
parameters described for synchronous write input (SW)
apply to each of the byte write enable inputs (SBa, SBb,
etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
The output buffers can also be programmed in a minimum
impedance configuration by connecting ZQ to V
.
DD
(V ). Reads of all bytes proceed normally and write cycles,
SS
POWER UP AND INITIALIZATION
activated via a low on SW and the rising edge of CK, write
the entire RAM I/O width. This way the designer is spared
having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable
inputs in conjunction with the synchronous write input (SW).
It is important to note that writing any one byte will inhibit a
read of all bytes at the current address. The RAM can not
simultaneously read one byte and write another at the same
address. A write cycle initiated with none of the byte write
enable inputs active, is neither a read or a write. No write will
The following supply voltage application sequence is
recommended: V , V , then V . Please note, per
SS DD
DDQ
DDQ
+ 0.5 V, whatever the instantaneous value of V
the Absolute Maximum Ratings table, V
is not to exceed
V
.
DD
DD
Once supplies have reached specification levels, a minimum
dwell of 1.0 ms with CK clock inputs cycling is required
before beginning normal operations. At power up the output
impedance will be set at approximately 50 Ω as stated
above.
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
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SLEEP MODE
No Read/Write Allowed
During the period of time just prior to sleep and during
This device is equipped with an optional sleep or low
power mode. The sleep mode pin is asynchronous and
active high. During normal operation, the ZZ pin is pulled low.
When ZZ is pulled high, the chip will enter sleep mode where
the device will meet the lowest possible power conditions.
The Sleep Mode Timing diagram shows the following modes
of operation: Normal Operation, No Read/Write Allowed, and
Sleep Mode.
recovery from sleep, the assertion of any write or read signal
is not allowed. If a write or read operation occurs during
these periods, the memory array may be corrupted. Validity
of data out from the RAM can not be guaranteed immediately
after ZZ is asserted (prior to being in sleep). During sleep
mode recovery, the output impedance must be given
additional time above and beyond t
desired impedance (see explanation in Output Impedance
Circuitry paragraph).
in order to match
ZZR
Sleep Mode
Normal Operation
The RAM automatically deselects itself. The RAM discon-
nects its internal clock buffer. The external clock may con-
All inputs must meet setup and hold times prior to sleep
and t
nanoseconds after recovering from sleep. Clock
tinue to run without impacting the RAMs sleep current (I ).
ZZR
ZZ
(CK) must also meet cycle high and low times during these
periods. Two cycles prior to sleep, initiation of either a read or
write operation is not allowed.
All outputs will remain in a High–Z state while in sleep mode.
All inputs are allowed to toggle. The RAM will not be
selected, and perform any reads or writes.
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
1149.1 compliant TAPs. The TAP operates using conven-
tional JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS
logic level signaling.
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the RAMs critical speed path. Nevertheless,
the RAM supports the standard TAP controller architecture.
The TAP controller is the state machine that controls the TAP
operation and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfering with normal
operation of the device, TCK must be tied to V
to preclude
SS
mid–level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to V
nected.
through a 1 k resistor. TDO should be left uncon-
DD
TAP DC OPERATING CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
Parameter
Symbol
Min
2.0
–0.3
—
Max
V + 0.3
DD
Unit
V
Notes
Logic Input Logic High
Logic Input Logic Low
Logic Input Leakage Current
CMOS Output Logic Low
CMOS Output Logic High
TTL Output Logic Low
TTL Output Logic High
NOTES:
V
IH
1
V 1
IL
0.8
±5
V
I
µA
V
1
2
3
4
5
lkg
V 1
OL
—
0.2
—
V
1
2
V
– 0.2
V
OH
DD
V
—
0.4
—
V
OL
V
OH
2
2.4
V
1. 0 V ± V ± V
2. I 1 ≤ 100 µA @ V
OL OL
for all logic input pins.
= 0.2 V. Sampled, not 100% tested.
– 0.2 V. Sampled, not 100% tested.
= 0.4 V.
in DDQ
3.
I
1
≤ 100 µA @ V
OH
OL
DDQ
4. I 2 ≤ 8 mA @ V
5.
OL
≤ 8 mA @ V
I
2
= 2.4 V.
OH
OH
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
14
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Output Test Load . . . . . 50 Ω Parallel Terminated T–Line with 20 pF
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Receiver Input Capacitance
Test Load Termination Supply Voltage (V ) . . . . . . . . . . . . . . . 1.5 V
T
TAP CONTROLLER TIMING
Parameter
Symbol
Min
100
40
40
10
10
10
10
10
10
0
Max
—
—
—
—
—
—
—
—
—
—
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle Time
t
THTH
Clock High Time
Clock Low Time
TMS Setup
t
THTL
t
TLTH
t
MVTH
THMX
TMS Hold
t
TDI Valid to TCK High
TCK High to TDI Don’t Care
Capture Setup
t
DVTH
THDX
t
t
1
1
CS
Capture Hold
t
CH
TCK Low to TDO Unknown
TCK Low to TDO Valid
NOTE:
t
t
TLQX
—
TLOV
1. t + t
CS CH
defines the minimum pause in RAM I/O pad transitions to ensure accurate pad data capture.
AC TEST LOAD
1.5 V
50
Ω
DEVICE
UNDER
TEST
50
Ω
TAP CONTROLLER TIMING DIAGRAM
t
THTH
t
TLTH
TEST CLOCK
(TCK)
t
THTL
t
THMX
t
MVTH
TEST MODE SELECT
(TMS)
t
THDX
t
DVTH
TEST DATA IN
(TDI)
t
t
TLQV
TLQX
TEST DATA OUT
(TDO)
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
BOUNDARY SCAN REGISTER
TEST ACCESS PORT PINS
The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic 1) reserved for density
upgrade address pins. There are a total of 70 bits in the case
of the x36 device and 51 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAM I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state. Several TAP instructions can be used to
activate the boundary scan register.
The Bump/Bit Scan Order tables describe which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a
logic 1 input level.
TDI — TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-
mined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (see Figure 6). An undriven TDI pin will produce the
same result as a logic 1 input level.
IDENTIFICATION (ID) REGISTER
TDO — TEST DATA OUT (OUTPUT)
The ID register is a 32–bit register that is loaded with a
device and vendor specific 32–bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32–bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
Output that is active depending on the state of the TAP
state machine (see Figure 6). Output changes in response to
the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
TRST — TAP RESET
This device does not have a TRST pin. TRST is optional in
IEEE 1149.1. The test–logic–reset state is entered while
TMS is held high for five rising edges of TCK. Power–on
reset circuitry is included internally. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
ID Register Presence Indicator
Bit No.
Value
0
1
TEST ACCESS PORT REGISTERS
OVERVIEW
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1–1990)
Bit No. 11
Value
10
9
8
7
6
5
4
3
2
1
The various TAP registers are selected (one at a time) via
the sequences of 1s and 0s input to the TMS pin as the TCK
is strobed. Each of the TAP registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on the subsequent falling edge of TCK.
When a register is selected, it is “placed” between the TDI
and TDO pins.
0
0
0
0
0
0
0
1
1
1
0
Reserved For Future Use
Bit No.
Value
17
16
15
14
13
12
x
x
x
x
x
x
Device Width
Configuration
128K x 36
Bit No.
Value
Value
22
0
21
20
1
19
0
18
0
INSTRUCTION REGISTER
0
0
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are 3 bits long. The register can be loaded when it is placed
between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at
power up or whenever the controller is placed in test–logic–
reset state.
256K x 18
0
0
1
1
Device Depth
Configuration
Bit No.
Value
Value
27
0
26
0
25
1
24
0
23
1
128K x 36
256K x 18
0
0
1
1
0
Revision Number
BYPASS REGISTER
Bit No.
Value
31
30
29
28
The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
x
x
x
x
Figure 5. ID Register Bit Meanings
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
MCM69L736C Bump/Bit Scan Order
MCM69L818C Bump/Bit Scan Order
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
1
M2
SA
5R
4P
4T
6R
5T
7T
6P
7P
6N
7N
6M
6L
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
SA
NC
3B
2B
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
4D
4E
4G
4H
4M
3L
1
M2
SA
5R
6T
4P
6R
5T
7T
7P
6N
6L
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
SBb
ZQ
3G
4D
4E
4G
4H
4M
2K
1L
2
2
3
SA
SA
3
SA
SS
4
SA
SA
4
SA
NC
5
SA
SA
5
SA
NC
6
ZZ
SA
6
ZZ
SW
DQb
DQb
DQb
DQb
DQb
SA
7
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
SBa
CK
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
SBc
ZQ
7
DQa
DQa
DQa
DQa
SBa
CK
8
8
9
9
2M
1N
2P
3T
2R
4N
2T
3R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
7K
5L
4L
7L
CK
4K
4F
6H
7G
6F
7E
6D
6A
6C
5C
5A
6B
5B
3B
2B
3A
3C
2C
2A
1D
2E
2G
1H
SA
6K
7K
5L
G
SA
DQa
DQa
DQa
DQa
DQa
SA
SA
M1
4L
CK
4K
4F
5G
7H
6H
7G
6G
6F
7E
6E
7D
6D
6A
6C
5C
5A
6B
5B
SS
G
NC
SBb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
SA
NC
SW
SBd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
SA
SA
SA
1K
2K
1L
SA
NC
SA
2L
SA
2M
1N
2N
1P
2P
3T
2R
4N
3R
NC
SA
SA
SA
SA
SA
SA
DQb
DQb
DQb
DQb
SA
SA
NC
SA
35
SA
M1
NOTES:
1. TheNC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced
to logic one. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.
2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation.
3. ZQ, M1, and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1, and M2 must be driven to within 100 mV
of a V
or V
supply rail to ensure consistent results.
SS
DD
4. ZZ must remain at V during boundary scan to ensure consistent results.
IL
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
17
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
expected. RAM input signals must be stabilized for long
enough to meet the TAPs input data capture setup plus hold
time (t plus t ). The RAMs clock inputs need not be
TAP CONTROLLER INSTRUCTION SET
OVERVIEW
CS
CH
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
There are two classes of instructions defined in IEEE Stan-
dard 1149.1–1990, the standard (public) instructions and
device specific (private) instructions. Some public instruc-
tions are mandatory for IEEE 1149.1 compliance. Optional
public instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully imple-
mented. The TAP on this device may be used to monitor all
input and I/O pads, but can not be used to load address,
data, or control signals into the RAM or to preload the I/O
buffers. In other words, the device will not perform IEEE
1149.1 EXTEST, INTEST, or the preload portion of the
SAMPLE/PRELOAD command.
When the TAP controller is placed in capture–IR state, the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state,
the instruction register is placed between TDI and TDO. In
this state, the desired instruction is serially loaded through
the TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not
implemented in this device, moving the controller to the
update–DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not IEEE 1149.1
compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device. Therefore, this
device is not IEEE 1149.1 compliant. Nevertheless, this RAM
TAP does respond to an all 0s instruction, as follows. With
the EXTEST (000) instruction loaded in the instruction
register, the RAM responds just as it does in response to the
SAMPLE/PRELOAD instruction described above, except the
DQ pins are forced to High–Z any time the instruction is
loaded.
IDCODE
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at power up and any time the controller
is placed in the test–logic–reset state.
The BYPASS instruction is loaded in the instruction regis-
ter when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE–Z
SAMPLE/PRELOAD
If the SAMPLE–Z instruction is loaded in the instruction
register, all DQ pins are forced to an inactive drive state
(High–Z) and the boundary scan register is connected
between TDI and TDO when the TAP controller is moved to
the shift–DR state.
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the instruction register, moving the TAP controller
into the capture–DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK), it is
possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e., in a metast-
able state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results can not be
DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP
Do not use these instructions; they are reserved for future
use.
MCM69L736C•MCM69L818C
MOTOROLA FAST SRAM
18
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
EXTEST
Code*
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins to High–Z state. NOT IEEE 1149.1 COMPLIANT.
IDCODE
001**
100
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1
COMPLIANT.
BYPASS
111
010
Places bypass register between TDI and TDO. Does not affect RAM operation.
SAMPLE–Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins to High–Z state.
*Instruction codes expressed in binary; MSB on left, LSB on right.
**Default instruction automatically loaded at power up and in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
NO OP
Code*
Description
011
Do not use these instructions; they are reserved for future use.
NO OP
NO OP
101
110
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
TEST–LOGIC
RESET
1
0
1
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
1
0
0
0
1
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–IR
1
SHIFT–IR
1
0
0
1
1
EXIT1–DR
0
EXIT1–IR
0
PAUSE–DR
1
PAUSE–IR
1
0
0
0
0
EXIT2–DR
1
EXIT2–IR
1
UPDATE–DR
UPDATE–IR
1 0
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 6. TAP Controller State Diagram
MCM69L736C•MCM69L818C
19
MOTOROLA FAST SRAM
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007
ORDERING INFORMATION
(Order by Full Part Number)
69L736C
MCM
69L818C XX
X
X
Motorola Memory Prefix
Part Number
R = Tape and Reel, Blank = Tray
Speed (5.5 = 5.5 ns, 6.5 = 6.5 ns,
7.5 = 7.5 ns, 8.5 = 8.5 ns)
Package (ZP = PBGA)
Full Part Numbers —MCM69L736CZP5.5
MCM69L818CZP5.5
MCM69L736CZP6.5
MCM69L818CZP6.5
MCM69L736CZP7.5
MCM69L818CZP7.5
MCM69L736CZP8.5
MCM69L818CZP8.5
MCM69L736CZP5.5R
MCM69L818CZP5.5R
MCM69L736CZP6.5R MCM69L736CZP7.5R MCM69L736CZP8.5R
MCM69L818CZP6.5R MCM69L818CZP7.5R MCM69L818CZP8.5R
PACKAGE DIMENSIONS
ZP PACKAGE
7 X 17 BUMP PBGA
CASE 999–02
0.20
4X
119X
b
B
M
0.3
A
A
B C
E
C
M
0.15
7
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
D
D1
D2
K
L
M
N
P
R
T
16X e
MILLIMETERS
U
DIM
A
A1
A2
A3
D
D1
D2
E
E1
E2
b
MIN
–––
0.50
1.30
0.80
22.00 BSC
20.32 BSC
19.40 19.60
14.00 BSC
7.62 BSC
MAX
2.40
0.70
1.70
1.00
6X
e
E2
TOP VIEW
A3
E1
BOTTOM VIEW
0.25
A
A
0.35
11.90
0.60
1.27 BSC
12.10
0.90
0.20
A
A2
e
A
SEATING
PLANE
SIDE VIEW
A1
A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
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MCM69L736C/D
◊
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